Clock circuit and related method improving frequency hopping

Abstract

To provide a clock circuit and a method capable of improving frequency hopping.SOLUTION: A clock circuit 10 includes a frequency hopping circuit 100 and a frequency divider 140. The frequency hopping circuit 100 provides a first divisor number fra_out to the frequency divider 140. The frequency divider 140 performs frequency division according to a first divisor number fra_out. When hopping to a frequency or a spread spectrum range corresponding to an input number fra_in, if a convergence condition is not satisfied, the frequency hopping circuit 100 performs a stepping operation to update the first divisor number fra_out from a previous value fra_out[i-1], fra_out[i1-1] or fra_out[i2-1] to a current value fra_out[i], fra_out[i1] or fra_out[i2] which may not be equal the input number.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to clock circuits and related methods for improving frequency hopping, and more particularly to clock circuits and related methods involving a frequency divider and a frequency hopping circuit, where the divider may perform division according to a first divisor and the clock circuit may provide a clock according to the result of the division performed by the divider; when the clock circuit is requested to hop the frequency of the clock from a first frequency (or a first spread spectrum range) to a second frequency (or a second spread spectrum range), the clock circuit may stabilize the frequency of the clock at the second frequency (or the second spread spectrum range) after an interval; during the interval, the frequency hopping circuit may change the first divisor in steps, thereby allowing the clock circuit to achieve frequency hopping without the need to relock the timing (frequency and / or phase) of the clock. [Background technology]

[0002] A clock circuit can provide one or more periodic clocks and / or signals and is an essential building block of various types of integrated circuits. With respect to this disclosure, the Taiwan Intellectual Property Office has cited US11811317 as related art in its Notice of Examination Opinion numbered 11420232690 (March 4, 2025). Summary of the Invention

[0003] The clock circuit of the present disclosure may not only provide one or more clocks (e.g., ck1 in FIG. 1 ), but may also implement a frequency hopping function and / or a spread spectrum function for the clock, thus meeting the diverse needs that modern integrated circuits may require. For the clock, the spread spectrum function may vary the frequency of the clock in a spread spectrum range, for example, may vary the frequency of the clock periodically between an upper frequency and a lower frequency. Regarding the frequency hopping function for the clock, the clock circuit of the present disclosure may implement normal frequency hopping and spread spectrum frequency hopping for the clock. For a clock, normal frequency hopping (e.g., FIG. 5) may cause the frequency of the clock (e.g., f_ck1 in FIG. 5) to hop from a first frequency (e.g., f1 in FIG. 5) to a second frequency (e.g., f2 in FIG. 5) when a spread spectrum function is not performed on the clock, and spread spectrum frequency hopping (e.g., FIG. 6) may cause the frequency of the clock (e.g., f_ck1 in FIG. 6) to hop from a first spread spectrum range (e.g., fR1 in FIG. 6) to a second spread spectrum range (e.g., fR2 in FIG. 6) when a spread spectrum function is performed on the clock.

[0004] It is an object of the present disclosure to provide a clock circuit (e.g., 10 in FIG. 1) that improves frequency hopping. The clock circuit may include a frequency divider (e.g., 140 in FIG. 1) and a frequency hopping circuit (e.g., 100 in FIG. 1). The frequency divider may perform frequency division according to a first divisor (e.g., fra_out in FIG. 1). The frequency hopping circuit may be coupled to the frequency divider and may provide the first divisor. When hopping to a frequency or spread spectrum range corresponding to an input number (e.g., fra_in in FIG. 1, 3a or 3b), if a convergence condition (e.g., in step 410 in FIG. 4) is not met, the frequency hopping circuit may perform a stepping operation (e.g., in step 412 in FIG. 4) to update the first divisor from a previous value (e.g., fra_out[i-1], fra_out[i1-1] or fra_out[i2-1] in FIG. 1, 3a or 3b) to a current value (e.g., fra_out[i], fra_out[i1] or fra_out[i2] in FIG. 1, 3a or 3b), which may not be equal to the input number.

[0005] In one embodiment (e.g., FIG. 4), when the convergence condition is met, the frequency hopping circuit may cause the first divisor to be equal to the input number (e.g., in step 414 in FIG. 4).

[0006] In one embodiment (e.g., FIG. 4 ), the frequency hopping circuit may further perform a calculation operation (e.g., in step 406) and a determination operation (e.g., in step 410) before performing the stepping operation, and may repeat the calculation operation and the determination operation after performing the stepping operation. When the frequency hopping circuit performs the calculation operation, the frequency hopping circuit may calculate a difference number (e.g., df1) between the input number and the first divisor. When the frequency hopping circuit performs the determination operation, the frequency hopping circuit may determine whether the convergence condition is satisfied. Whether the convergence condition is satisfied may be related to whether a historical trend in the sign of the difference number indicates a limit cycle during past iterations of the calculation operation.

[0007] In one embodiment (eg, FIG. 4), whether the convergence condition is met may relate to whether the absolute difference between the input number and the first divisor is less than a threshold.

[0008] In one embodiment, each of the first divisor and the threshold may be a non-integer value; the frequency hopping circuit may represent the first divisor and the threshold by two binary values ​​of the same number of bits; the least significant bit of the binary value representing the threshold may be equal to 1, and the remaining bits of the binary value representing the threshold may be equal to 0.

[0009] In one embodiment (e.g., FIGS. 1 and 4), the frequency hopping circuit may be further coupled to a hopping enable signal (e.g., fh_en in FIGS. 1 and 4); the frequency hopping circuit may perform a stepping operation when the hopping enable signal is equal to a predefined logic value (e.g., ca1 in FIG. 4) and the convergence condition is not satisfied.

[0010] In one embodiment (e.g., FIGS. 1 and 4), when the hopping enable signal is not equal to the predefined logic value, the frequency hopping circuit may cause the first divisor to be equal to the input number (e.g., in step 416 in FIG. 4).

[0011] In one embodiment (e.g., FIGS. 3a and 3b), when the frequency hopping circuit performs the stepping operation to update the first divisor from the previous value (e.g., fra_out[i1-1] or fra_out[i2-1] in FIG. 3a or 3b) to the current value (e.g., fra_out[i1] or fra_out[i2] in FIG. 3a or 3b), if the input number is less than the previous value (e.g., fra_out[i1-1] in FIG. 3a), the frequency hopping circuit If the input number is greater than the previous value (e.g., fra_out[i2-1] in FIG. 3b), the frequency hopping circuit may set the current value (e.g., fra_out[i1] in FIG. 3b) equal to the previous value (e.g., fra_out[i1-1] in FIG. 3a) minus a step value (e.g., rg_ms in FIG. 3a). The step value may be a predetermined positive value.

[0012] In one embodiment (e.g., FIGS. 1, 3a, 3b, and 4), the frequency hopping circuit may perform the stepping operation during one period (e.g., T1 in FIGS. 3a and 3b) of an internal clock (e.g., sdm_ck in FIGS. 1, 3a, and 3b). When the divider performs the division according to the first divisor, the divider may perform the division according to the sum of the first divisor and a second divisor (e.g., ramp2 in FIGS. 1, 2b, and 6). The second divisor may periodically vary between a lower limit value (e.g., vL0 in FIGS. 2b and 6) and an upper limit value (e.g., vH0 in FIGS. 2b and 6), and one period (e.g., Tss1 in FIG. 2b) during which the second divisor varies may be longer than the period (e.g., T1 in FIG. 2b) of the internal clock.

[0013] In one embodiment (e.g., FIG. 1), the clock circuit may further include a spread spectrum circuit (e.g., 110 in FIG. 1) and a summing circuit (e.g., 120 in FIG. 1). The summing circuit may be coupled between the spread spectrum circuit, the frequency hopping circuit, and the frequency divider. The spread spectrum circuit may provide the second divisor, and the summing circuit may calculate the sum of the first divisor and the second divisor.

[0014] In one embodiment (e.g., FIG. 1), the clock circuit may further include a sigma-delta modulator (e.g., 130 in FIG. 1) coupled between the frequency divider and the frequency hopping circuit. The sigma-delta modulator may perform sigma-delta modulation on the sum of the first divisor and the second divisor, thus generating a modulated divisor (e.g., sdm1 in FIG. 1). When the frequency divider performs the division according to the first divisor, the frequency divider may perform the division according to the modulated divisor.

[0015] In one embodiment (e.g., FIG. 1), the frequency hopping circuit may include a first multiplexer (e.g., m1), a second multiplexer (e.g., m2), and an internal control circuit (e.g., 103). The first multiplexer may include two input terminals, one output terminal, and one selection terminal coupled to a first node (e.g., n1), a sixth node (e.g., n6), a second node (e.g., n2), and a fifth node (e.g., n5), respectively. The second multiplexer may include two input terminals, one output terminal, and one selection terminal coupled to the first node, the second node, a third node (e.g., n3), and a fourth node (e.g., n4), respectively. The internal control circuit may include two input terminals and two output terminals coupled to the first node, a seventh node (e.g., n7), the fifth node, and the sixth node, respectively. The first node may be further coupled to the input number, and the fourth node may be further coupled to a hopping enable signal (e.g., fh_en). The internal control circuit may check whether the convergence condition is met and therefore provide a hopping ready signal (e.g., fh_rdy) at the fifth node. If the convergence condition is not met, the internal control circuit may further calculate an internal number (e.g., s1 in FIGS. 1 and 4) output to the sixth node. The first multiplexer may selectively couple (conduct or electrically connect) one of the first node and the sixth node to the second node according to the logic value of the hopping ready signal. The second multiplexer may selectively couple (conduct or electrically connect) one of the first node and the second node to the third node according to the logic value of the hopping enable signal. The frequency hopping circuit may provide the first divisor at the seventh node according to a signal at the third node.

[0016] In one embodiment (e.g., FIG. 1), the frequency hopping circuit may further include a flip-flop (e.g., 1062), which may include one input terminal, one output terminal, and one clock terminal coupled to the third node, the seventh node, and the internal clock (e.g., sdm_ck), respectively.

[0017] In one embodiment (e.g., FIG. 1 ), the frequency hopping circuit may further include a front multiplexer (e.g., m0) and a front flip-flop (e.g., 1061). The front multiplexer may include two input terminals, one output terminal, and one select terminal, respectively coupled to a source number (e.g., fra0), the first node, a front node (e.g., n0), and a synchronized indication signal (e.g., chg_sync). The front flip-flop may include one input terminal, one output terminal, and one clock terminal, respectively coupled to the front node, the first node, and the internal clock (e.g., sdm_ck). The front multiplexer may selectively couple (conduct or electrically connect) one of the source number and the first node to the front node according to the logic value of the synchronized indication signal.

[0018] In one embodiment (e.g., FIG. 1), the clock circuit may further include a facilitation circuit (e.g., 150). The facilitation circuit may be coupled to the frequency divider and may output a first clock (e.g., ck1) to the frequency divider. When the frequency divider performs the division, the frequency divider may perform the division on the first clock to generate a second clock (e.g., ck2).

[0019] In one embodiment (eg, FIG. 1), the facilitation circuit may further control the timing of the first clock according to the timing (frequency and / or phase) of the second clock.

[0020] In one embodiment (e.g., FIG. 1 ), the clock circuit may further include a detector (e.g., 152), a filter (e.g., 154), and an oscillator (e.g., 156). The detector may have two input terminals and one output terminal coupled to a reference clock (e.g., fref_ck), a second clock (e.g., ck2), and a first internal node (e.g., u1), respectively. The filter may have one input terminal and one output terminal coupled to the first internal node and a second internal node (e.g., u2), respectively. The oscillator may have one input terminal and one output terminal coupled to the second internal node and the divider, respectively. The detector may detect a timing difference between the reference clock and the second clock, and thus provide a first internal signal (e.g., su1) at the first internal node. The filter may perform signal processing on the first internal signal, and thus provide a second internal signal (e.g., su2) at the second internal node. The oscillator may generate a first clock according to the second internal signal, so that the timing of the first clock may be related to the signal value of the second internal signal.

[0021] An object of the present disclosure is to provide a clock circuit (e.g., 10 in FIG. 1) that can improve frequency hopping. The clock circuit may include a frequency divider (e.g., 140) and a frequency hopping circuit (e.g., 100). The frequency divider may perform frequency division according to a first divisor (e.g., fra_out). The frequency hopping circuit may be coupled to the frequency divider and may provide the first divisor. The clock circuit may provide a clock according to a result of the frequency division performed by the frequency divider. When the clock circuit is requested to hop the frequency of the clock from a first frequency to a second frequency (e.g., from fa1 to fa2 or from fa2 to fa3 in FIG. 7), the clock circuit may stabilize the frequency of the clock to the second frequency after a certain interval (e.g., Da1 or Da2 in FIG. 7). During the interval, the frequency hopping circuit may change the first divisor in steps, so that the frequency of the clock does not increase and then decrease during the interval; for example, the frequency of the clock may not suffer from frequency overshoot (e.g., 701 or 702 in FIG. 7) during the interval. When hopping from the first frequency to the second frequency (e.g., from fa1 to fa2, or from fa2 to fa3), if the second frequency (e.g., fa2) is greater (higher) than the first frequency (e.g., fa1), the frequency hopping circuit may not increase the frequency of the clock above the second frequency and then decrease it to the second frequency during the interval (e.g., Da1). When the second frequency (e.g., fa3) is less than (lower than) the first frequency (e.g., fa2), the frequency hopping circuit may not, during the interval (e.g., Da2), cause the frequency of the clock to decrease to the second frequency, then increase above the second frequency and then decrease again to the second frequency.

[0022] In one embodiment (e.g., FIG. 8), when the divider performs the division according to the first divisor, the divider may perform the division according to the sum of the first divisor and a second divisor (e.g., ramp2 in FIG. 1). The clock circuit may further include a spread spectrum circuit (e.g., 110 in FIG. 1) that can provide the second divisor (e.g., ramp2). When the spread spectrum circuit enables a spread spectrum function, the spread spectrum circuit may vary the second divisor between a lower limit value (e.g., vL0 in FIG. 2b) and an upper limit value (e.g., vH0 in FIG. 2b). When the spread spectrum circuit enables the spread spectrum function and a frequency hopping circuit causes the first divisor to equal a first value (e.g., vb1 in FIG. 8), the frequency of the clock may spread over a first spread spectrum range (e.g., fRb1 in FIG. 8). When the clock circuit is requested to hop the frequency of the clock from the first spread spectrum range to a second spread spectrum range (e.g., fRb2 in FIG. 8), the clock circuit may steadily spread the frequency of the clock across the second spread spectrum range after a second interval (e.g., Db1 in FIG. 8). During the second interval, the frequency hopping circuit may change the first divisor stepwise, and the spread spectrum circuit may continue to enable the spread spectrum function.

[0023] An object of the present disclosure is to provide a method (e.g., 400 in FIG. 4 ) applicable to a clock circuit (e.g., 10 in FIG. 4 ). The clock circuit may include a frequency divider (e.g., 140 in FIG. 1 ), which may perform frequency division according to a first divisor (e.g., fra_out in FIGS. 1 and 4 ), and the clock circuit may provide a clock according to a result of the frequency division performed by the frequency divider. The method may include the steps of: when hopping the clock to a frequency or spread spectrum range corresponding to an input number (e.g., fra_in), proceeding to a decision step (e.g., 410 in FIG. 4 ) for determining whether a convergence condition is met; if the convergence condition is not met, proceeding to a stepping step (e.g., 412 in FIG. 4 ); and if the convergence condition is met, proceeding to a settling step (e.g., 414 in FIG. 4 ). The stepping step may include updating the first divisor from a previous value (e.g., fra_out[i-1] in FIG. 1) to a current value (e.g., fra_out[i] in FIG. 1) that is not equal to the input number, and repeating the determining step. The settling step may include causing the first divisor to equal the input number.

[0024] In one embodiment (e.g., FIG. 1), the clock circuit may further include a boost circuit (e.g., 150 in FIG. 1), and the boost circuit and the divider may form a phase-locked loop (e.g., 170 in FIG. 1).

[0025] Numerous objects, features, and advantages of the present disclosure will become readily apparent from the following detailed description of the embodiments thereof when read in conjunction with the accompanying drawings, in which: The drawings employed herein are for illustrative purposes only and should not be considered limiting. [Brief explanation of the drawings]

[0026] The above objects and advantages of the present disclosure will become more readily apparent to those skilled in the art after reviewing the following detailed description and accompanying drawings.

[0027] [Figure 1] FIG. 1 illustrates a clock circuit according to an embodiment of the present disclosure, which may include a spread spectrum circuit and a frequency hopping circuit.

[0028] [Figure 2] Figure 2a shows an embodiment of a number of waveforms and timings when the spread spectrum circuit in Figure 1 does not enable the spread spectrum function, and Figure 2b shows an embodiment of a number of waveforms and timings when the spread spectrum circuit in Figure 1 enables the spread spectrum function.

[0029] [Figure 3a] 2 shows, by way of example, an embodiment of waveforms and timing of relevant signals and numbers when the frequency hopping circuit in FIG. 1 operates; [Figure 3b] 2 shows, by way of example, an embodiment of waveforms and timing of relevant signals and numbers when the frequency hopping circuit in FIG. 1 operates;

[0030] [Figure 4] 1 is a flowchart according to an embodiment of the present disclosure.

[0031] [Figure 5] 2 shows an example embodiment of waveforms and timing of relevant signals and numbers when the clock circuit in FIG. 1 performs normal frequency hopping.

[0032] [Figure 6] 2 shows an embodiment of waveforms and timing of relevant signals and numbers when the clock circuit in FIG. 1 performs spread spectrum frequency hopping, as an example. [Figure 7] 2 shows an example embodiment of waveforms and timing of relevant signals and numbers when the clock circuit in FIG. 1 performs normal frequency hopping. [Figure 8]2 shows an embodiment of waveforms and timing of relevant signals and numbers when the clock circuit in FIG. 1 performs spread spectrum frequency hopping, as an example. DETAILED DESCRIPTION OF THE INVENTION

[0033] FIG. 1 illustrates a clock circuit 10 according to one embodiment of the present disclosure; the clock circuit 10 may be a clock generator, a clock synthesizer, a local oscillator for providing a local carrier signal, or the like. For example, in one embodiment, the clock circuit 10 may provide one or more clocks for a processor (not shown), so that the processor may operate (e.g., execute program code and / or perform digital signal processing) according to the timing (frequency and / or phase) of the one or more clocks. In another embodiment, the clock circuit 10 may provide one or more clocks for a wired interface circuit (e.g., a physical layer circuit conforming to a particular wired communication protocol, not shown), so that the interface circuit may receive and / or transmit digital signals according to the timing of the one or more clocks. In yet another embodiment, the clock circuit 10 may provide one or more carrier signals for a wireless radio frequency transceiver (not shown), so that the radio frequency transceiver may transmit and / or receive wireless radio frequency signals in one or more bands corresponding to the one or more carrier signals, respectively.

[0034] As shown in FIG. 1, clock circuit 10 may include a frequency hopping circuit 100, a spread spectrum circuit 110, a summing circuit 120, a sigma-delta modulator 130, a frequency divider 140, a facilitation circuit 150, and a synchronization circuit 160.

[0035] In one embodiment of the present disclosure, the facilitation circuit 150 may include two input terminals and one output terminal coupled to the clock fref_ck and two nodes u3 and u4, respectively; as shown in FIG. 1 , according to one embodiment of the present disclosure, the facilitation circuit 150 may further include a detector 152, a filter 154, and an oscillator 156.

[0036] In clock circuit 10, frequency divider 140 may include two input terminals and one output terminal coupled to node u3, node a8, and node u4, respectively. Sigma-delta modulator 130 may include one input terminal and one output terminal coupled to node n8 and another node a7, respectively.

[0037] In clock circuit 10, synchronization circuit 160 may include three input terminals and one output terminal respectively coupled to signal chg_in, clock sdm_ck, signal fbk_rstb, and node a4; as shown in FIG. 1, according to one embodiment of the present disclosure, synchronization circuit 160 may further include three flip-flops 162, 164, and 166, and a logic gate g1.

[0038] In clock circuit 10, spread spectrum circuit 110 may include four input terminals and one output terminal respectively coupled to clock sdm_ck, signal fbk_rstb, another signal ssc_en, node a4, and another node a5. Summation circuit 120 may include four input terminals and one output terminal respectively coupled to clock sdm_ck, signal fbk_rstb, node n7, node a5, and node a7; as shown in FIG. 1 , according to one embodiment of the present disclosure, summation circuit 120 may further include adder 122 and flip-flop 124.

[0039] In the clock circuit 10, the frequency hopping circuit 100 may include five input terminals and one output terminal respectively coupled to the clock sdm_ck, the signal fbk_rstb, the source number fra0, the signal fh_en, the node a4 and the node n7; as shown in FIG. 1, according to one embodiment of the present disclosure, the frequency hopping circuit 100 may further include three multiplexers m0, m1 and m2, two flip-flops 1061 and 1062, and an internal control circuit 103.

[0040] In clock circuit 10, facilitation circuit 150 may output clock ck1 at node u3, sigma-delta modulator 130 may perform sigma-delta modulation on divisor ramp_out to generate another divisor sdm1, and divider 140 may perform division on clock ck1 according to divisor sdm1 to generate clock ck2, such that the frequency of clock ck2 may be substantially equal to the frequency of clock ck1 divided by divisor ramp_out. In one embodiment, divisor ramp_out may not be an integer, for example, divisor ramp_out may include an integer portion and a fractional portion (i.e., a non-integer portion).

[0041] In the facilitation circuit 150 of the clock circuit 10, the detector 152 may include two input terminals and one output terminal coupled to the clock fref_ck, the node u4, and the node u1, respectively; the filter 154 may include one input terminal and one output terminal coupled to the node u1 and another node u2, respectively; the oscillator 156 may include one input terminal and one output terminal coupled to the nodes u2 and u3, respectively. The detector 152 may detect a timing (frequency and / or phase) difference between the clocks fref_ck and ck2 and thus provide a signal su1 at the node u1; the filter 154 may perform a signal filtering process on the signal su1 and thus provide a signal su2 at the node u2; the oscillator 156 may generate the clock ck1 under the control of the signal su2, so that the timing of the clock ck1 may be related to the signal value of the signal su2.

[0042] In the clock circuit 10, the facilitation circuit 150 and the frequency divider 140 may form a phase-locked loop 170 and may control the timing (frequency and / or phase) of the clock ck1 according to the timings of the clocks fref_ck and ck2. The phase-locked loop 170 may lock the timings of the clocks ck1 and ck2 to be synchronized with the timing of the clock fref_ck; that is, when the phase-locked loop 170 achieves phase lock, the phase-locked loop 170 may maintain a predefined correlation between the timings of the clocks ck1, ck2, and fref_ck, for example, aligning the kth and (k+Nc2)th rising edges (or falling edges) of the clock ck1 with the jth and (j+Nc1)th rising edges (or falling edges) of the clock fref_ck, respectively, where the value Nc1 may be an integer greater than or equal to 1, the value Nc2 may be an integer greater than or equal to 1, and the values ​​Nc1 and Nc2 may be the same or different. The phase-locked loop 170 shown in FIG. 1 may be just one of various embodiments; in other embodiments not shown, the phase-locked loop 170 (and / or the facilitation circuit 150) may include other circuits, such as one or more additional dividers, detectors, and / or feedback circuits (not shown).

[0043] In one embodiment, the cooperation of the facilitation circuit 150 and the divider 140 may cause the frequency of the clock ck2 to be related to (e.g., substantially equal to) the frequency of the clock fref_ck, and the frequency of the clock ck1 to be related to (e.g., substantially equal to) the frequency of the clock fref_ck multiplied by the divisor ramp_out. In one embodiment, the clock fref_ck may be a reference clock, and the frequency of the clock fref_ck may be a constant.

[0044] In clock circuit 10, synchronization circuit 160 may provide signal chg_sync at node a4 according to signal chg_in under the trigger of clock sdm_ck. Under control of signal chg_sync (as well as clock sdm_ck and signal fbk_rstb), frequency hopping circuit 100 may provide divisor fra_out at node n7 according to source number fra0. Under control of signal ssc_en (as well as signals chg_sync, clock sdm_ck, and signal fbk_rstb), spread spectrum circuit 110 may provide divisor ramp2 at node a5. Under trigger of clock sdm_ck, summation circuit 120 may sum the two divisors fra_out and ramp2, thus providing divisor ramp_out.

[0045] In clock circuit 10, frequency hopping circuit 100 may control the value of divisor fra_out to implement a frequency hopping function for clock circuit 10. Spread spectrum circuit 110 may control the value of divisor ramp2 to implement a spread spectrum function for clock circuit 10. In clock circuit 10, whether signal ssc_en is logic 1 may reflect whether the spread spectrum function of spread spectrum circuit 110 should be enabled, and whether signal fh_en is logic 1 may reflect whether the small scale updates (described later) of the present disclosure should be enabled when frequency hopping circuit 100 implements the frequency hopping function. When spread spectrum circuit 110 enables the spread spectrum function, the frequency of clock ck1 may be spread over a spread spectrum range. When signal ssc_en is logic 0, the value switches of signal chg_in and source number fra0 may indicate that clock circuit 10 is requested to perform normal frequency hopping, so that the frequency of clock ck1 may hop from one frequency to another. When signal ssc_en is logic 1, the value switches of signal chg_in and source number fra0 may indicate that clock circuit 10 is requested to perform spread spectrum frequency hopping, so that the frequency of clock ck1 may hop from one spread spectrum range to another spread spectrum range.

[0046] In the synchronous circuit 160, the flip-flop 162 may include one input terminal (labeled with a "D"), one output terminal (labeled with a "Q"), one clock terminal, and one reset terminal (labeled with a "rst") coupled to the signal chg_in, the node a1, the clock sdm_ck, and the signal fbk_rstb, respectively; the flip-flop 164 may include one input terminal, one output terminal, one clock terminal, and one reset terminal coupled to the node a1, the node a2, the clock sdm_ck, and the signal fbk_rstb, respectively; the flip-flop 166 may include one input terminal, one output terminal, one clock terminal, and one reset terminal coupled to the node a2, another node a3, the clock sdm_ck, and the signal fbk_rstb, respectively. The logic gate g1 may include two input terminals and one output terminal coupled to the nodes a2, a3, and a4, respectively. In one embodiment, flip-flop 162 may sample signal chg_in at each significant edge of clock sdm_ck and output the sampling result to node a1; flip-flop 164 may sample the signal at node a1 at each significant edge of clock sdm_ck and output the sampling result to node a2; flip-flop 166 may sample the signal at node a2 at each significant edge of clock sdm_ck and output the sampling result to node a3. The significant edge of clock sdm_ck may be a rising edge of clock sdm_ck or a falling edge of clock sdm_ck. Logic gate g1 may perform a logical operation on the signals at nodes a2 and a3, thus forming signal chg_sync at node a4; in one embodiment, logic gate g1 may be an exclusive OR.If the logical value of signal chg_in does not switch (remains logical 0 or logical 1), synchronization circuit 160 may cause signal chg_sync to remain at logical 0; in response to a logical value switch of signal chg_in (e.g., from logical 0 to logical 1 or from logical 1 to logical 0), synchronization circuit 160 may form a logical 1 pulse in signal chg_sync, which may start on the corresponding significant edge of clock sdm_ck and may last for one period of clock sdm_ck.

[0047] In clock circuit 10, when signal ssc_en is logic 0, spread spectrum circuit 110 may cause divisor ramp2 to maintain a particular constant value v0 (which may be 0 or non-zero); FIG. 2a shows an embodiment of the waveform and timing of divisor ramp2 when signal ssc_en is logic 0. On the other hand, when signal ssc_en is logic 1, spread spectrum circuit 110 may cause divisor ramp2 to periodically vary between a lower limit value vL0 and an upper limit value vH0; FIG. 2b shows an embodiment of the waveform and timing of divisor ramp2 when signal ssc_en is logic 1, where a period Tss1 may represent one period over which divisor ramp2 varies. 2b, when signal ssc_en is logic 1, spread spectrum circuit 110 may increase (e.g., monotonically increase) divisor ramp2 from lower limit value vL0 to upper limit value vH0 during one such period Tss1, and then decrease (e.g., monotonically decrease) from upper limit value vH0 to lower limit value vL0. In one embodiment, when spread spectrum circuit 110 increases divisor ramp2 from lower limit value vL0 to upper limit value vH0, spread spectrum circuit 110 may increase divisor ramp2 by value dr1 in each period T1 of clock sdm_ck. 2b, in response to a rising edge of the clock sdm_ck at time tr[q1], the spread spectrum circuit 110 may update the divisor ramp2 from a previous value ramp2[q1-1] to a current value ramp2[q1], which may be equal to the value ramp2[q1-1] plus the value dr1. One period T1 of the clock sdm_ck later, in response to a successive rising edge of the clock sdm_ck at another time tr[q1+1] (tr[q1+1]=tr[q1]+T1), the spread spectrum circuit 110 may update the divisor ramp2 from the value ramp2[q1] to the value ramp2[q1+1], which may be equal to the value ramp2[q1] plus the value dr1.

[0048] On the other hand, if the spread spectrum circuit 110 decreases the divisor ramp2 from the upper limit value vH0 to the lower limit value vL0, the spread spectrum circuit 110 may decrease the divisor ramp2 by a value dr2 in each period T1 of the clock sdm_ck. For example, as shown in FIG. 2b, in response to a rising edge of the clock sdm_ck at time tr[q2], the spread spectrum circuit 110 may update the divisor ramp2 from a previous value ramp2[q2-1] to a current value ramp2[q2], which may be equal to the value ramp2[q2-1] minus the value dr2. In response to successive rising edges of clock sdm_ck at another time tr[q2+1] (tr[q2+1]=tr[q2]+T1) one period T1 of clock sdm_ck, spread spectrum circuit 110 may update divisor ramp2 from value ramp2[q2] to value ramp2[q2+1], which may be equal to value ramp2[q2] minus value dr2. In one embodiment, values ​​dr1 and dr2 may be positive values; in one embodiment, values ​​dr1 and dr2 may be equal. In one embodiment, a period Tss1 during which divisor ramp2 fluctuates up and down may be longer than period T1 of clock sdm_ck; for example, period Tss1 may cover multiple periods T1.

[0049] 1, in summation circuit 120, adder 122 may include two input terminals and one output terminal coupled to node a5, node n7, and another node a6, respectively; flip-flop 124 may include one input terminal, one output terminal, one clock terminal, and one reset terminal coupled to node a6, node a7, clock sdm_ck, and signal fbk_rstb, respectively. Adder 122 may calculate the sum of divisor fra_out and ramp2 and output the summation result at node a6; flip-flop 124 may sample the signal at node a6 at each significant edge of clock sdm_ck, thus forming divisor ramp_out at node a7.

[0050] As shown in FIG. 1, in the frequency hopping circuit 100, multiplexer m0 may include one select terminal, two input terminals, and one output terminal coupled to node a4, source number fra0, and two other nodes n1 and n2, respectively. Flip-flop 1061 may include one clock terminal, one reset terminal, one input terminal, and one output terminal coupled to clock sdm_ck, signal fbk_rstb, node n0, and node n1, respectively. Multiplexer m1 may include two input terminals, one output terminal, and one select terminal coupled to node n1 and three other nodes n6, n2, and n5, respectively. Multiplexer m2 may include one select terminal, two input terminals, and one output terminal coupled to signal fh_en, node n1, node n2, and another node n3, respectively. Flip-flop 1062 may include one clock terminal, one reset terminal, one input terminal, and one output terminal coupled to clock sdm_ck, signal fbk_rstb, node n3, and node n7, respectively. Internal control circuit 103 may include two input terminals and two output terminals coupled to nodes n1, n7, n5, and n6, respectively.

[0051] In frequency hopping circuit 100, multiplexer m0 may selectively couple (conduct or electrically connect) one of source number fra0 and node n1 to node n0 according to the logic value at node a4. In one embodiment, when signal chg_sync at node a4 is logic 1, multiplexer m0 may couple source number fra0 to node n0; when signal chg_sync is logic 0, multiplexer m0 may couple node n1 to node n0. Flip-flop 1061 may sample the signal at node n0 at each significant edge of clock sdm_ck, thus forming input number fra_in at node n1. Flip-flop 1062 may sample the signal at node n3 at each significant edge of clock sdm_ck, thus forming divisor fra_out at node n7. When the divisor fra_out is fed back to the internal control circuit 103, the value of the divisor fra_out may be referred to as the previous value fra_out[i-1]. In the frequency hopping circuit 100, the internal control circuit 103 may check whether a convergence condition is met according to the input number fra_in and the divisor fra_out at nodes n1 and n7, respectively, and may therefore provide a signal fh_rdy at node n5; if the convergence condition is not met, the internal control circuit 103 may further calculate an internal number s1, which is output to node n6. In one embodiment, the internal control circuit 103 may cause the signal fh_rdy to be logic 0 if the convergence condition is not met, and may cause the signal fh_rdy to be logic 1 if the convergence condition is met. Whether the convergence condition is met may reflect whether the divisor fra_out is close to the input number fra_in.

[0052] In frequency hopping circuit 100, multiplexer m1 may selectively couple (conduct or electrically connect) one of nodes n1 and n6 to node n2 according to the logic value at node n5, thus providing internal number s2 at node n2. In one embodiment, when signal fh_rdy at node n5 is logic 1, multiplexer m1 may couple input number fra_in at node n1 to node n2; when signal fh_rdy is logic 0, multiplexer m1 may couple internal number s1 at node n6 to node n2. Multiplexer m2 may selectively couple (conduct or electrically connect) one of nodes n1 and n2 to node n3. In one embodiment, when signal fh_en is logic 1, multiplexer m2 may couple internal number s2 at node n2 to node n3; when signal fh_en is logic 0, multiplexer m2 may couple input number fra_in at node n1 to node n3. When flip-flop 1062 samples the signal at node n3, the signal value at node n3 may be referred to as the current value fra_out[i] of divisor fra_out.

[0053] In one embodiment of the present disclosure, when the internal control circuit 103 calculates the internal number s1, the internal control circuit 103 may subtract the previous value fra_out[i-1] from the value of the input number fra_in to obtain a difference number df1. If the value of the input number fra_in is greater than the previous value fra_out[i-1] of the divisor fra_out, and therefore the difference number df1 is positive, the internal circuit 103 may set the internal number s1 equal to the previous value fra_out[i-1] plus the step value rg_ms; on the other hand, if the value of the input number fra_in is less than the previous value fra_out[i-1] of the divisor fra_out, and therefore the difference number df1 is negative, the internal circuit 103 may set the internal number s1 equal to the previous value fra_out[i-1] minus the step value rg_ms. In one embodiment, the step value rg_ms may be a predetermined positive value, for example, a predefined positive constant.

[0054] In the clock circuit 10 shown in FIG. 1, the clocks ck1, ck2, and sdm_ck may be referred to as a first clock, a second clock, and an internal clock, respectively. The signals su1 and su2 may be referred to as an error signal and an oscillation control signal, respectively. The divisors sdm1, fra_out, ramp2, and ramp_out may be referred to as a modulated divisor, a first divisor, a second divisor, and a sum divisor, respectively. The signal chg_in may be referred to as an indication signal, the signal chg_sync may be referred to as a synchronized indication signal, the signal fh_rdy may be referred to as a hopping ready signal, the signal fh_en may be referred to as a hopping enable signal, and the signal ssc_en may be referred to as a spread spectrum enable signal. The combination including the synchronization circuit 160, the spread spectrum circuit 110, the frequency hopping circuit 100 and the summation circuit 120 may be referred to as a divisor module; under the control and trigger of the signals fh_en, ssc_en, chg_in, fbk_rstb and the clock sdm_ck, the divisor module may control the value of the divisor ramp_out according to the source number fra0.

[0055] 3a shows an embodiment of the timing and waveforms of relevant signals and numbers of the frequency hopping circuit 100 shown in FIG. 1, where a signal sign_df1 may represent the sign of the difference number df1 and another signal stp1 may represent the product of signal sign_df1 multiplied by a step value rg_ms. In the example shown in FIG. 3a, signals fh_en and ssc_en (FIG. 1) may be maintained at logic 1 and logic 0, respectively. In the frequency hopping circuit 100 shown in FIG. 1, in response to the value switch of signal chg_in and source number fra0, multiplexer m0 and flip-flop 1061 may switch the value of input number fra_in under the trigger of clock sdm_ck. In the example of Figure 3a, the value switch of input number fra_in from value v1 to smaller value v2 at time t1 may represent that clock circuit 10 is requested to perform normal frequency hopping at time t1, so that the frequency of clock ck1 may hop from a frequency corresponding to value v1 to a lower frequency corresponding to value v2. In one embodiment, time t1 may be a particular significant edge (e.g., a rising edge in the example of Figure 3a) of clock sdm_ck. As shown in Figure 3a, before time t1, the values ​​of input number fra_in and divisor fra_out may both be equal to value v1, thus satisfying the convergence condition, and internal control circuit 103 may cause signal fh_rdy to become logic 1.

[0056] At time t1, if input number fra_in switches from value v1 to v2, the divisor fra_out still maintains the previous value v1, in which case the convergence condition is not met and internal control circuit 103 may switch signal fh_rdy from logic 1 to logic 0. Because the value (v2-v1) is negative, signal sign_df1 may switch to negative 1 (-1), signal stp1 may switch to a negative step value (-rg_ms), and internal number s1 (FIG. 1) may switch to the value (v1-rg_ms) based on the calculations of internal control circuit 103. Because signals fh_rdy and fh_en are logic 0 and logic 1, respectively, multiplexers m1 and m2 may couple internal number s1 at node n6 to node n3, and flip-flop 1062 may update divisor fra_out from the previous value v1 to the current value (v1-rg_ms) at another time (t1+T1) one period T1 later than time t1.

[0057] In response to the divisor fra_out being updated to the value (v1-rg_ms) at time (t1+T1), the internal control circuit 103 may cause the difference number df1 to switch to the value (v2-v1+rg_ms). Assuming that the difference number df1 is still negative and the convergence condition is still not satisfied, the internal control circuit 103 may cause the signal fh_rdy to remain at logic 0, the signal sign_df1 may remain at negative 1, the signal stp1 may maintain a negative step value (-rg_ms), and the internal number s1 may be updated to the value (v1-2*rg_ms). Because signals fh_rdy and fh_en are logic 0 and logic 1, respectively, multiplexers m1 and m2 may couple the updated internal number s1 to node n3, and flip-flop 1062 may update divisor fra_out from the previous value (v1-rg_ms) to the current value (v1-2*rg_ms) at another time (t1+2*T1).

[0058] That is, in response to the input number fra_in switching from value v1 to a lower value v2 at time t1 as signal fh_en remains logic 1, frequency hopping circuit 100 may incrementally change (decrease) the value of divisor fra_out in small steps (by small steps) at each period T1 of clock sdm_ck until a convergence condition is met. After multiple periods T1, in response to frequency hopping circuit 100 updating divisor fra_out to value (v1-N1*rg_ms) at time (t11-T1), where value N1 is an integer, if the convergence condition is met, internal control circuit 103 may switch signal fh_rdy from logic 0 to logic 1, multiplexers m1 and m2 may couple input number fra_in at node n1 to node n3, and flip-flop 1062 may cause the value of divisor fra_out to be equal to value v2 of input number fra_in at later time t11. In one embodiment, time t11 may be a significant edge of clock sdm_ck. In response to the divisor fra_out being updated to value v2 at time t11, signal sign_df1 may switch from negative 1 to 0 and signal stp1 may switch from a negative step value (-rg_ms) to 0 because the input number fra_in and the divisor fra_out are both equal to value v2.

[0059] 3a, it can be seen that, in response to the input number fra_in switching from value v1 to value v2 at time t1, the frequency hopping circuit 100 may update the divisor fra_out stepwise in small scales (update the divisor fra_out by small scale steps) as the signal fh_en remains at logic 1, thereby postponing setting the divisor fra_out to value v2 until time t11. As shown in FIG. 3a, the interval D1 between times t1 and t11 may be referred to as a small-scale update interval, and the time length of the interval D1 may be related to (e.g., positively correlated with or approximate to) the ratio (|v1-v2| / rg_ms). The operation of the frequency hopping circuit 100 during the interval D1 may be referred to as a small-scale update; by holding the signal fh_en to remain at logic 1, the frequency hopping circuit 100 may enable the small-scale update to gradually change the value of the divisor fra_out in response to the value switch of the input number fra_in. The small-scale updates of the frequency hopping circuit 100 of the present disclosure may effectively improve frequency hopping, and various technical advantages of the present disclosure will be described later (eg, by referring to FIGS. 7 and 8).

[0060] 3a, if the convergence condition is not satisfied, at time t[i1] between time t1 and time t11, the internal control circuit 103 in the frequency hopping circuit 100 may perform a stepping operation to update the divisor fra_out from the previous value fra_out[i1-1] at the previous time t[i1-1] to the current value fra_out[i1]. Time t[i1] may be one period T1 later than time t[i1-1] (i.e., t[i1] = t[i1-1] + T1), and the current value fra_out[i1] may be between the previous value fra_out[i1-1] and the value v2 of the input number fra_in, but may not be equal to the previous value fra_out[i1-1] or the value v2. For example, the current value fra_out[i1] may be equal to the previous value fra_out[i1-1] minus the step value rg_ms.

[0061] Similarly, at another time point t[i1+1] after time point t[i1], the frequency hopping circuit 100 may update the divisor fra_out from the previous value fra_out[i1] at the previous time point t[i1] to the current value fra_out[i1+1]. Time point t[i1+1] may be one period T1 later than time point t[i1] (i.e., t[i1+1] = t[i1] + T1), and the current value fra_out[i1+1] may be between the value v2 of the input number fra_in and the previous value fra_out[i1], but may not be equal to the previous value fra_out[i1] or the value v2. For example, the current value fra_out[i1+1] may be equal to the previous value fra_out[i1] minus the step value rg_ms.

[0062] In the example of FIG. 3a, input number fra_in may switch from value v2 to a higher (larger) value v3 at time t2 after time t11, and the value switch of input number fra_in at time t2 may represent a request that clock circuit 10 perform normal frequency hopping at time t2, so that the frequency of clock ck1 may hop from a frequency corresponding to value v2 to a higher frequency corresponding to value v3. In one embodiment, time t2 may be a significant edge of clock sdm_ck. Following the example of FIG. 3a, FIG. 3b shows an embodiment of waveforms and timing of relevant signals and numbers after time t2; in the example of FIG. 3b, signals fh_en and ssc_en may continue to maintain logic 1 and logic 0, respectively. As shown in FIG. 3b, between times t11 and t2, the input number fra_in and the divisor fra_out may both be equal to the value v2, so the difference number df1, the signal sign_df1 and the signal stp1 may be 0, the internal number s1 may be equal to the value v2, and the signal fh_rdy may be logic 1.

[0063] At time t2, when the input number fra_in switches from value v2 to v3, the difference number df1 may switch to the value (v3-v2) because the divisor fra_out still maintains the previous value v2; therefore, the convergence condition may not be met, and the internal control circuit 103 may switch the signal fh_rdy from logic 1 to logic 0. Because the value (v3-v2) is positive, the signal sign_df1 may switch to positive 1 (+1), the signal sign_df1 may switch to the step value rg_ms, and the internal number s1 may switch to the value (v2+rg_ms) based on the calculation of the internal control circuit 103. Because signals fh_rdy and fh_en are logic 0 and logic 1, respectively, multiplexers m1 and m2 may couple internal number s1 at node n6 to node n3, and flip-flop 1062 may update divisor fra_out from the previous value v2 to the current value (v2+rg_ms) at a time (t2+T1) that is one such period T1 after time t2.

[0064] In response to the divisor fra_out being updated to the value (v2+rg_ms) at time (t2+T1), the difference number df1 may switch to the value (v3-v2-rg_ms). Provided that the convergence condition is still not met, the internal control circuit 103 may cause the signal fh_rdy to remain at logic 0, the signal sign_df1 may remain at positive 1, the signal stp1 may maintain the step value rg_ms, and the internal number s1 may be updated by the internal control circuit 103 to the value (v2+2*rg_ms). Because signals fh_rdy and fh_en are logic 0 and logic 1, respectively, multiplexers m1 and m2 may couple the updated internal number s1 to node n3, and flip-flop 1062 may update divisor fra_out from the previous value (v2+rg_ms) to the current value (v2+2*rg_ms) at another time (t2+2*T1).

[0065] That is, in response to the input number fra_in switching from value v2 to a higher value v3 at time t2 as signal fh_en remains at logic 1, frequency hopping circuit 100 may change (increase) the value of divisor fra_out in small steps at each period T1 of clock sdm_ck until a convergence condition is met. After multiple periods T1, in response to frequency hopping circuit 100 updating divisor fra_out to value (v2+N2*rg_ms) at time (t22-T1), where value N2 is an integer, if the convergence condition is met, internal control circuit 103 may cause signal fh_rdy to switch from logic 0 to logic 1, multiplexers m1 and m2 may couple input number fra_in at node n1 to node n3, and flip-flop 1062 may cause the value of divisor fra_out to be equal to value v3 of input number fra_in at a later time t22. In one embodiment, time t22 may be a significant edge of clock sdm_ck. In response to the divisor fra_out being updated to value v3 at time t22, signal sign_df1 may switch from positive 1 to 0 and signal stp1 may switch from step value rg_ms to 0 because input number fra_in and divisor fra_out are both equal to value v3.

[0066] 3b, it can be seen that in response to the input number fra_in switching from value v2 to value v3 at time t2 as the signal fh_en remains at logic 1, the frequency hopping circuit 100 may update the divisor fra_out stepwise in small increments, thereby postponing setting the divisor fra_out to value v3 until time t22. As shown in FIG. 3b, the interval D2 between time t2 and t22 may be referred to as another small-scale update interval, and the time length of the interval D2 may be related to (e.g., positively correlated with or approximate to) the ratio (|v2-v3| / rg_ms). As shown in FIG. 3b, at time t[i2] between time t2 and t22, if the convergence condition is not satisfied, the frequency hopping circuit 100 may update the divisor fra_out from the previous value fra_out[i2-1] at the previous time t[i2-1] to the current value fra_out[i2]. The time point t[i2] may be one period T1 later than the time point t[i2-1] (i.e., t[i2] = t[i2-1] + T1), and the current value fra_out[i2] may be between the previous value fra_out[i2-1] and the value v3 of the input number fra_in, but may not be equal to the previous value fra_out[i2-1] and the value v3. For example, the current value fra_out[i2] may be equal to the previous value fra_out[i2-1] plus the step value rg_ms.

[0067] Similarly, at another time point t[i2+1] after time point t[i2], the frequency hopping circuit 100 may update the divisor fra_out from the previous value fra_out[i2] at the previous time point t[i2] to the current value fra_out[i2+1]. Time point t[i2+1] may be one period T1 later than time point t[i2] (i.e., t[i2+1]=t[i2]+T1), and the current value fra_out[i2+1] may be between the previous value fra_out[i2] and the value v3 of the input number fra_in, but may not be equal to the previous value fra_out[i2] or the value v3. For example, the current value fra_out[i2+1] may be equal to the previous value fra_out[i2] plus the step value rg_ms.

[0068] In the example of FIG. 3b (and FIG. 3a), input number fra_in may switch from value v3 to a lower value v4 at time t3 after time t22, thereby indicating that clock circuit 10 is requested to perform normal frequency hopping at time t3, so that the frequency of clock ck1 may hop from the frequency corresponding to value v3 to the lower frequency corresponding to value v4. As signal fh_en remains logic 1, in response to input number fra_in switching from value v3 to v4 at time t3, frequency hopping circuit 100 may again perform a small-scale update of divisor fra_out to gradually change divisor fra_out, thereby postponing setting divisor fra_out to value v4 until time t33. The interval D3 between times t3 and t33 may be referred to as yet another small-scale update interval. The step change of the divisor fra_out performed by the frequency hopping circuit 100 between times t3 and t33 may be similar to the step change of the divisor fra_out performed by the frequency hopping circuit 100 between times t1 and t11 (Figure 3a) and will not be described any further for the sake of brevity.

[0069] 4 shows a flowchart 400 according to one embodiment of the present disclosure; flowchart 400 may be implemented by the frequency hopping circuit 100 in the clock circuit 10 shown in FIG. 1. The main steps of flowchart 400 may be described as follows:

[0070] Step 402: Flowchart 400 may begin. In one embodiment, flowchart 400 may begin after phase-locked loop 170 (FIG. 1) has achieved lock. For example, flowchart 400 may begin after phase-locked loop 170 has stabilized the interrelationship between the timing of clocks ck2 and fref_ck to steadily meet a predefined lock condition.

[0071] Step 404: If the logical value of the signal fh_en is equal to a predefined logical value ca1 (e.g., logical 1), the flowchart 400 may proceed to step 406; if the signal fh_en is not equal to the logical value ca1, the flowchart 400 may proceed to step 416.

[0072] Step 406: The internal control circuit 103 in the frequency hopping circuit 100 may calculate a difference number df1 (also shown in FIG. 1), i.e., the difference between the input number fra_in and the divisor fra_out. The flowchart may then proceed to step 408.

[0073] Step 408: The internal control circuit 103 in the frequency hopping circuit 100 may calculate an internal number s1 (also shown in FIG. 1 ). If the difference number df1 is positive, the internal control circuit 103 in the frequency hopping circuit 100 may make the internal number s1 equal to the divisor fra_out plus the step value rg_ms; if the difference number df1 is negative, the internal control circuit 103 in the frequency hopping circuit 100 may make the internal number s1 equal to the divisor fra_out minus the step value rg_ms; then, the flowchart 400 may proceed to step 410. In one embodiment, if the difference number df1 is equal to 0, the frequency hopping circuit 100 may make the internal number s1 equal to the divisor fra_out.

[0074] Step 410: The internal control circuit 103 in the frequency hopping circuit 100 may check whether a convergence condition is met. If the convergence condition is not met, the flowchart 400 may proceed to step 412; if the convergence condition is met, the flowchart 400 may proceed to step 414.

[0075] Step 412: The multiplexers m1, m2 and the flip-flop 1062 in the frequency hopping circuit 100 may make the divisor fra_out equal to the internal number s1, and the flowchart 400 may repeat step 406.

[0076] Step 414: Multiplexers m1, m2 and flip-flop 1062 in frequency hopping circuit 100 may make divisor fra_out equal to input number fra_in, and flowchart 400 may proceed to step 418. In flowchart 400, steps 406 and 408 may be referred to as a difference number calculation step and a current value calculation step, respectively, and steps 410, 412, and 414 may be referred to as a decision step, a stepping step, and a settling step, respectively; steps 406, 408, 410, 412, and 414 may form a small-scale update procedure 430.

[0077] Step 416: The multiplexer m2 and the flip-flop 1062 in the frequency hopping circuit may make the divisor fra_out equal to the input number fra_in, and the flowchart 400 may proceed to step 418.

[0078] Step 418: If there is a need to repeat step 404 and / or small-scale update procedure 430, flowchart 400 may repeat step 404; otherwise, flowchart 400 may proceed to step 420. In one embodiment, flowchart 400 may repeat step 404 when input number fra_in updates and the logic value of signal chg_in (FIG. 1) toggles. In one embodiment, a logic value switch of signal chg_in may be associated with a value switch of source number fra0. In response to the logic value switch of signal chg_in, synchronization circuit 160 may generate a logic 1 pulse in signal chg_sync, and multiplexer m0 and flip-flop 1061 in frequency hopping circuit 100 may update the value of input number fra_in to value switch source number fra0, for example, at time t1 or t2 in FIGS. 3a and 3b. When the flowchart 400 repeats steps 418 through 404 and the small scale update procedure 430, the frequency hopping circuit 100 may repeatedly cycle from step 412 through steps 406 and 408 over multiple times in multiple periods T1 of the clock sdm_ck, respectively, thereby gradually changing the divisor fra_out, for example, during interval D1 or D2 in FIG. 3a or 3b; eventually, as the flowchart 400 progresses from step 410 to step 414, the frequency hopping circuit 100 may make the divisor fra_out equal to the input number fra_in, for example, at time t11 or t12 in FIG. 3a or 3b.

[0079] In one embodiment of the present disclosure, whether the convergence condition is met in step 410 may be related to the number of times the historical trend of the sign of the difference number dfl indicates a limit cycle during past iterations of step 406. For example, whether the convergence condition is met may be whether the number of times the historical trend of the sign of the difference number dfl indicates a limit cycle during the iterations of step 406 is greater than a predefined convergence count. For example, when performing step 410, if the sign of the difference number dfl demonstrates an alternating “positive-negative-positive-negative” pattern indicating a limit cycle during the most recent M (an integer) iterations of step 406, and the count M is greater than a predefined convergence count, the internal control circuit 103 may determine that the convergence condition is met.

[0080] In another embodiment of the present disclosure, whether the convergence condition is met in step 410 may be related to (or may be) whether the absolute difference |df1| between the input number fra_in and the divisor fra_out (i.e., the absolute value of the difference number df1 calculated in step 406) is less than a threshold value ms1 (not shown). The threshold value ms1 may be greater than, equal to, or less than the step value rg_ms in step 408. In one embodiment, the divisor fra_out and the threshold value ms1 may each be a non-integer value, and the frequency hopping circuit 100 may represent the divisor fra_out and the threshold value ms1 by two binary values ​​of the same number of bits (e.g., 28 bits), where the binary value representing the threshold value ms1 may have the least significant bit equal to 1 and the remaining bits equal to 0.

[0081] Continuing with the example of FIGS. 3a and 3b, FIG. 5 illustrates an embodiment of waveforms and timing of relevant signals and numbers when clock circuit 10 in FIG. 1 performs normal frequency hopping; in the example of FIG. 5, signals fh_en and ssc_en (FIG. 1) may maintain logic 1 and logic 0, respectively. As shown in FIG. 5, because signal ssc_en maintains logic 0, spread spectrum circuit 110 may cause divisor ramp2 to maintain value v0. Furthermore, in response to input number fra_in switching from value v1 to smaller value v2 at time t1, a small-scale update of frequency hopping circuit 100 in clock circuit 10 may stepwise change divisor fra_out from value v1 to value v2 during interval D1 between time t1 and t11. Because the divisor ramp_out provided by the summing circuit 120 is the sum of the divisors fra_out and ramp2 provided by the frequency hopping circuit 100 and the spread spectrum circuit 110, respectively, the divisor ramp_out may change gradually from a value sv1 to a lower value sv2 during the interval D1, and the values ​​sv1 and sv2 may be equal to the values ​​(v1+v0) and (v2+v0), respectively. Because the divisor sdm1 by which the divider 140 performs the division is derived from the divisor ramp_out, the frequency f_ck1 of the clock ck1 may change smoothly and gradually from a frequency f1 to a lower frequency f2 during the interval D1 between times t1 and t11, and may steadily maintain the frequency f2 after time t11. The frequencies f1 and f2 may correspond to the values ​​sv1 and sv2, respectively, and may for example be equal to the frequencies (f_ref*sv1) and (f_ref*sv2), respectively, where the frequency f_ref (not shown) is the frequency of the clock fref_ck.

[0082] Similarly, in response to input number fra_in switching from value v2 to a higher value v3 at time t2, the small-scale update of frequency hopping circuit 100 may cause divisor fra_out to change stepwise from value v2 to value v3 during interval D2 between times t2 and t22. As a result, divisor ramp_out may change stepwise from value sv2 to a higher value sv3 during interval D2 between times t2 and t22, and frequency f_ck1 of clock ck1 may change smoothly and gradually from frequency f2 to a higher frequency f3 during interval D2 between times t2 and t22, steadily settling to frequency f3 after time t22. Value sv3 may be equal to value (v3+v0), and frequency f3 may correspond to value sv3, e.g., may be equal to frequency (f_ref*sv3).

[0083] Similarly, in response to input number fra_in switching from value v3 to lower value v4 at time t3, the small-scale update of frequency hopping circuit 100 may cause divisor fra_out to change stepwise from value v3 to value v4 during interval D3 between times t3 and t33. As a result, divisor ramp_out may change stepwise from value sv3 to lower value sv4 during interval D3 between times t3 and t33, and frequency f_ck1 of clock ck1 may change smoothly and gradually from frequency f3 to lower frequency f4 during interval D3 between times t3 and t33, steadily settling to frequency f4 after time t33. Value sv4 may be equal to value (v4+v0), and frequency f4 may correspond to value sv4, e.g., may be equal to frequency (f_ref*sv4).

[0084] As an example, Figure 6 shows an embodiment of waveforms and timing of relevant signals and numbers when clock circuit 10 performs spread-spectrum frequency hopping; in the example of Figure 6, signals fh_en and ssc_en (Figure 1) may both maintain a logic 1. As shown in Figure 6, because signal ssc_en maintains a logic 1, spread-spectrum circuit 110 in clock circuit 10 may periodically vary divisor ramp2 between a lower limit value vL0 and an upper limit value vH0. If input number fra_in switches from a value v6 to another value v7 at time t6, the value switch of input number fra_in may represent a request that clock circuit 10 hop the frequency of clock ck1 from a spread-spectrum range corresponding to value v6 to another spread-spectrum range corresponding to value v7.

[0085] 6 shows that in response to input number fra_in switching from value v6 to lower value v7 at time t6, frequency hopping circuit 100 in clock circuit 10 may enable a small-scale update because signal fh_en is logic 1; thus, divisor fra_out may change stepwise and may postpone equaling value v7 until another time t66. An interval D6 between times t6 and t66 may be referred to as a small-scale update interval, and the time length of interval D6 may be related to the ratio |v6-v7| / rg_ms. Since the divisor ramp_out provided by the summation circuit 120 is the sum of the divisors fra_out and ramp2 provided by the frequency hopping circuit 100 and the spectrum spread circuit 110, respectively, the divisor ramp_out may change gradually during the interval D6 between times t6 and t66 from a value range vR1 corresponding to a value v6 to a lower value range vR2 corresponding to a value v7, where the value range vR1 may be from a value svL1 to another value svH1, and the value range vR2 may be from a value svL2 to another value svH2, and the values ​​svL1, svH1, svL2 and svH2 may be equal to the values ​​(v6+vL0), (v6+vH0), (v7+vL0) and (v7+vH0), respectively. Since the divisor sdm1 by which the divider 140 performs division is derived from the divisor ramp_out, the frequency f_ck1 of the clock ck1 may smoothly and gradually change from the spread spectrum range fR1 to the lower spread spectrum range fR2 during the interval D6 between times t6 and t66, and may steadily settle to the spread spectrum range fR2 after time t66. As shown in FIG. 6, the spectrum spreading range fR1 may extend from a lower limit frequency fL1 to an upper limit frequency fH1, the spectrum spreading range fR2 may extend from a lower limit frequency fL2 to an upper limit frequency fH2, and the spectrum spreading ranges fR1 and fR2 may correspond to value ranges vR1 and vR2, respectively, and for example, the frequencies fL1, fH1, fL2 and fH2 may be equal to the frequencies (f_ref*svL1), (f_ref*svH1), (f_ref*svL2) and (f_ref*svH2), respectively.

[0086] As an example, Figure 7 illustrates the improvement provided by small scale updates of frequency hopping circuit 100 of the present disclosure when clock circuit 10 performs normal frequency hopping; in the example of Figure 7, signal ssc_en (Figure 1) may remain at logic 0. In Figure 7, curve f_ck1_a1 may represent the frequency of clock ck1 when small scale updates of the present disclosure are utilized during normal frequency hopping, and curve f_ck1_a0 may represent the frequency of clock ck1 when small scale updates of the present disclosure are not utilized during normal frequency hopping. When signal ssc_en remains logic 0, and signal fh_en (FIG. 1) remains logic 1, frequency hopping circuit 100 may enable small scale updates to be utilized by clock circuit 10 (i.e., flowchart 400 in FIG. 4 may proceed from step 404 to small scale update procedure 430); when signal fh_en remains logic 0, frequency hopping circuit 100 may not enable small scale updates and clock circuit 10 may not utilize small scale updates (i.e., flowchart 400 in FIG. 4 may proceed from step 404 to step 416). When signal fh_en is logic 0 and frequency hopping circuit 100 does not enable small-scale updates, multiplexer m2 and flip-flop 1062 (FIG. 1) in the frequency hopping circuit may cause divisor fra_out to approximately track input number fra_in; when the input number switches from a first value to another second value, divisor fra_out will also switch quickly from the first value to the second value and will not change gradually to postpone reaching the second value until one interval has elapsed.

[0087] 7, when input number fra_in is equal to value va1, phase-locked loop 170 (FIG. 1) may achieve lock and enter a locked status between two times t0 and ta0, and may then steadily maintain the frequency of clock ck1 to maintain frequency fa1. At a later time ta1, input number fra_in may switch from value va1 to a higher value va2, requesting clock circuit 10 to hop from frequency fa1 corresponding to value va1 to the higher frequency fa2 corresponding to value va2.

[0088] As the curve f_ck1_a1 shows, when the small-scale update of the present disclosure is utilized, the frequency hopping circuit 100 may gradually change the divisor fra_out by small-scale steps after time ta1, so that the divisor fra_out may postpone reaching the value va2 until time ta11; as a result, the frequency of the clock ck1 may smoothly and gradually change from frequency fa1 to frequency fa2 at time ta11 and may steadily maintain frequency fa2 after time ta11. As the curve f_ck1_a1 shows, during the interval Da1 from time ta1 to ta11, the divisor fra_out changes in small-scale steps, so the divisor ramp_out ( FIG. 1 ) may also change in small-scale steps, so that the phase-locked loop 170 may remain in a locked status and may not need to relock the timing of the clock ck1. As previously described (e.g., by reference to FIGS. 3a and 3b), when signal fh_en remains at logic 1, and thus frequency hopping circuit 100 enables small scale updates, frequency hopping circuit 100 may decrease or increase divisor fra_out by a step value rg_ms in each of the periods T1 during a small scale update interval (e.g., Da1). In one embodiment, the amount of the step value rg_ms may be related to the length of period T1 and / or the characteristics (e.g., response time and stability) of phase-locked loop 170, such that phase-locked loop 170 does not fall out of a locked status during the small scale update interval.

[0089] On the other hand, as shown by curve f_ck1_a0, if small-scale updates are not used, the value switch of input number fra_in at time ta1 causes the values ​​of divisors fra_out and ramp_out to switch rapidly, causing phase-locked loop 170 to exit the locked state and require relocking of the timing of clock ck1. During relocking, the frequency of clock ck1 rises from frequency fa1 to exceed frequency fa2, drops downward to compensate, and then relocks to frequency fa2 at time ta111. As shown in FIG. 7 , relocking between times ta1 and ta111 causes frequency overshoot 701 in curve f_ck1_a0. Compared to the smooth change of curve f_ck1_a1 during interval Da1, frequency overshoot 701 in curve f_ck1_a0 indicates that phase-locked loop 170 in clock circuit 10 must consume additional power (energy) to relock when hopping from frequency fa1 to frequency fa2.

[0090] At another time ta2, the input number fra_in may switch from value va2 to a lower value va3, requesting the clock circuit 10 to hop from frequency fa2 to the lower frequency fa3 corresponding to value va3. As shown by the curve f_ck1_a1, when the small-scale updates of the present disclosure are utilized, the divisor fra_out may change in small steps and may postpone reaching the value va3 until time ta22; as a result, the frequency of the clock ck1 may change smoothly and gradually from frequency fa2 to frequency fa3 at time ta22 and then steadily maintain frequency fa3. As shown by the curve f_ck1_a1, during the interval Da2 between times ta2 and ta22, the divisor fra_out changes in small steps, so the divisor ramp_out ( FIG. 1 ) may also change in small steps; therefore, the phase-locked loop 170 may not need to exit a locked status and may not need to relock the timing of the clock ck1. During the interval Da2, the frequency of the clock ck1 may be substantially maintained between frequencies fa2 and fa3, and may be substantially not lower than frequency fa3 and not higher than frequency fa2.

[0091] On the other hand, as shown by curve f_ck1_a0, if small-scale updates are not used, the value switch of input number fra_in at time ta2 will cause the values ​​of divisors fra_out and ramp_out to switch quickly, so phase-locked loop 170 will not need to relock the timing of clock ck1; during relocking, the frequency of clock ck1 will first decrease from frequency fa2, rise above frequency fa3, drop downward to correct, and then relock to frequency fa3 at time ta222. As shown in FIG. 7 , relocking between times ta2 and ta222 will cause frequency overshoot 702 in curve f_ck1_a0. Compared to the smooth change in curve f_ck1_a1 during interval Da2, frequency overshoot 702 in curve f_ck1_a0 indicates that phase-locked loop 170 in clock circuit 10 must consume additional power to relock when hopping from frequency fa2 to frequency fa3.

[0092] At another time ta3, input number fra_in may switch from value va3 to a higher value va4, requesting clock circuit 10 to hop from frequency fa3 to the higher frequency fa4 corresponding to value va4. As curve f_ck1_a1 shows, if the small-scale updates of the present disclosure are utilized, divisor fra_out may change in small-scale steps, postponing reaching value va4 until time ta33; as a result, the frequency of clock ck1 may change smoothly and gradually from frequency fa3 to frequency fa4 at time ta33 and then steadily maintain frequency fa4. As curve f_ck1_a1 shows, during the interval Da3 between times ta3 and ta33, because divisor fra_out changes in small-scale steps, divisor ramp_out ( FIG. 1 ) may also change in small-scale steps, and thus phase-locked loop 170 may not need to relock the timing of clock ck1. During the period Da3, the frequency of the clock ck1 may be substantially maintained between the frequencies fa3 and fa4, and may be substantially not lower than the frequency fa3 and not higher than the frequency fa4.

[0093] On the other hand, as shown by curve f_ck1_a0, if small-scale updates are not used, the value switch of input number fra_in at time ta3 will cause the values ​​of divisors fra_out and ramp_out to switch quickly, so phase-locked loop 170 will not need to relock the timing of clock ck1; during relocking, the frequency of clock ck1 will rise from frequency fa3 to exceed frequency fa4, then drop to compensate, before relocking to frequency fa4 at time ta333. As shown in FIG. 7 , relocking between times ta3 and ta333 will cause frequency overshoot 703 in curve f_ck1_a0. Compared to the smooth change in curve f_ck1_a1 during interval Da3, frequency overshoot 703 in curve f_ck1_a0 indicates that phase-locked loop 170 in clock circuit 10 must consume additional power to relock when hopping from frequency fa3 to frequency fa4.

[0094] As an example, FIG. 8 illustrates the improvement provided by small-scale updates of frequency hopping circuit 100 of the present disclosure when clock circuit 10 performs spread-spectrum frequency hopping. In FIG. 8, curve f_ck1_b1 may represent the frequency of clock ck1 when small-scale updates of the present disclosure are utilized during spread-spectrum frequency hopping, and curve f_ck1_b0 may represent the frequency of clock ck1 when small-scale updates of the present disclosure are not utilized during spread-spectrum frequency hopping. When signal fh_en (FIG. 1) maintains a logic 1, frequency hopping circuit 100 may enable small-scale updates to be utilized by clock circuit 10; when signal fh_en maintains a logic 0, frequency hopping circuit 100 may not enable small-scale updates, and clock circuit 10 may not utilize small-scale updates.

[0095] 8, when signal ssc_en is logic 0 and input number fra_in is equal to value vb1, phase-locked loop 170 in clock circuit 10 may achieve lock between two time points t0 and tb0, enter a locked state, and steadily maintain the frequency of clock ck1 to maintain frequency fbH1. At a later time point tb1, signal ssc_en may switch from logic 0 to logic 1, causing spread spectrum circuit 110 to enable (start) the spread spectrum function; thus, spread spectrum circuit 110 may periodically vary divisor ramp2, causing the frequency of clock ck1 to spread over a spread spectrum range fRb1 corresponding to value vb1. The spread spectrum range fRb1 may be from frequency fbL1 to frequency fbH1. At another later time tb1, the input number fra_in may switch from value vb1 to another value vb2, requesting the clock circuit 10 to hop from the spread spectrum range fRb1 to another spread spectrum range fRb2 corresponding to value vb2, which may be between two frequencies fbL2 and fbH2.

[0096] As shown by curve f_ck_b1, when the small-scale updates of the present disclosure are utilized, divisor fra_out may change in small-scale steps and may postpone reaching value vb2 until time tb11; as a result, the frequency of clock ck1 may change smoothly and gradually from spread-spectrum range fRb1 to spread-spectrum range fRb2 at time tb11 and may steadily spread across spread-spectrum range fRb2 after time tb11. Because divisor fra_out changes in small-scale steps during interval Db1 from time tb1 to tb11, divisor ramp_out ( FIG. 1 ) may also change in small-scale steps; therefore, phase-locked loop 170 may not need to fall out of a locked status and may not need to relock the timing of clock ck1. During the period Db1, the frequency of the clock ck1 may be substantially maintained between the highest (frequency fbH2 in the example of FIG. 8) and the lowest (frequency fbL1 in the example of FIG. 8) of the four frequencies fbL1, fbL2, fbH1, and fbH2.

[0097] On the other hand, as shown by curve f_ck1_b0, if small-scale updates are not utilized during spread-spectrum frequency hopping, signal ssc_en must switch from logic 1 to logic 0 at time tbs2 between times tbs1 and tb1 to disable the spread-spectrum function of spread-spectrum circuit 110 so that the spread-spectrum function does not prevent relocking during frequency hopping. If input number fra_in subsequently switches from value vb1 to value vb2 at time tb1, requesting clock circuit 10 to perform spread-spectrum frequency hopping, phase-locked loop 170 will relock the timing of clock ck1. During relocking, the frequency of clock ck1 will first increase, exceeding the upper frequency fbH2 of spread-spectrum range fRb2, then decrease to correct and lock onto frequency fbH2 at time tb111. After time tb111, signal ssc_en switches back from logic 0 to logic 1 to re-enable (start) the spread spectrum function of spread spectrum circuit 110, so that the frequency of clock ck1 can spread across spread spectrum range fRb2. As shown in FIG. 8, if small-scale updates are not utilized, relocking will cause a frequency overshoot 801 in curve f_ck1_b0 between time tb1 and tb111. Compared to the smooth transition of curve f_ck1_b1 during interval Db1, frequency overshoot 801 in curve f_ck1_b0 means that phase-locked loop 170 in clock circuit 10 must consume extra power to hop from spread spectrum range fRb1 to fRb2.

[0098] 8, it can be seen that when the small-scale updates of the present disclosure are not utilized when performing spread-spectrum frequency hopping, not only does relocking cause frequency overshoot, but additional control procedures of high complexity must also be implemented to disable and enable the spread-spectrum function before and after relocking, respectively. Conversely, when the small-scale updates of the present disclosure are utilized, relocking may no longer be necessary, and the spread-spectrum function may not need to be repeatedly disabled and enabled; even if the spread-spectrum circuit 110 continues to enable the spread-spectrum function without disabling it, the small-scale updates of the frequency hopping circuit 100 may successfully hop the frequency of clock ck1 from the spread-spectrum range fRb1 to fRb2. That is, when the small-scale updates of the present disclosure are utilized, the signal ssc_en may remain at logic 1 after time tbs1, and therefore the spread-spectrum circuit 110 may continue to enable the spread-spectrum function before, during, and after the interval Db1.

[0099] When signal fh_en remains at logic 1, thereby causing frequency hopping circuit 100 to enable small scale updates, frequency hopping circuit 100 may decrease or increase divisor fra_out by a step value rg_ms in each of the periods T1 during the small scale update interval (e.g., Db1). When signal ssc_en remains at logic 1, thereby causing spread spectrum circuit 110 to enable spread spectrum functionality, spread spectrum circuit 110 may increase or decrease divisor ramp2 by a value dr1 or dr2 (FIG. 2b) in each of the periods T1. In one embodiment, the amount of step value rg_ms may be related to the length of period T1, the amount of values ​​dr1 and dr2, and / or characteristics of phase-locked loop 170 (e.g., response time, stability, etc.) so that phase-locked loop 170 does not fall out of a locked status during the small scale update interval.

[0100] In one embodiment (not shown) of clock circuit 10 in FIG. 1 , the expediting circuit 150 and divider 140 may not need to form a phase-locked loop; divider 140 performs division on clock ck1 to generate clock ck2, and clock ck2 may not be fed back to the expediting circuit 150, and the expediting circuit 150 may not control the timing of clock ck1 according to the timing of clock ck2. For example, the expediting circuit 150 may be a clock generator for generating clock ck1, and the generated clock ck1 may have a given frequency; in conjunction with the division performed by divider 140, the frequency of clock ck2 may be equal to the given frequency divided by the divisor ramp_out. In such an embodiment, when spread spectrum circuit 110 enables a spread spectrum function, the spread spectrum circuit 110 may spread the frequency of clock ck2 over a spread spectrum range. When signal ssc_en is logic 0, the value switches of signal chg_in and source number fra0 may indicate that clock circuit 10 is requested to perform normal frequency hopping, so that the frequency of clock ck2 may hop from a first frequency to another second frequency; when signal fh_en remains logic 1, frequency hopping circuit 100 may enable small scale updates during frequency hopping, so that the frequency of clock ck2 may change smoothly and gradually from a first frequency to a second frequency during a small scale update interval, similar to curve f_ck1_a1 in FIG. 7. When ssc_en is logic 1, the value switch of signal chg_in and source number fra0 may indicate that the clock circuit 10 is requested to perform spread spectrum frequency hopping, so that the frequency of clock ck2 may hop from a first spread spectrum range to another second spread spectrum range; when signal fh_en remains logic 1, the frequency hopping circuit 100 may enable small scale updates during frequency hopping, so that the frequency of clock ck2 may change smoothly and gradually from the first spread spectrum range to the second spread spectrum range during the small scale update interval, similar to curve f_ck1_b1 in FIG. 8.

[0101] In summary, the present disclosure may provide a small-scale update mechanism for a clock circuit (e.g., 10 in FIG. 1 ). When an input number (e.g., fra_in) switches from a first input value (e.g., va1 or vb1 in FIG. 7 or FIG. 8 ) to a second input value (e.g., va2 or vb2 in FIG. 7 or FIG. 8 ), requesting the clock circuit to hop the frequency of a clock (e.g., ck1) from a first frequency (e.g., fa1 in FIG. 7 ) to a second frequency (e.g., fa2 in FIG. 7 ), or from a first spread-spectrum range (e.g., fRb1 in FIG. 8 ) to a second spread-spectrum range (e.g., fRb2 in FIG. 8 ), the small-scale update of the present disclosure may stepwise change a divisor associated with the clock (e.g., fra_out in FIG. 1 ) from the first input value to the second input value during an interval (e.g., Da1, Da2, or Da3 in FIG. 7 , or Db1 in FIG. 8 ). By utilizing the small-scale updates of the present disclosure during the interval, the clock circuit may not need to consume additional power and resources to relock the timing of the clock. Because the present disclosure may not need to relock during frequency hopping, the present disclosure may perform frequency hopping when the spread spectrum function remains enabled, thus avoiding complex controls to disable and enable the spread spectrum function before and after relocking, respectively.

[0102] While the present disclosure has been described with reference to several embodiments, it is to be understood that the present disclosure is not necessarily limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, and the scope of the claims is to be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims

1. 1. A clock circuit for improving frequency hopping, comprising: a frequency divider configured to perform frequency division according to a first divisor; and a frequency hopping circuit coupled to the frequency divider Equipped with a clock circuit configured to, when hopping to a frequency or spread spectrum range corresponding to an input number, if a convergence condition is not met, perform a stepping operation to update the first divisor from a previous value to a current value that is not equal to the input number.

2. 2. The clock circuit of claim 1, wherein the frequency hopping circuit is configured to cause the first divisor to be equal to the input number when the convergence condition is met.

3. the frequency hopping circuit is further configured to perform a calculation operation and a determination operation before performing the stepping operation, and to repeat the calculation operation and the determination operation after performing the stepping operation; When the frequency hopping circuitry is configured to perform the calculation operation, the frequency hopping circuitry is configured to calculate a difference number between the input number and the first divisor; When the frequency hopping circuit is configured to perform the decision operation, the frequency hopping circuit is configured to determine whether the convergence condition is satisfied; 2. The clock circuit of claim 1, wherein whether the convergence condition is met relates to whether a number of historical trends in the sign of the difference number indicate a limit cycle during the iteration of the calculation operation.

4. 2. The clock circuit of claim 1, wherein whether the convergence condition is met relates to whether an absolute difference between the input number and the first divisor is less than a threshold value.

5. each of the first divisor and the threshold value is a non-integer value; the frequency hopping circuit is configured to represent the first divisor and the threshold value by two binary values ​​of the same number of bits; 5. The clock circuit of claim 4, wherein the least significant bit of the binary value representing the threshold value is equal to 1, and the remaining bits of the binary value representing the threshold value are equal to 0.

6. the frequency hopping circuitry is further coupled to a hopping enable signal; 2. The clock circuit of claim 1, wherein the frequency hopping circuit is configured to perform a stepping operation when the hopping enable signal is equal to a predefined logic value and the convergence condition is not satisfied.

7. 7. The clock circuit of claim 6, wherein the frequency hopping circuit is configured to cause the first divisor to be equal to the input number when the hopping enable signal is not equal to the predefined logic value.

8. 2. The clock circuit of claim 1, wherein when the frequency hopping circuit is configured to perform the stepping operation, when the input number is less than the previous value, the frequency hopping circuit is configured to cause the current value to equal the previous value minus a step value; and when the input number is greater than the previous value, the frequency hopping circuit is configured to cause the current value to equal the previous value plus the step value.

9. the frequency hopping circuit is configured to perform the stepping operation during one period of an internal clock; When the frequency divider is configured to perform the division according to the first divisor, the frequency divider is configured to perform the division according to a sum of the first divisor and a second divisor; the second divisor periodically varies between a lower limit value and an upper limit value; 2. The clock circuit according to claim 1, wherein one period over which said second divisor fluctuates is longer than said one period of said internal clock.

10. the clock circuit further comprises a spread spectrum circuit and a summing circuit; the summing circuit is coupled between the spread spectrum circuit, the frequency hopping circuit, and the frequency divider; the spread spectrum circuitry configured to provide the second divisor; The clock circuit of claim 9 , wherein the summation circuit is configured to calculate the sum of the first divisor and the second divisor.

11. the clock circuit further comprising a sigma-delta modulator coupled between the frequency divider and the frequency hopping circuit; the sigma-delta modulator is configured to perform sigma-delta modulation on a sum of the first divisor and the second divisor, thus generating a modulated divisor; 11. A clock circuit according to claim 1, wherein when the divider is configured to perform the division according to the first divisor, the divider is configured to perform the division according to the modulated divisor.

12. the frequency hopping circuit includes a first multiplexer, a second multiplexer, and an internal control circuit; the first multiplexer includes two input terminals, one output terminal, and one selection terminal coupled to the first node, the sixth node, the second node, and the fifth node, respectively; the second multiplexer includes two input terminals, one output terminal, and one selection terminal coupled to the first node, the second node, a third node, and a fourth node, respectively; the internal control circuit includes two input terminals and two output terminals respectively coupled to the first node, the seventh node, the fifth node, and the sixth node; the first node is further coupled to the input number; the fourth node is further coupled to a hopping enable signal; the internal control circuit is configured to check whether the convergence condition is met and provide a hopping ready signal at the fifth node accordingly; If the convergence condition is not satisfied, the internal control circuit is further configured to calculate an internal number output to the sixth node; the first multiplexer is configured to selectively couple one of the first node and the sixth node to the second node according to a logic value of the hopping ready signal; the second multiplexer is configured to selectively couple one of the first node and the second node to the third node according to a logic value of the hopping enable signal; 11. A clock circuit according to claim 1, wherein the frequency hopping circuit is configured to provide the first divisor at the seventh node in accordance with a signal at the third node.

13. the frequency hopping circuit further comprises a flip-flop; 13. The clock circuit of claim 12, wherein the flip-flop includes one input terminal, one output terminal, and one clock terminal coupled to the third node, the seventh node, and an internal clock, respectively.

14. The frequency hopping circuit further comprises a front multiplexer and a front flip-flop; the front multiplexer includes two input terminals respectively coupled to a number of sources, the first node, a front node, and a synchronized indication signal, one output terminal, and one selection terminal; the front flip-flop includes one input terminal, one output terminal, and one clock terminal coupled to the front node, the first node, and an internal clock, respectively; 13. The clock circuit of claim 12, wherein the front multiplexer is configured to selectively couple one of the number of sources and the first node to the front node according to a logic value of the synchronized indication signal.

15. the clock circuit further comprising an expediting circuit; the facilitation circuit is coupled to the frequency divider and configured to output a first clock to the frequency divider; 11. The clock circuit of claim 1, wherein the divider is configured to generate a second clock by performing the division on the first clock.

16. 16. The clock circuit of claim 15, wherein the expediting circuit is further configured to control the timing of the first clock according to the timing of the second clock.

17. the clock circuit further comprising a detector, a filter, and an oscillator; the detector has two input terminals and one output terminal respectively coupled to a reference clock, a second clock, and a first internal node; the filter having one input terminal and one output terminal coupled to the first internal node and the second internal node, respectively; the oscillator having one input terminal and one output terminal respectively coupled to the second internal node and the frequency divider; the detector is configured to detect a timing difference between the reference clock and the second clock and provide a first internal signal at the first internal node accordingly; the filter is configured to perform signal processing on the first internal signal, thus providing a second internal signal at the second internal node; the oscillator is configured to generate a first clock according to the second internal signal; 11. The clock circuit of claim 1, wherein the divider is configured to generate a second clock by performing the division on the first clock.

18. 1. A clock circuit for improving frequency hopping, comprising: a frequency divider configured to perform frequency division according to a first divisor; and a frequency hopping circuit coupled to the frequency divider for providing the first divisor; Equipped with the clock circuit configured to provide a clock according to a result of the frequency division; when the clock circuit is requested to hop the frequency of the clock from a first frequency to a second frequency, the clock circuit is configured to stabilize the frequency of the clock to the second frequency after an interval; The frequency hopping circuit is configured to change the first divisor stepwise during the interval, so that the frequency of the clock does not increase and then decrease during the interval.

19. When the frequency divider is configured to perform the division according to the first divisor, the frequency divider is configured to perform the division according to a sum of the first divisor and a second divisor; the clock circuit further comprising a spread spectrum circuit for providing the second divisor; when the spread spectrum circuit is configured to enable a spread spectrum function, the spread spectrum circuit is configured to vary the second divisor between a lower limit value and an upper limit value; When the spread spectrum circuit is configured to enable the spread spectrum function, the frequency hopping circuit is configured to cause the first divisor to equal a first value, and the frequency of the clock is spread over a first spread spectrum range; when the clock circuit is requested to hop the frequency of the clock from the first spread spectrum range to a second spread spectrum range, the clock circuit is configured to steadily spread the frequency of the clock across the second spread spectrum range after a second interval; the frequency hopping circuit is configured to vary the first divisor stepwise during the second interval; 20. The clock circuit of claim 18, wherein the spread spectrum circuit is configured to continue enabling the spread spectrum function during the second interval.

20. A method applied to a clock circuit, comprising: the clock circuit comprises a frequency divider; the frequency divider configured to perform frequency division according to a first divisor; the clock circuit configured to provide a clock according to a result of the frequency division; The method comprises: proceeding to a decision step of determining whether a convergence condition is met when hopping the clock to a frequency or spread spectrum range corresponding to an input number; proceeding to a stepping stage if the convergence condition is not met; and proceeding to a settling phase if said convergence condition is met. Provided with: the stepping step includes updating the first divisor from a previous value to a current value not equal to the input number, and repeating the determining step; The method, wherein the settling step comprises the step of causing the first divisor to equal the input number.

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