Pixel and display device having the same

Abstract

To provide a pixel that can be applied to a high-resolution panel, and a display device having the same.SOLUTION: A pixel includes: a first transistor in which a first electrode is connected to a first node, a second electrode is connected to a second node, and a gate electrode is connected to a third node; a second transistor connected between a data line and the third node while the gate electrode is electrically connected to a first scanning line; a third transistor connected between a first power line through which a first drive power supply is supplied and the first node while the gate electrode is electrically connected to a light emitting control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power line through which a reference power supply is supplied; a third capacitor connected between the second node and the third node; and a light emitting element connected between the second node and a second power line through which a second drive power supply is supplied.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a pixel and a display device including the pixel. [Background technology]

[0002] With the development of information technology, the importance of display devices, which are a connection medium between users and information, is increasing, and accordingly, the use of display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs) is increasing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent No. 0911978 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-039435 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-097052

[0004] In recent years, head-mounted display devices (HMDs) have been developed. A head-mounted display device is a display device worn by a user in the form of glasses or a helmet, and realizes virtual reality (VR) or augmented reality (AR), in which a focus is formed at a close distance in front of the user's eyes. High-resolution panels are used in head-mounted display devices, which requires pixels suitable for high-resolution panels. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a pixel applicable to a high-resolution panel and a display device including the same. [Means for solving the problem]

[0006] A pixel according to one embodiment of the present invention includes a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a data line and the third node and having a gate electrode electrically connected to a first scan line; a third transistor connected between a first power supply line supplied with a first driving power source and the first node, and having a gate electrode electrically connected to a light emitting control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power supply line supplied with a reference power source; a third capacitor connected between the second node and the third node; and a light emitting element connected between the second node and a second power supply line supplied with a second driving power source.

[0007] In the embodiment, the pixel may further include a fourth transistor having a first electrode connected to the second node, a second electrode electrically connected to a third power line through which an initialization power source is supplied, and a gate electrode electrically connected to the second scan line.

[0008] In an embodiment, the voltage level of the reference power supply may be lower than the voltage level of the first driving power supply and higher than the voltage level of the initialization power supply.

[0009] In an embodiment, the voltage level of the reference power supply may be the same as the voltage level of the first driving power supply, and the reference power supply line may be the first power supply line.

[0010] In the embodiment, the light emitting element may be turned off when the voltage of the initialization power supply is supplied to the second node.

[0011] In an embodiment, each of the first to fourth transistors may be a MOSFET including a body electrode.

[0012] In the embodiment, the voltage of the first driving power supply may be supplied to the body electrodes of the first to fourth transistors.

[0013] In an embodiment, one horizontal period may include a first period, a second period, and a third period, and during the first period, the second transistor, the third transistor, and the fourth transistor may be set to a turned-on state, during the second period, the second transistor and the fourth transistor may be set to a turned-on state and the third transistor may be set to a turned-off state, and during the third period, the third transistor and the fourth transistor may be set to a turned-on state and the second transistor may be set to a turned-off state.

[0014] In the embodiment, a voltage of a data signal may be supplied to the data line during the first period to the third period.

[0015] In an embodiment, each of the first to third capacitors may be a MOM (Metal-Oxide-Metal) capacitor or a MIM (Metal-Insulator-Metal) capacitor.

[0016] In an embodiment, each of the first and second capacitors may be a MOM (Metal-Oxide-Metal) capacitor or a MIM (Metal-Insulator-Metal) capacitor, and the third capacitor may be a parasitic capacitor.

[0017] a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a jth data line of the data lines and the third node, and turned on when a first scan signal is supplied to a first scan line of the write scan lines; a third transistor connected between a first power line supplied with a voltage of a first driving power supply and the first node, and turned off when a light emission control signal is supplied to a kth (k is an integer greater than or equal to 0) light emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power line supplied with a reference power supply; a third capacitor connected between the second node and the third node; and a light emitting element connected between the second node and a second power line supplied with a second driving power supply.

[0018] In the embodiment, a pixel located in the ith pixel row and the jth pixel column may further include a fourth transistor having a first electrode connected to the second node and a second electrode electrically connected to a third power line through which an initialization power source is supplied, the fourth transistor being turned on when a second scan signal is supplied to a second scan line.

[0019] In an embodiment, the voltage level of the reference power supply may be lower than the voltage level of the first driving power supply and higher than the voltage level of the initialization power supply.

[0020] In an embodiment, the voltage level of the reference power supply may be the same as the voltage level of the first driving power supply, and the reference power supply line may be the first power supply line.

[0021] In the embodiment, each of the first to fourth transistors may be a MOSFET including a body electrode, and the voltage of the first driving power supply may be supplied to the body electrode. [Effects of the Invention]

[0022] According to a pixel and a display device including the pixel according to an embodiment of the present invention, the pixel can be implemented using a transistor (eg, MOSFET) suitable for high resolution.

[0023] However, the effects of the present invention are not limited to the above-mentioned effects, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a diagram showing a transistor according to an embodiment of the present invention; [Figure 2] 1 is a block diagram showing a display device according to an embodiment of the present invention; [Figure 3] 3 is a block diagram showing an embodiment of a scan driver, a data driver, and a power supply unit shown in FIG. 2.

[0023] FIG. [Figure 4] FIG. 3 is a circuit diagram showing an embodiment of the pixel shown in FIG. 2. [Figure 5] 5 is a waveform diagram showing an embodiment of a method for driving the pixel shown in FIG. 4. FIG. [Figure 6] FIG. 6 is a circuit diagram showing the operation process of the pixel according to the signals of FIG. 5. [Figure 7] FIG. 6 is a circuit diagram showing the operation process of the pixel according to the signals of FIG. 5. [Figure 8] FIG. 6 is a circuit diagram showing the operation process of the pixel according to the signals of FIG. 5. [Figure 9] FIG. 6 is a circuit diagram showing the operation process of the pixel according to the signals of FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0025] The present invention may be embodied in various different forms and is not limited to the embodiments described below, but may be embodied in various other forms, such as by way of example only, with the aid of the accompanying drawings, in which:

[0026] In the drawings, parts that are not relevant to the present invention will be described as necessary to clarify the description of the present invention, and the same or similar components will be designated by the same reference numerals throughout the specification.

[0027] Throughout the specification, when a moiety is referred to as being "connected" to another moiety, this includes not only "directly connected" but also "indirectly connected" via an intervening element. The terms used herein are intended to describe specific embodiments and are not intended to limit the present invention. Throughout the specification, when a moiety is referred to as "comprising" a certain element, this does not exclude other elements, but means that the other elements are further included, unless otherwise specified. The terms "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, and one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of the relevant elements.

[0028] Here, terms such as "first" and "second" are used to describe various components, but such components are not limited to such terms. These terms are used to distinguish one component from another. Therefore, a first component may be a second component within a scope that does not deviate from what is disclosed herein.

[0029] FIG. 1 is a diagram showing a transistor according to an embodiment of the present invention.

[0030] 1, a transistor 10 according to an embodiment of the present invention may include a first electrode 12, a second electrode 14, a gate electrode 16, and a body electrode 18. For example, the transistor 10 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). The transistor 10 (e.g., a MOSFET) including the body electrode 18 has a small mounting area and is suitable for realizing high-resolution pixels.

[0031] The transistor 10 may be formed on a silicon wafer. For example, a panel may be realized by stacking a transistor layer, a light-emitting layer, a cover layer, etc. on a silicon wafer. However, this is merely an example, and the transistor 10 may be formed on various currently known substrates (for example, a glass substrate).

[0032] The first electrode 12 of the transistor 10 may be set as a source electrode (or drain electrode), and the second electrode 14 may be set as a drain electrode (or source electrode). If the transistor 10 includes a body electrode 18, the threshold voltage of the transistor 10 may be changed by the body effect. The body effect means that the threshold voltage of the transistor 10 is changed by the voltage difference between the body electrode 18 and the first electrode 12 of the transistor.

[0033] According to one embodiment of the present invention, threshold voltage compensation may be possible while using transistor 10, including body electrode 18, as a drive transistor.

[0034] 2 is a diagram illustrating a display device according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating an embodiment of the scan driver, data driver, and power supply shown in FIG.

[0035] 2, a display device 100 according to an embodiment of the present invention may include a pixel unit 110 (or panel), a timing control unit 120, a scan driver 130, a data driver 140, a power supply 150, and an emission driver 160. The above components may be implemented as separate integrated circuits, or two or more of the above components may be integrated into a single integrated circuit. The scan driver 130 and / or the emission driver 160 may be formed in the pixel unit 110.

[0036] The pixel section 110 can include pixels PX connected to write scan lines SL11 to SL1n, initialization scan lines SL21 to SL2n, data lines DL1 to DLm, light emission control lines EL1 to ELo, and power supply lines PL1, PL2, and PL3 (where n, m, and o are integers greater than or equal to 0).

[0037] For example, a pixel PXij (see FIG. 4) located on the ith horizontal line (or pixel row) and the jth vertical line (or pixel column) may be connected to the ith write scan line SL1i, the ith initialization scan line SL2i, the kth light-emitting control line ELk, and the jth data line DLj (where i is an integer equal to or less than n, j is an integer equal to or less than m, and k is an integer equal to or less than o). Here, k may be equal to or less than i. For example, when each of the light-emitting control lines EL1-ELo is connected to pixels PX located on one horizontal line, k may be equal to i. For example, when each of the light-emitting control lines EL1-ELo is connected to pixels PX located on two or more horizontal lines, k may be less than i.

[0038] When a first scan signal is supplied to each of the write scan lines SL11 to SL1n, the pixels PX are selected in units of horizontal lines (for example, pixels PX connected to the same scan line can be grouped into one horizontal line (or pixel row)), and the pixels PX selected by the first scan signal can receive a data signal from the data line (any one of DL1 to DLm) connected to them. The pixels PX that receive the data signal can generate light of a predetermined brightness corresponding to the voltage of the data signal.

[0039] The timing control unit 120 can receive input data Din and a control signal CS from a host system via an interface. For example, the timing control unit 120 can receive the input data Din and the control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS can include various signals including a clock signal.

[0040] The timing control unit 120 generates a scan drive signal SCS, a data drive signal DCS, and an emission drive signal ECS based on the control signal CS. The scan drive signal SCS, the data drive signal DCS, and the emission drive signal ECS can be supplied to the scan driver 130, the data driver 140, and the emission driver 160, respectively.

[0041] The timing control unit 120 may realign the input data Din according to the specifications of the display device 100. Furthermore, the timing control unit 120 may correct the input data Din to generate output data Dout and provide the output data Dout to the data driver 140. In an embodiment, the timing control unit 120 may correct the input data Din according to optical measurement results measured during a process.

[0042] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required to drive the scan driver 130. The scan driver 130 may generate first and second scan signals by shifting the scan start signal in response to the clock signal.

[0043] For this purpose, the scan driver 130 may include a first scan driver 132 and a second scan driver 134, as shown in FIG.

[0044] The first scan driver 132 receives the first scan start signal FLM1 and generates the first scan signal by shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 sequentially supplies the first scan signal to the write scan lines SL11 to SL1n.

[0045] The second scan driver 134 receives the second scan start signal FLM2 and generates the second scan signal by shifting the second scan start signal FLM2 in response to a clock signal. The second scan driver 134 sequentially supplies the second scan signal to the initialization scan lines SL21 to SL2n. The first and second scan signals may be set to gate-on voltages to turn on transistors included in the pixels PX.

[0046] For example, a P-type transistor may be supplied with a first scan signal and a second scan signal at a low level, and an N-type transistor may be supplied with a first scan signal and a second scan signal at a high level. A transistor receiving the first scan signal or the second scan signal may be turned on in response to the first scan signal or the second scan signal. Hereinafter, supplying the first scan signal and the second scan signal may mean that a gate-on voltage is supplied to the write scan line SL1 and the initialization scan line SL2. Not supplying the first scan signal and the second scan signal may mean that a gate-off voltage is supplied to the write scan line SL1 and the initialization scan line SL2.

[0047] 3, the first scan driver 132 and the second scan driver 134 are illustrated as being connected to the write scan line SL1 and the initialization scan line SL2, respectively, but the embodiment of the present invention is not limited thereto. For example, the write scan line SL1 and the initialization scan line SL2 may be driven by a single scan driver.

[0048] The data driver 140 may receive output data Dout and a data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal required to drive the data driver 140.

[0049] The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the gray level of the output data Dout.

[0050] The data driver 140 may apply a constant voltage to the data lines DL1 to DLm based on the generated analog data signal. For example, referring to FIG. 5, the data driver 140 may supply a data signal voltage Vdata (see FIG. 5) to the data lines DL1 to DLm during one horizontal period 1H (see FIG. 5).

[0051] The power supply unit 150 may generate various power supplies necessary for driving the display device 100. For example, the power supply unit 150 may generate a first driving power supply VDD, a second driving power supply VSS, and an initialization power supply Vint.

[0052] The first driving power supply VDD may be a power supply that supplies a driving current to the pixel PX. The second driving power supply VSS may be a power supply that receives a driving current from the pixel PX. During a period in which the pixel PX is set to an emitting state, the first driving power supply VDD may be set to a voltage higher than the second driving power supply VSS.

[0053] The initialization power supply Vint may be a voltage for initializing the first electrode (or anode electrode) of the light emitting element LD (see FIG. 4) included in each pixel PX. The initialization power supply Vint may have a voltage value that turns off the light emitting element LD when supplied to the first electrode of the light emitting element LD.

[0054] The first driving power VDD generated by the power supply unit 150 may be supplied to the first power line PL1, the second driving power VSS to the second power line PL2, and the initialization power Vint to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be commonly connected to the pixel PX, but the embodiment of the present invention is not limited thereto.

[0055] In one embodiment of the present invention, the first power line PL1 is composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX from one another. In one embodiment of the present invention, the second power line PL2 is composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX from one another. In one embodiment of the present invention, the third power line PL3 is composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX from one another. In one embodiment of the present invention, a pixel PX may be connected to any one of the first power lines PL1, any one of the second power lines PL2, and any one of the third power lines PL3.

[0056] In one embodiment of the present invention, the power supply unit 150 may generate a reference power supply VRF (see FIG. 4) and supply the reference power supply VRF to a fourth power supply line PL4 (see FIG. 4). The pixels PX may be connected to the first to fourth power supply lines PL1 to PL4.

[0057] The light emitting driver 160 may receive a light emitting drive signal ECS from the timing controller 120. The light emitting drive signal ECS may include a light emitting start signal and a clock signal required for driving the light emitting driver 160. The light emitting driver 160 may generate a light emitting control signal by shifting the light emitting start signal EFLM according to the clock signal. The light emitting driver 160 may sequentially supply the light emitting control signals to the light emitting control lines EL1 to ELo. The light emitting control signal may be set to a gate-off voltage so that a transistor included in the pixel PX can be turned off.

[0058] For example, a high-level light-emitting control signal may be supplied to a P-type transistor, and a low-level light-emitting control signal may be supplied to an N-type transistor. A transistor that receives the light-emitting control signal may be turned off in response to the light-emitting control signal. Hereinafter, supplying a light-emitting control signal may mean that a gate-off voltage is supplied to the light-emitting control line EL. Not supplying a light-emitting control signal may mean that a gate-on voltage is supplied to the light-emitting control line EL.

[0059] Fig. 4 is a diagram showing an example of the pixel shown in Fig. 2. Fig. 4 shows a pixel located on the ith horizontal line and the jth vertical line.

[0060] 4, pixel PXij according to an embodiment of the present invention may be connected to corresponding signal lines SL1i, SL2i, ELk, and DLj. For example, pixel PXij may be connected to the ith write scan line SL1i, the ith initialization scan line SL2i, the kth light-emitting control line ELk, and the jth data line DLj. In an embodiment of the present invention, pixel PXij may further be connected to a first power line PL1, a second power line PL2, a third power line PL3, and a fourth power line PL4.

[0061] A pixel PXij according to an embodiment of the present invention can include a light emitting element LD and a pixel circuit PC for controlling the amount of current supplied to the light emitting element LD.

[0062] The light emitting element LD may be connected between a first power line PL1 and a second power line PL2. For example, a first electrode (or an anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via a second node N2, a first transistor M1, a first node N1, and a third transistor M3, and a second electrode (or a cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light of a predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0063] The light emitting element LD may be selected as an organic light emitting diode. Alternatively, the light emitting element LD may be selected as an inorganic light emitting diode such as a micro LED (light emitting diode) or a quantum dot light emitting diode. Alternatively, the light emitting element LD may be an element having a combination of organic and inorganic materials. Although FIG. 4 illustrates the pixel PXij as including a single light emitting element LD, in other embodiments, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, parallel, or series-parallel.

[0064] The pixel circuit PC may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0065] The first to fourth transistors M1 to M4 may be transistors including body electrodes. For example, each of the first to fourth transistors M1 to M4 may be a metal oxide semiconductor field effect transistor (MOSFET). In this case, the first to fourth transistors M1 to M4 can be implemented in a small area, thereby allowing the pixel PXij to be applied to a high-resolution panel. The body electrodes of the first to fourth transistors M1 to M4 may be supplied with a first driving power supply VDD. For example, the body electrodes of the first to fourth transistors M1 to M4 may be electrically connected to a first power line PL1.

[0066] In one embodiment of the present invention, the first transistor M1 to the fourth transistor M4 may be formed of P-type transistors, however, this is merely an example and at least one of the first transistor M1 to the fourth transistor M4 may be replaced with an N-type transistor.

[0067] A first electrode of the first transistor M1 may be connected to a first node N1, and a second electrode thereof may be connected to a second node N2. "Connected" includes the meaning of being electrically connected. A gate electrode of the first transistor M1 may be connected to a third node N3. The first node N1 may refer to a node to which a second electrode of the third transistor M3 is connected, and the second node N2 may refer to a node to which a first electrode of the light emitting element LD is connected. The first transistor M1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD in response to the voltage of the third node N3.

[0068] The second transistor M2 may be connected between the data line DLj and a third node N3. A gate electrode of the second transistor M2 may be electrically connected to the ith write scan line SL1i. The second transistor M2 may be turned on when the first scan signal GW is supplied to the ith write scan line SL1i, thereby electrically connecting the data line DLj and the third node N3.

[0069] A first electrode of the third transistor M3 may be electrically connected to the first power line PL1, and a second electrode of the third transistor M3 may be connected to the first node N1. A gate electrode of the third transistor M3 may be electrically connected to the light emitting control line ELk. The third transistor M3 may be turned off when a light emitting control signal is supplied to the light emitting control line ELk, and may be turned on when the light emitting control signal is not supplied. When the third transistor M3 is turned off, the first power line PL1 and the first node N1 may be electrically disconnected.

[0070] A first electrode of the fourth transistor M4 is connected to the second node N2, a second electrode of the fourth transistor M4 is electrically connected to the third power line PL3, and a gate electrode of the fourth transistor M4 is electrically connected to the i-th initialization scan line SL2i. When the second scan signal EB is supplied to the i-th initialization scan line SL2i, the fourth transistor M4 is turned on to electrically connect the second node N2 and the third power line PL3.

[0071] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may operate as a coupling capacitor to transfer a voltage change amount of the first node N1 to the third node N3 and store the voltage of the third node N3.

[0072] The second capacitor C2 may be connected between the third node N3 and a fourth power line PL4 to which a reference power supply VRF is supplied. The voltage level of the reference power supply VRF may be determined within a range not exceeding the maximum voltage that the second capacitor C2 can have. In this embodiment, the voltage level of the reference power supply VRF may be lower than the voltage level of the first driving power supply VDD and higher than the voltage level of the initialization power supply Vint.

[0073] In another embodiment, the voltage level of the reference power supply VRF may be the same as the voltage level of the first driving power supply VDD, in which case the second capacitor C2 may be connected between the third node N3 and the first power line PL1 to which the first driving power supply VDD is supplied.

[0074] The third capacitor C3 may be connected between the second node N2 and the third node N3, and may operate as a coupling capacitor to transfer the voltage change amount of the second node N2 to the third node N3.

[0075] In one embodiment of the present invention, each of the first to third capacitors C1 to C3 may be configured as a MOM (Metal-Oxide-Metal) capacitor or a MIM (Metal-Insulator-Metal) capacitor.

[0076] In one embodiment of the present invention, each of the first and second capacitors C1 and C2 may be a MOM (Metal-Oxide-Metal) capacitor or a MIM (Metal-Insulator-Metal) capacitor, and the third capacitor C3 may be a parasitic capacitor.

[0077] FIG. 5 is a waveform diagram showing an embodiment of a method for driving the pixel shown in FIG.

[0078] 2, 4, and 5, a horizontal period 1H (or a specific horizontal period) in which a data signal is supplied to a pixel PXij located on the ith horizontal line and the jth vertical line may be divided into a first period T1, a second period T2, and a third period T3. The start point of the second period T2 may be after the end point of the first period T1. The start point of the third period T3 may be after the end point of the second period T2. A fourth period T4 in which the light emitting element LD emits light may start after the horizontal period 1H. The start point of the fourth period T4 may be after the end point of the third period T3.

[0079] The data driver 140 may supply a voltage Vdata of a data signal to the data line DLj during a first period T1 to a third period T3.

[0080] The scan driver 130 (or the first scan driver 132) may supply a first scan signal GW to the i-th write scan line SL1i during the first and second periods T1 and T2.

[0081] The scan driver 130 (or the second scan driver 134) may supply a second scan signal EB to the i-th initialization scan line SL2i during the first to third periods T1 to T3.

[0082] The light emitting driver 160 can supply the light emitting control signal EM to the light emitting control line ELk during the first period T1, the third period T3, and the fourth period T4.

[0083] The first period T1 is a period during which the first driving power supply VDD voltage is supplied to the first node N1, the initialization power supply Vint voltage is supplied to the second node N2, and the data signal voltage Vdata is supplied to the third node N3. During the first period T1, the light emitting element LD can be initialized. During the first period T1, the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be initialized and simultaneously store the data signal voltage Vdata supplied to the third node N3. The first period T1 can be referred to as an initialization period and a data signal writing period.

[0084] The second period T2 is a period during which the voltage of the initialization power supply Vint is supplied to the second node N2 and the voltage of the data signal Vdata is supplied to the third node N3. During the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the first capacitor C1. The second period T2 may be referred to as a first threshold voltage compensation period.

[0085] During the third period T3, the first transistor M1 controls the amount of current supplied from the first driving power supply VDD to the initialization power supply Vint in response to the voltage of the third node N3. In this case, it is possible to prevent unnecessary current from being supplied to the light emitting element LD after the second period T2. The third period T3 can be called a brightness control period.

[0086] During the fourth period T4, the first transistor M1 controls the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light emitting element LD in response to the voltage of the third node N3. In this case, during the fourth period T4, the light emitting element LD can emit light at a brightness corresponding to the amount of current supplied from the first transistor M1. The fourth period T4 can be called a light emitting period.

[0087] 6 to 9 are circuit diagrams showing the operation process of the pixel according to the signals of Fig. 5. The pixel circuit PC of Figs. 6 to 9 can correspond to the pixel circuit PC of Fig. 5.

[0088] 6, during a first period T1, a first scan signal GW is supplied to the ith write scan line SL1i, and a second scan signal EB is supplied to the ith initialization scan line SL2i. During the first period T1, no light emitting control signal EM is supplied to the light emitting control line ELk, thereby turning on the third transistor M3. When the third transistor M3 is turned on, the voltage of the first driving power supply VDD is supplied to the first node N1.

[0089] When the first scan signal GW is supplied to the ith write scan line SL1i, the second transistor M2 is turned on. When the second transistor M2 is turned on, the data signal voltage Vdata is supplied from the data line DLj to the third node N3. At this time, the first capacitor C1 may be initialized by the data signal voltage Vdata and the voltage of the first driving power supply VDD. For example, the first capacitor C1 may be charged with a voltage corresponding to the data signal voltage Vdata and the first driving power supply VDD during the first period T1, regardless of the voltage charged in the previous period (or the previous frame period).

[0090] When the second scan signal EB is supplied to the ith initialization scan line SL2i, the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the voltage of the initialization power supply Vint is supplied to the second node N2. When the voltage of the initialization power supply Vint is supplied to the second node N2, the light emitting element LD may be initialized. For example, when the voltage of the initialization power supply Vint is supplied, a parasitic capacitor of the light emitting element LD may be discharged. Here, the voltage of the initialization power supply Vint is set to a voltage at which the light emitting element LD is turned off (or does not emit light), and thus the light emitting element LD may be set to a non-emitting state.

[0091] The second capacitor C2 can be initialized by the voltage Vdata of the data signal supplied via the data line DLj. For example, during the first period T1, the second capacitor C2 can be charged with a voltage corresponding to the voltage Vdata of the data signal and the reference power supply VRF, regardless of the voltage charged to the second capacitor C2 during the previous period (or the previous frame period).

[0092] The third capacitor C3 may be initialized by the voltage Vdata of the data signal supplied to the third node N3 and the voltage of the initialization power supply Vint supplied to the second node N2. For example, the third capacitor C3 may be charged with a voltage corresponding to the voltage Vdata of the data signal and the initialization power supply Vint during the first period T1, regardless of the voltage charged in the previous period (or the previous frame period).

[0093] During the first period T1, the current supplied from the first transistor M1 corresponding to the voltage of the third node N3 can be supplied to the initialization power source Vint via the fourth transistor M4, so that the light emitting element LD can maintain a non-emitting state during the first period T1.

[0094] Referring to FIG. 7, during the second period T2, the second transistor M2 can be maintained in a turned-on state by the first scan signal GW supplied to the ith write scan line SL1i, and the fourth transistor M4 can be maintained in a turned-on state by the second scan signal EB supplied to the ith initialization scan line SL2i.

[0095] During the second period T2, the third transistor M3 may be turned off by the light emitting control signal EM supplied to the light emitting control line ELk, and when the third transistor M3 is turned off, the electrical connection between the first power line PL1 and the first node N1 is cut off.

[0096] During the second period T2, the second transistor M2 is set to a turn-on state, and therefore the data signal voltage Vdata is supplied to the third node N3 from the data line DLj. In this case, the voltage of the first node N1 can be decreased from the voltage of the first driving power supply VDD to a voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the data signal voltage Vdata.

[0097] That is, during the second period T2, the third node N3 may be set to the voltage Vdata of the data signal, and the first node N1 may be set to a voltage obtained by adding the absolute value threshold voltage of the first transistor M1 to the voltage Vdata of the data signal (Vdata+|Vth(M1)|). Therefore, during the second period T2, the threshold voltage of the first transistor M1 may be stored in the first capacitor C1.

[0098] During the second period T2, the fourth transistor M4 is set to a turned-on state, so that the current supplied from the first node N1 to the second node N2 via the first transistor M1 can be supplied to the initialization power source Vint via the fourth transistor M4, thereby allowing the light emitting element LD to maintain a non-emitting state during the second period T2.

[0099] 8, during the third period T3, the supply of the light emitting control signal EM to the light emitting control line ELk is stopped, thereby turning on the third transistor M3. During the third period T3, the supply of the first scan signal GW to the i-th write scan line SL1i is stopped, thereby turning off the second transistor M2. During the third period T3, the supply of the second scan signal EB to the i-th initialization scan line SL2i is maintained, thereby turning on the fourth transistor M4.

[0100] During the third period T3, the third transistor M3 is turned on, thereby supplying the first drive power supply VDD to the first node N1, and the second transistor M2 is turned on, thereby supplying the data signal voltage Vdata from the data line DLj to the third node N3. Thus, the voltage of the third node N3 may be the sum of the data signal voltage Vdata and a value (α(VDD-(Vdata+|Vth(M1)|))) that reflects the difference between the voltage of the first node N1 and the voltage of the first drive power supply VDD during the second period T2.

[0101] The first transistor M1 controls the amount of current supplied from the first driving power source VDD to the second node N2 in response to the voltage applied to the third node N3.

[0102] At this time, because the fourth transistor M4 is turned on, the current supplied to the second node N2 can be supplied to the initialization power supply Vint. As a result, the light emitting element LD is set to a non-emitting state during the third period T3, enabling accurate gray scale representation in the display device 100. For example, during the second period T2, the voltage of the second node N2 may rise to a voltage higher than the desired voltage. As a result, an unintended current may be supplied to the light emitting element LD. For example, even when implementing a black gray scale in the pixel PXij, the light emitting element LD may temporarily emit light. According to one embodiment of the present invention, the current supplied from the first transistor M1 is supplied to the initialization power supply Vint during the third period T3, thereby preventing unintended emission of light from the light emitting element LD.

[0103] 9, during the fourth period T4, the supply of the second scan signal EB to the i-th initialization scan line SL2i is stopped, thereby turning off the fourth transistor M4. During the fourth period T4, the first scan signal GW is not supplied to the i-th write scan line SL1i, thereby maintaining the second transistor M2 in the turned-off state. During the fourth period T4, the light emitting control signal EM is not supplied to the light emitting control line ELk, thereby maintaining the third transistor M3 in the turned-on state.

[0104] At this time, the first transistor M1 can control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light emitting element LD in response to the voltage of the third node N3. During the fourth period T4, the light emitting element LD can generate light with a brightness corresponding to the amount of driving current supplied from the first transistor M1.

[0105] A threshold voltage compensation process according to an embodiment of the present invention will be described in detail with reference to FIGS.

[0106] 7, the threshold voltage of the first transistor M1 may be determined by the voltage difference between the body electrode and the source electrode (e.g., the first node N1). For example, assuming that the voltage of the first drive power supply VDD is set to 8V, the body electrode of the first transistor M1 may be set to 8V and the source electrode may be set to a voltage lower than the body electrode during the second period T2. As an example, assuming that the first node N1 is set to 4V, the voltage difference between the body electrode and the source electrode of the first transistor M1 may be set to 4V (e.g., VBS=4V). In this case, the first transistor M1 may have a first threshold voltage corresponding to the voltage difference between the body electrode and the source electrode of 4V.

[0107] During the second period T2, the first threshold voltage may be compensated. For example, during the second period T2, the third node N3 is set to the voltage Vdata of the data signal, and the first node N1 is set to a voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal. The threshold voltage of the first transistor M1 may be stored in the first capacitor C1. Thus, according to one embodiment of the present invention, the threshold voltage of the first transistor M1 may be primarily compensated during the second period T2. For example, after the second period T2, the third transistor M3 is turned on, and the threshold voltage reflected at the first node N1 may be reflected in the voltage of the third node N3. The turn-on and / or turn-off of the first transistor M1 may be controlled according to the voltage of the third node N3. This compensates the first threshold voltage of the first transistor M1.

[0108] 8, during the third period T3, the first node N1 may be set to the voltage of the first drive power supply VDD. Thus, the source electrode of the first transistor M1 may have the same voltage as the body electrode. For example, the voltage difference between the source electrode and the body electrode of the first transistor M1 may be approximately 0 V. In response to the changed voltage difference between the body electrode and the source electrode of the first transistor M1, the first transistor M1 may have a second threshold voltage different from the first threshold voltage.

[0109] During the third period T3, when the voltage of the first driving power supply VDD is supplied to the first node N1, the voltage of the third node N3 may change according to the change in the voltage of the first node N1. In this embodiment, the voltage of the third node N3 may be set as shown in Equation 1.

[0110]

number

[0111] Referring to Equation 1, VN3a may represent the voltage of the third node N3. During the third period T3, the first drive power supply VDD is provided to the first node N1, so that the voltage of the first node N1 may be changed from the voltage (Vdata + |Vth(M1)|) obtained by adding the voltage Vdata of the data signal and the absolute threshold voltage (|Vth(M1)|) of the first transistor M1 to the voltage of the first drive power supply VDD during the third period T3. Therefore, VDD - (Vdata + |Vth(M1)|) may represent the amount of change in the voltage of the first node N1.

[0112] The voltage of the third node N3 may also be changed by the coupling of the first capacitor C1. The amount of change in the voltage of the third node N3 may be determined according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3. For example, as shown in Equation 1, the amount of change in the voltage of the third node N3 resulting from the amount of change in the voltage of the first node N1 may be a value obtained by multiplying the amount of change in the voltage of the first node N1 by C1 / (C1+C2+C3). In this way, when the amount of change in the voltage of the third node N3 is controlled by the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, a sufficiently wide voltage range of the data signal can be ensured. For example, the voltage range of the data signal may be determined by the components included in the pixel PXij. In one embodiment of the present invention, the voltage of the third node N3 is changed according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, so that a wide voltage range of the data signal Vdata can be set. For example, depending on the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3, the voltage change amount of the third node N3 may be relatively low, and accordingly, the voltage of the third node N3 may also be relatively low. As a result, even if the voltage range of the data signal is designed to be relatively wide, the voltage applied to the third node N3 may fall within a required voltage range. For example, the data driver 140 may implement 255 gray levels using a relatively wide voltage range of about 3.29V. As a result, fine gray level representation of the pixel PXij may be possible in one embodiment of the present invention.

[0113] The second capacitor C2 adjusts the ratio of the voltage change amount at the first node N1 to the voltage change amount at the second node N2. For example, as the second capacitor C2 increases, the voltage change amount at the third node N3 relative to the voltage change amount at the first node N1 may decrease. In this case, the voltage range of the data signal may be selected to be more suitable for the display device 100.

[0114] Meanwhile, after the voltage of the third node N3 is set as in Equation 1, the amount of current supplied to the second node N2 through the first transistor M1 can be changed in response to the voltage of the third node N3, thereby changing the voltage of the anode electrode (e.g., the second node N2) of the first transistor M1.

[0115] The second node N2 and the third node N3 are coupled via a third capacitor C3. The voltage of the third node N3 may be further varied depending on the amount of voltage variation of the second node N2. For example, the voltage of the third node N3 may be varied by the coupling of the third capacitor C3.

[0116]

number

[0117] Referring to Equation 2, ΔVN2 represents the voltage change amount of the second node N2, and VN3b represents the voltage of the third node N3 corresponding to the voltage change amount ΔVN2 of the second node N2. As shown in Equation 2, the voltage of the third node N3 can be determined by the sum of VN3a in Equation 1 and a value obtained by multiplying the voltage change amount ΔVN2 of the second node N2 by C3 / (C1+C2+C3).

[0118] According to an embodiment of the present invention, the voltage change amount ΔVN2 of the second node N2 is reflected in the voltage of the third node N3 via the third capacitor C3, thereby secondarily compensating for the threshold voltage of the first transistor M1.

[0119] The voltage change amount ΔVN2 of the second node N2 may be set in response to a change in the threshold voltage of the first transistor M1. For example, the voltage change amount ΔVN2 of the second node N2 may be determined to vary in response to a change from the first threshold voltage to the second threshold voltage of the first transistor M1. For example, the voltage change amount ΔVN2 of the second node N2 may reflect the second threshold voltage of the first transistor M1. The voltage of the third node N3 is further changed in accordance with the voltage change amount ΔVN2 of the second node N2, and the first transistor M1 is turned on and / or turned off, thereby compensating for the second threshold voltage of the first transistor M1.

[0120] According to one embodiment of the present invention, threshold voltage compensation is performed independently for each of the first transistors M1 included in the pixel PX of FIG. 2. For example, each of the pixels PX included in the pixel unit 110 of FIG. 2 may include a first transistor. In this case, during the driving process of the display device 100, each of the first transistors of the pixel PX may have a different threshold voltage. In this case, the voltage change amounts of the first and second nodes N1 and N2 of the pixel PX may also be set to be different corresponding to the respective threshold voltages of the first transistors. The voltage change amounts of the first and second nodes N1 and N2 may be reflected in the third node N3, thereby compensating for the threshold voltage of the first transistor included in each of the pixel PX. According to one embodiment of the present invention, the display device 100 may have improved gray scale expression.

[0121] The aspects of the present invention are not limited to the contents described in the detailed description of the specification, but should be defined by the claims. All modifications and variations derived from the claims and their equivalents should be construed as being included in the technical scope of the present invention. [Explanation of symbols]

[0122] 100 display device 110 Pixel section 120 Timing control section 130 Scanning driver 132 First scan driver 134 Second scan driver 140 Data Drive Unit 150 Power supply section 160 Light emitting driver

Claims

1. a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node, the second transistor having a gate electrode electrically connected to the first scan line; a third transistor connected between a first power supply line to which a first driving power supply is supplied and the first node, the third transistor having a gate electrode electrically connected to the light emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power supply line to which a reference power supply is supplied; a third capacitor connected between the second node and the third node; a light-emitting element connected between the second node and a second power line to which a second driving power source is supplied;

2. 2. The pixel of claim 1, further comprising a fourth transistor having a first electrode connected to the second node, a second electrode electrically connected to a third power line to which an initialization power source is supplied, and a gate electrode electrically connected to the second scan line.

3. The pixel of claim 2 , wherein the voltage level of the reference power supply is lower than the voltage level of the first driving power supply and higher than the voltage level of the initialization power supply.

4. the voltage level of the reference power supply is the same as the voltage level of the first driving power supply; The pixel according to claim 2 , wherein the reference power supply line is the first power supply line.

5. 3. The pixel of claim 2, wherein the light-emitting element is turned off when the voltage of the initialization power supply is supplied to the second node.

6. The pixel of claim 2 , wherein each of the first to fourth transistors is a MOSFET including a body electrode.

7. The pixel of claim 6 , wherein the voltage of the first driving power source is supplied to the body electrodes of the first to fourth transistors.

8. one horizontal period includes a first period, a second period, and a third period; During the first period, the second transistor, the third transistor, and the fourth transistor are set to a turned-on state; During the second period, the second transistor and the fourth transistor are set to a turned-on state, and the third transistor is set to a turned-off state; The pixel of claim 2 , wherein during the third period, the third transistor and the fourth transistor are set to a turned-on state, and the second transistor is set to a turned-off state.

9. The pixel of claim 8 , wherein a voltage of a data signal is supplied to the data line during the first period, the second period, and the third period.

10. 2. The pixel of claim 1, wherein each of the first to third capacitors is a metal-oxide-metal (MOM) capacitor or a metal-insulator-metal (MIM) capacitor.

11. Each of the first and second capacitors is a MOM (Metal-Oxide-Metal) capacitor or a MIM (Metal-Insulator-Metal) capacitor; The pixel according to claim 1 , wherein the third capacitor is a parasitic capacitor.

12. The pixel includes a pixel connected to a write scan line, an initialization scan line, a data line, and a light emission control line; The pixel located in the i-th (i is an integer equal to or greater than 0) pixel row and the j-th (j is an integer equal to or greater than 0) pixel column is a first transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a j-th data line of the data lines and the third node, and turned on when a first scan signal is supplied to a first scan line of the write scan lines; a third transistor connected between a first power supply line to which a voltage of a first driving power supply is supplied and the first node, and turned off when a light emission control signal is supplied to a k-th (k is an integer equal to or greater than 0) light emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the third node and a reference power supply line to which a reference power supply is supplied; a third capacitor connected between the second node and the third node; a light-emitting element connected between the second node and a second power line to which a second driving power source is supplied.

13. The pixel located in the i pixel row and the j pixel column is 13. The display device of claim 12, further comprising a fourth transistor having a first electrode connected to the second node and a second electrode electrically connected to a third power line through which an initialization power source is supplied, the fourth transistor being turned on when a second scanning signal is supplied to the second scanning line.

14. The display device of claim 13 , wherein the voltage level of the reference power supply is lower than the voltage level of the first driving power supply and higher than the voltage level of the initialization power supply.

15. the voltage level of the reference power supply is the same as the voltage level of the first driving power supply; The display device according to claim 13 , wherein the reference power supply line is the first power supply line.

16. The display device of claim 15, wherein each of the first to fourth transistors is a MOSFET including a body electrode, and the body electrode is supplied with the voltage of the first driving power supply.

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