Processor, information processing device and control method for processor

Abstract

To provide a processor, an information processing device and a control method for a processor for reducing branch prediction latency.SOLUTION: A branch instruction processing unit determines whether a branch has occurred based on a given branch instruction, detects branch prediction errors, and completes the given branch instruction. A prediction TAGE table RAM 171 stores a prediction TAGE table used for branch prediction for fetching. An update TAGE table RAM 173 stores an update TAGE table, in which information similar to that in the prediction TAGE table is registered. An update determination circuit 172 determines whether to execute an update when it receives notification of the completion of a predetermined branch instruction and obtains information related to the predetermined branch instruction from the update TAGE table, provided that no write operation for updating has been performed on the update TAGE table. If it determines to execute the update, it updates both the prediction TAGE table and the update TAGE table.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a processor, an information processing device, and a method for controlling a processor. [Background technology]

[0002] The TAGE (Tagged Geometric History Length Branch Prediction) branch prediction mechanism is widely known as a branch prediction mechanism with high prediction accuracy. The TAGE branch predictor has a T0 table (also called a bimodal table) indexed by a program counter (PC). The TAGE branch predictor also has multiple tables indexed by the exclusive OR of the program counter and a global history register (GHR). For example, the TAGE branch predictor has T1 to T4 tables as multiple tables indexed by the exclusive OR of the program counter and GHR. The T1 to T4 tables have GHR lengths that increase geometrically in the order of T1 table, T2 table, T3 table, and T4 table. For example, the T1 to T4 tables have GHR lengths that increase from 2, 4, 8, and 16.

[0003] The TAGE branch predictor folds the GHR when the GHR length is longer than the table index length. Each of the T1 to T4 tables has a tag, Pred, and a useful bit. Pred is a counter that increases or decreases depending on whether the result is taken or not taken, and is used to determine whether the result is taken or not.

[0004] When making a prediction, the TAGE branch predictor searches each of the T0 to T4 tables. Then, among the results where the tag matches (TAG-MATCH) between T1 and T4, the TAGE branch predictor uses the result with the longest GHR length as the prediction.

[0005] When updating the table, the TAGE branch predictor performs the update according to the TAGE algorithm, but the useful bit indicates the validity of each entry, and determines that entries with a useful bit value of 0 can be overwritten. If the prediction is incorrect, the TAGE branch predictor creates an entry by overwriting an entry with a useful bit value of 0. The TAGE branch predictor also updates the Pred of the entry used in the prediction according to the actual result, whether the branch was taken or not taken.

[0006] When TAGE branch prediction is implemented in a superscalar, out-of-order, and pipelined processor, branch prediction is typically performed in a pipeline stage close to instruction fetch. On the other hand, table updates are performed after it is determined whether the branch instruction is taken or not, and are therefore often performed in the latter pipeline stages, at the pipeline stage where the branch instruction is completed.

[0007] In addition, in the TAGE branch prediction, the table is read once before the update to determine whether to update the counter, and a read is also performed during the update to write the counter, etc. Because the pipeline stage close to the instruction fetch and the pipeline stage where the branch instruction is completed are separated, the TAGE branch predictor has two independent systems: a read port for prediction and a read port for update. In addition, since branch prediction is performed in parallel when writing the read results, TAGE branch predictors generally perform read and write operations simultaneously.

[0008] In addition, since the prediction accuracy of the TAGE branch prediction mechanism generally improves with an increased number of entries, it is often implemented using area-efficient SRAM. Therefore, when implementing a TAGE branch prediction mechanism, it is usually implemented using RAM that is capable of 2 read-1 write and simultaneous read-write. 2 read-1 write is a function that allows reading to be performed in two independent systems and writing to be performed in one system. Simultaneous read-write is a function that allows writing and reading to be performed simultaneously.

[0009] For example, a technique has been proposed for the TAGE branch prediction mechanism that determines the confidence level of a branch prediction by adding weighted or normalized values ​​of the TAGE alternate count, provider count, and bimodal count and comparing the result to a threshold. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Special Publication No. 2023-540036 Summary of the Invention [Problem to be solved by the invention]

[0011] However, RAMs that support 2Read-1Write and simultaneous Read-Write generally tend to be larger in area, sometimes twice as large as RAMs that do not support 1Read-1Write and simultaneous Read-Write. As RAM area increases, the wiring length for transmitting signals used in prediction increases, resulting in longer prediction latency. Furthermore, even with technology that predicts the reliability level of branch predictions from TAGE substitution counts, no special consideration is given to the RAM used, making it difficult to suppress the extension of latency due to increased RAM area.

[0012] The disclosed technology has been made in view of the above, and aims to provide a processor, an information processing device, and a method for controlling a processor that reduce the latency of branch prediction. [Means for solving the problem]

[0013] In one aspect of the processor, information processing device, and processor control method disclosed herein, a pipeline fetches and executes an instruction. A branch instruction processing unit determines whether a branch has been taken due to a predetermined branch instruction during execution of the instruction in the pipeline, detects a branch prediction error, and completes the predetermined branch instruction. A first storage unit stores a first table in which information about branch instructions is registered and which is used for branch prediction for the fetch. A second storage unit stores a second table in which information about branch instructions similar to that in the first table is registered. If no writing for updating has been performed in the second table, an update determination circuit, upon receiving notification of completion information of the predetermined branch instruction from the branch instruction processing unit, obtains information about the predetermined branch instruction from the second table and determines whether to perform an update. If it determines to perform the update, it updates the first table and the second table. [Effects of the Invention]

[0014] In one aspect, the present invention can reduce the latency of branch prediction. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a system according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a superscalar processor according to an embodiment. [Figure 3] FIG. 3 is a block diagram of a branch prediction mechanism. [Figure 4] FIG. 4 is a flowchart of a process for notifying completion information of a completed branch instruction. [Figure 5] FIG. 5 is a flowchart of the TAGE table update process. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of a processor, an information processing device, and a method for controlling a processor disclosed in the present application will be described in detail with reference to the accompanying drawings. Note that the processor, the information processing device, and the method for controlling a processor disclosed in the present application are not limited to the following embodiments. [Example]

[0017] 1 is a diagram showing an example of the configuration of a system according to an embodiment of the present invention, which is, for example, an information processing device such as a server 1 shown in FIG.

[0018] The server 1 is an information processing device having a plurality of CPUs (Central Processing Units) 10, a plurality of memories 11, and an interconnect control unit 13.

[0019] The interconnect control unit 12 relays communications between the CPUs 10. For example, the interconnect control unit 12 relays communications between the CPUs 10. The interconnect control unit 12 also relays communications between each CPU 10 and the external device 2.

[0020] The memory 11 is a main storage device, and is, for example, a dynamic random access memory (DRAM).

[0021] Each CPU 10 is connected to a separate memory 11. Each CPU 10 is also connected to an interconnect control unit 12. Each CPU 10 is an example of a "processor."

[0022] The CPU 10 communicates with other CPUs 10 and external devices 2 via the interconnect control unit 12. The CPU 10 also uses a memory 11 to execute various programs such as an OS (Operating System).

[0023] The CPU 10 according to this embodiment executes a program using pipeline processing. Furthermore, the CPU 10 executes the program by performing TAGE branch prediction on branch instructions. If a branch prediction error occurs, the CPU 10 performs out-of-order re-instruction fetching to continue processing from the address of the correct branch instruction. An example of the details of the CPU 10 will be described below.

[0024] 2 is a diagram illustrating an example of the configuration of a superscalar processor according to an embodiment. Here, an example will be described in which the CPU 10 is a superscalar processor that performs multiple pipeline processes in parallel. However, FIG. 2 is an example of the CPU 10, and the CPU 10 may be a processor with a different configuration.

[0025] 2, the CPU 10 includes an instruction fetch address generator 101, a primary instruction cache 102, a secondary instruction cache 103, an instruction buffer 104, an instruction decoder 105, and a register renaming unit 106. The CPU 10 also includes a reservation station for address generation (RSA) 110, an operand address generator 111, and a primary data cache 112. The CPU 10 also includes a reservation station for execution (RSE) 120, a computing unit 121, a fixed-point update buffer 122, a reservation station for floating point (RSF) 130, a computing unit 131, and a floating-point update buffer 132. The CPU 10 also includes a reservation station for branch (RSBR) 140, a commit stack entry (CSE) 150, a program counter (PC) 160, and a branch prediction mechanism 170.

[0026] The mechanisms other than the secondary instruction cache 103 in the CPU 10 are sometimes called cores. Each reservation station, such as the RSA 110, RSE 120, RSF 130, and RSBR 140, is a mechanism that holds instructions until they are executable. Each of the RSA 110, RSE 120, RSF 130, and RSBR 140 has a queue.

[0027] The instruction fetch address generator 101, the instruction buffer 104, and the instruction decoder 105 correspond to an instruction execution pipeline, and the instruction fetch address generator 101 and the instruction buffer 104 correspond to an instruction fetch mechanism.

[0028] The instruction fetch address generator 101 receives an input of an instruction fetch address in accordance with the program order from the program counter 160. The instruction fetch address generator 101 also receives an input of a branch prediction result obtained by the branch prediction mechanism 170.

[0029] If the branch prediction result by the branch prediction mechanism 170 indicates that the instruction will not branch, the instruction fetch address generator 101 processes the instructions in the order obtained from the program counter 160. If the branch prediction result by the branch prediction mechanism 170 indicates that the instruction will branch, the instruction fetch address generator 101 generates a fetch address of the branch destination. Then, the instruction fetch address generator 101 processes the instruction at the generated fetch address. Then, the instruction fetch address generator 101 outputs the generated fetch address to the branch prediction mechanism 170. Thereafter, the instruction fetch address generator 101 continues processing the instructions following that instruction in the order obtained from the program counter 160.

[0030] The instruction fetch address generator 101 processes each instruction as follows. If the instruction at the generated fetch address results in a cache hit in the primary instruction cache 102, the instruction fetch address generator 101 stores the instruction held in the primary instruction cache 102 in the instruction buffer 104. On the other hand, if there is a cache miss in the primary instruction cache 102, the instruction fetch address generator 101 searches for the target instruction in the secondary instruction cache 103. If there is a cache hit in the secondary instruction cache 103, the instruction fetch address generator 101 stores the instruction held in the secondary instruction cache 103 in the primary instruction cache 102 and also stores the instruction in the instruction buffer 104. If there is a cache miss in the secondary instruction cache 103, the instruction fetch address generator 101 obtains the instruction from the memory 11. Thereafter, the instruction fetch address generator 101 causes the primary instruction cache 102 to store the instruction held in the secondary instruction cache 103 , and also causes the instruction buffer 104 to store the instruction.

[0031] The instruction buffer 104 is a buffer that stores a sequence of instructions to be executed in the future. The instruction buffer 104 stores instructions up to its maximum capacity, regardless of the instruction execution status. The instruction buffer 104 can also output the instructions it holds, regardless of the instruction fetch status. The instruction buffer 104 separates instruction fetching from instruction execution, thereby concealing the latency caused by instruction execution and instruction fetching.

[0032] The instruction decoder 105 acquires the instructions stored in the instruction buffer 104 in the order of processing, decodes the acquired instructions, and outputs the decoded instructions to the register renaming 106.

[0033] The register renaming 106 is a buffer that temporarily holds instructions until their execution is committed (confirmed) and stored in a register. The register renaming 106 receives a decoded instruction as input from the instruction decoder 105. Next, the register renaming 106 determines the resource to be used for executing the instruction from among the RSA 110, RSE 120, RSF 130, and RSBR 140. The register renaming 106 then determines whether the determined resource has free space. If the determined resource has free space, the register renaming 106 assigns the determined resource to the decoded instruction. The register renaming 106 then assigns an identifier to the decoded instruction and issues the instruction to one of the RSA 110, RSE 120, RSF 130, and RSBR 140 that has been assigned.

[0034] The register renaming 106 also assigns an instruction identification (IID) to each of the decoded instructions in order, and transmits the instruction identifiers to the CSE 150 in the assigned order.

[0035] The RSA 110 is a reservation station for calculating addresses of load / store instructions. A load / store instruction is either a load instruction or a store instruction. The RSA 110 holds the instruction obtained from the instruction decoder 105 until the operand address generator 111 is able to process it. After that, when the operand address generator 111 is able to process it, the RSA 110 outputs the instruction to the operand address generator 111. The RSA 110 executes the load / store instruction out of order. After that, when the execution of the load / store instruction is completed, the RSA 110 reports the end of the execution instruction to the CSE 150.

[0036] There are multiple operand address generators 111. The operand address generators 111 receive input of load / store instructions from the RSA 110. Then, the operand address generators 111 generate operands for address calculation, perform address calculation using the generated addresses, and generate addresses according to the instructions. Thereafter, the operand address generators 111 wait for store data and write the data to the primary data cache 112 using the generated addresses.

[0037] The RSE 120 is a reservation station for integer operations. The RSE 120 holds the instruction obtained from the instruction decoder 105 until the arithmetic unit 121 is ready to perform the operation. After that, when the arithmetic unit 121 is ready to perform the operation, the RSE 120 outputs the instruction to the arithmetic unit 121. The RSE 120 executes the instruction out of order. After that, when the execution of the operation instruction is completed, the RSE 120 reports the end of the execution instruction to the CSE 150.

[0038] There are multiple arithmetic units 121. The arithmetic units 121 execute fixed-point arithmetic using a fixed-point update buffer 122 and a fixed-point register 123. After the arithmetic operation is completed, the result data is written to the fixed-point update buffer 122. Thereafter, when the calculation data is committed, the committed calculation data is sent to the fixed-point register 123.

[0039] The RSF 130 is a reservation station for floating-point operations. The RSF 130 holds the instruction obtained from the instruction decoder 105 until the arithmetic unit 131 is ready to perform the operation. After that, when the arithmetic unit 131 is ready to perform the operation, the RSF 130 outputs the instruction to the arithmetic unit 131. The RSF 130 executes the instruction out of order. After that, when the execution of the operation instruction is completed, the RSF 130 reports the end of the execution instruction to the CSE 150.

[0040] There are multiple arithmetic units 131. Each arithmetic unit 131 executes a floating-point calculation using a floating-point update buffer 132 and a floating-point register 133. After the calculation is completed, the result data is written to the floating-point update buffer 132. After that, when the calculation data is committed, the committed calculation data is sent to the floating-point register 133.

[0041] The CSE 150 is a circuit that executes the commit process. The CSE 150 has a queue that stores decoded instructions in the order in which the instructions are to be executed. The CSE 150 stores and accumulates instructions received from the register renaming 106 in the queue in the order in which the instructions are to be executed. Then, the CSE 150 stores the instructions in the queue and waits for a report that the instructions have been processed.

[0042] The CSE 150 receives out-of-order completion reports of each executed instruction from the RSA 110, RSE 120, and RSF 130. The CSE 150 also receives in-order signals from the RSBR 140 indicating the completion of branch instruction processing.

[0043] The CSE 150 then reorders the queued instructions awaiting completion reports in accordance with the execution order. When the CSE 150 receives a signal indicating that processing has completed, it commits the queued instructions for which processing has been notified, and updates the resources.

[0044] The RSBR 140 is a reservation station for branch instructions. The RSBR 140 receives branch instruction input from the instruction decoder 105. Then, the RSBR 140 stores the branch instruction in its own RSBR queue. The RSBR queue is a queue that operates on a FIFO (First In First Out) basis. Each entry in the RSBR queue holds the predicted address and the prediction result indicating whether the branch will be taken or not taken in the branch prediction.

[0045] The RSBR 140 receives the results of the calculations performed by the arithmetic unit 121 or 131 from the arithmetic unit 121 or 131. Then, the RSBR 140 determines whether the branch instruction resulted in a branch (taken) or a branch (not-taken) based on the calculation results obtained for each entry. For example, if the CPU 10 is an ARM-based processor, the RSBR 140 obtains a value stored in the NZCV register based on the calculation results of the NZCV determination instruction to make the determination. The RSBR 140 also determines the target address of the instruction stored for each entry.

[0046] The RSBR 140 normally processes branch instructions stored in the RSBR queue in order. That is, the RSBR 140 processes the instructions stored in the RSBR queue in the order they were stored. However, the RSBR 140 outputs an instruction re-fetch request out of order when a branch prediction error occurs.

[0047] The RSBR 140 uses the branch determination result of each entry to determine whether a branch misprediction has occurred in each branch instruction. If the RSBR 140 determines that a branch misprediction has occurred, it decides to re-fetch an instruction for that branch instruction. The RSBR 140 then outputs an instruction re-fetch request to the instruction fetch address generator 101, causing the instruction fetch address generator 101 to execute the instruction re-fetch. Furthermore, the RSBR 140 clears instructions in the pipeline before they are decoded, thereby clearing the pipeline.

[0048] After that, the RSBR 140 completes the branch instruction in order after determining whether a branch prediction error has occurred. Then, the RSBR 140 outputs a completion report and completion information for the completed branch instruction to the branch prediction mechanism 170. However, if the RSBR 140 receives an instruction from the branch prediction mechanism 170 to inhibit the completion of the branch instruction, the RSBR 140 suspends the process of completing the branch instruction until it receives a notification that the inhibition has been lifted. Here, the completion information includes information indicating whether the completed branch instruction was taken (Taken) or not taken (Not-Taken). This RSBR 140 is an example of a "branch instruction processing unit."

[0049] The branch prediction mechanism 170 executes TAGE branch prediction and outputs the prediction result indicating whether the instruction will be taken or not taken to the instruction fetch address generator 101.

[0050] Fig. 3 is a block diagram of the branch prediction mechanism. The operation of the branch prediction mechanism 170 will be described in detail below with reference to Fig. 3. The branch prediction mechanism 170 includes a prediction TAGE table RAM (Random Access Memory) 171, an update determination circuit 172, an update TAGE table RAM 173, a TAGE update buffer 174, and a control unit 175.

[0051] The prediction TAGE table RAM 171 holds a prediction TAGE table used for TAGE branch prediction by the branch prediction mechanism 170. Information about branch instructions, such as completion information, is registered in the prediction TAGE table. The prediction TAGE table RAM 171 is located near an instruction fetch mechanism, such as the instruction fetch address generator 101. The prediction TAGE table RAM 171 is a RAM that supports one read and one write and does not support simultaneous read and write execution.

[0052] The update TAGE table RAM 173 holds an update TAGE table used to determine whether to update the TAGE table. The update TAGE table is a table used to determine whether to update the prediction TAGE table, and information about branch instructions similar to that of the prediction TAGE table is registered in it. The update TAGE table RAM 173 is located near the location where the completion of branch instructions is processed. For example, the update TAGE table RAM 173 is located near the RSBR 140. The update TAGE table RAM 173 is also a RAM that supports 1 read and 1 write and does not support simultaneous read and write execution. Hereinafter, the prediction TAGE table and the update TAGE table may be collectively referred to simply as the "TAGE table."

[0053] Here, the prediction TAGE table is an example of a "first table." The prediction TAGE table RAM171 is an example of a "first storage unit." The update TAGE table is an example of a "second table." The update TAGE table RAM173 is an example of a "second storage unit."

[0054] The control unit 175 receives a completion report and completion information for a completed branch instruction from the RSBR 140. Upon receiving the completion report, the control unit 175 creates an entry for the completed branch instruction in the TAGE update buffer 174. If there is no space to create an entry in the TAGE update buffer 174, the control unit 175 inhibits the RSBR 140 from completing the branch instruction. The control unit 175 registers information about the branch instruction for which the completion report was received, including the completion information of the branch instruction, in the created entry. After that, when space becomes available in the TAGE update buffer 174, the control unit 175 notifies the RSBR 140 that the inhibition of the completion of the branch instruction has been lifted.

[0055] Furthermore, the control unit 175 adds an out-pointer to indicate the entry of the next instruction to be read in order to read in-order the completion information of the branch instruction whose entry has been created in the TAGE update buffer 174. This TAGE update buffer 174 is an example of a "temporary storage unit." That is, the control unit 175 receives notification of a predetermined branch instruction from the RSBR 140 and stores the completion information of the predetermined branch instruction in the TAGE update buffer 174, which is a temporary storage unit.

[0056] Thereafter, the control unit 175 reads the completion information of the branch instruction from the TAGE update buffer 174 in order to have the update determination circuit 172 determine whether to update the TAGE table. Here, when reading the completion information of the branch instruction from the TAGE update buffer 174, the control unit 175 determines whether or not it has received an instruction from the update determination circuit 172 to inhibit reading of the branch prediction from the TAGE update buffer 174. If it has received an instruction to inhibit reading of the branch prediction, the control unit 175 inhibits reading of the completion information of the branch prediction until it receives an instruction from the update determination circuit 172 to cancel the inhibition of reading of the branch prediction.

[0057] If the control unit 175 has not received an instruction to inhibit reading of the branch prediction or has received a notification that inhibition of reading of the branch prediction has been lifted, the control unit 175 reads the branch instruction from the entry indicated by the out-pointer. Furthermore, at the timing when the control unit 175 reads the branch instruction, the control unit 175 determines whether writing to the update TAGE table RAM 173 by the update determination circuit 172 has been performed.

[0058] The control unit 175 executes the following process when the update determination circuit 172 has not written to the update TAGE table RAM 173. The control unit 175 determines that there is no collision between the read of the update TAGE table from the update TAGE table RAM 173 for update determination by the update determination circuit 172 and the write to the update TAGE table RAM 173 for updating the update TAGE table. Then, the control unit 175 notifies the update determination circuit 172 of the completion information of the branch instruction read from the TAGE update buffer 174. Furthermore, the control unit 175 deletes the entry of the read branch instruction from the update TAGE table RAM 173, and updates the out-pointer to point to the entry of the branch instruction to be read next.

[0059] On the other hand, if it is determined that the update determination circuit 172 is writing to the update TAGE table RAM 173, the control unit 175 executes the following process. The control unit 175 determines that there is a conflict between the read of the update TAGE table from the update TAGE table RAM 173 for update determination by the update determination circuit 172 and the write to the update TAGE table RAM 173 for updating the update TAGE table. In this case, the control unit 175 stops notifying the update determination circuit 72 of the completion information of the branch instruction read from the TAGE update buffer 174. The control unit 175 then maintains the out-pointer indicating the read entry. By not updating the out-pointer in this way, the control unit 175 can reprocess, in the next order, the branch instructions that were read but for which update determination was not performed.

[0060] Maintaining the out-pointer indicating the read entry without notifying the update determination circuit 72 of the completion information of the branch instruction read from the TAGE update buffer 174 can be said to be processing that treats the branch instruction as not having been read from the TAGE update buffer 174. Therefore, in the following, processing that maintains the out-pointer indicating the read entry without notifying the update determination circuit 72 of the completion information of the branch instruction read from the TAGE update buffer 174 is called "cancelling the reading of the branch instruction."

[0061] In this way, the control unit 175 reads the completion information of the predetermined branch instruction from the TAGE update buffer 174, which is a temporary storage unit, and determines whether or not writing for updating has been performed on the update TAGE table, which is the second table. If writing for updating has not been performed on the update TAGE table, the control unit 175 notifies the update determination circuit 172 of the completion information of the predetermined branch instruction.

[0062] The update determination circuit 172 receives notification of completion information of the branch instruction read from the TAGE update buffer 174 from the control unit 175. Then, the update determination circuit 172 reads the branch instruction indicated by the notified completion information from the update TAGE table stored in the update TAGE table RAM 173. Then, the update determination circuit 172 determines whether to update the TAGE table using the information in the update TAGE table and the completion information.

[0063] When updating the TAGE table, the update determination circuit 172 updates both the update TAGE table held in the update TAGE table RAM 173 and the prediction TAGE table held in the prediction TAGE table RAM 171. For example, the update determination circuit 172 updates Pred, which is a counter that counts branch results in the update TAGE table and the prediction TAGE table, according to the determination result of whether the branch was taken (Taken) or not (Not-Taken). The update determination circuit 172 also updates Useful in the update TAGE table and the prediction TAGE table according to the result of whether a branch prediction error occurred.

[0064] In this way, when the update determination circuit 172 has not written anything for updating to the update TAGE table itself, it receives from the control unit 175 a notification of completion information sent from the RSBR 140. That is, when the update determination circuit 172 has not written anything for updating to the second table, it receives a notification of completion information of a predetermined branch instruction from the RSBR 140. Then, the update determination circuit 172 obtains information about the predetermined branch instruction from the second table to determine whether or not to execute the update, and if it determines to execute the update, it updates the first table and the second table.

[0065] When updating the TAGE table, the update determination circuit 172 instructs the control unit 175 to inhibit reading of branch predictions from the TAGE update buffer 174. The update determination circuit 172 also notifies the instruction fetch address generator 101 of the inhibition of instruction fetching. After that, when the writing is completed, the update determination circuit 172 notifies the control unit 175 of the cancellation of the inhibition of reading of branch predictions from the TAGE update buffer 174, and also notifies the instruction fetch address generator 101 of the cancellation of the inhibition of instruction fetching. In this way, when the update determination circuit 172 determines to update the TAGE table, it inhibits the control unit 175 from reading information from the TAGE update buffer 174, which is a temporary storage unit.

[0066] As described above, when the update determination circuit 172 is writing to the update TAGE table RAM 173 for updating the TAGE table, the control unit 175 does not notify the update determination circuit 172 of branch prediction completion information. Furthermore, the update determination circuit 172 suppresses reading from the TAGE update buffer 174 when updating the update TAGE table. This double measure allows the update determination circuit 172 to prioritize writing to the update TAGE table RAM 173 for updating over reading from the update TAGE table RAM 173 for update determination. Furthermore, when updating the prediction TAGE table, the update determination circuit 172 suppresses instruction fetching and prioritizes writing due to the TAGE table update. Therefore, both the prediction TAGE table RAM 141 and the update TAGE table RAM 173 can use RAMs that are 1 read-1 write and do not support simultaneous read-write execution.

[0067] 4 is a flowchart of the process of notifying completion information of a completed branch instruction. Next, the flow of the process of notifying completion information of a completed branch instruction by the control unit 175 will be described with reference to FIG.

[0068] The control unit 175 acquires a completion report and completion information for the completed branch instruction from the RSBR 140 (step S1).

[0069] Next, the control unit 175 creates an entry for the branch instruction for which the completion report has been received in the TAGE update buffer 174 (step S2). The control unit 175 registers the completion information of the branch instruction for which the completion report has been received, etc., in the created entry.

[0070] Thereafter, the control unit 175 reads the completion information of the branch instructions from the TAGE update buffer 174 in the order in which they were stored (step S3).

[0071] Next, the control unit 175 determines whether or not the update determination circuit 172 is writing an update to the update TAGE table RAM 173 at the timing when the branch instruction is read out. As a result, the control unit 175 determines whether or not there is a collision between reading and writing to the update TAGE table RAM 173 (step S4).

[0072] If there is a collision between reading and writing to the update TAGE table RAM 173 (step S4: No), the control unit 175 does not notify the update determination circuit 172 of the completion information of the branch instruction read from the TAGE update buffer 174. Then, the control unit 175 cancels the reading of the information of the branch instruction from the TAGE update buffer 174 without updating the out-pointer in the TAGE update buffer 174 (step S5). After that, the control unit 175 returns to step S3.

[0073] On the other hand, if there is no collision between reading and writing to the update TAGE table RAM 173 (step S4: Yes), the control unit 175 notifies the update determination circuit 172 of the completion information of the branch instruction read from the TAGE update buffer 174 (step S6).

[0074] 5 is a flowchart of the TAGE table update process. Next, the flow of the TAGE table update process by the update determination circuit 172 will be described with reference to FIG.

[0075] The update determination circuit 172 receives a notification of the completion information of the branch instruction read from the TAGE update buffer 174 by the control unit 175 (step S11).

[0076] The update determination circuit 172 reads the update TAGE table from the update TAGE table RAM 173 (step S12).

[0077] Next, the update determination circuit 172 determines whether to update the TAGE table using the information in the update TAGE table and the completion information of the branch instruction (step S13). If the TAGE table is not to be updated (step S13: No), the update determination circuit 172 ends the TAGE table update process.

[0078] On the other hand, if the TAGE table is to be updated (step S13: Yes), the update determination circuit 172 inhibits the control unit 175 from reading out a branch instruction from the TAGE update buffer 174 (step S14).

[0079] Next, the update determination circuit 172 inhibits the instruction fetch address generator 101 from fetching an instruction (step S15).

[0080] Thereafter, the update determination circuit 172 executes updates to both the prediction TAGE table and the update TAGE table (step S16).

[0081] As described above, in the CPU 10 according to this embodiment, the prediction TAGE table RAM 171 is arranged near the instruction fetch mechanism, and the update TAGE table RAM 173 is arranged near the mechanism that completes branch instructions. When a conflict occurs between reading and writing to the update TAGE table RAM 173 by the update determination circuit 172, the CPU 10 prioritizes writing. Furthermore, when updating the update TAGE table, the update determination circuit 172 inhibits reading from the TAGE update buffer 174. Furthermore, when updating the prediction TAGE table, the update determination circuit 172 inhibits instruction fetching, and prioritizes writing to the prediction TAGE table RAM 171 due to the TAGE table update.

[0082] As a result, the prediction TAGE table RAM 141 and the update TAGE table RAM 173 are read separately in one system, and neither need support two-system reads. Furthermore, neither the prediction TAGE table RAM 141 nor the update TAGE table RAM 173 are read and written simultaneously. Therefore, both the prediction TAGE table RAM 141 and the update TAGE table RAM 173 can use RAMs that are 1 read-1 write and do not support simultaneous read-write. This allows the RAM area to be reduced, minimizing the circuit scale, and shortening the wiring length during prediction, thereby shortening the latency of prediction. [Explanation of symbols]

[0083] 1 server 2 External device 10 CPU 11. Memory 12 Interconnect Control Section 101 Instruction Fetch Address Generator 102 Primary instruction cache 103 Secondary instruction cache 104 Instruction Buffer 105 Instruction Decoder 106 Register Renaming 110 RSA 111 Operand Address Generator 112 Level 1 Data Cache 120 RSE 121 Arithmetic unit 122 fixed-point update buffers 123 fixed-point registers 130 RSF 131 Arithmetic unit 132 floating point update buffers 133 floating-point registers 140 RSBR 150 CSE 160 Program Counter 170 Branch Prediction Mechanism 171 Prediction TAGE table RAM 172 Update judgment circuit 173 TAGE table RAM for updating 174 TAGE update buffer 175 Control Unit

Claims

1. a pipeline that fetches and executes instructions; a branch instruction processing unit that determines whether a branch has been taken due to a predetermined branch instruction in the execution of an instruction in the pipeline, detects a branch prediction error, and completes the predetermined branch instruction; a first storage unit for storing a first table in which information relating to a branch instruction is registered and which is used for branch prediction for the fetch; a second storage unit for storing a second table in which information related to branch instructions similar to that in the first table is registered; an update determination circuit that, when no writing for update has been performed on the second table, receives notification of completion information of the predetermined branch instruction from the branch instruction processing unit, obtains information about the predetermined branch instruction from the second table, determines whether or not to execute update, and updates the first table and the second table when it is determined that update is to be executed; A processor comprising:

2. receiving a notification of the predetermined branch instruction from the branch instruction processing unit, and storing completion information of the predetermined branch instruction in a temporary storage unit; reading completion information of the predetermined branch instruction from the temporary storage unit; determining whether or not an update write has been performed on the second table; a control unit that notifies the update determination circuit of completion information of the predetermined branch instruction when no writing for updating has been performed on the second table; The processor of claim 1 further comprising:

3. 3. The processor according to claim 2, wherein the update determination circuit, when determining that an update is to be performed, inhibits the control unit from reading information from the temporary storage unit.

4. the first storage unit is arranged near an instruction fetch mechanism of the pipeline; The second storage unit is disposed near the branch instruction processing unit. The processor of claim 1 .

5. An information processing device having a processor and a main storage device, The processor: a pipeline that fetches and executes instructions; a branch instruction processing unit that determines whether a branch has been taken due to a predetermined branch instruction in the execution of an instruction in the pipeline, detects a branch prediction error, and completes the predetermined branch instruction; a first storage unit for storing a first table in which information relating to a branch instruction is registered and which is used for branch prediction for the fetch; a second storage unit for storing a second table in which information related to branch instructions similar to that in the first table is registered; an update determination circuit that, when no writing for updating has been performed to the second table, receives notification of completion information of the predetermined branch instruction from the branch instruction processing unit, obtains information about the predetermined branch instruction from the second table, determines whether or not to perform an update, and updates the first table and the second table when it is determined that the update is to be performed.

1. An information processing device comprising:

6. a pipeline that fetches and executes instructions; a branch instruction processing unit that determines whether a branch has been taken due to a predetermined branch instruction in the execution of an instruction in the pipeline, detects a branch prediction error, and completes the predetermined branch instruction; A first storage section and a second storage section A method for controlling a processor having: the processor when no writing for updating has been performed on the second table stored in the second storage unit and in which information related to the branch instruction is registered, receiving a notification of completion information of the predetermined branch instruction, and determining whether or not to obtain information related to the predetermined branch instruction from the second table and perform an update; When it is determined that the update is to be performed, the first table, which is stored in the first storage unit, in which information about the branch instruction similar to that in the second table is registered, and which is used for branch prediction for the fetch, and the second table are updated. A method for controlling a processor, characterized by executing a process.

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