Photoelectric conversion device, photoelectric conversion system, and movable body

Abstract

To achieve both reduction of FD parasitic capacitance and the degree of freedom in wiring layout.SOLUTION: A photoelectric conversion device comprises: a semiconductor substrate having a first photoelectric conversion part and a second photoelectric conversion part, a first floating diffusion layer to which electric charges generated in the first photoelectric conversion part are transferred, and a second floating diffusion layer to which electric charges generated in the second photoelectric conversion part are transferred; and a plurality of wiring layers laminated on a surface of the semiconductor substrate. The photoelectric conversion device has first wiring connecting the first floating diffusion layer and the second floating diffusion layer, at a height between the height of the surface and a height at which the wiring layer closest to the semiconductor substrate, of the plurality of wiring layers, is provided.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system, and a moving object. [Background technology]

[0002] There is a photoelectric conversion device that transfers charges photoelectrically converted by a photodiode to a floating diffusion and amplifies the signal as a voltage signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 199588 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the parasitic capacitance of the floating diffusion is suppressed by using low-profile wiring from the floating diffusion to the gate of the source follower transistor or the source of the reset transistor. However, no suitable configuration is considered for the layout of the wiring connecting the floating diffusions together. [Means for solving the problem]

[0005] A photoelectric conversion device comprising: a semiconductor substrate having a first photoelectric conversion unit, a second photoelectric conversion unit, a first floating diffusion layer to which charges generated in the first photoelectric conversion unit are transferred, and a second floating diffusion layer to which charges generated in the second photoelectric conversion unit are transferred; and a plurality of wiring layers stacked on a surface of the semiconductor substrate, the height of which is between the height of the surface and the height of a wiring layer of the plurality of wiring layers that is closest to the semiconductor substrate, and a first wiring that connects the first floating diffusion layer and the second floating diffusion layer. [Effects of the Invention]

[0006] To improve the freedom of wiring layout while suppressing the parasitic capacitance of FD. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram illustrating a schematic configuration of a photoelectric conversion device. [Figure 2] FIG. 2 is an equivalent circuit diagram of a pixel according to the first embodiment. [Figure 3] FIG. 2 is a plan view of a pixel according to the first embodiment. [Figure 4] FIG. 2 is a cross-sectional view of a pixel according to the first embodiment. [Figure 5] FIG. 2 is a cross-sectional view of a pixel according to the first embodiment. [Figure 6] FIG. 10 is a plan view of a pixel according to a second embodiment. [Figure 7] FIG. 10 is a plan view of a pixel according to a third embodiment. [Figure 8] FIG. 10 is a plan view of a pixel according to a fourth embodiment. [Figure 9] FIG. 10 is a plan view of a pixel according to a fourth embodiment. [Figure 10] FIG. 11 is an equivalent circuit diagram of a pixel according to a fifth embodiment. [Figure 11] FIG. 10 is a plan view of a pixel according to a fifth embodiment. [Figure 12] FIG. 10 is a plan view of a pixel according to a fifth embodiment. [Figure 13] FIG. 13 is an equivalent circuit diagram of a pixel according to a sixth embodiment. [Figure 14] FIG. 13 is a plan view of a pixel according to a seventh embodiment. [Figure 15] FIG. 13 is a cross-sectional view of a pixel according to a seventh embodiment. [Figure 16] FIG. 13 is a plan view of a pixel according to an eighth embodiment. [Figure 17] FIG. 13 is a plan view of a pixel according to a ninth embodiment. [Figure 18] FIG. 20 is a functional block diagram of a photoelectric conversion system according to a tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0010] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a view of a cross section perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0011] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0012] (First embodiment) A first embodiment of the present invention will be described with reference to FIGS.

[0013] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a pixel array 101, a vertical scanning circuit 102, a column amplifier circuit 103, a horizontal scanning circuit 104, an output circuit 105, and a control circuit 106. The photoelectric conversion device is a semiconductor device formed on a semiconductor substrate such as a silicon substrate, and is a CMOS image sensor in this embodiment.

[0014] The pixel array 101 includes a plurality of pixels 107 arranged two-dimensionally on a semiconductor substrate, including a plurality of rows and a plurality of columns.

[0015] The vertical scanning circuit 102 supplies a plurality of control signals for controlling a plurality of transistors included in the pixels 107 to be on (conductive state) or off (non-conductive state). A column signal line 108 is provided for each column of the pixels 107, and signals from the pixels 107 are read out to the column signal line 108 for each column.

[0016] The column amplifier circuit 103 amplifies the pixel signals output to the column signal lines 108, and performs processes such as correlated double sampling based on the signals at the time of resetting the pixels 107 and the signals at the time of photoelectric conversion.

[0017] The horizontal scanning circuit 104 supplies a switch connected to the amplifier of the column amplifier circuit 103 and a control signal for controlling the switch to be on or off.

[0018] The output circuit 105 includes a buffer amplifier, a differential amplifier, etc., and outputs the pixel signals from the column amplifier circuit 103 to a signal processing unit outside the photoelectric conversion device.

[0019] The control circuit 106 controls the vertical scanning circuit 102 , the column amplifier circuit 103 , and the horizontal scanning circuit 104 .

[0020] Furthermore, an AD conversion unit may be provided so that the photoelectric conversion device outputs a digital pixel signal. Various elements constituting the photoelectric conversion device may be arranged separately on multiple semiconductor substrates. For example, the pixel array 101 may be arranged on a first substrate, and other elements may be arranged on a second substrate, with the first substrate and the second substrate being stacked.

[0021] 2 is an equivalent circuit diagram for two pixels 107. One pixel 107 of the photoelectric conversion device according to this embodiment has two photodiodes (PD), and the two pixels share one floating diffusion (FD), and the four PDs 201 of the two pixels share the FD 203.

[0022] To one FD203, a first photoelectric conversion unit PD201a is connected via a first transfer transistor TX202a. A second photoelectric conversion unit PD201b is connected to the FD203 via a second transfer transistor TX202b. A third photoelectric conversion unit PD201c is connected to the FD203 via a third transfer transistor TX202c. A fourth photoelectric conversion unit PD202d is connected to the FD203 via a fourth transfer transistor TX202d.

[0023] The FD 203 is connected to the source of a dual conversion gain transistor (DCG) 204, and the drain of the DCG 204 is connected to the source of a reset transistor (RES) 205. The drain of the RES 205 is connected to a power supply. The FD 203 is also connected to the gate of a source follower transistor (SF) 206, and the source of the SF 206 is connected to the drain of a select transistor (SEL) 207. The source of the SEL 207 is connected to a column signal line 108.

[0024] Each of the PDs 201a to 201d (hereinafter also referred to as PD201) generates an electric charge according to the amount of incident light. The generated electric charge is transferred to the FD203 by turning on the TXs 202a to 202d. The FD203 temporarily holds the electric charge transferred from the PD201 and converts the signal charge into a voltage signal. At this time, the gain of the charge-voltage conversion is determined by the capacitance of the FD203. The capacitance value of the FD203 can be changed by switching on and off the DCG204 connected to the FD203, and the gain of the charge-voltage conversion in the FD203 can be controlled.

[0025] Here, the source of the DCG 204 is connected to the FD 203, but a configuration in which the DCG 204 is not present and the source of the RES 205 is connected to the FD 203 may also be used. The RES 205 is used to discharge the charge accumulated in the FD 203 to the power supply and reset the charge accumulated in the FD 203. The gate potential of the SF 206 changes due to the charge accumulated in the FD 203, and the source potential of the SF 206 fluctuates accordingly. By sequentially outputting the source potential of the SF 206 to the column signal line 108 via the SEL 207, it is possible to output the light incident on the PD 201 as an electrical signal.

[0026] 3A and 3B are plan views of a pixel according to this embodiment, in which the FD wiring 210 and pixel transistors are also arranged, and FIG. 3B shows only the semiconductor layer.

[0027] 3 shows four pixels 107 arranged in two rows and two columns. As shown in FIG. 2, each pixel 107 has a DCG 204, a RES 205, an SF 206, and a SEL 207. One microlens 220 is arranged for each pixel 107, and each pixel 107 has two PDs 201. In other words, two PDs 201 are arranged for one microlens 220. By arranging multiple PDs 201 for one microlens 220 in this way, it is possible to obtain not only an imaging signal but also a phase difference detection signal for autofocus.

[0028] As shown in Figure 3(b), the two PDs 201 arranged in one pixel are formed in one semiconductor layer connected at the center. The PD 201 on the left side of the first pixel 107 in the upper left of Figure 3(b) is PD201a, the PD 201 on the right side is PD201b, and the PD 201 on the left side of the second pixel 107 in the lower left is PD201c, and the PD 201 on the right side is PD201d. In other words, two pixels lined up in the vertical direction (column direction) in Figure 3(b) are two pixels that share a common FD203 shown in the circuit diagram of Figure 2.

[0029] As shown in FIG. 3(a), PD201a is provided with a gate for TX202a, and PD201b is provided with a gate for TX202b. PD201c is provided with a gate for TX202c, and PD201d is provided with a gate for TX202d. Furthermore, the pixel 107 at the top left of FIG. 3(a) is provided with gates for DCG204 and RES205, and the pixel 107 at the bottom left of FIG. 3(a) is provided with gates for SF206 and SEL207. Each PD201 is the source of TX202a, TX202b, TX202c, and TX202d. The drain of TX202a is the first floating diffusion layer, and the drain of TX202b is the second floating diffusion layer. The drain of TX202c is the third floating diffusion layer, and the drain of TX202d is the fourth floating diffusion layer. These floating diffusion layers are all connected to a single FD wiring 210 dedicated to the floating diffusion layers, and are connected to the gate of the SF 206 and the source of the DCG 204 as one FD 203 by the FD wiring 210.

[0030] The cross sections taken along dashed lines AB and AC in FIG. 3 are shown in FIGS. 4 and 5, respectively.

[0031] 4 is a cross-sectional view of a pixel according to this embodiment taken along the line AB. Multiple wiring layers of a wiring structure 1000 are stacked on the surface of a semiconductor substrate 2000. The wiring structure 1000 has, from the side closest to the semiconductor substrate 2000, a first wiring layer 230, a second wiring layer 240, and a third wiring layer 250. Although three wiring layers are shown in FIG. 4, the number of wiring layers is not limited to this and may be more or less than three.

[0032] In this embodiment, the FD wiring 210 is disposed at a height between the height of the surface of the semiconductor substrate 2000 and the height of the first wiring layer 230, which is the wiring layer closest to the semiconductor substrate 2000. Here, the height of the first wiring layer 230 refers to the height (H230) of the surface of the first wiring layer facing the semiconductor substrate 2000. Similarly, for other wiring layers, the height of the surface facing the semiconductor substrate 2000 is treated as the height of that wiring layer.

[0033] Furthermore, the FD wiring 210 is disposed at a height between the height of the first wiring layer 230 and the height (H202) of the gates of transistors such as TX202a and TX202c. The FD wiring 210 and FD203 are connected by contact metal 206. The FD wiring 210 is lower in height than the first wiring layer 230 and the second wiring layer 240. This reduces the parasitic capacitance of the wiring. Reducing the regulated capacitance of the FD wiring 210 leads to the suppression of RTS noise (random telegraph signal noise). Specifically, the height from the semiconductor substrate 2000 to the surface (H230) of the first wiring layer 230 facing the semiconductor substrate 2000 is 0.6 μm, and the thickness of the first wiring layer 230 is 0.2 μm. The height from the semiconductor substrate 2000 to the surface (H240) of the second wiring layer 240 facing the semiconductor substrate 2000 is 1.2 μm, and the thickness of the second wiring layer 240 is 0.2 μm. The height from the semiconductor substrate 2000 to the gate upper surface (H202) of the TX202 is 0.2 μm. On the other hand, the height from the semiconductor substrate 2000 to the surface (H210) of the FD wiring facing the semiconductor substrate 2000 is 0.3 μm, and the thickness of the FD wiring is 0.05 μm.

[0034] The FD wiring can be formed of, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), copper (Cu), etc. The FD wiring may be configured with a layered structure of titanium and titanium nitride (Ti / TiN / Ti).

[0035] Furthermore, the PD 201a and PD 201b, and each PD 201 and its adjacent pixel 107, are electrically isolated by inter-pixel isolation 301. Similarly, the floating diffusion layers 203 are also isolated by inter-pixel isolation 301 to prevent signal mixing. Isolation between pixels may be PN isolation or dielectric isolation. That is, the inter-pixel isolation may be a semiconductor layer of a different conductivity type from the semiconductor layer constituting the PD 201, or may be a trench structure formed in the semiconductor layer. The trench structure may or may not be filled with metal or insulator. In the example shown in FIG. 4, the inter-pixel isolation 301 is a DTI (Deep Trench Isolation) that penetrates the semiconductor substrate 2000.

[0036] 5 is a cross-sectional view of a pixel according to this embodiment taken along line AC. An FD wiring 210 connected to the FD 203 is connected to the gate of the SF 206 via a contact metal 260.

[0037] The wiring connecting the FDs 203 is arranged to connect multiple PDs 201 included in a single pixel or PDs 201 included in multiple pixels, so from a layout perspective, it is difficult to route it on the same layer as other wiring. In addition, capacitive coupling with other wiring can cause noise. Therefore, it is desirable to arrange the FD wiring 210 on a wiring layer separate from other wiring.

[0038] In the photoelectric conversion device according to this embodiment, the FD wiring 210 is arranged at a height between the height of the first wiring layer 230 and the height of the transistor gate. This reduces layout constraints on the elements and wiring that make up the pixel, allowing for a more space-saving arrangement and an arrangement that avoids capacitive coupling. This also has the effect of suppressing noise caused by wiring capacitance.

[0039] (Second embodiment) A photoelectric conversion device according to the second embodiment will be described with reference to FIG. 6. The differences from the first embodiment will be mainly described, and common explanations will be omitted where appropriate. In the photoelectric conversion device according to this embodiment, the arrangement direction of two PDs 201 arranged in a pixel 107 differs from that of the photoelectric conversion device according to the first embodiment. In the first embodiment, two PDs 201 were arranged in the row direction for one pixel 107, but in this example, two PDs 201 are arranged in the vertical direction for one pixel.

[0040] In the photoelectric conversion device according to the first embodiment, autofocusing is easy when the subject has vertical stripe contrast, but autofocusing is difficult when the subject has horizontal stripe contrast. The arrangement of the PD201 in the photoelectric conversion device according to this embodiment is such that autofocusing is easier when the subject has horizontal stripe contrast.

[0041] In this way, it is possible to achieve a configuration that makes it easier to autofocus on a subject that has contrast in any direction by changing the arrangement direction (alignment direction) of the two PDs 201 relative to the microlens 220. Here, the case where the PDs 201 are divided into upper and lower sections is described, but the PDs 201 may also be arranged at an angle, such as diagonally.

[0042] (Third embodiment) A photoelectric conversion device according to the third embodiment will be described with reference to Fig. 7. The differences from the first embodiment will be mainly described, and common explanations will be omitted as appropriate. This embodiment differs from the first embodiment in that two types of pixels 107, each having two PDs 201 arranged in different directions, are mixed in the pixel array 101.

[0043] By arranging the pixel 107 in which the arrangement directions of the two PDs 201 are changed in the pixel array 101 in this way, it becomes possible to perform highly accurate autofocusing on a wider variety of subject patterns.

[0044] (Fourth embodiment) A photoelectric conversion device according to the fourth embodiment will be described with reference to Figures 8 and 9. The photoelectric conversion device according to this embodiment differs from the first embodiment in that the elements included in the two pixels 107 that share the FD 203 are arranged in a mirror symmetrical manner with the FD 203 in between. With this arrangement, the FD wiring 210 can be made shorter than in the configuration described in the first embodiment, and the parasitic capacitance of the FD 203 can be further reduced.

[0045] Figure 9 shows another modification of the configuration shown in Figure 8. Even in the case of a mirror arrangement as shown in Figure 9, the arrangement direction of the two PDs 201 in a pixel 107 may be vertical. Furthermore, two types of pixels 107 in which the arrangement directions of the two PDs differ from each other, such as the pixels in Figure 8 and the pixels in Figure 9, may be mixed in the pixel array. In this way, by differing the arrangement directions of the two PDs 201 included in one pixel relative to the pixel array direction, a configuration is achieved that makes it easier to autofocus on a subject that has contrast in any direction.

[0046] (Fifth embodiment) A photoelectric conversion device according to the fifth embodiment will be described with reference to Figures 10, 11, and 12. In this embodiment, four pixels share one FD 203, and eight PDs 201 of these four pixels share the FD 203. Furthermore, this embodiment differs from the first embodiment in that the FD 203 is connected in parallel to multiple SFs 206.

[0047] Reducing the size of the PD 201 for purposes such as pixel miniaturization results in a worsening SNR. The SNR can be improved by sharing the FD 203 among multiple PDs 201 and collectively converting the charges generated by each PD into a voltage signal. As the number of PDs sharing one FD 203 increases, the length of the FD wiring 210 also increases, raising concerns that RTS noise may worsen due to the parasitic capacitance of the wiring. In this embodiment, the FD wiring 210 is arranged at a height between the height of the first wiring layer 230 and the height of the transistor gate, thereby improving layout efficiency and suppressing noise caused by capacitive coupling.

[0048] 10 shows an example of an equivalent circuit diagram of this embodiment. PD201a, which is a first photoelectric conversion unit, is connected to one FD203 via TX202a, which is a first transfer transistor. PD201b, which is a second photoelectric conversion unit, is connected to FD203 via TX202b, which is a second transfer transistor. PD201c, which is a third photoelectric conversion unit, is connected to FD203 via TX202c, which is a third transfer transistor. PD202d, which is a fourth photoelectric conversion unit, is connected to FD203 via TX202d, which is a fourth transfer transistor. PD202e, which is a fifth photoelectric conversion unit, is connected to FD203 via TX202e, which is a fifth transfer transistor. PD202f, which is a sixth photoelectric conversion unit, is connected to FD203 via TX202f, which is a sixth transfer transistor. PD202g, which is a seventh photoelectric conversion unit, is connected to FD203 via TX202g, which is a seventh transfer transistor. The eighth photoelectric conversion unit PD202h is connected to the FD203 via the eighth transfer transistor TX202h.

[0049] DCG204a, DCG204b, and DCG204c are connected in series between FD203 and RES205. The drain of RES205 and the gate of DCG204c are connected to the power supply. That is, DCG204c is always in a conductive state. In addition, FD203 is connected to the gates of SF206a, SF206b, and SF206c, and the source of each SF206 is connected to the column signal line 108 via SEL207.

[0050] As shown in the plan view of Figure 11, four pixels 107 share the FD 203 via the FD wiring 210 connected to the source of the TX 202, and all PDs 201 of these four pixels share the FD 203. In Figure 11, the pixels 107 including PDs 201c and 201d are provided with a RES 205 and an SF 206a, and the pixels 107 including PDs 201e and 201f are provided with a DCG 204a and a DCG 204b. Furthermore, the pixels including PDs 201a and 201b are provided with a DCG 204c, and the pixels 107 including PDs 201g and 201h are provided with an SF 206b and an SF 206c. The combination of transistors arranged in each pixel 107 is not limited to this; it is sufficient that the necessary transistors are arranged in each of the four pixels 107.

[0051] 12, the arrangement direction of the two PDs 201 in each pixel 107 may be the column direction of the pixel array. Also, multiple types of pixels in which the arrangement directions of the two PDs 201 differ from each other may be mixed in the pixel array. By incorporating multiple types of pixels 107 in which the arrangement directions of the two PDs 201 differ from each other, it is possible to realize a photoelectric conversion device that can easily perform autofocus on a subject that has contrast in any direction.

[0052] As shown in this embodiment, RTS noise can be suppressed by connecting the FD 203 and the FD wiring 210 in parallel to the gates of multiple SFs 206. Furthermore, configuring the DCG 204 with multiple transistors allows the conversion gain to be switched in multiple stages. This allows for an improvement in the signal-to-noise ratio and an expansion of the dynamic range.

[0053] (Sixth embodiment) A photoelectric conversion device according to the sixth embodiment will be described with reference to Fig. 13. In this embodiment, the FDs 203 of the pixels 107 arranged in different pixel rows in the pixel array are connected to each other by inter-row FD connection wiring 401.

[0054] 13 shows an example of an equivalent circuit diagram of this embodiment. In pixel 107_1, a first photoelectric conversion unit PD201a_1 is connected to one FD203_1 via a first transfer transistor TX202a_1. A second photoelectric conversion unit PD201b_1 is connected to FD203_1 via a second transfer transistor TX202b_1. A third photoelectric conversion unit PD201c_1 is connected to FD203_1 via a third transfer transistor TX202c_1. A fourth photoelectric conversion unit PD202d_1 is connected to FD203_1 via a fourth transfer transistor TX202d_1.

[0055] The DCG 204_1 is connected in series between the FD 203_1 and the RES 205_1. The drain of the RES 205_1 is connected to the power supply. The FD 203_1 is connected to the gate of the SF 206_1, and the source of the SF 206_1 is connected to the column signal line 108_1 via the SEL 207_1.

[0056] Similarly, in pixel 107_2, a first photoelectric conversion unit PD201a_2 is connected to one FD203_2 via a first transfer transistor TX202a_2. A second photoelectric conversion unit PD201b_2 is connected to FD203_2 via a second transfer transistor TX202b_2. A third photoelectric conversion unit PD201c_2 is connected to FD203_2 via a third transfer transistor TX202c_2. A fourth photoelectric conversion unit PD202d_2 is connected to FD203_2 via a fourth transfer transistor TX202d_2.

[0057] The DCG 204_2 is connected in series between the FD 203_2 and the RES 205_2. The drain of the RES 205_2 is connected to the power supply. The FD 203_2 is connected to the gate of the SF 206_2, and the source of the SF 206_2 is connected to the column signal line 108_2 via the SEL 207_2.

[0058] 13, the node between RES205_1 and DCG204_1 and the node between RES205_2 and DCG204_2 are connected by an inter-row FD connection wiring 401. Connecting the drains of DCG204 to each other by the inter-row FD connection wiring 401 makes it possible to add a larger FD capacitance. This makes it possible to hold a larger signal charge in FD203, thereby expanding the dynamic range.

[0059] When the inter-row FD connection wiring 401 is arranged, the number of wirings increases, and therefore the wiring layout is subject to restrictions compared to when the inter-row FD connection wiring 401 is not included. However, by arranging the FD wiring 210 at a height between the height at which the first wiring layer 230 is provided and the height at which the transistor gates are provided, the FD wiring 210 is not subject to the layout restrictions imposed by the inter-row FD connection wiring 401. The inter-row FD connection wiring 401 may be provided in the same layer as the FD wiring 210. In other words, the inter-row FD connection wiring 401 may be arranged between the height at which the first wiring layer 230 is provided and the height at which the transistor gates are provided.

[0060] Alternatively, the FD wiring 210 corresponding to a certain PD 201 may be provided between the height of the first wiring layer 230 and the height at which the transistor gate is provided, and the FD wiring 210 corresponding to another PD 201 may be provided at the height of the first wiring layer 230. Similarly, the inter-row FD connection wiring 401 corresponding to a certain pixel 107 may be provided between the height of the first wiring layer 230 and the height at which the transistor gate is provided, and the inter-row FD connection wiring 401 corresponding to another pixel 107 may be provided at the height of the first wiring layer 230. In either case, the effect of reducing the layout constraints on the arrangement of each wiring can be obtained.

[0061] In this embodiment, a photoelectric conversion device having inter-row FD connection wiring 401 has been described, but the same applies to a configuration in which the FDs 203 of pixels 107 arranged in different pixel columns in a pixel array are connected to each other by inter-column FD wiring 402.

[0062] (Seventh embodiment) The seventh embodiment will be described with reference to Figures 14 and 15. In the photoelectric conversion device according to this embodiment, a shield wiring 501 is arranged around the FD wiring 210 for the purpose of suppressing noise.

[0063] Fig. 14 shows a plan view of four pixels of a photoelectric conversion device according to this embodiment. In the example shown in Fig. 14, two pixels aligned in the column direction share one FD 203, and FD wiring 210 is provided so that four PDs 201 share the FD 203. A shield wiring 501 is provided on the first wiring layer 230 side of the FD wiring 210 so as to overlap the FD wiring 210 in a plan view and cover the FD wiring 210. For convenience, its outline is shown by a dashed line in Fig. 14.

[0064] The FD wiring 210 is subject to capacitive coupling with surrounding wiring, and is therefore affected by potential fluctuations in the surrounding wiring. This causes noise to be introduced into the voltage signal corresponding to the signal charge that should be output. For this reason, in this embodiment, a shield wiring 501 is provided to suppress noise caused by the capacitive coupling of the FD wiring 210. This makes it possible to suppress the effect of potential fluctuations in other wiring on the FD wiring 210, thereby suppressing RTS noise.

[0065] 15 shows a cross-sectional view of the photoelectric conversion device according to this embodiment, taken along the line AB in FIG.

[0066] The shield wiring 501 is wiring provided at the height of the first wiring layer 230, and is arranged at a position where at least a part of it overlaps with the FD wiring 210 in a plan view. In particular, it is arranged between the FD wiring 210 and wiring such as the column signal line 108 provided in the first wiring layer 230. In FIG. 15 , the shield wiring 501 is arranged in the same layer as the first wiring layer 230, but the shield wiring 501 may be arranged in a layer such as the second wiring layer 240 or the third wiring layer 250 depending on the wiring layer in which the wiring to be shielded is arranged.

[0067] Furthermore, when this embodiment is applied to the configuration shown in the sixth embodiment, for example, a second shield wiring 501 provided at the same height as the first FD wiring 210_1 may be arranged between the first FD wiring 210_1 and the second FD wiring 210_2. In this case, the shield wiring 501 overlapping the first FD wiring 210_1 is defined as the first shield wiring.

[0068] Leaving the shield wiring 501 in a floating state may actually increase noise. However, applying the source potential of SF206 to the shield wiring 501 makes it possible to effectively suppress noise. Therefore, it is desirable that the shield wiring 501 be electrically connected to the source of SF206.

[0069] (Eighth embodiment) The eighth embodiment will be described with reference to Fig. 16. The photoelectric conversion device according to this embodiment has a configuration in which FD wirings 210 that connect FDs 203 of a plurality of pixels 107 to each other are connected to each other by wiring in a first wiring layer 230.

[0070] 16, the two pixels on the left side have their FDs 203 connected to each other by an FD wiring 210_1. Similarly, the two pixels on the right side have their FDs 203 connected to each other by an FD wiring 210_2. In this embodiment, the FD wiring 210_1 and the FD wiring 210_2 are further connected to each other by an FD connection wiring 280. The FD connection wiring 280 is a wiring provided in the first wiring layer 230.

[0071] When FDs 203 are connected to each other using a single wiring layer, the wiring becomes more complex as the number of PDs 201 to which the FDs 203 are connected increases, reducing the degree of freedom in layout. Connecting the FDs 203 to each other using the FD wiring 210 and wiring arranged in the first wiring layer 230 can improve the degree of freedom in the layout of wiring for FD sharing. Note that a switch may be provided between the FD wiring 210 and the FD connection wiring 280 to control the number of pixels 107 that share the FD 203. Here, any of the transistors shown in FIG. 16 may be used as the switch.

[0072] (Ninth embodiment) The ninth embodiment will be described with reference to FIG. 17. In this embodiment, one FD 203 is configured as a diffusion layer and is shared by multiple pixels 107. Of the four pixels 107 shown in FIG. 17, in the upper left pixel 107, a first floating diffusion layer FD 203_1 is connected to the gates of TX 202a and TX 202b. That is, in the configuration of this embodiment, the FD connected from PD 201a via TX 202a and the FD connected from PD 201b via TX 202b are not separated by DTI. Similarly, in the lower left pixel 107, a second floating diffusion layer FD 203_2 is connected to the gates of TX 202c and TX 202d. These FD 203_1 and FD 203_2 are connected by FD wiring 210 and treated as one FD 203. In other words, in the configuration of FIG. 8, one PD 201 is connected to the FD wiring 210 via one contact metal, whereas in the configuration of FIG. 17, two PDs 201 are connected to the FD wiring 210 via one contact metal.

[0073] In this way, by using a portion of the FD 203 shared by multiple pixels 107 as a diffusion layer, it is possible to shorten the wiring length of the FD wiring 210 connecting the FDs 203 to each other, thereby reducing the parasitic capacitance of the FD 203. Here, the wiring length includes not only the length of the wiring provided in the wiring layer but also the length of the contacts connecting the wiring layers.

[0074] In addition, in the present embodiment, an example has been shown in which the FD 203_1 connected to one of the two PDs 201 and the FD 203_2 connected to the other are connected to each other in each pixel 107, but for example, four FDs 203 connected to four PDs 201 may be connected to each other. The number of the plurality of PDs 201 to which the FDs 203 formed by the diffusion layer are connected and the number of the plurality of pixels 107 are not limited to two.

[0075] (Tenth embodiment) The tenth embodiment can be applied to any of the first to ninth embodiments. FIG. 18(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 of this embodiment. The photoelectric conversion device of each of the above-described embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be described in detail. In addition to the semiconductor device 910, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0076] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0077] The portion including at least one of the processing device 960, the display device 970, the storage device 980, and the mechanical device 990 is a processing unit having the function of processing the signal from the semiconductor device 930 and generating an image.

[0078] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0079] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0080] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0081] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0082] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0083] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0084] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 18(b) and 18(c).

[0085] FIG. 18(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (image capture device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0086] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0087] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear.

[0088] 18(c) shows a photoelectric conversion system when capturing an image of the area ahead of the vehicle (image capturing range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0089] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0090] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0091] The disclosure of this embodiment includes the following configuration.

[0092] (Configuration 1) a first photoelectric conversion unit and a second photoelectric conversion unit; a first floating diffusion layer to which charges generated in the first photoelectric conversion portion are transferred; a semiconductor substrate having a second floating diffusion layer to which charges generated in the second photoelectric conversion portion are transferred; a plurality of wiring layers stacked on the surface of the semiconductor substrate; A photoelectric conversion device having a first wiring that connects the first floating diffusion layer and the second floating diffusion layer at a height between the height of the surface and the height of a wiring layer among the plurality of wiring layers that is closest to the semiconductor substrate.

[0093] (Configuration 2) the semiconductor substrate has a plurality of pixels including a first pixel and a second pixel; 2. The photoelectric conversion device according to configuration 1, wherein the first pixel has the first photoelectric conversion unit, and the second pixel has the second photoelectric conversion unit.

[0094] (Configuration 3) the first pixel has a plurality of photoelectric conversion units including the first photoelectric conversion unit, 3. The photoelectric conversion device according to configuration 2, wherein the second pixel has a plurality of photoelectric conversion units including the second photoelectric conversion unit.

[0095] (Configuration 4) the semiconductor substrate includes a third photoelectric conversion unit, a fourth photoelectric conversion unit, a third floating diffusion layer to which charges generated in the third photoelectric conversion portion are transferred; 4. The photoelectric conversion device according to any one of Structures 1 to 3, further comprising: a fourth floating diffusion layer to which charges generated in the fourth photoelectric conversion section are transferred.

[0096] (Configuration 5) The photoelectric conversion device according to configuration 4, wherein the first floating diffusion layer, the second floating diffusion layer, the third floating diffusion layer, and the fourth floating diffusion layer are connected by the first wiring.

[0097] (Configuration 6) 6. The photoelectric conversion device according to any one of Structures 1 to 5, wherein the first floating diffusion layer and the second floating diffusion layer are connected to a common floating diffusion layer.

[0098] (Configuration 7) The photoelectric conversion device according to configuration 4, wherein the third floating diffusion layer and the fourth floating diffusion layer are connected to a common floating diffusion layer.

[0099] (Configuration 8) The photoelectric conversion device according to any one of structures 1 to 7, characterized in that the first floating diffusion layer and the second floating diffusion layer are connected via a wiring layer closest to the semiconductor substrate and a part of the first wiring.

[0100] (Configuration 9) The photoelectric conversion device according to configuration 4, wherein the third floating diffusion layer and the fourth floating diffusion layer are connected via a part of the wiring layer closest to the semiconductor substrate and the first wiring.

[0101] (Configuration 10) 10. The photoelectric conversion device according to any one of Structures 1 to 9, wherein the wiring layer closest to the semiconductor substrate includes a first shield wiring that overlaps the first FD wiring in a plan view.

[0102] (Configuration 11) a second wiring provided at a height between the surface and a height at which a wiring layer closest to the semiconductor substrate is provided, the second wiring connecting the third floating diffusion layer and the fourth floating diffusion layer; 5. The photoelectric conversion device according to configuration 4, further comprising a second shield wiring provided between the first wiring and the second wiring at the same height as the first wiring.

[0103] (Configuration 12) a separation portion penetrating the semiconductor substrate is provided between the first photoelectric conversion portion and the second photoelectric conversion portion; 12. The photoelectric conversion device according to any one of Structures 1 to 11, wherein the separation section separates the first floating diffusion layer and the second floating diffusion layer.

[0104] (Configuration 13) 13. The photoelectric conversion device according to any one of structures 1 to 12, further comprising a reset transistor connected to the first photoelectric conversion unit, the first wiring being connected to a source of the reset transistor.

[0105] (Configuration 14) The photoelectric conversion device according to any one of configurations 1 to 13, a processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

[0106] (Configuration 15) A moving object including the photoelectric conversion device according to any one of configurations 1 to 13, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device. [Explanation of symbols]

[0107] 201 Photoelectric conversion unit 203 Floating Diffusion Layer 210 First Wiring 220 wiring layer

Claims

1. a first photoelectric conversion unit and a second photoelectric conversion unit; a first floating diffusion layer to which charges generated in the first photoelectric conversion unit are transferred; a semiconductor substrate having a second floating diffusion layer to which charges generated in the second photoelectric conversion portion are transferred; a plurality of wiring layers stacked on the surface of the semiconductor substrate; A photoelectric conversion device having a first wiring that connects the first floating diffusion layer and the second floating diffusion layer at a height between the height of the surface and the height of a wiring layer among the plurality of wiring layers that is closest to the semiconductor substrate.

2. the semiconductor substrate has a plurality of pixels including a first pixel and a second pixel; The photoelectric conversion device according to claim 1 , wherein the first pixel has the first photoelectric conversion unit, and the second pixel has the second photoelectric conversion unit.

3. the first pixel has a plurality of photoelectric conversion units including the first photoelectric conversion unit, The photoelectric conversion device according to claim 2 , wherein the second pixel has a plurality of photoelectric conversion units including the second photoelectric conversion unit.

4. the semiconductor substrate includes a third photoelectric conversion unit, a fourth photoelectric conversion unit, a third floating diffusion layer to which charges generated in the third photoelectric conversion unit are transferred; The photoelectric conversion device according to claim 1 , further comprising: a fourth floating diffusion layer to which charges generated in the fourth photoelectric conversion portion are transferred.

5. 5. The photoelectric conversion device according to claim 4, wherein the first floating diffusion layer, the second floating diffusion layer, the third floating diffusion layer, and the fourth floating diffusion layer are connected by the first wiring.

6. 2. The photoelectric conversion device according to claim 1, wherein the first floating diffusion layer and the second floating diffusion layer are connected to a common floating diffusion layer.

7. 5. The photoelectric conversion device according to claim 4, wherein the third floating diffusion layer and the fourth floating diffusion layer are connected to a common floating diffusion layer.

8. 2. The photoelectric conversion device according to claim 1, wherein the first floating diffusion layer and the second floating diffusion layer are connected via a wiring layer closest to the semiconductor substrate and a part of the first wiring.

9. 5. The photoelectric conversion device according to claim 4, wherein the third floating diffusion layer and the fourth floating diffusion layer are connected via a part of a wiring layer closest to the semiconductor substrate and the first wiring.

10. 2. The photoelectric conversion device according to claim 1, wherein the wiring layer closest to the semiconductor substrate includes a first shield wiring that overlaps the first wiring in a plan view.

11. a second wiring provided at a height between the surface and a height at which a wiring layer closest to the semiconductor substrate is provided, the second wiring connecting the third floating diffusion layer and the fourth floating diffusion layer; 5. The photoelectric conversion device according to claim 4, further comprising a second shield wiring provided between the first wiring and the second wiring at the same height as the first wiring.

12. a separation portion penetrating the semiconductor substrate is provided between the first photoelectric conversion portion and the second photoelectric conversion portion; The photoelectric conversion device according to claim 1 , wherein the separation section separates the first floating diffusion layer and the second floating diffusion layer.

13. 2. The photoelectric conversion device according to claim 1, further comprising a reset transistor connected to the first photoelectric conversion unit, the first wiring being connected to a source of the reset transistor.

14. The photoelectric conversion device according to any one of claims 1 to 13, a processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

15. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 13, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

Images