Apparatus and method for overcurrent limiting for multi-channel digital-to-analog converters - Patents.com

Abstract

A system (100) includes a plurality of digital-to-analog converter (DAC) channels (C1-CN). Each DAC channel includes a current control circuit (150-1) that receives a start limit signal or an end limit signal. The current control circuit (150-1) reduces an output current limit value of the channel in response to the start limit signal and increases the output current limit value in response to the end limit signal. Each channel includes a current sensor circuit (120-1) adapted to measure an output current of the channel and provide a channel overcurrent alert signal if the output current exceeds a high current limit value. The system (100) includes a controller (140) that asserts the start limit signal when the number of channels exceeding the high current limit value is greater than a maximum allowed number and asserts the end limit signal when the number of channels exceeding the high current limit value is less than the maximum allowed number minus a hysteresis value.

Description

[Technical field]

[0001] This description relates generally to digital-to-analog converters (DACs), and more particularly to overcurrent limiting for multi-channel DACs. [Background technology]

[0002] Multi-channel DACs are used in wireless base stations, radar systems, and other systems that utilize radio frequency (RF) power amplifiers, for example, to transmit signals (over the air or by another medium). In many applications, a power supply is utilized to power the multi-channel DACs, and the outputs of the multi-channel DACs may be coupled to respective dynamic loads (e.g., antennas). Because the current demands of the dynamic loads may vary, the DAC channels are typically designed to supply the peak current demands of the loads. This requires that the power supply be designed to be able to meet the total peak current demands of the loads coupled to all the DAC channels. Because the peak current demands of one or more dynamic loads may only be sustained momentarily, utilizing a power supply that can meet the peak current demands of all the loads leads to an inefficient and expensive system.

[0003] For example, a 16-channel DAC may be configured such that each DAC channel can provide a peak current of 50 mA. Thus, a power supply capable of providing 800 mA may be utilized to provide power to the DAC channels. At any given time, only a small subset (e.g., three) of the DAC channels may be required to provide an output current greater than 50 mA (e.g., 60 mA), while the other 13 DAC channels may provide only 10 mA. Existing multi-channel DACs are configured such that if the output current of any individual DAC channel exceeds a peak current limit, the output of that DAC channel is pulled to a voltage source (e.g., a supply rail). As a result, the DAC channel is no longer required to provide a high output current to prevent a drop in the output voltage. As a result, damage to the transistors of the DAC channel is prevented. For example, if the output current of a DAC channel has a peak output limit of 50 mA, but is providing 60 mA, the output of the DAC channel is pulled to a voltage source (supply rail). In many cases, even though the power supply may be able to meet the total current demand of all DAC channels because some DAC channels may draw less current, one or more DAC channels may be inoperable because their output current exceeds the peak current limit. Summary of the Invention

[0004] In one aspect, a multi-channel digital-to-analog converter (DAC) system includes a plurality of DAC channels, each of the plurality of DAC channels including an input adapted to receive a digital input signal and convert the digital input signal to an analog output signal. Each DAC channel includes a current control circuit including a first input adapted to receive a start limit signal or an end limit signal. The current control circuit reduces an output current limit value of an output current of the DAC channel from a high current limit value to a low current limit value in response to the start limit signal and increases the output current limit value to a high current limit value in response to the end limit signal. Each DAC channel includes a current sensor circuit coupled to the current control circuit. The current sensor circuit measures the output current and provides a channel overcurrent alert signal when the output current exceeds the high current limit value. Each DAC channel includes an analog filter coupled to the current sensor circuit. The analog filter provides a filtered channel overcurrent alert signal in response to the channel overcurrent alert signal. The multi-channel DAC system includes a summer circuit coupled to each DAC channel. The summer circuit provides a sum signal indicative of the number of DAC channels that exceed the high current limit value. The multi-channel DAC system includes a controller coupled to the summer circuit. The controller asserts the start limit signal when the number of DAC channels exceeding the high current limit value is greater than the maximum channel overcurrent limit signal, and asserts the end limit signal when the number of channels exceeding the high current limit value is less than the maximum channel overcurrent limit signal minus a hysteresis value.

[0005] In an additional aspect, the multi-channel DAC system includes a digital filter having an input adapted to receive a limit end signal. The digital filter applies a time delay to the limit end signal. The digital filter passes the limit start signal without applying a time delay.

[0006] In an additional aspect, the analog filter is a low pass filter that removes high frequency components from the channel over-current signal and provides a filtered channel over-current alert signal.

[0007] In an additional aspect, a multi-channel DAC system includes a plurality of DAC channels. The DAC channels include respective inputs adapted to receive a digital input signal and convert the digital input signal to an analog output signal. The DAC channels each include a current control circuit including a first input adapted to receive a start limit signal or a delayed end limit signal. The current control circuit dynamically adjusts the output current limit of the DAC channel by reducing the output current limit from a high current limit value to a low current limit value in response to the start limit signal and increasing the output current limit to a high current limit value in response to the delayed end limit signal. The DAC channels each include a current sensor circuit adapted to measure the output current of the DAC channel and provide a channel overcurrent alert signal if the output current exceeds the high current limit value. The DAC channels each include a low pass filter including an input adapted to receive the channel overcurrent alert signal. The low pass filter removes high frequency components from the channel overcurrent alert signal and provides a filtered channel overcurrent alert signal. The multi-channel DAC system includes a summer circuit, the summer circuit including an input adapted to receive the respective filtered channel over-current alert signals from the DAC channels and provide a sum signal indicative of the number of DAC channels that exceed the high current limit. The multi-channel DAC system includes a controller, the controller including a first input adapted to receive a clock signal, a second input adapted to receive a hysteresis signal having a hysteresis value, a third input adapted to receive a maximum channel over-current limit signal indicative of the maximum number of DAC channels allowed to exceed the high current limit, and a fourth input adapted to receive the sum signal. The controller asserts a start limit signal when the number of DAC channels that exceed the high current limit is greater than the maximum channel over-current limit signal, and asserts an end limit signal when the number of channels that exceed the high current limit is less than the maximum channel over-current limit signal minus the hysteresis value. The multi-channel DAC system includes a digital filter including an input adapted to receive the start limit signal or the end limit signal.The digital filter applies a time delay to the end limit signal to provide a delayed end limit signal but passes the start limit signal.

[0008] In an additional aspect, a method of overcurrent protection for a multi-channel digital-to-analog converter (DAC) includes measuring an output current of a DAC channel and providing a channel overcurrent alert signal when the output current rises above a high current limit. The method includes filtering the channel overcurrent alert signal to remove high frequency components and determining a total number of DAC channels that exceed the high current limit based on the filtered overcurrent alert signal. The method includes comparing the total number of DAC channels that exceed the high current limit to a maximum channel overcurrent limit and the maximum channel overcurrent limit minus a hysteresis value. The method includes asserting a start limit signal when the total number of DAC channels that exceed the high current limit is greater than the maximum channel overcurrent limit and asserting an end limit signal when the total number of DAC channels that exceed the high current limit is less than the maximum channel overcurrent limit minus a hysteresis value. The method includes reducing an output current limit value of the DAC channel from a high current limit value to a lower current limit value in response to a begin limit signal, and increasing the output current limit value of the DAC channel from the lower current limit value to the high current limit value in response to an end limit signal. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1 is a block diagram of an example multi-channel DAC system.

[0010] [Figure 1B] This is an overcurrent alert waveform. [Figure 1C] 1 is a filtered overcurrent alert waveform.

[0011] [Diagram 2] 1 illustrates increasing and decreasing the output current limit of an example DAC channel.

[0012] [Diagram 3] 1 is a flow chart of an example method.

[0013] In the drawings, the same reference numerals or other feature designations are used to denote the same or similar (functional and / or structural) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In some examples, a cumulative current limit for high channel count DACs is implemented, allowing individual channels or a defined subset of channels to be in their maximum current state, but forcing a general current limit on all DAC channels if the total number of channels in a high current state exceeds a defined maximum limit. These examples may allow individual channels to source the maximum current the DAC can provide instantaneously, but still allow the power supply to be rated closer to the nominal load. Some examples facilitate cumulative current limit control of independent power domains. Some examples may include: (1) a high current (which may be defined during device manufacturing, by the end user, or during operation) detection and output flag for each DAC channel; (2) a per-channel current limit that may facilitate limiting (either per channel or as a cumulative value) the maximum current to a predetermined value (which may be defined during device manufacturing, by the end user, or during operation); and / or (3) a state machine or other processor or controller for maintaining / limiting the number of channels in a high current state, setting the current limit, and / or implementing hysteresis for enabling and disabling the current limit.

[0015] FIG. 1A is a block diagram of an example multi-channel DAC system 100. System 100 includes multiple DAC channels (C1, C2, CN) adapted to receive digital input signals (D1, D2, ...DN, respectively). DAC channel C1 receives digital input signal D1 at input 106-1, DAC channel C2 receives digital input signal D2 at input 106-2, and DAC channel CN ​​receives digital input signal DN at input 106-N. Digital input signals D1-DN are also referred to as digital input words. DAC channels C1-CN convert digital input signals D1-DN to respective analog output signals (VOUT-1, VOUT-2, ...VOUT-N, respectively) provided at respective outputs (108-1, 108-2, ...108-N, respectively). For simplicity, only output 108-1 and analog output signal VOUT-1 are shown in FIG. 1. The output signals VOUT-1, VOUT-2, . . . VOUT-N are analog representations of the respective digital input signals D1 through DN.

[0016] Although DAC channels C1-CN each have a respective load coupled to their output, FIG. 1 shows only a single load 110-1 for simplicity. Load 110-1 is coupled between output 108-1 and a common potential (e.g., ground). In some examples, the load may be a dynamic load such as a power amplifier or an RF transceiver. Depending on the operating state of the dynamic load, the output current demand from DAC channels C1-CN may vary. For example, C1-CN may be coupled to a respective power amplifier (not shown in FIG. 1), and each power amplifier may be coupled to an associated antenna or other transmission medium. At any given time, only a subset of the antennas / transmission channels may be active, while other antennas / transmission channels may be inactive. As a result, only a subset of the power amplifiers coupled to active antennas / transmission channels may draw high current (e.g., about 60 mA-80 mA) from their associated DAC channels, while power amplifiers coupled to inactive antennas / transmission channels may draw low / lower current (e.g., about 5 mA-10 mA) from their associated DAC channels.

[0017] In some examples, the DAC channels C1-CN may include a string DAC section and an interpolator section (not shown in FIG. 1). A DAC channel including a string DAC section and one or more interpolator sections is described in U.S. patent application Ser. No. 17 / 581,516, entitled "Digital-to-Analog Converter with Cascaded Least Significant Bit (LSB) Interpolator Circuits," filed Jan. 21, 2022, which is assigned to the present assignee and incorporated herein by reference. The string DAC section generates an output that is a coarse representation of the digital input word, and the interpolator section generates an output that is a fine interpolation of a voltage between the coarse representation voltage and a second voltage, which may be a voltage very close to the coarse representation voltage. In other examples, the DAC channel may have a delta-sigma architecture or any other suitable architecture. [Patent Document 1] U.S. Patent Application 17 / 581,516

[0018] Each of the DAC channels C1-CN may include a current sensor (e.g., current sensor 120-1 for channel C1) that measures the output current provided by the respective DAC channel. FIG. 1 illustrates only the current sensor for channel C1 for simplicity. The current sensor provides a channel overcurrent alert signal (e.g., OVER-CURRENT-1 for C1) when the output current of the DAC channel exceeds a channel overcurrent limit (HIGH-CURRENT-LIMIT). For example, channel C1 includes a current sensor 120-1 that measures the output current IOUT-1 and provides an overcurrent alert signal OVER-CURRENT-1 when IOUT-1 exceeds the HIGH-CURRENT-LIMIT. The channel overcurrent limit HIGH-CURRENT-LIMIT may be a user-defined input, as described below, set during device manufacturing, and / or set during operation (e.g., by a state machine, processor, or other digital circuitry, and / or software). For example, if there are 16 total DAC channels, each capable of supplying approximately 50mA of output current, then the HIGH-CURRENT-LIMIT may be set higher than 50mA (e.g., 10% or 20% higher than 50mA) if the power supply can meet the cumulative current demand from all DAC channels. Thus, if the power supply can supply 800mA, then the HIGH-CURRENT-LIMIT may be set equal to, for example, 60mA, as long as the power supply can meet the cumulative current demand. The effect of this is that one or more channels may be allowed to supply 60mA for a limited period of time if the power supply can meet the cumulative current demand from all DAC channels. In another example, the HIGH-CURRENT-LIMIT may be channel specific, such that certain channels have higher or lower limits than other channels.

[0019] In some examples, the current sensor 120-1 measures the magnetic field (or other electrical, magnetic, or mechanical indicator of the channel current) generated when the output current IOUT-1 flows through the load 110-1 and, in response, generates a voltage that is converted into an amount of current flowing through the load 110-1.

[0020] Each of the DAC channels C1-CN includes a respective analog (or digital) filter (only the filter of C1 is shown for simplicity) that filters the over-current alert signal. For example, C1 includes an analog (or digital) filter 124-1 (e.g., a low-pass filter, a high-pass filter, or a notch filter) that includes an input 126-1 coupled to receive the over-current alert signal OVER-CURRENT-1. The analog filter 124-1 removes certain frequency components (such as high frequency components if the filter is a low-pass filter) from OVER-CURRENT-1 and provides a filtered channel over-current alert signal FILTERED-OVER-CURRENT-1 at the output 126-2. The analog filter 124-1 blocks OVER-CURRENT-1 if the output current IOUT-1 momentarily exceeds the HIGH-CURRENT-LIMIT and then returns below the HIGH-CURRENT-LIMIT. The effect of this is that momentary glitches created by momentary over-current conditions are filtered out. 1B and 1C are example input and output waveforms of analog filter 124-1, respectively. The x-axis represents time, and the y-axis represents the over-current alert signal and the filtered over-current alert signal. FIG. 1B shows waveform OVER-CURRENT-1, which is the input to analog filter 124-1. Waveform OVER-CURRENT-1 includes glitch 127 generated by a momentary over-current condition in DAC channel C1. Thus, OVER-CURRENT-1 is the over-current condition before filtering. FIG. 1C shows waveform FILTERED-OVER-CURRENT-1, which is the output of analog filter 124-1. Glitch 127 is filtered (e.g., removed) by analog filter 124-1. Thus, FILTERED-OVER-CURRENT-1 is the over-current condition after filtering.

[0021] System 100 includes a summer circuit 130 that includes an input (132-1, ... 132-N) coupled to the output of an analog filter for each of the respective DAC channels C1-CN. Summer circuit 130 provides a sum signal (SUMMATION) at output 134 that indicates the number of channels ("N") that have exceeded the channel overcurrent limit. For example, system 100 may include a total of 32 channels, 10 of which may be in an overcurrent state. Thus, sum signal SUMMATION indicates that 10 channels (e.g., N is 10) have exceeded the channel overcurrent limit.

[0022] The system 100 includes a controller 140 having a first input 142-1 coupled to receive a clock signal CLK that may be generated by a signal generator 144. In some examples, a user may configure the signal generator 144 to provide a clock signal CLK of a desired frequency (e.g., 100 MHz, 200 MHz, 500 MHz). The controller 140 has a second input 142-2 coupled to receive a hysteresis signal (HYSTERIS) from a hysteresis configuration module 141. The hysteresis signal HYSTERESIS indicates a hysteresis value ("H"). As described below, in order to increase the output current limit value from a lower current level to the channel overcurrent limit value HIGH-CHANNEL-LIMIT, the sum number N (indicated by the sum signal SUMMATION) must be less than the maximum number "M" minus H (i.e., N is less than (MH)). The controller 140 has a third input 142-3 coupled to receive a maximum channel limit signal (MAX-CHANNEL-LIMIT) from the threshold configuration module 145. The maximum channel limit signal, MAX-CHANNEL-LIMIT, indicates the maximum number of channels ("M") that must be in an overcurrent state to cause the output current limit value to be reduced from HIGH-CHANNEL-LIMIT to a lower current limit value, LOW-LIMIT. In some examples, MAX-CHANNEL-LIMIT and HYSTERESIS are user configurable. For example, the maximum number of channels ("M") that are allowed to exceed the MAX-CHANNEL-LIMIT may be based on the maximum current that can be supplied by a power supply coupled to the system 100.

[0023] The controller 140 includes a fourth input 142-4 coupled to receive a sum signal SUMMATION that indicates the number of DAC channels ("N") that are in an overcurrent condition.

[0024] Controller 140 asserts a start limit signal (START-LIMIT) at output 146 if the sum number N (denoted SUMMATION) is greater than a maximum channel limit M (denoted MAX-CHANNEL-LIMIT), and asserts an end limit signal (END-LIMIT) at output 146 if the sum number N is less than or equal to M minus H (MH). Thus, if the total number of channels in an overcurrent condition exceeds the maximum allowed number M, the controller asserts START-LIMIT at output 146. However, controller 140 does not immediately assert END-LIMIT if the total number of channels in an overcurrent condition falls below M. Instead, controller 140 waits until the total number of channels in an overcurrent condition is less than MH before asserting END_LIMIT.

[0025] In operation, high channel current demand may cause one or more channels to operate slightly above the channel overcurrent limit value HIGH-CURRENT-LIMIT. If the channel current demand decreases slightly, those channels may operate slightly below the HIGH-CURRENT-LIMIT, which may prompt the controller 140 to assert the END-LIMIT. If the channel current demand increases, those channels may operate slightly above the HIGH-CURRENT-LIMIT, which may prompt the controller 140 to assert the START-LIMIT. As a result, the DAC 100 is forced to activate and deactivate overcurrent protection that may not be necessary. By implementing hysteresis, the controller 140 is prevented from asserting the END-LIMIT and then immediately asserting the START-LIMIT, thus preventing the system from cycling. The hysteresis value H may indicate a number (e.g., the number of DAC channels). Controller 140, or portions thereof, may be implemented in hardware (eg, logic circuitry, state machines, microprocessors, memory, and / or application specific integrated circuits), firmware, and / or software.

[0026] Each of the DAC channels C1-CN includes a respective current control circuit that reduces the output current limit of the DAC channel in response to a start limit signal START-LIMIT and increases the output current limit in response to an end limit signal END-LIMIT. For example, channel C1 includes a current control circuit 150-1 having a first input 152-1 coupled (directly or indirectly via digital filter 160) to output 146 of controller 140. Current control circuit 150-1 reduces the output current limit of DAC channel C1 from HIGH-CURRENT-LIMIT to a lower current level LOWER-LIMIT in response to the start limit signal START-LIMIT and increases the output current limit back to HIGH-CURRENT-LIMIT in response to END-LIMIT. Unlike existing multi-channel DACs that shut down individual DAC channels if their output current exceeds the peak current limit, the described examples allow individual DAC channels to supply output currents that may exceed the peak current limit for short periods of time if the total number of channels in an overcurrent state is less than the maximum allowed number of channels in an overcurrent state (e.g., M) and the power supply can supply the cumulative current demand from all channels. For example, the HIGH-CURRENT-LIMIT may be set equal to 60mA and the maximum number of channels allowed to be in an overcurrent state, M, may be set equal to 5. If four channels exceed the HIGH-CURRENT-LIMIT (e.g., four channels each supply 65mA), those four channels may be allowed to continue operating beyond the HIGH-CURRENT-LIMIT if the power supply can meet the total cumulative current demand from all DAC channels. In some examples, the HIGH-CURRENT-LIMIT for a DAC channel may be set during manufacturing. Some other examples allow setting of the system maximum current, but rather than reducing the maximum current of all channels to ensure that the total system current is within their supply capabilities, they allow a higher maximum current for each individual channel (as long as it does not exceed the maximum system current).

[0027] 2 illustrates increasing the output current limit of a DAC channel to the HIGH-CURRENT-LIMIT in response to assertion of the END-LIMIT signal, and decreasing the output current limit of a DAC channel to a lower current level, LOWER_LIMIT, in response to assertion of the START-LIMIT signal. The x-axis represents the total number of channels in an overcurrent condition, and the y-axis represents the output current.

[0028] If the total number of channels in an overcurrent state, N, is greater than the maximum number of channels allowed to be in an overcurrent state, M, then DAC 100 asserts START-LIMIT, which causes the current control circuits in all channels (e.g., current control circuits 150-1 through 150-N for DAC channels C1 through CN, respectively) to reduce their output current limits to a lower level, LOWER-LIMIT. Thus, in response to the assertion of START-LIMIT, the output currents of all DAC channels (e.g., C1 through CN) are reduced to the lower level, LOWER-LIMIT. This is shown by the dashed lines in FIG. 2. If N then falls below M, then the current control circuit of each DAC channel (e.g., current control circuit 150-1 for DAC channel C1) does not immediately increase its output current limit. This is shown in FIG. 2 by the lower solid line between "M" and "MH". Instead, the current control circuit of each DAC channel waits until N is less than (MH) before increasing its output current limit. When the output current limit is increased, the output current of the DAC channel (e.g., IOUT-1 of C1) is allowed to increase. By implementing hysteresis H, the controller 140 is prevented from asserting END-LIMIT and then immediately asserting START-LIMIT, thus preventing the system 100 from cycling.

[0029] In some examples, system 100 includes a digital filter 160 that is incorporated between the output 146 of controller 140 and the input to each DAC channel (e.g., inputs 152-1, ... 152-N of current limit circuits 150-1, ... 150-N). Digital filter 160 has an input 162 that is coupled to output 146 of controller 140. When controller 140 asserts END-LIMIT, digital filter 160 applies a time delay (e.g., 1 ms, 10 ms) to signal END-LIMIT and provides a delayed END-LIMIT at output 164. However, when controller asserts START-LIMIT, digital filter 160 does not apply a time delay to START-LIMIT but simply forwards it to output 164. Therefore, when controller 140 asserts START-LIMIT in response to an over-current condition, digital filter 160 passes the signal on without applying a time delay, allowing the current control circuits in each DAC channel to immediately apply current limits without delay, thus preventing damage to the DAC channels. However, when controller 140 asserts END-LIMIT (because the total number of channels in an over-current condition has fallen below MH), digital filter 160 adds a time delay to prevent potential cycling caused by one or more DAC channels momentarily falling below the maximum allowed number before exceeding it.

[0030] In some examples, system 100 reduces the output current limit of all DAC channels (e.g., C1-CN) even if only a subset of the total number of DAC channels are in an overcurrent state. For example, system 100 may have a total of 16 DAC channels (e.g., C1-C16), and the maximum number of channels that may operate above the channel overcurrent limit HIGH-CHANNEL-LIMIT may be set equal to 5. If six channels exceed the HIGH-CURRENT-LIMIT (i.e., an overcurrent state), controller 140 asserts START-LIMIT, which causes current control circuitry 150 to reduce the output current of all channels (C1-C16) from the HIGH-CURRENT-LIMIT (e.g., 50mA) to the LOWER-LIMIT (e.g., 10mA). In other examples, controller 140 reduces only the current of certain DAC channels (e.g., the six channels that exceed the limit and / or the channels that have a history of exceeding the current limit).

[0031] 3 is a flow chart of an example method 300. In block 304, the output current of a DAC channel is measured and an overcurrent alert signal is generated if the output current of the DAC channel exceeds a channel overcurrent limit HIGH-CURRENT-LIMIT. In one example, a current sensor in each DAC channel (e.g., 120-1...120-N) measures the output current of an associated DAC channel and provides an overcurrent alert signal if the output current of the DAC channel exceeds the HIGH-CURRENT-LIMIT.

[0032] At block 308, the one or more over-current alert signals are filtered to remove spurious and / or transient components (eg, remove high frequency components).

[0033] In block 312, a total number of DAC channels in an overcurrent state is determined. In one example, adder circuit 130 determines the number N of DAC channels in an overcurrent state (also referred to as sum number N) based on the number of overcurrent alert signals. In block 316, sum number N is compared to the maximum number M of channels allowed to operate in an overcurrent state and to M minus H (MH), where H is a hysteresis value. In one example, controller 140 compares N to M and N to (MH). If N is greater than M (N>M), a start limit signal START-LIMIT is asserted (block 320). If N is less than M minus H (N<(MH)), an end limit signal END-LIMIT is asserted (block 324). If START-LIMIT is asserted, the output current limit value of DAC channels C1-CN is reduced to a lower current level LOWER-LIMIT (block 328). In one example, the current control circuit of each DAC channel (e.g., 150-1...150-N) reduces the output current limit of the respective DAC channel to a lower current level to protect the DAC channel. If the END-LIMIT is asserted, a time delay is applied to the END-LIMIT (block 332), and then (at block 336) the output current limit is increased to a higher level (e.g., the HIGH-CURRENT-LIMIT). In one example, the digital filter 160 applies a time delay to the END-LIMIT and provides the delayed END-LIMIT to the current control circuit of each of the DAC channels. In response, the current control circuit of each of the DAC channels increases the output current limit to the HIGH-CURRENT-LIMIT.

[0034] The systems described herein may include one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources). System 100 may include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) that may be coupled to at least some of the passive elements and / or sources to form the described structures, either during or after manufacture, such as by an end user and / or a third party. Some examples may include certain elements implemented within an integrated circuit and other elements are external to the integrated circuit, while in other examples additional or fewer features may be incorporated within the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included within the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) integrated in / on a semiconductor substrate, (2) integrated in a single semiconductor package, (3) integrated in the same module, and / or (4) integrated in / on the same printed circuit board.

[0035] In this description, the term "coupled" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, (a) in a first example, device A is coupled to device B if device A provides a signal that controls device B to perform a certain action, or (b) in a second example, device A is coupled to device B via an intervening component C, where the intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via a control signal provided by device A. Also, in this description, a device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) at the time of manufacture by a manufacturer to perform that function and / or configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the construction and / or layout of the device's hardware components and interconnections, or a combination thereof. Also, in this description, circuits or devices including certain components may instead be adapted to be coupled to those components to form the described circuit elements or devices. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be adapted to be coupled to at least some of the passive elements and / or sources, either during or after manufacture, such as by an end user and / or a third party, to form the described structure.

[0036] As used herein, the terms "terminal," "node," "interconnect," and "pin" are used interchangeably. Unless specifically stated to the contrary, such terms are used generally to mean an interconnection between, or a termination of, a device element, a circuit element, an integrated circuit, a device, or other electronic or semiconductor component.

[0037] While some examples suggest that certain elements are included within an integrated circuit while other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated within the integrated circuit. Also, some or all of the features shown as being external to the integrated circuit may be included within the integrated circuit and / or some features shown as being internal to the integrated circuit may be incorporated external to the integration. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated on the same printed circuit board.

[0038] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. The circuits described herein are reconfigurable to include the replaced components to provide at least partially similar functionality to that available prior to replacing the components. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series or parallel between the same two nodes as the single resistor or capacitor, respectively. Additionally, the use of the phrase "ground terminal" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value, or, if the value is zero, a reasonable range of values ​​around the zero.

[0039] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the appended claims.

Claims

1. 1. A multi-channel digital-to-analog converter (DAC), comprising: a plurality of DAC channels, each having an input adapted to receive a digital input signal and operable to convert the digital input signal to an analog output signal; a summer circuit coupled to each DAC channel; a controller coupled to the adder circuit; Including, Each DAC channel has an output current, each DAC channel comprising: a current control circuit having a first input adapted to receive a start limit signal or an end limit signal, the current control circuit operable to reduce an output current limit value of the output current from a high current limit value to a low current limit value in response to the start limit signal and to increase the output current limit value to the high current limit value in response to the end limit signal; a current sensor circuit coupled to the current control circuit, the current sensor circuit adapted to measure the output current and provide a channel overcurrent alert signal when the output current exceeds the high current limit; an analog filter coupled to the current sensor circuit, the analog filter operable in response to the channel over-current alert signal to provide a filtered channel over-current alert signal; Including, the summer circuit is operable to provide a sum signal indicative of a number of DAC channels exceeding the high current limit; the controller is operable to assert the start limit signal when a number of DAC channels exceeding the high current limit value is greater than a maximum channel overcurrent limit signal, and to assert the end limit signal when a number of channels exceeding the high current limit value is less than the maximum channel overcurrent limit signal minus a hysteresis value. D A C.

2. 2. The DAC of claim 1 further comprising a digital filter coupled to the controller, the digital filter operable to apply a time delay to the end limit signal.

3. 2. The DAC of claim 1, further comprising a digital filter coupled to the controller, the digital filter operable to pass the limited start signal without applying a time delay.

4. 2. The DAC of claim 1, wherein the analog filter is a low pass filter operable to remove high frequency components from the channel over-current alert signal and to provide the filtered channel over-current alert signal.

5. 2. The DAC of claim 1, wherein the controller includes a comparison circuit operable to assert the start limit signal or the end limit signal by comparing a number of channels exceeding the channel overcurrent limit value to the maximum channel overcurrent limit signal and the maximum channel overcurrent limit signal minus the hysteresis value.

6. 2. The DAC of claim 1, wherein in response to a rising edge or a falling edge of the clock signal, the controller is operable to compare a number of channels exceeding the channel overcurrent limit value to the maximum channel overcurrent limit signal and the maximum channel overcurrent limit signal minus the hysteresis value.

7. 1. A multi-channel digital-to-analog converter (DAC), comprising: a plurality of DAC channels, each having a digital signal input and an analog signal output; a summer circuit coupled to each DAC channel; a controller coupled to the adder circuit; a digital filter coupled to the controller; Including, Each DAC channel has an output current, each DAC channel comprising: a current control circuit having a first input adapted to receive a start limit signal or a delayed end limit signal, the current control circuit operable to reduce an output current limit value of the DAC channel by reducing the output current limit value from a high current limit value to a low current limit value in response to the start limit signal and to increase the output current limit value to the high current limit value in response to the delayed end limit signal; a current sensor circuit coupled to the current control circuit, the current sensor circuit adapted to measure the output current and provide a channel overcurrent alert signal when the output current exceeds the high current limit; a low pass filter coupled to the current sensor circuit, the low pass filter operable in response to the channel over-current alert signal to provide a filtered channel over-current alert signal; Including, the summer circuit is operable to provide a sum signal indicative of a number of DAC channels exceeding the high current limit; the controller is operable to assert the start limit signal when a number of DAC channels exceeding the high current limit value is greater than a maximum channel overcurrent limit signal, and to assert the end limit signal when a number of channels exceeding the high current limit value is less than the maximum channel overcurrent limit signal minus a hysteresis value; the digital filter is operable to provide the delayed end limit signal by applying a time delay to the end limit signal and to pass the start limit signal. D A C.

8. 8. The DAC of claim 7, wherein the controller includes a comparison circuit operable to assert the start limit signal or the end limit signal by comparing a number of channels exceeding the high current limit value to the maximum channel overcurrent limit signal and the maximum channel overcurrent limit signal minus the hysteresis value.

9. 8. The DAC of claim 7, wherein in response to a rising edge or a falling edge of the clock signal, the controller is operable to compare the number of channels exceeding the high current limit value to the maximum channel overcurrent limit signal and the maximum channel overcurrent limit signal minus the hysteresis value.

10. 8. A DAC as claimed in claim 7, wherein the digital filter is operable to pass the limited start signal without applying a time delay.

11. 1. A method of overcurrent protection for a multi-channel digital-to-analog converter (DAC), comprising: measuring an output current of each DAC channel and asserting a channel overcurrent alert signal for each DAC channel having an output current greater than a high current limit; determining a sum of asserted channel overcurrent alert signals; asserting a start limit signal in response to the sum of asserted channel overcurrent alert signals exceeding a maximum channel overcurrent limit; asserting an end limit signal in response to the sum of asserted channel overcurrent alert signals being less than the maximum channel overcurrent limit minus a hysteresis value; reducing an output current limit value of the DAC channel from the high current limit value to a lower current limit value in response to asserting the start limit signal; increasing the output current limit value of the DAC channel from the lower current limit value to the high current limit value in response to asserting the end limit signal; A method comprising:

12. 12. The method of claim 11, further comprising delaying the increase of the output current limit value from the lower current limit value to the high current limit value by applying a time delay to the end limit signal.

13. 12. The method of claim 11, further comprising not delaying the reduction of the output current limit value from the high current limit value to a lower current limit value by not applying a time delay to the limit start signal.

14. 12. The method of claim 11, further comprising asserting the start limit signal or the end limit signal in response to a rising edge of a clock signal.

15. 12. The method of claim 11, further comprising asserting the start limit signal or the end limit signal in response to a falling edge of a clock signal.

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