Display device and tiled display device

Abstract

A display device is provided, comprising: a first data wiring to which a first data voltage is applied, a second data wiring to which a second data voltage is applied, a low potential wiring to which a low potential voltage is applied, and a first sub-pixel connected to the first data wiring, the second data wiring, and the low potential wiring, the first sub-pixel including a cathode pad electrode connected to the low potential wiring, a first transistor generating a control current in response to a first data voltage of the first data wiring and having a first gate electrode, an eighth transistor generating a driving current to be applied to a light emitting element in response to a second data voltage of the second data wiring, and a first capacitor including a first capacitor electrode connected to the first gate electrode and a second capacitor electrode disposed on the first capacitor electrode, the low potential wiring being disposed in the same layer as the second capacitor electrode and surrounding the second capacitor electrode.

Description

[Technical field]

[0001] The present invention relates to displays and tiled displays. [Background technology]

[0002] With the development of the information society, the requirements for display devices for displaying images are becoming more and more diverse. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, a light emitting display device, etc. The light emitting display device may be an organic light emitting display device including an organic light emitting diode device as a light emitting element, or a light emitting diode display device including an inorganic light emitting diode device such as an LED (Light Emitting Diode) as a light emitting element. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS An object of the present invention is to provide a display device capable of reducing manufacturing costs by reducing the number of masks.

[0004] The object of the present invention is not limited to the above-mentioned objects, and other technical objects not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] According to one embodiment of the present invention, there is provided a display device comprising: a first data wiring to which a first data voltage is applied, a second data wiring to which a second data voltage is applied, a low potential wiring to which a low potential voltage is applied, and a first sub-pixel connected to the first data wiring, the second data wiring, and the low potential wiring, the first sub-pixel including a cathode pad electrode connected to the low potential wiring, a first transistor generating a control current in response to a first data voltage of the first data wiring and having a first gate electrode, an eighth transistor generating a drive current to be applied to a light-emitting element in response to a second data voltage of the second data wiring, and a first capacitor including a first capacitor electrode connected to the first gate electrode and a second capacitor electrode disposed on the first capacitor electrode, the low potential wiring being disposed in the same layer as the second capacitor electrode and surrounding the second capacitor electrode.

[0006] According to another embodiment of the present invention, there is provided a display device comprising: a first data wiring to which a first data voltage is applied; a second data wiring to which a second data voltage is applied; a low potential wiring to which a low potential voltage is applied; a second high potential wiring to which a second high potential voltage is applied; and a first sub-pixel connected to the first data wiring, the second data wiring, the low potential wiring, and the second high potential wiring, wherein the first sub-pixel comprises: a first transistor having a first gate electrode and generating a control current in response to a first data voltage of the first data wiring; an eighth transistor generating a drive current to be applied to a light-emitting element in response to a second data voltage of the second data wiring; and a capacitor electrode disposed on the first gate electrode, wherein the low potential wiring is disposed in the same layer as the capacitor electrode; and the second high potential wiring includes an opening exposing the low potential wiring.

[0007] A display device according to another embodiment for solving the other problem includes a substrate, an active layer including a first channel, a first source electrode, and a first drain electrode disposed on the substrate, a first insulating film disposed on the active layer, a first gate electrode and a first capacitor electrode disposed on the first insulating film and overlapping with the first channel, a second insulating film disposed on the first gate electrode and the first capacitor electrode, a second capacitor electrode and a low potential wiring disposed on the second insulating film and overlapping with the first capacitor electrode, a third insulating film disposed on the second capacitor electrode and the low potential wiring, a scan write wiring disposed on the third insulating film and to which a scan write signal is applied, a fourth insulating film disposed on the scan write wiring, a second high potential wiring disposed on the fourth insulating film and to which a second high potential voltage is applied, and a cathode pad electrode disposed on the second high potential wiring and connected to the low potential wiring.

[0008] According to another embodiment of the present invention, a display device for solving the other problem includes a substrate, an active layer disposed on the substrate and having a first channel, a first gate metal layer disposed on the active layer and having a first gate electrode overlapping the first channel, and a first capacitor electrode, a second gate metal layer disposed on the first gate metal layer and having a second capacitor electrode overlapping the first capacitor electrode, and a low potential wiring spaced from the second capacitor electrode, a first source metal layer disposed on the second gate metal layer and having a first light emitting wiring to which a first light emitting signal is applied, a second source metal layer disposed on the first source metal layer and having a data wiring to which a data voltage is applied, a third source metal layer disposed on the second source metal layer and having a high potential wiring to which a high potential voltage is applied, and an anode pad electrode and a cathode pad electrode disposed on the third source metal layer. Effect of the Invention

[0009] According to an embodiment of the present invention, a display device may include a first gate metal layer including a gate electrode of a transistor, and a second gate metal layer including an upper capacitor electrode. The second gate metal layer includes a low potential wiring to which a low potential voltage is applied in an area where the upper capacitor electrode is not disposed, thereby reducing the number of masks. As a result, the manufacturing cost of the display device may be reduced and the manufacturing process may be simplified. The effects of the embodiments are not limited to the above examples, and more various effects are included in the present specification. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a display device according to an embodiment. [Diagram 2] FIG. 2 is an illustrative diagram showing an example of a pixel in FIG. [Diagram 3] 1. FIG. 4 is a diagram illustrating still another example of the pixel in FIG. [Figure 4] 1 is a block diagram showing a display device according to an embodiment. [Diagram 5] FIG. 4 is a circuit diagram illustrating a first sub-pixel according to an embodiment. [Figure 6] FIG. 2 is a layout diagram showing an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to an embodiment. [Figure 7] FIG. 7 is a layout diagram showing a third source metal layer and a pad electrode in FIG. 6. [Figure 8] FIG. 7 is a layout diagram showing the active layer and the first gate metal layer of FIG. 6. [Figure 9] FIG. 7 is a layout diagram showing the active layer, the first gate metal layer, and the second gate metal layer of FIG. 6. [Figure 10] FIG. 7 is a layout diagram showing the first and second source metal layers of FIG. 6. [Figure 11] FIG. 7 is a layout diagram showing the first source metal layer, the second source metal layer, and the third source metal layer of FIG. 6. [Figure 12]FIG. 8 is an enlarged layout diagram showing in detail area A of FIGS. 6 and 7. [Figure 13] FIG. 8 is an enlarged layout diagram showing in detail area A of FIGS. 6 and 7. [Figure 14] FIG. 7 is an enlarged layout diagram showing the details of region B in FIG. 6. [Figure 15] FIG. 8 is an enlarged layout diagram showing in detail area C of FIGS. 6 and 7. [Figure 16] FIG. 8 is an enlarged layout diagram showing in detail area C of FIGS. 6 and 7. [Figure 17] FIG. 8 is a cross-sectional view taken along line II' in FIGS. 6 and 7. [Figure 18] FIG. 8 is a cross-sectional view taken along line II-II' in FIGS. 6 and 7. [Figure 19] FIG. 8 is a cross-sectional view taken along line III-III' in FIGS. 6 and 7. [Figure 20] 8 is a cross-sectional view taken along lines IV-IV' and V-V' in FIGS. 6 and 7. FIG. [Figure 21] 8A to 8C are other examples of cross-sectional views taken along lines IV-IV' and V-V' in FIGS. 6 and 7. [Figure 22] FIG. 1 is a perspective view illustrating a tiled display device including a plurality of display devices according to one embodiment. [Figure 23] FIG. 23 is an enlarged layout diagram showing in detail area E of FIG. 22. [Figure 24] 22 is a cross-sectional view showing an example of a tiled display device taken along the line X1-X1' in FIG. 21. [Diagram 25] FIG. 23 is an enlarged layout diagram showing the F region in detail in FIG. 22. [Figure 26] 26 is a cross-sectional view showing an example of a tiled display device taken along the line X5-X5' in FIG. 25. [Figure 27] FIG. 1 is a block diagram illustrating a tiled display device according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The advantages and features of the present invention, as well as the methods for achieving them, will become clear from the detailed description of the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0012] When elements or layers are referred to as "on" other elements or layers, this includes all cases where other layers or other elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments are merely illustrative, and the present invention is not limited to the illustrated matters.

[0013] Although the terms "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that the first component referred to below may be the second component within the technical concept of the present invention.

[0014] The respective features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and various technical interlocking and driving mechanisms are possible, and each embodiment may be implemented independently of each other or in conjunction with each other.

[0015] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0016] Fig. 1 is a plan view illustrating a display device according to an embodiment, Fig. 2 is a diagram illustrating an example of a pixel of Fig. 1, Fig. 3 is a diagram illustrating another example of the pixel of Fig. 1.

[0017] 1 to 3, a display device 10 is a device for displaying moving or still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and Ultra Mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT) devices.

[0018] The display panel 100 may be formed as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting with the first direction DR1. A corner where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded or formed at a right angle to have a predetermined curvature. The plane shape of the display panel 100 is not limited to a rectangle, and may be formed as other polygonal, circular, or elliptical shapes. The display panel 100 is formed to be flat, but is not limited thereto. For example, the display panel 100 may include curved portions having a constant curvature or a varying curvature formed on the left and right edges. In addition, the display panel 100 may be formed to be flexible so as to be bent, warped, bent, folded, or rolled.

[0019] The display panel 100 may further include pixels PX, scan lines extending in a first direction DR1, and data lines extending in a second direction DR2 to display an image. The pixels PX may be arranged in a matrix in the first direction DR1 and the second direction DR2.

[0020] Each pixel PX may include a number of sub-pixels RP, GP, and BP as shown in Figures 2 and 3. Figures 2 and 3 illustrate an example in which each pixel PX includes three sub-pixels RP, GP, and BP, i.e., a first sub-pixel RP, a second sub-pixel GP, and a third sub-pixel BP, but the embodiments of this specification are not limited to this.

[0021] The first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be connected to one of the data lines and at least one of the scan lines.

[0022] Each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a rectangular, square, or diamond-shaped planar shape. For example, each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2, as shown in Fig. 2. Alternatively, each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a square or diamond-shaped planar shape including sides having the same length in the first direction DR1 and the second direction DR2, as shown in Fig. 3.

[0023] As shown in Fig. 2, the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be arranged in a first direction DR1. Alternatively, one of the second sub-pixel GP and the third sub-pixel BP and the first sub-pixel RP may be arranged in the first direction DR1, and the remaining one of the second sub-pixel GP and the first sub-pixel RP may be arranged in the second direction DR2. For example, as shown in Fig. 3, the first sub-pixel RP and the second sub-pixel GP may be arranged in the first direction DR1, and the first sub-pixel RP and the third sub-pixel BP may be arranged in the second direction DR2.

[0024] Alternatively, the first sub-pixel RP or any one of the third sub-pixels BP and the second sub-pixel GP may be arranged in the first direction DR1, and the remaining one and the second sub-pixel GP may be arranged in the second direction DR2. Alternatively, the first sub-pixel RP or any one of the second sub-pixels GP and the third sub-pixel BP may be arranged in the first direction DR1, and the remaining one and the third sub-pixel BP may be arranged in the second direction DR2.

[0025] The first sub-pixel RP may include a first light-emitting element that emits a first light, the second sub-pixel GP may include a second light-emitting element that emits a second light, and the third sub-pixel BP may include a third light-emitting element that emits a third light. Here, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0026] Each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element that emits light. For example, the inorganic light-emitting element may be a flip chip type micro LED (Light Emitting Diode), but the embodiment of the present specification is not limited thereto.

[0027] 2 and 3, the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be substantially the same, but the embodiments of the present specification are not limited thereto. At least one of the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be different from the others. Alternatively, any two of the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be substantially the same, and the remaining one may be different from the two. Alternatively, the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be different from each other.

[0028] FIG. 4 is a block diagram illustrating a display device according to an embodiment.

[0029] 4, the display device 10 includes a display panel 100, a scan driver 110, a source driver 200, a timing controller 300, and a power supply 400. The display panel 100 includes a display panel 100, a scan driver 110, a source driver 200, a timing controller 300, and a power supply 400.

[0030] The display area DA of the display panel 100 may include sub-pixels RP, GP, and BP that display an image, scan write wiring GWL connected to the sub-pixels RP, GP, and BP, scan initialization wiring GIL, scan control wiring GCL, sweep signal wiring SWPL, PWM (Pulse Width Modulation) light-emitting wiring PWEL, PAM (Pulse width Amplitude) light-emitting wiring PAEL, PWM data wiring DL, a first PAM data wiring RDL, a second PAM data wiring GDL, and a third PAM data wiring BDL.

[0031] The scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep signal line SWPL, the PWM light emission line PWEL, and the PAM light emission line PAEL may extend in a first direction DR1 and be arranged in a second direction DR2 intersecting the first direction DR1. The PWM data line DL, the first PAM data line RDL, the second PAM data line GDL, and the third PAM data line BDL may extend in the second direction DR2 and be arranged in the first direction DR1. The first PAM data lines RDL may be electrically connected to each other, the second PAM data lines GDL may be electrically connected to each other, and the third PAM data lines BDL may be electrically connected to each other.

[0032] Each of the sub-pixels RP, GP, and BP may be connected to one of the scan write lines GWL, one of the scan initialization lines GIL, one of the scan control lines GCL, one of the sweep signal lines SWPL, one of the PWM light emission lines PWEL, and one of the PAM light emission lines PAEL. Each of the first sub-pixels RP may be connected to one of the PWM data lines DL and one of the first PAM data lines RDL. Each of the second sub-pixels GP may be connected to one of the PWM data lines DL and one of the second PAM data lines GDL. Each of the third sub-pixels BP may be connected to one of the PWM data lines DL and one of the third PAM data lines BDL.

[0033] A scan driver 110 for applying signals to the scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep signal line SWPL, the PWM light emission line PWEL, and the PAM light emission line PAEL may be disposed in the non-display area of ​​the display panel 100. Although FIG. 4 illustrates an example in which the scan driver 110 is disposed on one side edge of the display panel 100, the present invention is not limited thereto. The scan driver 110 may be disposed on both sides of the display panel 100.

[0034] The scan driver 110 may include a first scan signal driver 111, a second scan signal driver 112, a sweep signal driver 113, and an emission signal driver 114.

[0035] The first scan signal driver 111 may receive a first scan drive control signal from the timing controller 300. The first scan signal driver 111 may output a scan initialization signal to the scan initialization line GIL and a scan write signal to the scan write line GWL in response to the first scan drive control signal. That is, the first scan signal driver 111 may output two scan signals, i.e., a scan initialization signal and a scan write signal.

[0036] The second scan signal driver 112 may receive a second scan drive control signal from the timing control unit 300. The second scan signal driver 112 may output a scan control signal to the scan control line GCL in response to the second scan drive control signal.

[0037] The sweep signal driver 113 may receive a first light emission control signal and a sweep control signal from the timing controller 300. The sweep signal driver 113 may output a PWM light emission signal to the PWM light emission wiring PWEL and a sweep signal to the sweep signal wiring SWPL in response to the first light emission control signal. That is, the sweep signal driver 113 may output both the PWM light emission signal and the sweep signal.

[0038] The light emission signal driver 114 may receive a second light emission control signal from the timing controller 300. The light emission signal driver 114 may output a PAM light emission signal to the PAM light emission wiring PAEL in response to the second light emission control signal.

[0039] The timing controller 300 receives digital video data DATA and a timing signal TS. The timing controller 300 can generate a scan timing control signal for controlling the operation timing of the scan driver 110 in response to the timing signal TS. The scan timing control signal can be a first scan drive control signal, a second scan drive control signal, a first light emission control signal, a second light emission control signal, and a sweep control signal. The timing controller 300 can also generate a source control signal for controlling the operation timing of the source driver 200.

[0040] The timing control unit 300 outputs a first scan drive control signal, a second scan drive control signal, a first light emission control signal, a second light emission control signal, and a sweep control signal to the scan driver 110. The timing control unit 300 outputs digital video data DATA and a PWM control signal DCS to the source driver 200.

[0041] The source driver 200 converts the digital video data DATA into an analog PWM data voltage and outputs it to the PWM data line DL. Thus, the sub-pixels RP, GP, and BP are selected by the scan write signal of the scan driver 110, and the PWM data voltage can be supplied to the selected sub-pixels RP, GP, and BP.

[0042] The power supply unit 400 may output a first PAM data voltage to each of the first PAM data lines RDL in common, a second PAM data voltage to each of the second PAM data lines GDL in common, and a third PAM data voltage to each of the third PAM data lines BDL in common. The power supply unit 400 may generate a plurality of power supply voltages and output them to the display panel 100.

[0043] The power supply unit 400 may output a first power supply voltage VDD1, a second power supply voltage VDD2, a third power supply voltage VSS, an initialization voltage VINT, a gate-on voltage VGL, and a gate-off voltage VGH to the display panel 100. The first power supply voltage VDD1 and the second power supply voltage VDD2 may be high potential driving voltages for driving the light emitting elements of the sub-pixels RP, GP, and BP. The third driving voltage VSS may be a low potential driving voltage for driving the light emitting elements of the sub-pixels RP, GP, and BP. The initialization voltage VINT and the gate-off voltage VGH may be applied to the sub-pixels RP, GP, and BP, respectively, and the gate-on voltage VGL and the gate-off voltage VGH may be applied to the scan driver 110.

[0044] Each of the source driver 200, the timing controller 300, and the power supply 400 may be formed as an integrated circuit, and the source driver 200 may be formed as a plurality of integrated circuits.

[0045] FIG. 5 is a circuit diagram illustrating a first sub-pixel according to an embodiment.

[0046] 5, the first sub-pixel RP according to an embodiment may be connected to a kth (k is a positive integer) scan write line GWLk, a kth scan initialization line GILk, a kth scan control line GCLk, a kth sweep signal line SWPLk, a kth PWM light emission line PWELk, and a kth PAM light emission line PAELk. The first sub-pixel RP may also be connected to a jth PWM data line DLj and a first PAM data line RDL. The first sub-pixel RP may also be connected to a first power supply line VDL1 to which a first power supply voltage VDD1 is applied, a second power supply line VDL2 to which a second power supply voltage VDD2 is applied, a third power supply line VSL to which a third power supply voltage VSS is applied, an initialization voltage line VIL to which an initialization voltage VINT is applied, and a gate-off voltage line VGHL to which a gate-off voltage VGH is applied. For convenience of explanation, the j-th PWM data line DLj may be referred to as the first data line, the first PAM data line RDL may be referred to as the second data line, the first power supply line VDL1 may be referred to as the first high potential line, the second power supply line VDL2 may be referred to as the second high potential line, and the third power supply line VSL may be referred to as the low potential line.

[0047] The first sub-pixel RP may include a light emitting element (EL), a first pixel driving unit PDU1, a second pixel driving unit PDU2, and a third pixel driving unit PDU3.

[0048] The light emitting element EL emits light according to the driving current Ids generated by the second pixel driving unit PDU2. The light emitting element EL may be disposed between the seventeenth transistor T17 and the third power wiring VSL. A first electrode of the light emitting element EL may be connected to a second electrode of the seventeenth transistor T17, and a second electrode of the light emitting element EL may be connected to the third power wiring VSL. The first electrode of the light emitting element EL may be an anode electrode, and the second electrode may be a cathode electrode. The light emitting element EL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light emitting element EL may be, but is not limited to, a micro light emitting diode made of an inorganic semiconductor. In FIG. 20, the first electrode of the light emitting element EL may be a p-type semiconductor PSEM, and the second electrode of the light emitting element EL may be an n-type semiconductor NSEM.

[0049] The first pixel driving unit PDU1 generates a control current Ic in response to the jth PWM data voltage of the jth PWM data line DLj to control the voltage of the third node N3 of the third pixel driving unit PDU3. Since the pulse width of the driving current Ids flowing to the light emitting element EL can be adjusted by the control current Ic of the first pixel driving unit PDU1, the first pixel driving unit PDU1 can be a pulse width modulation unit (or PWM unit) that performs pulse width modulation of the driving current Ids flowing to the light emitting element EL.

[0050] The first pixel driving unit PDU1 may include first to seventh transistors T1 to T7 and a first capacitor C1.

[0051] The first transistor T1 controls a control current Ic flowing between the second electrode and the first electrode in response to a PWM data voltage applied to the gate electrode.

[0052] The second transistor T2 is turned on by a k-th scan write signal of the k-th scan write line GWLk to supply a PWM data voltage of the j-th PWM data line DLj to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the k-th scan write line GWLk, a first electrode may be connected to the j-th PWM data line DLj, and a second electrode may be connected to the first electrode of the first transistor T1.

[0053] The third transistor T3 is turned on by the kth scan initialization signal of the kth scan initialization line GILk and connects the initialization voltage line VIL to the gate electrode of the first transistor T1. Thus, during a period in which the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. At this time, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In particular, since the difference voltage between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the third transistor T3, the third transistor T3 may be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the initialization voltage VINT may be stably applied to the gate electrode of the first transistor T1 regardless of the threshold voltage of the third transistor T3.

[0054] The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. This prevents the voltage of the gate electrode of the first transistor T1 from leaking through the third transistor T3. The gate electrode of the first sub-transistor T31 may be connected to the k-th scan initialization line GILk, the first electrode may be connected to the gate electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the second sub-transistor T32. The gate electrode of the second sub-transistor T32 may be connected to the k-th scan initialization line GILk, the first electrode may be connected to the second electrode of the first sub-transistor T31, and the second electrode may be connected to the initialization voltage line VIL.

[0055] The fourth transistor T4 is turned on by a k-th scan write signal of the k-th scan write line GWLk to connect the gate electrode and the second electrode of the first transistor T1, so that the first transistor T1 is diode-connected and operates like a diode during a period in which the fourth transistor T4 is turned on.

[0056] The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. This prevents the voltage of the gate electrode of the first transistor T1 from leaking through the fourth transistor T4. The gate electrode of the third sub-transistor T41 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the fourth sub-transistor T42. The gate electrode of the fourth sub-transistor T42 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the third sub-transistor T41, and the second electrode may be connected to the gate electrode of the first transistor T1.

[0057] The fifth transistor T5 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect a first electrode of the first transistor T1 to the first power supply wiring VDL1. A gate electrode of the fifth transistor T5 may be connected to the kth PWM light-emitting wiring PWELk, a first electrode may be connected to the first power supply wiring VDL1, and a second electrode may be connected to the first electrode of the first transistor T1.

[0058] The sixth transistor T6 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driving unit PDU3. The sixth transistor T6 has a gate electrode connected to the kth PWM light-emitting wiring PWELk, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the third node N3 of the third pixel driving unit PDU3.

[0059] The seventh transistor T7 may be turned on by a kth scan control signal of the kth scan control line GCLk to supply the gate-off voltage VGH of the gate-off voltage line VGHL to the first node N1 connected to the kth sweep signal line SWPLk. Thus, during a period in which the initialization voltage VINT is applied to the gate electrode of the first transistor T1 and a period in which the PWM data voltage of the jth PWM data line DLj and the threshold voltage Vth1 of the first transistor T1 are programmed, the first capacitor C1 may prevent a voltage change of the gate electrode of the first transistor T1 from being reflected in the kth sweep signal of the kth sweep signal line SWPLk. The gate electrode of the seventh transistor T7 may be connected to the kth scan control line GCLk, a first electrode may be connected to the gate-off voltage line VGHL, and a second electrode may be connected to the first node N1.

[0060] The first capacitor C1 may be disposed between the gate electrode of the first transistor T1 and the first node N1. One electrode of the first capacitor C1 may be coupled to the gate electrode of the first transistor T1, and the other electrode may be coupled to the first node N1.

[0061] The first node N1 may be a junction of the k-th sweep signal wiring SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor C1.

[0062] The second pixel driving unit PDU2 generates a driving current Ids to be applied to the light emitting element EL in response to the first PAM data voltage of the first PAM data line RDL. The second pixel driving unit PDU2 may be a pulse amplitude modulation unit (or PAM unit) that performs pulse amplitude modulation. The second pixel driving unit PDU2 may be a constant current generating unit that generates a constant driving current Ids in response to the first PAM data voltage.

[0063] In addition, the second pixel driving units PDU2 of the first sub-pixels RP can generate the same driving current Ids when the same first PAM data voltage is input, regardless of the luminance of the first sub-pixels RP. Similarly, the second pixel driving units PDU2 of the second sub-pixels GP can generate the same driving current Ids when the same second PAM data voltage is input, regardless of the luminance of the second sub-pixels GP. The third pixel driving units PDU3 of the third sub-pixels BP can generate the same driving current Ids when the same third PAM data voltage is input, regardless of the luminance of the third sub-pixels BP.

[0064] The second pixel driving unit PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor C2.

[0065] The eighth transistor T8 controls a driving current Ids flowing through the light emitting element EL in response to a voltage applied to a gate electrode thereof. The gate electrode of the eighth transistor T8 may be connected to the second capacitor C2, a first electrode of the eighth transistor T8 may be connected to a second electrode of the ninth transistor T9, and a second electrode of the eighth transistor T8 may be connected to a first electrode of the fifteenth transistor T15.

[0066] The ninth transistor T9 is turned on by a kth scan write signal of the kth scan write line GWLk to supply the first PAM data voltage of the first PAM data line RDL to the first electrode of the eighth transistor T8. The ninth transistor T9 may have a gate electrode connected to the kth scan write line GWLk, a first electrode connected to the first PAM data line RDL, and a second electrode connected to the first electrode of the eighth transistor T8.

[0067] The tenth transistor T10 is turned on by the kth scan initialization signal of the kth scan initialization line GILk and connects the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Thus, during a period in which the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. At this time, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In particular, since the difference voltage between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the tenth transistor T10, the tenth transistor T10 may be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the eighth transistor T8. Therefore, when the tenth transistor T10 is turned on, the initialization voltage VINT may be stably applied to the gate electrode of the eighth transistor T8 regardless of the threshold voltage of the tenth transistor T10.

[0068] The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. This prevents the voltage of the gate electrode of the eighth transistor T8 from leaking through the tenth transistor T10. The gate electrode of the fifth sub-transistor T101 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the gate electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the sixth sub-transistor T102. The gate electrode of the sixth sub-transistor T102 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the second electrode of the fifth sub-transistor T101, and the second electrode may be connected to the initialization voltage line VIL.

[0069] The eleventh transistor T11 is turned on by a kth scan write signal of the kth scan write line GWLk to connect the gate electrode and the second electrode of the eighth transistor T8, so that the eighth transistor T8 is diode-connected and operates like a diode during the period in which the eleventh transistor T11 is turned on.

[0070] The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. This prevents the voltage of the gate electrode of the eighth transistor T8 from leaking through the eleventh transistor T11. The gate electrode of the seventh sub-transistor T111 may be connected to the kth scan write line GWLk, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the eighth sub-transistor T112. The gate electrode of the eighth sub-transistor T112 may be connected to the kth scan write line GWLk, the first electrode may be connected to the second electrode of the seventh sub-transistor T111, and the second electrode may be connected to the gate electrode of the eighth transistor T8.

[0071] The twelfth transistor T12 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect a first electrode of the eighth transistor T8 to the second power supply wiring VDL2. The gate electrode of the twelfth transistor T12 may be connected to the kth PWM light-emitting wiring PWELk, a first electrode may be connected to the second power supply wiring VDL2, and a second electrode may be connected to the first electrode of the eighth transistor T8.

[0072] The thirteenth transistor T13 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the first power line VDL1 to the second node N2. The thirteenth transistor T13 has a gate electrode connected to the kth scan control line GCLk, a first electrode connected to the first power line VDL1, and a second electrode connected to the second node N2.

[0073] The fourteenth transistor T14 is turned on by the kth PWM light-emitting signal of the kth PWM light-emitting wire PWELk to connect the second power supply wire VDL2 to the second node N2. Thus, when the fourteenth transistor T14 is turned on, the second power supply voltage VDD2 of the second power supply wire VDL2 may be supplied to the second node N2. The fourteenth transistor T14 may have a gate electrode connected to the kth PWM light-emitting wire PWELk, a first electrode connected to the second power supply wire VDL2, and a second electrode connected to the second node N2.

[0074] The second capacitor C2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor C2 may be coupled to the gate electrode of the eighth transistor T8, and the other electrode may be coupled to the second node N2.

[0075] The second node N2 may be a junction of the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the other electrode of the second capacitor C2.

[0076] The third pixel driving unit PDU3 adjusts the period during which the driving current Ids is applied to the light emitting element EL according to the voltage of the third node N3.

[0077] The third pixel driving unit PDU3 may include fifteenth to nineteenth transistors T15 to T19 and a third capacitor C3.

[0078] The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. When the fifteenth transistor T15 is turned on, the driving current Ids of the eighth transistor T8 is supplied to the light emitting element EL, and when the fifteenth transistor T15 is turned off, the driving current Ids of the eighth transistor T8 is not supplied to the light emitting element EL. Therefore, the turn-on period of the fifteenth transistor T15 may be substantially the same as the light emitting period of the light emitting element EL. The gate electrode of the fifteenth transistor T15 may be connected to the third node N3, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the seventeenth transistor T17.

[0079] The sixteenth transistor T16 is turned on by the k-th scan control signal of the k-th scan control line GCLk to connect the initialization voltage line VIL to the third node N3, so that the third node N3 can be discharged to the initialization voltage VINT of the initialization voltage line VIL during the period in which the sixteenth transistor T16 is turned on.

[0080] The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162. This prevents the voltage of the third node N3 from leaking through the sixteenth transistor T16. The gate electrode of the ninth sub-transistor T161 may be connected to the kth scan control line GCLk, the first electrode may be connected to the third node N3, and the second electrode may be connected to the first electrode of the tenth sub-transistor T162. The gate electrode of the tenth sub-transistor T162 may be connected to the kth scan control line GCLk, the first electrode may be connected to the second electrode of the ninth sub-transistor T161, and the second electrode may be connected to the initialization voltage line VIL.

[0081] The seventeenth transistor T17 is turned on by a k-th PAM light-emitting signal of the k-th PAM light-emitting wiring PAELk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the light-emitting element EL. The gate electrode of the seventeenth transistor T17 may be connected to the k-th PAM light-emitting wiring PAELk, the first electrode of the seventeenth transistor T17 may be connected to the second electrode of the fifteenth transistor T15, and the second electrode of the seventeenth transistor T17 may be connected to the first electrode of the light-emitting element EL.

[0082] The 18th transistor T18 is turned on by a kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to a first electrode of the light emitting element EL. Thus, during a period in which the 18th transistor T18 is turned on, the first electrode of the light emitting element EL may be discharged to the initialization voltage VINT of the initialization voltage line VIL. The 18th transistor T18 has a gate electrode connected to the kth scan control line GCLk, a first electrode connected to the first electrode of the light emitting element EL, and a second electrode connected to the initialization voltage line VIL.

[0083] The 19th transistor T19 is turned on by a test signal of the test signal line TSTL to connect a first electrode of the light emitting element EL to the third power supply line VSL. A gate electrode of the 19th transistor T19 may be connected to the test signal line TSTL, a first electrode of the 19th transistor T19 may be connected to the first electrode of the light emitting element EL, and a second electrode of the 19th transistor T19 may be connected to the third power supply line VSL.

[0084] The third capacitor C3 may be disposed between the third node N3 and the initialization voltage line VIL, and one electrode of the third capacitor C3 may be coupled to the third node N3 and the other electrode may be coupled to the initialization voltage line VIL.

[0085] The third node N3 may be a junction of the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the ninth sub-transistor T161, and one electrode of the third capacitor C3.

[0086] One of the first electrode and the second electrode of each of the first through nineteenth transistors T1 to T19 may be a source electrode, and the remaining one may be a drain electrode. The active layer of each of the first through nineteenth transistors T1 to T19 may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the active layer of each of the first through nineteenth transistors T1 to T19 is polysilicon, it may be formed by a low temperature polysilicon (LTPS) process.

[0087] 5, the first through nineteenth transistors T1 to T19 are mainly formed of P-type MOSFETs, but the embodiments of the present specification are not limited to this. For example, the first through nineteenth transistors T1 to T19 may be formed of N-type MOSFETs.

[0088] Alternatively, in order to block leakage current and improve the black expression capability of the light emitting element EL, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 in the first sub-pixel RP may be formed of N-type MOSFETs. In this case, the gate electrodes of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, and the gate electrodes of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be connected to the kth scan control signal GCLk. The kth scan initialization signal GILk and the kth scan control signal GCLk may have pulses generated by the gate-off voltage VGH. In addition, the active layers of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an oxide semiconductor, and the remaining transistors may be formed of polysilicon.

[0089] Alternatively, one of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the transistor formed of an N-type MOSFET may be formed of an oxide semiconductor, and the transistor formed of a P-type MOSFET may be formed of polysilicon.

[0090] Alternatively, one of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the transistor formed of the N-type MOSFET of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed of an oxide semiconductor, and the transistor formed of the P-type MOSFET may be formed of polysilicon.

[0091] Alternatively, one of the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 that are formed of an N-type MOSFET may be formed of an oxide semiconductor, and the transistor that are formed of a P-type MOSFET may be formed of polysilicon.

[0092] Alternatively, one of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 formed of an N-type MOSFET may be formed of an oxide semiconductor, and the transistor formed of a P-type MOSFET may be formed of polysilicon.

[0093] Also, the second sub-pixel GP and the third sub-pixel BP according to an embodiment may be substantially the same as the first sub-pixel RP described with reference to Fig. 5. Therefore, a description of the second sub-pixel GP and the third sub-pixel BP according to an embodiment will be omitted.

[0094] FIG. 6 is a layout diagram illustrating the active layer, the first gate metal layer, the second gate metal layer, the first source metal layer, and the second source metal layer of the first subpixel shown in FIG. 5 according to an embodiment. FIG. 7 is a layout diagram illustrating the third source metal layer and the pad electrode of FIG. 6. FIG. 8 is a layout diagram illustrating the active layer and the first gate metal layer of FIG. 6. FIG. 9a is a layout diagram illustrating the second gate metal layer of FIG. 6. FIG. 9b is a layout diagram illustrating the active layer, the first gate metal layer, and the second gate metal layer of FIG. 6. FIG. 10 is a layout diagram illustrating the first source metal layer and the second source metal layer of FIG. 6. FIG. 11 is a layout diagram illustrating the first source metal layer, the second source metal layer, and the third source metal layer of FIG. 6.

[0095] 6 to 11, the first subpixel RP may include an active layer ACT, a first gate metal layer, a second gate metal layer, a first source metal layer, a second source metal layer, a third source metal layer, an anode pad electrode APD, and a cathode pad electrode CPD.

[0096] 6, 8, 9a, and 9b, the active layer ACT may include channels CH1 to CH19, source electrodes S1 to S19, and drain electrodes D1 to D19 of the first to nineteenth transistors T1 to T19. The channel, source electrode, and drain electrode of each transistor will be described in detail with reference to FIGS. 12 to 16.

[0097] The first gate metal layer disposed on the active layer ACT may include gate electrodes G1 to G19, a first capacitor electrode CE1, a third capacitor electrode CE3, a fifth capacitor electrode CE5, and first to fifth gate connecting electrodes GCE1 to GCE5 of the first to nineteenth transistors T1 to T19. The first gate electrode G1 of the first transistor T1 may be formed integrally with the first capacitor electrode CE1. The eighth gate electrode G8 of the eighth transistor T8 may be formed integrally with the third capacitor electrode CE3. The fourth gate connecting electrode GCE4 may be formed integrally with the fifth capacitor electrode CE5.

[0098] The second gate metal layer disposed on the first gate metal layer may include a second capacitor electrode CE2, a fourth capacitor electrode CE4, a sixth capacitor electrode CE6, and a third power wiring VSSL. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3 to form a first capacitor C1, the fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3 to form a second capacitor C2, and the sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3 to form a third capacitor C3. In this specification, the first capacitor electrode CE1, the third capacitor electrode CE3, and the fifth capacitor electrode CE5 may be referred to as lower capacitor electrodes, and the second capacitor electrode CE2, the fourth capacitor electrode CE4, and the sixth capacitor electrode CE6 may be referred to as upper capacitor electrodes.

[0099] The third power supply wiring VSSL may be disposed apart from the second capacitor electrode CE2, the fourth capacitor electrode CE4, and the sixth capacitor electrode CE6. The third power supply wiring VSSL may be formed of a single plate surrounding the second capacitor electrode CE2, the fourth capacitor electrode CE4, and the sixth capacitor electrode CE6. The third power supply wiring VSSL may not overlap the first capacitor electrode CE1, the third capacitor electrode CE3, and the fifth capacitor electrode CE5. The third power supply wiring VSSL may overlap the first to third gate connecting electrodes GCE1, GCE2, GCE3, and the fifth and sixth gate connecting electrodes GCE5, GCE6. The third power supply wiring VSSL may not overlap the first gate electrode G1 and the eighth gate electrode G8, and may overlap the gate electrodes of the second to seventh transistors T2 to T7 and the gate electrodes of the ninth to nineteenth transistors T9 to T19.

[0100] The third power wiring VSSL may include a plurality of holes HOL exposing a part of the active layer ACT or a part of the first gate metal layer. The holes HOL may be a region where a contact hole connecting the active layer ACT and the first source metal layer is located, or a region where a contact hole connecting the first gate metal layer and the first source metal layer is located. For example, the third power wiring VSSL may include a hole HOL exposing the second source electrode ("S2" in FIG. 12) of the second transistor T2, and the first data connecting electrode ("DCE1" in FIG. 12) may be connected to the second source electrode S2 through the first data contact hole DCT1 at the hole HOL. As another example, the third power wiring VSSL may include a hole HOL exposing the first gate connecting electrode GCE1, and the k-th scan write wiring GWLk may be connected to the first gate connecting electrode GCE1 through the first gate contact hole GCT1 at the hole HOL. As shown in Fig. 9b, holes HOL may be formed in the regions where the second to eleventh, thirteenth, fourteenth, sixteenth, seventeenth, nineteenth, twenty-first, twenty-third, and twenty-fourth contact holes CT2 to CT11, CT13, CT14, CT16, CT17, CT19, CT21, CT23, and CT24, the first and third data contact holes DCT1, DCT3, the first to third gate contact holes GCT1, GCT2, and GCT3, and the second power contact hole VCT2 are located. In one embodiment, as shown in Fig. 9b, a hole may be formed in the region where the first power contact hole VCT1 is located.

[0101] In this specification, the third power supply wiring VSSL may be referred to as a low potential wiring, similar to the third power supply wiring VSL in Fig. 5. As will be described later, the third power supply wiring VSSL may be connected to a cathode pad electrode ("CPD" in Fig. 20) through a pad contact hole ("PCT" in Fig. 20) and may receive a third power supply voltage ("VSS" in Fig. 4).

[0102] Referring to Figures 6, 10 and 11 together, the first source metal layer arranged on the second gate metal layer may include an initialization voltage wiring VIL, a kth scan initialization wiring GILk, a kth scan write wiring GWLk, a kth PWM light emission wiring PWELk, a first horizontal power supply wiring HVDL, a gate off voltage wiring VGHL, a kth sweep signal wiring SWPLk, a kth scan control wiring GCLk, a kth PAM light emission wiring PAELk, a test signal wiring TSTL, and a third horizontal power supply wiring HVSL extending in a first direction DR1. The initialization voltage line VIL, the kth scan initialization line GILk, the kth scan write line GWLk, the kth PWM light emission line PWELk, the first horizontal power line HVDL, the gate-off voltage line VGHL, the kth sweep signal line SWPLk, the kth scan control line GCLk, the kth PAM light emission line PAELk, the test signal line TSTL, and the third horizontal power line HVSL may be spaced apart in the second direction DR2. The first source metal layer may further include first and second data connecting electrodes DCE1, DCE2, and first to seventh connecting electrodes CCE1 to CCE7. The first data connecting electrode DCE1 may be connected to the jth data line DLj, and the second data connecting electrode DCE2 may be connected to the first PAM data line RDL.

[0103] The second source metal layer disposed on the first source metal layer may include a j-th data line DLj, a first vertical power line VVDL, and a first PAM data line RDL extending in the second direction DR2. Although not shown, the second PAM data line GDL and the third PAM data line BDL in FIG. 4 may extend in the second direction DR2. The j-th data line DLj, the first vertical power line VVDL, the first PAM data line RDL, the second PAM data line GDL, and the third PAM data line BDL may be spaced apart in the first direction DR1. The second source metal layer may further include a first anode connecting electrode ANDE1 and a second power connecting electrode VDCE. The first anode connecting electrode ANDE1 may be connected to the p-type semiconductor PSEM of the light emitting element EL via the second anode connecting electrode ANDE2 and the anode pad electrode APD (see FIG. 20). The second power supply connecting electrode VDCE may be connected to the second power supply wiring VDL2 (see FIG. 18).

[0104] 7 and 11, the third source metal layer disposed on the second source metal layer may include a second power wiring VDL2, a cathode connecting electrode VSCE, and a second anode connecting electrode ANDE2. The cathode connecting electrode VSCE may be connected to the n-type semiconductor NSEM of the light emitting element EL via the cathode pad electrode CPD, and the second anode connecting electrode ANDE2 may connect the first anode connecting electrode ANDE1 and the anode pad electrode APD (see FIG. 20). In one embodiment, the cathode connecting electrode VSCE may be omitted.

[0105] The second power wiring VDL2 may be disposed apart from the cathode connecting electrode VSCE and the second anode connecting electrode ANDE2 and may be formed as a single plate surrounding the cathode connecting electrode VSCE and the second anode connecting electrode ANDE2. The second power wiring VDL2 may include an opening OP exposing a portion of the third power wiring VSSL of the second gate metal layer. The cathode pad electrode CPD may be connected to the third power wiring VSSL through a pad contact hole PCT at the opening OP (see FIG. 20). The opening OP may overlap the third power wiring VSSL and not overlap the electrode and wiring of the second source metal layer.

[0106] In this specification, the first horizontal power supply wiring HVDL and the first vertical power supply wiring VVDL can be wirings to which a first power supply voltage ("VDD1" in FIG. 4) is applied, the second power supply wiring VDL2 can be wirings to which a second power supply voltage ("VDD2" in FIG. 4) is applied, and the third power supply wiring VSSL and the third horizontal power supply wiring HVSL can be wirings to which a third power supply voltage ("VSS" in FIG. 4) is applied.

[0107] Figures 12 and 13 are enlarged layout diagrams showing in detail area A in Figures 6 and 7. Figure 14 is an enlarged layout diagram showing in detail area B in Figure 6. Figures 15 and 16 are enlarged layout diagrams showing in detail area C in Figures 6 and 7.

[0108] 12 shows the active layer, the first gate metal layer, the second gate metal layer, the first source metal layer, and the second source metal layer of FIG. 6, and FIG. 13 further shows the second power wiring VDL2 and the fifth power contact hole VCT5 of the third source metal layer in FIG. 12. FIG. 14 shows the active layer, the first gate metal layer, the second gate metal layer, the first source metal layer, and the second source metal layer of FIG. 6. FIG. 15 shows the active layer, the first gate metal layer, the second gate metal layer, the first source metal layer, and the second source metal layer, and FIG. 16 further shows the second power wiring VDL2, the cathode connecting electrode VSCE, and the second anode connecting electrode ANDE2 of the third source metal layer in FIG. 15, and the pad electrode.

[0109] 12 to 16, the first sub-pixel RP includes first to nineteenth transistors T1 to T19, first to sixth capacitor electrodes CE1 to CE6, first to fifth gate connecting electrodes GCE1 to GCE5, first and second data connecting electrodes DCE1, DCE2, first to seventh connecting electrodes CCE1 to CCE7, a first anode connecting electrode ANDE1, a second power connecting electrode VDCE, a second anode connecting electrode ANDE2, and a cathode connecting electrode VSCE. The first sub-pixel RP further includes a cathode pad electrode CPD overlapping the cathode connecting electrode VSCE, an anode pad electrode APD overlapping the second anode connecting electrode ANDE2, and a light emitting element EL.

[0110] The first transistor T1 includes a first channel CH1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first channel CH1 may extend in a first direction DR1. The first channel CH1 may overlap the first gate electrode G1 in a third direction DR3. The first gate electrode G1 may be connected to the first connecting electrode CCE1 through a first contact hole CT1. The first gate electrode G1 may be integrally formed with the first capacitor electrode CE1. The first gate electrode G1 may overlap the second capacitor electrode CE2 in the third direction DR3. The first source electrode S1 may be disposed on one side of the first channel CH1, and the first drain electrode D1 may be disposed on the other side of the first channel CH1. The first source electrode S1 may be connected to the second drain electrode D2 and the fifth drain electrode D5. The first drain electrode D1 may be connected to the third sub-source electrode S41 and the sixth source electrode S6. The first source electrode S1 and the first drain electrode D1 may not overlap the first gate electrode G1 in the third direction DR3, and may overlap the second capacitor electrode CE2 in the third direction DR3.

[0111] The second transistor T2 includes a second channel CH2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second channel CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second gate electrode G2 may be formed integrally with the first gate connecting electrode GCE1. The second source electrode S2 may be disposed on one side of the second channel CH2, and the second drain electrode D2 may be disposed on the other side of the second channel CH2. The second source electrode S2 may be connected to the first data connecting electrode DCE1 through the first data contact hole DCT1. The second drain electrode D2 may be connected to the first source electrode S1. The second source electrode S2 and the second drain electrode D2 may not overlap with the second gate electrode G2 in the third direction DR3. The second drain electrode D2 may extend in the second direction DR2. The second drain electrode D2 may be connected to the first source electrode S1.

[0112] The first sub-transistor T31 of the third transistor T3 includes a first sub-channel CH31, a first sub-gate electrode G31, a first sub-source electrode S31, and a first sub-drain electrode D31. The first sub-channel CH31 may overlap the first sub-gate electrode G31 in the third direction DR3. The first sub-gate electrode G31 may be formed integrally with the second gate connecting electrode GCE2. The first sub-source electrode S31 may be disposed on one side of the first sub-channel CH31, and the first sub-drain electrode D31 may be disposed on the other side of the first sub-channel CH31. The first sub-source electrode S31 may be connected to the fourth sub-drain electrode D42, and the first sub-drain electrode D31 may be connected to the second sub-source electrode S32. The first sub-source electrode S31 and the first sub-drain electrode D31 may not overlap the first sub-gate electrode G31. The first sub-source electrode S31 may overlap the k-th scan write line GWLk in the third direction DR3, and the first sub-drain electrode D31 may overlap the initialization voltage line VIL in the third direction DR3.

[0113] The second sub-transistor T32 of the third transistor T3 includes a second sub-channel CH32, a second sub-gate electrode G32, a second sub-source electrode S32, and a second sub-drain electrode D32. The second sub-channel CH32 may overlap the second sub-gate electrode G32 in the third direction DR3. The second sub-gate electrode G32 may be formed integrally with the second gate connecting electrode GCE2. The second sub-source electrode S32 may be disposed on one side of the second sub-channel CH32, and the second sub-drain electrode D32 may be disposed on the other side of the second sub-channel CH32. The second sub-source electrode S32 may be connected to the first sub-drain electrode D31, and the second sub-drain electrode D32 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The second sub-source electrode S32 and the second sub-drain electrode D32 may not overlap the second sub-gate electrode G32. The second sub-source electrode S32 and the second sub-drain electrode D32 may overlap the initialization voltage line VIL in the third direction DR3.

[0114] The third sub-transistor T41 of the fourth transistor T4 includes a third sub-channel CH41, a third sub-gate electrode G41, a third sub-source electrode S41, and a third sub-drain electrode D41. The third sub-channel CH41 may overlap the third sub-gate electrode G41 in the third direction DR3. The third sub-gate electrode G41 may be formed integrally with the first gate connecting electrode GCE1. The third sub-source electrode S41 may be disposed on one side of the third sub-channel CH41, and the first sub-drain electrode D31 may be disposed on the other side of the third sub-channel CH41. The third sub-source electrode S41 may be connected to the first drain electrode D1, and the third sub-drain electrode D41 may be connected to the fourth sub-source electrode S42. The third sub-source electrode S41 and the third sub-drain electrode D41 may not overlap the third sub-gate electrode G41.

[0115] The fourth sub-transistor T42 of the fourth transistor T4 includes a fourth sub-channel CH42, a fourth sub-gate electrode G42, a fourth sub-source electrode S42, and a fourth sub-drain electrode D42. The fourth sub-channel CH42 may overlap with the fourth sub-gate electrode G42 in the third direction DR3. The fourth sub-gate electrode G42 may be formed integrally with the first gate connecting electrode GCE1. The fourth sub-source electrode S42 may be disposed on one side of the fourth sub-channel CH42, and the fourth sub-drain electrode D42 may be disposed on the other side of the fourth sub-channel CH42. The fourth sub-source electrode S42 may be connected to the third sub-drain electrode D41, and the fourth sub-drain electrode D42 may be connected to the first sub-source electrode S31. The fourth sub-source electrode S42 and the fourth sub-drain electrode D42 may not overlap with the fourth sub-gate electrode G42.

[0116] The fifth transistor T5 includes a fifth channel CH5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth channel CH5 may overlap the fifth gate electrode G5 in the third direction DR3. The fifth gate electrode G5 may be formed integrally with the sixth gate connecting electrode GCE6. The fifth source electrode S5 may be disposed on one side of the fifth channel CH5, and the fifth drain electrode D5 may be disposed on the other side of the fifth channel CH5. The fifth source electrode S5 may be connected to the first horizontal power line HVDL through the second power contact hole VCT2. The fifth drain electrode D5 may be connected to the first source electrode S1. The fifth source electrode S5 and the fifth drain electrode D5 may not overlap the fifth gate electrode G5 in the third direction DR3. The fifth drain electrode D5 may overlap an extension of the second capacitor electrode CE2 in the third direction DR3.

[0117] The sixth transistor T6 includes a sixth channel CH6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth channel CH6 may overlap with the sixth gate electrode G6 in the third direction DR3. The sixth gate electrode G6 may be formed integrally with the sixth gate connecting electrode GCE6. The sixth source electrode S6 may be disposed on one side of the sixth channel CH6, and the sixth drain electrode D6 may be disposed on the other side of the sixth channel CH6. The sixth source electrode S6 may be connected to the first drain electrode D1. The sixth drain electrode D6 may be connected to the fourth connecting electrode CCE4 through a tenth contact hole CT10. The sixth source electrode S6 and the sixth drain electrode D6 may not overlap with the sixth gate electrode G6 in the third direction DR3. The sixth drain electrode D6 may overlap with the second connecting electrode CCE2 and the first horizontal power line HVDL in the third direction DR3.

[0118] The seventh transistor T7 includes a seventh channel CH7, a seventh gate electrode G7, a seventh source electrode S7, and a seventh drain electrode D7. The seventh channel CH7 may overlap with the seventh gate electrode G7 in the third direction DR3. The seventh gate electrode G7 may be integrally formed with the third gate connecting electrode GCE3. The seventh gate electrode G7 may overlap with the initialization voltage line VIL in the third direction DR3. The seventh source electrode S7 may be disposed on one side of the seventh channel CH7, and the seventh drain electrode D7 may be disposed on the other side of the seventh channel CH7. The seventh source electrode S7 may be connected to the gate-off voltage line VGHL via a seventh contact hole CT7. The seventh drain electrode D7 may be connected to the k-th sweep signal line SWPLk via a sixth contact hole CT6. The seventh source electrode S7 and the seventh drain electrode D7 may not overlap with the seventh gate electrode G7 in the third direction DR3.

[0119] The eighth transistor T8 includes an eighth channel CH8, an eighth gate electrode G8, an eighth source electrode S8, and an eighth drain electrode D8. The eighth channel CH8 may overlap with the eighth gate electrode G8 in the third direction DR3. The eighth gate electrode G8 may extend in the second direction DR2. The eighth gate electrode G8 may be formed integrally with the third capacitor electrode CE3. The eighth source electrode S8 may be disposed on one side of the eighth channel CH8, and the eighth drain electrode D8 may be disposed on the other side of the eighth channel CH8. The eighth source electrode S8 may be connected to the ninth drain electrode D9 and the twelfth drain electrode D12. The eighth drain electrode D8 may be connected to the seventh sub-source electrode S111. The eighth source electrode S8 and the eighth drain electrode D8 may not overlap with the eighth gate electrode G8 in the third direction DR3.

[0120] The ninth transistor T9 includes a ninth channel CH9, a ninth gate electrode G9, a ninth source electrode S9, and a ninth drain electrode D9. The ninth channel CH9 may overlap with the ninth gate electrode G9 in the third direction DR3. The ninth gate electrode G9 may extend in the second direction DR2. The ninth gate electrode G9 may be formed integrally with the first gate connecting electrode GCE1. The ninth source electrode S9 may be disposed on one side of the ninth channel CH9, and the ninth drain electrode D9 may be disposed on the other side of the ninth channel CH9. The ninth source electrode S9 may be connected to the second data connecting electrode DCE2 via the third data contact hole DCT3. The ninth drain electrode D9 may be connected to the eighth source electrode S8. The ninth source electrode S9 and the ninth drain electrode D9 may not overlap with the ninth gate electrode G9 in the third direction DR3.

[0121] The fifth sub-transistor T101 of the tenth transistor T10 includes a fifth sub-channel CH101, a fifth sub-gate electrode G101, a fifth sub-source electrode S101, and a fifth sub-drain electrode D101. The fifth sub-channel CH101 may overlap the fifth sub-gate electrode G101 in the third direction DR3. The fifth sub-gate electrode G101 may be formed integrally with the second gate connecting electrode GCE2. The fifth sub-source electrode S101 may be disposed on one side of the fifth sub-channel CH101, and the fifth sub-drain electrode D101 may be disposed on the other side of the fifth sub-channel CH101. The fifth sub-source electrode S101 may be connected to the eighth sub-drain electrode D112, and the fifth sub-drain electrode D101 may be connected to the sixth sub-source electrode S102. The fifth sub-source electrode S101 and the fifth sub-drain electrode D101 may not overlap the fifth sub-gate electrode G101. The fifth sub-source electrode S101 may overlap the k-th scan write line GWLk in the third direction DR3, and the fifth sub-drain electrode D101 may overlap the initialization voltage line VIL in the third direction DR3.

[0122] The sixth sub-transistor T102 of the tenth transistor T10 includes a sixth sub-channel CH102, a sixth sub-gate electrode G102, a sixth sub-source electrode S102, and a sixth sub-drain electrode D102. The sixth sub-channel CH102 may overlap with the sixth sub-gate electrode G102 in the third direction DR3. The sixth sub-gate electrode G102 may be formed integrally with the second gate connecting electrode GCE2. The sixth sub-source electrode S102 may be disposed on one side of the sixth sub-channel CH102, and the sixth sub-drain electrode D102 may be disposed on the other side of the sixth sub-channel CH102. The sixth sub-source electrode S102 may be connected to the fifth sub-drain electrode D101, and the sixth sub-drain electrode D102 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may not overlap with the sixth sub-gate electrode G102. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may overlap the initialization voltage line VIL in the third direction DR3.

[0123] The seventh sub-transistor T111 of the eleventh transistor T11 includes a seventh sub-channel CH111, a seventh sub-gate electrode G111, a seventh sub-source electrode S111, and a seventh sub-drain electrode D111. The seventh sub-channel CH111 may overlap with the seventh sub-gate electrode G111 in the third direction DR3. The seventh sub-gate electrode G111 may be formed integrally with the first gate connecting electrode GCE1. The seventh sub-source electrode S111 may be disposed on one side of the seventh sub-channel CH111, and the seventh sub-drain electrode D111 may be disposed on the other side of the seventh sub-channel CH111. The seventh sub-source electrode S111 may be connected to the eighth drain electrode D8, and the seventh sub-drain electrode D111 may be connected to the eighth sub-source electrode S112. The seventh sub-source electrode S111 and the seventh sub-drain electrode D111 may not overlap with the seventh sub-gate electrode G111.

[0124] The eighth sub-transistor T112 of the eleventh transistor T11 includes an eighth sub-channel CH112, an eighth sub-gate electrode G112, an eighth sub-source electrode S112, and an eighth sub-drain electrode D112. The eighth sub-channel CH112 may overlap with the eighth sub-gate electrode G112 in the third direction DR3. The eighth sub-gate electrode G112 may be formed integrally with the first gate connecting electrode GCE1. The eighth sub-source electrode S112 may be disposed on one side of the eighth sub-channel CH112, and the eighth sub-drain electrode D112 may be disposed on the other side of the eighth sub-channel CH112. The eighth sub-source electrode S112 may be connected to the seventh sub-drain electrode D111, and the eighth sub-drain electrode D112 may be connected to the fifth sub-source electrode S101. The eighth sub-source electrode S112 and the eighth sub-drain electrode D112 may not overlap with the eighth sub-gate electrode G112.

[0125] The twelfth transistor T12 includes a twelfth channel CH12, a twelfth gate electrode G12, a twelfth source electrode S12, and a twelfth drain electrode D12. The twelfth channel CH12 may overlap the twelfth gate electrode G12 in the third direction DR3. The twelfth gate electrode G12 may be integrally formed with the third gate connecting electrode GCE3. The twelfth source electrode S12 may be disposed on one side of the twelfth channel CH12, and the twelfth drain electrode D12 may be disposed on the other side of the twelfth channel CH12. The twelfth source electrode S12 may be connected to the fifth connecting electrode CCE5 via an eleventh contact hole CT11. The twelfth source electrode S12 and the twelfth drain electrode D12 may not overlap the twelfth gate electrode G12 in the third direction DR3.

[0126] The thirteenth transistor T13 includes a thirteenth channel CH13, a thirteenth gate electrode G13, a thirteenth source electrode S13, and a thirteenth drain electrode D13. The thirteenth channel CH13 may overlap with the thirteenth gate electrode G13 in the third direction DR3. The thirteenth gate electrode G13 may be integrally formed with the third gate connecting electrode GCE3. The thirteenth source electrode S13 may be disposed on one side of the thirteenth channel CH13, and the thirteenth drain electrode D13 may be disposed on the other side of the thirteenth channel CH13. The thirteenth source electrode S13 may be connected to the first horizontal power line HVDL via a second power contact hole VCT2. The thirteenth drain electrode D13 may be connected to the second connecting electrode CCE2 via a third contact hole CT3. The thirteenth source electrode S13 and the thirteenth drain electrode D13 may not overlap with the thirteenth gate electrode G13 in the third direction DR3.

[0127] The fourteenth transistor T14 includes a fourteenth channel CH14, a fourteenth gate electrode G14, a fourteenth source electrode S14, and a fourteenth drain electrode D14. The fourteenth channel CH14 may overlap with the fourteenth gate electrode G14 in the third direction DR3. The fourteenth gate electrode G14 may be integrally formed with the sixth gate connecting electrode GCE6. The fourteenth source electrode S14 may be disposed on one side of the fourteenth channel CH14, and the fourteenth drain electrode D14 may be disposed on the other side of the fourteenth channel CH14. The fourteenth source electrode S14 may be connected to the fifth connecting electrode CCE5 via an eleventh contact hole CT11. The fourteenth drain electrode D14 may be connected to the second connecting electrode CCE2 via a fourth contact hole CT4. The fourteenth source electrode S14 and the fourteenth drain electrode D14 may not overlap with the fourteenth gate electrode G14 in the third direction DR3.

[0128] The fifteenth transistor T15 includes a fifteenth channel CH15, a fifteenth gate electrode G15, a fifteenth source electrode S15, and a fifteenth drain electrode D15. The fifteenth channel CH15 may overlap with the fifteenth gate electrode G15 in the third direction DR3. The fifteenth gate electrode G15 may be formed integrally with the fifth capacitor electrode CE5. The fifteenth source electrode S15 may be disposed on one side of the fifteenth channel CH15, and the fifteenth drain electrode D15 may be disposed on the other side of the fifteenth channel CH15. The fifteenth source electrode S15 may be connected to the eighth drain electrode D8. The fifteenth drain electrode D15 may be connected to the seventeenth source electrode S17. The fifteenth source electrode S15 and the fifteenth drain electrode D15 may not overlap with the fifteenth gate electrode G15 in the third direction DR3.

[0129] The ninth sub-transistor T161 of the sixteenth transistor T16 includes a ninth sub-channel CH161, a ninth sub-gate electrode G161, a ninth sub-source electrode S161, and a ninth sub-drain electrode D161. The ninth sub-channel CH161 may overlap the ninth sub-gate electrode G161 in the third direction DR3. The ninth sub-gate electrode G161 may be formed integrally with the third gate connecting electrode GCE3. The ninth sub-source electrode S161 may be disposed on one side of the ninth sub-channel CH161, and the ninth sub-drain electrode D161 may be disposed on the other side of the ninth sub-channel CH161. The ninth sub-source electrode S161 may be connected to the fourth connecting electrode CCE4 through a tenth contact hole CT10, and the ninth sub-drain electrode D161 may be connected to the tenth sub-source electrode S162. The ninth sub-source electrode S161 and the ninth sub-drain electrode D161 may not overlap the ninth sub-gate electrode G161.

[0130] The tenth sub-transistor T162 of the sixteenth transistor T16 includes a tenth sub-channel CH162, a tenth sub-gate electrode G162, a tenth sub-source electrode S162, and a tenth sub-drain electrode D162. The tenth sub-channel CH162 may overlap with the tenth sub-gate electrode G162 in the third direction DR3. The tenth sub-gate electrode G162 may be integrally formed with the third gate connecting electrode GCE3. The tenth sub-source electrode S162 may be disposed on one side of the tenth sub-channel CH162, and the tenth sub-drain electrode D162 may be disposed on the other side of the tenth sub-channel CH162. The tenth sub-source electrode S162 may be connected to the ninth sub-drain electrode D161, and the tenth sub-drain electrode D162 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. The tenth sub-source electrode S162 and the tenth sub-drain electrode D162 do not have to overlap with the tenth sub-gate electrode G162.

[0131] The 17th transistor T17 includes a 17th channel CH17, a 17th gate electrode G17, a 17th source electrode S17, and a 17th drain electrode D17. The 17th channel CH17 may overlap with the 17th gate electrode G17 in the third direction DR3. The 17th gate electrode G17 may be integrally formed with the fifth gate connecting electrode GCE5. The 17th source electrode S17 may be disposed on one side of the 17th channel CH17, and the 17th drain electrode D17 may be disposed on the other side of the 17th channel CH17. The 17th source electrode S17 may be connected to the 15th drain electrode D15. The 17th drain electrode D17 may be connected to the seventh connecting electrode CCE7 through a 16th contact hole CT16. The 17th source electrode S17 and the 17th drain electrode D17 may not overlap with the 17th gate electrode G17 in the third direction DR3.

[0132] The 18th transistor T18 includes an 18th channel CH18, an 18th gate electrode G18, an 18th source electrode S18, and an 18th drain electrode D18. The 18th channel CH18 may overlap with the 18th gate electrode G18 in the third direction DR3. The 18th gate electrode G18 may be integrally formed with the third gate connecting electrode GCE3. The 18th source electrode S18 may be disposed on one side of the 18th channel CH18, and the 18th drain electrode D18 may be disposed on the other side of the 18th channel CH18. The 18th source electrode S18 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. The 18th drain electrode D18 may be connected to the seventh connecting electrode CCE7 via a sixteenth contact hole CT16. The 18th source electrode S18 and the 18th drain electrode D18 may not overlap with the 18th gate electrode G18 in the third direction DR3.

[0133] The 19th transistor T19 includes a 19th channel CH19, a 19th gate electrode G19, a 19th source electrode S19, and a 19th drain electrode D19. The 19th channel CH19 may overlap with the 19th gate electrode G19 in the third direction DR3. The 19th gate electrode G19 may be connected to the test signal line TSTL via a 23rd contact hole CT23. The 19th source electrode S19 may be disposed on one side of the 19th channel CH19, and the 19th drain electrode D19 may be disposed on the other side of the 19th channel CH19. The 19th source electrode S19 may be connected to the third connecting electrode CCE3 via a 21st contact hole CT21. The 19th drain electrode D19 may be connected to the third horizontal power line HVSL via a 24th contact hole CT24. The 19th source electrode S19 and the 19th drain electrode D19 may not overlap with the 19th gate electrode G19 in the third direction DR3.

[0134] The first capacitor electrode CE1 may be formed integrally with the first gate electrode G1. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3. The first capacitor electrode CE1 may be one electrode of the first capacitor C1, and the second capacitor electrode CE2 may be the other electrode of the first capacitor C1.

[0135] The second capacitor electrode CE2 includes a hole exposing the first gate electrode G1, and the first connecting electrode CCE1 may be connected to the first gate electrode G1 through the first contact hole CT1.

[0136] The second capacitor electrode CE2 may include an extension extending in the second direction DR2. The extension of the second capacitor electrode CE2 may intersect with the kth PWM light emitting wiring PWELk and the first horizontal power supply wiring HVDL. The extension of the second capacitor electrode CE2 may be connected to the kth sweep signal wiring SWPLk through a fifth contact hole CT5.

[0137] The third capacitor electrode CE3 may be formed integrally with the eighth gate electrode G8. The fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3. The third capacitor electrode CE3 may be one electrode of the second capacitor C2, and the fourth capacitor electrode CE4 may be the other electrode of the second capacitor C2.

[0138] The fourth capacitor electrode CE4 includes a hole exposing the eighth gate electrode G8, and the sixth connecting electrode CCE6 may be connected to the eighth gate electrode G8 through a twelfth contact hole CT12 in the hole.

[0139] The fifth capacitor electrode CE5 may be integrally formed with the fourth gate connecting electrode GCE4 and the fifteenth gate electrode G15. The sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. The fifth capacitor electrode CE5 may be one electrode of the third capacitor C3, and the sixth capacitor electrode CE6 may be the other electrode of the third capacitor C3. The sixth capacitor electrode CE6 may be connected to the initialization voltage line VIL via an eighteenth contact hole CT18.

[0140] The first gate connecting electrode GCE1 may be connected to the kth scan write line GWLk through the first gate contact hole GCT1 and the third gate contact hole GCT3. The second gate connecting electrode GCE2 may be connected to the kth scan initialization line GILk through the second gate contact hole GCT2. The third gate connecting electrode GCE3 may be connected to the kth scan control line GCLk through the eighth contact hole CT8. The fourth gate connecting electrode GCE4 may be connected to the fourth connecting electrode CCE4 through the seventeenth contact hole CT17. The fifth gate connecting electrode GCE5 may be connected to the kth PAM light emission line PAELk through the nineteenth contact hole CT19. The sixth gate connecting electrode GCE6 may be connected to the kth PWM light emission line PWELk through the fourteenth contact hole CT14. The first gate connecting electrode GCE1, the second gate connecting electrode GCE2, the third gate connecting electrode GCE3, the fifth gate connecting electrode GCE5, and the sixth gate connecting electrode GCE6 may overlap the third power supply line VSSL in the third direction DR3.

[0141] The first data connecting electrode DCE1 may be connected to the second source electrode S2 through the first data contact hole DCT1 and may be connected to the j-th data line DLj through the second data contact hole DCT2. The first data connecting electrode DCE1 may connect the second source electrode S2 and the j-th data line DLj.

[0142] The second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through a third data contact hole DCT3 and may be connected to the first PAM data line RDL through a fourth data contact hole DCT4. The second data connecting electrode DCE2 may connect the ninth source electrode S9 and the first PAM data line RDL.

[0143] The first connecting electrode CCE1 may extend in a second direction DR2, may be connected to the first gate electrode G1 through a first contact hole CT1, and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 through a second contact hole CT2.

[0144] The second connecting electrode CCE2 may extend in the first direction DR1. The second connecting electrode CCE2 may be connected to the thirteenth drain electrode D13 through the third contact hole CT3, to the fourteenth drain electrode D14 through the fourth contact hole CT4, and to the fourth capacitor electrode CE4 through the fifteenth contact hole CT15.

[0145] The third connecting electrode CCE3 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 and may be connected to the first anode connecting electrode ANDE1 through a twenty-second contact hole CT22.

[0146] The fourth connecting electrode CCE4 may extend in the first direction DR1, may be connected to the sixth drain electrode D6 and the ninth sub-source electrode S161 through a tenth contact hole CT10, and may be connected to the fourth gate connecting electrode GCE4 through a seventeenth contact hole CT17.

[0147] The fifth connecting electrode CCE5 may extend in the first direction DR1. The fifth connecting electrode CCE5 may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11, and may be connected to the second power connecting electrode VDCE through a fourth power contact hole VCT4.

[0148] The sixth connecting electrode CCE6 may extend in the second direction DR2, may be connected to the third capacitor electrode CE3 through a twelfth contact hole CT12, and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 through a thirteenth contact hole CT13.

[0149] The seventh connecting electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16. The seventh connecting electrode CCE7 may be connected to the first anode connecting electrode ANDE1 through a twentieth contact hole CT20.

[0150] The first anode connecting electrode ANDE1 may extend in the second direction DR2. The first anode connecting electrode ANDE1 may be connected to the seventh connecting electrode CCE7 through a twentieth contact hole CT20 and to the third connecting electrode CCE3 through a twenty-second contact hole CT22. The first anode connecting electrode ANDE1 may be connected to the second anode connecting electrode ANDE2 through a sixth power contact hole VCT6.

[0151] The second power connecting electrode VDCE may extend in the second direction DR2, may be connected to the fifth connecting electrode CCE5 through a fourth power contact hole VCT4, and may be connected to the second power wiring VDL2 through a fifth power contact hole VCT5.

[0152] The second anode connecting electrode ANDE2 may extend in a second direction DR2. The second anode connecting electrode ANDE2 may be connected to the first anode connecting electrode ANDE1 through a sixth power contact hole VCT6. The second anode connecting electrode ANDE2 may overlap the anode pad electrode APD.

[0153] The cathode-connecting electrode VSCE extends in the second direction DR2 and is adjacent to the second anode-connecting electrode ANDE2. The cathode-connecting electrode VSCE may overlap the cathode pad electrode CPD. The size of the cathode-connecting electrode VSCE may be smaller or larger than the size of the second anode-connecting electrode ANDE2. Here, "size" may be the length or area in the second direction DR2.

[0154] The anode pad electrode APD may extend in the second direction DR2 and overlap the second anode connecting electrode ANDE2 in the third direction DR3. The anode pad electrode APD may be in contact with the second anode connecting electrode ANDE2.

[0155] The cathode pad electrode CPD may include a trunk CPDa extending in a first direction DR1, and a branch portion CPDb branching from the trunk CPDa and extending in a second direction DR2. The trunk CPDa of the cathode pad electrode CPD may be coupled to the third power supply wiring VSSL via a pad contact hole PCT. A portion of the trunk CPDa and the pad contact hole PCT may be disposed within an opening OP of the third power supply wiring VSSL. The branch portion CPDb may overlap the cathode connecting electrode VSCE in the third direction DR3. As another example, when the cathode connecting electrode VSCE is omitted, the branch portion CPDb may contact the second planarization film ("180" in FIG. 21).

[0156] The anode pad electrode APD and the branch portion CPDb of the cathode pad electrode CPD are adjacent to each other in the first direction DR1. For example, the anode pad electrode APD may be disposed on the left side of the branch portion CPDb. Without being limited thereto, the anode pad electrode APD may be disposed on the right side of the branch portion CPDb. The length of the anode pad electrode APD in the second direction DR2 may be shorter than the length of the branch portion CPDb of the cathode pad electrode CPD in the second direction DR2.

[0157] The anode pad electrode APD may be connected to a first electrode of the light emitting element EL, and the cathode pad electrode CPD may be connected to a second electrode of the light emitting element EL.

[0158] Although not shown, the cathode pad electrode CPD extends in the first direction DR1 and can be arranged not only in the first subpixel RP but also in the second subpixel GP and the third subpixel BP adjacent to the first subpixel RP in the first direction DR1. A trunk CPDa of the cathode pad electrode CPD extends in the first direction DR1 across the multiple subpixels RP, GP, BP, and multiple branch portions CPDb branching from the trunk CPDa can be arranged in each of the multiple subpixels RP, GP, BP.

[0159] Fig. 17 is a cross-sectional view taken along line I-I' in Fig. 6 and Fig. 7. Fig. 18 is a cross-sectional view taken along line II-II' in Fig. 6 and Fig. 7. Fig. 19 is a cross-sectional view taken along line III-III' in Fig. 6 and Fig. 7. Fig. 20 is a cross-sectional view taken along line IV-IV' and V-V' in Fig. 6 and Fig. 7.

[0160] 17 to 20, a buffer film BF may be disposed on a substrate SUB. The substrate SUB may be made of an insulating material such as glass or polymer resin. For example, when the substrate SUB is made of polymer resin, it may include polyimide. The substrate SUB may be a flexible substrate capable of bending, folding, rolling, and the like.

[0161] The buffer film BF is a film for protecting the transistors of the thin film transistor layer TFTL and the active layer of the light-emitting element EL from moisture that may penetrate through the substrate SUB, which is susceptible to moisture permeation. The buffer film BF is made of a plurality of inorganic films that are alternately laminated. For example, the buffer film BF may be formed of a multi-layer film in which one or more inorganic films selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated.

[0162] An active layer may be disposed on the buffer film BF. The active layer includes the first to nineteenth channels CH1 to CH19, the first to nineteenth source electrodes S1 to S19, and the first to nineteenth drain electrodes D1 to D19 of the first to nineteenth transistors T1 to T19. The active layer may include polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. The first to nineteenth source electrodes S1 to S19 and the first to nineteenth drain electrodes D1 to D19 may be regions of silicon semiconductor or oxide semiconductor doped with ions or impurities to have conductivity. Note that a light-shielding layer may be omitted between the buffer film BF and the active layer. In other words, the buffer film BF may be in direct contact with the first to nineteenth channels CH1 to CH19, the first to nineteenth source electrodes S1 to S19, and the first to nineteenth drain electrodes D1 to D19 of the active layer.

[0163] The first to nineteenth channels CH1 to CH19 may overlap the first to nineteenth gate electrodes G1 to G19 in the third direction DR3, respectively. The first to nineteenth source electrodes S1 to S19 and the first to nineteenth drain electrodes D1 to D19 do not have to overlap the first to nineteenth gate electrodes G1 to G19 in the third direction DR3.

[0164] A gate insulating layer 130 may be disposed on the active layer. The gate insulating layer 130 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The gate insulating layer 130 may be referred to as a first insulating layer.

[0165] A first gate metal layer may be disposed on the gate insulating film 130. For example, the first gate metal layer may include the second gate electrode G2, the first gate electrode G1, the third sub-gate electrode G41, the fourth sub-gate electrode G42, and the first capacitor electrode CE1 in Fig. 17, the ninth gate electrode G9, the eighth gate electrode G8, the twelfth gate electrode G12, and the third capacitor electrode CE3 in Fig. 18, and the seventeenth gate electrode G17, the fifth capacitor electrode CE5, and the fourth to sixth gate connecting electrodes GCE4, GCE5, and GCE6 in Fig. 19. The first gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0166] A first interlayer insulating film 141 may be disposed on the first gate metal layer. The first interlayer insulating film 141 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may be referred to as a second insulating film.

[0167] A second gate metal layer may be disposed on the first interlayer insulating film 141. For example, the second gate metal layer may include a second capacitor electrode CE2 (see FIG. 17), a fourth capacitor electrode CE4 (see FIG. 18), a sixth capacitor electrode CE6 (see FIG. 19), and a third power supply wiring VSSL (see FIGS. 17 to 20). The second gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0168] The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3, the fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3, and the sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. Since the first interlayer insulating film 141 has a predetermined dielectric constant, a first capacitor C1 may be formed by the first capacitor electrode CE1, the second capacitor electrode CE2, and the first interlayer insulating film 141 disposed therebetween. In addition, a second capacitor C2 may be formed by the third capacitor electrode CE3, the fourth capacitor electrode CE4, and the first interlayer insulating film 141 disposed therebetween. A third capacitor C3 may be formed by the fifth capacitor electrode CE5, the sixth capacitor electrode CE6, and the first interlayer insulating film 141 disposed therebetween.

[0169] In the drawing, the third power supply wiring VSSL may overlap with the second gate electrode G2, the third sub-gate electrode G41, the fourth sub-gate electrode G42, the ninth gate electrode G9, the eighth gate electrode G8, the twelfth gate electrode G12, and the seventeenth gate electrode G17. Although not shown, the third power supply wiring VSSL may also overlap with the second to seventh gate electrodes G2 to G7 and the ninth to nineteenth gate electrodes G9 to G19. The third power supply wiring VSSL may not overlap with the first gate electrode G1 and the eighth gate electrode G8.

[0170] A first source metal layer may be disposed on the second interlayer insulating film 142. The first source metal layer may include an initialization voltage line VIL, a kth scan initialization line GILk, a kth scan write line GWLk, a kth PWM light emission line PWELk, a first horizontal power line HVDL, a gate-off voltage line VGHL, a kth sweep signal line SWPLk, a kth scan control line GCLk, a kth PAM light emission line PAELk, a test signal line TSTL, and a third horizontal power line HVSL. The first source metal layer may also include first and second data connecting electrodes DCE1, DCE2, and first to seventh connecting electrodes CCE1 to CCE7. The first source metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0171] The k-th scan write wiring GWLk may be connected to the fourth sub-gate electrode G42 and the first gate connecting electrode GCE1 through a first gate contact hole GCT1 and a third gate contact hole GCT3 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 (see FIG. 17). The first gate contact hole GCT1 may be disposed in a hole ("HOL" in FIG. 9b) of the third power supply wiring VSSL.

[0172] The kth scan initialization line GILk may be connected to the second gate connecting electrode GCE2 through a second gate contact hole GCT2 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The second gate contact hole GCT2 may be disposed in a hole HOL of the third power supply line VSSL.

[0173] The kth scan control line GCLk may be connected to the third gate connecting electrode GCE3 through an eighth contact hole CT8 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The eighth contact hole CT8 may be disposed in a hole HOL of the third power supply line VSSL.

[0174] The kth PAM light emitting wiring PAELk may be connected to the fifth gate connecting electrode GCE5 through a 19th contact hole CT19 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 (see FIG. 19 ). The 19th contact hole CT19 may be disposed in a hole HOL of the third power supply wiring VSSL.

[0175] The kth PWM light emitting wiring PWELk may be connected to the sixth gate connecting electrode GCE6 through a fourteenth contact hole CT14 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 (see FIG. 19 ). The fourteenth contact hole CT14 may be disposed in a hole HOL of the third power supply wiring VSSL.

[0176] The initialization voltage line VIL may be connected to the second sub-drain electrode D32 and the sixth sub-drain electrode D102 through a first power contact hole VCT1 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The first power contact hole VCT1 may be disposed in a hole HOL of the third power line VSSL.

[0177] In addition, the initialization voltage line VIL may be connected to the tenth sub-drain electrode D162 and the eighteenth source electrode S18 through a ninth contact hole CT9 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The ninth contact hole CT9 may be disposed in a hole HOL of the third power wiring VSSL. The initialization voltage line VIL may be connected to the sixth capacitor electrode CE6 through an eighteenth contact hole CT18 penetrating the second interlayer insulating film 142 (see FIG. 19).

[0178] The first horizontal power line HVDL may be connected to the fifth source electrode S5 and the thirteenth source electrode S13 via a second power contact hole VCT2 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The second power contact hole VCT2 may be disposed in a hole HOL of the third power line VSSL.

[0179] The gate-off voltage line VGHL may be connected to the seventh source electrode S7 through a seventh contact hole CT7 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The seventh contact hole CT7 may be disposed in a hole HOL of the third power supply line VSSL.

[0180] The test signal wiring TSTL may be connected to the 19th gate electrode G19 through a 23rd contact hole CT23 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The third horizontal power supply wiring HVSL may be connected to the 19th drain electrode D19 through a 24th contact hole CT24 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The 23rd contact hole CT23 and the 24th contact hole CT24 may be disposed in a hole HOL of the third power supply wiring VSSL.

[0181] In FIG. 17, the first data connecting electrode DCE1 may be connected to the second source electrode S2 through a first data contact hole DCT1 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The first data contact hole DCT1 may be disposed in a hole HOL of the third power wiring VSSL. The first connecting electrode CCE1 may be connected to the first gate electrode G1 through a first contact hole CT1 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The k-th scan write wiring GWLk may be connected to the fourth sub-gate electrode G42 through a first gate contact hole GCT1 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The first gate contact hole GCT1 may be disposed in a hole HOL of the third power wiring VSSL.

[0182] 18, the second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through a third data contact hole DCT3 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The third data contact hole DCT3 may be disposed in a hole HOL of the third power wiring VSSL. The fifth connecting electrode CCE5 may be connected to the twelfth drain electrode D12 through an eleventh contact hole CT11 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The eleventh contact hole CT11 may be disposed in a hole HOL of the third power wiring VSSL.

[0183] FIG. 19 shows the fourteenth contact hole CT14, the seventeenth contact hole CT17, the eighteenth contact hole CT18, and the nineteenth contact hole CT19, and the description thereof has been given above and will not be repeated here.

[0184] 20, the third connecting electrode CCE3 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The twenty-first contact hole CT21 may be disposed in a hole HOL of the third power supply wiring VSSL.

[0185] A first planarization film 160 may be disposed on the first source metal layer. The first planarization film 160 may be formed of an organic film such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The first planarization film 160 may be referred to as a fourth insulating film.

[0186] A second source metal layer may be disposed on the first planarization film 160. The second source metal layer may include the jth data line DLj, the first vertical power line VVDL, and the first PAM data line RDL. The second source metal layer may also include a first anode connecting electrode ANDE1 and a second power connecting electrode VDCE. The second source metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0187] 17, the jth data line DLj may be connected to the first data connecting electrode DCE1 through a second data contact hole DCT2 penetrating the first planarization layer 160. The jth data line DLj may be connected to the second source electrode S2 through the first data connecting electrode DCE1.

[0188] 18, the first PAM data line RDL may be connected to the second data connecting electrode DCE2 through a fourth data contact hole DCT4 penetrating the first planarization layer 160. The first PAM data line RDL may be connected to the ninth source electrode S9 through the second data connecting electrode DCE2.

[0189] The first vertical power line VVDL may be connected to the first horizontal power line HVDL through a third power contact hole VCT3 penetrating the first planarization layer 160. The third power contact hole VCT3 may overlap the second power contact hole VCT2 in the third direction DR3 (see FIG. 14).

[0190] 16 and 20, the first anode connecting electrode ANDE1 may be connected to the seventh connecting electrode CCE7 through a twentieth contact hole CT20 penetrating the first planarization film 160, and may be connected to the third connecting electrode CCE3 through a 22nd contact hole CT22 penetrating the first planarization film 160. The first anode connecting electrode ANDE1 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through the seventh connecting electrode CCE7, and may be connected to the nineteenth source electrode S19 through the third connecting electrode CCE3.

[0191] 18, the second power connecting electrode VDCE may be connected to the fifth connecting electrode CCE5 through a fourth power contact hole VCT4 penetrating the first planarization layer 160. The second power connecting electrode VDCE may be connected to the twelfth source electrode S12 through the fifth connecting electrode CCE5.

[0192] A second planarization film 180 may be disposed on the second source metal layer. The second planarization film 180 may be formed of an organic film such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second planarization film 180 may be referred to as a fifth insulating film.

[0193] A third source metal layer may be disposed on the second planarization film 180. The third source metal layer may include a second power wiring VDL2, a second anode connecting electrode ANDE2, and a cathode connecting electrode VSCE. The third source metal layer may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0194] 18, the second power wiring VDL2 may be connected to the second power connecting electrode VDCE through a fifth power contact hole VCT5 penetrating the second planarization film 180. Therefore, the second power supply voltage ("VDD2" in FIG. 4) of the second power wiring VDL2 may be applied to the twelfth source electrode S12 of the twelfth transistor T12 through the second power connecting electrode VDCE and the fifth connecting electrode CCE5.

[0195] 20, the second anode connecting electrode ANDE2 may be connected to the first anode connecting electrode ANDE1 through a sixth power contact hole VCT6 penetrating the second planarization film 180. The second anode connecting electrode ANDE2 may overlap and directly contact the anode pad electrode APD in the third direction DR3. Therefore, the driving current Ids of the eighth transistor T8 may be transferred to the p-type semiconductor PSEM through the first contact electrode CTE1 of the light emitting element EL via the seventeenth drain electrode D17, the seventh connecting electrode CCE7, the first anode connecting electrode ANDE1, and the second anode connecting electrode ANDE2.

[0196] 20, the cathode connecting electrode VSCE may be disposed on the second planarization film 180. The cathode connecting electrode VSCE may overlap and directly contact the cathode pad electrode CPD in the third direction DR3.

[0197] A pad electrode may be disposed on the third source metal layer. The pad electrode may include an anode pad electrode APD and a cathode pad electrode CPD. The pad electrode is made of a transparent metal layer. For example, the pad electrode may be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light.

[0198] The anode pad electrode APD may be disposed on the second anode connecting electrode ANDE2.

[0199] The cathode pad electrode CPD may be disposed on the cathode connecting electrode VSCE. The cathode pad electrode CPD may be connected to the third power wiring VSSL through a pad contact hole PCT penetrating the second interlayer insulating film 142, the first planarization film 160, and the second planarization film 180. In an embodiment, the pad contact hole PCT may be disposed in an opening OP of the second power wiring VDL2. The pad contact hole PCT may not overlap with the second power wiring VDL2. Although FIG. 16 illustrates an example in which the pad contact hole PCT and the opening OP are located at the right edge of the first sub-pixel RP, the present invention is not limited thereto. The pad contact hole PCT and the opening OP may be appropriately formed in an empty space where the first source metal layer and the second source metal layer of the first sub-pixel RP are not disposed. In addition, in a manufacturing process, the pad contact hole PCT may be formed by a general etching process. The etching process may include a dry etching method or a wet etching method. As another example, the pad contact hole PCT may be formed by a laser drilling process. The laser drilling process may minimize the area of ​​the pad contact hole PCT. For example, the pad contact hole PCT may have an area of ​​18 μm×18 μm or more.

[0200] In addition, although the cathode pad electrode CPD and the third power wiring VSSL are directly connected in the embodiment, the present invention is not limited thereto. In some embodiments, the cathode pad electrode CPD and the third power wiring VSSL may be indirectly connected through a plurality of connection electrodes. For example, the cathode pad electrode CPD may be connected to the third power wiring VSSL through a connection electrode of the third source metal layer, a connection electrode of the second source metal layer, and a connection electrode of the first source metal layer. In this case, the pad contact hole PCT is formed through the second planarization film 180, so that the area of ​​the pad contact hole PCT can be minimized.

[0201] A protective film PAS may be disposed on the third source metal layer and the pad electrode. The protective film PAS may be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The protective film PAS may expose a portion of the upper surface of the anode pad electrode APD and the cathode pad electrode CPD without covering the portion.

[0202] In addition, an inorganic insulating layer may be further included between the planarization layer and the metal layer. For example, an inorganic insulating layer may be disposed between the first planarization layer 160 and the second source metal layer, and between the second planarization layer 180 and the third source metal layer. The inorganic insulating layer may be formed of, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0203] 20, a light emitting element EL may be disposed on the anode pad electrode APD and the cathode pad electrode CPD that are not covered by the protective film PAS. The light emitting element EL is a flip-chip type micro LED in which the first contact electrode CTE1 faces the anode pad electrode APD and the second contact electrode CTE2 faces the cathode pad electrode CPD. The light emitting element EL may include an inorganic material such as GaN. The horizontal length and the third direction DR3 of the light emitting element EL may each be several μm to several hundred μm.

[0204] The light-emitting element EL may be formed by growing on a semiconductor substrate such as a silicon wafer. The light-emitting element EL may be transferred directly onto the anode pad electrode APD and the cathode pad electrode CPD of the substrate SUB from the silicon wafer. Alternatively, the light-emitting element EL may be transferred onto the anode pad electrode APD and the cathode pad electrode CPD of the substrate SUB by an electrostatic method using an electrostatic head or a stamp method using an elastic polymeric material such as PDMS or silicon as a transfer substrate.

[0205] The light emitting element EL may be a light emitting structure including a base substrate BSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2.

[0206] The base substrate BSUB may be a sapphire substrate, although embodiments herein are not limited thereto.

[0207] The n-type semiconductor NSEM may be disposed on one side of the base substrate BSUB. For example, the n-type semiconductor NSEM may be disposed on the bottom side of the base substrate BSUB. The n-type semiconductor NSEM may be made of GaN doped with an n-type conductivity dopant such as Si, Ge, Sn, Se, or the like.

[0208] The active layer MQW may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may form electron-hole pair combinations in response to an electrical signal through electrons of the n-type semiconductor NSEM and holes of the p-type semiconductor PSEM, and may emit light. The active layer MQW may include a material having a single or multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, and may include another group III to V semiconductor material according to the wavelength band of the emitted light.

[0209] The p-type semiconductor PSEM may be disposed on one surface of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, or Ba.

[0210] The first contact electrode CTE1 may be disposed on the p-type semiconductor PSEM, and the second contact electrode CTE2 may be disposed on another part of one surface of the n-type semiconductor NSEM. The other part of the one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed apart from the part of the one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0211] The first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other by a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the first contact electrode CTE1 and the anode pad electrode APD may be bonded to each other by a soldering process.

[0212] The second contact electrode CTE2 and the cathode pad electrode CPD may be bonded to each other by a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the second contact electrode CTE2 and the cathode pad electrode CPD may be bonded to each other by a soldering process.

[0213] In addition, a third planarization film for planarizing a step caused by the light-emitting element EL may be disposed. The fourth planarization film may be disposed so as to surround the side surface of the light-emitting element EL, and may expose the upper surface of the light-emitting element EL without covering it.

[0214] In the display device 10 according to the present embodiment, the third power wiring VSSL to which a low potential voltage is applied is designed in the second gate metal layer, so that a mask process for forming an additional conductive layer on the third source metal layer can be omitted. The second gate metal layer may further include the third power wiring VSSL at a position separated from the second capacitor electrode CE2, the fourth capacitor electrode CE4, and the sixth capacitor electrode CE6. That is, by patterning the third power wiring VSSL in an area where the upper capacitor electrode is not arranged in the second gate metal layer, a process for disposing a separate low potential wiring on the third source metal layer and the third planarization film can be omitted. As a result, two mask processes can be omitted, so that the manufacturing process of the display device 10 can be simplified and the manufacturing cost can be reduced by reducing the number of masks.

[0215] In addition, when the second gate metal layer further includes the third power wiring VSSL, the area occupied by each subpixel can be reduced by approximately 3% and the thickness of each metal layer can be increased by 120 Å to minimize the reduction in the resistance of the signal wiring.

[0216] In addition, in one embodiment, by replacing the mask for forming the align key with the active layer ACT, the light-shielding layer disposed between the buffer layer BF and the gate insulating layer 130 can be omitted. When the light-shielding layer is omitted, one mask process can be further omitted. In this case, the leakage of light emitted from the display device 10 can be controlled by the first gate metal layer.

[0217] FIG. 21 is another example of a cross-sectional view taken along lines IV-IV' and V-V' in FIG. 6 and FIG.

[0218] In the display device 10_1 according to this embodiment, the cathode connecting electrode VSCE may be omitted. In this case, the cathode pad electrode CPD_1 may be in direct contact with the second planarization film 180. The branches of the cathode pad electrode CPD_1 may be in contact with the second planarization film 180. In addition, the height of the cathode pad electrode CPD_1 in the third direction DR3 from the second planarization film 180 may be lower than the height of the anode pad electrode APD in the third direction DR3 from the second planarization film 180. Descriptions of other reference numerals will be omitted as they are similar to those of the previous embodiment.

[0219] FIG. 22 is a perspective view of a tiled display including multiple displays according to one embodiment.

[0220] 22, the tiled display device TD may include a plurality of display devices 11, 12, 13, and 14, and a seam portion SM. For example, the tiled display device TD may include a first display device 11, a second display device 12, a third display device 13, and a fourth display device 14.

[0221] The multiple display devices 11, 12, 13, 14 may be arranged in a lattice pattern. The multiple display devices 11, 12, 13, 14 may be arranged in a matrix pattern of M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device 11 and the second display device 12 are adjacent to each other in the first direction DR1. The first display device 11 and the third display device 13 are adjacent to each other in the second direction DR2. The third display device 13 and the fourth display device 14 are adjacent to each other in the first direction DR1. The second display device 12 and the fourth display device 14 are adjacent to each other in the second direction DR2.

[0222] However, in the tiled display device TD, the number and arrangement of the multiple display devices 11, 12, 13, and 14 are not limited to those shown in Fig. 22. In the tiled display device TD, the number and arrangement of the display devices 11, 12, 13, and 14 can be determined according to the sizes of the display devices 11, 12, 13, and 14 and the tiled display device TD, respectively, and the shape of the tiled display device TD.

[0223] The display devices 11, 12, 13, and 14 may have the same size, but are not limited to this. For example, the display devices 11, 12, 13, and 14 may have different sizes.

[0224] Each of the multiple display devices 11, 12, 13, 14 may be rectangular in shape including a long side and a short side. The multiple display devices 11, 12, 13, 14 may be arranged with their long sides or short sides connected to each other. Some or all of the multiple display devices 11, 12, 13, 14 may be arranged on the edge of the tiled display device TD and form one side of the tiled display device TD. At least one display device among the multiple display devices 11, 12, 13, 14 may be arranged on at least one edge of the tiled display device TD and form two adjacent sides of the tiled display device TD. At least one display device among the multiple display devices 11, 12, 13, 14 may be surrounded by other display devices.

[0225] Each of the multiple display devices 11, 12, 13, and 14 may be substantially the same as the display device 10 described with reference to Fig. 1. Therefore, a description of each of the multiple display devices 11, 12, 13, and 14 will be omitted.

[0226] The seam portion SM may include a joining member or an adhesive member. In this case, the multiple display devices 11, 12, 13, and 14 may be connected to each other by the joining member or the adhesive member of the seam portion SM. The seam portion SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0227] FIG. 23 is an enlarged layout diagram showing the details of region E in FIG.

[0228] 23, the seam portion SM may have a planar shape of a cross, a cross, or a plus sign in a central region of the tiled display device TD adjacent to the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14. The seam portion SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0229] The first display device 11 may include first pixels PX1 arranged in a matrix in a first direction DR1 and a second direction DR2 to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image.

[0230] The minimum distance between adjacent first pixels PX1 in the first direction DR1 may be defined as a first horizontal separation distance GH1, and the minimum distance between adjacent second pixels PX2 in the first direction DR1 may be defined as a second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially equal to each other.

[0231] A seam portion SM may be disposed between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1. The minimum distance GA12 between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1 may be the sum of the minimum distance GHS1 between the first pixel PX1 and the seam portion SM in the first direction DR1, the minimum distance GHS2 between the second pixel PX2 and the seam portion SM in the first direction DR1, and the width GSM1 of the seam portion SM in the first direction DR1.

[0232] The minimum distance GA12 between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 may be substantially the same. For this purpose, the minimum distance GHS1 between the first pixel PX1 and the seam portion SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1, and the minimum distance GHS2 between the second pixel PX2 and the seam portion SM in the first direction DR1 may be smaller than the second horizontal separation distance GH2. Also, the width GSM1 of the seam portion SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

[0233] The minimum distance between the third pixels PX3 adjacent to each other in the first direction DR1 may be defined as a third horizontal separation distance GH3, and the minimum distance between the fourth pixels PX4 adjacent to each other in the first direction DR1 may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially equal to each other.

[0234] A seam portion SM may be disposed between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1. The minimum distance GA34 between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1 may be the sum of the minimum distance GHS3 between the third pixel PX3 and the seam portion SM in the first direction DR1, the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM in the first direction DR1, and the width GSM1 of the seam portion SM in the first direction DR1.

[0235] The minimum distance GA34 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 may be substantially the same. For this purpose, the minimum distance GHS3 between the third pixel PX3 and the seam portion SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3, and the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM in the first direction DR1 may be smaller than the fourth horizontal separation distance GH4. Also, the width GSM1 of the seam portion SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

[0236] The minimum distance between adjacent first pixels PX1 in the second direction DR2 may be defined as a first vertical separation distance GV1, and the minimum distance between adjacent third pixels PX3 in the second direction DR2 may be defined as a third vertical separation distance GV3. The first vertical separation distance GV1 and the third vertical separation distance GV3 may be substantially equal to each other.

[0237] A seam portion SM may be disposed between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2. The minimum distance GA13 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS1 between the first pixel PX1 and the seam portion SM in the second direction DR2, the minimum distance GVS3 between the third pixel PX3 and the seam portion SM in the second direction DR2, and the width GSM2 of the seam portion SM in the second direction DR2.

[0238] The minimum distance GA13 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2, the first vertical separation distance GV1, and the third vertical separation distance GV3 may be substantially the same. For this purpose, the minimum distance GVS1 between the first pixel PX1 and the seam portion SM in the second direction DR2 may be smaller than the first vertical separation distance GV1, and the minimum distance GVS3 between the third pixel PX3 and the seam portion SM in the second direction DR2 may be smaller than the third vertical separation distance GV3. Also, the width GSM2 of the seam portion SM in the second direction DR2 may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

[0239] The minimum distance between adjacent second pixels PX2 in the second direction DR2 may be defined as a second vertical separation distance GV2, and the minimum distance between adjacent fourth pixels PX4 in the second direction DR2 may be defined as a fourth vertical separation distance GV4. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially equal to each other.

[0240] A seam portion SM may be disposed between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2. The minimum distance GA24 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS2 between the second pixel PX2 and the seam portion SM in the second direction DR2, the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM in the second direction DR2, and the distance GSM4 of the seam portion SM in the second direction DR2.

[0241] The minimum distance GA24 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 may be substantially the same. For this purpose, the minimum distance GVS2 between the second pixel PX2 and the seam portion SM in the second direction DR2 may be smaller than the second vertical separation distance GV2, and the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM in the second direction DR2 may be smaller than the fourth vertical separation distance GV4. Also, the width GSM2 of the seam portion SM in the second direction DR2 may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4.

[0242] As shown in FIG. 23, in order to prevent seam portions SM from being visible between images displayed by multiple display devices 11, 12, 13, and 14, the minimum distance between pixels of adjacent display devices may be substantially the same as the minimum distance between pixels of each of the display devices.

[0243] FIG. 24 is a cross-sectional view showing an example of a tiled display device taken along the line X1-X1' of FIG.

[0244] 24, the first display device 11 includes a first display module DPM1 and a first front cover COV1, and the second display device 12 includes a second display module DPM2 and a second front cover COV2.

[0245] Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer TFTL, and a light emitting element layer. The thin film transistor layer TFTL and the light emitting element layer have already been described in detail with reference to Fig. 20. In Fig. 24, the description overlapping with the embodiment of Fig. 20 will be omitted.

[0246] The substrate SUB may include a first surface 41 on which the thin film transistor layer TFTL is disposed, a second surface 42 opposite to the first surface, and a first side surface 43 disposed between the first surface 41 and the second surface 42. The first surface 41 may be a front or top surface of the substrate SUB, and the second surface 42 may be a back or bottom surface of the substrate SUB.

[0247] In addition, the substrate SUB may further include chamfered surfaces 44 disposed between the first surface 41 and the first side surface 43 and between the second surface 42 and the first side surface 43. The thin film transistor layer TFTL and the light emitting element layer do not have to be disposed on the chamfered surface 44. The chamfered surface 44 can prevent the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 from colliding with each other and being damaged.

[0248] The chamfered surfaces 44 may also be disposed between the first surface 41 and each of the other side surfaces except the first side surface 43, and between the second surface 42 and each of the other side surfaces except the first side surface 43. For example, when the first display device 11 and the second display device 12 have a rectangular planar shape as shown in Fig. 23, the chamfered surfaces 44 may be disposed between the first surface 41 and each of the second side surface, the third side surface, and the fourth side surface, and between the second surface 42 and each of the second side surface, the third side surface, and the fourth side surface.

[0249] The first front cover COV1 may be arranged on the chamfered surface 44 of the substrate SUB, i.e. the first front cover COV1 may protrude from the substrate SUB in the first direction DR1 and in the second direction DR2. Thus, the distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 may be greater than the distance GCOV between the first front cover COV1 and the second front cover COV2.

[0250] Each of the first front cover COV1 and the second front cover COV2 may include an adhesive member 51, a light transmittance adjusting layer 52 disposed on the adhesive member 51, and an anti-glare layer (Anti-Glare Layer, 53) disposed on the light transmittance adjusting layer 52.

[0251] The adhesive member 51 of the first front cover COV1 serves to attach and adhere the light emitting element layer EML of the first display module DPM1 to the first front cover COV1. The adhesive member 51 of the second front cover COV2 serves to attach and adhere the light emitting element layer EML2 of the second display module DPM2 to the second front cover COV2. The adhesive member 51 may be a transparent adhesive member that can transmit light. For example, the adhesive member 51 may be an optically clear adhesive film or an optically clear resin.

[0252] The anti-glare layer 53 can be designed to diffusely reflect external light to prevent the external light from being reflected as it is and reducing the visibility of the image. Therefore, the anti-glare layer 53 increases the contrast ratio of the images displayed by the first display device 11 and the second display device 12.

[0253] The light transmittance adjusting layer 52 may be designed to reduce the transmittance of external light or light reflected by the first display module DPM1 and the second display module DPM2, thereby preventing the gap GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 from being visible from the outside.

[0254] The anti-glare layer 53 may be realized as a polarizer, and the light transmittance adjusting layer 52 may be realized as a phase retardation layer, but the embodiments of the present specification are not limited thereto.

[0255] Note that an example of a tiled display device cut along X2-X2', X3-X3', and X4-X4' in Figure 23 is substantially identical to the example of a tiled display device cut along X1-X1' described with reference to Figure 24, so a description thereof will be omitted.

[0256] Fig. 25 is an enlarged layout diagram showing in detail the F region in Fig. 22. Fig. 26 is a cross-sectional view showing an example of a tiled display device cut along the line X5-X5' in Fig. 25. In Fig. 26, explanations that overlap with the embodiment in Figs. 17 to 21 will be omitted.

[0257] FIG. 25 shows the first pad PD1 and the second sub-pixel GP of the first pixel PX1 arranged on the upper side of the first display device 11.

[0258] 25, a first pad PD1 may be disposed at an upper edge of the first display device 11. When the data lines DL of the first display device 11 extend in the second direction DR2, the first pad PD1 may be disposed at the upper and lower edges of the first display device 11. Alternatively, when the data lines DL of the first display device 11 extend in the first direction DR1, the first pad PD1 may be disposed at the left and right edges of the first display device 11.

[0259] Each of the first pads PD1 may be connected to a data line DL. Also, each of the first pads PD1 may be connected to a side line SIL. The side line SIL may be disposed on one side and a bottom surface (or back surface) of the substrate SUB. The side line SIL may be connected to a back surface connecting line BCL on the bottom surface of the substrate SUB.

[0260] The first pad PD1 may be disposed on the second interlayer insulating film 142. The first pad PD1 may be exposed without being covered by the first planarization film 160 and the second planarization film 180.

[0261] The first pad PD1 may include first to fourth subpads SPD1, SPD2, SPD3, and SPD4. The second subpad SPD2 may be disposed on the first subpad SPD1, and the third subpad SPD3 may be disposed on the second subpad SPD2. The fourth subpad SPD4 may be disposed on the third subpad SPD3. Although the first subpad SPD1 is included in a pad electrode layer including a first source metal layer, the second subpad SPD2 is included in a pad electrode layer including a second source metal layer, the third subpad SPD3 is included in a pad electrode layer including a third source metal layer, and the fourth subpad SPD4 is included in a pad electrode layer including a transparent metal material (TCO) as an example, the embodiment of the present specification is not limited thereto.

[0262] The back interconnect BCL may be disposed on the bottom surface of the substrate SUB. The back interconnect BCL may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0263] The second pad PD2 may be disposed at one end of the back connecting line BCL, and the third pad PD3 may be disposed at the other end of the back connecting line BCL. The second pad PD2 and the third pad PD3 may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0264] The third planarization layer 170 may be disposed on the rear connecting wiring BCL and the rear surface of the substrate SUB. The third planarization layer 170 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0265] The second protective film PVX2 may be disposed on the third planarization film 170. The second protective film PVX2 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0266] The side wiring SIL may be disposed on the first surface 41, the second surface 42, the first side surface 43, and the first chamfered surface 44 of the substrate SUB. The side wiring SIL may be disposed on a first pad PD1 disposed on the edge of the first surface 41 of the substrate SUB, and coupled to the first pad PD1. The side wiring SIL may be disposed on a second pad PD2 disposed on the edge of the second surface 42 of the substrate SUB, and coupled to the second pad PD2. The side wiring SIL may be in contact with the first chamfered surface 44 and the first side surface 43 of the substrate SUB.

[0267] The overcoat layer OC may be disposed on the first surface 41, the first chamfered surface 44, the first side surface 43, and the second surface 42 of the substrate SUB. The overcoat layer OC may be disposed so as to cover the side wiring SIL. The overcoat layer OC may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0268] The circuit board FPCB may be disposed on the rear surface of the substrate SUB. The circuit board FPCB may be connected to the third pads PD3 exposed and not covered by the third planarization film 170 and the second protective film PVX2 using a conductive adhesive member CAM. The circuit board FPCB may be connected to the third pads PD3 by the conductive adhesive member CAM. The conductive adhesive member CAM may be an anisotropic conductive film or an anisotropic conductive paste. The circuit board FPCB may be a printed circuit board, a flexible printed circuit board, or a flexible film.

[0269] FIG. 27 is a block diagram illustrating a tiled display device according to one embodiment.

[0270] For convenience of explanation, FIG. 27 shows a first display device 11 and a host system HOST.

[0271] Referring to FIG. 27, a tiled display device TD according to one embodiment may include a host system HOST, a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a hard disk drive (HDD, 260), a network communication unit 270, a user interface (UI) generation unit 280 and a control unit 290.

[0272] The host system HOST may be realized as any one of a television system, a home theater system, a set-top box, a navigation system, a digital video disc (DVD) player, a Blu-ray player, a personal computer (PC), a mobile phone system, and a tablet.

[0273] A user's command may be input to the host system HOST in various forms. For example, the host system HOST may receive a command by touch input from the user, or may receive a command by keyboard input or button input from a remote controller.

[0274] The host system HOST may receive original video data corresponding to an original image from the outside. The host system HOST may divide the original video data into the number of display devices. For example, the host system HOST may divide the original video data into first video data corresponding to a first image, second video data corresponding to a second image, third video data corresponding to a third image, and fourth video data corresponding to a fourth image, corresponding to a first display device 11, a second display device 12, a third display device 13, and a fourth display device 14 shown in FIG. 22. The host system HOST may transmit the first video data to the first display device 11, the second video data to the second display device 12, the third video data to the third display device 13, and the fourth video data to the fourth display device 14.

[0275] The first display device 11 can display a first image according to the first video data, the second display device 12 can display a second image according to the second video data, the third display device 13 can display a third image according to the third video data, and the fourth display device 14 can display a fourth image according to the fourth video data. Therefore, the user can view an original image in which the first to fourth images displayed on the first to fourth display devices 11, 12, 13, and 14 are combined.

[0276] The first display device 11 may include a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a HDD 260, a network communication unit 270, a UI generation unit 280, and a control unit 290.

[0277] The broadcast tuning unit 210 can tune to a predetermined channel frequency and receive a broadcast signal of the corresponding channel through an antenna under the control of the control unit 290. The broadcast tuning unit 210 can include a channel detection module and a radio frequency (RF) demodulation module.

[0278] The broadcast signal demodulated by the broadcast tuning unit 210 is processed by a signal processing unit 220 and output to a display unit 230 and a speaker 240. Here, the signal processing unit 220 may include a demultiplexer 221, a video decoder 222, a video processing unit 223, an audio decoder 224, and an additional data processing unit 225.

[0279] The demultiplexer 221 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by a video decoder 222, an audio decoder 224, and an additional data processor 225, respectively. At this time, the video decoder 222, the audio decoder 224, and the additional data processor 225 restore the signals to a decoding format corresponding to the encoding format used when the broadcast signal was transmitted.

[0280] In addition, the decoded video signal is converted by the video processing unit 223 to conform to the vertical frequency, resolution, aspect ratio, etc. that meets the output standards of the display unit 230, and the decoded audio signal is output to the speaker 240.

[0281] The display unit 230 includes a display panel 100 on which an image is displayed, and a panel driver that controls driving of the display panel 100. A detailed block diagram of the display panel 100 and the panel driver has already been described in detail with reference to FIG.

[0282] The user input unit 250 receives a signal transmitted by the host system HOST. The user input unit 250 is provided to allow a user to select and input data for channel selection, UI (User Interface) menu selection and operation transmitted by the host system HOST, as well as commands for communication with other display devices.

[0283] The HDD 260 stores various software programs including an operating system (OS) program, recorded broadcast programs, videos, photos, and other data, and may be a storage medium such as a hard disk or a non-volatile memory.

[0284] The network communication unit 270 is for short-range communication with the host system HOST and other display devices, and can be realized as a communication module including an antenna pattern capable of realizing mobile communication, data communication, Bluetooth (registered trademark), RF, Ethernet, etc.

[0285] The network communication unit 270 can also transmit and receive wireless signals to and from at least one of a base station, an external terminal, and a server on a mobile communication network constructed in accordance with a technical standard or communication method for mobile communication (e.g., Global System for Mobile communication (GSM), Code Division Multi Access (CDMA), Code Division Multi Access 2000 (CDMA2000), Enhanced Voice-Data Optimized or Enhanced Voice-Data Only (EV-DO), Wideband CDMA (WCDMA (registered trademark)), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Long Term Evolution-Advanced (LTE-A), 5G, etc.) through an antenna pattern described below.

[0286] The network communication unit 270 can also transmit and receive wireless signals through a communication network using wireless Internet technologies through an antenna pattern described below. Examples of wireless Internet technologies include Wireless LAN (WLAN), Wireless-Fidelity (Wi-Fi), Wireless Fidelity (Wi-Fi) Direct, Digital Living Network Alliance (DLNA), Wireless Broadband (WiBro), World Interoperability for Microwave Access (WiMAX), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), and Long Term Evolution-Advanced (LTE-A), and the antenna pattern transmits and receives data according to at least one wireless Internet technology including Internet technologies not listed above.

[0287] The UI generating unit 280 generates a UI menu for communication with the host system HOST and other display devices, and can be realized by an algorithm code and an optical scanning device (OSD) IC. The UI menu for communication with the host system HOST and other display devices can be a menu for specifying a digital TV with which communication is desired and for selecting a desired function.

[0288] The control unit 290 is responsible for the overall control of the first display device 11 and for communication control between the host system HOST and the second through fourth display devices 12, 13, and 14, and can be realized by an MCU (Micro Controller Unit) in which the corresponding algorithm code for control is stored and the stored algorithm code is executed.

[0289] The control unit 290 controls the transmission of corresponding control commands and data to the host system HOST and the second through fourth display devices 12, 13, and 14 via the network communication unit 270 in response to the input and selection of the user input unit 250. Of course, when a predetermined control command and data are input from the host system HOST and the second through fourth display devices 12, 13, and 14, the control unit 290 performs an operation according to the corresponding control command.

[0290] Note that the block diagram of the second display device 12, the block diagram of the third display device 13, and the block diagram of the fourth display device 14 are substantially identical to the block diagram of the first display device 11 described with reference to Figure 27, so descriptions thereof will be omitted.

[0291] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0292] 10 Display device T1 to T19: 1st to 19th transistors PDU1 to PDU3: First to third pixel driving units RP, GP, BP subpixels GWL Scan Write Wiring GIL scan initialization wiring GCL Scan control wiring SWPL Sweep signal wiring PWEL PWM light emitting wiring PAEL PAM light-emitting wiring DL PWM data wiring RDL 1st PAM data line VDL1, VDL2 First and second power supply wiring VSSL 3rd power wiring APD anode pad electrode CPD cathode pad electrode

Claims

1. a first data line to which a first data voltage is applied; a second data line to which a second data voltage is applied; A low-potential wiring to which a low-potential voltage is applied; and a first sub-pixel connected to the first data line, the second data line, and the low potential line; The first sub-pixel is a cathode pad electrode connected to the low potential wiring; a first transistor generating a control current in response to a first data voltage on the first data line and having a first gate electrode; an eighth transistor that generates a driving current to be applied to a light emitting device in response to a second data voltage of the second data line; and a first capacitor including a first capacitor electrode connected to the first gate electrode and a second capacitor electrode disposed on the first capacitor electrode; The low potential wiring is arranged in the same layer as the second capacitor electrode, and is arranged so as to surround the second capacitor electrode.

2. A scan write line for applying a scan write signal; and a second transistor including a second gate electrode connected to the scan write line; The display device according to claim 1 , wherein the second gate electrode overlaps with the low potential wiring.

3. The display device of claim 1 , wherein the low potential wiring is disposed below the first data wiring and the second data wiring.

4. The display device of claim 1 , wherein the cathode pad electrode is connected to the low potential wiring through a pad contact hole.

5. 5. The display device of claim 4, wherein the cathode pad electrode includes a stem extending in a first direction and a branch connected to the stem and extending in a second direction intersecting the first direction, and the pad contact hole is located in the stem.

6. a second light-emitting wiring to which a second light-emitting signal is applied; a second high potential wiring to which a second high potential voltage is applied; and a twelfth transistor connecting the second high potential wiring to one electrode of the eighth transistor in response to the second light emission signal, The display device according to claim 1 , wherein the second high potential wiring is disposed on the low potential wiring.

7. the low potential wiring is a hole exposing one electrode of the twelfth transistor; and The display device of claim 6 , further comprising a connection electrode having a contact hole connecting one electrode of the twelfth transistor and the second high potential wiring in the hole.

8. a substrate supporting the first sub-pixel; The display device of claim 7 , wherein the low potential wiring, the connecting electrode, and the second high potential wiring are sequentially arranged in a thickness direction of the substrate.

9. the second high potential wiring includes an opening exposing the low potential wiring; The display device of claim 6 , wherein the cathode pad electrode is connected to the low potential wiring within the opening.

10. The cathode pad electrode and an anode pad electrode spaced apart from each other, The display device according to claim 1 , wherein the light-emitting element is disposed on the cathode pad electrode and the anode pad electrode.

11. a first light-emitting wiring to which a first light-emitting signal is applied; a first high potential wiring to which a first high potential voltage is applied; and a fifth transistor connecting the first high potential wiring to one electrode of the first transistor in response to the first light emitting signal, The display device according to claim 1 , wherein the low potential wiring includes a hole exposing one electrode of the fifth transistor.

12. The display device according to claim 1 , wherein the light emitting element is a flip-chip type micro light emitting diode element.

13. a first data line to which a first data voltage is applied; a second data line to which a second data voltage is applied; a low potential wiring to which a low potential voltage is applied; a second high potential wiring to which a second high potential voltage is applied; and a first sub-pixel connected to the first data line, the second data line, the low potential line, and the second high potential line; The first sub-pixel is a first transistor generating a control current in response to a first data voltage on the first data line and having a first gate electrode; an eighth transistor that generates a driving current to be applied to a light emitting device in response to a second data voltage of the second data line; and a capacitor electrode disposed on the first gate electrode; The low potential wiring is disposed in the same layer as the capacitor electrode, and the second high potential wiring includes an opening that exposes the low potential wiring.

14. The display device according to claim 13 , further comprising a cathode pad electrode connected to the low potential wiring within the opening.

15. The display device according to claim 13, wherein the light emitting element is a flip-chip type micro light emitting diode element.

16. substrate; an active layer disposed on the substrate, the active layer including a first channel, a first source electrode, and a first drain electrode; a first insulating film disposed on the active layer; a first gate electrode and a first capacitor electrode disposed on the first insulating film and overlapping with the first channel; a second insulating film disposed on the first gate electrode and the first capacitor electrode; a second capacitor electrode and a low potential wiring disposed on the second insulating film and overlapping with the first capacitor electrode; a third insulating film disposed on the second capacitor electrode and the low potential wiring; a scan write wiring disposed on the third insulating film and to which a scan write signal is applied; a fourth insulating film disposed on the scan write wiring; a second high potential wiring disposed on the fourth insulating film and to which a second high potential voltage is applied; and a cathode pad electrode disposed on the second high potential wiring and connected to the low potential wiring;

17. the second high potential wiring includes an opening exposing the low potential wiring; The display device according to claim 16 , wherein the cathode pad electrode is connected to the low potential wiring within the opening.

18. 17. The display device of claim 16, wherein the cathode pad electrode is directly connected to the low potential wiring through a pad contact hole penetrating the fourth insulating film and the third insulating film.

19. 20. The display device of claim 18, wherein the pad contact holes are formed by laser drilling.

20. a first anode connecting electrode disposed on the fourth insulating film; a fifth insulating film disposed on the first anode connecting electrode; a second anode connecting electrode disposed on the fifth insulating film; and The display device of claim 16, further comprising an anode pad electrode disposed on the second anode connecting electrode.

21. The display device of claim 20 , wherein the second anode connecting electrode is in contact with the anode pad electrode.

22. The display device of claim 20 , wherein the second high potential wiring is disposed in the same layer as the second anode connecting electrode.

23. The second anode connecting electrode is disposed in the same layer as the cathode connecting electrode, The display device of claim 20 , wherein the cathode pad electrode is disposed on the cathode connecting electrode.

24. The display device according to claim 20 , wherein the cathode pad electrode is in direct contact with the fifth insulating film.

25. further comprising a buffer layer disposed between the substrate and the active layer; The display device of claim 16 , wherein the buffer film is in direct contact with the first channel, the first source electrode, and the first drain electrode.

26. substrate; an active layer disposed on the substrate, the active layer having a first channel; a first gate metal layer disposed on the active layer and having a first gate electrode overlying the first channel, and a first capacitor electrode; a second gate metal layer disposed on the first gate metal layer, the second gate metal layer having a second capacitor electrode overlapping the first capacitor electrode and a low potential wiring spaced apart from the second capacitor electrode; a first source metal layer disposed on the second gate metal layer and having a first light-emitting wiring to which a first light-emitting signal is applied; a second source metal layer disposed on the first source metal layer and having a data line to which a data voltage is applied; a third source metal layer disposed on the second source metal layer and having a high potential wiring to which a high potential voltage is applied; and the display device further comprising an anode pad electrode and a cathode pad electrode disposed on the third source metal layer.

27. 27. The display device of claim 26, wherein the anode pad electrode and the cathode pad electrode comprise a transparent conductive material.

28. the active layer further includes a second channel coupled to the first channel, the first gate metal layer further includes a second gate electrode overlapping the second channel and connected to the first light emitting wiring; The display device according to claim 26 , wherein the low potential wiring overlaps with the second gate electrode in a thickness direction of the substrate.

29. The display device according to claim 28 , wherein the high potential wiring is electrically connected to an electrode coupled to the second channel.

30. A seam portion is disposed between a plurality of display devices, A first display device among the plurality of display devices is A substrate; and a first data wiring to which a first data voltage is applied, a second data wiring to which a second data voltage is applied, a low potential wiring to which a low potential voltage is applied, and a first sub-pixel connected to the first data wiring, the second data wiring, and the low potential wiring; The first sub-pixel is Light emitting element; a cathode pad electrode connected to the low potential wiring; a first transistor generating a control current in response to a first data voltage on the first data line and having a first gate electrode; an eighth transistor that generates a driving current to be applied to the light emitting device in response to a second data voltage of the second data line; and a first capacitor including a first capacitor electrode connected to the first gate electrode and a second capacitor electrode disposed on the first capacitor electrode; A tiled display device, wherein the low potential wiring is arranged in the same layer as the second capacitor electrode and is arranged so as to surround the second capacitor electrode.

31. 31. The tiled display device according to claim 30, wherein each of the light emitting elements is a flip-chip type micro light emitting diode element.

32. 31. The tiled display of claim 30, wherein the substrate is made of glass.

33. The first display device is a pad disposed on a first surface of the substrate; and 31. The tiled display device of claim 30, further comprising a side wiring disposed on a first surface of the substrate, a second surface opposite to the first surface, and one side between the first surface and the second surface, and connected to the pad.

34. The first display device is an interconnection wire disposed on the second surface of the substrate; and The flexible film may further include a conductive adhesive material connected to the connecting wire. The tiled display device of claim 33 , wherein the side wiring is connected to the connecting wiring.

35. 31. The tiled display of claim 30, wherein the plurality of displays are arranged in a matrix of M rows and N columns.

Images