Quantum error correcting codes and the collaborative design of physical and logical gates

Abstract

Techniques are disclosed for performing error correction in a quantum circuit of a quantum computing system. A quantum error correcting code (QECC) is selected. The QECC is associated with a code space. The quantum computing system identifies one or more diagonal physical gates in the quantum circuit that induce a target logical gate based on one or more characteristics of the QECC and preserves the code space. The quantum computing system configures the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified diagonal physical gates.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Application No. 63 / 304,387, filed January 28, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0002] Government Licensing Rights This invention was made with government support under awards CCF-1908730 and CCF-2106213, respectively, from the National Science Foundation. The Government has certain rights in this invention.

[0003] The present disclosure relates generally to quantum error correction, and more specifically, to identifying each possible diagonal physical gate that induces a target logic gate and preserves the code space for a given CSS code in a given code space. [Background technology]

[0004] Combining error tolerance with universal computation is a well-known challenge in quantum computing. In particular, various factors such as decoherence caused by environmental interactions, other types of noise, and defective gates can affect the information-bearing quantum state. It is therefore essential to achieve fault-tolerant quantum computing. However, unlike classical computing, fault tolerance in quantum computing cannot involve creating redundancy by copying quantum information, as this is physically impossible.

[0005] Instead, quantum error correcting codes (QECCs) provide fault tolerance by using qubit operations and measurements to correct quantum states as they are transformed by logic gates. For example, a stabilizer code adds a qubit to a given qubit or group of qubits to protect. A unitary encoding circuit then rotates the global state to a subspace of a larger Hilbert space, which results in a highly entangled state that corrects the local noise. Calderbank-Shor-Steane (CSS) codes are a type of stabilizer code constructed from pairs of classical binary error correcting codes. The stabilizer group for CSS codes can be generated from Pauli terms that are products of only X terms or only Z terms.

[0006] Typically, QECC is designed to implement logical operators via transverse physical gates in quantum circuits of quantum computing systems. The transverse physical gates are unitary tensor products on individual code blocks. Furthermore, magic state distillation (MSD) allows combining transverse physical gates with auxiliary states to create a universal set of logical gates. The MSD protocol uses CSS codes that support fault-tolerant non-Clifford logical gates induced by the transverse physical gates. The interaction between the transverse diagonal gates and the induced logical gates resides strongly in the code of the Z stabilizer in a given CSS code. A conventional approach in quantum error correction via QECC involves fixing a given transverse diagonal physical gate and a target logical gate, and then deriving a sufficient condition in the CSS code that the diagonal physical gate preserves the CSS code and induces the target logical gate. Summary of the Invention [Means for solving the problem]

[0007] The embodiments presented herein disclose techniques to induce a target logic gate to synthesize each possible diagonal physical gate that preserves the underlying code space, given a CSS code, to generate a QECC that is preserved by a particular diagonal physical gate.

[0008] For example, embodiments presented herein disclose a computer-implemented method for performing error correction in a quantum circuit of a quantum computing system. The method generally includes selecting, by the quantum computing system, a quantum error correcting code (QECC). The QECC is associated with a code space. The method generally also includes identifying, by the quantum computing system, one or more diagonal physical gates in the quantum circuit that induce a target logical gate based on one or more characteristics of the QECC and preserve the code space. The method generally also includes configuring, by the quantum computing system, the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more diagonal physical gates.

[0009] Another embodiment presented herein discloses a quantum computing system comprising a quantum circuit having a plurality of diagonal physical gates, a processor, and a controller comprising a memory having a plurality of instructions. The instructions, when executed by the processor, cause the quantum computing system to select a quantum error correcting code (QECC). The QECC is associated with a code space. The instructions further cause the quantum computing system to identify one or more diagonal physical gates in the quantum circuit that induce a target logic gate based on one or more characteristics of the QECC and preserve the code space. The instructions further cause the quantum computing system to configure the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more diagonal physical gates in the plurality of diagonal physical gates.

[0010] Yet another embodiment presented herein discloses a computer-readable storage medium storing a plurality of instructions. The plurality of instructions, when executed on a processor, causes a quantum computing processor to select a quantum error correcting code (QECC). The QECC is associated with a code space. The plurality of instructions further causes the quantum computing system to identify one or more diagonal physical gates in a quantum circuit that induces a target logical gate based on one or more characteristics of the QECC and preserves the code space. The plurality of instructions further causes the quantum computing system to configure the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more diagonal physical gates in the plurality of diagonal physical gates.

[0011] The concepts described herein are illustrated by way of example, and not by way of limitation, in the accompanying figures. For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or similar elements. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram of an exemplary ion trap quantum computer configured to implement a quantum error correction protocol based on codes constructed under a generator coefficient framework, according to an embodiment. [Diagram 2] FIG. 1 is a flow diagram of an exemplary method for implementing a quantum error correction protocol based on codes constructed under a generator coefficient framework, according to an embodiment. [Diagram 3] FIG. 1 is a flow diagram of an example method for identifying, from a CSS code, diagonal physical gates that derive a target diagonal logic gate and preserve the code space associated with the code, according to an embodiment. [Figure 4]FIG. 1 is a conceptual diagram of a quantum circuit illustrating a CSS code implemented in an exemplary MSD protocol, according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Quantum error correcting codes (QECCs) protect information as it is transformed by logic gates. The objective of fault tolerance in quantum computing proposes to construct QECCs that implement logic operators using transversal physical gates. As known, transversal gates are unitary tensor products on individual code blocks. However, the Eastin-Knill theorem teaches that QECCs cannot implement the universal set of logic gates exclusively through transversal physical gates. Magic state injection circumvents this limitation by consuming magic states to implement non-Clifford gates. Furthermore, state injection typically uses the magic state distillation (MSD) technique, which generates a high-fidelity magic state from multiple low-fidelity states. The MSD protocol uses Calderbank-Shor-Steane (CSS) codes that support fault-tolerant non-Clifford logic gates induced by transversal physical gates.

[0014] The embodiments presented herein disclose techniques for constructing QECCs that are conserved by diagonal physical gates in the underlying code space. More specifically, these techniques provide a generator coefficient framework that induces a target diagonal logic gate and synthesizes each possible diagonal physical gate for a CSS code that conserves the code space. Through the framework, the techniques enable optimization of quantum error correction in quantum computing systems based on the locality of physical gates, leading to improved fault tolerance.

[0015] In contrast to conventional approaches that fix transverse diagonal gates and target diagonal logic gates and then derive sufficient conditions for CSS codes, this approach instead fixes the CSS codes and uses a generator coefficient framework to identify each possible diagonal physical gate that induces the target diagonal logic gate based on properties associated with the CSS codes. Advantageously, the generator coefficient framework enables a systematic analysis of the locality of diagonal physical operators. Furthermore, the framework also enables the derivation of conditions on CSS codes that are necessary and sufficient for diagonal physical gates to preserve CSS codes and induce target diagonal logic gates. Furthermore, using the possible diagonal physical gates, the current approach also identifies physical gates that induce an identity mapping in the code space for the CSS codes, which enables CSS codes that are noise mitigating for a particular noisy system based on the correlation of idling noise represented by the physical gates. Codes constructed from the framework can be used in implementing various quantum error correction protocols, such as MSD.

[0016] It is noted that the present disclosure uses a trapped ion quantum computer as a reference example for adapting the generator coefficient framework for quantum error correction, however, those skilled in the art will recognize that in addition to trapped ion quantum computers, embodiments may also be applied to other types of quantum computing systems, such as quantum annealing systems, superconducting quantum computers, spin qubit quantum computers, etc.

[0017] FIG. 1 is a partial diagram of an exemplary ion trap quantum computer or system 100 for analyzing the locality of diagonal physical operators for creating QECCs in the decoherence-free subspace (DFS) of a noise system, according to one embodiment. The system 100 includes a classical (digital) computer 101, a system controller 118, and a quantum register that is a chain 102 of trapped ions (i.e., five as shown) extending along the Z-axis. The classical computer 101 includes a central processing unit (CPU), memory, and support circuits (or I / O). The memory is connected to the CPU and can be one or more of readily available memories, such as read-only memory (ROM), random access memory (RAM), floppy disk, hard disk, or any other form of digital storage, local or remote. Software instructions, algorithms, and data are encoded and stored in the memory to instruct the CPU. Support circuits (not shown) are also connected to the CPU to support the processor in a conventional manner. The support circuits can include conventional caches, power supplies, clock circuits, input / output circuits, subsystems, and the like.

[0018] An imaging objective 104, for example an objective with a numerical aperture (NA) of 0.37, collects fluorescence from the ions along the Y-axis and maps each ion to a multichannel photomultiplier tube (PMT) 106 for measurement of the individual ions. A non-co-propagating Raman laser beam from a laser 108 provided along the X-axis performs operations on the ions. A diffractive beam splitter 110 creates an array of static Raman beams 112 that are individually switched using a multichannel acousto-optic modulator (AOM) 114 and configured to selectively act on individual ions. A global Raman laser beam 116 illuminates all the ions at once. A system controller (also called an "RF controller") 118 controls the AOM 114. The system controller 118 includes a central processing unit (CPU) 120, a read-only memory (ROM) 122, a random access memory (RAM) 124, a storage unit 126, etc. The CPU 120 is the processor of the RF controller 118. The ROM 122 stores various programs, and the RAM 124 is a working memory for various programs and data. The storage unit 126 includes a non-volatile memory such as a hard disk drive (HDD) or a flash memory, and stores various programs even when the power is turned off. The CPU 120, the ROM 122, the RAM 124, and the storage unit 126 are interconnected via a bus 128.

[0019] The RF controller 118 executes a control program stored in the ROM 122 or storage unit 126 and uses the RAM 124 as a working area. The control program includes a software application including program code that can be executed by the processor to receive and analyze data and perform various functions related to controlling any and all aspects of the methods and hardware used to create the ion trap quantum computer system 100 discussed herein. For example, the control program may include program code for assembling each possible diagonal physical gate of the quantum circuit in the system 100 that induces a target diagonal logic gate, deriving conditions in the CSS code that are necessary and sufficient for the diagonal physical gate to preserve the CSS code and induce the logic gate, and implementing a generator coefficient framework and using the generator coefficient framework to implement a protocol (e.g., magic state distillation) quantum error computing code based on the identified locality of the diagonal physical gate. The control program may further include program code for instructing the system controller 118 (or other error correction components, not shown) to perform error correction for quantum computing based on the QECC design techniques disclosed herein.

[0020] Given a CSS code, the generator coefficient framework synthesizes each possible diagonal physical gate that conserves code space and induces a target logic gate. To do this, the system 100

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[0021] In addition, the diagonal entries of the diagonal physical gates are

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[0022] The generator coefficient framework of the embodiments described herein is preserved by the physical traversal T

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[0023] As a first issue, in an embodiment, the disclosed generator coefficient framework can be derived using the concepts of Pauli groups, Clifford hierarchies, and stabilizer codes.

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[0024] Additionally, the system 100 may

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[0025] D(a,b) can have orders of 1, 2, or 4,

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[0026] The first level of the Clifford hierarchy is the Pauli group C 1 =P N For l ≧2, the system 100 sets the level l as

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[0027] D N represents an N × N diagonal matrix,

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[0028] The system 100 divides the stabilizer group S into the Pauli group P N where all group elements are Hermitian and -I N Furthermore, there is no group element for which S = 〈v i E(c i ,d iIf S can be generated by r independent elements, where v : i = 1,...,r, then S has dimension r, where v i ∈{±1} and

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[0029] Given a stabilizer set S, the corresponding stabilizer code is

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[0030] For any Hermitian Pauli matrix E(c,d) and v∈{±1}, the operator

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[0031] As is well known, CSS codes are a particular type of stabilizer code whose generators can be separated into strictly X-type operators and strictly Z-type operators. For example, suppose there exist two classical binary codes C1, C2 such that C2 ⊂ C1, and

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[0032] Referring now to FIG. 2, in operation, the system 100 may execute a method 200 for implementing a generator coefficient framework for quantum error correction. As shown, the method 200 begins at block 202, where the system 100 identifies each possible diagonal physical gate that derives a target diagonal logic gate for a CSS code in a given code space and preserves the code space. To do this, for example, turning briefly to the method 300 of FIG. 3, the system 100 may select (at block 302) a CSS code (or otherwise obtain), identify (304) a diagonal physical gate in the quantum circuit, index (306) the diagonal entries within the identified gate, and identify (308) whether the entry meets specified criteria as described further below. In particular, in an embodiment, the generator coefficient framework may select (or otherwise obtain) a CSS code in a quantum circuit that derives a target diagonal logic gate for the CSS code in a given code space and preserves the code space.

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[0033] Hadamard Gate

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[0034] In an embodiment, an arbitrary code state ρ1 is prepared, and then the code state ρ1 is changed to obtain ρ2. U z Applying the probability ρ μ and the post-measurement state ρ3, which results from using the X stabilizer to measure ρ2 to obtain a syndrome μ with

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[0035] In an embodiment, the generator coefficient A μ,γ is the logical operator B μ Z logical Pauli operator

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[0036] Fixed

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[0037] In an embodiment, the physical gate Uz is

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[0038] In particular, the invariance of the code space is the trivial syndrome β μ=0 is equivalent to requiring that the logical operators induced by are unitary. Furthermore, (18)

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[0039] As an example, the [[15,1,3]] punctured quantum Reed-Muller code is

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[0040] Then, for wH(u)=0 or 8, u∈C1, d u = 1, for u∈C1 with wH(u) = 7 or 15

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[0041] The induced logical operator is the physical gate U z Given a CSS code and a target logic gate, the constraints on the corresponding physical gates are applied only to the diagonal elements corresponding to the coset C1+y.

[0042] As is well known, the quadratic form diagonal (QFD) physical gate is

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[0043] Using (23), the system 100

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[0044] As another example, the system 100 selects a Reed-Muller code, C1=RM(r1,m) ⊃ C2=RM(r2,m), with r1>r2.

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[0045] Given a CSS code, the generator coefficient framework not only represents when a physical diagonal gate conserves code space, but also characterizes all possible physical gates that realize the target diagonal logical gate. For example, assume that the logical operator is the identity operator.

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[0046] The mapping from physical gates to induced logical operators that preserves a given CSS code is a group homomorphism. The kernel of this homomorphism is the group of physical gates that induce the logical identity mapping. This therefore enables code design in the decoherence-free subspace (DFS) for noisy systems in quantum computing systems such as system 100. For uniform coherent noise (with the same angle at each physical qubit), U z For θ∈(0,2π),

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[0047] To realize a non-trivial diagonal logic gate in a given CSS code, the system 100 may characterize all possible physical gates in terms of a target logic gate.

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[0048] Next, on both sides of (31),

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[0049] The above is preserved by the physical traversal T

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[0050] for example,

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[0051] The above (39) allows the system 100 to directly determine whether a physical gate preserves a particular CSS code, and further allows the design of CSS codes that are preserved by particular physical diagonal gates. In addition, (39) also implies that CSS codes with more Z stabilizers (smaller than |C1|) can be preserved by more physical diagonal gates.

[0052] Referring back to Table I, all of the vectors of weight 0 and weight 8 are in C2, and all of the vectors of weight 7 and weight 15 are in coset C2+1. As mentioned before, diagonal entries in the same coset of C2 in C1 are identical. For example,

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[0053] In block 204, the system 100 configures a quantum computing circuit to implement a quantum error correction protocol using the CSS code and at least one of the identified diagonal physical gates. For example, an embodiment may be adapted for a magic state distillation (MSD) protocol that concatenates two codes, one inside the other (instead of using tri-orthogonal CSS codes directly). The [[n,k,d]] outer code may be selected from the code family disclosed above, e.g., a [[31,5,3]] code corresponding to m=5. The [[k,1,d']] inner code may be selected from a transverse T-gate in the outer code.

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[0054] One possible inner code used in combination with the [[31,5,3]] outer code is the [[5,1,3]] stabilizer code. Referring now to FIG. 4, a conceptual quantum circuit diagram is shown illustrating the CSS code implemented in the MSD protocol. In particular, FIG. 4 shows a 31-to-1 MSD protocol in which the system 100 concatenates a [[31,5,3]] CSS code and a [[5,1,3]] stabilizer code. The performance of the 31-to-1 MSD protocol has the same distillation curve as the 15-to-1 scheme, but the few-layer design / technique allows for a wide variety of potential MSD protocols to be reached.

[0055] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that there is no intention to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the scope of the present disclosure and the appended claims.

[0056] References herein to "one embodiment," "embodiment," "exemplary embodiment," and the like indicate that the embodiment being described may include a particular feature, structure, or characteristic, but all embodiments may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, if a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to operate such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described. Additionally, it should be understood that an item included in a list in the form "at least one of A, B, and C" can mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). Similarly, an item listed in the form "at least one of A, B, or C" can mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0057] The disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof, in some cases. The disclosed embodiments may also be implemented as instructions carried by or stored on a temporary or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure (e.g., volatile or non-volatile memory, media disk, or other media device) for storing or transmitting information in a form readable by a machine.

[0058] In the figures, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or ordering may not be required. Rather, in some embodiments, such features may be arranged in a different manner and / or order than that shown in the example figures. Additionally, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, it may not be included or may be combined with other features.

[0059] The present disclosure is considered to be illustrative and not restrictive. By its nature, all changes and modifications that come within the spirit and scope of the disclosure are desired to be protected. While certain aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art in view of the foregoing teachings.

[0060] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined from the following claims.

[0061] example Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more, and any combination, of the examples described below.

[0062] Example 1 includes a computer-implemented method for performing error correction in a quantum circuit of a quantum computing system, the computer-implemented method including: selecting, by the quantum computing system, a quantum error correcting code (QECC), where the QECC is associated with a code space; identifying, by the quantum computing system, one or more diagonal physical gates in the quantum circuit that induce a target logical gate based on one or more characteristics of the QECC and preserve the code space; and configuring, by the quantum computing system, the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more diagonal physical gates.

[0063] Example 2 includes the subject matter of Example 1, where the QECC is a Calderbank-Shor-Steane (CSS) code.

[0064] Example 3 includes the subject matter of any of Examples 1 and 2, wherein each diagonal physical gate includes a plurality of diagonal entries, and further includes indexing, by the quantum computing system, into the diagonal entries.

[0065] Example 4 includes the subject matter of any of examples 1-3, further including determining whether the indexed diagonal entries satisfy a specified criterion.

[0066] Example 5 includes the subject matter of any of Examples 1-4, wherein configuring the quantum computing circuit includes implementing a protocol incorporating at least a QECC to mitigate correlation based on correlation of idling noise represented by the identified diagonal physical gates.

[0067] Example 6 includes the subject matter of any of Examples 1-5, wherein configuring the quantum computing circuit to implement a quantum error correction protocol includes constructing one or more QECCs that are unaware of the identified diagonal physical gates.

[0068] Example 7 includes the subject matter of any of Examples 1-6, wherein the quantum computing system is an ion trap quantum computing system.

[0069] Example 8 includes a quantum computing system comprising a quantum circuit having a plurality of diagonal physical gates, a processor, and a controller comprising a memory having a plurality of instructions, wherein the plurality of instructions, when executed by the processor, cause the quantum computing system to: select a quantum error correcting code (QECC), where the QECC is associated with a code space; identify one or more diagonal physical gates in the quantum circuit that induce a target logical gate to preserve the code space based on one or more characteristics of the QECC; and configure the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more diagonal physical gates of the plurality of diagonal physical gates.

[0070] Example 9 includes the subject matter of Example 8, where the QECC is a Calderbank-Shor-Steane (CSS) code.

[0071] Example 10 includes the subject matter of any of examples 8 and 9, wherein each diagonal physical gate includes a plurality of diagonal entries, and the instructions further cause the quantum computing system to index into the diagonal entries.

[0072] Example 11 includes the subject matter of any of Examples 8-10, wherein the instructions further cause the quantum computing system to determine whether the indexed diagonal entry satisfies a specified criterion.

[0073] Example 12 includes the subject matter of any of Examples 8-11, wherein configuring the quantum computing circuit includes implementing a protocol incorporating at least a QECC to mitigate correlation based on correlation of idling noise represented by the identified diagonal physical gates.

[0074] Example 13 includes the subject matter of any of Examples 8-12, wherein configuring the quantum computing circuit to implement a quantum error correction protocol includes constructing one or more QECCs that are unaware of the identified diagonal physical gates.

[0075] Example 14 includes the subject matter of any of Examples 8-13, wherein the quantum computing system is an ion trap quantum computing system.

[0076] Example 15 includes a computer-readable storage medium storing a plurality of instructions that, when executed by a processor, cause a quantum computing system to: select a quantum error correcting code (QECC), where the QECC is associated with a code space; identify, based on one or more characteristics of the QECC, one or more diagonal physical gates in a quantum circuit that direct a target logical gate to preserve the code space; and configure the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more diagonal physical gates of the plurality of diagonal physical gates.

[0077] Example 16 includes the subject matter of Example 15, where the QECC is a Calderbank-Shor-Steane (CSS) code.

[0078] Example 17 includes the subject matter of any of examples 15 and 16, wherein each diagonal physical gate includes a plurality of diagonal entries, and the instructions further cause the quantum computing system to index into the diagonal entries.

[0079] Example 18 includes the subject matter of any of Examples 15-17, wherein the instructions further cause the quantum computing system to determine whether the indexed diagonal entry satisfies a specified criterion.

[0080] Example 19 includes the subject matter of any of Examples 15-18, wherein configuring the quantum computing circuit includes implementing a protocol incorporating at least a QECC to mitigate correlation based on correlation of idling noise represented by the identified diagonal physical gates.

[0081] Example 20 includes the subject matter of any of Examples 15-19, wherein configuring the quantum computing circuit to implement a quantum error correction protocol includes constructing one or more QECCs that are unaware of the identified diagonal physical gates. [Explanation of symbols]

[0082] 100 Ion trap quantum computer or system 101 Classical (Digital) Computers 102 Chain 104 Imaging Objective Lens 106 Multichannel Photomultiplier Tube (PMT) 108 Laser 110 Diffractive Beam Splitter 112 Static Raman beam 114 Multi-channel Acousto-Optic Modulator (AOM) 116 Global Raman Laser Beam 118 System Controller 120 Central Processing Unit (CPU) 122 Read-Only Memory (ROM) 124 Random Access Memory (RAM) 126 Storage Unit 128 Bus

Claims

1. 1. A computer-implemented method for performing error correction in a quantum circuit of a quantum computing system, comprising: selecting, by the quantum computing system, a quantum error correcting code (QECC), the QECC being associated with a code space; deriving, by the quantum computing system, a target logical gate based on one or more properties of the QECC and identifying one or more diagonal physical gates in the quantum circuit that preserve the code space; configuring, by the quantum computing system, a quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more diagonal physical gates; 4. A computer-implemented method comprising:

2. 2. The computer-implemented method of claim 1, wherein the QECC is a Calderbank-Shor-Steane (CSS) code.

3. 2. The computer-implemented method of claim 1, wherein each diagonal physical gate includes a plurality of diagonal entries, and further comprising indexing, by the quantum computing system, into the diagonal entries.

4. The computer-implemented method of claim 3 , further comprising determining whether the indexed diagonal entries meet a specified criterion.

5. 2. The computer-implemented method of claim 1, wherein configuring the quantum computing circuit comprises implementing a protocol incorporating at least the QECC to mitigate the correlation based on correlation of idling noise represented by the identified diagonal physical gates.

6. 2. The computer-implemented method of claim 1, wherein configuring the quantum computing circuit to implement the quantum error correction protocol comprises constructing one or more QECCs that do not recognize the identified diagonal physical gates.

7. 10. The computer-implemented method of claim 1, wherein the quantum computing system is an ion trap quantum computing system.

8. A quantum circuit having a plurality of diagonal physical gates; A processor; A controller having a memory with a plurality of instructions; wherein the instructions, when executed by the processor, cause the quantum computing system to: selecting a quantum error correcting code (QECC), the QECC being associated with a code space; inducing a target logic gate to identify one or more of the diagonal physical gates in the quantum circuit that preserves the code space based on one or more characteristics of the QECC; configuring a quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more of the plurality of diagonal physical gates; A quantum computing system that performs the above.

9. 9. The quantum computing system of claim 8, wherein the QECC is a Calderbank-Shor-Steane (CSS) code.

10. 10. The quantum computing system of claim 8, wherein each diagonal physical gate includes a plurality of diagonal entries, and wherein the instructions further cause the quantum computing system to index into the diagonal entries.

11. 11. The quantum computing system of claim 10, wherein the instructions further cause the quantum computing system to determine whether the indexed diagonal entry satisfies a specified criterion.

12. 10. The quantum computing system of claim 8, wherein configuring the quantum computing circuitry includes implementing a protocol incorporating at least the QECC to mitigate the correlation based on a correlation of idling noise represented by the identified diagonal physical gates.

13. 10. The quantum computing system of claim 8, wherein configuring the quantum computing circuitry to implement the quantum error correction protocol comprises constructing one or more QECCs that do not recognize the identified diagonal physical gates.

14. The quantum computing system of claim 8 , wherein the quantum computing system is an ion trap quantum computing system.

15. 1. A computer-readable storage medium storing a plurality of instructions, the plurality of instructions, when executed by a processor, for providing a quantum computing system comprising: selecting a quantum error correcting code (QECC), the QECC being associated with a code space; inducing a target logic gate to identify one or more diagonal physical gates in a quantum circuit that preserves the code space based on one or more characteristics of the QECC; configuring a quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified one or more of a plurality of diagonal physical gates; A computer-readable storage medium for causing a computer to perform the above steps.

16. 16. The computer-readable storage medium of claim 15, wherein the QECC is a Calderbank-Shor-Steane (CSS) code.

17. 16. The computer-readable storage medium of claim 15, wherein each diagonal physical gate includes a plurality of diagonal entries, the plurality of instructions further causing the quantum computing system to index into the diagonal entries.

18. 20. The computer-readable storage medium of claim 17, wherein the instructions further cause the quantum computing system to determine whether the indexed diagonal entry satisfies a specified criterion.

19. 16. The computer-readable storage medium of claim 15, wherein configuring the quantum computing circuit includes implementing a protocol incorporating at least the QECC to mitigate the correlation based on a correlation of idling noise represented by the identified diagonal physical gates.

20. 16. The computer-readable storage medium of claim 15, wherein configuring the quantum computing circuit to implement the quantum error correction protocol comprises constructing one or more QECCs that do not recognize the identified diagonal physical gates.

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