Display device and tiled display device including same

Abstract

A display device is provided, the display device including a plurality of anode electrodes respectively corresponding to a plurality of sub-pixels, a plurality of cathode electrodes respectively corresponding to the plurality of sub-pixels and arranged apart from the plurality of anode electrodes, a cathode wiring connected to the plurality of cathode electrodes, a plurality of anode pads respectively covering the plurality of anode electrodes, a plurality of cathode pads respectively covering the plurality of cathode electrodes, and a cathode wiring pad covering at least a portion of the cathode wiring.

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of the information society, the demands for display devices for displaying images are becoming more and more diverse. The display devices may be flat panel display devices such as liquid crystal displays, field emission displays, light emitting displays, etc.

[0003] The light emitting display device includes an organic light emitting display device including an organic light emitting diode element as a light emitting element, or a light emitting diode display device including an inorganic light emitting diode element such as an LED (Light Emitting Diode) as a light emitting element. In the case of an organic light emitting display device, the brightness or gray scale of the light of the organic light emitting diode element is adjusted by adjusting the magnitude of the driving current applied to the organic light emitting diode element. However, since the wavelength of light emitted by the inorganic light emitting diode element changes depending on the driving current, the image quality is degraded when driven in the same manner as the organic light emitting diode element. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of reducing short-circuit defects of light-emitting elements.

[0005] The object of the present invention is not limited to the above-mentioned objects, and other technical objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] According to an embodiment of the present invention, a display device includes a substrate including a display region in which a plurality of sub-pixels are arranged, an active layer disposed on the substrate, a gate insulating film covering the active layer, a first interlayer insulating film covering a first conductive layer disposed on the gate insulating film, a second interlayer insulating film covering a second conductive layer disposed on the first interlayer insulating film, a first planarization film covering a third conductive layer disposed on the second interlayer insulating film, a second planarization film covering a fourth conductive layer disposed on the first planarization film, a third planarization film covering a fifth conductive layer disposed on the second planarization film, a sixth conductive layer disposed on the third planarization film, and a seventh conductive layer disposed on at least a portion of the sixth conductive layer. The sixth conductive layer includes a plurality of anode electrodes corresponding to the plurality of sub-pixels, a plurality of cathode electrodes corresponding to the plurality of sub-pixels and disposed apart from the plurality of anode electrodes, and cathode wirings connected to the plurality of cathode electrodes. The seventh conductive layer includes a plurality of anode pads covering the plurality of anode electrodes, respectively, a plurality of cathode pads covering the plurality of cathode electrodes, respectively, and a cathode wiring pad covering at least a portion of the cathode wiring.

[0007] In each of the plurality of subpixels, the anode pad may be disposed on the anode electrode, cover an upper surface and a side surface of the anode electrode, and be in contact with the third planarization film, and the cathode pad may be disposed on the cathode electrode, cover an upper surface and a side surface of the cathode electrode, and be in contact with the third planarization film.

[0008] In each of the plurality of sub-pixels, the cathode wiring pad may cover an edge of the cathode wiring that faces each of the anode electrode and the cathode electrode.

[0009] The cathode wiring pad may be disposed on an edge of the cathode wiring, cover an upper surface and a side surface of the edge of the cathode wiring, and be in contact with the third planarization film.

[0010] In each of the plurality of sub-pixels, the cathode wiring pad may be positioned away from the anode pad, correspond to boundaries between the anode electrode and the cathode electrode and the cathode wiring, and form a closed loop shape together with at least a portion of an edge of the cathode pad.

[0011] The anode electrodes and the cathode electrodes of adjacent sub-pixels in one direction among the plurality of sub-pixels may be arranged side by side in the one direction.

[0012] The cathode wiring pads may correspond to the plurality of sub-pixels, respectively, and the cathode wiring pads of the sub-pixels adjacent to each other in the one direction may be spaced apart from each other.

[0013] Alternatively, a plurality of pixels may be provided, each of which is composed of two or more sub-pixels adjacent to each other in the one direction among the plurality of sub-pixels, and the cathode wiring pad may correspond to each of the plurality of pixels and be further disposed at a boundary between the two or more sub-pixels included in each of the plurality of pixels, and the cathode wiring pads of the sub-pixels adjacent to each other in the one direction and corresponding to different pixels may be disposed apart from each other.

[0014] Alternatively, the cathode wiring pads may correspond to the sub-pixels adjacent in the one direction, and may be further disposed at the boundary between the sub-pixels adjacent in the one direction.

[0015] Alternatively, the cathode wiring pad may cover the entire cathode wiring.

[0016] Alternatively, each of the plurality of anode pads, the plurality of cathode pads and the cathode wiring pad may extend onto the third planarization film.

[0017] The display device may further include a scan write wiring to which a scan write signal is applied, a scan initialization wiring to which a scan initialization signal is applied, a sweep signal wiring to which a sweep signal is applied, a first data wiring to which a first data voltage is applied, and a second data wiring to which a second data voltage is applied. Each of the plurality of sub-pixels may be connected to the scan write wiring, the scan initialization wiring, the sweep signal wiring, the first data wiring, and the second data wiring. Each of the plurality of sub-pixels may include a first pixel driver generating a control current in response to the first data voltage of the first data wiring, a second pixel driver generating a drive current to be applied to the anode electrode in response to the second data voltage of the second data wiring, and a third pixel driver controlling a period for passing the drive current to a light emitting element in response to the control current of the first pixel driver. The first pixel driving unit may include a first transistor generating the control current in response to the first data voltage, a second transistor applying the first data voltage of the first data line to a first electrode of the first transistor in response to the scan write signal, a third transistor applying an initialization voltage of an initialization voltage line to a gate electrode of the first transistor in response to the scan initialization signal, a fourth transistor connecting the gate electrode and a second electrode of the first transistor in response to the scan write signal, and a first capacitor disposed between the sweep signal line and the gate electrode of the first transistor.

[0018] The display device may further include a first power supply wiring to which a first power supply voltage is applied, a second power supply wiring to which a second power supply voltage is applied, a first light emission wiring to which a first light emission signal is applied, and a scan control wiring to which a scan control signal is applied. The first pixel driving unit may further include a fifth transistor connecting the first power supply wiring to a first electrode of the first transistor in response to the first light emission signal, a sixth transistor connecting a second electrode of the first transistor to a first node in response to the first light emission signal, and a seventh transistor connecting the sweep signal wiring to a gate-off voltage wiring to which a gate-off voltage is applied in response to the scan control signal.

[0019] The second pixel driving unit may include an eighth transistor generating the driving current in response to the second data voltage, a ninth transistor applying the second data voltage of the second data line to a first electrode of the eighth transistor in response to the scan write signal, a tenth transistor applying an initialization voltage of the initialization voltage line to a gate electrode of the eighth transistor in response to the scan initialization signal, and an eleventh transistor connecting a gate electrode and a second electrode of the first transistor in response to the scan write signal.

[0020] The second pixel driving unit may further include a twelfth transistor connecting the first power supply wiring to a second node in response to the scan control signal, a thirteenth transistor connecting the second power supply wiring to a first electrode of the ninth transistor in response to the first light emitting signal, a fourteenth transistor connecting the second power supply wiring to the second node in response to the first light emitting signal, and a second capacitor disposed between a gate electrode of the ninth transistor and the second node.

[0021] The third pixel driving unit may include a 15th transistor including a gate electrode connected to the third node, a 16th transistor connecting the first node to the initialization voltage wiring in response to the scan control signal, a 17th transistor connecting a second electrode of the 15th transistor to a first electrode of the light emitting element in response to the second light emitting signal, an 18th transistor connecting the first electrode of the light emitting element to the initialization voltage wiring in response to the scan control signal, and a third capacitor disposed between the first node and the initialization voltage wiring.

[0022] The display device may further include a test signal line to which a test signal is applied and a third power line to which a third power voltage is applied. The third pixel driving part may further include a 19th transistor connecting a first electrode of the light emitting element to the third power line in response to the test signal. The cathode line may be connected to the third power line.

[0023] The active layer may include channels, source electrodes, and drain electrodes of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, 12th, 13th, 14th, 15th, 16th, 17th, 18th, and 19th transistors, respectively, the first conductive layer may include gate electrodes of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, 12th, 13th, 14th, 15th, 16th, 17th, 18th, and 19th transistors, respectively, and first, third, and fifth capacitor electrodes which are one end of the first, second, and third capacitors, respectively, and the second conductive layer may include second, fourth, and sixth capacitor electrodes which are the other end of the first, second, and third capacitors, respectively.

[0024] The third conductive layer includes the initialization voltage wiring, the scan initialization wiring, the scan write wiring, the first light emitting wiring, the second light emitting wiring, a first horizontal power supply wiring to which the first power supply voltage is applied, the sweep signal wiring, a gate-off voltage wiring, a scan control wiring, a test signal wiring, and a third auxiliary power supply wiring to which the third power supply voltage is applied, and the fourth conductive layer includes the first data wiring, a first vertical power supply wiring to which the first power supply voltage is applied, the second data wiring, and a first anode connecting electrode, and the first anode connecting electrode may be connected to a drain electrode of the 17th transistor and a drain electrode of the 18th transistor.

[0025] The fifth conductive layer may include the third power wiring and a second anode connecting electrode connected to the first anode connecting electrode.

[0026] The display device may further include a protective film disposed on the third planarization film and covering edges of the anode pads, edges of the cathode pads, the cathode wiring pad, and the cathode wiring. In each of the sub-pixels, the anode pad may be connected to a first contact electrode of a light-emitting element via an anode contact electrode, and the cathode pad may be connected to a second contact electrode of the light-emitting element via a cathode contact electrode.

[0027] According to an embodiment of the present invention, a tiled display device includes a plurality of display devices and a seam portion disposed between the plurality of display devices. Any one of the plurality of display devices includes a substrate including a display region in which a plurality of sub-pixels are arranged, an active layer disposed on the substrate, a gate insulating film covering the active layer, a first interlayer insulating film covering a first conductive layer disposed on the gate insulating film, a second interlayer insulating film covering a second conductive layer disposed on the first interlayer insulating film, a first planarization film covering a third conductive layer disposed on the second interlayer insulating film, a second planarization film covering a fourth conductive layer disposed on the first planarization film, a third planarization film covering a fifth conductive layer disposed on the second planarization film, a sixth conductive layer disposed on the third planarization film, and a seventh conductive layer disposed on at least a portion of the sixth conductive layer. The sixth conductive layer includes a plurality of anode electrodes corresponding to the plurality of sub-pixels, a plurality of cathode electrodes corresponding to the plurality of sub-pixels and spaced apart from the plurality of anode electrodes, and a cathode wiring connected to the plurality of cathode electrodes. The seventh conductive layer includes a plurality of anode pads covering the plurality of anode electrodes, a plurality of cathode pads covering the plurality of cathode electrodes, and a cathode wiring pad covering at least a portion of the cathode wiring.

[0028] The substrate may be made of glass.

[0029] Any one of the display devices may further include a pad arranged on a first surface of the substrate, and a side wiring arranged on the first surface of the substrate, a second surface opposite to the first surface, and one side between the first surface and the second surface and connected to the pad.

[0030] Any one of the display devices may further include a connecting wire disposed on a second surface of the substrate, and a flexible film connected to the connecting wire via a conductive adhesive member. The side wiring may be connected to the connecting wire.

[0031] The plurality of display devices may be arranged in a matrix of M rows and N columns.

[0032] The display device may further include a plurality of light emitting devices disposed on the anode electrodes and the cathode electrodes of the sub-pixels, The light emitting devices may be flip-chip type micro light emitting diode devices.

[0033] In each of the sub-pixels, the anode pad may be disposed on the anode electrode, cover an upper surface and a side surface of the anode electrode, and be in contact with the third planarization film. The cathode pad may be disposed on the cathode electrode, cover an upper surface and a side surface of the cathode electrode, and be in contact with the third planarization film.

[0034] In each of the plurality of sub-pixels, the cathode wiring pad may cover an edge of the cathode wiring that faces the anode electrode and the cathode electrode, respectively.

[0035] The cathode wiring pad may be disposed on an edge of the cathode wiring, cover an upper surface and a side surface of the edge of the cathode wiring, and be in contact with the third planarization film.

[0036] In each of the plurality of sub-pixels, the cathode wiring pad may be disposed away from the anode pad, may correspond to boundaries between the anode electrode and the cathode electrode, and may form a closed loop shape together with at least a part of an edge of the cathode pad. The anode electrodes and the cathode electrodes of adjacent sub-pixels in one direction among the plurality of sub-pixels may be arranged side by side in the one direction.

[0037] The plurality of anode pads, the plurality of cathode pads, and the cathode wiring pad may each extend onto the third planarization film.

[0038] Specific details of other embodiments are included in the detailed description and drawings. Effect of the Invention

[0039] A display device according to an embodiment includes a plurality of anode electrodes corresponding to the plurality of subpixels, a plurality of cathode electrodes corresponding to the plurality of subpixels and arranged apart from the plurality of anode electrodes, cathode wiring connected to the plurality of cathode electrodes, a plurality of anode pads covering the plurality of anode electrodes, a plurality of cathode pads covering the plurality of cathode electrodes, and a cathode wiring pad covering at least a portion of the cathode wiring.

[0040] In each of the multiple sub-pixels, the anode pad covers the upper surface and side surfaces of the anode electrode, the cathode pad covers the upper surface and side surfaces of the cathode electrode, and the cathode wiring pad covers the upper surface and side surfaces of the edges of the cathode wiring that face each of the anode electrode and the cathode electrode.

[0041] In this way, the side surfaces of the anode electrode, the side surfaces of the cathode electrode, and the side surfaces of the edges of the cathode wiring are not exposed in the patterning process for arranging the anode pad, the cathode pad, and the cathode wiring pad, and therefore an undercut structure is not formed. This makes it possible to prevent peeling of the protective film due to the undercut structure, and therefore to prevent short-circuiting defects of the light-emitting element.

[0042] The effects of the embodiments are not limited to the above examples, and more diverse effects are included in the present specification. [Brief description of the drawings]

[0043] [Figure 1] 1 is a plan view illustrating a display panel of a display device according to an embodiment. [Diagram 2] FIG. 2 is an illustrative diagram showing an example of a pixel in FIG. [Diagram 3] 1. FIG. 4 is a diagram illustrating still another example of the pixel in FIG. [Figure 4] 3 is a cross-sectional view showing an example of a display panel taken along line AA' in FIG. 2. [Diagram 5]1 is a block diagram showing a display device according to an embodiment. [Figure 6] FIG. 4 is a circuit diagram illustrating a first sub-pixel according to an embodiment. [Figure 7] 11 is a graph showing the wavelength of light emitted by a light-emitting element of a first sub-pixel, the wavelength of light emitted by a light-emitting element of a second sub-pixel, and the wavelength of light emitted by a light-emitting element of a third sub-pixel according to a driving current according to one embodiment. [Figure 8] 11 is a graph showing the luminous efficiency of a light emitting element of a first sub-pixel, the luminous efficiency of a light emitting element of a second sub-pixel, and the luminous efficiency of a light emitting element of a third sub-pixel as a function of a driving current according to an embodiment. [Figure 9] 1 is an exemplary diagram illustrating an operation of a display device during an N-th to (N+2)-th frame period. [Figure 10] 11 is yet another exemplary diagram illustrating an operation of the display device during the Nth to (N+2)th frame periods. [Figure 11] FIG. 11 is a waveform diagram showing a scan initialization signal, a scan write signal, a scan control signal, a PWM light-emitting signal, a PAM light-emitting signal, and a sweep signal applied to sub-pixels arranged on row lines k to k+5 in an N-th frame period according to an embodiment. [Figure 12] FIG. 11 is a waveform diagram showing a period during which the kth scan initialization signal, the kth scan write signal, the kth scan control signal, the kth PWM light-emitting signal, the kth PAM light-emitting signal, and the kth sweep signal are applied to each of the sub-pixels arranged on the kth row line in the Nth frame period according to an embodiment, the voltage of the third node, and the driving current applied to the light-emitting element are applied. [Figure 13] FIG. 11 is a timing diagram illustrating a kth sweep signal, a voltage of a gate electrode of a first transistor, a turn-on timing of the first transistor, and a turn-on timing of a fifteenth transistor during a fifth period and a sixth period according to an embodiment. [Figure 14] 13 is a circuit diagram showing an operation of the first sub-pixel in a first period in FIG. 12. FIG. [Figure 15] 13 is a circuit diagram showing an operation of the first sub-pixel in a second period in FIG. 12. FIG. [Figure 16] 13 is a circuit diagram showing an operation of the first sub-pixel in a third period in FIG. 12. FIG. [Figure 17] 13 is a circuit diagram showing an operation of the first sub-pixel in a sixth period in FIG. 12. FIG. [Figure 18] 4 is a layout diagram showing an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of a first sub-pixel according to an embodiment. FIG. [Figure 19] FIG. 19 is an enlarged layout diagram showing in detail area I of FIG. [Figure 20] FIG. 19 is an enlarged layout diagram showing in detail region II of FIG. 18. [Figure 21] FIG. 19 is an enlarged layout diagram showing in detail region III of FIG. 18. [Figure 22] 19 is a layout diagram showing an example of a fifth conductive layer of the first sub-pixel shown in FIG. 18. [Figure 23] 19 is a layout diagram showing an example of a sixth conductive layer of the first sub-pixel shown in FIG. 18. [Figure 24] 19 is a layout diagram showing an example of a seventh conductive layer of the first sub-pixel shown in FIG. 18. FIG. [Diagram 25] 19 is a cross-sectional view showing an example of a display panel taken along line BB' in FIG. 18. [Figure 26] 19 is a cross-sectional view showing an example of a display panel taken along CC' in FIG. 18. [Figure 27] 19 is a cross-sectional view showing an example of a display panel taken along the line DD' in FIG. 18. [Figure 28] 19 is a cross-sectional view showing an example of a display panel taken along the line EE' in FIG. 18. [Figure 29] 19 is a cross-sectional view showing an example of a display panel taken along the line FF' in FIG. 18. [Diagram 30] 19 is a cross-sectional view showing an example of a display panel taken along line GG' in FIG. 18. [Diagram 31] 19 is a cross-sectional view showing an example of a display panel taken along the line HH' in FIG. 18. [Diagram 32]19 is a cross-sectional view showing an example of a display panel taken along II' in FIG. 18. [Diagram 33] 19 is a cross-sectional view showing an example of a display panel taken along the line J-J' in FIG. 18. [Diagram 34] 25 is a cross-sectional view showing an example of a display panel taken along the line K-K' in FIGS. 18, 22, and 24. FIG. [Diagram 35] 25 is a cross-sectional view showing an example of a display panel taken along the line K-K' in FIGS. 18, 22, and 24. FIG. [Diagram 36] 25 is a cross-sectional view showing another example of a display panel taken along the line K-K' in FIGS. 18, 22, and 24. FIG. [Figure 37] 4 is a layout diagram showing sixth conductive layers and seventh conductive layers of sub-pixels aligned in a first direction according to the first embodiment. FIG. [Figure 38] FIG. 11 is a layout diagram showing sixth and seventh conductive layers of sub-pixels aligned in a first direction according to a second embodiment. [Figure 39] FIG. 11 is a layout diagram showing sixth and seventh conductive layers of sub-pixels aligned in a first direction according to a third embodiment. [Diagram 40] FIG. 13 is a layout diagram showing sixth conductive layers and seventh conductive layers of sub-pixels aligned in a first direction according to a fourth embodiment. [Diagram 41] 1 is a perspective view illustrating a tiled display device including a plurality of display devices according to an embodiment. [Diagram 42] FIG. 42 is an enlarged layout diagram showing the L region in detail in FIG. 41. [Diagram 43] 44 is a cross-sectional view showing an example of a tiled display device taken along the line NN' in FIG. 43. [Diagram 44] FIG. 42 is an enlarged layout diagram showing the M region of FIG. 41 in detail. [Diagram 45] 45 is a cross-sectional view showing an example of a tiled display device taken along the line O-O' in FIG. 44. [Diagram 46] FIG. 1 is a block diagram showing a tiled display device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] The advantages and features of the present invention, as well as the methods for achieving the same, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains, and the present invention is defined only by the scope of the claims.

[0045] When elements or layers are referred to as "on" other elements or layers, this includes all cases where other layers or other elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments are merely illustrative, and the present invention is not limited to the illustrated matters.

[0046] Although the terms "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that the first component referred to below may be the second component within the technical concept of the present invention.

[0047] The respective features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and various technical interlocking and driving mechanisms are possible, and each embodiment may be implemented independently of each other or in conjunction with each other.

[0048] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0049] Fig. 1 is a plan view illustrating a display device according to an embodiment, Fig. 2 is a diagram illustrating an example of a pixel of Fig. 1, Fig. 3 is a diagram illustrating another example of the pixel of Fig. 1.

[0050] Referring to FIG. 1, a display device including a flat display panel 100 is a device for displaying moving or still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT).

[0051] The display panel 100 may be formed as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting with the first direction DR1. A corner where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded or formed at a right angle to have a predetermined curvature. The plane shape of the display panel 100 is not limited to a rectangle, and may be formed as other polygonal, circular, or elliptical shapes. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed at left and right side edges and having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed flexibly so that it can be bent, warped, bent, folded, or rolled.

[0052] The display panel 100 may further include pixels PX for displaying images, scan lines extending in a first direction DR1, and data lines extending in a second direction DR2. The pixels PX may be arranged in a matrix in the first direction DR1 and the second direction DR2.

[0053] Each pixel PX may include multiple sub-pixels RP, GP, and BP, as shown in Figures 2 and 3. Figures 2 and 3 illustrate an example in which each pixel PX includes three sub-pixels RP, GP, and BP, i.e., a first sub-pixel RP, a second sub-pixel GP, and a third sub-pixel BP, but the embodiments of this specification are not limited to this.

[0054] The first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be connected to one of the data lines and at least one of the scan lines.

[0055] Each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may have a rectangular, square, or diamond planar shape.

[0056] For example, as shown in FIG. 2, each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a rectangular planar shape with a shorter side in the first direction DR1 and a longer side in the second direction DR2.

[0057] Alternatively, as shown in FIG. 3, each of the first subpixel RP, the second subpixel GP, and the third subpixel BP may have a square or diamond planar shape including sides having the same length in the first direction DR1 and the second direction DR2.

[0058] 2, the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be arranged in a first direction DR1, or one of the second sub-pixel GP and the third sub-pixel BP and the first sub-pixel RP may be arranged in the first direction DR1, and the remaining one of the second sub-pixel GP and the first sub-pixel RP may be arranged in the second direction DR2.

[0059] For example, as shown in FIG. 3, the first sub-pixel RP and the second sub-pixel GP may be arranged in a first direction DR1, and the first sub-pixel RP and the third sub-pixel BP may be arranged in a second direction DR2.

[0060] Alternatively, the first sub-pixel RP, any one of the third sub-pixel BP, and the second sub-pixel GP may be arranged in the first direction DR1, and the remaining one and the second sub-pixel GP may be arranged in the second direction DR2. Alternatively, the first sub-pixel RP, any one of the second sub-pixel GP, and the third sub-pixel BP may be arranged in the first direction DR1, and the remaining one and the third sub-pixel BP may be arranged in the second direction DR2.

[0061] The first sub-pixel RP may emit a first light, the second sub-pixel GP may emit a second light having a color different from the first light, and the third sub-pixel BP may emit a third light having a color different from the first light and the second light.

[0062] As an example, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band, where the red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0063] Each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element that emits light. For example, the inorganic light-emitting element may be a flip chip type micro LED (Light Emitting Diode), but the embodiment of the present specification is not limited thereto.

[0064] 2 and 3, the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be substantially the same, but the embodiments of the present specification are not limited thereto. At least one of the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be different from the others. Alternatively, any two of the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be substantially the same, and the remaining one may be different from the two. Alternatively, the areas of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be different from each other.

[0065] FIG. 4 is a cross-sectional view showing an example of a display device taken along the line AA' in FIG.

[0066] 4, a thin film transistor layer TFTL may be disposed on a substrate SUB. The thin film transistor layer TFTL may be a layer in which a thin film transistor (TFT) is formed. A detailed description of the thin film transistor layer TFTL will be given later.

[0067] The substrate SUB may be a member for supporting the display device 10. The substrate SUB may be a rigid substrate made of a glass material. Alternatively, the substrate SUB may be a flexible substrate that allows bending, folding, rolling, etc. In this case, the substrate SUB may include an insulating material such as a polymer resin, such as polyimide (PI).

[0068] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL.

[0069] The light-emitting element layer EML includes an anode electrode AND, a cathode electrode CTD, and a light-emitting element LE.

[0070] The light-emitting element layer EML may further include an anode contact electrode ANDC between the light-emitting element LE and the anode electrode AND, and a cathode contact electrode CTDC between the light-emitting element LE and the cathode electrode CTD.

[0071] Each of the light emitting elements LE may include a base substrate BSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first contact electrode CTE1, and a second contact electrode CTE2.

[0072] The base substrate BSUB may be a sapphire substrate, although embodiments herein are not limited thereto.

[0073] The n-type semiconductor NSEM may be disposed on one side of the base substrate BSUB. For example, the n-type semiconductor NSEM may be disposed on a lower side of the base substrate BSUB. The n-type semiconductor NSEM may be made of GaN doped with an n-type conductivity dopant such as Si, Ge, Sn, or the like.

[0074] The active layer MQW may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single or multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layers are formed of InGaN, and the barrier layers are formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, and may include different Group 3 to Group 5 semiconductor materials according to the wavelength band of the emitted light.

[0075] The p-type semiconductor PSEM may be disposed on one surface of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Se, Ba, or the like.

[0076] The first contact electrode CTE1 may be disposed on the p-type semiconductor PSEM, and the second contact electrode CTE2 may be disposed on another part of one surface of the n-type semiconductor NSEM. The other part of the one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed away from the part of the one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

[0077] The first contact electrode CTE1 and the anode electrode AND may be bonded to each other via the anode contact electrode ANDC.

[0078] The second contact electrode CTE2 and the cathode electrode CTD can be bonded to each other via the cathode contact electrode CTDC.

[0079] The anode contact electrode ANDC and the cathode contact electrode CTDC may be a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP).

[0080] Alternatively, the light-emitting element LE does not include the anode contact electrode ANDC and the cathode contact electrode CTDC, and instead, the first contact electrode CTE1 and the anode electrode AND, and the second contact electrode CTE2 and the cathode electrode CSD may be bonded by a soldering process.

[0081] The light emitting element LE may be a flip-chip type micro LED.

[0082] Such a flip-chip type light emitting element LE includes a first contact electrode CTE1 arranged on a p-type semiconductor PSEM, and a second contact electrode CTE2 arranged on an n-type semiconductor NSEM exposed by removing a part of the active layer MQW and the p-type semiconductor PSEM. That is, the flip-chip type light emitting element LE has a mesa (MESA) structure in which the first contact electrode CTE1 protrudes from the second contact electrode CTE2. 。

[0083] No. Each of the first, second, and third sub-pixels RP, GP, and BP includes a light-emitting element LE connected to an anode electrode AND and a cathode electrode CSD. The anode electrode AND corresponds to each of the sub-pixels RP, GP, and BP, and can be called a pixel electrode. And, the cathode electrode CTD is common to the sub-pixels RP, GP, and BP, and can be called a common electrode.

[0084] The anode electrode AND and the cathode electrode CTD can include highly reflective metallic materials such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a laminated structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0085] In the light-emitting element LE, the length in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 may be several to several hundred μm. For example, the length in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 of the light-emitting element LE may be approximately 100 μm or less.

[0086] The light emitting element LE can be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the light emitting elements LE can be directly transferred from the silicon wafer onto the anode electrode AND and the cathode electrode CTD of the substrate SUB. Alternatively, each of the light emitting elements LE can be transferred onto the anode electrode AND and the cathode electrode CTD of the substrate SUB by an electrostatic method using an electrostatic head or a stamp method using an elastic polymeric material such as PDMS or silicon as a transfer substrate.

[0087] The light-emitting element layer EML may further include a protective film PAS that covers the edges of the anode electrode AND and the cathode electrode CSD.

[0088] As an example, the protective film PAS can be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0089] FIG. 5 is a block diagram illustrating a display device according to an embodiment.

[0090] 5, a display device 10 according to an embodiment includes a display panel 100, a scan driver 110, a source driver 200, a timing controller 300, and a power supply 400.

[0091] The display area DA of the display panel 100 may include sub-pixels RP, GP, and BP that display an image, a scan write line GWL connected to the sub-pixels RP, GP, and BP, a scan initialization line GIL, a scan control line GCL, a sweep signal line SWPL, a PWM light emission line PWEL, a PAM light emission line PAEL, a PWM data line DL, a first PAM data line RDL, a second PAM data line GDL, and a third PAM data line BDL.

[0092] The scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep signal line SWPL, the PWM light emission line PWEL, and the PAM light emission line PAEL may extend in a first direction DR1 and be arranged in a second direction DR2 intersecting the first direction DR1. The PWM data line DL, the first PAM data line RDL, the second PAM data line GDL, and the third PAM data line BDL may extend in the second direction DR2 and be arranged in the first direction DR1. The first PAM data lines RDL may be electrically connected to each other, the second PAM data lines GDL may be electrically connected to each other, and the third PAM data lines BDL may be electrically connected to each other.

[0093] The sub-pixels RP, GP, and BP may include a first sub-pixel RP that emits a first light, a second sub-pixel GP that emits a second light, and a third sub-pixel BP that emits a third light. The first light refers to light in a red wavelength band, the second light refers to light in a green wavelength band, and the third light refers to light in a blue wavelength band. For example, the main peak wavelength of the first light may be located at approximately 600 nm to 750 nm, the main peak wavelength of the second light may be located at approximately 480 nm to 560 nm, and the main peak wavelength of the third light may be located at approximately 370 nm to 460 nm.

[0094] Each of the sub-pixels RP, GP, and BP may be connected to one of the scan write lines GWL, one of the scan initialization lines GIL, one of the scan control lines GCL, one of the sweep signal lines SWPL, one of the PWM light emission lines PWEL, and one of the PAM light emission lines PAEL. Each of the first sub-pixels RP may be connected to one of the PWM data lines DL and one of the first PAM data lines RDL. Each of the second sub-pixels GP may be connected to one of the PWM data lines DL and one of the second PAM data lines GDL. Each of the third sub-pixels BP may be connected to one of the PWM data lines DL and one of the third PAM data lines BDL.

[0095] A scan driver 110 for applying signals to the scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep signal line SWPL, the PWM light emission line PWEL, and the PAM light emission line PAEL may be disposed in the non-display area NDA of the display panel 100. Although FIG. 5 illustrates a case in which the scan driver 110 is disposed at one edge of the display panel 100 in the first direction DR1, the present invention is not limited thereto. The scan driver 110 may be disposed at both edges of the display panel 100 in the first direction DR1.

[0096] The scan driver 110 may include a first scan signal driver 111, a second scan signal driver 112, a sweep signal driver 113, and an emission signal driver 114.

[0097] The first scan signal driver 111 may receive a first scan drive control signal GDCS1 from the timing controller 300. The first scan signal driver 111 may output a scan initialization signal to the scan initialization line GIL and a scan write signal to the scan write line GWL in response to the first scan drive control signal GDCS1. That is, the first scan signal driver 111 may output two scan signals, i.e., a scan initialization signal and a scan write signal.

[0098] The second scan signal driver 112 may receive a second scan drive control signal GDCS2 from the timing control unit 300. The second scan signal driver 112 may output a scan control signal to the scan control line GCL in response to the second scan drive control signal GDCS2.

[0099] The sweep signal driving unit 113 may receive the first light emission control signal ECS1 and the sweep control signal SWCS from the timing control unit 300. The sweep signal driving unit 113 may output a PWM light emission signal to the PWM light emission wiring PWEL and a sweep signal to the sweep signal wiring SWPL in response to the first light emission control signal ECS1. That is, the sweep signal driving unit 113 may output both the PWM light emission signal and the sweep signal.

[0100] The light emission signal output unit 114 may receive an input of a second light emission control signal ECS2 from the timing control unit 300. The light emission signal output unit 114 may output a PAM light emission signal to the PAM light emission wiring PAEL in response to the second light emission control signal ECS2.

[0101] The timing controller 300 receives digital video data DATA and a timing signal TS. The timing controller 300 can generate a scan timing control signal STCS for controlling the operation timing of the scan driver 110 in response to the timing signal TS. The scan timing control signal STCS can generate a first scan drive control signal GDCS1, a second scan drive control signal GDSC2, a first light emission control signal ECS1, a second light emission control signal ECS2, and a sweep control signal SWCS. The timing controller 300 can also generate a source control signal DCS for controlling the operation timing of the source driver 200.

[0102] The timing controller 300 outputs a first scan drive control signal GDCS1, a second scan drive control signal GDSC2, a first light emission control signal ECS1, a second light emission control signal ECS2, and a sweep control signal SWCS to the scan driver 110. The timing controller 300 outputs digital video data DATA and a source control signal DCS to the source driver 200.

[0103] The source driver 200 converts the digital video data DATA into an analog PWM data voltage and outputs it to the PWM data line DL. Thus, the sub-pixels RP, GP, and BP are selected by the scan write signal of the scan driver 110, and the PWM data voltage can be supplied to the selected sub-pixels RP, GP, and BP.

[0104] The power supply unit 400 may output a first PAM data voltage to the first PAM data line RDL in common, a second PAM data voltage to the second PAM data line GDL in common, and a third PAM data voltage to the third PAM data line BDL in common. The power supply unit 400 may generate a plurality of power supply voltages and output them to the display panel 100.

[0105] The power supply unit 400 may output a first power supply voltage VDD1, a second power supply voltage VDD2, a third power supply voltage VSS, an initialization voltage VINT, a gate-on voltage VGL, and a gate-off voltage VGH to the display panel 100. The first power supply voltage VDD1 and the second power supply voltage VDD2 may be high potential driving voltages for driving the light emitting elements of the sub-pixels RP, GP, and BP. The initialization voltage VINT may be a low potential driving voltage for driving the light emitting elements of the sub-pixels RP, GP, and BP. The initialization voltage VINT and the gate-off voltage VGH may be applied to the sub-pixels RP, GP, and BP, respectively, and the gate-on voltage VGL and the gate-off voltage VGH may be applied to the scan driver 110.

[0106] Each of the source driver 200, the timing controller 300, and the power supply 400 may be formed as an integrated circuit, and the source driver 200 may be formed as a plurality of integrated circuits.

[0107] FIG. 6 is a circuit diagram illustrating a first sub-pixel according to an embodiment. 6, the first sub-pixel RP according to an embodiment may be connected to the kth (k is a positive integer) scan write line GWLk, the kth scan initialization line GILk, the kth scan control line GCLk, the kth sweep signal line SWPLk, the kth PWM light emission line PWELk, and the kth PAM light emission line PAELk. The first sub-pixel RP may also be connected to the jth PWM data line DLj and the first PAM data line RDL. The first sub-pixel RP may also be connected to a first power supply line VDL1 to which a first power supply voltage VDD1 is applied, a second power supply line VDL2 to which a second power supply voltage VDD2 is applied, a third power supply line VSL to which a third power supply voltage VSS is applied, an initialization voltage line VIL to which an initialization voltage VINT is applied, and a gate-off voltage line VGHL to which a gate-off voltage VGH is applied. For convenience of explanation, the j-th PWM data line DLj can be referred to as a first data line, and the first PAM data line RDL can be referred to as a second data line.

[0108] The first sub-pixel RP may include a light emitting element (EL), a first pixel driving unit PDU1, a second pixel driving unit PDU2, and a third pixel driving unit PDU3.

[0109] The first pixel driver PDU1, the second pixel driver PDU2, and the third pixel driver PDU3 are connected to each other, and the light emitting element EL emits light in response to the driving current Ids generated by the second pixel driver PDU2.

[0110] The light-emitting element EL may be disposed between the seventeenth transistor T17 and the third power wiring VSL. A first electrode of the light-emitting element EL may be coupled to a second electrode of the seventeenth transistor T17, and a second electrode of the light-emitting element EL may be coupled to the third power wiring VSL. The first electrode of the light-emitting element EL may be an anode electrode (i.e., a pixel electrode), and the second electrode may be a cathode electrode (i.e., a common electrode). The light-emitting element EL may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light-emitting element EL may be, but is not limited to, a micro light-emitting diode made of an inorganic semiconductor.

[0111] The first pixel driving unit PDU1 generates a control current Ic in response to the jth PWM data voltage of the jth PWM data line DLj to control the voltage of the third node N3 of the third pixel driving unit PDU3. Since the pulse width of the driving current Ids flowing to the light emitting element EL can be adjusted by the control current Ic of the first pixel driving unit PDU1, the first pixel driving unit PDU1 can be a pulse width modulation unit (PWM unit) that performs pulse width modulation of the driving current Ids flowing to the light emitting element EL.

[0112] The first pixel driving unit PDU1 may include first to seventh transistors T1 to T7 and a first capacitor PC1.

[0113] The first transistor T1 controls a control current Ic flowing between the second electrode and the first electrode in response to a PWM data voltage applied to the gate electrode.

[0114] The second transistor T2 is turned on by a k-th scan write signal of the k-th scan write line GWLk to supply a PWM data voltage of the j-th PWM data line DLj to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the k-th scan write line GWLk, a first electrode may be connected to the j-th PWM data line DLj, and a second electrode may be connected to the first electrode of the first transistor T1.

[0115] The third transistor T3 is turned on by the kth scan initialization signal of the kth scan initialization line GILk to connect the initialization voltage line VIL to the gate electrode of the first transistor T1. Thus, while the third transistor T3 is turned on, the gate electrode of the first transistor T1 can be discharged to the initialization voltage VINT of the initialization voltage line VIL. At this time, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In particular, since the voltage difference between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the third transistor T3, the third transistor T3 can be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the initialization voltage VINT can be stably applied to the gate electrode of the first transistor T1 regardless of the threshold voltage of the third transistor T3.

[0116] The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. This prevents the voltage of the gate electrode of the first transistor T1 from leaking through the third transistor T3. The gate electrode of the first sub-transistor T31 may be connected to the k-th scan initialization line GILk, the first electrode may be connected to the gate electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the second sub-transistor T32. The gate electrode of the second sub-transistor T32 may be connected to the k-th scan initialization line GILk, the first electrode may be connected to the second electrode of the first sub-transistor T31, and the second electrode may be connected to the initialization voltage line VIL.

[0117] The fourth transistor T4 is turned on by a k-th scan write signal of the k-th scan write line GWLk to connect the gate electrode and the second electrode of the first transistor T1, so that the first transistor T1 can operate as a diode while the fourth transistor T4 is turned on.

[0118] The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub transistor T41 and a fourth sub transistor T42. This prevents the voltage of the gate electrode of the first transistor T1 from leaking through the fourth transistor T4. The gate electrode of the third sub transistor T41 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the first transistor T1, and the second electrode may be connected to the first electrode of the fourth sub transistor T42. The gate electrode of the fourth sub transistor T42 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the third sub transistor T41, and the second electrode may be connected to the gate electrode of the first transistor T1.

[0119] The fifth transistor T5 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect a first electrode of the first transistor T1 to the first power supply wiring VDL1. A gate electrode of the fifth transistor T5 may be connected to the kth PWM light-emitting wiring PWELk, a first electrode may be connected to the first power supply wiring VDL1, and a second electrode may be connected to the first electrode of the first transistor T1.

[0120] The sixth transistor T6 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driving unit PDU3. The sixth transistor T6 has a gate electrode connected to the kth PWM light-emitting wiring PWELk, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the third node N3 of the third pixel driving unit PDU3.

[0121] The seventh transistor T7 may be turned on by a kth scan control signal of the kth scan control line GCLk to supply the gate-off voltage VGH of the gate-off voltage line VGHL to the first node N1 connected to the kth sweep signal line SWPLk. Thus, during a period in which the initialization voltage VINT is applied to the gate electrode of the first transistor T1 and during a period in which the PWM data voltage of the jth PWM data line DLj and the threshold voltage Vth1 of the first transistor T1 are programmed, the first capacitor PC1 may prevent a voltage change of the gate electrode of the first transistor T1 from being reflected in the kth sweep signal of the kth sweep signal line SWPLk. The gate electrode of the seventh transistor T7 may be connected to the kth scan control line GCLk, a first electrode may be connected to the gate-off voltage line VGHL, and a second electrode may be connected to the first node N1.

[0122] The first capacitor PC1 may be disposed between the gate electrode of the first transistor T1 and the first node N1, with one electrode of the first capacitor PC1 coupled to the gate electrode of the first transistor T1 and the other electrode coupled to the first node N1.

[0123] The first node N1 may be a junction of the k-th sweep signal wiring SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor PC1.

[0124] The second pixel driving unit PDU2 generates a driving current Ids to be applied to the light emitting element EL in response to a first PAM data voltage of the first PAM data line RDL. The second pixel driving unit PDU2 may be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. The second pixel driving unit PDU2 may be a constant current generating unit that generates a constant driving current Ids in response to the first PAM data voltage.

[0125] In addition, the second pixel driving unit PDU2 of each of the first sub-pixels RP may receive the same first PAM data voltage and generate the same driving current Ids regardless of the luminance of the first sub-pixel RP. Similarly, the second pixel driving unit PDU2 of each of the second sub-pixels GP may receive the same second PAM data voltage and generate the same driving current Ids regardless of the luminance of the second sub-pixel GP. The third pixel driving unit PDU3 of each of the third sub-pixels BP may receive the same third PAM data voltage and generate the same driving current Ids regardless of the luminance of the third sub-pixel BP.

[0126] The second pixel driving unit PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor PC2.

[0127] The eighth transistor T8 controls the driving current Ids flowing through the light-emitting element EL in response to the voltage applied to the gate electrode.

[0128] The ninth transistor T9 is turned on by a kth scan write signal of the kth scan write line GWLk to supply the first PAM data voltage of the first PAM data line RDL to the first electrode of the eighth transistor T8. The ninth transistor T9 may have a gate electrode connected to the kth scan write line GWLk, a first electrode connected to the first PAM data line RDL, and a second electrode connected to the first electrode of the eighth transistor T8.

[0129] The tenth transistor T10 is turned on by the kth scan initialization signal of the kth scan initialization line GILk to connect the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Thus, while the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 can be discharged to the initialization voltage VINT of the initialization voltage line VIL. At this time, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In particular, since the voltage difference between the gate-on voltage VGL and the initialization voltage VINT is greater than the threshold voltage of the tenth transistor T10, the tenth transistor T10 can be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the eighth transistor T8. Therefore, when the tenth transistor T10 is turned on, the initialization voltage VINT can be stably applied to the gate electrode of the eighth transistor T8 regardless of the threshold voltage of the tenth transistor T10.

[0130] The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. This prevents the voltage of the gate electrode of the eighth transistor T8 from leaking through the tenth transistor T10. The gate electrode of the fifth sub-transistor T101 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the gate electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the sixth sub-transistor T102. The gate electrode of the sixth sub-transistor T102 may be connected to the kth scan initialization line GILk, the first electrode may be connected to the second electrode of the fifth sub-transistor T101, and the second electrode may be connected to the initialization voltage line VIL.

[0131] The eleventh transistor T11 is turned on by the kth scan write signal of the kth scan write line GWLk to connect the gate electrode and the second electrode of the eighth transistor T8, so that the eighth transistor T8 can operate as a diode while the eleventh transistor T11 is turned on.

[0132] The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. This prevents the voltage of the gate electrode of the eighth transistor T8 from leaking through the eleventh transistor T11. The gate electrode of the seventh sub-transistor T111 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the eighth sub-transistor T112. The gate electrode of the eighth sub-transistor T112 may be connected to the k-th scan write line GWLk, the first electrode may be connected to the second electrode of the seventh sub-transistor T111, and the second electrode may be connected to the gate electrode of the eighth transistor T8.

[0133] The twelfth transistor T12 is turned on by a kth PWM light-emitting signal of the kth PWM light-emitting wiring PWELk to connect a first electrode of the eighth transistor T8 to the second power supply wiring VDL2. The gate electrode of the twelfth transistor T12 may be connected to the kth PWM light-emitting wiring PWELk, a first electrode may be connected to the first power supply wiring VDL1, and a second electrode may be connected to the first electrode of the eighth transistor T8.

[0134] The thirteenth transistor T13 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the first power line VDL1 to the second node N2. The thirteenth transistor T13 has a gate electrode connected to the kth scan control line GCLk, a first electrode connected to the first power line VDL1, and a second electrode connected to the second node N2.

[0135] The fourteenth transistor T14 is turned on by the kth PWM light-emitting signal of the kth PWM light-emitting wire PWELk to connect the second power supply wire VDL2 to the second node N2. Thus, when the fourteenth transistor T14 is turned on, the second power supply voltage VDD2 of the second power supply wire VDL2 can be supplied to the second node N2. The fourteenth transistor T14 has a gate electrode connected to the kth PWM light-emitting wire PWELk, a first electrode connected to the second power supply wire VDL2, and a second electrode connected to the second node N2.

[0136] The second capacitor PC2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor C2 may be coupled to the gate electrode of the eighth transistor T8, and the other electrode may be coupled to the second node N2.

[0137] The second node N2 may be a junction of the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the other electrode of the second capacitor C2.

[0138] The third pixel driving unit PDU3 adjusts the period during which the driving current Ids is applied to the light emitting element EL according to the voltage of the third node N3.

[0139] The third pixel driving unit PDU3 may include fifteenth to nineteenth transistors T15 to T19 and a third capacitor PC3.

[0140] The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. When the fifteenth transistor T15 is turned on, the driving current Ids of the eighth transistor T8 is supplied to the light-emitting element EL, and when the fifteenth transistor T15 is turned off, the driving current Ids of the eighth transistor T8 is not supplied to the light-emitting element EL. Therefore, the turn-on period of the fifteenth transistor T15 may be substantially the same as the light-emitting period of the light-emitting element EL. The gate electrode of the fifteenth transistor T15 may be connected to the third node N3, the first electrode may be connected to the second electrode of the eighth transistor T8, and the second electrode may be connected to the first electrode of the seventeenth transistor T17.

[0141] The sixteenth transistor T16 is turned on by the k-th scan control signal of the k-th scan control line GCLk to connect the initialization voltage line VIL to the third node N3, so that while the sixteenth transistor T16 is turned on, the third node N3 can be discharged to the initialization voltage of the initialization voltage line VIL.

[0142] The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162. This prevents the voltage of the third node N3 from leaking through the sixteenth transistor T16. The ninth sub-transistor T161 may have a gate electrode connected to the kth scan control line GCLk, a first electrode connected to the third node N3, and a second electrode connected to the first electrode of the tenth sub-transistor T162. The tenth sub-transistor T162 may have a gate electrode connected to the kth scan control line GCLk, a first electrode connected to the second electrode of the ninth sub-transistor T161, and a second electrode connected to the initialization voltage line VIL.

[0143] The seventeenth transistor T17 is turned on by a kth PAM light emitting signal of the kth PAM light emitting wiring PAELk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the light emitting element EL. The gate electrode of the seventeenth transistor T17 may be connected to the kth PAM light emitting wiring PAELk, the first electrode of the seventeenth transistor T17 may be connected to the second electrode of the fifteenth transistor T15, and the second electrode of the seventeenth transistor T17 may be connected to the first electrode of the light emitting element EL.

[0144] The 18th transistor T18 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the light emitting element EL. Thus, while the 18th transistor T18 is turned on, the first electrode of the light emitting element EL can be discharged to the initialization voltage of the initialization voltage line VIL. The gate electrode of the 18th transistor T18 may be connected to the kth scan control line GCLk, a first electrode may be connected to the first electrode of the light emitting element EL, and a second electrode may be connected to the initialization voltage line VIL.

[0145] The 19th transistor T19 is turned on by a test signal of the test signal line TSTL to connect a first electrode of the light emitting element EL to the third power line VSL. A gate electrode of the 19th transistor T19 may be connected to the test signal line TSTL, a first electrode of the 19th transistor T19 may be connected to the first electrode of the light emitting element EL, and a second electrode of the 19th transistor T19 may be connected to the third power line VSL.

[0146] The third capacitor PC3 may be disposed between the third node N3 and the initialization voltage line VIL. One electrode of the third capacitor PC3 may be coupled to the third node N3, and the other electrode may be coupled to the initialization voltage line VIL.

[0147] The third node N3 may be a junction of the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the ninth sub-transistor T161, and one electrode of the third capacitor C3.

[0148] One of the first electrode and the second electrode of each of the first through nineteenth transistors T1 to T19 may be a source electrode, and the other may be a drain electrode. The active layer of each of the first through nineteenth transistors T1 to T19 may be made of any one of polysilicon, amorphous silicon, and oxide semiconductor. When the active layer of each of the first through nineteenth transistors T1 to T19 is made of polysilicon, it may be formed by a low temperature polysilicon (LTPS) process.

[0149] 6, the first through nineteenth transistors T1 to T19 are mainly formed as P-type MOSFETs, but the embodiments of the present specification are not limited to this. For example, the first through nineteenth transistors T1 to T19 may be formed as N-type MOSFETs.

[0150] Alternatively, in order to block leakage current and improve the black display capability of the light emitting element EL, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 in the first sub-pixel RP may be formed as N-type MOSFETs. In this case, the gate electrodes of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, and the gate electrodes of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be connected to the kth control signal GNLk. The kth scan initialization signal GILk and the kth control signal GNLk may have pulses generated by the gate-off voltage VGH. In addition, the active layers of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 can be formed of an oxide semiconductor, and the remaining transistors can be formed of polysilicon.

[0151] Alternatively, one of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 can be formed as an N-type MOSFET, and the other can be formed as a P-type MOSFET. In this case, the transistor formed as an N-type MOSFET of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 can be formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET can be formed of polysilicon.

[0152] Alternatively, one of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 can be formed as an N-type MOSFET, and the other can be formed as a P-type MOSFET. In this case, the transistor formed as an N-type MOSFET of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 can be formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET can be formed of polysilicon.

[0153] Alternatively, one of the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 that are formed as N-type MOSFETs may be formed of an oxide semiconductor, and the transistor that are formed as P-type MOSFETs may be formed of polysilicon.

[0154] Alternatively, one of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 can be formed as an N-type MOSFET, and the other can be formed as a P-type MOSFET. In this case, the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 formed as an N-type MOSFET can be formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET can be formed of polysilicon.

[0155] In addition, the second sub-pixel GP and the third sub-pixel BP according to an embodiment may be substantially similar to the first sub-pixel RP described with reference to Fig. 6. Therefore, a description of the second sub-pixel GP and the third sub-pixel BP according to an embodiment will be omitted.

[0156] FIG. 7 is a graph showing the wavelength of light emitted by the light-emitting element of the first subpixel, the wavelength of light emitted by the light-emitting element of the second subpixel, and the wavelength of light emitted by the light-emitting element of the third subpixel depending on the driving current in one embodiment.

[0157] FIG. 7 is a graph showing the wavelength of light emitted by the light-emitting element of the first subpixel, the wavelength of light emitted by the light-emitting element of the second subpixel, and the wavelength of light emitted by the light-emitting element of the third subpixel depending on the driving current in one embodiment.

[0158] (a) of Figure 7 shows the wavelength of light emitted by the light-emitting element EL of the first subpixel RP depending on the driving current Ids applied to the light-emitting element EL of the first subpixel RP when the light-emitting element EL of the first subpixel RP contains an inorganic material, such as GaN.

[0159] (b) of Figure 7 shows the wavelength of light emitted by the light-emitting element EL of the second subpixel GP in response to the driving current Ids applied to the light-emitting element EL of the second subpixel GP when the light-emitting element EL of the second subpixel GP contains an inorganic material, such as GaN.

[0160] (c) of Figure 7 shows the wavelength of light emitted by the light-emitting element EL of the third subpixel BP in response to the driving current Ids applied to the light-emitting element EL of the third subpixel BP when the light-emitting element EL of the third subpixel BP contains an inorganic material, such as GaN.

[0161] In each of the graphs in (a), (b), and (c) of FIG. 7, the X-axis represents the drive current Ids, and the Y-axis represents the wavelength of light emitted by the light-emitting element.

[0162] 7, when the driving current Ids applied to the light emitting element EL of the first subpixel RP is 1 to 300 μA, the wavelength of the light emitted by the light emitting element EL of the first subpixel RP is constant at about 618 nm. As the driving current Ids applied to the light emitting element EL of the first subpixel RP goes from 300 μA to 1000 μA, the wavelength of the light emitted by the light emitting element EL of the first subpixel RP increases from about 618 nm to 620 nm.

[0163] As the driving current Ids applied to the light emitting element EL of the second subpixel GP goes from 1 μA to 1000 μA, the wavelength of the light emitted by the light emitting element EL of the second subpixel GP decreases from approximately 536 nm to 520 nm.

[0164] As the driving current Ids applied to the light emitting element EL of the third subpixel BP goes from 1 μA to 1000 μA, the wavelength of the light emitted by the light emitting element EL of the third subpixel BP decreases from about 464 nm to 461 nm.

[0165] In summary, the wavelength of the light emitted by the light emitting element EL of the first sub-pixel RP and the wavelength of the light emitted by the light emitting element EL of the third sub-pixel BP are almost the same even if the driving current Ids is changed. In contrast, the wavelength of the light emitted by the light emitting element EL of the second sub-pixel GP is inversely proportional to the driving current Ids. Therefore, when the driving current Ids applied to the light emitting element EL of the second sub-pixel GP is adjusted, the wavelength of the light emitted by the light emitting element EL of the second sub-pixel GP changes, and the color coordinates of the image displayed by the display panel 100 may change.

[0166] FIG. 8 is a graph illustrating the luminous efficiency of a light emitting element of a first sub-pixel, a light emitting element of a second sub-pixel, and a light emitting element of a third sub-pixel as a function of a driving current according to an embodiment.

[0167] FIG. 8(a) shows the luminous efficiency of the light-emitting element EL of the first sub-pixel RP according to the driving current Ids applied to the light-emitting element EL of the first sub-pixel RP when the light-emitting element EL of the first sub-pixel RP is made of an inorganic material.

[0168] FIG. 8(b) shows the luminous efficiency of the light-emitting element EL of the second subpixel GP as a function of the driving current Ids applied to the light-emitting element EL of the second subpixel GP when the light-emitting element EL of the second subpixel GP is made of an inorganic material.

[0169] (c) of Figure 8 shows the luminous efficiency of the light-emitting element EL of the third subpixel BP as a function of the driving current Ids applied to the light-emitting element EL of the third subpixel BP when the light-emitting element EL of the third subpixel BP is made of an inorganic material.

[0170] 8, when the driving current Ids flowing through the light-emitting element EL of the first subpixel RP is 10 μA, the luminous efficiency of the light-emitting element EL of the first subpixel RP is approximately 8.5 cd / A. When the driving current Ids flowing through the light-emitting element EL of the first subpixel RP is 50 μA, the luminous efficiency of the light-emitting element EL of the first subpixel RP is approximately 18 cd / A. In other words, when the driving current Ids flowing through the light-emitting element EL of the first subpixel RP is 50 μA, the luminous efficiency is approximately 2.1 times higher than when the driving current Ids is 10 μA.

[0171] When the driving current Ids passed through the light-emitting element EL of the second subpixel GP is 10 μA, the luminous efficiency of the light-emitting element EL of the second subpixel GP is approximately 72 cd / A. When the driving current Ids passed through the light-emitting element EL of the second subpixel GP is 50 μA, the luminous efficiency of the light-emitting element EL of the second subpixel GP is approximately 80 cd / A. In other words, when the driving current Ids passed through the light-emitting element EL of the second subpixel GP is 50 μA, the luminous efficiency is approximately 1.1 times higher than when it is 10 μA.

[0172] When the driving current Ids passed through the light-emitting element EL of the third subpixel BP is 10 μA, the luminous efficiency of the light-emitting element EL of the third subpixel BP is approximately 14 cd / A. When the driving current Ids passed through the light-emitting element EL of the third subpixel BP is 50 μA, the luminous efficiency of the light-emitting element EL of the third subpixel BP is approximately 13.2 cd / A. In other words, when the driving current Ids passed through the light-emitting element EL of the third subpixel BP is 50 μA, the luminous efficiency is approximately 1.06 times higher than when it is 10 μA.

[0173] In summary, the luminous efficiency of the light emitting element of the first sub-pixel RP, the luminous efficiency of the light emitting element of the second sub-pixel GP, and the luminous efficiency of the third sub-pixel BP may vary depending on the driving current Ids.

[0174] 7 and 8, when the driving current Ids applied to the light-emitting element EL of the second subpixel GP is adjusted, the color coordinates of the image displayed by the display panel 100 may change. In addition, the luminance efficiency of the light-emitting element of the first subpixel RP, the luminance efficiency of the light-emitting element of the second subpixel GP, and the luminance efficiency of the third subpixel BP may change according to the driving current Ids. Therefore, in order to maintain the color coordinates of the image displayed by the display panel 100 constant and to ensure that the light-emitting element EL of the first subpixel RP, the light-emitting element of the second subpixel GP, and the light-emitting element EL of the third subpixel BP have optimal luminance efficiencies, it is necessary to maintain the driving current Ids constant in each of the first subpixel RP, the second subpixel GP, and the third subpixel BP, and adjust the period during which the driving current Ids is applied to adjust the luminance of each of the first subpixel RP, the second subpixel GP, and the third subpixel BP.

[0175] 6, the second pixel driver PDU2 of the first subpixel RP generates a driving current Ids in response to the first PAM data voltage of the first PAM data line RDL so that the light emitting element EL of the first subpixel RP is driven with optimized light emitting efficiency. The first pixel driver PDU1 of the first subpixel RP generates a control current Ic in response to the PWM data voltage of the PWM data line to control the voltage of the third node N3 of the third pixel driver PDU3, and the third pixel driver PDU3 adjusts the period during which the driving current Ids is applied to the light emitting element EL in response to the voltage of the third node N3. Therefore, the first subpixel RP generates a constant driving current Ids in response to the optimized light emitting efficiency, and adjusts the duty ratio of the light emitting element EL, i.e., the period during which the driving current Ids is applied to the light emitting element EL, thereby adjusting the brightness of the light emitted by the light emitting element EL.

[0176] In addition, the second pixel driver PDU2 of the second subpixel GP generates a driving current Ids in response to the second PAM data voltage of the second PAM data line GDL so that the light emitting element EL of the second subpixel GP is driven with optimized light emitting efficiency. The first pixel driver PDU1 of the second subpixel GP generates a control current Ic in response to the PWM data voltage of the PWM data line to control the voltage of the third node N3 of the third pixel driver PDU3, and the third pixel driver PDU3 adjusts the period during which the driving current Ids is passed through the light emitting element EL in response to the voltage of the third node N3. Therefore, the second subpixel GP generates a constant driving current Ids in response to the optimized light emitting efficiency, and adjusts the duty ratio of the light emitting element EL, i.e., the period during which the driving current Ids is passed through the light emitting element EL, thereby adjusting the brightness of the light emitted by the light emitting element EL.

[0177] In addition, the second pixel driver PDU2 of the third subpixel BP generates a driving current Ids in response to the third PWM data voltage of the third PWM data line BDL so that the light emitting element EL of the third subpixel BP is driven with optimized light emitting efficiency. The first pixel driver PDU1 of the third subpixel BP generates a control current Ic in response to the PWM data voltage of the PWM data line to control the voltage of the third node N3 of the third pixel driver PDU3, and the third pixel driver PDU3 adjusts a period during which the driving current Ids is passed to the light emitting element EL in response to the voltage of the third node N3. Therefore, the third subpixel BP generates a constant driving current Ids in response to the optimized light emitting efficiency, and adjusts the duty ratio of the light emitting element EL, i.e., the period during which the driving current Ids is passed to the light emitting element EL, thereby adjusting the brightness of the light emitted by the light emitting element EL.

[0178] Therefore, it is possible to reduce or prevent degradation of image quality caused by changes in the wavelength of light emitted according to the driving current flowing through the light emitting element EL, and the light emitting element EL of the first sub-pixel RP, the light emitting element EL of the second sub-pixel GP, and the light emitting element EL of the third sub-pixel BP can each emit light with optimized luminous efficiency.

[0179] FIG. 9 is an exemplary diagram illustrating an operation of the display device during the Nth to N+2th frame periods.

[0180] 9, each of the Nth to N+2th frame periods may include an active period ACT and a blank period VB. The active period ACT may include a data address period ADDR for supplying a PWM data voltage and a first / second / third PWM data voltage to the first to third sub-pixels RP, GP, and BP, respectively, and a number of emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn) during which the light emitting element EL of each sub-pixel SP emits light. The blank period VB may be a period during which the sub-pixels RP, GP, and BP of the display panel 100 are inactive.

[0181] The address period ADDR and the first light emission period EP1 are shorter than the second through n-th light emission periods (EP2, EP3, EP4, EP5, ..., EPn). For example, the address period ADDR and the first light emission period EP1 may be approximately 5 horizontal periods, and each of the second through n-th light emission periods (EP2, EP3, EP4, EP5, ..., EPn) may be approximately 12 horizontal periods, but the embodiment of the present specification is not limited thereto. In addition, the active period ACT may include 25 light emission periods, but the number of light emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn) in the active period ACT is not limited thereto.

[0182] The sub-pixels RP, GP, and BP of the display panel 100 may sequentially receive the PWM data voltage and the first / second / third PWM data voltages for each row line during the address period ADDR. For example, the sub-pixels RP, GP, and BP arranged on the first row line to the sub-pixels RP, GP, and BP arranged on the n-th row line corresponding to the last row line may sequentially receive the PWM data voltage and the first / second / third PWM data voltages.

[0183] The sub-pixels RP, GP, and BP of the display panel 100 may emit light sequentially for each row in each of a plurality of emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn) of the display panel 100. For example, the sub-pixels RP, GP, and BP arranged in the first row may emit light sequentially to the sub-pixels RP, GP, and BP arranged in the last row.

[0184] The address period ADDR may overlap at least one of the emission periods (EP1, EP2, EP3, EP4, ..., EPn). For example, the address period ADDR may overlap the first to third emission periods EP1, EP2, EP3 as shown in Fig. 9. In this case, when the sub-pixels RP, GP, BP arranged on the pth row line (p is a positive integer) receive the PWM data voltage and the first / second / third PWM data voltages, the sub-pixels RP, GP, BP arranged on the qth row line (q is a positive integer less than p) may emit light.

[0185] Furthermore, each of the light emission periods (EP1, EP2, EP3, EP4, ..., EPn) may overlap with the adjacent light emission period. For example, the second light emission period EP2 may overlap with the first light emission period EP1 and the third light emission period EP3. In this case, the sub-pixels RP, GP, and BP arranged on the pth row line emit light in the second light emission period EP2, while the sub-pixels RP, GP, and BP arranged on the qth row line emit light in the first light emission period EP1.

[0186] FIG. 10 is a diagram illustrating still another example of the operation of the display device during the Nth to N+2th frame periods.

[0187] 10 differs from the embodiment of FIG. 9 in that the sub-pixels RP, GP, and BP of the display panel 100 emit light simultaneously in each of a plurality of light-emitting periods (EP1, EP2, EP3, EP4, EP5, . . . , EPn).

[0188] 10, the address period ADDR may not overlap with the multiple emission periods (EP1, EP2, EP3, EP4, ..., EPn). The first emission period EP1 may occur after the address period ADDR is completely finished.

[0189] The multiple light emission periods (EP1, EP2, EP3, EP4, ..., EPn) do not have to overlap with each other. In each of the multiple light emission periods (EP1, EP2, EP3, EP4, EP5, ..., EPn), the sub-pixels RP, GP, and BP arranged on all row lines can emit light simultaneously.

[0190] FIG. 11 is a waveform diagram showing a scan initialization signal, a scan write signal, a scan control signal, a PWM light emission signal, a PAM light emission signal, and a sweep signal applied to sub-pixels arranged on row lines k to k+5 during an Nth frame period according to one embodiment.

[0191] 11, the sub-pixels RP, GP, and BP arranged on the kth row line refer to the sub-pixels RP, GP, and BP connected to the kth scan initialization line GWLk, the kth scan write line GWLk, the kth scan control line GCLk, the kth PWM light emission line PWELk, the kth PAM light emission line PAELk, and the kth sweep signal line SWPLk. The kth scan initialization signal GIk refers to a signal applied to the kth scan initialization line GWLk, and the kth scan write signal GWk refers to a signal applied to the kth scan write line GWLk. The kth scan control signal GCk refers to a signal applied to the kth scan control line GCLk, and the kth PWM light emission signal PWEMk refers to a signal applied to the kth PWM light emission line PWELk. The kth PAM light emission signal PAEMk refers to a signal applied to the kth PAM light emission wiring PAELk, and the kth sweep signal SWPk refers to a signal applied to the kth sweep signal wiring SWPLk.

[0192] The scan initialization signals GIk to GIk+5, the scan write signals GWk to GWk+5, the scan control signals GCk to GCk+5, the PWM light emission signals PWEMk to PAEMk+5, the PAM light emission signals PAEMk to PAEMk+5, and the sweep signals SWPk to SWPk+5 may be sequentially shifted by one horizontal period 1H. The kth scan write signal GWk may be a signal obtained by shifting the kth scan initialization signal GIk by one horizontal period, and the k+1th scan write signal GWk+1 may be a signal obtained by shifting the k+1th scan initialization signal GIk+1 by one horizontal period. In this case, since the k+1th scan initialization signal GIk+1 is a signal obtained by shifting the kth scan initialization signal GIk by one horizontal period, the kth scan write signal GWk and the k+1th scan initialization signal GIk+1 may be substantially the same.

[0193] FIG. 12 is a waveform diagram showing the kth scan initialization signal, the kth scan write signal, the kth scan control signal, the kth PWM light-emitting signal, the kth PAM light-emitting signal, and the kth sweep signal applied to each of the sub-pixels arranged on the kth row line during the Nth frame period according to one embodiment, the voltage of the third node, and the period during which a driving current flows to the light-emitting element.

[0194] 12, the kth scan initialization signal GIk is a signal for controlling the turn-on and turn-off of the third and tenth transistors T3, T10 of the sub-pixels RP, GP, and BP, respectively. The kth scan write signal GWk is a signal for controlling the turn-on and turn-off of the second, fourth, ninth, and eleventh transistors T2, T4, T9, and T11 of the sub-pixels RP, GP, and BP, respectively. The kth scan control signal GCk is a signal for controlling the turn-on and turn-off of the seventh, thirteenth, sixteenth, and eighteenth transistors T7, T13, T16, and T18 of the sub-pixels RP, GP, and BP, respectively. The kth PWM light-emitting signal PWEMk is a signal for controlling the turn-on and turn-off of the fifth, sixth, twelfth, and fourteenth transistors T5, T6, T12, and T14. The kth PAM light-emitting signal PAEMk is a signal for controlling the turn-on and turn-off of the seventeenth transistor T17. The kth scan initialization signal, the kth scan write signal, the kth scan control signal, the kth PWM light emission signal, the kth PAM light emission signal, and the kth sweep signal may be generated at a cycle of one frame period.

[0195] The data address period ADDR includes first to fourth periods t1 to t4. The first period t1 and the fourth period t4 are first initialization periods for initializing the voltages of the first electrode of the light-emitting element EL and the third node N3. The second period t2 is a second initialization period for initializing the gate electrode of the first transistor T1 and the gate electrode of the eighth transistor T8. The third period t3 is a period for sampling the PWM data voltage Vdata of the jth PWM data line DLj and the threshold voltage Vth1 of the first transistor T1 at the gate electrode of the first transistor T1, and sampling the first PAM data voltage Rdata of the first PAM data line RDL and the threshold voltage Vth8 of the eighth transistor T8 at the gate electrode of the eighth transistor T8.

[0196] The first light emission period EP1 includes a fifth period t5 and a sixth period t6. The first light emission period EP1 is a period in which the turn-on period of the fifteenth transistor T15 is controlled in response to the control current Ic, and the driving current Ids is supplied to the light emitting element EL.

[0197] The second to n-th light emission periods EP2 to EPn each include seventh to ninth periods t7 to t9. The seventh period t7 is a third initialization period for initializing the third node N3, the eighth period t8 is substantially the same period as the fifth period t5, and the ninth period t9 is substantially the same period as the sixth period t6.

[0198] Adjacent light emission periods among the first through n-th light emission periods EP1 through EPn can be spaced apart by approximately several to several tens of horizontal periods.

[0199] The kth scan initialization signal GIk may have a gate-on voltage VGL during the second period t2 and a gate-off voltage VGH during the remaining period. That is, the kth scan initialization signal GIk may have a scan initialization pulse generated by the gate-on voltage VGL during the second period t2. The gate-off voltage VGH may be a voltage level higher than the gate-on voltage VGL.

[0200] The kth scan write signal GWk may have a gate-on voltage VGL during the third period t3 and a gate-off voltage VGH during the remaining period, i.e., the kth scan write signal GWk may have a scan write pulse generated by the gate-on voltage VGL during the third period t3.

[0201] The kth scan control signal GCk may have a gate-on voltage VGL during the first through fourth periods t1 to t4 and the seventh period t7, and may have a gate-off voltage VGH during the remaining periods. That is, the kth scan control signal GCk may have a scan control pulse generated by the gate-on voltage VGL during the first through fourth periods t1 to t4 and the seventh period t7.

[0202] The kth sweep signal SWPk may have a triangular waveform sweep pulse during the sixth period t6 and the ninth period t9, and may have a gate-off voltage VGH during the remaining periods. For example, the kth sweep signal SWPk may have a triangular waveform pulse that linearly decreases from the gate-off voltage VGH to the gate-on voltage Von during each of the sixth period t6 and the ninth period t9, and immediately increases from the gate-on voltage Von to the gate-off voltage Voff at the end of the sixth period t6 and the end of the ninth period t9.

[0203] The kth PWM light-emitting signal PWEMk may have the gate-on voltage VGL during the fifth and sixth periods t5, t6 and the eighth and ninth periods t8, t9, and may have the gate-off voltage VGH during the remaining periods, i.e., the kth PWM light-emitting signal PWEMk may include PWM pulses generated by the gate-on voltage VGL during the fifth and sixth periods t5, t6 and the eighth and ninth periods t8, t9.

[0204] The kth PAM light-emitting signal PAEMk may have a gate-on voltage VGL during the sixth period t6 and the ninth period t9, and may have a gate-off voltage VGH during the remaining periods. That is, the kth PAM light-emitting signal PAEMk may include a PAM pulse generated by the gate-on voltage VGL during the sixth period t6 and the ninth period t9. The PWM pulse width of the kth PWM light-emitting signal PWEMk may be greater than the sweep pulse width of the kth sweep signal SWPk.

[0205] 13 is a timing diagram illustrating the kth sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the fifteenth transistor during the fifth and sixth periods according to an embodiment. FIGs. 14 to 17 are circuit diagrams illustrating the operation of the first sub-pixel during the first, second, third, and sixth periods of FIG. 12.

[0206] Hereinafter, the operation of the first sub-pixel RP during the first to ninth periods t1 to t9 according to an embodiment will be described in detail with reference to FIGS.

[0207] First, as shown in FIG. 14, during a first period t1, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the kth scan control signal GCk of the gate-on voltage VGL.

[0208] When the seventh transistor T7 is turned on, the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, and when the thirteenth transistor T13 is turned on, the first power supply voltage VDD1 of the first power supply line VDL1 is applied to the second node N2.

[0209] When the sixteenth transistor T16 is turned on, the third node N3 is initialized to the initialization voltage VINT of the initialization voltage line VIL, and the fifteenth transistor T15 is turned on by the initialization voltage VINT of the third node N3. When the eighteenth transistor T18 is turned on, the first electrode of the light-emitting element EL is initialized to the initialization voltage VINT of the initialization voltage line VIL.

[0210] 15, during the second period t2, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the k-th scan control signal GCk of the gate-on voltage VGL, and during the second period t2, the third transistor T3 and the tenth transistor T10 are turned on by the k-th scan initialization signal GILk of the gate-on voltage VGL.

[0211] The seventh transistor T7, the thirteenth transistor T13, the fifteenth transistor T15, the sixteenth transistor T16, and the eighteenth transistor T18 are substantially similar to those described in the first period t1.

[0212] When the third transistor T3 is turned on, the gate electrode of the first transistor T1 is initialized to the initialization voltage VINT of the initialization voltage line VIL, and when the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 is initialized to the initialization voltage VINT of the initialization voltage line VIL.

[0213] At this time, the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, so that the voltage change amount of the gate electrode of the first transistor T1 is reflected to the kth sweep signal line SWPLk by the first pixel capacitor PC1, thereby preventing the gate-off voltage VGH of the kth sweep signal SWPk from fluctuating.

[0214] 16, during the third period t3, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the k-th scan control signal GCk of the gate-on voltage VGL, and during the third period t3, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the eleventh transistor T11 are turned on by the k-th scan write signal GWk of the gate-on voltage VGL.

[0215] The seventh transistor T7, the thirteenth transistor T13, the fifteenth transistor T15, the sixteenth transistor T16, and the eighteenth transistor T18 are substantially similar to those described in the first period t1.

[0216] When the second transistor T2 is turned on, the PWM data voltage Vdata of the jth PWM data line DLj is applied to the first electrode of the first transistor T1. When the fourth transistor T4 is turned on, the gate electrode and the second electrode of the first transistor T1 are connected to each other, so that the first transistor T1 operates as a diode.

[0217] At this time, since the voltage between the gate electrode and the first electrode of the first transistor T1 (Vgs=Vint-Vdata) is greater than the threshold voltage Vth1, the first transistor T1 is turned on and forms a current path until the voltage Vgs between the gate electrode and the first electrode reaches the threshold voltage Vth1. This allows the voltage of the gate electrode of the first transistor T1 to rise from "Vint" to "Vdata+Vth1". Since the first transistor T1 is formed as a P-type MOSFET, the threshold voltage Vth1 of the first transistor T1 may be less than 0V.

[0218] In addition, since the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, the first pixel capacitor PC1 can prevent the voltage change amount of the gate electrode of the first transistor T1 from being reflected on the kth sweep signal line SWPLk, thereby preventing the gate-off voltage VGH of the kth sweep signal SWPk from fluctuating.

[0219] When the ninth transistor T9 is turned on, the first PAM data voltage Rdata of the first PAM data line RDL is applied to the first electrode of the eighth transistor T8, and the gate electrode and the second electrode of the eighth transistor T8 are connected to each other, so that the eighth transistor T8 operates as a diode.

[0220] At this time, since the voltage between the gate electrode and the first electrode of the eighth transistor T8 (Vgs=Vint-Rdata) is greater than the threshold voltage Vth8, the eighth transistor T8 forms a current path until the voltage Vgs between the gate electrode and the first electrode reaches the threshold voltage Vth8. This allows the voltage of the gate electrode of the eighth transistor T8 to rise from "Vint" to "Rdata+Vth".

[0221] Fourth, during a fourth period t4, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the k-th scan control signal GCk of the gate-on voltage VGL.

[0222] The seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are substantially similar to those described in the first period t1.

[0223] Fifth, as shown in FIG. 17, during a fifth period t5, the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are turned on by the kth PWM light-emitting signal PWEMk of the gate-on voltage VGL.

[0224] When the fifth transistor T5 is turned on, the first power supply voltage VDD1 is applied to the first electrode of the first transistor T1, and when the sixth transistor T6 is turned on, the second electrode of the first transistor T1 is connected to the third node N3.

[0225] During the fifth period t5, the control current Ic that flows according to the voltage (Vdata+Vth1) of the gate electrode of the first transistor T1 does not depend on the threshold voltage Vth1 of the first transistor T1 as shown in Equation 1.

number

[0226] In Equation 1, k'' is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vth1 is a threshold voltage of the first transistor T1, VDD1 is a first power supply voltage, and Vdata is a PWM data voltage.

[0227] In addition, when the twelfth transistor T12 is turned on, the first electrode of the eighth transistor T8 may be coupled to the second power line VDL2.

[0228] Furthermore, when the fourteenth transistor T14 is turned on, the second power supply voltage VDD2 of the second power supply line VDL2 is applied to the second node N2. When the second power supply voltage VDD2 of the second power supply line VDL2 fluctuates due to a voltage drop or the like, the voltage difference ΔV2 between the first power supply voltage VDD1 and the second power supply voltage VDD2 may be reflected to the gate electrode of the eighth transistor T8 by the second pixel capacitor PC2.

[0229] When the fourteenth transistor T14 is turned on, a driving current Ids that flows according to the gate electrode voltage (Rdata+Vth8) of the eighth transistor T8 can be supplied to the fifteenth transistor T15. The driving current Ids does not depend on the threshold voltage Vth8 of the eighth transistor T8 as shown in Equation 2.

[0230]

number

[0231] In Equation 2, k' is a proportionality coefficient determined by the structure and physical characteristics of the eighth transistor T8, Vth8 is the threshold voltage of the eighth transistor T8, VDD2 is the second power supply voltage, and Rdata is the first PAM data voltage.

[0232] Sixth, as shown in FIG. 17, during a sixth period t6, the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are turned on by the kth PWM light-emitting signal PWEMk of the gate-on voltage VGL.

[0233] During the sixth period t6, the seventeenth transistor T17 is turned on by the k-th PAM light-emitting signal PAEMk of the gate-on voltage VGL. During the sixth period t6, the k-th sweep signal SWPk linearly decreases from the gate-off voltage VGH to the gate-on voltage Von.

[0234] The fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are substantially similar to those described in the fifth period t5.

[0235] When the seventeenth transistor T17 is turned on, the first electrode of the light-emitting element EL may be coupled to the second electrode of the fifteenth transistor T15.

[0236] During the sixth period t6, the kth sweep signal SWPk linearly decreases from the gate-off voltage VGH to the gate-on voltage Von, and the voltage change amount ΔV1 of the kth sweep signal SWPk is reflected to the gate electrode of the first transistor T1 by the first pixel capacitor PC1, so that the voltage of the gate electrode of the first transistor T1 can be Vdata+Vth1-ΔV1. That is, during the sixth period t6, as the voltage of the kth sweep signal SWPk decreases, the voltage of the gate electrode of the first transistor T1 linearly decreases.

[0237] The period during which the control current Ic is applied to the third node N3 may vary depending on the magnitude of the PWM data voltage Vdata applied to the first transistor T1. As a result, the voltage of the third node N3 varies depending on the magnitude of the PWM data voltage Vdata applied to the first transistor T1, so that the turn-on period of the fifteenth transistor T15 can be controlled. Therefore, by controlling the turn-on period of the fifteenth transistor T15, the period SEP during which the driving current Ids is applied to the light emitting element EL during the sixth period t6 can be controlled.

[0238] Also, as shown in FIG. 13, when the PWM data voltage Vdata of the gate electrode of the first transistor T1 is a gray-level PWM data voltage, the voltage VG_T1 of the gate electrode of the first transistor T1 may have a level higher than the first power supply voltage during the first sub-period t61 and a level lower than the first power supply voltage during the second sub-period t62 as the voltage of the k-th sweep signal SWPk decreases. Therefore, the first transistor T1 may be turned on during the second sub-period t62 of the sixth period t6. In this case, the control current Ic of the first transistor T1 flows to the third node N3 during the second sub-period t62, so that the voltage of the third node N3 may have a high level VH during the second sub-period t62. Therefore, the fifteenth transistor T15 may be turned off during the second sub-period t62. Therefore, the driving current Ids is applied to the light-emitting element EL during the first sub-period t61 and is not applied to the light-emitting element EL during the second sub-period t62. That is, the light-emitting element EL can emit light during the first sub-period t61, which is a part of the sixth period t6. The closer the first sub-pixel RP is to the peak black gradation, the shorter the light-emitting period SET of the light-emitting element EL is. Conversely, the closer the first sub-pixel RP is to the peak white gradation, the longer the light-emitting period SET of the light-emitting element EL is.

[0239] Also, as shown in FIG. 13, when the PWM data voltage Vdata of the gate electrode of the first transistor T1 is the PWM data voltage of the peak white gradation, the voltage VG_T1 of the gate electrode of the first transistor T1 is higher than the first power supply voltage VDD1 during the sixth period t6, even though the voltage of the k-th sweep signal SWPk is reduced. As a result, the first transistor T1 can be turned off throughout the sixth period t6. In this case, the control current Ic of the first transistor T1 does not flow to the third node N3 throughout the sixth period t6, so that the voltage of the third node N3 can maintain the initialization voltage VINT. Therefore, the fifteenth transistor T15 can be turned on throughout the sixth period t6. Therefore, the driving current Ids is applied to the light-emitting element EL throughout the sixth period t6, and the light-emitting element EL can emit light throughout the sixth period t6.

[0240] Furthermore, as the kth sweep signal SWPk rises from the gate-on voltage VGL to the gate-off voltage VGH at the end of the sixth period t6, the voltage VG_T1 of the gate electrode of the first transistor T1 can rise to be substantially the same as that of the fifth period t5 at the end of the sixth period t6.

[0241] As described above, the light emitting period of the light emitting element EL can be adjusted by adjusting the PWM data voltage applied to the gate electrode of the first transistor T1. Therefore, by adjusting the magnitude of the driving current Ids flowing through the light emitting element EL, the gray scale to be expressed by the first sub-pixel RP can be adjusted by adjusting the period during which the driving current Ids flows through the light emitting element EL while keeping the driving current Ids flowing through the light emitting element EL constant.

[0242] If the digital video data converted into the PWM data voltage is 8 bits, the digital video data of the peak black gradation may be 0, and the digital video data of the peak white gradation may be 255. Also, the digital video data of the black gradation area may be 0 to 63, the digital video data of the gray gradation area may be 64 to 191, and the digital video data of the white gradation area may be 192 to 255.

[0243] Moreover, the seventh period t7, the eighth period t8, and the ninth period t9 of each of the second to n-th light emission periods EP2 to EPn are substantially the same as the first period t1, the fifth period t5, and the sixth period t6 described above. That is, in each of the second to n-th light emission periods EP2 to EPn, after the third node N3 is initialized, the period during which the driving current Ids generated according to the first PAM data voltage Rdata written to the gate electrode of the eighth transistor T8 flows to the light-emitting element EL based on the PWM data voltage Vdata written to the gate electrode of the first transistor T1 during the address period ADDR can be adjusted.

[0244] Furthermore, since the test signal on the test signal line TSTL is applied at the gate-off voltage VGH during the active period ACT of the Nth frame period, the nineteenth transistor T19 can be turned off during the active period ACT of the Nth frame period.

[0245] Meanwhile, the second subpixel GP and the third subpixel BP can operate substantially identically to the first subpixel RP, as described with reference to Figures 9 to 17, and therefore, the description of the operation of the second subpixel GP and the third subpixel BP will be omitted.

[0246] Figure 18 is a layout diagram showing an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of a first sub-pixel according to an embodiment. Figure 19 is an enlarged layout diagram showing a detail of region I of Figure 18. Figure 20 is an enlarged layout diagram showing a detail of region II of Figure 18. Figure 21 is an enlarged layout diagram showing a detail of region III of Figure 18.

[0247] 18 to 21, the initialization voltage wiring VIL, the kth scan initialization wiring GILk, the kth scan write wiring GWLk, the kth PWM light emission wiring PWELk, the first horizontal power supply wiring VDL1, the gate-off voltage wiring VGHL, the kth sweep signal wiring SWPLk, the kth scan control wiring GCLk, the kth PAM light emission wiring PAELk, the test signal wiring TSTL, and the third auxiliary power supply wiring AVSL may extend in the first direction DR1. The initialization voltage wiring VIL, the kth scan initialization wiring GILk, the kth scan write wiring GWLk, the kth PWM light emission wiring PWELk, the first horizontal power supply wiring VDL1, the gate-off voltage wiring VGHL, the kth sweep signal wiring SWPLk, the kth scan control wiring GCLk, the kth PAM light emission wiring PAELk, the test signal wiring TSTL, and the third auxiliary power supply wiring AVSL may be arranged apart in the second direction DR2.

[0248] The j-th data line DLj, the first vertical power line VVDL, and the first PAM data line RDL may extend in the second direction DR2. The second PAM data line GDL and the third PAM data line BDL shown in Fig. 5 may extend in the second direction DR2. The j-th data line DLj, the first vertical power line VVDL, the first PAM data line RDL, the second PAM data line GDL, and the third PAM data line BDL may be arranged apart in the first direction DR1.

[0249] The first sub-pixel RP includes first to nineteenth transistors T1 to T19, first to sixth capacitor electrodes CE1 to CE6, first to fifth gate connecting electrodes GCE1 to GCE5, first and second data connecting electrodes DCE1, DCE2, first to eighth connecting electrodes CCE1 to CCE8, a first anode connecting electrode ANDE1, and a light emitting element EL.

[0250] The first transistor T1 includes a first channel CH1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first channel CH1 may extend in a first direction DR1. The first channel CH1 may overlap the first gate electrode G1 in a third direction DR3. The first gate electrode G1 may be connected to the first connecting electrode CCE1 through a first contact hole CT1. The first gate electrode G1 may be integrally formed with the first capacitor electrode CE1. The first gate electrode G1 may overlap the second capacitor electrode CE2 in the third direction DR3. The first source electrode S1 may be disposed on one side of the first channel CH1, and the first drain electrode D1 may be disposed on the other side of the first channel CH1. The first source electrode S1 may be connected to the second drain electrode D2 and the fifth drain electrode D5. The first drain electrode D1 may be connected to the third sub-source electrode S41 and the sixth source electrode S6. The first source electrode S1 and the first drain electrode D1 do not have to overlap the first gate electrode G1 in the third direction DR3. The first source electrode S1 and the first drain electrode D1 may overlap the second capacitor electrode CE2 in the third direction DR3.

[0251] The second transistor T2 includes a second channel CH2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second channel CH2 may overlap the second gate electrode G2 in the third direction DR3. The second gate electrode G2 may be formed integrally with the first gate connecting electrode GCE1. The second source electrode S2 may be disposed on one side of the second channel CH2, and the second drain electrode D2 may be disposed on the other side of the second channel CH2. The second source electrode S2 may be connected to the first data connecting electrode DCE1 through the first data contact hole DCT1. The second drain electrode D2 may be connected to the first source electrode S1. The second source electrode S2 and the second drain electrode D2 may not overlap the second gate electrode G2 in the third direction DR3. The second drain electrode D2 may extend in the second direction DR2. The second drain electrode D2 may be connected to the first source electrode S1.

[0252] The first sub-transistor T31 of the third transistor T3 includes a first sub-channel CH31, a first sub-gate electrode G31, a first sub-source electrode S31, and a first sub-drain electrode D31. The first sub-channel CH31 may overlap the first sub-gate electrode G31 in the third direction DR3. The first sub-gate electrode G31 may be formed integrally with the second gate connecting electrode GCE2. The first sub-source electrode S31 may be disposed on one side of the first sub-channel CH31, and the first sub-drain electrode D31 may be disposed on the other side of the first sub-channel CH31. The first sub-source electrode S31 may be connected to the fourth sub-drain electrode D42, and the first sub-drain electrode D31 may be connected to the second sub-source electrode S32. The first sub-source electrode S31 and the first sub-drain electrode D31 may not overlap the first sub-gate electrode G31. The first sub-source electrode S31 may overlap the k-th scan write line GWLk in the third direction DR3. The first sub-drain electrode D31 may overlap the initialization voltage line VIL in the third direction DR3.

[0253] The second sub-transistor T32 of the third transistor T3 includes a second sub-channel CH32, a second sub-gate electrode G32, a second sub-source electrode S32, and a second sub-drain electrode D32. The second sub-channel CH32 may overlap the second sub-gate electrode G32 in the third direction DR3. The second sub-gate electrode G32 may be formed integrally with the second gate connecting electrode GCE2. The second sub-source electrode S32 may be disposed on one side of the second sub-channel CH32, and the second sub-drain electrode D32 may be disposed on the other side of the second sub-channel CH32. The second sub-source electrode S32 may be connected to the first sub-drain electrode D31, and the second sub-drain electrode D32 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The second sub-source electrode S32 and the second sub-drain electrode D32 may not overlap the second sub-gate electrode G32. The second sub-source electrode S32 and the second sub-drain electrode D32 may overlap the initialization voltage line VIL in the third direction DR3.

[0254] The third sub-transistor T41 of the fourth transistor T4 includes a third sub-channel CH41, a third sub-gate electrode G41, a third sub-source electrode S41, and a third sub-drain electrode D41. The third sub-channel CH41 may overlap the third sub-gate electrode G41 in the third direction DR3. The third sub-gate electrode G41 may be formed integrally with the first gate connecting electrode GCE1. The third sub-source electrode S41 may be disposed on one side of the third sub-channel CH41, and the third sub-drain electrode D41 may be disposed on the other side of the third sub-channel CH41. The third sub-source electrode S41 may be connected to the first drain electrode D1, and the third sub-drain electrode D41 may be connected to the fourth sub-source electrode S42. The third sub-source electrode S41 and the third sub-drain electrode D41 may not overlap the third sub-gate electrode G41.

[0255] The fourth sub-transistor T42 of the fourth transistor T4 includes a fourth sub-channel CH42, a fourth sub-gate electrode G42, a fourth sub-source electrode S42, and a fourth sub-drain electrode D42. The fourth sub-channel CH42 may overlap the fourth sub-gate electrode G42 in the third direction DR3. The fourth sub-gate electrode G42 may be formed integrally with the second gate connecting electrode GCE2. The fourth sub-source electrode S42 may be disposed on one side of the fourth sub-channel CH42, and the fourth sub-drain electrode D42 may be disposed on the other side of the fourth sub-channel CH42. The fourth sub-source electrode S42 may be connected to the third sub-drain electrode D41, and the fourth sub-drain electrode D42 may be connected to the first sub-source electrode S31. The fourth sub-source electrode S42 and the fourth sub-drain electrode D42 may not overlap the fourth sub-gate electrode G42.

[0256] The fifth transistor T5 includes a fifth channel CH5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth channel CH5 may overlap the fifth gate electrode G5 in the third direction DR3. The fifth gate electrode G5 may be formed integrally with the third gate connecting electrode GCE3. The fifth source electrode S5 may be disposed on one side of the fifth channel CH5, and the fifth drain electrode D5 may be disposed on the other side of the fifth channel CH5. The fifth source electrode S5 may be connected to the first horizontal power supply wiring HVDL through the second power supply contact hole VCT2. The fifth drain electrode D5 may be connected to the first source electrode S1. The fifth source electrode S5 and the fifth drain electrode D5 may not overlap the fifth gate electrode G5 in the third direction DR3. The fifth drain electrode D5 may overlap the extension portion EX of the second capacitor electrode CE2 in the third direction DR3.

[0257] The sixth transistor T6 includes a sixth channel CH6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth channel CH6 may overlap the sixth gate electrode G6 in the third direction DR3. The sixth gate electrode G6 may be formed integrally with the third gate connecting electrode GCE3. The sixth source electrode S6 may be disposed on one side of the sixth channel CH6, and the sixth drain electrode D6 may be disposed on the other side of the sixth channel CH6. The sixth source electrode S6 may be connected to the first drain electrode D1. The sixth drain electrode D6 may be connected to the fourth connecting electrode CCE4 through a tenth contact hole CT10. The sixth source electrode S6 and the sixth drain electrode D6 may not overlap the sixth gate electrode G6 in the third direction DR3. The sixth drain electrode D6 may overlap the second connecting electrode CCE2 and the first horizontal power line HVDL in the third direction DR3.

[0258] The seventh transistor T7 includes a seventh channel CH7, a seventh gate electrode G7, a seventh source electrode S7, and a seventh drain electrode D7. The seventh channel CH7 may overlap the seventh gate electrode G7 in the third direction DR3. The seventh gate electrode G7 may be integrally formed with the third gate connecting electrode GCE3. The seventh gate electrode G7 may overlap the initialization voltage wiring VIL in the third direction DR3. The seventh source electrode S7 may be disposed on one side of the seventh channel CH7, and the seventh drain electrode D7 may be disposed on the other side of the seventh channel CH7. The seventh source electrode S7 may be connected to the gate-off voltage wiring VGHL via a seventh contact hole CT7. The seventh drain electrode D7 may be connected to the k-th sweep signal wiring SWPLk via a sixth contact hole CT6. The seventh source electrode S7 and the seventh drain electrode D7 may not overlap the seventh gate electrode G7 in the third direction DR3.

[0259] The eighth transistor T8 includes an eighth channel CH8, an eighth gate electrode G8, an eighth source electrode S8, and an eighth drain electrode D8. The eighth channel CH8 may overlap with the eighth gate electrode G8 in the third direction DR3. The eighth gate electrode G8 may extend in the second direction DR2. The eighth gate electrode G8 may be formed integrally with the third capacitor electrode CE3. The eighth source electrode S8 may be disposed on one side of the eighth channel CH8, and the eighth drain electrode D8 may be disposed on the other side of the eighth channel CH8. The eighth source electrode S8 may be connected to the ninth drain electrode D9 and the twelfth drain electrode D12. The eighth drain electrode D8 may be connected to the seventh sub-source electrode S111. The eighth source electrode S8 and the eighth drain electrode D8 may not overlap with the eighth gate electrode G8 in the third direction DR3.

[0260] The ninth transistor T9 includes a ninth channel CH9, a ninth gate electrode G9, a ninth source electrode S9, and a ninth drain electrode D9. The ninth channel CH9 may overlap the ninth gate electrode G9 in the third direction DR3. The ninth gate electrode G9 may extend in the second direction DR2. The ninth gate electrode G9 may be formed integrally with the first gate connecting electrode GCE1. The ninth source electrode S9 may be disposed on one side of the ninth channel CH9, and the ninth drain electrode D9 may be disposed on the other side of the ninth channel CH9. The ninth source electrode S9 may be connected to the second data connecting electrode DCE2 via the third data contact hole DCT3. The ninth drain electrode D9 may be connected to the eighth source electrode S8. The ninth source electrode S9 and the ninth drain electrode D9 may not overlap the ninth gate electrode G9 in the third direction DR3.

[0261] The fifth sub-transistor T101 of the tenth transistor T10 includes a fifth sub-channel CH101, a fifth sub-gate electrode G101, a fifth sub-source electrode S101, and a fifth sub-drain electrode D101. The fifth sub-channel CH101 may overlap the fifth sub-gate electrode G101 in the third direction DR3. The fifth sub-gate electrode G101 may be formed integrally with the second gate connecting electrode GCE2. The fifth sub-source electrode S101 may be disposed on one side of the fifth sub-channel CH101, and the fifth sub-drain electrode D101 may be disposed on the other side of the fifth sub-channel CH101. The fifth sub-source electrode S101 may be connected to the eighth sub-drain electrode D112, and the fifth sub-drain electrode D101 may be connected to the sixth sub-source electrode S102. The fifth sub-source electrode S101 and the fifth sub-drain electrode D101 may not overlap the fifth sub-gate electrode G101. The fifth sub-source electrode S101 may overlap the k-th scan write line GWLk in the third direction DR3. The fifth sub-drain electrode D101 may overlap the initialization voltage line VIL in the third direction DR3.

[0262] The sixth sub-transistor T102 of the tenth transistor T10 includes a sixth sub-channel CH102, a sixth sub-gate electrode G102, a sixth sub-source electrode S102, and a sixth sub-drain electrode D102. The sixth sub-channel CH102 may overlap with the sixth sub-gate electrode G102 in the third direction DR3. The sixth sub-gate electrode G102 may be formed integrally with the second gate connecting electrode GCE2. The sixth sub-source electrode S102 may be disposed on one side of the sixth sub-channel CH102, and the sixth sub-drain electrode D102 may be disposed on the other side of the sixth sub-channel CH102. The sixth sub-source electrode S102 may be connected to the fifth sub-drain electrode D101, and the sixth sub-drain electrode D102 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may not overlap with the sixth sub-gate electrode G102. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may overlap the initialization voltage line VIL in the third direction DR3.

[0263] The seventh sub-transistor T111 of the eleventh transistor T11 includes a seventh sub-channel CH111, a seventh sub-gate electrode G111, a seventh sub-source electrode S111, and a seventh sub-drain electrode D111. The seventh sub-channel CH111 may overlap the seventh sub-gate electrode G111 in the third direction DR3. The seventh sub-gate electrode G111 may be formed integrally with the first gate connecting electrode GCE1. The seventh sub-source electrode S111 may be disposed on one side of the seventh sub-channel CH111, and the seventh sub-drain electrode D111 may be disposed on the other side of the seventh sub-channel CH111. The seventh sub-source electrode S111 may be connected to the eighth drain electrode D8, and the seventh sub-drain electrode D111 may be connected to the eighth sub-source electrode S112. The seventh sub-source electrode S111 and the seventh sub-drain electrode D111 may not overlap the seventh sub-gate electrode G111.

[0264] The eighth sub-transistor T112 of the eleventh transistor T11 includes an eighth sub-channel CH112, an eighth sub-gate electrode G112, an eighth sub-source electrode S112, and an eighth sub-drain electrode D112. The eighth sub-channel CH112 may overlap with the eighth sub-gate electrode G112 in the third direction DR3. The eighth sub-gate electrode G112 may be formed integrally with the second gate connecting electrode GCE2. The eighth sub-source electrode S112 may be disposed on one side of the eighth sub-channel CH112, and the eighth sub-drain electrode D112 may be disposed on the other side of the eighth sub-channel CH112. The eighth sub-source electrode S112 may be connected to the seventh sub-drain electrode D111, and the eighth sub-drain electrode D112 may be connected to the fifth sub-source electrode S101. The eighth sub-source electrode S112 and the eighth sub-drain electrode D112 may not overlap with the eighth sub-gate electrode G112.

[0265] The twelfth transistor T12 includes a twelfth channel CH12, a twelfth gate electrode G12, a twelfth source electrode S12, and a twelfth drain electrode D12. The twelfth channel CH12 may overlap the twelfth gate electrode G12 in the third direction DR3. The twelfth gate electrode G12 may be formed integrally with the third gate connecting electrode GCE3. The twelfth source electrode S12 may be disposed on one side of the twelfth channel CH12, and the twelfth drain electrode D12 may be disposed on the other side of the twelfth channel CH12. The twelfth source electrode S12 may be connected to the fifth connecting electrode CCE5 via an eleventh contact hole CT11. The twelfth source electrode S12 and the twelfth drain electrode D12 may not overlap the twelfth gate electrode G12 in the third direction DR3.

[0266] The thirteenth transistor T13 includes a thirteenth channel CH13, a thirteenth gate electrode G13, a thirteenth source electrode S13, and a thirteenth drain electrode D13. The thirteenth channel CH13 may overlap the thirteenth gate electrode G13 in the third direction DR3. The thirteenth gate electrode G13 may be formed integrally with the third gate connecting electrode GCE3. The thirteenth source electrode S13 may be disposed on one side of the thirteenth channel CH13, and the thirteenth drain electrode D13 may be disposed on the other side of the thirteenth channel CH13. The thirteenth source electrode S13 may be connected to the first horizontal power supply wiring HVDL through the second power supply contact hole VCT2. The thirteenth drain electrode D13 may be connected to the second connecting electrode CCE2 through the third contact hole CT3. The thirteenth source electrode S13 and the thirteenth drain electrode D13 may not overlap the thirteenth gate electrode G13 in the third direction DR3.

[0267] The fourteenth transistor T14 includes a fourteenth channel CH14, a fourteenth gate electrode G14, a fourteenth source electrode S14, and a fourteenth drain electrode D14. The fourteenth channel CH14 may overlap the fourteenth gate electrode G14 in the third direction DR3. The fourteenth gate electrode G14 may be formed integrally with the third gate connecting electrode GCE3. The fourteenth source electrode S14 may be disposed on one side of the fourteenth channel CH14, and the fourteenth drain electrode D14 may be disposed on the other side of the fourteenth channel CH14. The fourteenth source electrode S14 may be connected to the fifth connecting electrode CCE5 via an eleventh contact hole CT11. The fourteenth drain electrode D14 may be connected to the second connecting electrode CCE2 via a fourth contact hole CT4. The fourteenth source electrode S14 and the fourteenth drain electrode D14 may not overlap the fourteenth gate electrode G14 in the third direction DR3.

[0268] The fifteenth transistor T15 includes a fifteenth channel CH15, a fifteenth gate electrode G15, a fifteenth source electrode S15, and a fifteenth drain electrode D15. The fifteenth channel CH15 may overlap the fifteenth gate electrode G15 in the third direction DR3. The fifteenth gate electrode G15 may be formed integrally with the fifth capacitor electrode CE5. The fifteenth source electrode S15 may be disposed on one side of the fifteenth channel CH15, and the fifteenth drain electrode D15 may be disposed on the other side of the fifteenth channel CH15. The fifteenth source electrode S15 may be connected to the ninth drain electrode D9. The fifteenth drain electrode D15 may be connected to the seventeenth source electrode S17. The fifteenth source electrode S15 and the fifteenth drain electrode D15 may not overlap the fifteenth gate electrode G15 in the third direction DR3.

[0269] The ninth sub-transistor T161 of the sixteenth transistor T16 includes a ninth sub-channel CH161, a ninth sub-gate electrode G161, a ninth sub-source electrode S161, and a ninth sub-drain electrode D161. The ninth sub-channel CH161 may overlap the ninth sub-gate electrode G161 in the third direction DR3. The ninth sub-gate electrode G161 may be formed integrally with the third gate connecting electrode GCE3. The ninth sub-source electrode S161 may be disposed on one side of the ninth sub-channel CH161, and the ninth sub-drain electrode D161 may be disposed on the other side of the ninth sub-channel CH161. The ninth sub-source electrode S161 may be connected to the fourth connecting electrode CCE4 through a tenth contact hole CT10, and the ninth sub-drain electrode D161 may be connected to the tenth sub-source electrode S162. The ninth sub-source electrode S161 and the ninth sub-drain electrode D161 may not overlap the ninth sub-gate electrode G161.

[0270] The tenth sub-transistor T162 of the sixteenth transistor T16 includes a tenth sub-channel CH162, a tenth sub-gate electrode G162, a tenth sub-source electrode S162, and a tenth sub-drain electrode D162. The tenth sub-channel CH162 may overlap with the tenth sub-gate electrode G162 in the third direction DR3. The tenth sub-gate electrode G162 may be formed integrally with the third gate connecting electrode GCE3. The tenth sub-source electrode S162 may be disposed on one side of the tenth sub-channel CH162, and the tenth sub-drain electrode D162 may be disposed on the other side of the tenth sub-channel CH162. The tenth sub-source electrode S162 may be connected to the ninth sub-drain electrode D161, and the tenth sub-drain electrode D162 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. The tenth sub-source electrode S162 and the tenth sub-drain electrode D162 may not overlap the tenth sub-gate electrode G162.

[0271] The 17th transistor T17 includes a 17th channel CH17, a 17th gate electrode G17, a 17th source electrode S17, and a 17th drain electrode D17. The 17th channel CH17 may overlap the 17th gate electrode G17 in the third direction DR3. The 17th gate electrode G17 may be formed integrally with the fifth gate connecting electrode GCE5. The 17th source electrode S17 may be disposed on one side of the 17th channel CH17, and the 17th drain electrode D17 may be disposed on the other side of the 17th channel CH17. The 17th source electrode S17 may be connected to the 15th drain electrode D15. The 17th drain electrode D17 may be connected to the seventh connecting electrode CCE7 via the 16th contact hole CT16. The 17th source electrode S17 and the 17th drain electrode D17 may not overlap the 17th gate electrode G17 in the third direction DR3.

[0272] The 18th transistor T18 includes an 18th channel CH18, an 18th gate electrode G18, an 18th source electrode S18, and an 18th drain electrode D18. The 18th channel CH18 may overlap with the 18th gate electrode G18 in the third direction DR3. The 18th gate electrode G18 may be formed integrally with the third gate connecting electrode GCE3. The 18th source electrode S18 may be disposed on one side of the 18th channel CH18, and the 18th drain electrode D18 may be disposed on the other side of the 18th channel CH18. The 18th source electrode S18 may be connected to the initialization voltage line VIL via a ninth contact hole CT9. The 18th drain electrode D18 may be connected to the seventh connecting electrode CCE7 via a sixteenth contact hole CT16. The 18th source electrode S18 and the 18th drain electrode D18 may not overlap with the 18th gate electrode G18 in the third direction DR3.

[0273] The 19th transistor T19 includes a 19th channel CH19, a 19th gate electrode G19, a 19th source electrode S19, and a 19th drain electrode D19. The 19th channel CH19 may overlap the 19th gate electrode G19 in the third direction DR3. The 19th gate electrode G19 may be connected to the test signal wiring TSTL via a 23rd contact hole CT23. The 19th source electrode S19 may be disposed on one side of the 19th channel CH19, and the 19th drain electrode D19 may be disposed on the other side of the 19th channel CH19. The 19th source electrode S19 may be connected to the eighth connecting electrode CCE8 via a 21st contact hole CT21. The 19th drain electrode D19 may be connected to the third auxiliary power wiring AVSL via a 24th contact hole CT24. The 19th source electrode S19 and the 19th drain electrode D19 may not overlap the 19th gate electrode G19 in the third direction DR3.

[0274] The first capacitor electrode CE1 may be formed integrally with the first gate electrode G1. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3. The first capacitor electrode CE1 may be one electrode of the first capacitor C1, and the second capacitor electrode CE2 may be the other electrode of the first capacitor C1.

[0275] The second capacitor electrode CE2 includes a hole exposing the first gate electrode G1, and the first connecting electrode CCE1 may be connected to the first gate electrode G1 through the first contact hole CT1.

[0276] The second capacitor electrode CE2 may include an extension EX extending in the second direction DR2. The extension EX of the second capacitor electrode CE2 may intersect with the k-th PWM light emitting wiring PWELk and the first horizontal power supply wiring HVDL. The extension EX of the second capacitor CE2 may be coupled to the k-th sweep signal wiring SWPLk through a fifth contact hole CT5.

[0277] The third capacitor electrode CE3 may be formed integrally with the eighth gate electrode G8. The fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3. The third capacitor electrode CE3 may be one electrode of the second capacitor C2, and the fourth capacitor electrode CE4 may be the other electrode of the second capacitor C2.

[0278] The fourth capacitor electrode CE4 includes a hole exposing the eighth gate electrode G8, and the sixth connecting electrode CCE6 may be connected to the eighth gate electrode G8 through a twelfth contact hole CT12 in the hole.

[0279] The fifth capacitor electrode CE5 may be integrally formed with the fourth gate connecting electrode GCE4 and the fifteenth gate electrode G15. The sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. The fifth capacitor electrode CE5 may be one electrode of the third capacitor C3, and the sixth capacitor electrode CE6 may be the other electrode of the third capacitor C3. The sixth capacitor electrode CE6 may be connected to the initialization voltage line VIL via an eighteenth contact hole CT18.

[0280] The first gate connecting electrode GCE1 may be connected to the k-th scan write line GWLk through the first gate contact hole GCT1 and the third gate contact hole GCT3. The second gate connecting electrode GCE2 may be connected to the k-th scan initialization line GILk through the second gate contact hole GCT2. The third gate connecting electrode GCE3 may be connected to the k-th PWM light emission line PWELk through the fourteenth contact hole CT14. The fourth gate connecting electrode GCE4 may be connected to the k-th scan control line GCLk through the eighth contact hole CT8. The fourth gate connecting electrode GCE4 may be connected to the fourth connecting electrode CCE4 through the seventeenth contact hole CT17. The fifth gate connecting electrode GCE5 may be connected to the k-th PAM light emission line PAELk through the nineteenth contact hole CT19.

[0281] The first data connecting electrode DCE1 may be connected to the second source electrode S2 through the first data contact hole DCT1 and to the j-th data line DLj through the second data contact hole DCT2. The second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through the third data contact hole DCT3 and to the first PAM data line RDL through the fourth data contact hole DCT4.

[0282] The first connecting electrode CCE1 may extend in a second direction DR2, may be connected to the first gate electrode G1 through a first contact hole CT1, and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 through a second contact hole CT2.

[0283] The second connecting electrode CCE2 may extend in the first direction DR1 and may be connected to the twelfth drain electrode D12 through a third contact hole CT3, to the fourteenth drain electrode D14 through a fourth contact hole CT4, and to the fourth capacitor electrode CE4 through a fifteenth contact hole CT15.

[0284] The fourth connecting electrode CCE4 may extend in the first direction DR1, may be connected to the sixth drain electrode D6 and the ninth sub-source electrode S161 through a tenth contact hole CT10, and may be connected to the fourth gate connecting electrode GCE4 through a seventeenth contact hole CT17.

[0285] The fifth connecting electrode CCE5 may extend in the first direction DR1, may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11, and may be connected to the fourth capacitor electrode CE4 through a fourth power contact hole VCT4.

[0286] The sixth connecting electrode CCE6 may extend in the second direction DR2, may be connected to the third capacitor electrode CE3 through a twelfth contact hole CT12, and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 through a thirteenth contact hole CT13.

[0287] The seventh connecting electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16. The seventh connecting electrode CCE7 may be connected to the first anode connecting electrode ANDE1 through a twentieth contact hole CT20.

[0288] The eighth connecting electrode CCE8 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 and may be connected to the first anode connecting electrode ANDE1 through a twenty-second contact hole CT22.

[0289] The first anode connecting electrode ANDE1 may extend in the second direction DR2 and may be connected to the seventh connecting electrode CCE7 through a twentieth contact hole CT20 and to the eighth connecting electrode CCE8 through a twenty-second contact hole CT22.

[0290] The second power connecting electrode VDCE may extend in a second direction DR2 and may be connected to the fifth connecting electrode CCE5 through a fourth power contact hole VCT4.

[0291] Fig. 22 is a layout diagram showing an example of a fifth conductive layer of the first subpixel shown in Fig. 18. Fig. 23 is a layout diagram showing an example of a sixth conductive layer of the first subpixel shown in Fig. 18. Fig. 24 is a layout diagram showing an example of a seventh conductive layer of the first subpixel shown in Fig. 18.

[0292] Referring to FIG. 22, a fifth conductive layer disposed on an organic film covering the fourth conductive layer may include a third power supply line VSL.

[0293] The third power supply wiring VSL can correspond to the entirety of the display area DA except for a part where the light emitting elements LE of each of the plurality of sub-pixels RP, GP, and BP are arranged.

[0294] In addition, the fifth conductive layer may further include a second anode connecting electrode ANDE2 overlapping the first anode connecting electrode ANDE1.

[0295] Referring to FIG. 23, a sixth conductive layer disposed on another organic film covering the fifth conductive layer may include an anode electrode AND corresponding to each of the plurality of sub-pixels RP, GP, and BP, a cathode electrode CSD corresponding to each of the plurality of sub-pixels RP, GP, and BP, and a cathode wiring CSL connected to the cathode electrode CSD.

[0296] That is, the display panel 100 according to one embodiment may include a plurality of anode electrodes AND corresponding to each of the plurality of sub-pixels RP, GP, and BP, a plurality of cathode electrodes CSD corresponding to each of the plurality of sub-pixels RP, GP, and BP and disposed apart from each of the plurality of anode electrodes AND, and a cathode wiring CSL connected to the plurality of cathode electrodes CSD.

[0297] Here, the cathode wiring CSL may be connected to a third power supply wiring VSL to which a third power supply voltage (VSS in FIG. 5) is applied. For example, the cathode wiring CSL may be disposed in the non-display area NDA and connected to the third power supply wiring VSL via a contact hole (not shown) penetrating an organic film under the sixth conductive layer. However, this is merely an example, and the cathode wiring CSL may include an arrangement and connection for satisfying a condition for applying the third power supply voltage VSS.

[0298] For example, the cathode line CSL may be disposed over the entire display area DA except for the anode electrode AND and the cathode electrode CSD disposed in a portion of each of the sub-pixels RP, GP, and BP. In each of the sub-pixels RP, GP, and BP, the cathode electrode CSD is formed of a portion of the cathode line CSL protruding in the second direction DR2 so as to be arranged alongside the anode electrode AND in the first direction DR1.

[0299] The anode electrode AND is disposed apart from the cathode wiring CSL and the cathode electrode CSD.

[0300] Moreover, in the first direction DR1, the cathode electrode CSD can be disposed away from the cathode wiring CSL.

[0301] Referring to FIG. 24, the seventh conductive layer disposed on at least a portion of the sixth conductive layer may include a plurality of anode pads ANDP covering each of the multiple anode electrodes AND, a plurality of cathode pads CSDP covering each of the multiple cathode electrodes CSD, and a cathode wiring pad CSLP covering at least a portion of the cathode wiring.

[0302] The anode pads ANDP have a width larger than that of the anode electrodes AND, and thus can cover the upper and side surfaces of the anode electrodes AND.

[0303] The multiple cathode pads CSDP have a width larger than that of the multiple cathode electrodes CSD, and can cover the upper and side surfaces of the multiple cathode electrodes CSD.

[0304] The cathode wiring pad CSLP can cover the edges of the cathode wiring CSL that face the multiple anode electrodes AND and the multiple cathode electrodes CSD, respectively. That is, the cathode wiring pad CSLP can cover the upper and side portions of the edges of the cathode wiring CSL.

[0305] In each of the sub-pixels RP, GP, and BP, the cathode wiring pad CSLP is disposed away from the anode pad ANDP, thereby making it possible to prevent a short circuit between the anode electrode AND and the cathode wiring CSL via the cathode wiring pad CSLP.

[0306] In each of the sub-pixels RP, GP, and BP, the cathode wiring pad CSLP corresponds to the boundaries between the anode electrode AND and the cathode electrode CSD, and the cathode wiring CSL, respectively. That is, the cathode wiring pad CSLP covers the edge of the cathode wiring CSL, which corresponds to the boundaries between the anode electrode AND and the cathode electrode CSD, and the cathode wiring CSL, respectively.

[0307] As a result, in each of the sub-pixels RP, GP, and BP, the cathode wiring pad CSLP can form a closed loop shape together with at least a part of the edge of the cathode pad CSDP.

[0308] That is, the inner edge of the cathode wiring pad CSLP corresponding to the boundaries between the anode electrode AND and the cathode electrode CSD and the cathode wiring CSL can be connected to a part of the edge of the cathode pad CSDP to form a closed loop shape.

[0309] FIG. 25 is a cross-sectional view showing an example of a display panel cut along B-B' in FIG. 18. FIG. 26 is a cross-sectional view showing an example of a display panel cut along C-C' in FIG. 18. FIG. 27 is a cross-sectional view showing an example of a display panel cut along D-D' in FIG. 18. FIG. 28 is a cross-sectional view showing an example of a display panel cut along E-E' in FIG. 18. FIG. 29 is a cross-sectional view showing an example of a display panel cut along F-F' in FIG. 18. FIG. 30 is a cross-sectional view showing an example of a display panel cut along G-G' in FIG. 18. FIG. 31 is a cross-sectional view showing an example of a display panel cut along H-H' in FIG. 18. FIG. 32 is a cross-sectional view showing an example of a display panel cut along I-I' in FIG. 18. FIG. 33 is a cross-sectional view showing an example of a display panel cut along J-J' in FIG. 18. FIGS. 34 and 35 are cross-sectional views showing examples of display panels cut along K-K' in FIGS. 18, 22, and 24.

[0310] 25 to 35, a buffer film BF may be disposed on a substrate SUB.

[0311] The substrate SUB is made of an insulating material such as polymer resin or glass.

[0312] For example, the substrate SUB is made of a polymer resin such as polyimide. The substrate SUB may be a flexible substrate that is capable of bending, folding, rolling, and the like.

[0313] The buffer film BF is an insulating film for protecting the transistors in the thin film transistor layer TFTL and the light emitting elements LE in the light emitting element layer EML from moisture that penetrates through the substrate SUB, which is susceptible to moisture permeation.

[0314] The buffer film BF is made of a plurality of inorganic films stacked alternately. For example, the buffer film BF may be formed as a multi-layer structure in which one or more inorganic films selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked alternately.

[0315] An active layer may be disposed on the buffer film BF. The active layer includes first to nineteenth channels CH1 to CH19, first to nineteenth source electrodes S1 to S19, and first to nineteenth drain electrodes D1 to D19 of the first to nineteenth transistors T1 to T19.

[0316] The active layer may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0317] The first to nineteenth channels CH1 to CH19 may overlap the first to nineteenth gate electrodes G1 to G19, respectively, in the third direction DR3. The first to nineteenth source electrodes S1 to S19 and the first to nineteenth drain electrodes D1 to D19 may not overlap the first to nineteenth gate electrodes G1 to G19 in the third direction DR3. The first to nineteenth source electrodes S1 to S19 and the first to nineteenth drain electrodes D1 to D19 may be regions having conductivity formed by doping ions or impurities into a silicon semiconductor or an oxide semiconductor.

[0318] A gate insulating film 130 may be disposed on the active layer. The gate insulating film 130 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The gate insulating film 130 may be referred to as a first insulating film.

[0319] A first conductive layer may be disposed on the gate insulating film 130. The first conductive layer includes first to nineteenth gate electrodes G1 to G19, a first capacitor electrode CE1, a third capacitor electrode CE3, a fifth capacitor electrode CE5, and first to fifth gate connecting electrodes GCE1 to GCE5 of the first to nineteenth transistors T1 to T19. The first to nineteenth gate electrodes G1 to G19, the first capacitor electrode CE1, the third capacitor electrode CE3, the fifth capacitor electrode CE5, and the first to fifth gate connecting electrodes GCE1 to GCE5 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0320] A first interlayer insulating film 141 may be disposed on the first conductive layer. The first interlayer insulating film 141 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may be referred to as a second insulating film.

[0321] A second conductive layer may be disposed on the first interlayer insulating film 141. The second conductive layer may include a second capacitor electrode CE2, a fourth capacitor electrode CE4, and a sixth capacitor electrode CE6. The second conductive layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0322] The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3, the fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3, and the sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. Since the first interlayer insulating film 141 has a predetermined dielectric constant, the first capacitor C1 may be formed by the first capacitor electrode CE1, the second capacitor electrode CE2, and the first interlayer insulating film 141 disposed therebetween. Also, the second capacitor C2 may be formed by the third capacitor electrode CE3, the fourth capacitor electrode CE4, and the first interlayer insulating film 141 disposed therebetween. The third capacitor C3 may be formed by the fifth capacitor electrode CE5, the sixth capacitor electrode CE6, and the first interlayer insulating film 141 disposed therebetween.

[0323] A second interlayer insulating film 142 may be disposed on the second conductive layer. The second interlayer insulating film 142 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may be referred to as a third insulating film.

[0324] A third conductive layer may be disposed on the second interlayer insulating film 142. The third conductive layer may further include an initialization voltage wiring VIL, a k-th scan initialization wiring GILk, a k-th scan write wiring GWLk, a k-th PWM light emission wiring PWELk, a first horizontal power supply wiring HVDL, a gate-off voltage wiring VGHL, a k-th sweep signal wiring SWPLk, a k-th scan control wiring GCLk, a k-th PAM light emission wiring PAELk, a test signal wiring TSTL, and a third auxiliary power supply wiring AVSL.

[0325] In addition, the third conductive layer may include first and second data connecting electrodes DCE1 and DCE2 and first to eighth connecting electrodes CCE1 to CCE8.

[0326] The third conductive layer may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0327] The kth scan write line GWLk may be connected to the first gate connecting electrode GCE1 through a first gate contact hole GCT1 and a third gate contact hole GCT3 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The kth scan initialization line GILk may be connected to the second gate connecting electrode GCE2 through a second gate contact hole GCT2 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The kth PWM light emission line PWELk may be connected to the third gate connecting electrode GCE3 through a fourteenth contact hole CT14 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The kth scan control line GCLk may be connected to the fourth gate connecting electrode GCE4 through an eighth contact hole CT8 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The k-th PAM light emitting wiring PAELk may be connected to the fifth gate connecting electrode GCE5 through a nineteenth contact hole CT19 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0328] The initialization voltage line VIL may be connected to the second sub-drain electrode D32 and the sixth sub-drain electrode D102 through a first power contact hole VCT1 that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The initialization voltage line VIL may be connected to the tenth sub-drain electrode D162 and the eighteenth drain electrode D18 through a ninth contact hole CT9 that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The initialization voltage line VIL may be connected to the sixth capacitor electrode CE6 through an eighteenth contact hole CT18 that penetrates the second interlayer insulating film 142. The first horizontal power line HVDL may be connected to the fifth source electrode S5 and the thirteenth source electrode S13 through a second power contact hole VCT2 that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The gate-off voltage line VGHL may be connected to the seventh source electrode S7 through a seventh contact hole CT7 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The test signal line TSTL may be connected to the nineteenth gate electrode G19 through a twenty-third contact hole CT23 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The third power line VSL may be connected to the nineteenth drain electrode D19 through a twenty-fourth contact hole CT24 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0329] The first data connecting electrode DCE1 may be connected to the second source electrode S2 through a first data contact hole DCT1 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The second data connecting electrode DCE2 may be connected to the ninth source electrode S9 through a third data contact hole DCT3 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0330] The first connecting electrode CCE1 may be connected to the first gate electrode G1 via a first contact hole CT1 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142, and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 via a second contact hole CT2 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0331] The second connecting electrode CCE2 may be connected to the seventeenth drain electrode D17 via a third contact hole CT3 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142, connected to the fourteenth drain electrode D14 via a fourth contact hole CT4 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142, and connected to the fourth capacitor electrode CE4 via a fifteenth contact hole CT15 penetrating the second interlayer insulating film 142.

[0332] The fourth connecting electrode CCE4 may be connected to the sixth drain electrode D6 via a tenth contact hole CT10 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142, and may be connected to the fourth gate connecting electrode GCE4 via a seventeenth contact hole CT17 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0333] The fifth connecting electrode CCE5 may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0334] The sixth connecting electrode CCE6 may be connected to the eighth gate electrode G8 via a twelfth contact hole CT12 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142, and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 via a thirteenth contact hole CT13 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0335] The seventh connecting electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0336] The eighth connecting electrode CCE8 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0337] A first planarization film 160 may be disposed on the third conductive layer. The first planarization film 160 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first planarization film 160 may be referred to as a fourth insulating film.

[0338] A fourth conductive layer may be disposed on the first planarization film 160. The fourth conductive layer may include the jth data line DLj, the first vertical power line VVDL, and the first PAM data line RDL. The fourth conductive layer may also include a first anode connecting electrode ANDE1 and a second power connecting electrode VDCE. The fourth conductive layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0339] The jth data line DLj may be connected to the first data connecting electrode DCE1 through a second data contact hole DCT2 penetrating the first planarization film 160. The first PAM data line RDL may be connected to the second data connecting electrode DCE2 through a fourth data contact hole DCT4 penetrating the first planarization film 160. The first vertical power line VVDL may be connected to the first horizontal power line HVDL through a third power contact hole VCT3 penetrating the first planarization film 160. The third power contact hole VCT3 may overlap with the second power contact hole VCT2 in the third direction DR3. The area of ​​the third power contact hole VCT3 may be larger than the area of ​​the second power contact hole VCT2.

[0340] The first anode connecting electrode ANDE1 may be connected to the seventh connecting electrode CCE7 through a twentieth contact hole CT20 penetrating the first planarization film 160, and may be connected to the eighth connecting electrode CCE8 through a twenty-second contact hole CT22 penetrating the first planarization film 160. The second power connecting electrode VDCE may be connected to the fifth connecting electrode CCE5 through a fourth power contact hole VCT4 penetrating the first planarization film 160.

[0341] A second planarization film 170 may be disposed on the fourth conductive layer. The second planarization film 170 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The second planarization film 170 may be referred to as a fifth insulating film.

[0342] A fifth conductive layer may be disposed on the second planarization film 170. The fifth conductive layer may include a third power wiring VSL. The third power wiring VSL may be connected to the second power connecting electrode VDCE via a fifth power contact hole VCT5 penetrating the second planarization film 170. The fifth conductive layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0343] A third planarization film 180 may be disposed on the fifth conductive layer. The third planarization film 180 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The third planarization film 180 may be referred to as a fifth insulating film.

[0344] 34, a sixth conductive layer may be disposed on the third planarization film 180. The sixth conductive layer includes an anode electrode AND, a cathode electrode CSD, and a cathode wiring CSL.

[0345] Although not shown, the sixth conductive layer may further include a second sub-power supply wiring and a third sub-power supply wiring.

[0346] The sixth conductive layer may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. As an example, the sixth conductive layer may include a metal material with high reflectivity, such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a laminated structure of an APC alloy and ITO (ITO / APC / ITO). As another example, the sixth conductive layer may be formed of a double layer structure of Al / Ti.

[0347] The anode electrodes AND correspond to the plurality of sub-pixels RP, GP, and BP, respectively.

[0348] The cathode electrodes CSD correspond to the plurality of sub-pixels RP, GP, and BP, respectively, and are disposed apart from the anode electrodes AND.

[0349] The cathode line CSL is connected to the cathode electrodes CSD of the sub-pixels RP, GP, and BP.

[0350] A seventh conductive layer may be disposed over at least a portion of the sixth conductive layer.

[0351] The seventh conductive layer may include an anode pad ANDP covering the anode electrode AND, a cathode pad CSDP covering the cathode electrode CSD, and a cathode wiring pad CSLP covering at least a portion of the cathode wiring CSL.

[0352] The seventh conductive layer is made of a transparent conductive material (TCO) such as ITO or IZO.

[0353] In each of the sub-pixels RP, GP, and BP, the anode pad ANDP is disposed on the anode electrode AND and covers the upper surface and side surfaces of the anode electrode AND. At this time, the anode pad ANDP is disposed to completely cover the side surfaces of the anode electrode AND, so that the edge of the anode pad ANDP may contact the third planarization film 180 disposed under the anode electrode AND.

[0354] Similarly, in each of the sub-pixels RP, GP, and BP, the cathode pad CSDP is disposed on the cathode electrode CSD and covers the upper surface and side surface of the cathode electrode CSD. At this time, the cathode pad CSDP is disposed so as to completely cover the side surface of the cathode electrode CSD, so that the edge of the cathode pad CSDP can contact the third planarization film 180 disposed under the cathode electrode CSD.

[0355] The cathode wiring pad CSLP may cover edges of the cathode wiring CSL that face the anode electrode AND and the cathode electrode CSD, respectively.

[0356] The cathode wiring pad CSLP is disposed on the edge of the cathode wiring CSL and covers the upper and side surfaces of the edge of the cathode wiring CSL. At this time, the cathode wiring pad CSLP is disposed so as to completely cover the side surfaces of the edge of the cathode wiring CSL, so that the edge of the cathode wiring pad CSLP can come into contact with the third planarization film 180 disposed below the cathode wiring CSL.

[0357] In this way, the seventh conductive layer can prevent damage to the edges of the anode electrode AND, the cathode electrode CSD, and the cathode wiring CSL caused by a patterning process or the like for the inorganic material disposed on the seventh conductive layer.

[0358] A protective layer PAS may be disposed on the seventh conductive layer, and may be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0359] The protective film PAS may leave exposed a central portion of the upper surface of the anode pad ANDP and a central portion of the upper surface of the cathode pad CSDP without covering them.

[0360] That is, the protective film PAS covers the edge of the anode pad ANDP and the edge of the cathode pad CSDP, and can cover the cathode wiring CSL and the cathode wiring pad CSLP.

[0361] As shown in FIG. 35, the light emitting element LE can be disposed on the anode pad ANDP and the cathode pad CSDP that are not covered by the protective film PAS.

[0362] The anode pad ANDP may be connected to the first contact electrode CTE1 of the light emitting element LE via the anode contact electrode ANDC.

[0363] The cathode pad CSDP may be connected to the second contact electrode CTE2 of the light emitting element LE via a cathode contact electrode CSDC.

[0364] The anode contact electrode ANDC and the cathode contact electrode CSDC are made of a conductive adhesive material.

[0365] The light emitting element LE has been described above with reference to FIG. 4, so a duplicated description will be omitted.

[0366] Thus, according to one embodiment, the upper and side edges of the anode electrode AND, cathode electrode CSD, and cathode electrode wiring CSL made of the sixth conductive layer are completely covered by the anode pad ANDP, cathode pad CSDP, and cathode wiring pad CSLP made of the seventh conductive layer, and are not exposed to the patterning process. This prevents the sixth conductive layer from being undercut by exposure to the patterning process, and therefore prevents the protective film PAS from being peeled off by the undercut structure of the sixth conductive layer.

[0367] Specifically, if the sixth conductive layer includes a first layer of aluminum (Al), which is relatively susceptible to the patterning process, and a second layer of titanium (Ti) covering the first layer, exposure to the patterning process may result in an undercut structure between the first and second layers.

[0368] Due to such an undercut structure between the first and second layers, when the protective film PAS that covers the seventh conductive layer is disposed, a defect is likely to occur in which the side surface of the first layer is not completely covered with the protective film PAS.

[0369] In particular, if an alignment error of the light-emitting element LE occurs during the process of positioning the light-emitting element LE when the cathode wiring CSL is not covered with the protective film PAS, a short circuit defect may occur as the first contact electrode CTE1 of the light-emitting element LE comes into contact with the exposed cathode wiring CSL that is not covered with the protective film PAS.

[0370] However, according to one embodiment, the upper and side surfaces of the edges of the anode electrode AND, the cathode electrode CSD, and the cathode electrode wiring CSL are completely covered by the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP. Therefore, during the patterning process of the seventh conductive layer for arranging the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP, the side surfaces of the edges of the anode electrode AND, the cathode electrode CSD, and the cathode electrode wiring CSL are not exposed to the patterning process, so that it is possible to prevent the undercut structure from being deformed.

[0371] Therefore, since it is possible to prevent the protective film PAS from being separated due to the undercut structure, the cathode wiring CSL can be completely covered with the protective film PAS, thereby making it possible to prevent a short circuit defect in the light emitting element LE.

[0372] On the other hand, Figures 34 and 35 show an example in which the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP extend until they contact the third planarization film 180 on the edges of the anode electrode AND, the cathode electrode CSD, and the cathode wiring CSL, thereby completely covering the side surfaces of the anode electrode AND, the side surfaces of the cathode electrode CSD, and the side surfaces of the edges of the cathode wiring CSL.

[0373] However, this is merely an example, and the sides of the anode electrode AND, the sides of the cathode electrode CSD, and the sides of the edges of the cathode wiring CSL may be covered by the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP, and the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP may be deformed to the extent that the cathode wiring pad CSLP is separated from the anode pad ANDP.

[0374] FIG. 36 is a cross-sectional view showing another example of a display panel taken along the line K-K' in FIGS.

[0375] 36, each of the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP may extend onto the third planarization film 180.

[0376] That is, the anode pad ANDP may further include a portion disposed on the third planarization film 180 in addition to a portion covering the upper surface of the anode electrode AND and a portion covering the side surface of the anode electrode AND.

[0377] Similarly, the cathode pad CSDP may further include a portion disposed on the third planarization film 180, in addition to a portion covering the upper surface of the cathode electrode CSD and a portion covering the side surface of the cathode electrode CSD.

[0378] Moreover, the cathode wiring pad CSLP may further include a portion disposed on the third planarization film 180, in addition to a portion covering the upper surface of the edge of the cathode wiring CSL and a portion covering the side surface of the edge of the cathode wiring CSL.

[0379] In this way, by attaching the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP to the third planarization film 180, the side surfaces of the anode electrode AND, the side surfaces of the cathode electrode CSD, and the side surfaces of the edges of the cathode wiring CSL can be more firmly covered by the anode pad ANDP, the cathode pad CSDP, and the cathode wiring pad CSLP, thereby making it possible to better prevent deformation into an undercut structure.

[0380] Next, examples of the cathode wiring pad CSLP will be described with reference to FIGS.

[0381] FIG. 37 is a layout diagram showing the sixth conductive layers and the seventh conductive layers of the sub-pixels aligned in the first direction according to the first embodiment.

[0382] 37, the display panel 101 according to the first embodiment includes cathode wiring pads CSLP1 corresponding to each of the sub-pixels RP, GP, and BP.

[0383] As described above with reference to FIGS. 1 and 5, the substrate SUB of the display panel 101 includes a display area DA in which a plurality of sub-pixels RP, GP, BP are arranged in the first direction DR1 and the second direction DR2.

[0384] As shown in FIG. 2 and FIG. 37, a plurality of pixels PX can be provided, each of which is made up of two or more sub-pixels RP, GP, BP adjacent to each other in the first direction DR1 among the plurality of sub-pixels RP, GP, BP.

[0385] 37, the anode electrodes AND and the cathode electrodes CSD of the sub-pixels adjacent to each other in the first direction DR1 among the sub-pixels RP, GP, and BP may be arranged side by side in the first direction DR1, which makes it easier to align the light-emitting elements LE.

[0386] The cathode electrodes CSD of the sub-pixels RP, GP, and BP may be provided in a pattern connected to the cathode wiring CSL. That is, the cathode electrodes CSD are formed of parts of the cathode wiring CSL that protrude in the first direction DR1 and are aligned with the anode electrodes AND.

[0387] The cathode wiring CSL and the cathode electrode CSD are disposed apart from the anode electrode AND.

[0388] 24, 34, 35, and 36, the cathode wiring pad CSLP1 according to the first embodiment corresponds to each of the sub-pixels RP, GP, and BP. Therefore, the cathode wiring pads CSLP1 of the sub-pixels (RP, GP) and (GP, BP) adjacent to each other in the first direction DR1 can be disposed apart from each other.

[0389] FIG. 38 is a layout diagram showing the sixth conductive layers and the seventh conductive layers of the sub-pixels aligned in the first direction according to the second embodiment.

[0390] Referring to FIG. 38, a display panel 102 according to the second embodiment includes cathode wiring pads CSLP2 corresponding to each of a plurality of pixels PX.

[0391] The cathode wiring pad CSLP2 according to the second embodiment corresponds to any one of the pixels PX and is similar to the cathode wiring pad CSLP of the above-mentioned embodiment, except that it is further arranged at the boundary between two or more sub-pixels RP, GP, BP that constitute any one of the pixels PX, and therefore a duplicated description will be omitted.

[0392] According to the second embodiment, the cathode wiring pads CSLP2 of two or more sub-pixels RP, GP, and BP constituting any one pixel PX are connected to each other in the first direction DR1.

[0393] The cathode wiring pads (LCSLP2, CSLP2) (RCSLP2, CSLP2) of the sub-pixels (LPX_BP, RP) (BP, RPX_BP) adjacent to each other in the first direction DR1 and corresponding to different pixels are disposed apart from each other.

[0394] That is, the third sub-pixel LPX_BP of another pixel adjacent to one side of any one pixel PX in the first direction DR1 is adjacent to the first sub-pixel RP of any one pixel PX in the first direction DR1. At this time, the cathode line pad LCSLP2 of the third sub-pixel LPX_BP of the other pixel is disposed away from the cathode line pad CSLP2 of the first sub-pixel RP of any one pixel PX.

[0395] Similarly, the first sub-pixel RPX_RP of another pixel adjacent to the other side of the pixel PX in the first direction DR1 is adjacent to the third sub-pixel BP of the pixel PX in the first direction DR1. At this time, the cathode wiring pad RCSLP2 of the first sub-pixel RPX_RP of the another pixel is disposed away from the cathode wiring pad CSLP2 of the third sub-pixel BP of the pixel PX.

[0396] FIG. 39 is a layout diagram showing the sixth conductive layers and the seventh conductive layers of the sub-pixels aligned in the first direction according to the third embodiment.

[0397] Referring to FIG. 39, a display panel 103 according to the third embodiment includes cathode wiring pads CSLP3 corresponding to sub-pixels adjacent to each other in one direction.

[0398] That is, the cathode wiring pad CSLP3 according to the third embodiment is similar to the cathode wiring pad CSLP of the above-mentioned embodiment, except that it is further arranged at the boundary between adjacent sub-pixels (LPX_BP, RP) (RP, GP) (GP, BP) (BP, RPX_BP) in the first direction DR1, and therefore duplicated explanations will be omitted.

[0399] According to the third embodiment, the cathode wiring pads CSLP3 of the sub-pixels (LPX_BP, RP), (RP, GP), (GP, BP), and (BP, RPX_BP) adjacent to each other in the first direction DR1 are connected to each other in the first direction DR1.

[0400] FIG. 40 is a layout diagram showing the sixth conductive layers and the seventh conductive layers of the sub-pixels aligned in the first direction according to the fourth embodiment.

[0401] Referring to FIG. 40, a display panel 104 according to the fourth embodiment includes a cathode line pad CSLP4 that entirely covers the cathode line CSL.

[0402] That is, the cathode wiring pad CSLP4 according to the fourth embodiment is similar to the cathode wiring pad CSLP of the above-described embodiment, except that it is arranged so as to completely cover the upper surface of the entire cathode wiring CSL and the side surfaces of the edges of the cathode wiring CSL, rather than covering only the edges of the cathode wiring CSL, and therefore a duplicated explanation will be omitted.

[0403] The cathode wiring pads CSLP1, CSLP2, CSLP3, and CSLP4 shown in FIGS. 37 to 40 are merely examples, and the planar shape of the cathode wiring pads CSLP can be modified in various ways within a range that satisfies the condition of covering the side portions of the edges of the cathode wiring CSL.

[0404] FIG. 41 is a diagram illustrating a tiled display including multiple displays according to one embodiment.

[0405] Referring to FIG. 41, a tiled display device TD according to an embodiment may include a plurality of display devices 11, 12, 13, and 14 arranged side by side in a first direction DR1 and a second direction DR2, and seams SM between the plurality of display devices 11, 12, 13, and 14.

[0406] For example, the tiled display device TD may include a first display device 11, a second display device 12, a third display device 13, and a fourth display device 14.

[0407] The multiple display devices 11, 12, 13, 14 may be arranged in a lattice pattern. The multiple display devices 11, 12, 13, 14 may be arranged in a matrix pattern with m (m is a positive integer) rows and n (n is a positive integer) columns. For example, the first display device 11 and the second display device 12 may be adjacent to each other in the first direction DR1. The first display device 11 and the third display device 13 may be adjacent to each other in the second direction DR2. The third display device 13 and the fourth display device 14 may be adjacent to each other in the first direction DR1. The second display device 12 and the fourth display device 14 may be adjacent to each other in the second direction DR2.

[0408] However, the number and arrangement of the multiple display devices 11, 12, 13, and 14 in the tiled display device TD are not limited to those shown in Fig. 41. The number and arrangement of the display devices 11, 12, 13, and 14 in the tiled display device TD can be determined according to the respective sizes of the display device 10 and the tiled display device TD and the shape of the tiled display device TD.

[0409] The display devices 11, 12, 13, and 14 may have the same size, but are not limited to this. For example, the display devices 11, 12, 13, and 14 may have different sizes.

[0410] Each of the multiple display devices 11, 12, 13, 14 may have a rectangular shape including a long side and a short side. The multiple display devices 11, 12, 13, 14 may be arranged with their long sides or short sides connected to each other. Some or all of the multiple display devices 11, 12, 13, 14 may be arranged at the edge of the tiled display device TD and form one side of the tiled display device TD. At least one of the multiple display devices 11, 12, 13, 14 may be arranged at at least one corner of the tiled display device TD and form two adjacent sides of the tiled display device TD. At least one of the multiple display devices 11, 12, 13, 14 may be surrounded by other display devices.

[0411] Each of the multiple display devices 11, 12, 13, and 14 may be substantially the same as the display device 10 of each embodiment described with reference to Figures 1 to 39. Therefore, a description of each of the multiple display devices 11, 12, 13, and 14 will be omitted.

[0412] The seam portion SM may include a joining member or an adhesive member. In this case, the multiple display devices 11, 12, 13, and 14 may be connected to each other by the joining member or adhesive member of the seam portion SM. The seam portion SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0413] FIG. 42 is an enlarged layout diagram showing the L region of FIG. 41 in detail.

[0414] 42, the seam portion SM may have a planar shape of a cross, a cross, or a plus sign in a central region of the tiled display device TD where the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 are adjacent. The seam portion SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

[0415] The first display device 11 may include first pixels PX1 arranged in a matrix in a first direction DR1 and a second direction DR2 to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix in the first direction DR1 and the second direction DR2 to display an image.

[0416] The minimum distance between adjacent first pixels PX1 in the first direction DR1 may be defined as a first horizontal separation distance GH1, and the minimum distance between adjacent second pixels PX2 in the first direction DR1 may be defined as a second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially equal to each other.

[0417] A seam portion SM may be disposed between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1. The minimum distance G12 between the first pixel PX1 and the second pixel PX2 adjacent to each other in the first direction DR1 may be the sum of the minimum distance GHS1 between the first pixel PX1 and the seam portion SM in the first direction DR1, the minimum distance GHS2 between the second pixel PX2 and the seam portion SM in the first direction DR1, and the width GSM1 of the seam portion SM in the first direction DR1.

[0418] The minimum distance G12 between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 may be substantially the same. For this purpose, the minimum distance GHS1 between the first pixel PX1 and the seam portion SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1, and the minimum distance GHS2 between the second pixel PX2 and the seam portion SM in the first direction DR1 may be smaller than the second horizontal separation distance GH2. Also, the width GSM1 of the seam portion SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

[0419] The minimum distance between the third pixels PX3 adjacent to each other in the first direction DR1 may be defined as a third horizontal separation distance GH3, and the minimum distance between the fourth pixels PX4 adjacent to each other in the first direction DR1 may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially equal to each other.

[0420] A seam portion SM may be disposed between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1. The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 adjacent to each other in the first direction DR1 may be the sum of the minimum distance GHS3 between the third pixel PX3 and the seam portion SM in the first direction DR1, the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM in the first direction DR1, and the width GSM1 of the seam portion SM in the first direction DR1.

[0421] The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 may be substantially the same. For this purpose, the minimum distance GHS3 between the third pixel PX3 and the seam portion SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3, and the minimum distance GHS4 between the fourth pixel PX4 and the seam portion SM in the first direction DR1 may be smaller than the fourth horizontal separation distance GH4. Also, the width GSM1 of the seam portion SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

[0422] The minimum distance between adjacent first pixels PX1 in the second direction DR2 may be defined as a first vertical separation distance GV1, and the minimum distance between adjacent third pixels PX3 in the second direction DR2 may be defined as a third vertical separation distance GV3. The first vertical separation distance GV1 and the third vertical separation distance GV3 may be substantially equal to each other.

[0423] A seam portion SM may be disposed between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2. The minimum distance G13 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS1 between the first pixel PX1 and the seam portion SM in the second direction DR2, the minimum distance GVS3 between the third pixel PX3 and the seam portion SM in the second direction DR2, and the width GSM2 of the seam portion SM in the second direction DR2.

[0424] The minimum distance G13 between the first pixel PX1 and the third pixel PX3 adjacent to each other in the second direction DR2, the first vertical separation distance GV1, and the third vertical separation distance GV3 may be substantially the same. For this purpose, the minimum distance GVS1 between the first pixel PX1 and the seam portion SM in the second direction DR2 may be smaller than the first vertical separation distance GV1, and the minimum distance GVS3 between the third pixel PX3 and the seam portion SM in the second direction DR2 may be smaller than the third vertical separation distance GV3. Also, the width GSM2 of the seam portion SM in the second direction DR2 may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

[0425] The minimum distance between adjacent second pixels PX2 in the second direction DR2 may be defined as a second vertical separation distance GV2, and the minimum distance between adjacent fourth pixels PX4 in the second direction DR2 may be defined as a fourth vertical separation distance GV4. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially equal to each other.

[0426] A seam portion SM may be disposed between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2. The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 adjacent to each other in the second direction DR2 may be the sum of the minimum distance GVS2 between the second pixel PX2 and the seam portion SM in the second direction DR2, the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM in the second direction DR2, and the distance GSM4 of the seam portion SM in the second direction DR2.

[0427] The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 may be substantially the same. For this purpose, the minimum distance GVS2 between the second pixel PX2 and the seam portion SM in the second direction DR2 may be smaller than the second vertical separation distance GV2, and the minimum distance GVS4 between the fourth pixel PX4 and the seam portion SM in the second direction DR2 may be smaller than the fourth vertical separation distance GV4. Also, the width GSM2 of the seam portion SM in the second direction DR2 may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4.

[0428] As shown in FIG. 42, in order to prevent seam portions SM from being visible between images displayed by multiple display devices 11, 12, 13, and 14, the minimum distance between pixels of adjacent display devices may be substantially the same as the minimum distance between pixels of each of the display devices.

[0429] FIG. 43 is a cross-sectional view showing an example of a tiled display device taken along the line NN' in FIG.

[0430] 43, the first display device 11 includes a first display module DPM1 and a first front cover COV1, and the second display device 12 includes a second display module DPM2 and a second front cover COV2.

[0431] Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer TFTL, and a light emitting element layer EML. The thin film transistor layer TFTL and the light emitting element layer EML have already been described in detail with reference to Figures 1 to 40, so duplicated description will be omitted.

[0432] The substrate SUB may include a first surface on which the thin film transistor layer TFTL is disposed, a second surface opposite to the first surface, and a first side surface disposed between the first surface and the second surface. The first surface may be a front or top surface of the substrate SUB, and the second surface may be a back or bottom surface of the substrate SUB.

[0433] In addition, the substrate SUB may further include chamfer surfaces, each of which is disposed between the first surface and the first side surface and between the second surface and the first side surface and which is formed of an inclined surface.

[0434] The thin film transistor layer TFTL and the light emitting element layer EML do not have to be disposed on the chamfered surface. Since the width of the first side surface is reduced by the chamfered surface, damage caused by a collision between the substrate SUB of the first display device 11 and the substrate of the second display device 12 can be reduced.

[0435] The chamfered surfaces may also be disposed between the first surface and each of the other side surfaces excluding the first side surface, and between the second surface and each of the other side surfaces excluding the first side surface. For example, when the first display device 11 and the second display device 12 have a rectangular planar shape as shown in Fig. 42, the substrate SUB may include chamfered surfaces disposed between the first surface and each of the second side surfaces, the third side surfaces, and the fourth side surfaces, and between the second surface and each of the second side surfaces, the third side surfaces, and the fourth side surfaces.

[0436] The first front cover COV1 may overlap a chamfered surface of the substrate SUB, i.e., the first front cover COV1 may protrude from the substrate SUB in the first direction DR1 and the second direction DR2. Therefore, the distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 may be greater than the distance GCOV between the first front cover COV1 and the second front cover COV2.

[0437] Each of the first front cover COV1 and the second front cover COV2 may include an adhesive member 51, a light transmittance adjusting layer 52 disposed on the adhesive member 51, and an anti-glare layer (53) disposed on the light transmittance adjusting layer 52.

[0438] The adhesive member 51 of the first front cover COV1 serves to attach the light emitting element layer EML of the first display module DPM1 to the first front cover COV1.

[0439] The adhesive member 51 of the second front cover COV2 serves to attach the light emitting element layer EML2 of the second display module DPM2 to the second front cover COV2.

[0440] The adhesive member 51 may be a transparent adhesive member that can transmit light. For example, the adhesive member 51 may be an optically clear adhesive film or an optically clear resin.

[0441] The anti-glare layer 53 can be designed to diffusely reflect external light to prevent the external light from being reflected as it is and reducing the visibility of the image. Therefore, the anti-glare layer 53 can increase the contrast ratio of the images displayed by the first display device 11 and the second display device 12.

[0442] The light transmittance adjusting layer 52 may be designed to reduce the transmittance of external light or light reflected by the first display module DPM1 and the second display module DPM2, thereby preventing the gap GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 from being visible from the outside.

[0443] The anti-glare layer 53 is realized as a polarizer, and the light transmittance adjusting layer 52 is realized as a phase retardation layer, but the embodiments herein are not limited thereto.

[0444] FIG. 44 is an enlarged layout diagram showing the M region of FIG. 41 in detail.

[0445] FIG. 44 shows a pad PAD and a first pixel PX1 arranged on the upper side of the first display device 10.

[0446] 44, a pad PAD may be disposed on an upper edge of the first display device 11. When the data wiring DL of the first display device 11 extends in the second direction DR2, the pad PAD may be disposed on the upper and lower edges of the first display device 11. Alternatively, when the data wiring DL of the first display device 11 extends in the first direction DR1, the pad PAD may be disposed on the left and right edges of the first display device 11.

[0447] Each of the pads PAD may be connected to a data line DL, or each of the pads PAD may be a part of the data line DL.

[0448] In addition, each of the pads PAD may be coupled to a side wiring (SCL in FIG. 45). The side wiring SCL may be disposed on one side and the lower surface (or rear surface) of the substrate SUB. The side wiring SCL may be coupled to a connecting wiring (CCL in FIG. 45) on the lower surface of the substrate SUB.

[0449] FIG. 45 is a cross-sectional view showing an example of a tiled display device taken along the line OO' in FIG.

[0450] 45, the pad PAD may be disposed on a portion of the data wiring DL. As an example, the pad PAD may include a first pad layer PAD1 made of a sixth conductive layer such as an anode electrode AND and a second pad layer PAD2 made of a seventh conductive layer such as an anode pad ANDP.

[0451] Alternatively, although not shown, the pad is made up of a part of the data wiring DL.

[0452] Alternatively, although not shown, the pad is disposed on an insulating film (not shown) covering the data line DL and is made of a conductive pattern that contacts a part of the data line DL via a hole penetrating the insulating film.

[0453] When the pad PAD has a structure including a first pad layer PAD1 and a second pad layer PAD2, a part of the pad PAD may be exposed without being covered by a planarizing film or other insulating film.

[0454] The first pad layer PAD1 may include a highly reflective metal material such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a laminated structure of APC alloy and ITO (ITO / APC / ITO).

[0455] The second pad layer PAD2 is made of a transparent conductive material (TCO) such as ITO or IZO.

[0456] The data wiring DL is made of the third conductive layer on the second interlayer insulating film 142 .

[0457] The interconnection wire CCL may be disposed on the lower surface of the substrate SUB. The interconnection wire CCL may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0458] The lower planarization film INS1 may be disposed on a portion of the interconnect CCL. The lower planarization film INS1 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0459] The lower insulating film INS2 may be disposed on the lower planarizing film INS1. The lower insulating film INS2 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0460] The side wiring SCL may be disposed on the bottom edge, side, and top edge of the substrate SUB. One end of the side wiring SCL may be coupled to the connecting wiring CCL. One end of the side wiring SCL may contact the side and bottom surface of the connecting wiring CCL. The other end of the side wiring SCL may be coupled to a pad or a data wiring DL. The other end of the side wiring SCL may be coupled to a pad or a data wiring DL via a contact hole penetrating the protective film PAS.

[0461] The side wiring SCL can be disposed on a side surface of the substrate SUB, a side surface of the buffer film BF, a side surface of the gate insulating film 130, a side surface of the first interlayer insulating film 141, and a side surface of the second interlayer insulating film 142.

[0462] The flexible film FPCB may be disposed on a lower surface of the lower insulating film INS2. The flexible film FPCB may be connected to the connection wiring CCL via a hole penetrating the lower planarization film INS1 and the lower insulating film INS2 and a conductive adhesive member CAM. A source driving circuit SIC for supplying a data voltage to the data line DL may be disposed on the lower surface of the flexible film FPCB. The conductive adhesive member CAM may be an anisotropic conductive film or an anisotropic conductive paste.

[0463] 44 and 45, in the first display device 11, the source driving circuit SIC of the flexible film FPCB disposed under the substrate SUB can be connected to the data wiring DL via the connecting wiring CCL, the side wiring SCL, and the pad PAD. That is, since the source driving circuit SIC is disposed under the substrate SUB, the non-display area NDA can be eliminated on the upper part of the substrate SUB, and the pixels PX can be formed even on the edge of the substrate SUB.

[0464] FIG. 46 is a block diagram illustrating a tiled display device according to one embodiment.

[0465] In FIG. 46, a first display device 11 and a host system HOST are shown.

[0466] Referring to FIG. 46, a tiled display device TD according to an embodiment is connected to a host system HOST.

[0467] The host system HOST can be realized as one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a mobile phone system, or a tablet.

[0468] A user's command may be input to the host system HOST in various forms. For example, the host system HOST may receive a command by touch input from the user. Alternatively, the host system HOST may receive a command by keyboard input or button input from a remote controller.

[0469] The host system HOST may receive an input of original video data ODATA corresponding to an original image from the outside. The host system HOST may divide the original video data ODATA as many times as the number of display devices. For example, the host system HOST may divide the original video data ODATA into first video data DATA1 corresponding to the first image, second video data DATA2 corresponding to the second image, third video data DATA3 corresponding to the third image, and fourth video data DATA4 corresponding to the fourth image, corresponding to the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14. The host system HOST may transmit the first video data DATA1 to the first display device 11, the second video data DATA2 to the second display device 12, the third video data DATA3 to the third display device 13, and the fourth video data DATA4 to the fourth display device 14.

[0470] The first display device 11 can display a first image according to the first video data DATA1, the second display device 12 can display a second image according to the second video data DATA2, the third display device 13 can display a third image according to the third video data DATA3, and the fourth display device 14 can display a fourth image according to the fourth video data DATA4. Therefore, the user can view the original image in which the first to fourth images displayed on the first to fourth display devices 11, 12, 13, and 14 are combined.

[0471] The first display device 11 may include a broadcast tuning unit 510, a signal processing unit 520, a display unit 530, a speaker 540, a user input unit 550, a HDD 560, a network communication unit 570, a UI generation unit 580, and a control unit 590.

[0472] The broadcast tuning unit 510 may tune to a predetermined channel frequency and receive a broadcast signal of the corresponding channel through an antenna under the control of the control unit 590. The broadcast tuning unit 510 may include a channel detection module and an RF demodulation module.

[0473] The broadcast signal demodulated by the broadcast tuning unit 510 is processed by a signal processing unit 520 and output to a display unit 530 and a speaker 540. Here, the signal processing unit 520 may include a demultiplexer 521, a video decoder 522, a video processing unit 523, an audio decoder 524, and an additional data processing unit 525.

[0474] The demultiplexer 521 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are respectively restored by a video decoder 522, an audio decoder 524, and an additional data processor 525. At this time, the video decoder 522, the audio decoder 524, and the additional data processor 525 restore the broadcast signal to a decoded format corresponding to the encoded format when the broadcast signal is transmitted.

[0475] Meanwhile, the decoded video signal is converted by the video processor 523 according to the vertical frequency, resolution, aspect ratio, etc. that meet the output standard of the display unit 530 , and the decoded audio signal is output to the speaker 540 .

[0476] The display unit 530 includes a display panel 100 on which an image is displayed and a panel driver that controls driving of the display panel 100. A detailed block diagram of the display panel 100 and the panel driver has been described with reference to FIG. 4, etc., so a duplicated description will be omitted.

[0477] The user input unit 550 can receive a signal transmitted by the host system HOST. The user input unit 550 can be provided so that the user can select and input data for commands related to communication with the other display devices DV2 to DV4 as well as data related to channel selection, UI (User Interface) menu selection and operation transmitted by the host system HOST.

[0478] The storage unit 560 stores various software programs including an OS program, recorded broadcast programs, videos, photos, and other data, and is implemented by a storage medium such as a hard disk or a non-volatile memory.

[0479] The network communication unit 570 is for short-range communication with the host system HOST and other display devices DV2 to DV4, and can be realized as a communication module including an antenna pattern capable of realizing mobile communication, data communication, Bluetooth (registered trademark), RF, Ethernet (registered trademark), etc.

[0480] The network communication unit 570 may also transmit and receive wireless signals to and from at least one of a base station, an external terminal, and a server on a mobile communication network constructed in accordance with a technical standard or communication method for mobile communication (e.g., Global System for Mobile communication (GSM), Code Division Multi Access (CDMA), Code Division Multi Access 2000 (CDMA2000), Enhanced Voice-Data Optimized or Enhanced Voice-Data Only (EV-DO), Wideband CDMA (WCDMA (registered trademark)), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Long Term Evolution-Advanced (LTE-A), 5G, etc.) via an antenna pattern described below.

[0481] The network communication unit 570 can also transmit and receive wireless signals over a communication network according to a wireless Internet technology through an antenna pattern described below. Examples of wireless Internet technologies include Wireless LAN (WLAN), Wireless-Fidelity (Wi-Fi), Wireless Fidelity (Wi-Fi) Direct, Digital Living Network Alliance (DLNA), Wireless Broadband (WiBro), World Interoperability for Microwave Access (WiMAX), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), and Long Term Evolution-Advanced (LTE-A), and the antenna pattern transmits and receives data according to at least one wireless Internet technology including Internet technologies not listed above.

[0482] The UI generating unit 580 generates a UI menu for communication with the host system HOST and the other display devices DV2 to DV4, and can be realized by an algorithm code and an OSD IC. The UI menu for communication with the host system HOST and the other display devices DV2 to DV4 can be a menu for specifying a digital TV with which communication is desired and for selecting a desired function.

[0483] The control unit 590 is responsible for the overall control of the first display device 11 and for communication control between the host system HOST and the second through fourth display devices 12, 13, and 14, and can be realized by an MCU (Micro Controller Unit) that stores the relevant algorithm code for control and executes the stored algorithm code.

[0484] The control unit 590 controls to transmit corresponding control commands and data to the host system HOST and the second through fourth display devices 12, 13, and 14 through the network communication unit 570 in response to the input and selection of the user input unit 550. Of course, when a predetermined control command and data is input from the host system HOST and the second through fourth display devices 12, 13, and 14, the control unit 590 operates according to the corresponding control command.

[0485] On the other hand, the block diagram of the second display device 12, the block diagram of the third display device 13, and the block diagram of the fourth display device 14 are substantially identical to the block diagram of the first display device 11 described with reference to Figure 46, so their explanations will be omitted.

[0486] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0487] 100 Display Panel PX pixels RP, GP, BP 1st, 2nd, 3rd sub-pixel SUB board TFTL Thin Film Transistor Layer EML Light emitting element layer AND Anode electrode CSD cathode electrode ANDP Anode Pad CSDP Cathode Pad ANDC Anode Contact Electrode CSDC cathode contact electrode PAS protective film LE Light Emitting Element BSUB Base Substrate NSEM n-type semiconductor MQW active layer PSEM p-type semiconductor CTE1,2 First and second contact electrodes 10 Display device DA display area NDA Hidden Area 110 Scan drive unit 200 Source drive unit 300 Timing control section 400 Power supply section GWL Scan Write Wiring GIL scan initialization wiring GCL Scan control wiring SWPL Sweep signal wiring PWEL PWM light emitting wiring PAEL PAM light-emitting wiring DL PWM data wiring RDL, GDL, BDL 1st, 2nd, 3rd PAM data wiring DATA Digital video data TS Timing Signal DCS PWM control signal VDD1,2 First and second power supply voltages VSS Third power supply voltage VINT Initialization voltage VGL Gate on voltage VGH Gate off voltage PDU1, PDU2, PDU3 1st, 2nd, 3rd pixel driving unit AVSL 3rd power supply auxiliary wiring VSL 3rd power supply wiring 130 Gate insulating film 141, 142 First and second interlayer insulating films 160 First planarization film 170 Second planarization film 180 Third planarization film ANDE1,2 First and second anode connecting electrodes CSL cathode wiring CSLP, CSLP1, CSLP2, CSLP3, CSLP4 Cathode wiring pad TD tile display device 11,12,13,14 1st, 2nd, 3rd, 4th display device

Claims

1. a substrate including a display region in which a plurality of sub-pixels are arranged; an active layer disposed on the substrate; a gate insulating film covering the active layer; a first interlayer insulating film covering a first conductive layer disposed on the gate insulating film; a second interlayer insulating film covering a second conductive layer disposed on the first interlayer insulating film; a first planarization film covering a third conductive layer disposed on the second interlayer insulating film; a second planarization film covering a fourth conductive layer disposed on the first planarization film; a third planarization film covering a fifth conductive layer disposed on the second planarization film; a sixth conductive layer disposed on the third planarization film; a seventh conductive layer disposed over at least a portion of the sixth conductive layer; The sixth conductive layer is a plurality of anode electrodes corresponding to the plurality of sub-pixels, a plurality of cathode electrodes corresponding to the plurality of sub-pixels, the cathode electrodes being spaced apart from the plurality of anode electrodes; a cathode wiring connected to the plurality of cathode electrodes, a plurality of anode pads covering the plurality of anode electrodes, respectively; a plurality of cathode pads covering the plurality of cathode electrodes, respectively; a cathode wiring pad covering at least a portion of the cathode wiring.

2. The light emitting device further includes a plurality of light emitting elements disposed on the anode electrode and the cathode electrode of each of the plurality of sub-pixels, The display device according to claim 1 , wherein the plurality of light-emitting elements are flip-chip type micro light-emitting diode elements.

3. In each of the plurality of sub-pixels, the anode pad is disposed on the anode electrode, covers an upper surface and a side surface of the anode electrode, and is in contact with the third planarization film; The display device according to claim 1 , wherein the cathode pad is disposed on the cathode electrode, covers an upper surface and a side surface of the cathode electrode, and is in contact with the third planarization film.

4. The display device according to claim 3 , wherein in each of the plurality of sub-pixels, the cathode wiring pad covers an edge of the cathode wiring that faces the anode electrode and the cathode electrode, respectively.

5. The display device according to claim 4 , wherein the cathode wiring pad is disposed on an edge of the cathode wiring, covers an upper surface and a side surface of the edge of the cathode wiring, and is in contact with the third planarization film.

6. In each of the plurality of sub-pixels, the cathode wiring pad is disposed away from the anode pad, corresponds to a boundary between each of the anode electrode and the cathode electrode and the cathode wiring, and forms a closed loop shape together with at least a part of an edge of the cathode pad; The display device according to claim 5 , wherein the anode electrodes and the cathode electrodes of adjacent sub-pixels in one direction among the plurality of sub-pixels are arranged side by side in the one direction.

7. the cathode wiring pads correspond to the plurality of sub-pixels, The display device according to claim 6 , wherein the cathode wiring pads of the sub-pixels adjacent to each other in the one direction are disposed apart from each other.

8. a plurality of pixels are provided, each of which is composed of two or more sub-pixels adjacent to each other in the one direction among the plurality of sub-pixels; the cathode wiring pad corresponds to each of a plurality of pixels, and is further disposed on a boundary between the two or more sub-pixels included in each of the plurality of pixels; The display device according to claim 6 , wherein the cathode wiring pads of sub-pixels adjacent in the one direction and corresponding to different pixels are disposed apart from each other.

9. The display device according to claim 6 , wherein the cathode wiring pads correspond to the sub-pixels adjacent in the one direction, and are further disposed at boundaries between the sub-pixels adjacent in the one direction.

10. The display device according to claim 6 , wherein the cathode wiring pad covers the entire cathode wiring.

11. The display device according to claim 6 , wherein each of the plurality of anode pads, the plurality of cathode pads and the cathode wiring pad extends onto the third planarization film.

12. a scan write line to which a scan write signal is applied; a scan initialization wiring to which a scan initialization signal is applied; a sweep signal line to which a sweep signal is applied; a first data line to which a first data voltage is applied; a second data line to which a second data voltage is applied, Each of the plurality of sub-pixels is connected to the scan write wiring, the scan initialization wiring, the sweep signal wiring, the first data wiring, and the second data wiring; Each of the plurality of sub-pixels includes a first pixel driver that generates a control current in response to the first data voltage of the first data line; a second pixel driver that generates a driving current to be applied to the anode electrode in response to the second data voltage of the second data line; a third pixel driving unit that controls a period during which the driving current is passed through a light emitting element in response to a control current of the first pixel driving unit; The first pixel driving unit is a first transistor that generates the control current in response to the first data voltage; a second transistor for applying the first data voltage of the first data line to a first electrode of the first transistor in response to the scan write signal; a third transistor for applying an initialization voltage of an initialization voltage line to a gate electrode of the first transistor in response to the scan initialization signal; a fourth transistor connecting a gate electrode and a second electrode of the first transistor in response to the scan write signal; The display device according to claim 6 , further comprising: a first capacitor disposed between the sweep signal wiring and a gate electrode of the first transistor.

13. a first power supply wiring to which a first power supply voltage is applied; a second power supply line to which a second power supply voltage is applied; a first light-emitting wiring to which a first light-emitting signal is applied; A scan control line to which a scan control signal is applied, The first pixel driving unit is a fifth transistor connecting the first power supply line to a first electrode of the first transistor in response to the first light-emitting signal; a sixth transistor connecting the second electrode of the first transistor to a first node in response to the first light-emitting signal; The display device of claim 12 , further comprising: a seventh transistor connecting the sweep signal line to a gate-off voltage line to which a gate-off voltage is applied in response to the scan control signal.

14. The second pixel driving unit is an eighth transistor that generates the driving current in response to the second data voltage; a ninth transistor applying the second data voltage of the second data line to a first electrode of the eighth transistor in response to the scan write signal; a tenth transistor that applies an initialization voltage of the initialization voltage line to a gate electrode of the eighth transistor in response to the scan initialization signal; The display device of claim 13 , further comprising an eleventh transistor connecting a gate electrode and a second electrode of the eighth transistor in response to the scan write signal.

15. The second pixel driving unit is a twelfth transistor connecting the second power supply line to a second node in response to the first light-emitting signal; a thirteenth transistor connecting the second power supply line to the first electrode of the ninth transistor in response to the first light-emitting signal; a fourteenth transistor connecting the first power supply line to a second node in response to the scan control signal; The display device according to claim 14 , further comprising: a second capacitor disposed between a gate electrode of the eighth transistor and the second node.

16. The third pixel driving unit is a fifteenth transistor including a gate electrode coupled to the third node; a sixteenth transistor connecting the first node to the initialization voltage line in response to the scan control signal; a seventeenth transistor connecting the second electrode of the fifteenth transistor to the first electrode of the light emitting device in response to a second light emitting signal; an eighteenth transistor connecting a first electrode of the light emitting device to the initialization voltage line in response to the scan control signal; The display device according to claim 15 , further comprising: a third capacitor disposed between the first node and the initialization voltage wiring.

17. a test signal wiring to which a test signal is applied; a third power supply wiring to which a third power supply voltage is applied; The third pixel driving unit is a 19th transistor connecting the first electrode of the light emitting device to the third power line in response to the test signal; The display device of claim 16 , wherein the cathode wiring is connected to the third power supply wiring.

18. the active layer includes a channel, a source electrode, and a drain electrode of each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, and nineteenth transistors; the first conductive layer includes gate electrodes of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth and nineteenth transistors, and first, third and fifth capacitor electrodes which are one ends of the first, second and third capacitors, respectively; 18. The display device according to claim 17, wherein the second conductive layer includes second, fourth and sixth capacitor electrodes which are the other ends of the first, second and third capacitors, respectively.

19. the third conductive layer includes the initialization voltage wiring, the scan initialization wiring, the scan write wiring, the first light emitting wiring, the second light emitting wiring, a first horizontal power supply wiring to which the first power supply voltage is applied, the sweep signal wiring, a gate-off voltage wiring, a scan control wiring, a test signal wiring, and a third auxiliary power supply wiring to which the third power supply voltage is applied, the fourth conductive layer includes the first data line, a first vertical power supply line to which the first power supply voltage is applied, the second data line, and a first anode connecting electrode; The display device of claim 18 , wherein the first anode connecting electrode is connected to a drain electrode of the seventeenth transistor and a drain electrode of the eighteenth transistor.

20. The fifth conductive layer is The third power supply wiring; The display device of claim 19 , further comprising: a second anode connecting electrode connected to the first anode connecting electrode.

21. a protection film disposed on the third planarization film and covering edges of the anode pads, edges of the cathode pads, the cathode wiring pad, and the cathode wiring; In each of the plurality of sub-pixels, the anode pad is connected to a first contact electrode of a light emitting element via an anode contact electrode; The display device of claim 6 , wherein the cathode pad is connected to the second contact electrode of the light emitting element through a cathode contact electrode.

22. A plurality of display devices and a seam portion disposed between the plurality of display devices, Any one of the plurality of display devices is a substrate including a display region in which a plurality of sub-pixels are arranged; an active layer disposed on the substrate; a gate insulating film covering the active layer; a first interlayer insulating film covering a first conductive layer disposed on the gate insulating film; a second interlayer insulating film covering a second conductive layer disposed on the first interlayer insulating film; a first planarization film covering a third conductive layer disposed on the second interlayer insulating film; a second planarization film covering a fourth conductive layer disposed on the first planarization film; a third planarization film covering a fifth conductive layer disposed on the second planarization film; a sixth conductive layer disposed on the third planarization film; a seventh conductive layer disposed over at least a portion of the sixth conductive layer; The sixth conductive layer is a plurality of anode electrodes corresponding to the plurality of sub-pixels, a plurality of cathode electrodes corresponding to the plurality of sub-pixels, the cathode electrodes being spaced apart from the plurality of anode electrodes; a cathode wiring connected to the plurality of cathode electrodes; The seventh conductive layer is a plurality of anode pads covering the plurality of anode electrodes, respectively; a plurality of cathode pads covering the plurality of cathode electrodes, respectively; a cathode wiring pad covering at least a portion of the cathode wiring.

23. The tiled display device of claim 22 , wherein the substrate is made of glass.

24. Any one of the display devices, a pad disposed on a first surface of the substrate; 23. The tiled display device of claim 22, further comprising: a first surface of the substrate, a second surface opposite to the first surface, and a side wiring disposed on one side between the first surface and the second surface and connected to the pad.

25. Any one of the display devices, a connecting wire disposed on a second surface of the substrate; a flexible film connected to the connecting wire via a conductive adhesive member, The tiled display device of claim 24 , wherein the side wiring is connected to the connecting wiring.

26. The tiled display device of claim 22 , wherein the plurality of display devices are arranged in a matrix of M rows and N columns.

27. Any one of the display devices, The light emitting device further includes a plurality of light emitting elements disposed on the anode electrode and the cathode electrode of each of the plurality of sub-pixels, The tiled display device according to claim 22 , wherein the light-emitting elements are flip-chip type micro light-emitting diode elements.

28. In each of the plurality of sub-pixels, the anode pad is disposed on the anode electrode, covers an upper surface and a side surface of the anode electrode, and is in contact with the third planarization film; The tiled display device according to claim 22 , wherein the cathode pad is disposed on the cathode electrode, covers an upper surface and a side surface of the cathode electrode, and is in contact with the third planarization film.

29. The tiled display device according to claim 28 , wherein in each of the plurality of sub-pixels, the cathode wiring pad covers an edge of the cathode wiring that faces each of the anode electrode and the cathode electrode.

30. The tiled display device according to claim 29 , wherein the cathode wiring pad is disposed on an edge of the cathode wiring, covers an upper surface and a side surface of the edge of the cathode wiring, and is in contact with the third planarization film.

31. In each of the plurality of sub-pixels, the cathode wiring pad is disposed away from the anode pad, corresponds to a boundary between each of the anode electrode and the cathode electrode and the cathode wiring, and forms a closed loop shape together with at least a part of an edge of the cathode pad; The tiled display device according to claim 30 , wherein the anode electrodes and the cathode electrodes of adjacent sub-pixels in one direction among the plurality of sub-pixels are arranged side by side in the one direction.

32. The tiled display device according to claim 31 , wherein each of the plurality of anode pads, the plurality of cathode pads and the cathode wiring pad extends onto the third planarization film.

Images