Circuit protection from input voltage

Abstract

The present disclosure generally relates to protecting a circuit from an input voltage. Various embodiments include an apparatus including one or more circuits for drawing or providing current from or to a pair of connectors for an input circuit. The connectors may be for electrically coupling to first and second terminals of a twisted pair. The one or more circuits may be at least partially responsive to positive and negative bias signals. The apparatus may further include an operational amplifier for generating the positive and negative bias signals. The operational amplifier may include a first input terminal at least partially responsive to a reference voltage and a second input terminal at least partially responsive to a common mode voltage of the input circuit. Related systems and methods are also disclosed.

Description

[Technical field]

[0001] (Priority Claim) This application claims the benefit of Chinese Patent Application No. 202210160218.8, entitled "Protecting a Circuit From an Input Voltage," filed on February 22, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0002] FIELD OF THEINVENTION This disclosure relates generally to protecting circuits from input voltages. [Background technology]

[0003] Differential signaling generally describes information being conveyed electronically using two different but complementary electrical signals. For example, a single signal may be represented as a signal and its complement, each using its own wire, for example in a twisted pair of conductors. Differential signals may be affected by interference that is common to both of the complementary signals, i.e., common mode interference, which appears as a common mode voltage. [Brief description of the drawings]

[0004] While the disclosure concludes with claims that particularly point out and distinctly claim certain embodiments, the various features and advantages of embodiments within the scope of the disclosure can be more readily ascertained from the following description when read in conjunction with the accompanying drawings. [Figure 1] FIG. 1 is a hybrid circuit schematic / functional block diagram illustrating an example apparatus according to one or more embodiments. [Diagram 2] FIG. 1 is a hybrid circuit schematic / functional block diagram illustrating an example circuit according to one or more embodiments. [Diagram 3] 1 illustrates a method according to one or more embodiments. [Figure 4] FIG. 1 is a functional block diagram illustrating an example apparatus in accordance with one or more embodiments. [Diagram 5]FIG. 1 is a functional block diagram illustrating an example apparatus in accordance with one or more embodiments. [Figure 6] FIG. 1 is a functional block diagram illustrating an example system in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of the present disclosure.

[0006] The drawings presented herein are not meant to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in various drawings may retain the same or similar numbering for the convenience of the reader, however, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to assist those skilled in the art in implementing the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory, and the scope of the present disclosure is intended to encompass examples and legal equivalents, but the use of such terms is not intended to limit the scope of the embodiments of the present disclosure to specific components, steps, features, functions, etc.

[0008] It will be readily understood that the components of the embodiments, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be depicted in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Additionally, the block definitions and partitioning of logic among various blocks are examples of specific implementations. It will be readily apparent to those skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like are omitted, and such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout this specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may show signals as a single signal for clarity of display and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal. Those skilled in the art will understand that the present disclosure encompasses communication of quantum information and qubits used to represent quantum information.

[0011] The various schematic logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (sometimes referred to herein as a host processor or simply a host) may be a microprocessor, although alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer, and a general purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0012] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of the acts may be rearranged. A process may correspond to, without limitation, a method, a thread, a function, a procedure, a subroutine, or a subprogram. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0013] 1 is a hybrid circuit schematic / functional block diagram illustrating an example apparatus 100 according to one or more embodiments. The apparatus 100 may modify a differential signal by reducing the magnitude of a voltage common to both of the differential signals, i.e., by reducing the common-mode voltage. The apparatus 100 may be electrically coupled to conductors configured to carry the differential signal, for example, in a transceiver of a signaling device. The apparatus 100 may reduce the magnitude of the common-mode voltage by providing or sinking a current. Because the conductors carrying the differential signal may be electrically coupled to several devices (e.g., transceivers), reducing the magnitude of the common-mode voltage in the apparatus 100 may benefit all of the several devices.

[0014] The device 100 may include one or more circuits 102 configured to sink or provide current from or to a pair of connectors (e.g., connector 104 and connector 106) for an input circuit (not shown in FIG. 1). In FIG. 1, for purposes of illustration, the device 100 is shown as including four circuits 102, namely, circuit 102a, circuit 102b, circuit 102c, and circuit 102d (which may be collectively referred to as circuits 102). Various embodiments may include any suitable number of circuits 102. The number of circuits 102 included in the device 100 may be a design choice based, for example, on the level of common-mode voltage to be rejected by the device 100. For example, each of the circuits 102 may sink or provide an amount of current (e.g., but not limited to, in the range of several hundred microamps). The device 100 may be designed to include a number of circuits 102 proportional to the amount of current that may need to be sink or provide.

[0015] Each of the circuits 102 may be electrically coupled to both a connector 104 and a connector 106 via a line 118 and a line 120, respectively. The connectors 104 and the connectors 106 may be, for example, connectors for electrically coupling to terminals 148 and 150, respectively, of a twisted pair 152. The voltage common to both the lines 118 and the lines 120 may be a common mode voltage 122.

[0016] Circuit 102 may sink or provide current to lines 118 and 120, for example, to reduce the magnitude of common-mode voltage 122, i.e., to reduce common-mode interference. Apparatus 100 may include a feedback loop to control the amount of current sinked or provided by circuit 102. For example, circuit 102 may sink or provide current to lines 118 and 120 at least in part in response to bias signals 108 and 110 (e.g., positive and negative bias signals, respectively).

[0017] The operational amplifier 112 may generate the bias signal 108 and the bias signal 110. The operational amplifier 112 may include an input terminal 114 (e.g., a positive input terminal) that may be electrically coupled to a node at which a reference voltage 124 is observable. The reference voltage 124 may be selected based on R1 and R2. In some embodiments, the reference voltage 124 may be midway between a rail voltage 144 (e.g., “VDD”) and a ground 146 (e.g., when R1=R2). The operational amplifier 112 may also include an input terminal 116 (e.g., a negative terminal) that may be electrically coupled to a node 128 at which a feedback voltage (vfb) 126 may be observable. The feedback voltage 126 may be at least partially responsive to a common mode voltage 122 of the device 100. In particular, the line 118 and the line 120 may be electrically coupled to the node 128 via two or more passive elements, such as a capacitor 130, a resistor 132, a resistor 134, and a capacitor 136. For example, line 118 may be electrically coupled to node 128 via capacitor 130 and resistor 132, and line 120 may be electrically coupled to node 128 via resistor 134 and capacitor 136. Feedback voltage 126 may be between the voltages at line 118 and line 120 based on the ratio of the resistances of resistor 132 and resistor 134 (and / or the ratio of the reactances of capacitor 130 and capacitor 136). For example, if resistor 132 has the same resistance as resistor 134, feedback voltage 126 may be midway between the voltages at line 118 and line 120. Thus, feedback voltage 126 will be related to common mode voltage 122, e.g., feedback voltage 126 may represent a voltage common to the voltages at line 118 and line 120. Capacitor 130 and capacitor 136 may improve the high frequency response of device 100.

[0018] The operational amplifier 112 may compare the difference between the reference voltage 124 and the feedback voltage 126 and generate the bias signal 108 and the bias signal 110 based on the difference. For example, when the common mode voltage 122 is higher than the reference voltage 124, the feedback voltage 126 may also be higher than the reference voltage 124. When the feedback voltage 126 is higher than the reference voltage 124, the operational amplifier 112 may increase the bias signal 108 and the bias signal 110. The increase in the bias signal 108 and the bias signal 110 may cause the circuit 102 to draw current from the lines 118 and 120 to ground (the connection between the circuit 102 and ground is not shown in FIG. 1), thereby decreasing the magnitude of the common mode voltage 122. As an alternative example, when the common mode voltage 122 is lower than the reference voltage 124, the feedback voltage 126 may be lower than the reference voltage 124. When the feedback voltage 126 is lower than the reference voltage 124, the operational amplifier 112 may decrease the bias signals 108 and 110. The decrease in the bias signals 108 and 110 may cause the circuit 102 to provide current to the lines 118 and 120, thereby decreasing the magnitude of the common-mode voltage 122 (e.g., when the voltages on the lines 118 and 120 are negative).

[0019] The apparatus 100 may include a feedback voltage protection circuit 138 that may maintain the feedback voltage 126 within a threshold. For example, the feedback voltage protection circuit 138 may include a first number of diodes 140 disposed between the rail voltage 144 and the node 128, and a second number of diodes 142 between the node 128 and ground 146. As an example of how the feedback voltage protection circuit 138 may maintain the feedback voltage 126 within a threshold, if the feedback voltage 126 is greater than the collective forward voltage of the diodes 142 (e.g., 2.8 volts for four diodes each having a forward voltage of 0.7 volts), any excess voltage is pulled to ground 146. Thus, the feedback voltage 126 may be at most the collective forward voltage of the diodes 142. As another example, if the feedback voltage 126 is less than the rail voltage 144 minus the collective forward voltage of the diodes 140 (e.g., VDD-2.8 volts), the rail voltage 144 provides the excess voltage. Thus, the feedback voltage 126 may be at its lowest the rail voltage 144 minus the overall forward voltage of the diodes 140. The feedback voltage protection circuit 138 may, among other things, prevent the feedback voltage 126 from damaging the operational amplifier 112, for example, by preventing the feedback voltage 126 from exceeding an operating threshold of the input terminal 116. In FIG. 1, both the diodes 140 and the diodes 142 are shown as including four diodes each for illustrative purposes. The number of diodes 140 and the diodes 142 may be selected based on the rail voltage 144 and the operating threshold of the input terminal 116.

[0020] Each of the circuits 102 may include a current mirror to sink or provide current to the lines 118 and 120 at least in part in response to the bias signals 108 and 110. Additionally, each of the circuits 102 may include protection circuitry to protect the transistors of the current mirrors from the voltage of one of the connectors. Additional details regarding embodiments of the circuits 102 are described with respect to FIG.

[0021] 2 is a hybrid circuit schematic / functional block diagram illustrating an example circuit 200 in accordance with one or more embodiments. Circuit 200 is one embodiment of circuit 102 of FIG. 1. Circuit 200 may, for example, sink or provide current from inputs 204 and 206 to reduce the magnitude of a common-mode voltage at inputs 204 and 206.

[0022] 1 as an example of circuit 102, input 204 may be electrically coupled to connector 104 of Figure 1 (e.g., via line 118 of Figure 1), and input 206 may be electrically coupled to connector 106 of Figure 1 (e.g., via line 120 of Figure 1). Additionally, when circuit 200 is placed in device 100, input 208 may receive bias signal 108 of Figure 1, and input 210 may receive bias signal 110 of Figure 1.

[0023] The circuit 200 may include a current mirror 212 for providing a current to a pair of inputs (i.e., inputs 204 and 206) at least in part in response to a bias signal (e.g., received at inputs 208 and 210). Additionally or alternatively, the circuit 200 may include a current mirror 218 for sinking a current from the inputs 204 and 206 at least in part in response to the bias signal. For example, when the bias signal at the inputs 208 and 210 is low, the mirror transistors 214 and 216, denoted MP0 and MP1, respectively, may allow current to flow from a rail voltage 264 (e.g., “VDD”) to the inputs 204 and 206. When the bias signal at the inputs 208 and 210 is high, the mirror transistors 220 and 222, denoted MN0 and MN1, respectively, may allow current from the inputs 204 and 206 to flow to ground 266.

[0024] Circuit 200 may be included in a circuit (e.g., device 100) in which inputs 204 and 206 may exhibit high common-mode voltages (e.g., common-mode voltages higher than rail voltage 264 or lower than ground 266). In some embodiments, circuit 200 may be included in a circuit in which inputs 204 and 206 may exhibit voltages up to about 40 volts and as low as about -40 volts.

[0025] To enable circuit 200 to operate with high common-mode voltages at input 204 and input 206, circuit 200 may include protection circuits to protect mirror transistor 214, mirror transistor 216, mirror transistor 220, and mirror transistor 222 from the effects of high voltages at input 204 and input 206. For example, circuit 200 may include protection circuit 224 (e.g., “first protection circuit 224”) to protect mirror transistor 214 (e.g., “first transistor 214”) of current mirror 212 (e.g., “first current mirror 212”) from excessive voltages at input 204. Circuit 200 may also include protection circuit 232 (e.g., “second protection circuit 232”) to protect mirror transistor 216 (e.g., “second transistor 216”) of current mirror 212 from excessive voltages at input 206. Circuit 200 may also include a protection circuit 240 (e.g., “third protection circuit 240”) to protect mirror transistor 220 (e.g., “third transistor 220”) of current mirror 218 (e.g., “second current mirror 218”) from excessive voltages at input 204. Circuit 200 may also include a protection circuit 248 (e.g., “fourth protection circuit 248”) to protect mirror transistor 222 (e.g., “fourth transistor 222”) of current mirror 218 from excessive voltages at input 206.

[0026] Each of the protection circuits 224, 232, 240, and 248 may include a respective high voltage capable diode, i.e., the protection circuit 224 may include an HV diode 230 (designated as D0), the protection circuit 232 may include an HV diode 238 (designated as D1), the protection circuit 240 may include an HV diode 246 (designated as D2), and the protection circuit 248 may include an HV diode 254 (designated as D3). Each of the HV diodes 230, 238, 246, and 254 may be capable of withstanding a high reverse voltage without breaking down and allowing current to flow. For example, as a non-limiting example, each of the HV diodes 230, 238, 246, and 254 may be capable of withstanding a reverse voltage of up to 80 volts without breaking down and allowing current to flow.

[0027] Thus, for example, if input 204 exhibits a voltage higher than rail voltage 264, HV diode 230 may protect HV transistor 226 and / or mirror transistor 214 by preventing body junction breakdown of HV transistor 226 and / or mirror transistor 214 and preventing unintended current from flowing from input 204 to HV transistor 226 and / or mirror transistor 214. Similarly, if input 206 exhibits a voltage higher than rail voltage 264, HV diode 238 may protect HV transistor 234 and / or mirror transistor 216 by preventing body junction breakdown of HV transistor 234 and / or mirror transistor 216 and preventing unintended current from flowing from input 206 to HV transistor 234 and / or mirror transistor 216. Similarly, when input 204 exhibits a voltage lower than ground 266, HV diode 246 may protect HV transistor 242 and / or mirror transistor 220 by preventing body junction breakdown of HV transistor 242 and / or mirror transistor 220 and preventing unintended current from flowing from HV transistor 242 and / or mirror transistor 220 to input 204. Similarly, when input 206 exhibits a voltage lower than ground 266, HV diode 254 may protect HV transistor 250 and / or mirror transistor 220 by preventing body junction breakdown of HV transistor 250 and / or mirror transistor 222 and preventing unintended current from flowing from HV transistor 250 and / or mirror transistor 220 to input 204.

[0028] Further, each of protection circuit 224, protection circuit 232, protection circuit 240, and protection circuit 248 may include a high-voltage capable transistor, such as a laterally-diffused (LD) metal-oxide semiconductor (MOS) field-effect transistor (FET). For example, protection circuit 224 may include HV transistor 226 (which may be an LD positive-channel MOS (LD-PMOS) transistor denoted as MP2), protection circuit 232 may include HV transistor 234 (which may be an LD-PMOS transistor denoted as MP3), protection circuit 240 may include HV transistor 242 (which may be an LD negative-channel MOS (LD-NMOS) transistor denoted as MN2), and protection circuit 248 may include HV transistor 250 (which may be an LD-NMOS transistor denoted as MN2). Each of HV transistor 226, HV transistor 234, HV transistor 242, and HV transistor 250 may be capable of withstanding high drain-source voltages (and / or source-drain voltages) without breaking down or allowing current to flow. For example, as a non-limiting example, each of HV transistor 226, HV transistor 234, HV transistor 242, and HV transistor 250 may be capable of a drain-source voltage (or source-drain voltage) of up to 60 volts without breaking down or allowing current to flow.

[0029] For example, when the input 204 exhibits a voltage lower than the ground 266, the HV transistor 226, whose gate is connected to the ground 266, may clamp the drain voltage of the mirror transistor 214 to the ground 266 plus the threshold voltage of the HV transistor 226, thereby preventing the source-drain voltage of the mirror transistor 214 from exceeding the safe operating area. Further, as a non-limiting example, the HV transistor 226 may be capable of withstanding a source-drain voltage of up to 60 volts. Thus, as a non-limiting example, if the input 204 exhibits a voltage of 40 volts, the HV transistor 226 may continue to operate without breaking down. Similarly, when the input 206 exhibits a voltage lower than the ground 266, the HV transistor 234, whose gate is connected to the ground 266, may clamp the drain voltage of the mirror transistor 216 to the ground 266 plus the threshold voltage of the HV transistor 234, thereby preventing the source-drain voltage of the mirror transistor 216 from exceeding the safe operating area. Further, by way of non-limiting example, HV transistor 234 may be capable of withstanding a source-drain voltage of up to 60 volts. Thus, by way of non-limiting example, if input 206 exhibits a voltage of 40 volts, HV transistor 226 may continue to operate without breaking down. Similarly, when input 204 exhibits a voltage higher than rail voltage 264, HV transistor 242, whose gate is connected to rail voltage 264, may clamp the drain voltage of mirror transistor 220 to rail voltage 264 minus the threshold voltage of HV transistor 242, thereby preventing the drain-source voltage of mirror transistor 220 from exceeding a safe operating area. Further, by way of non-limiting example, HV transistor 242 may be capable of withstanding a drain-source voltage of up to 60 volts. Thus, by way of non-limiting example, if input 204 exhibits a voltage of 40 volts, HV transistor 242 may continue to operate without breaking down.Similarly, when the input 206 exhibits a voltage higher than the rail voltage 264, the HV transistor 250, whose gate is connected to the rail voltage 264, may clamp the drain voltage of the mirror transistor 222 to the rail voltage 264 minus the threshold voltage of the HV transistor 250, thereby preventing the drain-source voltage of the mirror transistor 222 from exceeding its safe operating area. Further, as a non-limiting example, the HV transistor 250 may be able to withstand a drain-source voltage of up to 60 volts. Thus, as a non-limiting example, if the input 206 exhibits a voltage of 40 volts, the HV transistor 250 may continue to operate without breaking down.

[0030] Additionally, each of protection circuit 224, protection circuit 232, protection circuit 240, and protection circuit 248 may include a diode between the respective mirror transistor of the respective current mirror and both the gate and rail voltage or ground of the respective HV transistor of the respective protection circuit.

[0031] For example, the protection circuit 224 may include a forward facing diode 228, designated D4, (e.g., allowing current to flow) between ground 266 and the common connection of the source of HV transistor 226 and the drain of mirror transistor 214 of current mirror 212. Diode 228 may prevent current from flowing from the current mirror 212 (and from the source of HV transistor 226) to ground 266. Diode 228 may function to prevent the drain of mirror transistor 214 from dropping below ground 266 minus 0.7 volts during power down. Similarly, the protection circuit 232 may include a forward facing diode 236, designated D5, between ground 266 and the common connection of the source of HV transistor 234 and the drain of mirror transistor 216 of current mirror 212. Diode 236 may prevent current from flowing from the current mirror 212 (and from the source of HV transistor 234) to ground 266. Diode 236 may function to prevent the drain of mirror transistor 216 from dropping below ground 266 minus 0.7 volts during power down. Similarly, protection circuit 240 may include a forward facing diode 244, designated D6, between the common connection of the drain of mirror transistor 220 and the source of HV transistor 242 of current mirror 218 and the rail voltage 264. Diode 244 may prevent current from flowing from the rail voltage 264 to current mirror 218 (and the source of HV transistor 242). Diode 244 may function to prevent the drain of mirror transistor 220 from rising above rail voltage 264 plus 0.7 volts during power down. Similarly, protection circuit 248 may include a forward facing diode 252, designated D7, between the common connection of the drain of mirror transistor 222 and the source of HV transistor 250 of current mirror 218 and the rail voltage 264. Diode 252 may prevent current from flowing from the rail voltage 264 to the current mirror 218 (and the source of HV transistor 250). Diode 252 may function to prevent the drain of mirror transistor 222 from rising above the rail voltage 264+0.7 volts during power down.

[0032] Circuit 200 may also include a capacitor 256, denoted C0, electrically coupled between input 204 and input 208, a capacitor 258, denoted C1, electrically coupled between input 206 and input 208, a capacitor 260, denoted C2, electrically coupled between input 204 and input 210, and a capacitor 262, denoted C3, electrically coupled between input 206 and input 210. Capacitor 256, capacitor 258, capacitor 260, and capacitor 262 may provide high frequency compensation. For example, when the frequency of input 204 and input 206 is higher than the bandwidth of the operational amplifier (e.g., input terminal 114 in FIG. 1), capacitor 256, capacitor 258, capacitor 260, and capacitor 262 may directly feed back the common mode voltage to input 208 and input 210 and control the input impedance via mirror transistor 216, current mirror 218, mirror transistor 220, and mirror transistor 222. Additionally, capacitor 256 may be considered to be between input 204 and the gate of mirror transistor 214 and / or the gate of mirror transistor 216. Similarly, capacitor 258 may be considered to be between input 206 and the gate of mirror transistor 214 and / or the gate of mirror transistor 216. Similarly, capacitor 260 may be considered to be between input 204 and the gate of mirror transistor 220 and / or the gate of mirror transistor 222. Similarly, capacitor 262 may be considered to be between input 206 and the gate of mirror transistor 220 and / or the gate of mirror transistor 222.

[0033] 3 is a flowchart of an example method 300 according to various embodiments of the present disclosure. At least a portion of the method 300 may be performed in some embodiments by a device or system such as the apparatus 100 of FIG. 1 or another device or system. Although shown as multiple separate blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated depending on the desired implementation.

[0034] In block 302, the bias signal may be generated at least partially in response to a feedback signal. The feedback signal may be at least partially in response to a common mode voltage of the first terminal and the second terminal. For example, bias signal 108 of FIG. 1 and bias signal 110 of FIG. 1 may be generated in response to feedback voltage 126 of FIG. 1. Feedback voltage 126 may be at least partially in response to common mode voltage 122 of connector 104 of FIG. 1 and connector 106 of FIG. 1.

[0035] In block 304, the common mode voltage may be reduced at the first and second terminals by currents provided to or drawn from the first and second terminals at least in part in response to the bias signals. For example, the circuit 102 of FIG. 1 may provide current to or draw current from the connectors 104 and 106 at least in part in response to the bias signals 108 and 110.

[0036] In block 306, which may be optional, the transistors of the current mirror used to source or sink current may be protected by preventing the voltage at the source or drain of the transistor from exceeding a safe operating threshold. For example, the mirror transistor 214 of FIG. 2 of the current mirror 212 of FIG. 2 may be protected by the protection circuit 224 of FIG. 2, which may prevent the voltage at the source or drain of the mirror transistor 214 from exceeding a safe operating threshold of the mirror transistor 214.

[0037] In block 308, which may be optional, the operational amplifier used to generate the bias signal may be protected by preventing the feedback voltage from exceeding a threshold. For example, the operational amplifier 112 of FIG. 1 may be protected by the feedback voltage protection circuit 138 of FIG. 1, which prevents the feedback voltage 126 from exceeding a safe operating threshold of the operational amplifier 112.

[0038] Modifications, additions, or omissions may be made to method 300 without departing from the scope of the present disclosure. For example, the operations of method 300 may be implemented in a different order. Additionally, the outlined operations and acts are provided only as examples, and some of the operations and acts may be optional, may be combined into fewer operations and acts, or may be expanded to additional operations and acts without departing from the essence of the disclosed embodiments.

[0039] 4 is a functional block diagram illustrating an example apparatus 400 according to one or more embodiments. The apparatus 400 can modify a differential signal by reducing the magnitude of the voltage common to both differential signals, i.e., the common-mode voltage.

[0040] The device 400 may include an input circuit 420 (the input circuit 420 may include a pair of connectors 402), one or more circuits 404 (each of the one or more circuits 404 may include a first input 422 and a second input 424, respectively), and an operational amplifier 412 (the operational amplifier 412 may include a first input terminal 414 and a second input terminal 416). Additionally shown in FIG. 1 are the terminals of the twisted pair 406, a positive bias signal 408 (the positive bias signal 408 may be a signal between an output (e.g., a positive output) of the operational amplifier 412 and a first input 422), a negative bias signal 410 (the negative bias signal 410 may be a signal between another output (e.g., a negative output) of the operational amplifier 412 and a second input 424), and a first current 418 (the current 418 may be a current between the pair of connectors 402 and the one or more circuits 404).

[0041] Any two or more of the terminals of the twisted pair 406, the pair of connectors 402, the input circuitry 420, and the one or more circuits 404 are optional. The optionality of any two or more of the terminals of the twisted pair 406, the input circuitry 420, and the one or more circuits 404 is depicted in FIG. 4 using dashed lines.

[0042] 4, the device 400 may include one or more circuits 404 that may sink or provide a current 418 to a pair of connectors 402 of an input circuit 420. The pair of connectors 402 may be for electrically coupling to first and second terminals of a twisted pair 406. A first input 422 and a second input 424 of each of the one or more circuits 404 may be at least partially responsive to a positive bias signal 408 and a negative bias signal 410.

[0043] Additionally, the apparatus 400 may include an operational amplifier 412 for generating the positive bias signal 408 and the negative bias signal 410. The operational amplifier 412 has a first input terminal 414 (the first input terminal 414 is connected to a reference voltage (V REF ) and a second input terminal 416 (which may be at least partially responsive to the common mode voltage (V CM ) may be at least partially responsive to

[0044] 5 is a functional block diagram depicting an example device 500 in accordance with one or more embodiments. The device 500 can sink or provide a current 508 to a pair of inputs 504.

[0045] In a non-limiting example depicted by Figure 5, the device 500 may include a current mirror 502 (which may include a transistor 510) and a protection circuit 506. Additionally, a pair of inputs 504 is depicted in Figure 5, and the pair of inputs 504 is optional. The option of the pair of inputs 504 is depicted in Figure 5 using dashed lines. Additionally, Figure 5 depicts a voltage 512 (which may be a voltage at the pair of inputs 504 or may be a voltage of the pair of inputs 504) and a bias signal 514 (which may be received by the current mirror 502).

[0046] The current mirror 502 may sink or provide a current 508 to a pair of inputs 504 at least in part in response to a bias signal 514. A protection circuit 506 may protect a transistor 510 of the current mirror 502 from a voltage 512 on one or more of the pair of inputs 504.

[0047] 6 is a functional block diagram illustrating an example system 600 according to one or more embodiments. The system 600 detects a common mode voltage (V CM The system 600 may provide a differential signal (V DIFF ) may further be maintained.

[0048] In a non-limiting example depicted by Figure 6, the system 600 may include first and second connectors 602 for electrically coupling with respective first and second terminals of the twisted pair and one or more circuits 604. Additionally depicted in Figure 6 is a current 606 (which may be a current between the first and second connectors 602 of the twisted pair and the one or more circuits 604) and positive and negative bias signals 608 (which may be received by the one or more circuits 604).

[0049] One or more circuits 604 are electrically coupled to the first and second connectors 602 (which may be electrically coupled to the first and second terminals of the twisted pair, respectively) to detect a common mode voltage (V CM ) at the first and second connectors 210 by selectively drawing or providing a current 606 to or from the first and second connectors 602 in response to, at least in part, the positive and negative bias signals 608.DIFF ) may be maintained (twisted pair differential signaling may be maintained).

[0050] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation configured to perform the actions of a module or component and / or software object or routine that may be stored on and / or executed by general-purpose hardware (e.g., but not limited to, computer-readable media, processing device) of a computing system. In various embodiments, different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) executing on a computing system. Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored and / or executed on general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0051] As used in this disclosure, the term "combination" in reference to multiple elements may include a combination of all the elements or any of various different subcombinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to any one of A, B, C, or D; each combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0052] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," and the term "includes" should be interpreted, without limitation, as "including, but not limited to").

[0053] Additionally, if a particular number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce the recitation of claims. However, the use of such phrases should not be construed as implying that the introduction of a claim recitation with the indefinite article "a" or "an" limits any particular claim that includes such an introduced claim recitation to an embodiment that includes only one such recitation (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"), even if the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"). The same is true for the use of express articles used to introduce claim recitations.

[0054] In addition, even if a particular number of an introduced claim recitation is explicitly recited, one of ordinary skill in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other qualifiers means at least two recitations or more than two recitations). Furthermore, when a convention similar to "including but not limited to at least one of A, B, and C" or "including but not limited to one or more of A, B, and C" is used, such a structure is generally intended to include, but is not limited to, A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0055] Additionally, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either one of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0056] Additional non-limiting examples of the present disclosure may include the following.

[0057] Example 1: An apparatus comprising: one or more circuits for drawing current from or providing current to a pair of connectors for an input circuit, the connectors for electrically coupling to first and second terminals of a twisted pair, each first and second input of the one or more circuits being at least partially responsive to positive and negative bias signals; and an operational amplifier for generating the positive and negative bias signals, the operational amplifier having a first input terminal at least partially responsive to a reference voltage and a second input terminal at least partially responsive to a common mode voltage of the input circuit.

[0058] Example 2: The apparatus of example 1, wherein the second input terminal of the operational amplifier is at least partially responsive to a feedback voltage, the feedback voltage being observable at a node electrically connected to both of the pair of connectors.

[0059] Example 3: The apparatus of any one of examples 1 to 2, further comprising a feedback voltage protection circuit for keeping the feedback voltage within a threshold.

[0060] Example 4: The apparatus of any of Examples 1-3, wherein the feedback voltage protection circuit comprises a first number of diodes arranged between the rail voltage and a node at the feedback voltage, and a second number of diodes between the node at the feedback voltage and ground.

[0061] Example 5: An apparatus described in any of Examples 1-4, wherein each of the one or more circuits comprises a current mirror for sinking current from or providing current to the pair of connectors in at least partial response to positive and negative bias signals.

[0062] Example 6: An apparatus described in any of Examples 1 to 5, wherein each of the one or more circuits includes a protection circuit for protecting the transistors of the current mirror from the voltage of one of the pair of connectors.

[0063] Example 7: An apparatus comprising: a current mirror for sinking or providing current from a pair of inputs in at least partial response to a bias signal; and a protection circuit for protecting a transistor of the current mirror from a voltage of one of the pair of inputs.

[0064] Example 8: The apparatus of example 7, wherein the current mirror comprises a first current mirror for sinking current from the pair of inputs, and the protection circuit comprises a first protection circuit for protecting a first transistor of the first current mirror from a first voltage of one of the pair of inputs, and the apparatus comprises a second protection circuit for protecting a second transistor of the first current mirror from a second voltage of the other of the pair of inputs, a second current mirror for providing current to the pair of inputs, a third protection circuit for protecting a third transistor of the second current mirror from a third voltage of one of the pair of inputs, and a fourth protection circuit for protecting a fourth transistor of the second current mirror from a fourth voltage of the other of the pair of inputs.

[0065] Example 9: The apparatus of example 7 or 8, wherein the protection circuit comprises a high-voltage compatible diode between one of the pair of inputs and the transistor of the current mirror.

[0066] Example 10: An apparatus as described in any of Examples 7-9, wherein the current mirror sinks current from a pair of inputs and the high voltage compatible diode is for preventing current flow from the current mirror to one of the pair of inputs.

[0067] Example 11: An apparatus described in any of Examples 7 to 10, wherein the current mirror is for providing current to a pair of inputs and the high voltage compatible diode is for preventing current flow from one of the pair of inputs to the current mirror.

[0068] Example 12: The apparatus of any of Examples 7-11, wherein the protection circuit includes a high-voltage compatible transistor electrically connected between one of the pair of inputs and the transistor of the current mirror.

[0069] Example 13: A device described in any of Examples 7 to 12, wherein the high-voltage compatible transistor is for withstanding a voltage difference between a source or drain of the high-voltage compatible transistor electrically connected to one of a pair of inputs and the other of the source or drain of the high-voltage compatible transistor electrically connected to the transistor of the current mirror.

[0070] Example 14: An apparatus as described in any of Examples 7-13, wherein the current mirror is for sinking current from a pair of inputs, the gates of the high voltage capable transistors are electrically coupled to a voltage rail, and a diode is electrically connected between the gates of the high voltage capable transistors and the other of the sources of the high voltage capable transistors.

[0071] Example 15: The apparatus of any of examples 7-14, wherein the diode is for preventing current flow from the voltage rail to the source of the high voltage capable transistor.

[0072] Example 16: An apparatus described in any of Examples 7-15, wherein the current mirror is for providing current to a pair of inputs, the gate of the high voltage capable transistor is electrically coupled to ground, and a diode is electrically connected between the gate and source of the high voltage capable transistor.

[0073] Example 17: The apparatus of any of Examples 7-16, wherein the diode is for preventing current flow from a source of the high voltage capable transistor to a ground electrically coupled to the gate of the high voltage capable transistor.

[0074] Example 18: An apparatus according to any one of Examples 7 to 17, further comprising a capacitor between one of the pair of inputs and the gate of the transistor of the current mirror.

[0075] Example 19: A system comprising: first and second connectors for electrically coupling to respective first and second terminals of a twisted pair; and one or more circuits coupled to the first and second connectors to reduce a common mode voltage at the first and second connectors and maintain a differential signal at the first and second connectors by selectively drawing current from or providing current to the first and second connectors in at least partial response to positive and negative bias signals.

[0076] Example 20: The system described in Example 19, further comprising an operational amplifier for generating positive and negative bias signals, the operational amplifier having a first input terminal responsive at least in part to a reference voltage and a second input terminal responsive at least in part to a common mode voltage.

[0077] Example 21: A method comprising: generating a bias signal at least partially responsive to a feedback signal, the feedback signal being at least partially responsive to a common-mode voltage at a first terminal and a second terminal; and reducing the common-mode voltage at the first terminal and the second terminal by providing a current to or sinking a current from the first terminal and the second terminal, at least partially responsive to the bias signal.

[0078] Example 22: The method of example 21, comprising protecting a transistor of a current mirror used to provide or sink current by preventing a voltage at a source or drain of the transistor from exceeding a safe operating threshold.

[0079] Example 23: The method of examples 21 and 22, comprising protecting an operational amplifier used to generate the bias signal by preventing the feedback signal from exceeding a threshold.

[0080] While the present disclosure has been described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the present invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below along with their legal equivalents. In addition, features from one embodiment can be combined with features of another embodiment as contemplated by the inventors and still fall within the scope of the present disclosure.

Claims

1. An apparatus comprising: one or more circuits for drawing current from or providing current to a pair of connectors for input circuits, the pair of connectors for electrically coupling to first and second terminals of a twisted pair, the one or more circuits having respective first and second inputs that are at least partially responsive to positive and negative bias signals; an operational amplifier for generating the positive and negative bias signals, the operational amplifier comprising: a first input terminal at least partially responsive to a reference voltage; a second input terminal at least partially responsive to a common mode voltage of the input circuit.

2. 2. The apparatus of claim 1, wherein the second input terminal of the operational amplifier is at least partially responsive to a feedback voltage, the feedback voltage being observable at a node electrically connected to both of the pair of connectors.

3. The apparatus of claim 1 , further comprising a feedback voltage protection circuit for keeping the feedback voltage within a threshold.

4. 4. The apparatus of claim 3, wherein the feedback voltage protection circuit comprises a first number of diodes disposed between a rail voltage and a node at the feedback voltage, and a second number of diodes between the node at the feedback voltage and ground.

5. 2. The apparatus of claim 1, wherein each of the one or more circuits comprises a current mirror for sinking the current from or providing the current to the pair of connectors in at least part of the response to the positive and negative bias signals.

6. 6. The apparatus of claim 5, wherein each of the one or more circuits comprises a protection circuit for protecting a transistor of the current mirror from a voltage on one of the pair of connectors.

7. An apparatus comprising: a current mirror for sinking or providing current to a pair of inputs in response at least in part to a bias signal; a protection circuit for protecting the transistors of the current mirror from the voltage of one of the pair of inputs.

8. the current mirror comprises a first current mirror for sinking current from the pair of inputs, and the protection circuit comprises a first protection circuit for protecting a first transistor of the first current mirror from a first voltage of the one of the pair of inputs, and the apparatus further comprises: a second protection circuit for protecting a second transistor of the first current mirror from a second voltage of the other of the pair of inputs; a second current mirror for providing current to said pair of inputs; a third protection circuit for protecting a third transistor of the second current mirror from a third voltage on the one of the pair of inputs; 8. The apparatus of claim 7, further comprising: a fourth protection circuit for protecting a fourth transistor of the second current mirror from a fourth voltage of the other of the pair of inputs.

9. 8. The apparatus of claim 7, wherein the protection circuit comprises a high voltage capable diode between the one of the pair of inputs and the transistor of the current mirror.

10. 10. The apparatus of claim 9, wherein the current mirror sinks current from the pair of inputs, and the high voltage capable diode is for preventing current flow from the current mirror to the one of the pair of inputs.

11. 10. The apparatus of claim 9, wherein the current mirror is for providing current to the pair of inputs and the high voltage capable diode is for preventing current flow from the one of the pair of inputs to the current mirror.

12. 8. The apparatus of claim 7, wherein the protection circuit comprises a high voltage capable transistor electrically connected between the one of the pair of inputs and the transistor of the current mirror.

13. 13. The apparatus of claim 12, wherein the high-voltage capable transistor is for withstanding a voltage difference between one of a source or a drain of the high-voltage capable transistor electrically connected to the one of the pair of inputs and the other of the source or the drain of the high-voltage capable transistor electrically connected to the transistor of the current mirror.

14. 14. The apparatus of claim 13, wherein the current mirror is for sinking current from the pair of inputs, the gates of the high voltage capable transistors being electrically coupled to a voltage rail, and a diode is electrically connected between the gates of the high voltage capable transistors and the other of the source or drain of the high voltage capable transistor.

15. 15. The apparatus of claim 14, wherein the diode is for preventing current flow from the voltage rail to the source of the high voltage capable transistor.

16. 14. The apparatus of claim 13, wherein the current mirror is for providing a current to the pair of inputs, a gate of the high voltage capable transistor being electrically coupled to ground, and a diode is electrically connected between the gate and the source of the high voltage capable transistor.

17. 17. The apparatus of claim 16, wherein the diode is for preventing current flow from the source of the high voltage capable transistor to the ground that is electrically coupled to the gate of the high voltage capable transistor.

18. 8. The apparatus of claim 7, further comprising a capacitor between one of the pair of inputs and the gate of the transistor of the current mirror.

19. 1. A system comprising: first and second connectors for electrically coupling to the first and second terminals, respectively, of the twisted pair; and one or more circuits coupled to the first and second connectors to selectively draw current from or provide current to the first and second connectors in response at least in part to positive and negative bias signals to reduce a common mode voltage at the first and second connectors and maintain a differential signal at the first and second connectors.

20. and an operational amplifier for generating the positive and negative bias signals, the operational amplifier comprising: a first input terminal at least partially responsive to a reference voltage; and a second input terminal at least partially responsive to the common mode voltage.

21. 1. A method comprising: generating a bias signal at least partially responsive to a feedback signal, the feedback signal being at least partially responsive to a common mode voltage of the first terminal and the second terminal; and reducing the common-mode voltage at the first and second terminals by providing current to or sinking current from the first and second terminals in at least partial response to the bias signal.

22. 22. The method of claim 21, comprising protecting transistors of a current mirror used to source or sink the current by preventing a voltage at a source or drain of the transistor from exceeding a safe operating threshold.

23. 22. The method of claim 21, comprising protecting an operational amplifier used to generate the bias signal by preventing the feedback signal from exceeding a threshold.

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