Initiating transmission of a frame with a desired starting polarity and related systems, methods and devices - Patents.com

Abstract

Systems, methods, and devices are disclosed for communicating the source of a 10SPE wake. Such communication may be performed across a low pin count hardware interface of a 10SPE physical layer (PHY) module having a split configuration. The controller side of the 10SPE PHY may perform local or remote 10SPE wake transfers in response to the communicated source of the wake. Also disclosed is a digital interface for operatively coupling the PHY controller to a PHY transceiver via a low pin count connection, the digital interface including circuitry for checking circuit integrity of the digital interface. Also disclosed is a PHY transceiver of the 10SPE PHY, the transceiver including circuitry for controlling frame start polarity.

Description

[Technical field]

[0001] (Priority Claim) This application claims the benefit of the filing date of People's Republic of China Application No. 202210151634.1, filed on February 18, 2022, entitled "STARTING TRANSMISSION OF A FRAME WITH A DESIRED STARTING POLARITY, AND RELATED SYSTEMS, METHODS AND DEVICES," the disclosure of which is incorporated herein by reference in its entirety.

[0002] FIELD OF THEINVENTION The present disclosure generally relates to single pair Ethernet networks. Some embodiments relate to a limited number of connections interface for a 10SPE physical layer module with a split configuration. Some embodiments relate to initiating transmission of a frame with a predetermined starting polarity and controlling it in a physical layer transceiver of an Ethernet PHY. [Background technology]

[0003] Interconnects are widely used to facilitate communication between devices, subsystems, and systems of a network. Generally speaking, electrical signals are transmitted over a physical medium (such as, without limitation, a bus, coaxial cable, or twisted pair - commonly referred to simply as a "line" or a "bus") by devices coupled to that physical medium.

[0004] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., the electrical signals are discrete electrical pulses) to transmit data packets and ultimately messages communicated between network devices. According to the OSI model, specialized circuitry called physical layer (PHY) devices or controllers are used to interface between the analog domain of the line and the digital domain of the data link layer (also referred to herein simply as the "link layer"), which operates according to packet signaling. Although the data link layer may include one or more sublayers, in Ethernet-based computer networking, the data link layer typically includes at least a media access control (MAC) layer, which provides a control abstraction of the physical layer. As a non-limiting example, when transmitting data to another device in the network, the MAC controller may prepare a frame for the physical media, add error correction elements, and implement collision avoidance. Additionally, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare a frame for a higher layer.

[0005] There are various network topologies that implement the physical layer and link layer (and may include, without limitation, other layers). The Peripheral Component Interconnect (PCI) standard and the Parallel Advanced Technology Attachment (Parallel ATA) standard, both in use since the early 1990s, can implement a multi-drop bus topology. The trend since the early 2000s has been to use a point-to-point bus topology; for example, the PCI Express standard (PCIe) and the Serial ATA (SATA) standard implement a point-to-point topology.

[0006] A typical point-to-point bus topology may implement circuits between each device (e.g., without limitation, dedicated point-to-point) or circuits between devices and switches (e.g., without limitation, switched point-to-point). In a multi-drop bus topology, the physical transmission medium is a shared bus and each network device is coupled to the shared bus via circuitry that is selected based on, for example, the type of physical media (e.g., without limitation, coax or twisted pair).

[0007] Point-to-point bus topologies, such as dedicated point-to-point or switched point-to-point topologies, require more wires and more expensive materials than multi-drop topologies, due in part to the larger number of links between devices. In certain applications, such as in automobiles, physical constraints may exist that make it difficult to directly connect devices, and thus topologies that do not require direct connections or do not require the same number of direct connections within a network or sub-network (e.g., without limitation, multi-drop topologies) may be less susceptible to or hindered by such constraints.

[0008] Devices in a baseband network (such as, but not limited to, a multi-drop network) share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (i.e., the digital signals used in baseband transmission occupy the entire bandwidth of the medium). As a result, only one device of the baseband network may transmit at a given moment. Therefore, medium access control methods may be used to handle contention for such a shared transmission medium. [Brief description of the drawings]

[0009] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which that element is first introduced. [Figure 1] 1 is a block diagram of a portion of a physical layer transceiver including test pulse control circuitry in accordance with one or more embodiments. [Diagram 2] FIG. 1 is a flow diagram illustrating a process for performing a portion of cable diagnostics in a PHY transceiver in accordance with one or more embodiments. [Diagram 3] 1 illustrates a flow diagram showing a process for controlling the starting polarity at which a PHY transceiver begins transmitting a frame. [Figure 4] 1 illustrates aspects of the subject matter according to one embodiment. [Diagram 5] FIG. 1 is a block diagram illustrating a circuit for implementing some or all of the features or elements disclosed in one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized, and structure, materials, and processes may be changed without departing from the scope of the present disclosure.

[0011] The figures presented herein are not meant to be actual diagrams of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. The figures presented herein are not necessarily drawn to scale. Similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0012] The following description may include examples to assist those skilled in the art in enabling the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the relevant description is illustrative, and the scope of the disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the examples or the scope of the disclosure to specific components, steps, features, functions, etc.

[0013] It will be readily understood that the components of the examples, as generally described herein and illustrated in the Figures, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. Although various aspects of the examples may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0014] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic between various blocks are exemplary specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like are omitted, and such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of one skilled in the art.

[0015] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of display and explanation. Those skilled in the art will appreciate that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0016] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor (sometimes referred to herein as a host processor or simply a host) may be a microprocessor, although alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer, and the general purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0017] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of the acts may be rearranged. A process may correspond to, but is not limited to, a method, a thread, a function, a procedure, a subroutine, a subprogram. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0018] Any reference to elements herein using a designation such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, a reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. In addition, unless otherwise stated, a set of elements may include one or more elements.

[0019] As used herein, any relative terms such as "over," "under," "on," "underlying," "upper," "lower," and the like are used for clarity and convenience in understanding the disclosure and the accompanying drawings, and are not intended to be implied in or dependent upon any particular priority, orientation, or order unless the context clearly dictates otherwise.

[0020] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with small variations, such as, for example, within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0021] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers present. In contrast, when an element is described as "directly coupled" to another element, there are no intervening elements or layers present. The terms "on" and "connected" may be used interchangeably with the term "coupled" herein and have the same meaning unless expressly stated otherwise or the context indicates otherwise to one of ordinary skill in the art.

[0022] As used herein, the terms "assert," "de-assert," and their derivatives when used in reference to a pin refer to asserting or de-asserting, respectively, a signal associated with the pin (e.g., without limitation, a signal that is specifically assigned to the pin or a signal to which the pin is specifically assigned).

[0023] Vehicles, such as cars, trucks, buses, ships, and / or aircraft, may include a vehicle communication network. The complexity of the vehicle communication network may vary depending on the number of electronic devices in the network. For example, an advanced vehicle communication network may include various control modules for engine control, transmission control, safety control (e.g., anti-lock brakes), and emissions control, as non-limiting examples. To support these modules, the automotive industry relies on a variety of communication protocols.

[0024] 10SPE (i.e., 10Mbps Single Pair Ethernet) is a network technology currently under the IEEE 802.3cg™ specification. 10SPE can be used, for example but not limited to, to provide collision-free, deterministic transmission over multi-drop networks or shared transmission media.

[0025] Some bit-level encoding processes are used to encode the bits of a frame, and such encoded frame data is not polarity sensitive. As a non-limiting example, in Differential Manchester Encoded (DME) frames used in the 10SPE transmission scheme, the bits of the frame are encoded by state transitions in the signal, more specifically, the presence of a rising or falling edge in the signal. In general, whether a given state transition is a rising or falling edge does not affect the encoding of the DME frame, only the presence of such a transition. The inventors of the present disclosure understand that in some cases, it may be desirable for a PHY transceiver to selectively control the polarity of a frame.

[0026] As used herein, the term "polarity" when used with respect to a frame means the rising edge or falling edge of a transition of a bit of the frame, and the term "start polarity" when used with respect to a frame means the rising edge or falling edge of the first transition of the first bit of the frame, where the rising edge is defined as the first polarity and the falling edge is defined as the second polarity.

[0027] As a non-limiting example, the starting polarity of a frame (Ethernet or not) may affect electromagnetic emission (EME) in a given electronic system, and therefore actively transmitting frames with specific or randomly generated polarity patterns may be an effective strategy to minimize or control EME. The data (1s and 0s) in an Ethernet frame is typically encoded using a form of Manchester encoding (such as, but not limited to, DME), and the starting polarity of an Ethernet frame does not affect the Manchester encoded data.

[0028] As another non-limiting example, the PHY may support detection and / or diagnosis of cable faults on networks, including 10SPE networks, via time domain reflectometry, which may benefit from varying the starting polarity of the pulses generated for cable fault diagnosis. Cable fault diagnosis is necessary for many applications, such as vehicular communication networks that utilize 10SPE. Various types of cable faults can be detected and diagnosed, including cable "open" faults and cable "short" faults, as well as cable mismatch based on time domain reflection. Absence of cable faults can also be detected via time domain reflection (TDR).

[0029] For cable fault diagnosis, a pulse is transmitted from a PHY, and if a reflection is detected at the PHY, it may be determined that a cable fault exists. Furthermore, based on the detected reflection (e.g., phase and / or orientation (positive or negative)), a type of cable fault may be determined. For example, if the detected reflection includes a shape similar to that of the transmitted pulse, it may be determined that an "open" fault exists. If the detected reflection includes a shape similar to that of the transmitted pulse but an opposite shape, it may be determined that a "short" fault exists. Furthermore, if the detected reflection includes an amplitude different from that of the transmitted pulse, it may be determined that a "mismatch" fault exists. More specifically, if the detected reflection includes a shape similar to that of the transmitted pulse and the reflected and transmitted pulse have different amplitudes, it may be determined that an "open mismatch" fault exists. Furthermore, if the detected reflection includes a shape similar to that of the transmitted pulse but an opposite shape, it may be determined that a "short mismatch" fault exists.

[0030] To identify the type of cable fault, the PHY generates a first short frame (i.e., a pulse) with a first starting polarity and then generates a second short frame with a second starting polarity opposite to that of the first short frame. The information in the reflected frame can be used to identify the type of cable fault. However, in a split configuration such as that shown by FIG. 1, the control logic for cable fault diagnosis is typically in a PHY controller (e.g., PHY controller 404), which can command the transmit circuitry of the PHY to generate a pulse and then observe the reflection, but conventional PHY controllers known to the inventors cannot control or command the starting polarity of the pulses generated by the transmit circuitry of the PHY transceiver in such a split configuration.

[0031] One or more embodiments relate generally to controlling a starting polarity indicated by a frame generated by a PHY transceiver. The PHY transceiver may be, as a non-limiting example, a PHY transceiver of a PHY having a split configuration or another architecture. The PHY transceiver may be a transceiver provided at a 10SPE physical layer or another Ethernet physical layer. A signal conditioner of the PHY transceiver may include a polarity controller that selectively controls a starting polarity indicated by a transmitted frame. A signal generator provided to the polarity controller may control generation of a reference signal indicating a first or second state in response to a polarity setting in a polarity setting register. The reference signal may be provided to a transmitter that controls a starting polarity of a next transmission of a frame in response to a state of the reference signal. Configuration logic (config logic) of the PHY transceiver may be for setting a polarity setting in a polarity setting register. In some embodiments, the signal generator of the polarity controller may include logic for generating a reference signal according to a polarity rule, the logic being enabled in response to a polarity setting in the polarity setting register.

[0032] 1 is a block diagram illustrating a signal conditioner 130 of a PHY transceiver portion 100 for transmitting a frame indicating a predetermined starting polarity, according to one or more embodiments. The signal conditioner 130 includes a transmitter 120 and a polarity controller 126. The transmitter 120 is generally configured to initiate transmission of a frame on a shared transmission medium in response to a frame command 124 (e.g., received from a PHY controller) and a reference signal 114 generated by the polarity controller 126. The transmitter 120 includes a driver controller 110 that generates control signals for a driver 104 in response to a state of the reference signal 114. The driver 104 (e.g., a voltage signal driver) generates differential signals at pins TRXP 106 and TRXN 108 in response to the control signals provided by the driver controller 110 and the frame command 124, thereby generating the state transitions indicated. A state transition may be generated at pins TRXP106 and TRXN108, and thus at a shared transmission medium (e.g., transmission medium 414) coupled to the differential pins, by, as a non-limiting example, applying a first voltage signal of 0V to one of TRXP106 and TRXN108 and applying a second, higher voltage signal to the other of TRXP106 and TRXN108, and then switching the respective pins to which the first and second voltage signals are applied.

[0033] The starting polarity indicated by a frame generated by such a signal is controllable in response to the state of the reference signal 114. The polarity controller 126 generally generates the reference signal 114 to indicate a predetermined state such that the voltage signals driven at the differential pins TRXP 106 and TRXN 108 by the driver 104 in response to the reference signal indicate the predetermined starting polarity.

[0034] The reference signal 114 is generated by a signal generator 102 of the polarity controller 126. The signal generator 102 generally generates the reference signal 114 at least partially in response to internal signal generation logic (e.g., one of the logic modules 134 sets an initial polarity by setting a state of the reference signal 114 in response to a value in the polarity setting register 112, i.e., in response to the polarity setting 116) and a polarity setting 116 available in the polarity setting register 112 of the polarity controller 126. The polarity setting 116 may be available in the polarity setting register 112 having a value responsive to a polarity setting instruction 118 provided by a processor 132 (executing config firmware 122) in response to a configuration command 128 from a PHY controller (PHY controller not shown). In operation as contemplated with reference to Figures 1 and 1, when a configuration command 128 from the PHY controller is received in the PHY transceiver portion 100, the internal state machine transitions to a configuration state ("CONFIG" in Figure 1), and the PHY transceiver portion 100 waits and executes the configuration command until it is commanded to reset, at which point the internal state machine transitions to a normal state ("NORMAL").

[0035] In one or more embodiments, processor 132 may enable rules for the starting polarity of frames (e.g., by executing config firmware 122). Non-limiting examples of starting polarity rules include transmission of each and every frame with the same starting polarity, alternating starting polarity of each and every nth frame (e.g., but not limited to, for cable fault detection or EME mitigation), and random starting polarity for each and every frame (e.g., but not limited to, for EME mitigation).

[0036] As a non-limiting example of a contemplated operation, if the PHY performs cable fault diagnosis, the configuration command 128 includes instructions to alternate the starting polarity of the generated frames, because during cable fault diagnosis, reflections based on test pulses with different polarities will reveal more about the condition of the cable than if each and every pulse had the same starting polarity. The frame instructions 124 may include instructions to transmit a "short" frame (e.g., but not limited to, exhibiting a waveform characteristically similar to a pulse train). The processor 132 executing the config firmware 122 programs the polarity setting register 112 so that the polarity setting 116 initializes one of the logic modules 134 in the polarity controller 126 to alternate starting polarity every Nth frame. When the driver controller 110 controls the driver 104 to generate a set of short frames, it controls the driver 104 to generate a short frame exhibiting a first starting polarity in response to the state of the reference signal 114. The signal generator 102 may automatically change the starting polarity for subsequent frames to a second starting polarity by changing the state of the reference signal 114. When the driver controller 110 controls the driver 104 to generate a second set of short frames, it does so with the short frames indicating the second starting polarity in response to the changed state of the reference signal 114. In case of cable fault diagnosis, reflections, if any, are captured by an optional signal detector (not shown) and sent via a valid signal indication to an ED pin of a digital interface coupled to the PHY controller.

[0037] As a non-limiting example of another contemplated operation, the PHY may transmit Manchester encoded frames with a random starting polarity to attempt to reduce electromagnetic emissions (EME) generated by the transmission or the impact of other EME on the transmission. In this embodiment, the configuration command 128 includes instructions for the config firmware 122 to program the polarity setting register 112 to generate a polarity setting 116 that initializes one of the logic modules 134 in the polarity controller 126 to randomize the starting polarity of each frame. When the PHY transceiver transitions from the configuration state back to a normal state or a transmission state (XMITTING) and begins transmission, the starting polarity of each frame is random (including but not limited to true random or near random).

[0038] FIG. 2 is a flow chart illustrating a process 200 for controlling the starting polarity at which a PHY transceiver begins transmitting a frame, in accordance with one or more embodiments.

[0039] At operation 202, process 200 optionally enters a configuration state of the 10SPE PHY transceiver, and at operation 204, process 200 receives a first configuration command indicating a polarity setting that corresponds to a predetermined starting polarity for beginning transmission of the next frame (e.g., but not limited to, a 10SPE frame). In the configuration state, processor 132 (executing config firmware 122) of the 10SPE PHY transceiver may receive configuration command 228 that includes the polarity setting and program polarity setting register 212 accordingly.

[0040] In operation 206, process 200 configures a state of the reference signal at least in part in response to a predetermined starting polarity to be a first state or a second state, the first state corresponding to a first starting polarity when commencing transmission of the frame, and the second state corresponding to a second starting polarity when commencing transmission of the frame.

[0041] In operation 208, the process 200 generates a reference signal indicative of the configured state. The reference signal may be the reference signal 114 for the driver controller 210 that controls the driver 204 to generate a differential signal for the DME encoded frame.

[0042] In operation 210, process 200 configures the transmitter (e.g., transmitter 120) to begin a next transmission of a frame (e.g., a 10 SPE frame) indicating a predetermined starting polarity, at least in part by providing a reference signal to the transmitter (e.g., transmitter 120) indicating the configured state.

[0043] At operation 212, process 200 initiates transmission of a next frame (e.g., without limitation, a 10 SPE frame) exhibiting a predetermined starting polarity. Initiating transmission of the next frame exhibiting a predetermined starting polarity may include applying a first voltage signal to the first pin and applying a second voltage signal to the second pin, changing a voltage level indicated by the first voltage signal from a first level to a second level, and substantially simultaneously changing a voltage level indicated by the second voltage signal from the second level to the first level. The first level and the second level may correspond to a first starting polarity at least partially responsive to a reference signal indicative of a first state, or the first level and the second level may correspond to a second starting polarity at least partially responsive to a reference signal indicative of a second state.

[0044] 3 is a flow diagram illustrating a process 300 for controlling the starting polarity with which a PHY transceiver begins transmission of a frame, according to one or more embodiments. As discussed above, in some embodiments, logic module 134 in polarity controller 126 may be initialized by processor 132 executing config firmware 122 in response to configuration commands 128 indicating a rule for the starting polarity with which to begin transmission of one or more frames. Non-limiting examples of the rule include a random starting polarity, alternating starting polarity every nth frame, and the same starting polarity for each and every frame.

[0045] At operation 302, process 300 enters a configuration mode of the 10SPE PHY transceiver (e.g., as in the state diagram illustrated by FIG. 2 ). In the configuration mode, polarity setting register 212 can be read (e.g., via the RX / ED pin) and / or programmed (e.g., via the TX pin) by the PHY controller via processor 132 executing config firmware 122 in response to configuration command 128.

[0046] In operation 304, the process 300 receives a configuration command indicating a rule for the starting polarity with which the transmitter begins transmitting frames. Non-limiting examples of the rule include: all frames start with a first starting polarity (e.g., positive or negative); alternating, i.e., changing the starting polarity every Nth frame; randomly choosing the first or second starting polarity for a sequence of frames.

[0047] In operation 306, the process 300 initializes one of the logic modules 134 of the signal generator 102 corresponding to the rule indicated by the configuration command. The logic module 134 may comprise combinatorial logic or other basic logic circuitry for performing signal generation of the reference signal 114 according to one or more rules, including the rule indicated by the configuration command. As a non-limiting example, the logic module 134 may set the state of the reference signal 114 such that each and every frame exhibits the same starting polarity, the starting polarity changes every nth frame, or the starting polarity of each frame is randomized while the polarity setting 116 is exhibiting the associated state. The processor 132 may initialize one of the logic modules 134 by setting a value in the polarity setting register 112.

[0048] In operation 308, the process 300 enters a normal state for the 10SPE PHY transceiver to perform a frame transmission.

[0049] In operation 310, the process 300 begins transmission of each of one or more frames, each of which indicates a starting polarity according to the rule.

[0050] Example of a split PHY architecture Those skilled in the art will appreciate that controlling the starting polarity of 10SPE frames in a physical layer transceiver may be desirable in other PHY architectures (e.g., other than split configurations) and for frames in other transmission schemes (e.g., other than 10SPE) and bit-level encoding processes (e.g., other than DME) where the data is not polarity sensitive. Examples of starting polarity control may find particular application in PHY transceivers of PHYs with split configurations. Use of the disclosed polarity controller in architectures other than PHYs with split configurations is specifically contemplated by, and does not go beyond, the scope of this disclosure.

[0051] PHYs can be designed and / or manufactured with high voltage temperature processes, but such processes may not be suitable (e.g., without limitation, may be damaged or may be too expensive to test) for PHY designs having, by way of non-limiting example and without limitation, large and / or high speed digital blocks, random access memory (RAM), and / or one time programmable (OTP) memory. A non-limiting example of a high voltage temperature process is bulk current injection (BCI) susceptibility testing. During BCI and other high voltage temperature processes known to the inventors of the present disclosure, junction temperatures of approximately 175 degrees Celsius may be achieved.

[0052] One option to address some of these concerns is to simplify the digital design of the high voltage temperature process to meet timing requirements or fit into the die, but the design may not be suitable to simplify or meet such timing or die space requirements. The size of the die or package can be increased, but the size of the die and the size of the package are typically directly proportional to the overall processing cost, and the larger the die or package, the higher the processing cost.

[0053] The 10BASE-T1S Transceiver Interface Standard (hereinafter referred to as the "TC14 Standard"), currently under specification development by the OPEN Alliance's Technology Committee 14, defines a 3-pin hardware interface for a split (controller-transceiver) 10SPE PHY (split PHY).

[0054] 4 is a block diagram illustrating a system 400 including a split PHY 402 coupled to a transmission medium 414 by a bus network interface 412, according to one or more embodiments. The split PHY 402 includes a defined 3-pin hardware interface (hardware interface 408) currently specified by the TC14 standard. Generally speaking, a first portion of the split PHY (PHY controller 404) includes digital blocks that are susceptible to damage during high-voltage temperature processes and may be located on a first die that does not undergo high-voltage temperature processes. A second portion of the split PHY (PHY transceiver 406) includes analog and digital blocks that are not susceptible (individually or collectively) to high-voltage temperature processes and may be located on a second die that can undergo high-voltage temperature processes. The PHY transceiver 406 includes a signal conditioner 420 for transmitting a frame indicating a predetermined starting polarity, such as, but not limited to, the signal conditioner 130.

[0055] The hardware interface 408 includes three connections for signaling between the PHY transceiver 406 and the PHY controller 404: a TX connection 416, a RX connection 418, and an ED connection 410. The three connections are typically implemented through respective pins attached to respective integrated circuits of the split PHY, and thus each of the three connections is associated with a respective pin of the PHY transceiver 406 and the PHY controller 404. The TC14 standard currently specifies the use of these connections, some of which are associated with specific states of the PHY transceiver. In normal conditions, the TX connection 416 is used to carry transmission frames from the PHY controller 404 to the PHY transceiver 406, the RX connection 418 is used to carry received frames from the PHY transceiver 406 to the PHY controller 404, and the ED connection 410 is used to identify a valid signal from the PHY transceiver 406 to the PHY controller 404. The TC14 standard currently specifies that the RX connection 418 is the transceiver's comparator output indicating whether the signal is above or below a threshold, the ED connection 410 is the transceiver's signal detector output indicating inside or outside the threshold (i.e., indicating in-band and out-of-band signals), and TX is the transceiver's clockless, stateful input.

[0056] A split PHY can enable more efficient power consumption: some portions of the split PHY can go into a low power or "sleep" mode to conserve power consumption by the split PHY, while other portions of the split PHY (such as, but not limited to, transceivers or other hardware mounted elements) powered by an uninterruptible power supply can perform at least some functions of the split PHY while the entire split PHY is in the low power mode.

[0057] In some cases, it may be desirable to locate certain functions or operations in portions of a split PHY that are within the uninterrupted power domain so that they can operate to some degree while in a low power mode. By way of non-limiting examples, these may be functions associated with low power or wake detection of a split PHY, a node, a network segment, or a network, or functions associated with fault detection of the physical transmission medium ("cable fault detection").

[0058] As described above, in a typical split PHY, the first and second portions of the split PHY are coupled by a hardware interface of three wired connections. Each such first and second portion of the split PHY can include interface logic configured to associate individual pins with specific signals of the hardware interface and handle communication and signal propagation through the connections of the hardware interface. Any suitable number of pins and connections can be used to implement the hardware interface of the split PHY. Furthermore, a designer can take communication through such hardware interfaces into consideration when selecting where to locate digital blocks for implementing the features and functions of the split PHY architecture.

[0059] Notwithstanding these and other implementation challenges, a split PHY architecture can enable the split PHY (and systems and devices incorporating it, such as, without limitation, network switches, bridges, and endpoints) to be more digitally intensive and more power efficient than some single PHY architectures, allowing designers to take these aspects into consideration.

[0060] Those skilled in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein may be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 5 illustrates a non-limiting example of an implementation of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0061] FIG. 5 is a block diagram of a circuit 500 that, in some embodiments, may be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. The circuit 500 includes one or more processors (sometimes referred to herein as “processor 502”) operably coupled to one or more data storage devices (sometimes referred to herein as “storage device 504”). The storage device 504 includes machine-executable code 506 stored therein, and the processor 502 includes logic circuitry 508. The machine-executable code 506 includes information that describes functional elements that may be implemented (e.g., executed) by the logic circuitry 508. The logic circuitry 508 is adapted to implement (e.g., execute) the functional elements described by the machine-executable code 506. The circuitry 500, when executing the functional elements described by the machine-executable code 506, should be considered as dedicated hardware configured to execute the functional elements disclosed herein. In some embodiments, processor 502 may be configured to execute the functional elements described by machine-executable code 506 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0062] When implemented by the logic circuitry 508 of the processor 502, the machine executable code 506 is configured to adapt the processor 502 to perform operations of embodiments disclosed herein. For example, the machine executable code 506 may be configured to adapt the processor 502 to perform at least a portion or all of the blocks and processes illustrated in FIGS. 1-4. As another example, the machine executable code 506 may be configured to adapt the processor 502 to perform at least a portion or all of the operations discussed for one or more of the PHY transceivers or split PHY transceivers discussed herein. As another example, the machine executable code 506 may be configured to adapt the processor 132 to perform at least a portion or all of the operations discussed for one or more of the polarity controller 126, the polarity setting register 112, the signal generator 102, the logic module 134, the transmitter 120, the driver controller 110, the driver 104, and the processor 502.

[0063] As a specific, non-limiting example, the machine executable code 506 may be configured to adapt the processor 502 to perform some or all of the signal conditioning or polarity control discussed herein.

[0064] The processor 502 may include a general purpose processor, a special purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general purpose computer including a processor is considered a special purpose computer, while at the same time, the general purpose computer is configured to execute functional elements corresponding to the machine executable code 506 (e.g., software code, firmware code, hardware description) related to the embodiments of the present disclosure. It should be noted that the general purpose processor (sometimes referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, the processor 502 may include any conventional processor, controller, microcontroller, or state machine. The processor 502 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration.

[0065] In some embodiments, the memory 504 includes a volatile data storage device (e.g., random access memory (RAM)), a non-volatile data storage device (e.g., flash memory, a hard disk drive, a solid state drive, an erasable programmable read-only memory (EPROM), etc.). In some embodiments, the processor 502 and the memory 504 may be implemented in a single device (e.g., without limitation, a semiconductor device product, a system-on-chip (SOC), or a system-based chip). In some embodiments, the processor 502 and the memory 504 may be implemented in separate devices.

[0066] In some embodiments, machine-executable code 506 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by memory 504, accessed directly by processor 502, and executed by processor 502 using at least logic circuitry 508. As another non-limiting example, the computer-readable instructions may be stored in memory 504, transferred to a memory device (not shown) for execution, and executed by processor 502 using at least logic circuitry 508. Thus, in some embodiments, logic circuitry 508 includes electrically configurable logic circuitry 508.

[0067] In some embodiments, the machine-executable code 506 may describe hardware (e.g., circuits) to be implemented in logic circuitry 508 to perform the functional elements. This hardware may be described at any of a variety of levels of abstraction ranging from low-level transistor layouts to high-level description languages. At the high level of abstraction, a hardware description language (HDL) such as the IEEE Standard hardware description language (HDL) may be used. As non-limiting examples, Verilog™, SystemVerilog™, or very large scale integration (VLSI) hardware description language (VHDL™) may be used.

[0068] The HDL description may be converted into a description at any of a number of other levels of abstraction. As a non-limiting example, the high-level description may be converted into a logic-level description, such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by the hardware logic circuits (e.g., but not limited to, gates, flip-flops, registers) of logic circuit 508 may be described in RTL and then converted by a synthesis tool into a GL description, which may be converted by a place-and-route tool into a layout-level description that corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Thus, in some embodiments, machine-executable code 506 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0069] In embodiments in which machine-executable code 506 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 504) may be configured to implement the hardware description described by machine-executable code 506. As a non-limiting example, processor 502 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 508 may be electronically controlled to implement circuitry in logic circuitry 508 that corresponds to the hardware description. Also, as a non-limiting example, logic circuitry 508 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage 504) according to the hardware description in machine-executable code 506.

[0070] Regardless of whether machine-executable code 506 includes computer-readable instructions or a hardware description, logic circuitry 508, when implementing the functional elements of machine-executable code 506, is adapted to perform the functional elements described by machine-executable code 506. It should be noted that the hardware description may not directly describe the functional elements, but rather the hardware description indirectly describes functional elements that the hardware elements described by the hardware description are capable of performing.

[0071] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including, but not limited to," etc.).

[0072] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, such intent does not exist. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as limiting any particular claim that includes such introduced claim recitation to embodiments that include only one such recitation, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "one(a)" or "one(an)" (e.g., "one(a)" and / or "one(an)" should be construed to mean "at least one" or "one or more"). The same applies to the use of express articles used to introduce claim recitations.

[0073] In addition, even if a particular number of an introduced claim recitation is explicitly recited, one of ordinary skill in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other qualifiers means at least two recitations, i.e., two or more recitations). Furthermore, when a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, it is generally intended that such a structure include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0074] Additionally, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B." As used herein, "each" means a part or a whole. As used herein, "each and all" means the whole.

[0075] Characterizations such as "typical," "conventional," or "known" herein do not necessarily mean that the discussed aspect is disclosed in the prior art or that it is recognized in the prior art. Nor do they necessarily mean that it is widely known, well understood, or routinely used in the relevant field. Such characterizations should be understood to mean "known to the inventors of the present disclosure."

[0076] Further non-limiting examples of the present disclosure are as follows.

[0077] Example 1: A signal conditioner for a 10SPE physical layer transceiver, comprising: a transmitter for transmitting a 10SPE frame; and a polarity controller for controlling the transmitter to start transmitting a next frame indicating a predetermined starting polarity.

[0078] Example 2: The signal conditioner of example 1, wherein the transmitter is configured to generate a differential Manchester-encoded signal corresponding to a next frame, and an initial state transition indicated by the differential Manchester-encoded signal is at least partially responsive to a configured state of a reference signal.

[0079] Example 3: A signal conditioner described in any one of Examples 1 and 2, wherein the polarity controller comprises a polarity setting register and a signal generator configured to generate a reference signal indicating a configured state in response to a value of the polarity setting register.

[0080] Example 4: The signal conditioner of any one of Examples 1-3, wherein the polarity setting register is programmable by the 10SPE physical layer controller.

[0081] Example 5: A signal conditioner as described in any one of Examples 1 to 4, wherein the transmitter is configured to apply a first voltage signal to the first pin, apply a second voltage signal to the second pin, change a voltage level indicated by the first voltage signal from a first level to a second level, and change a voltage level indicated by the second voltage signal from the second level to the first level.

[0082] Example 6: A signal conditioner described in any one of Examples 1 to 4, wherein each value of the first level and the second level corresponds to a first starting polarity that is at least partially responsive to a reference signal indicating a first state, and each value of the first level and the second level corresponds to a second starting polarity that is at least partially responsive to a reference signal indicating a second state.

[0083] Example 7: A method for transmitting a 10SPE frame, the method including: receiving a polarity setting corresponding to a predetermined starting polarity for starting transmission of the 10SPE frame; configuring a transmitter to start transmission of the next 10SPE frame with the predetermined starting polarity; and starting transmission of the next 10SPE frame indicating the predetermined starting polarity.

[0084] Example 8: The method described in Example 7, wherein the step of configuring the transmitter to start transmission of the next 10SPE frame with a predetermined starting polarity includes a step of configuring the transmitter to start transmission of the next 10SPE frame with a predetermined starting polarity in response to a state of the reference signal.

[0085] Example 9: The method of any one of Examples 7 and 8, comprising configuring a state of the reference signal to be in a first state or in a second state.

[0086] Example 10: The method according to any one of Examples 7 to 9, comprising generating a reference signal indicative of the configured state.

[0087] Example 11: The method according to any one of Examples 7 to 10, comprising providing a reference signal indicative of the configured state to the transmitter.

[0088] Example 12: A method according to any one of Examples 7 to 11, wherein the step of initiating transmission of the next 10SPE frame indicating a predetermined starting polarity includes the steps of applying a first voltage signal to a first pin, applying a second voltage signal to a second pin, changing the voltage level indicated by the first voltage signal from the first level to a second level, and changing the voltage level indicated by the second voltage signal from the second level to the first level.

[0089] Example 13: A method according to any one of Examples 7 to 12, wherein the first level and the second level correspond to a first starting polarity that is at least partially responsive to a reference signal indicating a first state, or the first level and the second level correspond to a second starting polarity that is at least partially responsive to a reference signal indicating a second state.

[0090] Example 14: A system comprising a signal conditioner configured to generate an Ethernet frame, a processor and configuration firmware, the configuration firmware being configured, when executed by the processor, to enable the processor to initialize a logical module of the signal conditioner corresponding to a starting polarity rule for initiating transmission of the Ethernet frame.

[0091] Example 15: The system of example 14, wherein the rule for the starting polarity at which to start transmission of an Ethernet frame is a random starting polarity.

[0092] Example 16: A system according to any one of Examples 14 and 15, wherein the rule for the starting polarity at which transmission of an Ethernet frame is started is alternating starting polarity every Nth frame.

[0093] Example 17: The system according to any one of Examples 14 to 16, wherein the rule for the start polarity for starting transmission of an Ethernet frame is that the start polarity is the same for all frames.

[0094] Example 18: A system described in any one of Examples 14 to 17, wherein the configuration firmware, when executed by the processor, is configured to enable the processor to receive a command indicating a rule and initialize a logic module of the signal conditioner at least in part in response to the command.

[0095] While the present disclosure has been described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and appreciate that the present invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below along with their legal equivalents. In addition, features of one embodiment can be combined with features of other disclosed embodiments as contemplated by the inventors and still fall within the scope of the present disclosure.

Claims

1. 1. A signal conditioner for a 10SPE physical layer transceiver, comprising: a transmitter for transmitting 10 SPE frames; a polarity controller for controlling the transmitter to begin transmission of a next frame exhibiting a predetermined starting polarity.

2. 2. The signal conditioner of claim 1, wherein the transmitter generates a differential Manchester-encoded signal corresponding to the next frame, and an initial state transition indicated by the differential Manchester-encoded signal is responsive at least in part to a configured state of a reference signal.

3. The polarity controller comprises: A polarity setting register; 3. The signal conditioner of claim 2, further comprising: a signal generator responsive to a value of the polarity setting register to generate the reference signal indicative of the configured state.

4. 4. The signal conditioner of claim 3, wherein the polarity setting register is programmable by a 10SPE physical layer controller.

5. The transmitter comprises: applying a first voltage signal to a first pin; applying a second voltage signal to the second pin; changing a voltage level indicated by the first voltage signal from a first level to a second level; 3. The signal conditioner of claim 2, wherein the signal conditioner changes a voltage level indicated by the second voltage signal from the second level to the first level.

6. a value of each of the first level and the second level corresponds to a first starting polarity at least partially responsive to the reference signal indicating a first state; 6. The signal conditioner of claim 5, wherein the respective values ​​of the first level and the second level correspond to a second starting polarity at least partially responsive to the reference signal indicating a second state.

7. 1. A method for transmitting a 10 SPE frame, the method comprising: receiving a polarity setting corresponding to a predetermined starting polarity for initiating transmission of a 10 SPE frame; configuring the transmitter to begin transmission of the next 10 SPE frame with said predetermined starting polarity; and commencing the transmission of the next 10 SPE frame indicating the predetermined starting polarity.

8. The step of configuring the transmitter to begin the transmission of the next 10 SPE frame with the predetermined starting polarity comprises:

8. The method of claim 7, further comprising the step of configuring said transmitter to commence said transmission of said next 10 SPE frame at said predetermined starting polarity in response to a state of a reference signal.

9. The method of claim 8 , comprising configuring the state of the reference signal to be a first state or a second state.

10. The method of claim 8 , further comprising generating the reference signal indicative of a configured state.

11. The method of claim 10, comprising providing the reference signal indicative of the configured state to the transmitter.

12. The step of initiating the transmission of the next 10 SPE frame indicating the predetermined starting polarity comprises: applying a first voltage signal to a first pin; applying a second voltage signal to a second pin; changing a voltage level indicated by the first voltage signal from a first level to a second level; and changing a voltage level indicated by the second voltage signal from the second level to the first level.

13. 13. The method of claim 12, wherein the first level and the second level correspond to a first starting polarity at least partially responsive to the reference signal indicating a first state, or the first level and the second level correspond to a second starting polarity at least partially responsive to the reference signal indicating a second state.

14. 1. A system comprising: a signal conditioner that generates Ethernet frames; A system comprising: a processor; and configuration firmware, which, when executed by the processor, enables the processor to initialize logic modules of the signal conditioner corresponding to a starting polarity rule for initiating transmission of the Ethernet frame.

15. The system of claim 14 , wherein the rule for the starting polarity at which to begin transmission of the Ethernet frame is a random starting polarity.

16. 15. The system of claim 14, wherein the rule for the starting polarity at which to begin transmission of the Ethernet frames is alternating starting polarity every Nth frame.

17. 15. The system of claim 14, wherein the rule for the starting polarity at which to begin transmission of the Ethernet frames is the same starting polarity for all frames.

18. 15. The system of claim 14, wherein the configuration firmware, when executed by the processor, enables the processor to receive commands indicative of the rules and initialize the logic modules of the signal conditioner at least in part in response to the commands.

19. 15. The system of claim 14, wherein the signal conditioner is provided in a physical layer transceiver of a physical layer module (PHY) having a split PHY configuration.

20. 15. The system of claim 14, wherein the signal conditioner is provided in a physical layer transceiver of a physical layer module (PHY) having a combined controller-transceiver configuration.

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