Encoding a byte of information on a data bus

Abstract

Data may be communicated from a sending device to a receiving device via enabled or selected byte positions or other data bit groups of the data bus. The sending device may determine the data values ​​to be sent over the data bus and may determine which byte positions are enabled or selected and which are not. The sending device may also determine a code. The code may be a value that is not included in the data values ​​sent over the data bus. The sending device may then send the selected data values ​​in selected byte positions of the data bus and send the code in unselected byte positions of the data bus. The sending device may also send the code to the receiving device separately from the data bit lanes of the data bus.

Description

[Technical field]

[0001] 2. Description of Related Art

[0001] A computing device may include multiple subsystems, cores, or other components. Such a computing device may be, for example, a portable computing device ("PCD"), such as a laptop or palmtop computer, a cellular telephone or smartphone, a portable digital assistant, a portable game console, etc.

[0002]

[0002] Multiple subsystems, cores, or other components of a computing device may be included within the same integrated circuit chip or on different chips. A "system-on-a-chip" or "system-on-a-chip, SoC" is an example of one such chip that integrates multiple components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as central processing units ("CPUs"), graphics processing units ("GPUs"), digital signal processors ("DSPs"), and neural processing units ("NPUs"). An SoC may include other processing subsystems, such as a transceiver or "modem" subsystem that provides wireless connectivity, a memory subsystem, and the like.

[0003]

[0003] Various subsystems can communicate with each other via a data bus. The data bus may be serial or parallel. A parallel data bus comprises multiple signal lines, also called bits, lanes, etc. The number of data bus lanes may be referred to as the data bus width. A memory bus is a common example of a parallel data bus. A wider data bus may help increase bandwidth, but some drawbacks of a wider data bus may include more chip area occupied by data bus lanes, increased power consumption, tighter timing margins, etc.

[0004]

[0004] Some types of memory devices can be configured for different data widths depending on the application or data requirements. A feature of some systems with memory configurable for different data widths is the ability to selectively write only a portion or subset of the widest data width. A technique known as "byte enable" allows selected bytes to be written within a wider data width block. For example, for a 32-bit width (i.e., 4 bytes), only the least significant byte can be selected to be written instead of the entire 4 bytes. A byte-enable ("BE") bit can be communicated from a transmitting subsystem to a receiving subsystem along with a corresponding data byte. A transmitting device (e.g., a processor) can selectively transmit data on all bytes or only a subset of the data bus. A transmitting device can use the BE bit to indicate selected or enabled byte positions on the data bus. Based on the BE bit, a receiving device can process only data received in enabled byte positions on the data bus and ignore (i.e., not process) data received in non-enabled byte positions on the data bus. For example, a memory can write only data bytes that indicate the BE bit is enabled.

[0005]

[0005] In a data bus scheme where there is one BE bit for each data byte, the wider the byte-wise data bus, the more lanes are reserved for BE bits rather than for data. It is desirable to provide a BE feature that increases the efficient use of lanes for data. Summary of the Invention

[0006]

[0006] Systems, methods, computer-readable media, and other examples are disclosed for communicating data from a sending device to a receiving device over a data bus using selected byte positions or other groups of data bits.

[0007]

[0007] An exemplary method for data communication over a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit lanes. The method may include determining, by a transmitting device, a set of selected data values ​​to be transmitted over the data bus. The method may also include determining, by the transmitting device, selected data bit groups and unselected data bit groups. The method may further include determining, by the transmitting device, a code representing an unselected data value not included in the set of selected data values. The method may further include transmitting, to a receiving device over the data bit lanes, the selected data values ​​in the selected data bit groups and the code in the unselected data bit groups. The method may further include transmitting the code to the receiving device separately from the data bit lanes.

[0008]

[0008] An exemplary system for data communication over a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit lanes. The exemplary system may include an encoder and a data word formatter. The encoder may be configured to determine a set of selected data values ​​to be transmitted over the data bus. The data word formatter may be configured to determine selected data bit groups and unselected data bit groups. The data word formatter may also be configured to determine codes representing unselected data values ​​not included in the set of selected data values. The data word formatter may be further configured to provide a data word having selected data values ​​in the selected data bit groups and codes in the unselected data bit groups to a receiving device over the data bit lanes. The data word formatter may be further configured to provide codes to the receiving device over a plurality of code bit lanes separate from the data bit lanes.

[0009]

[0009] Another exemplary system for data communication over a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit lanes. The system may include means for determining a set of selected data values ​​to be transmitted over the data bus. The system may also include means for determining selected data bit groups and unselected data bit groups. The system may further include means for determining a code representing an unselected data value not included in the set of selected data values. The system may further include means for transmitting the selected data value in the selected data bit group and the code in the unselected data bit group to a receiving device over the data bit lanes. The system may further include means for transmitting the code to the receiving device separately from the data bit lanes.

[0010]

[0010] An exemplary computer-readable medium for data communication over a data bus may be provided. The data bus may have a plurality of data bit groups. Each data bit group may have a plurality of data bit lanes. The computer-readable medium may comprise a non-transitory computer-readable medium having instructions stored thereon in a computer-executable form. The instructions, when executed by a processing system of a computing device, may configure the processing system to control: determining a set of selected data values ​​to be transmitted over the data bus; the instructions may also configure the processing system to control determining selected data bit groups and unselected data bit groups; the instructions may further configure the processing system to control determining a code representing an unselected data value not included in the set of selected data values; the instructions may further configure the processing system to control transmitting the selected data values ​​in the selected data bit groups and the code in the unselected data bit groups to a receiving device over the data bit lanes; the instructions may further configure the processing system to control transmitting the code to the receiving device separately from the data bit lanes. [Brief description of the drawings]

[0011]

[0011] In the figures, similar reference symbols refer to similar parts throughout the various figures unless otherwise indicated. In the case of a reference symbol accompanied by a letter designation such as "102A" or "102B", the letter designation may distinguish between two similar parts or elements present in the same figure. When the reference symbol is intended to encompass all parts having the same reference symbol in all figures, the letter designation for the reference symbol may be omitted. [Figure 1]

[0012] 1 is a block diagram illustrating a system for communicating data between a sending device and a receiving device over a data bus according to an exemplary embodiment. [Diagram 2]

[0013] 2 is a data diagram illustrating an example data word configuration in which the system of FIG. 1 may operate, according to an example embodiment. [Diagram 3]

[0014] 1 is a flow diagram illustrating an exemplary method for communicating data between a sending device and a receiving device over a data bus, according to an exemplary embodiment. [Figure 4]

[0015] 1 is a block diagram illustrating a portion of a device configured to transmit or transmit data over a data bus according to an example embodiment. [Diagram 5]

[0016] 5 is a data diagram illustrating an example of the operation of the transmitting device of FIG. 4. [Figure 6]

[0017] FIG. 2 is a block diagram illustrating a portion of a device configured to receive data over a data bus in accordance with an exemplary embodiment. [Figure 7]

[0018] 4 is a flow diagram illustrating an example method for receiving data over a data bus in accordance with an example embodiment. [Figure 8]

[0019] FIG. 2 is a block diagram illustrating another system for communicating data between a sending device and a receiving device over a data bus in accordance with an exemplary embodiment. [Figure 9]

[0020] FIG. 1 is a block diagram of a computing device in accordance with an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0021] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "illustrative" may be used herein as a synonym for "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0013]

[0022] As shown in FIG. 1, the system 100 may include a transmitting device 102 and a receiving device 104. The transmitting device 102 and the receiving device 104 may be included on a system-on-chip or "SoC" 106. That is, the transmitting device 102 and the receiving device 104 may each comprise electronic circuitry on the SoC 106. In one example, the transmitting device 102 may comprise a processor or processing circuitry, and the receiving device 104 may comprise a memory device having a configurable data width. In this exemplary embodiment, the transmitting device 102 and the receiving device 104 are on the same SoC 106 as each other, but in other embodiments, such transmitting and receiving devices may be on separate chips. For example, the transmitting and receiving devices may be on separate "chiplets" within a package.

[0014]

[0023] A data bus 108 comprising a number ("N") of data bit lanes may interconnect the sending device 102 and the receiving device 104. Each data bit lane may be an electrical signal conductor or path, such as a metallization strip on the SoC 106. The data bus 108 may communicate N bits of information or data in parallel, with each data bit lane communicating one bit of data. The data bus 108 may have a width expressed in bits, bytes, or any other units. For purposes of this disclosure, the width of the data bus 108 may be expressed in units called "data bit groups," with each data bit group comprising two or more data bit lanes. In one example, each data bit group may consist of eight data bit lanes, i.e., one byte, and the data bus 108 may have a width of 256 bytes communicated across a total of N=2048 lanes (i.e., 256 bytes x 8 lanes per byte).

[0015]

[0024] In this example, each data bit group comprises 8 bits (i.e., one byte), but in other examples, each data bit group may include any number of bits greater than or equal to 2. The terms "sender" and "receiver" are used for illustrative purposes, and an exemplary direction of data communication is indicated by the arrows on the data bus 108 in FIG. 1, but it should be understood that the data bus 108 may be bidirectional in other examples. Also, the term "data bus" is used for convenience and should not be construed as limiting. For example, the data bus 108 may be a complex data interconnect, such as a type of data interconnect sometimes referred to as a network-on-chip or "network-on-a-chip, NoC," an interconnect "fabric," or the like. Although not shown in FIG. 1, a data bus according to the present disclosure may interconnect any number of different devices. Any such device that transmits data to another such device via the data bus may be a "sender" device as that term is used herein. Similarly, any such device that receives data from another such device via the data bus may be a "receiver" device as that term is used herein. In some examples, some devices may be bidirectional (i.e., transceivers), so that the transmitting device may be a bidirectional device configured in a mode for transmitting data, while the receiving device may be a bidirectional device configured in a mode for receiving data.

[0016]

[0025] In addition, several ("M") code bit lanes 110 may interconnect the sending device 102 and the receiving device 104. Similar to the above-described data bit lanes of the data bus 108, each code bit lane may be an electrical signal conductor or path, such as a metallization strip on the SoC 106. The code bit lanes 110 may communicate a code including M parallel code bits from the sending device 102 to the receiving device 104. The code may be the same data size as each data bit group. In an example where each data bit group consists of eight data bit lanes, the code may include eight bits (i.e., M=8 code bit lanes 110). Nevertheless, in other examples, the code may include any other number of bits consistent with the principles of operation described below. The code bit lanes 110 may be part of the same interconnect structure as the data bus 108, although the code bit lanes 110 and the data bus 108 are shown separately in FIG. 1 for clarity. Note that in the example shown in FIG. 1, at least N+M lanes interconnect or couple the transmitting device 102 and the receiving device 104 .

[0017]

[0026] As shown in FIG. 2, an exemplary data word structure 200 may consist of 256 bytes and correspondingly be communicated by a data bus 108 (FIG. 1) having N=2048 lanes (i.e., 256 bytes×8 lanes / byte). In the illustrated data word structure 200, the byte positions are examples of the aforementioned data bit groups of the data bus 108 (FIG. 1). Thus, in the example shown in FIG. 2, the data word structure 200 consists of a first byte position 202A (e.g., the least significant byte position), a second byte position 202B adjacent to the first byte position 202A, a third byte position 202C adjacent to the second byte position 202B, and so on up to a 256th byte position 202N (e.g., the most significant byte position). In the illustrated example, the first byte position 202A may include the first bit b0 of the data word, the second bit b1 of the data word, the third bit b2 of the data word, etc. through the eighth bit b7 of the data word, the second byte position 202B may include the ninth bit b8 of the data word through the sixteenth bit b15 of the data word, the third byte position 202C may include the seventeenth bit b16 of the data word through the twenty-fourth bit b23 of the data word, etc. through the 256th byte position 202N which may include the 2041st bit b2040 of the data word through the 2048th bit b2047 of the data word.

[0018]

[0027] In FIG. 3, a method 300 for communicating data over a data bus is shown. The data bus may be configured as described above with respect to FIGS. 1-2. That is, the data bus may include two or more data bit groups, such as two or more bytes, with each data bit group including two or more data bit lanes. The sending device may be configured to control some or all of the method 300. For example, in an embodiment in which the sending device includes a processor, the processor may be configured by software or firmware to control some or all of the method 300. Also, the sending device or a portion thereof (e.g., the processor) may be an example of a means for performing the functions described in the method 300. The method 300 may include the following features, functions, operations, etc., illustrated in blocks 302-310, which may be performed or otherwise performed in any order not inconsistent with the description herein. Although blocks 302-310 are described in an order that is helpful in understanding the exemplary method 300, the method for communicating data from the sending device to the receiving device over the data bus is not limited to that order.

[0019]

[0028] As indicated by block 302, method 300 may include determining a set of data values ​​(i.e., selected data values) to be transmitted over the data bus. For example, the transmitting device may obtain data from another source and arrange or organize the data values ​​for transmission to the receiving device. In some examples, the data values ​​transmitted to the receiving device may be the result of a calculation performed by the transmitting device. Referring again to the example illustrated in FIG. 2, each data value may be one byte, i.e., 8 bits. In such examples, the data values ​​may be in the range of 0 to 255. In some examples, the size of the set of selected data values ​​may be related to the size of a data word. For example, data values ​​up to 256 bytes may be selected to be transmitted over the data bus. In such examples, the transmitting device may determine or provide the selected data values ​​to be transmitted in the form of one 256-byte data word. In such examples, method 300 may be repeated any number of times to transmit any number of data words.

[0020]

[0029] As indicated by block 304, the method 300 may further include determining selected and unselected data bit groups. For example, the sending device may select which of the data bit groups to transmit selected data values ​​in and conversely, select which of the data bit groups not to transmit any selected data values ​​in. The sending device may select any or all of the data bit groups to collectively transmit the set of selected data values. Referring again to the example shown in FIG. 2, the sending device may select any of the byte positions 202A-202N to include data in a transfer or transmission operation from the sending device to the receiving device. The selected data bit groups (e.g., byte positions) may also be referred to as enabled data bit groups. In examples where the data bit groups are byte positions, the selected byte positions may also be referred to as enabled byte positions or enabled bytes. As described below, in some examples of the method 300, the sending device may generate a data structure, such as an array or vector of bits, that may indicate which data bit groups are selected (or enabled) and which data bit groups are not selected.

[0021]

[0030] As indicated by block 306, the method 300 may further include determining a code representing a non-selected data value. The code or non-selected data value may be any data value that is not included in the set of selected data values.

[0022]

[0031] As indicated by block 308, the method 300 may further include transmitting the selected data value in the selected data bit group and the code in the unselected data bit group to the receiving device via the data bit lane. In other words, in the transmitted data word, the selected data value is placed or included in the selected data bit group and the code is placed or included in the unselected data bit group. As indicated by block 310, the method 300 may also include transmitting the code to the receiving device separately from the data bit lane. For example, referring again to FIG. 1, the transmitting device 102 may transmit the code to the receiving device via the code bit lane 110.

[0023]

[0032] As shown in Figure 4, the system 400 may be configured to output a data word in which a selected data value is placed or included in selected data bit groups and a code is placed or included in non-selected data bit groups. The system 400 may be configured to output or provide the data word over a data bus (not shown in Figure 4). The system 400 may be an example of a portion of the transmitting device 102 (Figure 1) described above. The system 400 may comprise processor logic (e.g., programmed by software or firmware), discrete circuitry (e.g., finite state machines, combinatorial logic, etc.), or any combination thereof.

[0024]

[0033] The input data word 402 may include a set of selected data values ​​as described above at positions (e.g., byte positions) that correspond to selected data bit groups (e.g., selected byte positions). Positions in the input data word 402 that do not correspond to selected data bit groups, or conversely, that correspond to unselected data bit groups, may include any data value (i.e., logical "don't care" values). The input data word 402 may have a structure similar to the data word structure 200 (FIG. 2) described above. The input BE vector 404 may consist of an array or vector of bits that indicate which data bit groups in the input data word 402 are selected and which are not selected. The system 400 may maintain the input BE vector 404, for example, in the form of a data structure. In an example where the receiving device 104 (FIG. 1) is a memory having a bus with a configurable data width, the input BE vector 404 may indicate selected (i.e., enabled) memory bus bytes (e.g., by "1" bits) and unselected (i.e., not enabled) memory bus bytes (e.g., by "0" bits).

[0025]

[0034] The binary-to-unary encoder 406 may be configured to receive, obtain, or otherwise determine a set of selected data values ​​to be transmitted over the data bus. For example, the binary-to-unary encoder 406 may be configured to determine an input data word 402. Determining the input data word 402 may include, for example, receiving the input data word 402 from a data source, such as another portion of the transmitting device (not shown). The binary-to-unary encoder 406 may likewise receive, or possibly determine, an input BE vector 404. The binary-to-unary encoder 406, which may also be referred to as a two's complement encoder or converter, may also be configured to convert the input data word 402 into a bit vector of selected data values ​​408 using the input BE vector 404. As described below with respect to an example, the bit vector of selected data values ​​408 may include a "1" bit at each bit position where the bit position (i.e., numerical index) is equal to the selected data value and a "0" bit at each bit position where the bit position (i.e., numerical index) is not equal to the selected data value. As will be appreciated by those skilled in the art, the binary-to-unary encoder 406 may be implemented using a simple configuration of logic gates and conveniently provides a vectorized approach to indicating the selected data values ​​described herein. Nevertheless, the binary-to-unary encoder 406 is only one example of a circuit for determining a set of selected data values ​​to be transmitted over a data bus, and other approaches and examples may occur to those skilled in the art in view of the description herein.

[0026]

[0035] The data word formatter 410 may be configured to receive the input data word 402, the input BE vector 404, and the selected data value bit vector 408. The data word formatter 410 may be further configured to use the bit vector of the selected data value 408 to determine a code that represents an unselected data value. For example, the data formatter 410 may be configured to select bit positions in the bit vector of the selected data value 408 that contain a "0" bit. If there is more than one bit position that contains a "0" bit, the data formatter 410 may select any one of them.

[0027]

[0036] Data formatter 410 may also be configured to determine selected and unselected bytes or other groups of data bits. In the illustrated example, data formatter 410 may use input BE vector 404 to determine selected and unselected bytes.

[0028]

[0037] The data word formatter 410 may be further configured to provide an output data word to a receiving device (e.g., via the data bit lanes 108 described above with respect to FIG. 1). The output data word may include selected data values ​​in selected data bit groups and codes in unselected data bit groups. For example, the data word formatter 410 may place selected byte values ​​indicated in the input data word 402 into corresponding byte positions of the output data word and may place codes into remaining unselected byte positions of the output data word. The data word formatter 410 may also be configured to provide codes to the receiving device separately from the output data word (e.g., via the code bit lanes 110 described above with respect to FIG. 1).

[0029]

[0038] An example of the operation of the above-described system 400 is shown in Figure 5. In the illustrated example, a 256-bit input BE vector includes, among other bit values ​​(not all of which are shown for clarity), a "1" in bit position B255 (i.e., the most significant bit position) to indicate that the corresponding data bus byte position B255 is selected, a "1" in bit position b254 to indicate that the corresponding data bus byte position B254 is selected, a "0" in bit position b253 to indicate that the corresponding data bus byte position B253 is not selected, and a "1" in bit position b0 (i.e., the least significant bit position) to indicate that the corresponding data bus byte position B0 is selected. The exemplary BE vector may also include several other exemplary (or nth) bit positions "bn" that have a "0" to indicate that the corresponding data bus byte position Bn is not selected. The bit values ​​at bit positions b252 through b(n+1) and bit positions b(n-1) through b1 are not shown for clarity, but may similarly have a value of "1" indicating a selected data bus byte position or a "0" indicating an unselected data bus byte position.

[0030]

[0039] In the example shown in FIG. 5, the 256 byte input data word includes a data byte value of 252 in byte position B255 (i.e., the most significant byte position), a data byte value of 0 in byte position B254, and a data byte value of 2 in byte position B0 (i.e., the least significant byte position), among other data byte values ​​(not all of which are shown for clarity). The byte in byte position B253 can have any value, as indicated by the "don't care" symbol "X", since the input BE vector in this example indicates that data bus byte position B253 is not selected, as discussed above. Similarly, the byte in byte position Bn can have any value, as indicated by the "don't care" symbol "X", since the input BE vector in this example indicates that data bus byte position Bn is not selected, as discussed above. The data values ​​in byte positions B252 through B(n+1) and byte positions B(n-1) through B1 are not shown for clarity, but may have any value. Note that the data bit group in the illustrated example is one byte (ie, 8 bits), so each byte value can range from 0 to 255.

[0031]

[0040] In forming a bit vector of the selected data value in this example (FIG. 5), binary-to-unary encoder 406 (FIG. 4) may place a bit value of "1" in bit position B255, as indicated by arrow 502, because the data byte in selected data bus byte position b252 in the input data word has a value of 252, may place a bit value of "1" in bit position B254, as indicated by another arrow 504, because the data byte in selected data bus byte position B0 in the input data word has a value of 0, and may place a bit value of "1" in bit position b2, as indicated by another arrow 506, because the data byte in selected data bus byte position B0 in the input data word has a value of 2, among other bit values ​​(not all of which are shown for clarity). Although the data bytes in the input data word having data values ​​of 255 and 1 are not explicitly shown, the bit values ​​are similarly set to "1" in bit positions b255 and b1 of the selected data value bit vector in this example, as indicated by dashed arrows 508 and 510, respectively.

[0032]

[0041] It should be noted that the selected data value bit vector indicates by the presence of a "1" in a bit position that a data value equal to that bit position (numerical index) is in the set of selected data values, i.e., present in the input data word. For example, a "1" in bit position b255 indicates that a data value of 255 is present in the input data word, a "1" in bit position b252 indicates that a data value of 252 is present in the input data word, and so on. Similarly, the selected data value bit vector indicates by the presence of a "0" in a bit position that a data value equal to that bit position (numerical index) is not in the set of selected data values. For example, a "0" in bit position b254 indicates that a data value of 254 is not in the set of selected data values, a "0" in bit position b253 indicates that a data value of 253 is not in the set of selected data values, a "0" in bit position b3 indicates that a data value of 3 is not in the set of selected data values, and so on.

[0033]

[0042] In forming the output data word in this example (FIG. 5), data formatter 410 (FIG. 4) may first determine a code that represents an unused or unselected data value. To determine the code, data formatter 410 may determine which bit positions within the bit vector of the selected data value have a bit value of "0". In the example shown in FIG. 5, data formatter 410 may determine that bit positions b254, b253, b3 (and possibly other bits not shown) within the bit vector of the selected data value have a bit value of "0", and thus data values ​​of 254, 253, and 3 (and possibly other bits not shown) are not within the set of selected data values. In this example, data formatter 410 may select any of these unused data values, i.e., data values ​​that are not within the set of selected data values, to function as or represent a code. In the example shown, data formatter 410 selects unused data value 3. Nevertheless, data formatter 410 may instead select unused data value 253 or 254. A rule may be implemented for selecting an unused data value in instances where there are multiple unused data values, such as selecting the data value corresponding to the bit position closest to the least significant bit position.

[0034]

[0043] In forming the output data word in this example (FIG. 5), data formatter 410 may place a code, in this example a 3, in each unselected data bus byte location. Thus, data formatter 410 may place a byte value 3 in this example in data bus byte locations B253 and Bn, as indicated by arrows 512 and 514, respectively. Data formatter 410 may similarly place a byte value 3 in any other unselected data bus byte locations (not shown for clarity). Although arrow indicators are not shown for clarity, data formatter 410 may also place each selected data value, i.e., each data value present in the input word, in the same data bus byte location in the output data word where that data value was present in the input data word. Thus, data formatter 410 may place a data value 252 in data bus byte location B255 of the output data word, a data value 0 in data bus byte location B254 of the output data word, a data value 2 in data bus byte location B0 of the output data word, and so on. Data formatter 410 can similarly place other data values ​​(not shown for clarity) that may be present in the input data word into corresponding data bus byte locations in the output data word. Data formatter 410 can use the input BE vector to determine which data bus byte locations are selected and which are not selected.

[0035]

[0044] As shown in Figure 6, system 600 may be configured to receive a data word over a data bus (not shown). The data word may have the configuration of the output data word described above with respect to Figure 5. That is, in the data word, selected data values ​​are placed or included in selected data bus byte locations and codes are placed or included in unselected data bus byte locations. System 600 may be an example of a portion of receiving device 104 (Figure 1) described above. System 600 may comprise processor logic (e.g., programmed by software or firmware), discrete circuitry (e.g., finite state machines, combinatorial logic, etc.), or any combination thereof.

[0036]

[0045] The system 600 may include comparison logic 601. The comparison logic 601 may include a number of bit group (e.g., byte) comparators 602 equal to the number of data bus bit group (e.g., byte) positions. For example, a system 600 having 256 data bus byte positions may include 256 comparators 602 (not all of which are shown in FIG. 6 for clarity). Each comparator 602 may be configured to compare a data value received at one of the data bus byte positions to a code. The system 600 may be configured to reconstruct a BE vector. That is, the system 600 may form a reconstructed BE vector similar to the input BE vector described above with respect to FIG. 5. Once the system 600 forms the reconstructed BE vector, the system 600 or another portion of the receiving device 104 (FIG. 1) may use the reconstructed BE vector in a conventional manner to reconstruct or determine a data word.

[0037]

[0046] If the output of one of the comparators 602 indicates that the received data value matches the code, the system 600 places a bit value of "0" in the corresponding bit position in the reconstructed BE vector. If the output of one of the comparators 602 indicates that the received data value does not match the code, the system 600 places a bit value of "1" in the corresponding bit position in the reconstructed BE vector. The comparators 602 (or other comparison logic in other embodiments) thus enable the system 600 to determine each unselected data bus byte position indicated by a received data value that matches the code. Similarly, the comparators 602 enable the system 600 to determine each selected data bus byte position indicated by a received data value that does not match the code.

[0038]

[0047] The system 600, or another portion of the receiving device 104, such as a processor or other processing logic (not shown), may then reconstruct or determine the data word. For example, the receiving device 104 may ignore or treat as a logical "don't care" any data value received in one of the data bus byte positions that corresponds to a bit value of "0" in the corresponding bit position in the reconstructed BE vector. In other words, the reconstructed BE vector allows the receiving device 104 to determine which of the data bus byte positions are enabled and therefore which of the received data values ​​are valid.

[0039]

[0048] In the example where the received data values ​​are the received data values ​​of the output data word described above with respect to FIG. 5, the reconstruction of the data word by the receiving device 104 may include the following: The reconstructed byte enable vector indicates that the received data value 252 in data bus byte location B255 does not match the code (which is 3 in this example), so the received data value 252 is placed in the corresponding byte location in the reconstructed data word, as indicated by arrow 604. Similarly, the reconstructed byte enable vector indicates that the received data value 0 in data bus byte location B254 does not match the code, so the received data value 0 is placed in the corresponding byte location in the reconstructed data word, as indicated by arrow 606. However, the reconstructed byte enable vector indicates that the received data value 3 in data bus byte location B253 matches the code, so byte location B253 in the reconstructed data word is invalid. Similarly, the reconstructed byte enable vector indicates that the received data value 3 in data bus byte location Bn matches the code, so the corresponding byte location Bn in the reconstructed data word is invalid. Because the received data value 2 in data bus byte location B0 does not match the code, the received data value 2 is placed in the corresponding byte location in the reconstructed data word, as indicated by arrow 608.

[0040]

[0049] Once the receiving device 104 has reconstructed or determined the data word, the receiving device 104 may process all valid received data values ​​in a conventional manner (and not process invalid received data values). In examples where the receiving device 104 is a memory device, the memory device may store the valid received data values ​​(and not store any invalid received data values). Alternatively or additionally, in some examples, the receiving device 104 may place zeros in invalid or unselected byte positions prior to such processing.

[0041]

[0050] FIG. 7 illustrates a method 700 for receiving data over a data bus. The receiving device may be configured to control some or all of the method 700. For example, in an embodiment in which the receiving device includes a processor, the processor may be configured by software or firmware to control some or all of the method 700. Also, the receiving device, or a portion thereof (e.g., the processor), may be an example of a means for performing the functions described in the method 700. The method 700 may include the following features, functions, operations, etc., illustrated by blocks 702-712, which may be performed or otherwise performed in any order consistent with the description herein. Although blocks 702-712 are described in an order that is helpful in understanding the exemplary method 700, the method for receiving data over a data bus is not limited to that order.

[0042]

[0051] As indicated by block 702, method 700 may include a receiving device receiving a selected data value via a data bus (data bit lane) and a code via a code bit lane. As indicated by block 704, method 700 may include the receiving device comparing the code to each data value received at each data bus byte position (or other data bit grouping). As indicated by block 706, method 700 may also include the receiving device determining or identifying each data bus byte position having a data value that matches the code (i.e., identifying selected data bus byte positions). Similarly, as indicated by block 708, method 700 may include the receiving device determining or identifying each data bus byte position having a data value that does not match the code (i.e., identifying unselected data bus byte positions).

[0043]

[0052] As indicated by block 710, method 700 may further include the receiving device reconstructing the byte enable vectors. As indicated by block 712, method 700 may further include the receiving device reconstructing the data word using the reconstructed byte enable vectors and the received data values. In some examples, reconstructing the data word may include placing zeros in invalid or unselected byte positions.

[0044]

[0053] As shown in FIG. 8, the system 800 may include a transmitting device 802 and a receiving device 804 on a SoC 806. The system 800 may be similar to the system 100 (FIG. 1) described above and may include N data bit lanes 808 and M code bit lanes 810 interconnecting the transmitting device 802 and the receiving device 804. In addition, the system 800 may include a Full_Payload signal path 812 interconnecting the transmitting device 802 and the receiving device 804. The transmitting device may assert a Full_Payload signal on the signal path 812 to indicate that all data bit groups have been selected. For example, in an embodiment where there are 2048 data bit lanes 808 (i.e., N=2048) and each selectable data bit group is a byte, the transmitting device may assert a Full_Payload signal to indicate that all 256 data bus byte locations have been selected. In response to detecting the assertion of the Full_Payload signal, the receiving device 804 may forgo some of the methods described above for reconstructing a data word and instead may consider the data values ​​received in all data bus byte locations to be valid. In other words, when the receiving device 804 determines that the Full_Payload signal is asserted, the receiving device 804 may process all of the data values ​​received in all of the data bus byte locations.

[0045]

[0054] Additionally, system 800 may include a Has_Payload signal path 814 interconnecting the sending device 802 and the receiving device 804. The sending device 802 may deassert the Has_Payload signal on signal path 814 when none of the data bus byte positions (or other data bit groupings) are selected, and may assert the Has_Payload signal when at least one data bus byte position (or other data bit groupings) is selected. Deasserting the Has_Payload signal may indicate to the receiving device 804 that it does not expect to receive data.

[0046]

[0055] Figure 9 illustrates an example of a PCD 900, such as a mobile phone or smartphone, in which exemplary embodiments of systems, methods, computer readable media, and other examples of communicating data over a data bus may be provided. For clarity, some data buses, interconnects, signals, etc. are not shown in Figure 9. Although PCD 900 is shown as an example, other embodiments of systems, methods, computer readable media, and other examples of communicating data over a data bus may be provided in other types of computing devices or systems.

[0047]

[0056] The PCD 900 may include a SoC 902. The SoC 902 may include a central processing unit ("CPU") 904, a neural processing unit ("NPU") 905, a graphics processing unit ("GPU") 906, a digital signal processor ("DSP") 907, an analog signal processor 908, a modem or transceiver subsystem 954, or other processor. The CPU 904 may include one or more CPU cores, such as a first CPU core 904A, a second CPU core 904B, etc., up to an Nth CPU core 904N.

[0048]

[0057] A display controller 910 and a touchscreen controller 912 may be coupled to the CPU 904. A touchscreen display 914 external to the SoC 902 may be coupled to the display controller 910 and the touchscreen controller 912. The PCD 900 may further include a video decoder 916 coupled to the CPU 904. A video amplifier 918 may be coupled to the video decoder 916 and the touchscreen display 914. A video port 920 may be coupled to the video amplifier 918. A universal serial bus ("USB") controller 922 may also be coupled to the CPU 904, and a USB port 924 may be coupled to the USB controller 922. A subscriber identity module ("SIM") card 926 may also be coupled to the CPU 904.

[0049]

[0058] One or more memories may be coupled to the CPU 904. The one or more memories may include both volatile and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 928 and dynamic random access memory ("DRAM") 930 and 931. Such memories may be external to the SoC 902, such as DRAM 930, or may be internal to the SoC 902, such as DRAM 931. A DRAM controller 932 coupled to the CPU 904 may control the writing of data to and reading of data from the DRAMs 930 and 931.

[0050]

[0059] Although not shown for clarity, a data bus coupling one or more of the memories 928, 930, 931, etc. to the CPU 904 or other processors (e.g., NPU 905, GPU 906, DSP 907, etc.) may be an example of the data bus 108 (FIG. 1) or 808 (FIG. 8) described above. Any such processor or subsystem may be an example of a transmitting device 102 (FIG. 1) or 802 (FIG. 8), an example of a receiving device 104 (FIG. 1) or 804 (FIG. 8), or a combination of such transmitting and receiving devices (i.e., a transceiver device). Any of the memories 928, 930, 931, etc. may be an example of a receiving device 104 (FIG. 1) or 804 (FIG. 8) in which the memory has a configurable width. Such a processor or subsystem may thus have processing logic configured as described above with respect to FIGS. 3-7. Data buses or other interconnects (e.g., NoCs) coupling or interconnecting such sending and receiving devices are not shown in Figure 9 for clarity. Nevertheless, as will be appreciated by those skilled in the art, SoC 902 may include any number of such data buses or other interconnects coupling or interconnecting various types of sending and receiving devices on SoC 902. Other data buses may couple SoC 902 to external devices, such as external DRAM 930.

[0051]

[0060] A stereo audio codec 934 may be coupled to the analog signal processor 908. Additionally, an audio amplifier 936 may be coupled to the stereo audio codec 934. A first stereo speaker 938 and a second stereo speaker 940 may each be coupled to the audio amplifier 936. Additionally, a microphone amplifier 942 may be coupled to the stereo audio codec 934, and a microphone 944 may be coupled to the microphone amplifier 942. A frequency modulation ("FM") radio tuner 946 may be coupled to the stereo audio codec 934. An FM antenna 948 may be coupled to the FM radio tuner 946. Additionally, a stereo headphone 950 may be coupled to the stereo audio codec 934. Other devices that may be coupled to the CPU 904 include one or more digital (e.g., CCD or CMOS) cameras 952.

[0052]

[0061] A modem or RF transceiver 954 may be coupled to the analog signal processor 908 and the CPU 904. An RF switch 956 may be coupled to the RF transceiver 954 and an RF antenna 958. Additionally, a keypad 960, a mono headset with microphone 962, and a transducer device 964 may be coupled to the analog signal processor 908.

[0053]

[0062] The SoC 902 may have one or more internal or on-chip thermal sensors 970A and may be coupled to one or more external or off-chip thermal sensors 970B. An analog-to-digital converter controller 972 may convert the voltage drops generated by the thermal sensors 970A and 970B into digital signals. A power supply 974 and a PMIC 976 may provide power to the SoC 902.

[0054]

[0063] The firmware or software may be stored in any of the memories described above, such as DRAM 930 or 931, SRAM 928, or in local memory directly accessible by the processor hardware on which the software or firmware executes. Execution of such firmware or software may control aspects of any of the methods described above or may constitute aspects of any of the systems described above. Any such memory or other temporary storage medium having firmware or software stored therein in computer readable form for execution by the processor hardware may be an example of a "computer readable medium" as that term is understood in patent vocabulary.

[0055]

[0064] The above-described solutions can reduce the number of data bit lanes on a data bus, which can have the effect of reducing the required area or footprint of the data bus on an SoC or in other systems, improving the timing of the data bus, reducing power consumption, etc.

[0056]

[0065] The following numbered clauses describe example implementations.

[0066] 1. A method for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising:

[0067] determining a set of selected data values ​​to be transmitted over a data bus by a sending device;

[0068] determining, by a transmitting device, selected and unselected groups of data bits;

[0069] determining, by the sending device, codes representing unselected data values ​​not included in the set of selected data values;

[0070] transmitting selected data values ​​in selected data bit groups and codes in unselected data bit groups to a receiving device over a data bit lane;

[0071] transmitting the code to a receiving device separately from the data bit lane; A method comprising:

[0072] 2. The method of claim 1, wherein each data bit group consists of 8 bits.

[0073] 3. The method of claim 1 or 2, wherein transmitting the code includes transmitting the code over a plurality of code bit lanes that are separate from the data bit lanes.

[0074] 4.

[0075] determining, by a transmitting device, whether all of the data bit groups have been selected;

[0076] sending an indication of all selected data bit groups to a receiving device separately from the data bit lanes; 4. The method of any of clauses 1 to 3, further comprising:

[0077] 5.

[0078] determining, by a transmitting device, whether a data bit group is unselected;

[0079] sending an indication to the receiving device that no data bit groups have been selected, separate from the data bit lanes; 5. The method of any of clauses 1 to 4, further comprising:

[0080] 6.

[0081] receiving a data value over a data bit lane;

[0082] receiving a code separately from the data bit lane;

[0083] comparing, by the receiving device, the code to each data value in each data bit group received over the data bit lane;

[0084] determining, by the receiving device, that each data bit group has a data value that matches a code in one of the selected data bit groups;

[0085] determining, by the receiving device, that each data bit group has a data value that does not match a code in one of the non-selected data bit groups;

[0086] 6. The method of any of clauses 1 to 5, further comprising processing data values ​​in selected data bit groups while not processing data values ​​in unselected data bit groups.

[0087] 7. The method of any of clauses 1 to 6, wherein the transmitting of the selected data value to the receiving device over the data bit lanes, the transmitting of the code to the receiving device, the receiving of the selected data value over the data bit lanes, and the receiving of the code are all performed in a system on chip ("SoC").

[0088] 8. A system for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising:

[0089] an encoder configured to determine a set of selected data values ​​to be transmitted over the data bus in selected groups of data bits;

[0090] a data word formatter configured to determine selected data bit groups and unselected data bit groups, determine codes representing unselected data values ​​not included in the set of selected data values, provide a data word having the selected data values ​​in the selected data bit groups and the codes in the unselected data bit groups to a receiving device via the data bit lanes, and provide the codes to the receiving device via a plurality of code bit lanes separate from the data bit lanes; A system comprising:

[0091] 9. The system of claim 8, wherein the encoder comprises a binary-to-unary encoder configured to determine a bit vector having a plurality of bit positions corresponding to the selected data value.

[0092] 10. A system as described in clause 8 or 9, wherein each data bit group consists of 8 bits.

[0093] 11. The system of any of clauses 8 to 10, wherein the data word formatter is further configured to determine whether all data bit groups have been selected and provide a signal to a receiving device via the signal lane indicating that all data bit groups have been selected.

[0094] 12. The system of any of clauses 8 to 11, wherein the data word formatter is further configured to determine whether the data bit group is not selected and provide a signal to a receiving device via the signal lane indicating that the data bit group is not selected.

[0095] 13. The system of any of clauses 8 to 12, further comprising a receiving device coupled to the plurality of data bit lanes and the plurality of code bit lanes.

[0096] 14. The system of any of clauses 8 to 13, wherein the receiving device comprises a memory device having a configurable data width.

[0097] 15. The receiving device:

[0098] receiving a data value via a data bit lane;

[0099] Receive the code via the code bit lane,

[0100] comparing the code to each data value in each group of data bits received over the data bus;

[0101] determining that each data bit group has a data value that corresponds to a code in one of the selected data bit groups;

[0102] determining that each data bit group has a data value that does not match a code in one of the non-selected data bit groups; 15. The system of any of clauses 8 to 14, configured to

[0103] 16. The system of any of clauses 8 to 15, wherein the system and data bus for data communication are included in a system on a chip ("SoC").

[0104] 17. A system for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising:

[0105] means for determining a set of selected data values ​​to be transmitted over the data bus by a sending device;

[0106] means for determining selected and unselected groups of data bits by the transmitting device;

[0107] means for determining, by the sending device, codes representing unselected data values ​​not included in the set of selected data values;

[0108] means for transmitting selected data values ​​in selected data bit groups and codes in unselected data bit groups to a receiving device over a data bit lane;

[0109] means for transmitting the code to a receiving device separately from the data bit lanes; A system comprising:

[0110] 18. The system of claim 17, wherein each data bit group consists of 8 bits.

[0111] 19. The system of clause 17 or 18, wherein the means for transmitting the code comprises means for transmitting the code over a plurality of code bit lanes separate from the data bit lanes.

[0112] 20. The system of any of clauses 17 to 19, wherein the receiving device comprises a memory device having a configurable width.

[0113] twenty one.

[0114] means for determining, by a transmitting device, whether all of the data bit groups have been selected;

[0115] means for transmitting to a receiving device an indication of all selected data bit groups, separate from the data bit lanes; 21. The system of any of clauses 17 to 20, further comprising:

[0116] twenty two.

[0117] means for determining if a data bit group has not been selected by a transmitting device;

[0118] means for transmitting an indication to a receiving device that a data bit group has not been selected, separate from the data bit lane; 22. The system of any of clauses 17 to 21, further comprising:

[0119] twenty three.

[0120] means for receiving a data value over a data bit lane;

[0121] means for receiving the code separately from the data bit lanes;

[0122] means for comparing, by a receiving device, the code with each data value in each data bit group received over a data bit lane;

[0123] means for determining, by a receiving device, that each data bit group has a data value that matches a code in one of the selected data bit groups;

[0124] means for determining, by the receiving device, that each data bit group has a data value that does not match a code in one of the non-selected data bit groups;

[0125] means for processing data values ​​in selected data bit groups while not processing data values ​​in unselected data bit groups; 23. The system of any of clauses 17 to 22, further comprising:

[0126] 24. A computer-readable medium for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the computer-readable medium comprising a non-transitory computer-readable medium storing instructions in a computer-executable form, the instructions, when executed by a processing system of a computing device,

[0127] determining a set of selected data values ​​to be transmitted over a data bus;

[0128] determining selected and unselected groups of data bits;

[0129] determining codes representing non-selected data values ​​not included in the set of selected data values;

[0130] transmitting selected data values ​​in selected data bit groups and codes in unselected data bit groups to a receiving device over a data bit lane;

[0131] transmitting the code to a receiving device separately from the data bit lane; A method comprising:

[0132] 25. The computer-readable medium of claim 24, wherein each data bit group consists of 8 bits.

[0133] 26. The computer-readable medium of any one of clauses 24 to 25, wherein transmitting the code includes transmitting the code over a plurality of code bit lanes that are separate from the data bit lanes.

[0134] 27.

[0135] determining whether all data bit groups have been selected;

[0136] sending an indication of all selected data bit groups to a receiving device separately from the data bit lanes; 27. The computer-readable medium of any of clauses 24 to 26, further comprising instructions for configuring the processing system to control

[0137] 28.

[0138] determining, by a transmitting device, whether a data bit group is unselected;

[0139] sending an indication to a receiving device that the data bit group is not selected, separate from the data bit lane; 28. The computer-readable medium of any of clauses 24 to 27, further comprising instructions for configuring the processing system to control

[0140] 29. A method for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising:

[0141] receiving, by a receiving device, the code separately from the data bit lanes;

[0142] receiving, by a receiving device, a data value over a data bit lane of a data bus;

[0143] comparing, by the receiving device, the code with each data value in each data bit group received over the data bus;

[0144] determining, by a receiving device, that each group of data bits has a data value that corresponds to the code;

[0145] determining, by a receiving device, that each group of data bits has a data value that does not match the code;

[0146] providing an indication of selected data bit groups based on a determination that the data bit groups have data values ​​that match the code, and an indication of unselected data bit groups based on a determination that the data bit groups have data values ​​that do not match the code; A method comprising:

[0147] 30. The method of clause 29, further comprising processing data values ​​in selected data bit groups while not processing data values ​​in unselected data bit groups.

[0148] 31. A system for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising:

[0149] comparison logic configured to receive selected data values ​​via the data bit lanes, receive a code separately from the data bit lanes, compare the code to each data value in each data bit group, determine each data bit group having a data value that matches the code in one of the selected data bit groups, and determine each data bit group having a data value that does not match the code in one of the unselected data bit groups;

[0150] processing logic configured to provide an indication of a selected data bit group based on a determination that the data bit group has a data value that matches the code, and an indication of a non-selected data bit group based on a determination that the data bit group has a data value that does not match the code; A system comprising:

[0151] 32. The system of clause 31, wherein the processing logic is configured to process data values ​​in selected data bit groups and not process data values ​​in unselected data bit groups.

[0057]

[0152] Alternative embodiments will be apparent to those skilled in the art to which the invention pertains. Thus, while selected aspects have been shown and described in detail, it will be understood that various substitutions and modifications may be made thereto.

Claims

1. 1. A method for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising: determining a set of selected data values ​​to be transmitted over the data bus by a sending device; determining, by the transmitting device, selected and unselected groups of data bits; determining, by the sending device, codes representing non-selected data values ​​not included in the set of selected data values; transmitting selected data values ​​in selected data bit groups and said codes in unselected data bit groups to a receiving device via said data bit lanes; transmitting said code to said receiving device separately from said data bit lane; A method comprising:

2. 2. The method of claim 1, wherein each data bit group consists of 8 bits.

3. The method of claim 1 , wherein transmitting the code comprises transmitting the code over a plurality of code bit lanes that are separate from the data bit lanes.

4. determining, by the transmitting device, whether all data bit groups have been selected; sending an indication of all selected data bit groups to the receiving device separately from the data bit lanes; The method of claim 1 further comprising:

5. determining, by the transmitting device, whether a group of data bits has been selected; sending an indication to the receiving device that a data bit group has not been selected separately from the data bit lane; The method of claim 1 further comprising:

6. receiving a data value over the data bit lane; receiving said code separately from said data bit lanes; comparing, by the receiving device, the code with each data value in each data bit group received over the data bit lane; determining, by the receiving device, that each data bit group has a data value that matches the code in one of the selected data bit groups; determining, by the receiving device, that each data bit group has a data value in one of the non-selected data bit groups that does not match the code; processing data values ​​in the selected data bit groups while not processing data values ​​in the unselected data bit groups; The method of claim 1 further comprising:

7. 7. The method of claim 6, wherein the transmitting of the selected data value to the receiving device over the data bit lanes, the transmitting of the code to the receiving device, the receiving of the selected data value over the data bit lanes, and the receiving of the code are all performed in a system on chip ("SoC").

8. 1. A system for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising: an encoder configured to determine a set of selected data values ​​for transmission over the data bus in selected groups of data bits; a data word formatter configured to determine selected and unselected data bit groups, determine codes representing unselected data values ​​not included in the set of selected data values, provide a data word having the selected data values ​​in the selected data bit groups and the codes in the unselected data bit groups to a receiving device via the data bit lanes, and provide the codes to the receiving device via a plurality of code bit lanes separate from the data bit lanes; A system comprising:

9. 9. The system of claim 8, wherein the encoder comprises a binary-to-unary encoder configured to determine a bit vector having a plurality of bit positions corresponding to the selected data value.

10. 9. The system of claim 8, wherein each data bit group consists of eight bits.

11. 9. The system of claim 8, wherein the data word formatter is further configured to determine whether all data bit groups have been selected and provide a signal to the receiving device via a signal lane indicating that all data bit groups have been selected.

12. 9. The system of claim 8, wherein the data word formatter is further configured to determine if a data bit group is unselected and provide a signal to the receiving device via a signal lane indicating that a data bit group is unselected.

13. The system of claim 8 further comprising a receiving device coupled to the plurality of data bit lanes and the plurality of code bit lanes.

14. The system of claim 13 , wherein the receiving device comprises a memory device having a configurable data width.

15. The receiving device: receiving a data value via the data bit lane; receiving the code via the code bit lane; comparing said code with each data value in each group of data bits received over said data bus; determining that each data bit group has a data value that corresponds to the code in one of the selected data bit groups; determining that each data bit group has a data value that does not match the code in one of the non-selected data bit groups; The system of claim 13 configured to:

16. The system of claim 8 , wherein the system for data communication and the data bus are included in a system on a chip ("SoC").

17. 1. A system for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising: means for determining a set of selected data values ​​to be transmitted over said data bus by a sending device; means for determining selected and unselected groups of data bits by said transmitting device; means for determining, by the sending device, codes representing non-selected data values ​​not included in the set of selected data values; means for transmitting selected data values ​​in selected data bit groups and said codes in unselected data bit groups to a receiving device via said data bit lanes; means for transmitting said code to said receiving device separately from said data bit lanes; A system comprising:

18. 20. The system of claim 17, wherein each data bit group consists of 8 bits.

19. 20. The system of claim 17, wherein the means for transmitting the code comprises means for transmitting the code over a plurality of code bit lanes separate from the data bit lanes.

20. 20. The system of claim 17, wherein the receiving device comprises a memory device having a configurable width.

21. means for determining, by the transmitting device, whether all data bit groups have been selected; means for transmitting to the receiving device an indication of all data bit groups that have been selected, separate from the data bit lanes; The system of claim 17 further comprising:

22. means for determining, by the transmitting device, whether a group of data bits has been selected; 20. The system of claim 17, further comprising: means for transmitting an indication to the receiving device that no data bit groups have been selected, separate from the data bit lanes.

23. means for receiving data values ​​over the data bit lanes; means for receiving said code separately from said data bit lanes; means for comparing, by the receiving device, the code with each data value in each data bit group received over the data bit lane; means for determining, by the receiving device, that each data bit group has a data value that matches the code in one of the selected data bit groups; means for determining, by the receiving device, that each data bit group has a data value that does not match the code in one of the non-selected data bit groups; means for processing data values ​​in the selected data bit groups while not processing data values ​​in the unselected data bit groups; The system of claim 17 further comprising:

24. 1. A computer-readable medium for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the computer-readable medium comprising a non-transitory computer-readable medium having stored thereon instructions in a computer-executable form, the instructions, when executed by a processing system of a computing device, determining a set of selected data values ​​to be transmitted over the data bus; determining selected and unselected groups of data bits; determining codes representing non-selected data values ​​not included in the set of selected data values; transmitting selected data values ​​in selected data bit groups and said codes in unselected data bit groups to a receiving device via said data bit lanes; transmitting said code to said receiving device separately from said data bit lane; 4. A computer readable medium for configuring the processing system to control:

25. 25. The computer-readable medium of claim 24, wherein each data bit group consists of eight bits.

26. 25. The computer-readable medium of claim 24, wherein transmitting the code comprises transmitting the code over a plurality of code bit lanes that are separate from the data bit lanes.

27. determining whether all data bit groups have been selected; sending an indication of all selected data bit groups to the receiving device separately from the data bit lanes; 25. The computer readable medium of claim 24, further comprising instructions for configuring the processing system to control:

28. determining, by the transmitting device, whether a group of data bits has been selected; sending an indication to the receiving device that no data bit groups have been selected separately from the data bit lanes; 25. The computer readable medium of claim 24, further comprising instructions for configuring the processing system to control:

29. 1. A method for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the method comprising: receiving, by a receiving device, a code separately from said data bit lanes; receiving, by the receiving device, a data value over the data bit lane of the data bus; comparing, by the receiving device, the code with each data value in each data bit group received over the data bus; determining, by the receiving device, that each group of data bits has a data value that corresponds to the code; determining, by the receiving device, that each group of data bits has a data value that does not match the code; providing an indication of selected data bit groups based on a determination that a data bit group has a data value that matches the code, and an indication of unselected data bit groups based on a determination that a data bit group has a data value that does not match the code; A method comprising:

30. 30. The method of claim 29, further comprising processing data values ​​in the selected data bit groups while not processing data values ​​in the unselected data bit groups.

31. 1. A system for data communication over a data bus having a plurality of data bit groups, each data bit group having a plurality of data bit lanes, the system comprising: comparison logic configured to receive the selected data values ​​via the data bit lanes, receive the code separately from the data bit lanes, compare the code to each data value in each data bit group, and determine each data bit group having a data value that matches the code and determine each data bit group having a data value that does not match the code; processing logic configured to provide an indication of a selected data bit group based on a determination that a data bit group has a data value that matches the code, and an indication of a non-selected data bit group based on a determination that a data bit group has a data value that does not match the code; A system comprising:

32. 32. The system of claim 31 , wherein the processing logic is configured to process data values ​​in the selected data bit groups and not process data values ​​in the unselected data bit groups.

Images