Single-wire serial communication using pulse-width modulation in a daisy-chain architecture

Abstract

Improved serial communications are provided in a system in which each node regenerates received data and transmits the regenerated data to at least one other node in the system. Pulse width modulation (PWM) is used to encode the data. All pulse shapes of the PWM preferably begin with a sync feature. Also, the regeneration delay time at each node is preferably less than the clock period of the system.

Description

[Technical field]

[0001] The present invention relates to serial communications in which each node regenerates received data and transmits the regenerated data to other nodes. [Background technology]

[0002] Serial data links are commonly used in embedded systems where multiple devices need to communicate with each other. However, for small / low-power devices with low pin counts, traditional Serial Peripheral Interface (SPI) links, using 4-5 wires and two power pins, can be a significant overhead. Therefore, providing a less intrusive serial communication would be an advancement in the art. Summary of the Invention [Means for solving the problem]

[0003] An exemplary embodiment is a single-wire replicated serial data link that uses PWM (Pulse Width Modulation) for digital communication: Data is transmitted from a source as a stream of pulses with wide pulses equal to logic "1" and narrow pulses equal to logic "0" (and vice versa).

[0004] The advantages of this technology over conventional 4 / 5-wire SPI links are: - Uses fewer pins, making it suitable for low pin count devices. - Wiring of printed circuit boards becomes easier. Compared to a shift register type chain, the latency per device is only one bit period, allowing all devices in the chain to respond quickly to the data transmitted to them.

[0005] The advantages of this technique over repetitive Manchester encoded serial links are: No need for a highly accurate clock for data recovery or data regeneration: the clock can be synchronized to the start of every pulse and only needs to be "accurate / stable" for one bit period, not for a long data stream. · Accuracy of 1 bit period is not that important. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of one embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram illustrating an exemplary pulse width modulation format. [Diagram 3] FIG. 3 is a diagram illustrating some data formatting options. [Figure 4] FIG. 4 is a block diagram of an exemplary data regenerator. [Diagram 5] FIG. 5 is a timing diagram related to the example of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] FIG. 1 illustrates an exemplary embodiment of the present invention. This embodiment includes a controller 102 and two or more nodes 104-1, 104-2, ..., 104-n. The controller 102 is typically a microcontroller or FPGA (field programmable gate array) capable of generating and reading multiple pulse width modulated (PWM) signals. A controller can control one or more serial links, as described herein. Each node includes a corresponding data regenerator 108-1, 108-2, ..., 108-n. The remaining portions of each node are designated 106-1, 106-2, ..., 106-n and may include any circuit or device. It may be convenient to refer to these portions of the node as "control circuitry." Each node is connected to two or more serial data links 112-1, 112-2, .... Digital data on the two or more serial data links is pulse width modulated, e.g., encoded in modulation format 110. Each node is configured to regenerate the received data to generate regenerated data and transmit the regenerated data to one or more other nodes of the two or more nodes. Although the example of FIG. 1 shows a daisy-chain architecture, transmission from a node is not limited to only transmitting to a single other node. Transmission from a node may occur to multiple nodes, thereby forming a tree architecture. An important feature of some preferred embodiments is that the regeneration delay time τ is less than the clock period T. This capability is described below in conjunction with the examples shown in FIGS. 4 and 5.

[0008] The approach is applicable wherever serial communications are required, and is particularly advantageous for embedded systems where the components being connected are small enough (e.g., subparts of an integrated circuit chip) that the overhead of traditional serial communications would be burdensome. The two or more serial data links are preferably single-wire, half-duplex links.

[0009] FIG. 2 shows details of a preferred modulation format, which is binary (two symbol) pulse width modulation, where T is the system clock period. All pulse shapes of the pulse width modulation (PWM) preferably start with a synchronization feature (in this example, the synchronization feature is a rising edge 202). The data regenerator of each node includes a local clock. The data regenerator of each node can synchronize its local clock to the synchronization feature of the pulse width modulation. In this way, a separate clock line is not required for the serial data link. Also, the local clocks for data recovery and data generation do not need to be particularly stable, since they are resynchronized every system clock cycle. Of course, the roles of the 0s and 1s can be swapped in the example of FIG. 2, and various other pulse width modulation pulse shapes can be used. As will be seen in the following example, it is preferable to use a PWM pulse shape that allows the receiver to determine which symbol has been transmitted well before it has completed reception of the current PWM shape. Because when the number of symbols is greater than two, it becomes more difficult to determine what has been transmitted based on partial reception of the corresponding PWM shape, which increases the pipeline delay. Also, without binary pulse width modulation, the oscillator accuracy required for the local clock would be undesirably high.

[0010] So, this example is a single-wire replicated serial data link that uses PWM (Pulse Width Modulation) for digital communication. Data is sent from the source as a stream of pulses with wide pulses equal to logic "1" and narrow pulses equal to logic "0" (and vice versa). In addition, multiple bits can be represented by pulses of different widths, but this requires higher precision from the oscillator and increases the pipeline delay.

[0011] The pulse stream is regenerated at each node and then transmitted to the next node (see FIG. 1). The transmitted data may include both node addresses and data / control information. Any conventional addressing scheme may be used. A preferred addressing scheme is to structure the serial data such that the address bits arrive before the data bits in each word of the serial data stream (see 302 in FIG. 3). Optionally, the serial data may be structured such that the control bits arrive before the address bits (see 304 in FIG. 3). Alternatively, the serial data may be structured such that the control bits arrive after the address bits and before the data bits (see 306 in FIG. 3).

[0012] FIG. 4 is a simplified block diagram of an exemplary data regenerator, where the local clock is provided by two oscillators Osc1 (406) and Osc2 (408) that run at 8 times the system clock period. A typical clock period is 100 ns or 200 ns. For completeness, the remaining components in FIG. 4 are slicer 402, timing reference generator 404, sampling control 410, data sampling and storage 412, pulse width modulator 414, multiplexer 416, and output buffer 418. In this example, initialization is performed after power-up and the output of the slicer is applied directly to the output. This period of direct connection is used to detect if there is AC or DC coupling between the devices. Fine tuning and synchronization of the oscillators is performed during the preamble at the beginning of every major communication sequence.

[0013] Osc1 is triggered by the rising edge of the input data and is used to sample at count 4 (the halfway point). Osc2 is started when Osc1=4 and is used to time the output pulse (2 counts if sampled low, 6 counts if sampled high).

[0014] The resulting timing diagram is shown in FIG. 5, where 502 shows an exemplary bit sequence "0110" and 504 shows the corresponding PWM input data. 506 shows the slicer output, Tsr shows the slicer rise time, and Tsf shows the slicer fall time. The count sequence of Osc1 is shown at 508, and the corresponding sampled data is shown at 510. It can be seen that the transition in the sampled data 510 occurs only at count 4 of Osc1 (the midpoint above). The count sequence of Osc2 is shown at 512, and the corresponding encoded data is shown at 514. The output data is shown at 516, where Tor shows the output buffer rise time, and Tof shows the output buffer fall time.

[0015] Other notations in Figure 5 are: Thf_clk is the period of the node's internal high frequency clock (not to be confused with the period T of the system clock); T_high_0 is the coded data high time of bit 0 = 2 x Thf_clk; T_high_1 is the coded data high time of bit 1 = 6 x Thf_clk; T_low_0 is the coded data low time of bit 0 = 6 x Thf_clk; T_low_1 is the coded data low time of bit 1 = 2 x Thf_clk. Important reference times are: T1 is the rising edge of the input data; T2 is the rising edge of the corresponding output data; T3-T1 is the duration of the input bit and T4-T2 is the duration of the output bit (both durations are actually the system clock period T, so we actually define T3 and T4 here).

[0016] The pipeline delay, T_pipelined delay=T2-T1, which is equal to Tsr+4*Thf_clk+Tor. As mentioned above (and shown in FIG. 5), this pipeline delay is preferably smaller than the clock period T. Another way to express this desirable characteristic is that the start time of output bit 0 (T2) precedes the end time of input bit 0 (T3).

[0017] A further advantage of this exemplary embodiment is that rise and fall times do not matter, and errors do not accumulate as data is passed from node to node in the chain.

Claims

1. Two or more nodes; two or more serial data links configured to connect the two or more nodes; the digital data on said two or more serial data links is pulse width modulated encoded; An apparatus, wherein each node of the two or more nodes is configured to regenerate received data to generate regenerated data and to transmit the regenerated data to one or more nodes of the two or more nodes.

2. 2. The apparatus of claim 1, The apparatus, wherein a playback delay time of at least one of the two or more nodes is less than a clock period.

3. An embedded system comprising the device according to claim 1.

4. 2. The apparatus of claim 1, The apparatus, wherein the pulse width modulation is binary pulse width modulation.

5. 2. The apparatus of claim 1, The apparatus, wherein each pulse shape of the pulse width modulation begins with a synchronization feature.

6. 6. The apparatus of claim 5, An apparatus, wherein each node of the two or more nodes includes a local clock, and each node synchronizes its local clock to the synchronization feature of the pulse width modulation.

7. 2. The apparatus of claim 1, The two or more serial data links are single-wire, half-duplex links.

8. 2. The apparatus of claim 1, The digital data format comprises data bits and address bits disposed before the data bits.

9. 9. The apparatus of claim 8, The digital data format further comprises control bits located before the address bits.

10. 9. The apparatus of claim 8, The digital data format further comprises control bits located before the data bits and after the address bits.

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