SRAM with scan mode

Abstract

A memory is provided having a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation, in which while the write multiplexer clock signal is asserted, a scan-in signal is routed through the write multiplexer to a first bit line, and similarly, while the read multiplexer clock signal is asserted, a scan-in signal is routed from the first bit line through the read multiplexer.

Description

[Technical field]

[0001] This application relates to memory, and more particularly to static random-access memory (SRAM) having a scan mode of operation. [Background technology]

[0002] In a conventional static random access memory (SRAM), a bit cell connects to a pair of bit lines through a corresponding pair of access transistors during a read operation. To switch on the access transistors during a read operation, a self-timed clock circuit controls the assertion of a voltage on a word line that connects to the gate of each of the access transistors. Therefore, the pair of access transistors and the corresponding bit line can be treated as a single read port and a single write port for the bit cell. The pair of bit lines is shared by other bit cells and their corresponding access transistors. The resulting group of bit cells linked by their common bit line pair is commonly referred to as a column of bit cells. Since there is just one bit line pair for a column, only a single read operation or a single write operation can be performed each time a word line is asserted.

[0003] Triple-port SRAMs were developed to accommodate applications such as video processing that require at least two access ports. One processor may access the triple-port SRAM through a first read access port, while another processor accesses the triple-port SRAM through a second read access port. In a triple-port SRAM, each column has a pair of write bit lines for write operations, and two separate read bit lines, one for each read port. Hence, each bit cell has one pair of access transistors for coupling to the write bit lines, and may have two additional access transistors, one for each read port. Although such triple-port SRAMs allow for simultaneous read / write operations, the extra access transistors per bit cell result in a loss of density (the number of bit cells that can be implemented in a given area of ​​die space). Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory includes: a write driver configured to control a binary state of a write driver bit line during a scan mode of operation in response to a binary state of a scan-in signal during the scan mode of operation; a write multiplexer configured to couple the write driver bit line to a first bit line in response to assertion of a write multiplexer clock signal; and a read multiplexer configured to couple the first bit line to a global read bit line in response to assertion of a read multiplexer clock signal. a clock circuit configured to assert a write multiplexer clock signal substantially simultaneously with a read multiplexer clock signal during a scan mode of operation.

[0005] According to a second aspect of the present disclosure, a scan method for a memory includes asserting a write multiplexer clock signal while a read multiplexer clock signal is asserted during a scan mode of operation; A scanning method is provided that includes coupling a scan-in signal through a write multiplexer to a first bit line in response to assertion of a write multiplexer clock signal, and coupling the scan-in signal from the first bit line through a read multiplexer to a global read bit line in response to assertion of a read multiplexer signal.

[0006] According to a third aspect of the present disclosure, there is provided a memory including: a first switch configured to couple a write driver bit line to a first bit line in response to assertion of a write multiplexer clock signal; a global read bit line; a sense amplifier configured to sense a binary state of the first bit line to control a binary state of the global read bit line in response to assertion of the read multiplexer clock signal; and a clock circuit configured to assert the write multiplexer clock signal substantially simultaneously with the read multiplexer clock signal during a scan mode of operation.

[0007] These and additional advantages may be more fully understood through the following detailed description of the invention. [Brief description of the drawings]

[0008] [Figure 1] 1 shows a PTP SRAM in which the scan path bypasses the write and read multiplexers. [Diagram 2] 1 illustrates a bit cell for a PTP SRAM according to one embodiment of the present disclosure. [Diagram 3] 2 is a timing diagram for various signals during functional mode read and write operations in the PTP SRAM of FIG. 1. [Figure 4] 1 illustrates a PTP SRAM in which the scan path passes through peripheral logic including write and read multiplexers, according to one embodiment of the present disclosure. [Diagram 5]FIG. 13 is a timing diagram for various signals during a scan mode of operation in a PTP SRAM according to one embodiment of the present disclosure. [Figure 6] 11 is a flow chart for an exemplary method of operation for a pseudo triple port memory periphery logic scan in accordance with one aspect of the disclosure. [Figure 7] 1 illustrates several exemplary electronic systems each incorporating a pseudo triple port memory with periphery logic scan capability in accordance with an aspect of the present disclosure;

[0009] Implementations of the present disclosure and their advantages are best understood by reference to the following detailed description, it being understood that like reference numerals are used to identify like elements shown in one or more of the figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] To provide the access flexibility of triple-port memories without incurring the penalty of a density of more than two access transistors per bit cell, a pseudo-triple-port SRAM is disclosed. In a pseudo-triple-port (PTP) bit cell, a first word line controls a first access transistor coupled to a bit line, whereas a second word line controls a second access transistor coupled to a complementary bit line. Thus, a first read port is formed by the bit line and the first access transistor. Similarly, a second read port is formed by the complementary bit line and the second access transistor. Both bit lines and both access transistors form a write port. The read and write accesses are synchronized by a memory clock signal in a "double pumping" manner such that a read operation is performed to the bit cell during a first portion of a cycle of the memory clock signal, whereas a write operation is performed during a second portion of a cycle of the memory clock signal.

[0011] During a read operation, the read multiplexer selects the bit line being accessed. Similarly, during a write operation, the write multiplexer selects the bit line pair being accessed. During a read operation, the write multiplexer is inactive so that it does not interfere with the write operation. Similarly, the read multiplexer is inactive during a write operation. The read and write multiplexers, along with associated components such as write drivers and sense amplifiers, form what may be referred to as peripheral logic for the memory. However, the mutually exclusive operation of the read and write multiplexers complicates the implementation of a scan mode of operation for testing the peripheral logic. When the scan mode is performed during a first portion of the memory clock cycle, the write multiplexer is inactive, whereas the read multiplexer is inactive during a second portion of the memory clock cycle. Therefore, it is conventional for the scan mode of operation to bypass both the write multiplexer and the read multiplexer in a pseudo triple port SRAM.

[0012] Therefore, a pseudo triple port (PTP) SRAM having a scan operation mode that scans peripheral logic including read and write multiplexers is disclosed. To provide a deeper understanding of this innovative scan operation mode, first, another scan operation mode for the PTP SRAM 100 as shown in FIG. 1 is described. A system component such as a processor (not shown) generates a data-in signal for a write operation. The processor is in a system power domain powered by a system power supply voltage, whereas the PTP SRAM 100 is in a memory power domain powered by a memory power supply voltage. Therefore, the data-in signal is level-shifted from the system power domain to the memory power domain by the lever shifter 105. A first inverter 110 inverts the level-shifted output of the level shifter 105 to form a complementary data input signal dinb. A second inverter 115 inverts the complementary data input signal dinb to form a data input signal din.

[0013] During a write operation, write driver 120 drives write driver bitline wd in response to data input signal din, assuming bitmask signal ibyte_n is not asserted. If bitmask signal ibyte_n is asserted, write driver 120 is not responsive to data input signal din. Write driver 120 also drives complementary write driver bitline wdb in response to complementary data input signal dinb (again assuming bitmask signal ibyte_n is not asserted). Write multiplexer (mux) 125 couples write driver bitline wd to memory bank bitline ubl0 in response to assertion of write multiplexer clock signal uwm. Similarly, write multiplexer 125 couples complementary write driver bitline wdb to memory bank complementary bitline ublb0 in response to assertion of write multiplexer clock signal uwm. Bitlines ubl0 and ublb0 form a bitline pair.

[0014] Prior to a write operation, the bit line pair ubl0 and ublb0 are precharged to a memory power supply voltage. When the data input signal dinb is a binary 1 value (assuming an active high implementation), the bit line ubl0 remains in a charged state while the complementary bit line ublb0 is discharged. Conversely, when the data input signal dinb is a binary 0 value, the bit line ubl0 is discharged while the complementary bit line ublb0 remains in a charged state. Based on the complementary charge states of the bit line pair ubl0 and ublb0, the accessed PTP bit cell (not shown) is written accordingly. The bit lines ubl0 and ublb0 and the corresponding PTP bit cells form a column in an upper bank (not shown) in the PTP SRAM 100. A bank is an array of columns and corresponding bit cells.

[0015] Both pairs of bit lines ubl0 and ublb0 are driven through write mux 125 by write driver 120 during write operations. However, each bit line forms its own read port during read operations. In PTP SRAM 100, a read multiplexer (mux) and sense amplifiers 130 are combined. Depending on the active low assertion of a read mux clock signal rmp, the read mux and sense amplifiers 130 are either powered or not. When powered as controlled by the read mux clock signal rmp, the read column mux and sense amplifiers 130 sense both bit line ubl0 and corresponding bit line lbl0 from the lower bank (not shown).

[0016] As defined herein, a binary signal is considered to be "asserted" when the signal is logically true, regardless of whether the logically true state is represented using an active-high or active-low convention. Because the read multiplexer clock signal rmp is an active-low signal, it is therefore asserted by being discharged to ground. In contrast, if the read multiplexer clock signal rmp were an active-high signal, it would be asserted by being charged to the memory power supply voltage.

[0017] When the read multiplexer address signal rmp is asserted and bit line ubl0 remains charged during a read operation because the accessed PTP bit cell stores a binary 1 bit, the read column multiplexer and sense amplifier 130 functions to discharge its output signal 131 to ground. The output signal 131 drives the gate of an n-type metal-oxide semiconductor (NMOS) transistor M1, which has its source coupled to ground and its drain coupled to the global read bit line grbl.

[0018] The global read bit line grbl is part of the system power domain. Before a read operation, therefore, the precharge of the global read bit line grbl precharges it to the system power supply voltage. The discharged state of the output signal 131 prevents the transistor M1 from switching on, which causes the global read bit line grbl to remain in a charged state. However, if the accessed PTP bit cell stored a binary 0, the bit line ubl0 will discharge during the read operation, which will cause the output signal 131 to be asserted to the memory power supply voltage when the read multiplexer clock signal rmp is asserted. At this time, the global read bit line grbl will discharge towards ground due to the high state of the output signal 131. A global data output latch (not shown) latches the state of the global read bit line grbl as a data out (dout) signal during a read operation.

[0019] 2 shows an example column 200 for a PTP SRAM as disclosed herein. The column 200 includes a first PTP bit cell 205 and a second PTP bit cell 210, although it will be understood that the column 200 may include additional PTP bit cells that are not shown for clarity of illustration. Each PTP bit cell is in its own row of other bit cells (not shown) that share a corresponding pair of word lines. For example, the PTP bit cell 205 is located in the 0th row of bit cells. Similarly, the PTP bit cell 210 is in the 1st row of bit cells. Each PTP bit cell includes a cross-coupled pair of inverters that drive a true bit node Q and a complementary bit node QB.

[0020] The bit line pair formed by bit line ubl0 and complementary bit line ublb0 extends across column 200. Read port A word line WLA0 extends across the 0th row and drives a first n-type metal oxide semiconductor (NMOS) access transistor M3 in PTP bit cell 205 that couples between true bit node Q of PTP bit cell 205 and bit line ubl0. Read port A word line WLA0 similarly drives other first access transistors in the remaining PTP bit cells (not shown) in the 0th row. Read port B word line WLB0 also extends across the 0th row and drives a second NMOS access transistor M4 that couples between complementary bit node QB of PTP bit cell 205 and complementary bit line ublb0. Read port B word line WLB0 similarly drives other second access transistors (not shown) in the 0th row. Because the word lines are independently controlled during a read operation, the combination of bit line ubl0, read port A word line WLA0, and access transistor M3 form the read port A for the PTP bit cell 205. Therefore, bit line ubl0 may also be referred to as the read port A bit line. Similarly, the combination of complementary bit line ublb0, read port B word line WLB0, and access transistor M4 form the read port B for the bit cell 205. Therefore, complementary bit line ublb0 may also be referred to as the read port B bit line.

[0021] The word line pair for the first row of bit cells is similar. For example, the read port A word line WLA1 of the word line pair extends across the first row and drives the access transistor M5 in the PTP bit cell 210. The read port A word line WLA1 similarly drives other first access transistors in the remaining bit cells (not shown) in the first column. The read port B word line WLB1 extends across the first row and drives the access transistor M6 in the PTP bit cell 210. The read port B word line WLB1 similarly drives other second access transistors (not shown) in the first column. Thus, the PTP bit cell 210 has a read port A from the combination of its access transistor M5, bit line ubl0, and read port A word line WLA1. Similarly, the PTP bit cell 210 has a read port B from the combination of its access transistor M6, complementary bit line ublb0, and read port B word line WLB1.

[0022] Assume that read port A is accessed in PTP bit cell 205 through assertion of a voltage for word line WLA0. Because access transistor M3 couples between it and bit node Q of PTP bit cell 205, when the voltage of read port A word line WLA0 is asserted, the voltage of bit line ublb0 will be charged accordingly to the binary content of PTP bit cell 205. If PTP bit cell 205 stores a binary 1 in binary high convention, bit node Q of PTP bit cell 205 will therefore be charged to the memory power supply voltage. Before a read operation, bit line ubl0 is precharged to the memory power supply voltage. During a read operation for read port A, when PTP bit cell 205 stores a binary 1, bit line ubl0 will therefore remain charged to the memory power supply voltage. However, if PTP bit cell 205 stored a binary 0, a read operation to read port A would result in bit line ubl0 being discharged towards ground while access transistor M3 is switched on.

[0023] Some example waveforms for such a read operation for the PTP bit cell 205 are shown in FIG. 3. Prior to the assertion of the memory clock signal CLK at time t0, the bit line ubl0 is charged to the memory power supply voltage. The assertion of the memory clock signal at time t0 triggers a read cycle followed by a write cycle within one period of the memory clock signal CLK. From time t1 to time t2, the read port A word line WLA0 for the 0th row is asserted. Therefore, there is a read port A access from time t1 to time 2 for the bit cell 205. Once the word line voltage occurs, the read multiplexer clock signal rmp is then asserted. In this implementation, the read multiplexer clock signal rmp is an active low signal, so it is asserted by discharging to ground. In this example, it is assumed that the PTP bit cell 205 stores a binary 1 bit, which causes the bit node Q of the PTP bit cell 205 to be charged to the power supply voltage. Therefore, bit line ubl0 remains charged to the power supply voltage during the word line assertion period from time t1 to time t2. Note that during the same word line assertion period from time t1 to time t2, the read port B word line WLB1 for the first row (not shown in FIG. 3) may also be asserted to perform a read port B access to the PTP bit cell 210.

[0024] A read access through one of the bit lines in a bit line pair does not use the voltage of the remaining bit line, so the resulting read operation is single-ended. Referring again to the PTP SRAM, such an access to read port A then causes the global read bit line grbl of the SRAM 100 (FIG. 1) to remain charged to the system power supply voltage. As shown in FIG. 3, the data out signal dout is then charged high at time t3.

[0025] When the read operation is completed, the read multiplexer clock signal rmp is deasserted following time t2. A write precharge period extends from time t2 to time t4, and in some implementations, a precharge circuit charges bit line ubl0 and complementary bit line ublb0 to the memory power supply voltage during the write precharge period. Therefore, bit line ubl0 is shown in FIG. 3 as remaining charged to the memory power supply voltage during the write precharge period.

[0026] Next, a write port access is made to the PTP bit cell 205 from time t4 to time t5. At or before time t4, the write driver 120 (FIG. 1) couples the bit line ubl0 to the write driver bit line wd. Similarly, the write driver 120 couples the complementary bit line ublb0 to the complementary write driver bit line wdb. To enable the write driver 120 to respond to the byte mask command ibyte_n, a logic gate such as NOR gate 145 as shown in FIG. 1 processes the bit mask command using an active low write clock signal wrclk_n. If the bit cell accessed in the write operation is to be masked as part of a masked byte, the byte mask command signal ibyte_n is asserted to a binary value of logic 1, which results in the output signal bmsk_n of the NOR gate 145 becoming logic 0. If the byte mask command ibyte_n is logic 0, the NOR gate 145 functions to invert the active low write clock signal wrclk_n to form the output signal bmsk_n. During a write operation without byte masking, the write clock signal wrclk_n signal is grounded, which causes the output signal bmsk_n to be logic one. The write driver 120 is configured to couple the bit line ubl0 to the write driver bit line wd only when bmsk_n is logic one. In the following description for the PTP SRAM 100, it will be assumed that bmsk_n is asserted to a logic one value. In this example, the write driver bit line wd is discharged in response to the data input signal din also being discharged. Therefore, the binary state of the complementary write driver bit line wdb becomes a binary one. Once the write driver 120 charges the bit line pair accordingly, the self-timed clock circuit 140 controls the assertion of the word lines WLA0 and WLB0 from time t4 to time t5 to write the data input signal din to the PTP bit cell 205. The access transistors M3 and M4 are both switched on due to the simultaneous word line assertion during the write port access.

[0027] In this example, the write driver bit line wd is discharged, and therefore the bit line ubl0 is discharged during the write port access from time t4 to time t5. The word line assertion period from time t4 to time t5 is long enough so that the data input signal din (in this example, a binary 0) is written into the accessed bit cell. As shown in FIG. 3, the write multiplexer clock signal uwm is asserted before time t4 so that when the word line is asserted at time t4, the bit line voltage can be driven accordingly. In this implementation, the write multiplexer clock signal uwm is an active high signal, which causes it to be charged to the memory power supply voltage. With the release of the word line at time t5, the write multiplexer clock signal uwm can also be released.

[0028] During a read operation, the write multiplexer clock signal uwm is deasserted, which causes the write column multiplexer 125 to be inactive. In this manner, the write driver 120 is prevented from unnecessarily affecting the read operation. Similarly, the read multiplexer address signal rmp is deasserted by charging to the memory power supply voltage during a write operation to keep the read column multiplexer and sense amplifiers 130 unpowered so that the global read bit lines grbl are not disturbed during a write operation.

[0029] The self-timed clock circuit 140 controls the complementary assertion of the write multiplexer address signal uwm and the read multiplexer address signal in response to cycles of the memory clock (clk) signal. In addition, the self-timed clock circuit 140 controls the discharge of the write clock signal wrclk_n to release the write driver 120. The self-timed clock circuit 140 includes various elements such as dummy word lines and dummy bit lines so that the electrical behavior of real word lines and bit lines can be mimicked. The complementary assertion of the read multiplexer clock signal rmp and the write multiplexer clock signal uwm by the self-timed clock circuit 140 prevents the scan mode of operation from scanning through the peripheral logic including the write driver 120, the write column multiplexer 125, and the read column multiplexer and sense amplifiers 130. For example, while the read multiplexer clock signal rmp is asserted, the read column multiplexer and sense amplifiers 130 are active and can be scanned. However, at this time, write column multiplexer 125 is closed due to the complementary deassertion of write multiplexer clock signal uwm. Similarly, while write multiplexer clock signal uwm is asserted, write column multiplexer 125 is open and can be scanned, but at this time, read column multiplexer and sense amplifiers 130 are unpowered due to the complementary deassertion of read multiplexer clock signal rmp.

[0030] The PTP SRAM 100 includes bypass scan logic circuits such as a NOR gate 135 responsive to assertion of a scan mode control signal (scan_n) to bypass the write driver 120, the write column multiplexer 125, and the read column multiplexer and sense amplifier 130 during a scan mode of operation. In the scan mode of operation, the level shifter 105 level-shifts the scan-in signal instead of the data-in signal to form a level-shifted scan-in signal (sin). The NOR gate 135 NORs the level-shifted scan-in signal sin with the scan mode control signal scan_n to control whether the NMOS transistor M2 is conductive to discharge the global read bit line grbl. In this implementation, the scan mode control signal scan_n is an active low signal. The transistor M2 has a source coupled to ground and a drain coupled to the global read bit line grbl. During a functional (non-scan) mode of operation, the scan mode control signal scan_n is charged to the memory power supply voltage, which causes the NOR gate 135 to discharge the gate of the transistor M2. Therefore, the transistor M2 is turned off during the functional operation mode so as not to interfere with any read operation. During the scan operation mode, the scan mode control signal scan_n is asserted by being discharged (scan_n is an active low signal). At this time, the NOR gate 135 can respond to the level-shifted scan-in signal sin. When the level-shifted scan-in signal sin is a binary high, the NOR gate 135 continues to discharge the gate of the transistor M2. Since the global read bit line grbl is precharged before receiving the level-shifted scan-in signal sin, when the level-shifted scan-in signal sin is a binary high, the global read bit line grbl remains charged to the system power supply voltage. During the scan operation mode, the voltage of the global read bit line grbl determines the binary state of the scan-out (sout) signal.Therefore, the sout signal becomes a binary high signal according to the binary high state of the level-shifted scan-in signal sin. However, if the level-shifted scan-in signal sin is a binary low signal (discharged to ground), the NOR gate 135 switches on the transistor M2 and discharges the sout signal. At this time, the level-shifted scan-in signal sin can be passed as the sout signal, but the resulting scan completely bypasses the write driver 120, the write column multiplexer 125, and the read column multiplexer and sense amplifier 130 during the scan operation mode. Therefore, such a PTP scan cannot detect the operation errors of these peripheral logic components. Next, the PTP SRAM with an improved scan mode for scanning peripheral logic components will be described in more detail.

[0031] To provide an exhaustive scan of peripheral logic components, an SRAM is disclosed having a scan mode of operation that scans peripheral logic including write drivers, write column multiplexers, and read column multiplexers. The following description will be directed to a PTP SRAM having this improved scan mode of operation, but it will be understood that other types of six-transistor bit cell SRAMs, such as single-port SRAMs incorporating both read and write multiplexers, may also implement the scan mode of operation of the present disclosure. In a PTP SRAM, the PTP bit cells may be implemented as described for PTP bit cells 205 and 210. Similarly, the timing of assertion of the read multiplexer clock signal rmp and the timing of assertion of the write multiplexer clock uwm during functional mode may be performed as described for FIG. 3. An exemplary PTP SRAM 400 having this robust peripheral logic scan capability is shown in FIG. 4. As described for PTP SRAM 100, level shifter 105 functions to level shift the data-in signal from the system power domain to the memory power domain to form a level-shifted din signal during functional operation mode. Similarly, level shifter 105 level shifts the scan-in signal to form a level-shifted scan-in signal (sin) during scan operation mode. Inverter 110 inverts the level-shifted din signal to form a level-shifted complementary data-in signal (dinb) during functional operation mode. Similarly, inverter 110 inverts the level-shifted scan-in signal sin to form a level-shifted complementary scan-in signal (sinb) during scan operation mode.

[0032] A scan mode controller (not shown) controls whether the scan mode of operation is active by discharging the active-low scan mode control signal scan_n. The following description will focus on the scan mode of operation. To force the write driver 460 to a transparent state (active or open state) during the scan mode of operation, a logic gate such as NAND gate 405 processes the scan mode control signal scan_n with the write clock signal wrclk_n. When the scan_n signal is logic 0 in the scan mode of operation, the output signal of NAND gate 405 is forced to logic 1. An inverter 415 then inverts the output signal of NAND gate 405 and outputs a logic 0 signal. A NOR gate 420 NORs the output signal of inverter 415 with the byte mask signal ibyte_n to form the bmsk_n signal. During the scan mode of operation, the byte mask signal ibyte_n is at logic 0. Therefore, the bmsk_n signal is asserted to logic 1 when the scan_n signal is logic 0, forcing the write driver 460 to an enabled state.

[0033] In one implementation, the write driver 460 includes a NAND gate 430 that NANDs the level-shifted scan-in signal sin and the bmsk_n signal. When the bmsk_n signal is asserted to a logic one value during the scan mode of operation due to discharging of the scan mode control signal scan_n, the NAND gate 430 functions as an inverter to drive the gate of a p-type metal-oxide-semiconductor (PMOS) transistor P2 having a source coupled to a power supply node for the memory power supply voltage and a drain coupled to a write driver bit line wd. When the level-shifted scan-in signal sin is a binary one, the transistor P2 switches on in response to the binary low output signal of the NAND gate 430 to charge the write driver bit line wd to the power supply voltage.

[0034] Inverter 440 inverts the output signal of NAND gate 430 and drives the gate of NMOS transistor M7, which has its source coupled to ground and its drain coupled to the complementary write driver bit line wdb. When the level-shifted scan-in signal sin is a binary 1, the output signal of inverter 440 will also be asserted to a binary 1. Transistor M7 will then be switched on and will discharge the complementary write driver bit line wdb accordingly. Conversely, when the level-shifted scan-in signal sin is a binary 0, the output signal from NAND gate 430 will be a binary 1, which forces transistor P2 off so that it cannot affect the charge of the write driver bit line wd. Similarly, the binary high state of the output signal from NAND gate 430 is inverted by inverter 440, which also forces transistor M7 off so that it cannot affect the charge of the complementary write driver bit line wd.

[0035] The write driver 460 may also include a NAND gate 425 that NANDs the level-shifted complementary scan-in signal sinb with the bmsk_n signal. When the bmsk_n signal is asserted to a logic one value during the scan mode of operation due to the discharge of the scan_n signal, the NAND gate 425 functions as an inverter to drive the gate of a PMOS transistor P1 having a source coupled to a power supply node for the memory power supply voltage and a drain coupled to a complementary write driver bitline wdb. When the level-shifted complementary scan-in signal sinb is a binary one, the transistor P1 switches on in response to the binary low output signal of the NAND gate 425 to charge the complementary write driver bitline to the memory power supply voltage.

[0036] Inverter 435 inverts the output signal of NAND gate 425 and drives the gate of NMOS transistor M8, which has its source coupled to ground and its drain coupled to the write driver bit line wd. If the level-shifted complementary scan-in signal sinb is a binary 1, then the output signal of inverter 435 will also be asserted to a binary 1. Transistor M8 will then be switched on and will discharge the complementary write driver bit line wd accordingly. Conversely, if the level-shifted complementary scan-in signal sinb is a binary 0, then the output signal from NAND gate 425 will be a binary 1, which forces transistor P1 off so that it cannot affect the charge of the write driver bit line wd. Similarly, the binary high state of the output signal from NAND gate 425 is inverted by inverter 435, which also forces transistor M8 off so that it cannot affect the charge of the complementary write driver bit line wd.

[0037] Therefore, write driver 460 is responsive to the level-shifted scan-in signal sin, which causes write driver bit lines wd and wdb to be charged accordingly. When the level-shifted scan-in signal sin is a binary 1 signal, write driver 460 discharges the complementary write driver bit line wdb and charges the write driver bit line wd to the memory power supply voltage. Conversely, when the level-shifted scan-in signal sin is a binary 0 signal, write driver 460 discharges the write driver bit line wd and charges the complementary write driver bit line wdb to the memory power supply voltage.

[0038] Regarding the timing of the read multiplexer clock signal rmp, it has already been described how the self-timed clock circuit 140 of the PTP SRAM 100 asserts the read multiplexer clock signal rmp from about time t1 to about time t2 in FIG. 3. Similarly, the self-timed clock circuit 140 asserts the write multiplexer clock signal uwm from time t4 to time t5. This "double pumped" timing may be maintained by the self-timed clock circuit 450 of the PTP SRAM 400 with respect to the read multiplexer clock signal rmp and the write multiplexer clock signal uwm'. The self-timed clock circuit 450 may include a logic gate such as a NOR gate 455 (shown separately from the self-timed clock circuit 450 for clarity of illustration) to activate the write multiplexer 465 during the scan mode of operation while the read multiplexer clock signal rmp is asserted. It will be understood that other types of logic gates (or combinations of logic gates) may be used in alternative implementations, and the logic circuits disclosed herein, such as NOR gate 455, are merely exemplary. NOR gate 455 NORs the read multiplexer clock signal rmp with an active-low scan mode control signal scan_n, which is asserted by being grounded to activate a scan mode of operation. Self-timed clock circuit 450 includes logic gates, such as OR gate 475, which NORs the output signal of NOR gate 455 with write multiplexer clock signal uwm' to control the binary state of write multiplexer clock signal uwm. Thus, write multiplexer clock signal uwm will be asserted to the memory power supply voltage substantially simultaneously with the active-low assertion of read multiplexer clock signal rmp.During the functional mode of operation, the self-timed clock circuit 450 may control the read and write multiplexer clock signals rmp and uwm in the "double pumping" manner described with respect to FIG. 3, whereby the read multiplexer clock signal rmp is asserted during a first portion of the memory clock signal (clk) and the write multiplexer clock signal uwm is asserted during a second portion of the memory clock signal. Note that in the functional mode, the NOR gate 455 is unpowered during write operations so that it does not interfere with write cycle timing. Similarly, the active-low scan mode control signal scan_n is charged to the memory power supply voltage during functional mode, whereby the output signal of the NOR gate 455 is discharged during functional mode read operations, again so that it does not interfere with write cycle timing.

[0039] The write multiplexer 465 includes a first switch, such as a first transmission gate T1, that is conductive in response to assertion of the write multiplexer clock signal uwm (and an active low assertion of a complementary write multiplexer clock signal uwmn formed by the inverse of the write multiplexer clock signal uwm). When the transmission gate T1 is open (conducting), the write driver bitline wd is coupled to the 0th upper bank bitline ubl0. In this manner, the 0th upper bank bitline ubl0 will be driven to the same binary stage of the level-shifted scan-in signal sin. Similarly, the write multiplexer 465 includes a second transmission gate T2 that, when open, couples the complementary write driver bitline wdb to the 0th upper bank complementary bitline ublb0. The transmission gate T2 opens in response to assertion of the write multiplexer clock signal uwm and an active low assertion of the complementary write multiplexer clock signal uwmn.

[0040] The combined read multiplexer and sense amplifier 470 includes a NAND gate 445 that NANDs the 0th upper bank bitline, ubl0, with the corresponding 0th lower bank bitline, lbl0. The NAND gate 445 is powered through a PMOS transistor P3 that is switched on in response to an active low assertion of a read multiplexer clock signal, rmp. The drain of transistor P3 couples to a power supply node for the NAND gate 445, whereas the source of transistor P3 couples to a power supply node for the memory power supply voltage. The read multiplexer clock signal, rmp, drives the gate of transistor P3 to control whether transistor P3 powers the NAND gate 445. As discussed above, a bank is a contiguous array of bit cells. The lower bank is not shown for clarity of illustration. Prior to receipt of the level-shifted scan-in signal, sin, the bitlines in the upper and lower banks are precharged to the memory power supply voltage. Similarly, the global read bitline, grbl, is precharged to the system power supply voltage. When the level-shifted scan-in signal sin is charged to the memory power supply voltage during the scan operation mode, the 0th upper bank bit line ubl0 will remain charged to the memory power supply voltage, which causes the output signal of the NAND gate 445 to be discharged to ground. The output signal of the NAND gate 445 controls the gate of the NMOS transistor M1 described for the PTP SRAM 100. Therefore, the global read bit line grbl will remain charged to the system power supply voltage in response to the high state of the level-shifted scan-in signal sin. However, when the level-shifted scan-in signal sin is a binary 0, the output signal of the NAND gate 445 will be charged to the memory power supply voltage in response to the active low assertion of the read multiplexer clock signal rmp. At this time, the transistor M1 is switched on, which causes the global read bit line grbl to be discharged to ground accordingly.The read multiplexer clock signal rmp also drives the gate of an NMOS transistor M9, which has its drain coupled to the gate of transistor M1 and its source coupled to ground, to keep transistor M1 off while the active low read multiplexer clock signal rmp is deasserted by being charged to the power supply voltage. Therefore, transistor M9 is switched on while the read multiplexer clock signal rmp is being charged to the power supply voltage to keep transistor M1 off. A read multiplexer and sense amplifier (not shown), similar to read multiplexer and sense amplifier 470, couples to the 0th upper bank complementary bitline ublb0 to control the binary state of the complementary global read bitline (not shown).

[0041] Consider the advantages of the periphery logic scan of the PTP SRAM 400. Not only can the peripheral logic components such as the write driver 460, the write multiplexer 465, and the read multiplexer and sense amplifier 470 be fully scanned, but the clock margin is essentially the same as during functional mode. In contrast, the bypass scan through the NOR gate 135 and the transistor M2 has a very different clock margin compared to that achieved by the PTP SRAM 100 during functional mode. In addition, the periphery logic scan of the PTP SRAM 400 does not add any significant load to the global read bit line grbl. In contrast, the transistor M2 increases the load in the global read bit line grbl in the PTP SRAM 100.

[0042] 5 shows some example waveforms for a periphery logic scan in PTP SRAM 400. In scan operation mode, word lines WL0 and WLB0 to bit cells 205 remain in a discharged state. Assertion of the memory clock signal at time t0 triggers self-timed clock circuit 450 to discharge the active-low read multiplexer clock signal from time t1 to time t2, as would be performed during a read operation in functional mode. In addition, self-timed clock circuit 450 also asserts write multiplexer clock signal uwm from time t1 to time t2 as well. In contrast, self-timed clock circuit 440 only asserts write multiplexer clock signal uwm during the write operation portion of the memory clock cycle in functional mode.

[0043] Referring back to the PTP SRAM 400, the self-timed clock circuit 450 is configured to control the word lines WLA0 and WLB0 for the 0th row bit cell 205 as described for the timing waveforms of Figure 3. In a read access to port A, the self-timed clock circuit 450 controls the word lines such that only the word line WLA0 is charged to the memory power supply voltage, whereas the word line WLB0 remains in a discharged state. During a read access to port A of the 0th row bit cell 205, the self-timed clock circuit 450 may control the word lines in a read access to port B such that only the word line WLB1 is charged to the memory power supply voltage, whereas the word line WLA1 remains in a discharged state.

[0044] A method of operation for a periphery logic scan in a PTP memory will now be described with reference to the flow chart of FIG. 6. The method includes an operation 600 of asserting a write multiplexer clock signal while the read multiplexer clock signal is asserted during a scan mode of operation. A simultaneous active low assertion of the read multiplexer clock signal rmp and an active high assertion of the write multiplexer clock signal uwm by the self-timed clock circuit 450 is an example of operation 600. The method further includes an operation 605 of coupling a scan-in signal to a first bit line through a write multiplexer in response to the assertion of the write multiplexer clock signal. An opening of a transmission gate T1 in response to an assertion of the write multiplexer clock signal uwm to couple a level-shifted scan-in signal sin to bit line ubl0 is an example of operation 605. Finally, the method also includes an operation 610 of coupling a scan-in signal from the first bit line through a read multiplexer to a global read bit line in response to an assertion of the read multiplexer signal. The coupling of the level-shifted scan-in signal sin to the global read bit line grbl through the read multiplexer and sense amplifier 470 is an example of an operation 610.

[0045] The memories disclosed herein may be incorporated into a variety of electronic systems. For example, as shown in Figure 7, a cell phone 700, a laptop 705, and a tablet PC 710 may all include memories having peripheral logic scanning according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with memories constructed according to the present disclosure.

[0046] The disclosure will now be summarized in the following illustrative clauses:

[0047] Clause 1. A memory, a write driver configured to control a binary state of the write driver bit lines during the scan mode of operation in response to a binary state of the scan-in signal during the scan mode of operation; a write multiplexer configured to couple the write driver bit lines to the first bit lines in response to assertion of a write multiplexer clock signal; a read multiplexer configured to couple the first bit line to a global read bit line in response to assertion of a read multiplexer clock signal; a clock circuit configured to assert a write multiplexer clock signal substantially simultaneously with a read multiplexer clock signal during a scan mode of operation; A memory comprising:

[0048] Clause 2. The memory of clause 1, wherein the clock circuit includes a logic gate configured to assert a write multiplexer clock signal during a scan mode of operation in response to assertion of a read multiplexer clock signal and a scan mode control signal.

[0049] Clause 3. The memory of clause 2, wherein the logic gate comprises a NOR gate.

[0050] Clause 4. The memory of any one of clauses 1 to 3, wherein the write driver is further configured to receive a complementary scan-in signal during a scan mode of operation to control the binary state of the complementary write driver bit line.

[0051] Clause 5. The memory of clause 4, wherein the write multiplexer is further configured to couple the complementary write driver bitline to the first complementary bitline in response to assertion of a write multiplexer clock signal.

[0052] Clause 6. The memory of clause 5, wherein the write multiplexer includes a first transmission gate coupled between the write driver bit line and the first bit line, and a second transmission gate coupled between the complementary write driver bit line and the first complementary bit line.

[0053] Article 7. a first bit cell including a first pair of cross-coupled inverters having an output node for a first bit and a complementary output node for the complement of the first bit, a first access transistor coupled between the output node and the first bit line, and a second access transistor coupled between the complementary output node and the first complementary bit line; a first word line coupled to the gate of the first access transistor; The memory of clause 5 or 6, further comprising: a second word line coupled to a gate of the second access transistor, wherein the clock circuit is further configured to control assertion of the first word line to perform a single-ended read of the first bit through the first bit line during a first portion of a first cycle of the memory clock signal, and to assert both the first word line and the second word line to perform a differential write of the second bit to the first bit cell during a second portion of the first cycle of the memory clock signal.

[0054] Clause 8. A memory according to any one of clauses 1 to 7, wherein the clock circuit is a self-timed clock circuit.

[0055] Clause 9. The memory of clause 7, wherein the first access transistor and the second access transistor each comprise an n-type metal oxide semiconductor (NMOS) transistor.

[0056] Article 10. a second bitcell including a third access transistor coupled between an output node of the second bitcell and the first bitline, and a fourth access transistor coupled between a complementary output node of the second bitcell and the first complementary bitline; a third word line coupled to the gate of the third access transistor; The memory of clause 7, further comprising: a fourth word line coupled to a gate of the fourth access transistor, wherein the clock circuit is further configured to control assertion of the fourth word line to perform a single-ended read to the second bit cell through the first complementary bit line during a first portion of a first cycle of the memory clock signal.

[0057] Clause 11. The memory of any one of clauses 1 to 10, wherein the read multiplexer further comprises a sense amplifier.

[0058] Article 12. a global read bit line; 12. The memory of clause 11, further comprising: a transistor coupled between the global read bit line and ground, wherein the sense amplifier includes a NAND gate configured to drive a gate of the transistor.

[0059] Clause 13. The memory of clause 12, wherein the transistor is an NMOS transistor having a source coupled to ground and a drain coupled to a global read bitline.

[0060] Clause 14. The memory of clause 2, wherein the write driver is further configured to control the binary state of the write driver bit lines during a scan mode of operation in response to the binary state of a bit mask signal.

[0061] Clause 15. A scanning method for a memory, comprising: asserting a write multiplexer clock signal while a read multiplexer clock signal is asserted during a scan mode of operation; coupling the scan-in signal through the write multiplexer to the first bit line in response to assertion of a write multiplexer clock signal; in response to assertion of a read multiplexer signal, coupling a scan-in signal from the first bit line through the read multiplexer to a global read bit line; A scanning method including:

[0062] Article 16. 16. The scanning method of clause 15, further comprising receiving a memory clock signal edge at a clock circuit, wherein assertion of the write multiplexer clock signal and assertion of the read multiplexer clock signal are responsive to the memory clock signal edge.

[0063] Clause 17. The scanning method of clause 16, wherein assertion of the write multiplexer clock signal is further in response to assertion of a scan mode control signal.

[0064] Article 18. The scanning method of any one of clauses 15 to 17, further comprising performing a single-ended read to the first bit cell through the first bit line by asserting a first word line of a first pair of word lines for the first bit cell during a first portion of a first memory clock cycle, wherein performing the single-ended read further comprises asserting a read multiplexer clock signal while the write multiplexer clock signal is not asserted.

[0065] Article 19. The scanning method of claim 18, further comprising asserting both a first word line and a second word line of the first pair of word lines to write to the first bit cell through the first bit line and through the first complementary bit line during a second portion of the first memory clock cycle, and performing the write to the first bit cell further comprises asserting the write multiplexer clock signal while the read multiplexer clock signal is not asserted.

[0066] Clause 20. A memory comprising: a first switch configured to couple the write driver bit line to the first bit line in response to assertion of a write mux clock signal; a global read bit line; a sense amplifier configured to sense a binary state of the first bit line to control a binary state of a global read bit line in response to assertion of a read multiplexer clock signal; a clock circuit configured to assert a write multiplexer clock signal substantially simultaneously with a read multiplexer clock signal during a scan mode of operation; A memory comprising:

[0067] Article 21. a first transistor coupled between the global read bit line and ground, the sense amplifier comprising: The memory of clause 20, comprising: a first logic gate coupled between the first bit line and a gate of the first transistor, and a second transistor coupled between a power supply node for a memory power supply voltage and a power supply node of the first logic gate, the second transistor configured to switch on in response to assertion of a read multiplexer clock signal.

[0068] Clause 22. The memory of clause 21, wherein the first logic gate comprises a NAND gate.

[0069] Clause 23. The memory of clause 21, wherein the first transistor comprises an NMOS transistor and the second transistor comprises a PMOS transistor.

[0070] Clause 24. A memory according to any one of clauses 20 to 23, wherein the first switch includes a first transmission gate.

[0071] As will be appreciated by those skilled in the art at present, and depending on the specific application at hand, numerous modifications, substitutions, and variations can be made in and to the materials, arrangements, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, and as the specific embodiments illustrated and described herein are merely by way of example of some of the same, the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the following appended claims and their functional equivalents.

Claims

1. A memory, a write driver configured to control a binary state of the write driver bit lines during the scan mode of operation in response to a binary state of the scan-in signal during the scan mode of operation; a write multiplexer configured to couple the write driver bit lines to first bit lines in response to assertion of a write multiplexer clock signal; a read multiplexer configured to couple the first bit line to a global read bit line in response to assertion of a read multiplexer clock signal; a clock circuit configured to assert the write multiplexer clock signal substantially simultaneously with the read multiplexer clock signal during the scan mode of operation; A memory comprising:

2. 2. The memory of claim 1, wherein the clock circuit comprises a logic gate configured to assert the write multiplexer clock signal during the scan mode of operation in response to assertion of the read multiplexer clock signal and a scan mode control signal.

3. The memory of claim 2 , wherein the logic gate comprises a NOR gate.

4. 2. The memory of claim 1, wherein the write drivers are further configured to receive complementary scan-in signals during the scan mode of operation to control binary states of complementary write driver bitlines.

5. 5. The memory of claim 4, wherein the write multiplexer is further configured to couple the complementary write driver bitline to a first complementary bitline in response to the assertion of the write multiplexer clock signal.

6. 6. The memory of claim 5, wherein the write multiplexer includes a first transmission gate coupled between the write driver bit line and the first bit line, and a second transmission gate coupled between the complementary write driver bit line and the first complementary bit line.

7. a first bit cell including a first pair of cross-coupled inverters having an output node for a first bit and a complementary output node for the complement of the first bit, a first access transistor coupled between the output node and the first bit line, and a second access transistor coupled between the complementary output node and the first complementary bit line; a first word line coupled to a gate of the first access transistor; 6. The memory of claim 5, further comprising: a second word line coupled to a gate of the second access transistor, wherein the clock circuit is further configured to control assertion of the first word line to perform a single-ended read of the first bit through the first bit line during a first portion of a first cycle of a memory clock signal, and to assert both the first word line and the second word line to perform a differential write of a second bit to the first bit cell during a second portion of the first cycle of the memory clock signal.

8. 2. The memory of claim 1, wherein the clock circuit is a self-timed clock circuit.

9. 8. The memory of claim 7, wherein the first access transistor and the second access transistor each comprise an n-type metal-oxide-semiconductor (NMOS) transistor.

10. a second bitcell including a third access transistor coupled between an output node of the second bitcell and the first bitline, and a fourth access transistor coupled between a complementary output node of the second bitcell and the first complementary bitline; a third word line coupled to the gate of the third access transistor; 8. The memory of claim 7, further comprising: a fourth word line coupled to a gate of the fourth access transistor, wherein the clock circuit is further configured to control assertion of the fourth word line to perform a single-ended read through the first complementary bit line to the second bit cell during the first portion of the first cycle of the memory clock signal.

11. The memory of claim 1 , wherein the read multiplexer further comprises a sense amplifier.

12. a global read bit line; 12. The memory of claim 11, further comprising: a transistor coupled between the global read bit line and ground, wherein the sense amplifier includes a NAND gate configured to drive a gate of the transistor.

13. 13. The memory of claim 12, wherein the transistor is an NMOS transistor having a source coupled to ground and a drain coupled to the global read bitline.

14. The write driver: The memory of claim 2 , further configured to control the binary state of the write driver bitlines during the scan mode of operation in response to a binary state of a bitmask signal.

15. 1. A scanning method for a memory, comprising: asserting a write multiplexer clock signal while a read multiplexer clock signal is asserted during a scan mode of operation; coupling a scan-in signal through a write multiplexer to a first bitline in response to the assertion of the write multiplexer clock signal; in response to the assertion of the read multiplexer signal, coupling the scan-in signal from the first bit line through a read multiplexer to a global read bit line; A scanning method including:

16. 16. The method of scanning of claim 15, further comprising the step of receiving a memory clock signal edge at a clock circuit, the assertion of the write multiplexer clock signal and the assertion of the read multiplexer clock signal being responsive to the memory clock signal edge.

17. 17. The method of scanning of claim 16, wherein the assertion of the write multiplexer clock signal is further responsive to assertion of a scan mode control signal.

18. 16. The method of claim 15, further comprising performing a single-ended read to the first bit cell through the first bit line by asserting a first word line of a first pair of word lines for a first bit cell during a first portion of a first memory clock cycle, the performing the single-ended read further comprising asserting the read multiplexer clock signal while the write multiplexer clock signal is not asserted.

19. 20. The method of claim 18, further comprising asserting both the first word line and a second word line of the first pair of word lines to write to the first bit cell through the first bit line and through a first complementary bit line during a second portion of the first memory clock cycle, and wherein performing the write to the first bit cell further comprises asserting the write multiplexer clock signal while the read multiplexer clock signal is not asserted.

20. A memory, a first switch configured to couple a write driver bit line to the first bit line in response to assertion of a write mux clock signal; a global read bit line; a sense amplifier configured to sense the binary state of the first bit line to control the binary state of the global read bit line in response to assertion of a read multiplexer clock signal; a clock circuit configured to assert the write multiplexer clock signal substantially simultaneously with the read multiplexer clock signal during a scan mode of operation; A memory comprising:

21. a first transistor coupled between the global read bit line and ground, the sense amplifier further comprising:

21. The memory of claim 20 comprising: a first logic gate coupled between the first bit line and a gate of the first transistor, and a second transistor coupled between a power supply node for a memory power supply voltage and a power supply node of the first logic gate, the second transistor configured to switch on in response to assertion of the read multiplexer clock signal.

22. 22. The memory of claim 21 wherein the first logic gate comprises a NAND gate.

23. 22. The memory of claim 21, wherein the first transistor comprises an NMOS transistor and the second transistor comprises a PMOS transistor.

24. 21. The memory of claim 20, wherein the first switch comprises a first transmission gate.

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