Memory and its manufacturing method, electronic device

Abstract

According to an embodiment of the present disclosure, a memory, a manufacturing method thereof, and an electronic device are provided. [Solution] A memory having a substrate, and word lines, bit lines, and memory cells on one side of the substrate, the memory cells including transistors, the transistors including a semiconductor layer formed by sequentially connecting a source contact region, a semiconductor region, and a drain contact region, a main gate electrode electrically connected to the word line, a source electrode electrically connected to the bit line and the source contact region of the semiconductor layer, a drain electrode electrically connected to the drain contact region of the semiconductor layer, and an auxiliary gate electrode electrically connected to the drain electrode, the orthogonal projection of the main gate electrode onto the substrate and the orthogonal projection of the auxiliary gate electrode onto the substrate at least partially overlap with the orthogonal projection of the semiconductor region in the semiconductor layer onto the substrate. The present disclosure provides a transistor having a main gate electrode, and an auxiliary gate electrode electrically connected to the drain electrode, the auxiliary gate electrode obtaining a fixed potential synchronized with the drain electrode, and providing replenishment control to the semiconductor layer by the fixed potential, thereby optimizing the read / write performance of the memory.

Description

[Technical field]

[0001] This application claims priority based on patent application number 202210351082.9, filed in China on April 2, 2022, which is incorporated herein by reference.

[0002] The present disclosure relates to the field of memory technology, and in particular to a memory and a manufacturing method thereof, and electronic equipment. [Background technology]

[0003] Random Access Memory (RAM) usually includes transistors and memory structures, for example capacitors, where the transistors control read or write tasks to the memory structures. Thus, the performance of the transistors has a significant impact on the read and write performance of the entire memory. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure proposes a memory for improving the read / write performance of the memory, a manufacturing method thereof, and an electronic device. [Means for solving the problem]

[0005] A memory according to a first embodiment has a substrate, and word lines, bit lines, and memory cells on one side of the substrate. The memory cells include transistors. The transistors include a semiconductor layer formed by sequentially connecting a source contact region, a semiconductor region, and a drain contact region, a main gate electrode electrically connected to the word line, a source electrode electrically connected to the bit line and the source contact region of the semiconductor layer, a drain electrode electrically connected to the drain contact region of the semiconductor layer, and an auxiliary gate electrode electrically connected to the drain electrode. An orthogonal projection of the main gate electrode onto the substrate and an orthogonal projection of the auxiliary gate electrode onto the substrate each at least partially overlap with an orthogonal projection of the semiconductor region in the semiconductor layer onto the substrate. In some embodiments, the main gate electrode is provided between the substrate and the semiconductor layer, or the main gate electrode is located on a side of the semiconductor layer remote from the substrate. In some embodiments, the main gate electrode and the auxiliary gate electrode are located on opposite sides of the semiconductor layer. In some embodiments, the memory cell further comprises a memory structure, the memory structure including a capacitive memory structure formed between the auxiliary gate electrode and the first electrode. In some embodiments, the first electrode is a source electrode, and an orthogonal projection of the source electrode onto the substrate and an orthogonal projection of the auxiliary gate electrode onto the substrate partially overlap with each other.

[0006] In some embodiments, the main gate electrode is located on a side of the semiconductor layer remote from the substrate, the auxiliary gate electrode is located between the substrate and the semiconductor layer, and the first electrode is located between the substrate and the auxiliary gate electrode.

[0007] In some embodiments, the main gate electrode is located between the substrate and the semiconductor layer, the auxiliary gate electrode is located on a side of the semiconductor layer remote from the substrate, and the first electrode is located on a side of the auxiliary gate electrode remote from the substrate.

[0008] In some embodiments, the transistor further includes a first medium layer located between the semiconductor layer and the main gate electrode, and a second medium layer located between the auxiliary gate electrode and the semiconductor layer and between the auxiliary gate electrode and the source electrode, the second medium layer partially overlapping an orthogonal projection of the source electrode onto the substrate and an orthogonal projection of the auxiliary gate electrode onto the substrate.

[0009] In some embodiments, the main gate electrode is located on a side of the semiconductor layer remote from the substrate, the auxiliary gate electrode is located between the substrate and the semiconductor layer, the transistor includes a first insulating layer, a first through hole and a second through hole, the first insulating layer is located on a side of the main gate electrode remote from the substrate, the bit line is located on a side of the first insulating layer remote from the main gate electrode, the first through holes penetrate the first insulating layer and the first medium layer, respectively, and are connected to the bit line and a source contact region of the semiconductor layer, respectively, a source electrode is formed in at least a portion of the entirety including the first through hole and the source contact region of the semiconductor layer, the second through holes penetrate the first insulating layer, the first medium layer and the second medium layer, respectively, and are connected to the drain contact region of the semiconductor layer and the auxiliary gate electrode, respectively, and a drain electrode is formed in at least a portion of the entirety of the drain contact region including the second through hole and the semiconductor layer.

[0010] In some embodiments, the main gate electrode is located between the substrate and the semiconductor layer, the auxiliary gate electrode is located on a side of the semiconductor layer away from the substrate, the transistor includes a first insulating layer, a first through hole and a second through hole, the first insulating layer is located on a side of the auxiliary gate electrode away from the substrate, the bit line is located on a side of the first insulating layer away from the auxiliary gate electrode, the first through holes penetrate the first insulating layer and the second medium layer, respectively, and are connected to the bit line and a source contact region of the semiconductor layer, a source electrode is formed in at least a portion of the entire structure including the first through hole and the source contact region of the semiconductor layer, the second through hole penetrates the first insulating layer and the second medium layer, respectively, and is connected to the auxiliary gate electrode and the drain contact region of the semiconductor layer, and a drain electrode is formed in at least a portion of the entire structure including the second through hole and the drain contact region of the semiconductor layer. In some embodiments, the word lines are provided in the same layer as the main gate electrodes and in a different layer than the bit lines.

[0011] In some embodiments, the semiconductor layer comprises at least one of a metal oxide semiconductor, monocrystalline silicon, polycrystalline silicon, and amorphous silicon, and the metal oxide semiconductor comprises at least one element of indium, gallium, zinc, tin, and tungsten.

[0012] In some embodiments, at least two memory cells are stacked vertically relative to a substrate and / or at least two memory cells are arrayed on one side of the substrate, with main gate electrodes of transistors in at least two memory cells in the same row electrically connected to the same word line and source electrodes of transistors in at least two memory cells in the same column electrically connected to the same bit line. An electronic device according to a second aspect includes the memory according to any one of the above aspects.

[0013] A method for manufacturing a memory according to a third embodiment includes sequentially forming, on one side of a substrate, an auxiliary gate electrode, a second medium layer, a semiconductor layer, a first medium layer, a main gate electrode, a word line connected to the main gate electrode, and a first insulating layer, the semiconductor layer being formed by sequentially connecting a source contact region, a semiconductor region, and a drain contact region, the first insulating layer and the first medium layer being sequentially etched to obtain a first through hole exposing at least a part of the source contact region of the semiconductor layer, the first insulating layer, the first medium layer, and the second medium layer being sequentially etched to obtain a second through hole exposing at least a part of the drain contact region of the semiconductor layer and a part of the auxiliary gate electrode, a conductive material being formed in the first through hole and the second through hole such that a first via connecting the source contact region of the semiconductor layer is formed in the first through hole and a second via connecting the auxiliary gate electrode and the drain contact region of the semiconductor layer is formed in the second through hole, and a bit line is formed on the first via.

[0014] In some embodiments, sequentially forming an auxiliary gate electrode, a second medium layer, a semiconductor layer, a first medium layer, a main gate electrode, a word line connected to the main gate electrode, and a first insulating layer on one side of a substrate means that an auxiliary gate electrode is formed on one side of the substrate, a second medium layer is formed on the auxiliary gate electrode and the exposed substrate, a semiconductor layer is formed on the second medium layer such that the orthogonal projection of a semiconductor region of the semiconductor layer onto the substrate and the orthogonal projection of a source contact region of the semiconductor layer onto the substrate each partially overlap the orthogonal projection of the auxiliary gate electrode onto the substrate, and the source contact region and drain contact region of the semiconductor layer are made conductive.

[0015] In some embodiments, sequential etching of the first insulating layer and the first medium layer to obtain a first through hole exposing at least a portion of the source contact region of the semiconductor layer, and sequential etching of the first insulating layer, the first medium layer, and the second medium layer to obtain a second through hole exposing at least a portion of the drain contact region of the semiconductor layer and a portion of the auxiliary gate electrode are performed in a synchronous manner.

[0016] A fourth embodiment of the method for manufacturing a memory includes sequentially manufacturing a main gate electrode, a word line connected to the main gate electrode, a first medium layer, a semiconductor layer, a second medium layer, an auxiliary gate electrode, and a first insulating layer on one side of a substrate, the semiconductor layer being formed by connecting a source contact region, a semiconductor region, and a drain contact region in that order, the first insulating layer and the second medium layer being sequentially etched to obtain a first through hole exposing at least a part of the source contact region of the semiconductor layer, the first insulating layer and the second medium layer being sequentially etched to obtain a second through hole exposing a part of the auxiliary gate electrode and at least a part of the drain contact region of the semiconductor layer, a conductive material being formed in the first through hole and the second through hole such that a first via connecting the source contact region of the semiconductor layer is formed in the first through hole and a second via connecting the auxiliary gate electrode and the drain contact region of the semiconductor layer is formed in the second through hole, and a bit line is fabricated on the first via.

[0017] In some embodiments, sequentially manufacturing a main gate electrode, a word line connected to the main gate electrode, a first medium layer, a semiconductor layer, a second medium layer, an auxiliary gate electrode, and a first insulating layer on one side of a substrate means manufacturing a main gate electrode and a word line connected to the main gate electrode on one side of a substrate, manufacturing a first medium layer on the main gate electrode, the word line connected to the main gate electrode, and the exposed substrate, fabricating a semiconductor layer on the first medium layer such that an orthogonal projection of a semiconductor region of the semiconductor layer onto the substrate and an orthogonal projection of the main gate electrode onto the substrate partially overlap, a source contact region and a drain contact region of the semiconductor layer are made conductive, fabricating a second medium layer on the semiconductor layer and the exposed first medium layer, and fabricating an auxiliary gate electrode on the second medium layer such that an orthogonal projection of the auxiliary gate electrode onto the substrate partially overlaps with an orthogonal projection of a semiconductor region of the semiconductor layer onto the substrate and an orthogonal projection of a source contact region of the semiconductor layer onto the substrate, respectively.

[0018] In some embodiments, sequential etching of the first insulating layer and the second medium layer to obtain a first through hole exposing at least a portion of the source contact region of the semiconductor layer and sequential etching of the first insulating layer and the second medium layer to obtain a second through hole exposing a portion of the auxiliary gate electrode and at least a portion of the drain contact region of the semiconductor layer are performed synchronously. Effect of the Invention

[0019] The advantageous technical effects of the technology provided by the present disclosure include optimizing the configuration of the memory. Specifically, the transistor includes a main gate electrode that can realize conductivity control for the semiconductor layer, and an auxiliary gate electrode is introduced to provide conductivity control for the semiconductor layer, and the auxiliary gate electrode is electrically connected to the drain electrode, so that the auxiliary gate electrode can obtain a fixed potential synchronized with the drain electrode, which provides additional control for the semiconductor layer, and since the auxiliary gate electrode is not electrically connected to the source electrode, it can function as a negative bias for the threshold voltage during the read phase. This improves the performance of the transistor and optimizes the read and write performance of the memory.

[0020] Regarding the back gate electrode being connected to the drain electrode to improve the read / write performance, the auxiliary gate electrode is not connected to any electrode other than the drain electrode, and is located on the other side of the semiconductor layer but on both sides of the semiconductor layer with respect to the main gate electrode, and the back gate electrode of the present application is not a floating gate electrode, so it needs a fixed potential, but the potential must be synchronized with the drain electrode, which is suitable for memory read / write scenes, and the back gate electrode of the present application is not connected to the source electrode. This auxiliary gate electrode acts as a negative bias of Vth during the read stage.

[0021] Certain aspects and advantages of the disclosure will become apparent from the following description or will become apparent from practice of the present application. [Brief description of the drawings]

[0022] The above-mentioned disclosure and / or additional aspects and advantages will become apparent from the following detailed description of the embodiments based on the accompanying drawings. [Figure 1] FIG. 1 is a circuit diagram of a conventional memory cell. [Diagram 2] FIG. 2 is a circuit configuration diagram of a memory according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a circuit configuration diagram of a memory cell according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a configuration of a memory according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram showing a configuration of a memory cell according to a first embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing a configuration of a memory cell according to a second embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram showing a configuration of a memory cell according to a third embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing a configuration of a memory cell according to a fourth embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram illustrating a block configuration of an electronic device according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram showing a flow of a manufacturing method of a memory according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram showing a flow of a manufacturing method of another memory according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram showing a film layer configuration after step S301 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram showing a film layer configuration after step S302 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 14]FIG. 14 is a diagram showing a film layer configuration after step S303 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a diagram showing a film layer configuration after step S304 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram showing a film layer configuration after step S305 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing a film layer configuration after step S306 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram showing a film layer configuration after step S307 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram showing a film layer configuration after step S308 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram showing a film layer configuration after step S309 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 21] FIG. 21 is a diagram showing a film layer configuration after step S310 in a specific method for manufacturing a memory according to an embodiment of the present disclosure. [Figure 22] FIG. 22 is a diagram illustrating transfer characteristics of transistors when different data are written in the memory according to the embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the embodiments described below with reference to the drawings are illustrative descriptions for explaining the embodiments of the present disclosure, and needless to say, do not limit the technical idea of ​​one embodiment of the present disclosure.

[0024] Those skilled in the art will also understand that the singular terms "a", "one", "said" and "the" as used herein include the plural form unless otherwise specified. Furthermore, the term "comprises" as used in the specification of the present disclosure means the presence of the feature, integer, step, operation, element and / or component, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported in the field of the present technology. Note that when one element is referred to as being "connected" or "coupled" to another element, it may mean that one element is directly connected or coupled to the other element, or that one element and the other element are connected to each other via an intermediate element. In addition, "connected" or "coupled" as used herein may include either wireless connection or wireless coupling. "And / or" as used herein means at least one of the items defined by the term, for example, "A and / or B" may be realized as "A", "B", or "A and B".

[0025] As shown in Figure 1, the idea of ​​this disclosure is that a DRAM memory cell 10 is typically a 1T1C configuration consisting of one transistor and one capacitor. When the transistor is off, the charge stored in the capacitor is gradually lost due to current leakage across the channel, and frequent refresh is usually required to ensure the validity of the stored data.

[0026] Currently mainstream DRAM needs to be designed with a sufficiently large capacity in order to lower the refresh rate, but this makes it difficult to make the DRAM structure compact, resulting in a low degree of integration.

[0027] In the embodiment of the present disclosure, the memory 1 is an access memory having a memory array including one memory cell 10. For example, one memory cell 10 in one memory array of a dynamic random access memory (DRAM) or other type of memory 1 is used. Of course, the memory cell 10 is not limited to a memory cell 10 in a memory array, and may be at least any one of a plurality of memory cells 10 not in an array format.

[0028] Each memory array includes at least a row and column distribution of memory cells 10 , with each memory cell 10 including at least one transistor, at least one word line 30 , and at least one bit line 20 .

[0029] In some embodiments, the memory cell 10 may include one transistor, one memory 1 , one word line 30 and one bit line 20 . In some other embodiments, memory cell 10 may include only one transistor but two bit lines 20 . Also, in some embodiments, there may be less than one transistor.

[0030] In the memory cell 10 proposed by the present disclosure, the transistor includes a main gate electrode 105 capable of controlling the conductivity of the semiconductor layer 103, and an auxiliary gate electrode 101 is introduced to provide conductivity control to the semiconductor layer 103, and the auxiliary gate electrode 101 is electrically connected to the drain electrode. This allows the auxiliary gate electrode 101 to obtain a fixed potential synchronized with the drain electrode, and this fixed potential provides supplementary control to the semiconductor layer 103. In addition, since the auxiliary gate electrode 101 is not electrically connected to the source electrode, it can function as a negative bias of the threshold voltage in the read stage. This improves the performance of the transistor and further optimizes the read / write performance of the memory 1. The concept of the present invention will now be described with reference to specific examples.

[0031] The present application has been made to solve the above problems of the conventional technology, and provides a memory, a manufacturing method thereof, and an electronic device. As shown in Figures 2 to 8, a memory 1 according to an embodiment of the present disclosure includes a substrate 200, and word lines 30, bit lines 20, and memory cells 10 on the substrate 200 side.

[0032] The memory cell 10 includes a transistor, which has a semiconductor layer 103 , a main gate electrode 105 , a source electrode, a drain electrode, and an auxiliary gate electrode 101 . The semiconductor layer 103 is formed by sequentially connecting a source contact region 1031, a semiconductor region 1033, and a drain contact region 1032. The main gate electrode 105 is electrically connected to a word line 30 . The source electrode is electrically connected to the bit line 20 and a source contact region 1031 of the semiconductor layer 103, respectively. The drain electrode is electrically connected to a drain contact region 1032 of the semiconductor layer 103 . The auxiliary gate electrode 101 is electrically connected to the drain electrode.

[0033] Here, the orthogonal projection of the main gate electrode 105 onto the substrate 200 and the orthogonal projection of the auxiliary gate electrode 101 onto the substrate 200 overlap at least a part of the orthogonal projection of the semiconductor region 1033 of the semiconductor layer 103 onto the substrate 200, respectively.

[0034] The memory 1 provided by this embodiment is an optimized configuration of the memory 1, specifically, the transistor includes a main gate electrode 105 capable of realizing conductivity control with respect to the semiconductor layer 103, and an auxiliary gate electrode 101 is introduced to provide conductivity control to the semiconductor layer 103, and the auxiliary gate electrode 101 is electrically connected to the drain electrode. This allows the auxiliary gate electrode 101 to obtain a fixed potential synchronized with the drain electrode, and this fixed potential provides supplementary control to the semiconductor layer 103. In addition, since the auxiliary gate electrode 101 is not electrically connected to the source electrode, it can function as a negative bias of the threshold voltage in the read stage. The performance of the transistor can be improved, and the read / write performance of the memory 1 can be optimized.

[0035] In addition, the auxiliary gate electrode 101 in this embodiment is electrically connected to the drain electrode and has a fixed potential synchronized with the drain electrode, and therefore is not a floating gate.

[0036] 6 and 8, the main gate electrode 105 is located between the substrate 200 and the semiconductor layer 103. That is, the transistor may adopt a bottom gate structure.

[0037] 5 and 7, the main gate electrode 105 is located on the side of the semiconductor layer 103 that is farther from the substrate 200. That is, the transistor may adopt a top-gate structure.

[0038] Based on the above possible embodiment, in a further embodiment, as shown in FIG. 5 to FIG. 8, the main gate electrode 105 and the auxiliary gate electrode 101 are disposed on both sides of the semiconductor layer 103. This reduces mutual interference between the main gate electrode 105 and the auxiliary gate electrode 101, and improves the effective area where the main gate electrode 105 and the auxiliary gate electrode 101 act on the semiconductor layer 103, which is advantageous for improving the performance of the transistor. Specifically, when the transistor has a bottom gate structure, the main gate electrode 105 is located between the substrate 200 and the semiconductor layer 103, and the auxiliary gate electrode 101 is located on the side of the semiconductor layer 103 farther from the substrate 200. When the transistor has a top gate structure, the auxiliary gate electrode 101 is located between the substrate 200 and the semiconductor layer 103, and the main gate electrode is located on the side of the semiconductor layer 103 farther from the substrate 200.

[0039] The idea of ​​the present disclosure further includes a memory cell of a dynamic random access memory (DRAM) that typically includes a transistor and a capacitor typically realized by a capacitive electrode, such as a 1T1C structure. When the transistor is in an off state, there is a current leakage phenomenon across the channel, and at least a part of the charge stored in the capacitor gradually flows out due to the leakage current, so the stored data must be refreshed frequently to ensure the validity of the stored data. In DRAM products, the area of ​​the capacitive electrode can be increased to increase the storage capacitance and reduce the refresh rate, but the increased area of ​​the capacitive electrode reduces the integration density of the DRAM product. Therefore, the present disclosure enables the following realization for memory 1.

[0040] 7 and 8, in some embodiments of the present disclosure, the memory cell 10 further includes a memory structure. The memory structure includes a capacitive memory structure formed between the auxiliary gate electrode 101 and the first electrode 107.

[0041] In this embodiment, the memory cell 10 has a capacitive memory structure formed between the auxiliary gate electrode 101 and the first electrode 107, which allows data to be written and improves the problem of current leakage when the transistor is off. Using the auxiliary electrode as part of the capacitive memory structure is advantageous in achieving a relatively high degree of integration of the device.

[0042] Alternatively, the first electrode 107 may be a dedicated conductive structure that forms a capacitive memory structure with the auxiliary gate electrode 101, or the first electrode 107 may be a conductive structure that is conductive to other electrical structures in the memory 1 and can form a capacitive memory structure with the auxiliary gate electrode 101.

[0043] 7, the main gate electrode 105 is located on the side of the semiconductor layer 103 farther from the substrate 200, the auxiliary gate electrode 101 is located between the substrate 200 and the semiconductor layer 103, and the first electrode 107 is located between the substrate 200 and the auxiliary gate electrode 101. In other words, when the main gate electrode 105 and the auxiliary gate electrode 101 are located on both sides of the semiconductor layer 103 and the transistor has a top-gate structure, the first electrode 107 is located closer to the substrate 200 than the auxiliary gate electrode 101.

[0044] 8, the main gate electrode 105 is located between the substrate 200 and the semiconductor layer 103, the auxiliary gate electrode 101 is located on the side of the semiconductor layer 103 farther from the substrate 200, and the first electrode 107 is located on the side of the auxiliary gate electrode 101 farther from the substrate 200. In other words, when the main gate electrode 105 and the auxiliary gate electrode 101 are located on both sides of the semiconductor layer 103, and the transistor has a bottom gate structure, the first electrode 107 is located on the side farther from the substrate 200 than the auxiliary gate electrode 101.

[0045] In some embodiments, as shown in Figures 5 and 6, the first electrode 107 is a source electrode, and the orthogonal projection of the source electrode onto the substrate 200 partially overlaps with the orthogonal projection of the auxiliary gate electrode 101 onto the substrate 200.

[0046] In this embodiment, the source electrode is used as another part of the capacitive memory structure, and cooperates with the auxiliary gate electrode 101 to write data, thereby further increasing the integration level of the memory 1. That is, data can be read and written by simply providing one transistor in the memory cell 10 of the memory 1, and there is no need to provide a separate transistor or capacitive element. This greatly simplifies the configuration of the memory cell 10, and is advantageous in improving the integration level and storage density of the memory 1.

[0047] 2 and 3 show a storage capacitor, but in reality, this storage capacitor is composed of the auxiliary gate electrode 101 of the transistor and the source and drain electrodes of the transistor. The auxiliary gate electrode 101 has a backgate effect, that is, the potential of the auxiliary gate electrode 101 affects the threshold voltage of the transistor, so the magnitude of the voltage for turning on the transistor when reading stored data is between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0".

[0048] In the memory 1 provided in this embodiment, a first level is applied to the main gate electrode 105 via the word line 30 during a write operation. A memory signal is transmitted to the source electrode of the memory cell 10 to be written to via the bit line 20, and the source electrode transmits the memory signal to the drain electrode. The drain electrode transmits the memory signal to the auxiliary gate electrode 101, and the node capacitor of the auxiliary gate electrode 101 and the drain electrode becomes the memory capacitor of the memory cell 10. This realizes writing of data. In a read operation, the effect of the voltage on the auxiliary gate electrode 101 on the transistor threshold voltage is utilized. A second level is applied to the auxiliary gate electrode 101 via the word line 30, and then data is read by detecting the magnitude of the transistor output current. Therefore, data can be read and written in the memory cell 10 by providing only one transistor, and there is no need to provide a separate transistor or capacitance element. This is advantageous in extremely simplifying the configuration of the memory cell 10 and improving the integration degree and memory density of the memory 1.

[0049] Although the memory cell 10 in the memory 1 provided in this embodiment may include only one transistor, the film layer configuration of the memory 1 will be described in detail in the following embodiment. In some embodiments, the transistor further comprises a first medium layer 104 and a second medium layer 102, as shown in FIGS. The first medium layer 104 is located between the semiconductor layer 103 and the main gate electrode 105 .

[0050] The second medium layer 102 is located between the auxiliary gate electrode 101 and the semiconductor layer 103, and between the auxiliary gate electrode 101 and the source electrode, and the orthogonal projection of the source electrode onto the substrate 200 and the orthogonal projection of the auxiliary gate electrode 101 onto the substrate 200 partially overlap.

[0051] In the memory 1 provided in this embodiment, the second medium layer 102 is used as a dielectric material of a storage capacitor which serves as the auxiliary gate electrode 101 and the source electrode. The first medium layer 104 realizes an insulating layer 106 between the main gate electrode 105 and the source and drain electrodes.

[0052] In some embodiments, as shown in Figures 5 to 8, the memory 1 according to the present embodiment further includes a buffer layer 300 between the substrate 200 and a film layer of the transistor closest to the substrate 200 (e.g., the auxiliary gate electrode 101 in Figure 5). Optionally, the material of the substrate 200 is silicon or glass, and the buffer layer 300 is an insulating material.

[0053] In some embodiments, as shown in FIG. 5, a main gate electrode 105 and an auxiliary gate electrode 101 are located on both sides of the semiconductor layer 103, respectively, and the transistor uses a top-gate structure, the specific film layer structure being as follows: The main gate electrode 105 is located on the side of the semiconductor layer 103 remote from the substrate 200 , and the auxiliary gate electrode 101 is located between the substrate 200 and the semiconductor layer 103 . The transistor has a first insulating layer 106, a first through hole 107, and a second through hole . The first insulating layer 106 is located on the side of the main gate electrode 105 farther from the substrate 200 . The bit line 20 is located on the side of the first insulating layer 106 remote from the main gate electrode 105 .

[0054] The first through hole 107 penetrates the first insulating layer 106 and the first medium layer 104, respectively, and is connected to the bit line 20 and the source contact region 1031 of the semiconductor layer 103, respectively, and at least a portion of the entire source contact region 1031 including the first through hole 107 and the semiconductor layer 103 forms a source electrode.

[0055] The second through hole 108 penetrates each of the first insulating layer 106, the first medium layer 104, and the second medium layer 102, and is connected to the drain contact region 1032 of the semiconductor layer 103 and the auxiliary gate electrode 101, respectively, and at least a portion of the entire drain contact region 1032 including the second through hole 108 and the semiconductor layer 103 forms a drain electrode.

[0056] 5, in the memory 1 according to the present embodiment, the bit line 20 is electrically connected to the source contact region 1031 of the semiconductor layer 103 through a first via 107 penetrating the first insulating layer 106 and the first medium layer 104. The drain contact region 1032 of the semiconductor layer 103 may be electrically connected to the auxiliary gate electrode 101 through a second through hole 108 penetrating the second medium layer 102.

[0057] Here, at least a portion of the entire source contact region 1031 including the first through hole 107 and the semiconductor layer 103 may be used as a source electrode. For example, a portion or all of the first through hole 107 may be used as a source electrode, and a portion or all of the conductive source contact region 1031 of the semiconductor layer 103 may be used as a source electrode.

[0058] Similarly, at least a portion of the entire drain contact region 1032 including the second through hole 108 and the semiconductor layer 103 may be used as a drain electrode; for example, a portion or all of the second through hole 108 may be used as a drain electrode, or a portion or all of the drain contact region 1032 of the semiconductor layer 103 that has been treated to be conductive may be used as a drain electrode.

[0059] In addition, the second through hole 108 also penetrates the first insulating layer 106 (similar to the first through hole 107), and the first through hole 107 and the second through hole 108 can be manufactured using the same etching process, which contributes to further reducing the number of processes and reduces production costs.

[0060] Alternatively, the semiconductor layer 103 may be formed of the same material for forming the second through-hole 108 as the material for forming the first through-hole 107. In this manner, the first through-hole 107 and the second through-hole 108 can be manufactured using the same deposition process, which contributes to further reducing the number of processes and can reduce production costs.

[0061] In some embodiments, as shown in FIG. 6, a main gate electrode 105 and an auxiliary gate electrode 101 are located on either side of the semiconductor layer 103, and the specific film layer structure of the transistor having a bottom gate structure is as follows: The main gate electrode 105 is located between the substrate 200 and the semiconductor layer 103 , and the auxiliary gate electrode 101 is located on the side of the semiconductor layer 103 farther from the substrate 200 . The transistor has a first insulating layer 106, a first through hole 107, and a second through hole . The first insulating layer 106 is located on the side of the auxiliary gate electrode 101 farther from the substrate 200 . The bit line 20 is located on the side of the first insulating layer 106 remote from the auxiliary gate electrode 101 .

[0062] The first through hole 107 penetrates the first insulating layer 106 and the second medium layer 102, respectively, and is connected to the bit line 20 and the source contact region 1031 of the semiconductor layer 103, respectively, and at least a portion of the entire source contact region 1031 including the first through hole 107 and the semiconductor layer 103 forms a source electrode.

[0063] The second through hole 108 penetrates the first insulating layer 106 and the second medium layer 102, and is connected to the auxiliary gate electrode 101 and the drain contact region 1032 of the semiconductor layer 103, respectively, and a drain electrode is formed in at least a portion of the entire drain contact region 1032 including the second through hole 108 and the semiconductor layer 103. In some embodiments, the word lines 30 are provided in the same layer as the main gate electrodes 105 and are located in a different layer than the bit lines 20 .

[0064] 6, in the memory 1 according to the present embodiment, the word line 30 and the bit line 20 are in different layers, which is advantageous for mutual insulation between them, and the word line 30 is provided in the same layer as the main gate electrode 105, which is advantageous for further reducing the number of processes, and allows for further reduction in production costs. In some embodiments, the semiconductor layer 103 includes at least one material selected from the group consisting of a metal oxide semiconductor, single crystal silicon, polycrystalline silicon, and amorphous silicon. Here, the metal oxide semiconductor includes at least one element selected from the group consisting of indium, gallium, zinc, tin, and tungsten.

[0065] In the memory 1 provided in this embodiment, the material of the semiconductor layer 103 contains a metal oxide, and due to the inherent characteristics of metal oxide semiconductors (such as low electron mobility), when a metal oxide is used as the material of the semiconductor layer 103, the leakage current of the transistor can be reduced. By reducing the speed at which charges are lost on the storage capacitance, the data retention time of the memory 110 can be extended. This is advantageous for reducing the refresh frequency and power consumption of the memory 110.

[0066] Specifically, the metal oxide material may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is 10 -15 A), which ensures the low refresh rate of memory 1. The metal oxide materials are ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y N z , Mg x Zinc y O z , In x Zinc y O z , In x Ga y Zincz O a , Zr x In y Zinc z O a , Hf x In y Zinc z O a , Sn x In y Zinc z O a , Al x Sn y In z Zinc a O d , Si x In y Zinc z O a , Zn x Sn y O z , Al x Zinc y Sn z O a , Ga x Zinc y Sn z O a , Zr x Zinc y Sn z O a , InGaSiO, or other materials may be used as long as it is guaranteed that the leakage current of the transistor satisfies the requirements, and the specific details are adjusted according to the actual situation.

[0067] To further increase the integration density of memory 1, memory 1 may have multiple memory cells 10, but in some embodiments, at least two memory cells 10 are stacked in a direction perpendicular to substrate 200.

[0068] 4 to 8, the memory 1 according to the present embodiment further includes a planarization layer 109 located on the side of the bit line 20 farther from the substrate 200. By fabricating the auxiliary gate electrodes 101 of the upper layer memory cell group 100 on the planarization layer 109 of the lower layer memory cell group 100, it becomes possible to overlap the memory cell groups 100 in a direction perpendicular to the substrate 200, thereby obtaining a high density and high integration memory 1.

[0069] In some embodiments, at least two memory cells 10 are arranged in an array on one side of the substrate 200, and in at least two memory cells 10 in the same row, the main gate electrodes 105 of the transistors are electrically connected to the same word line 30, and in at least two memory cells 10 in the same column, the source electrodes of the transistors are electrically connected to the same bit line 20.

[0070] As shown in FIG. 4, the memory 1 according to the present embodiment includes a substrate 200 on which a plurality of word lines 30, a plurality of bit lines 20, and a plurality of memory cells 10 are provided. The plurality of memory cells 10 are divided into a plurality of memory cell groups 100 arranged in a direction perpendicular to the substrate 200. The memory cell groups 100 include a plurality of memory cells 10 arranged in a direction parallel to the substrate 200. Here, the gate electrodes of the transistors in the memory cells 10 in the same row are electrically connected to the same word line 30. The source electrodes of the transistors in the memory cells 10 in the same column are electrically connected to the same bit line 20.

[0071] In a specific implementation, depending on the specific memory capacity requirements and spatial constraints on memory 1, different layouts can be selected, i.e., by adjusting the number of memory cell groups 100 and the number of memory cells 10 for each memory cell group 100 (including adjusting the number of memory cells 10 for each row and / or column), to achieve an optimized design of memory capacity and memory space.

[0072] Based on the same inventive idea, according to an embodiment of the present disclosure, as shown in FIG. 9, an electronic device 2 is provided that includes a memory 1 according to any of the above-mentioned embodiments, and since the functional effects of the memory 1 according to the above-mentioned embodiments are achieved, a description thereof will be omitted.

[0073] Alternatively, the electronic device in the embodiment of the present disclosure may include a memory device, a smartphone, a computer, a tablet, an artificial smart device, a wearable device, or a mobile power source.

[0074] According to an embodiment of the present disclosure, based on the same inventive concept, as shown in FIG. 10, there is provided a manufacturing method of a memory 1 including the following steps S101 to S105.

[0075] In S101, an auxiliary gate electrode, a second medium layer, a semiconductor layer, a first medium layer, a main gate electrode, a word line connected to the main gate electrode, and a first insulating layer are sequentially manufactured on one side of a substrate, and the semiconductor layer is formed by sequentially connecting a source contact region, a semiconductor region, and a drain contact region.

[0076] In some embodiments, in step S101, sequentially fabricating an auxiliary gate electrode, a second medium layer, a semiconductor layer, a first medium layer, a main gate electrode, a word line connected to the main gate electrode, and a first insulating layer on one side of the substrate includes:

[0077] An auxiliary gate electrode is fabricated on one side of the substrate. Optionally, the auxiliary gate electrode 101 is formed by depositing a first metal layer and patterning the first metal layer. A second medium layer is fabricated on the auxiliary gate electrode and the exposed substrate. Optionally, the second medium layer 102 may be fabricated by a blanket coating method.

[0078] A semiconductor layer is formed on the second medium layer such that the orthogonal projection of the semiconductor region of the semiconductor layer onto the substrate and the orthogonal projection of the source contact region of the semiconductor layer onto the substrate partially overlap with the orthogonal projection of the auxiliary gate electrode onto the substrate. Alternatively, a metal oxide layer may be formed on the second medium layer 102, and then the metal oxide layer may be patterned to form the semiconductor layer 103. The source and drain contact regions to the semiconductor layer are conductive.

[0079] In step S102, the first insulating layer and the first medium layer are sequentially etched to obtain a first through hole exposing at least a part of the source contact region of the semiconductor layer. Step S104 is then performed.

[0080] In step S103, the first insulating layer, the first medium layer and the second medium layer are sequentially etched to obtain a second through hole exposing at least a part of the drain contact region of the semiconductor layer and a part of the auxiliary gate electrode. Step S104 is then performed.

[0081] In some embodiments, the first through hole exposing at least a part of the source contact region of the semiconductor layer by sequentially etching the first insulating layer and the first medium layer, and the second through hole exposing at least a part of the drain contact region of the semiconductor layer and the partial auxiliary gate electrode by sequentially etching the first insulating layer, the first medium layer, and the second medium layer are obtained and synchronously performed. This allows the first through hole 107 and the second through hole 108 to be manufactured by sharing the same etching process, which contributes to further reducing the number of steps and reduces the production cost.

[0082] Note that the present disclosure does not limit the order of execution between steps S102 and S103, and step S102 may be executed first, or step S103 may be executed first.

[0083] In S104, a conductive material is prepared in the first through hole and the second through hole so as to form a first via connecting the source contact region of the semiconductor layer in the first through hole and a second via connecting the auxiliary gate electrode and the drain contact region of the semiconductor layer in the second through hole. In some embodiments, the conductive material in the first through hole and the second through hole may be the same metal material, for example the same metallic material. In S105, a bit line is formed on the first through hole.

[0084] In some embodiments, step S105 may include creating a third metal layer and patterning the third metal layer to form a plurality of bit lines 20 electrically connected to the first through holes 107 and the source electrodes via the first through paths.

[0085] By going through the above steps S101 to S105, a memory using a transistor with a top-gate structure in which a main gate electrode and an auxiliary gate electrode are located on both sides of a semiconductor layer is obtained.

[0086] In the memory manufacturing method according to the present embodiment, since the memory cell 10 in the memory has only one transistor, the number of film layers can be reduced, which is advantageous in reducing the number of processes and reducing production costs. By providing only one transistor in the memory cell 10, data can be read and written. Since there is no need to provide a separate transistor or capacitive element, the configuration of the memory cell 10 is extremely simplified, which is advantageous in improving the integration degree and storage density of the dynamic memory.

[0087] According to an embodiment of the present disclosure, based on the same inventive concept, as shown in FIG. 11, another memory manufacturing method includes the following steps S201 to S205.

[0088] In S201, a main gate electrode, a word line connected to the main gate electrode, a first medium layer, a semiconductor layer, a second medium layer, an auxiliary gate electrode, and a first insulating layer are provided on one surface of a substrate, in this order, and the semiconductor layer is formed by connecting a source contact region, a semiconductor region, and a drain contact region in order.

[0089] In some embodiments, in step S201, sequentially fabricating a main gate electrode, a word line connected to the main gate electrode, a first medium layer, a semiconductor layer, a second medium layer, an auxiliary gate electrode, and a first insulating layer on one side of a substrate includes:

[0090] Fabricating a main gate electrode and a word line connected to the main gate electrode on one side of the substrate, and optionally depositing and patterning a second metal layer to form the main gate electrode and the word line connected to the main gate electrode.

[0091] The first medium layer is fabricated on the main gate electrode, the word line connected to the main gate electrode, and the exposed substrate, and can optionally be fabricated by a blanket coating process.

[0092] A semiconductor layer is fabricated on the first medium layer such that an orthogonal projection of a semiconductor region of the semiconductor layer onto the substrate partially overlaps an orthogonal projection of the main gate electrode onto the substrate. Optionally, a metal oxide layer may be deposited on the first medium layer and then patterned to form the semiconductor layer. The source contact region and the drain contact region of the semiconductor layer are made conductive. A second medium layer is formed on the semiconductor layer and the exposed first medium layer. Optionally, the second medium layer may be formed by a blanket coating process.

[0093] In the second medium layer, the auxiliary gate electrode is fabricated such that an orthogonal projection of the auxiliary gate electrode onto the substrate partially overlaps an orthogonal projection of the semiconductor region of the semiconductor layer onto the substrate and an orthogonal projection of the source contact region of the semiconductor layer onto the substrate. Optionally, the auxiliary gate electrode 101 is formed by fabricating a first metal layer and patterning the first metal layer.

[0094] In step S202, the first insulating layer and the second medium layer are sequentially etched to obtain a first through hole exposing at least a part of the source contact region of the semiconductor layer, and then step S204 is performed.

[0095] In S203, the first insulating layer and the second medium layer are sequentially etched to obtain a second through hole exposing the auxiliary gate electrode and at least a part of the drain contact region of the semiconductor layer, after which step S204 is performed.

[0096] In some embodiments, the first through hole, which sequentially etches the first insulating layer and the second medium layer to expose at least a part of the source contact region of the semiconductor layer, and the second through hole, which sequentially etches the first insulating layer and the second medium layer to expose at least a part of the auxiliary gate electrode and the drain contact region of the semiconductor layer, are formed in a synchronized manner. This allows the first through hole 107 and the second through hole 108 to be manufactured using the same etching process, which contributes to further reducing the number of steps and reduces production costs.

[0097] Note that the present disclosure does not limit the order of execution between step S202 and step S203, and step S202 may be executed first, or step S203 may be executed first.

[0098] In S204, a conductive material is prepared in the first through hole and the second through hole so as to form a first via connecting the source contact region of the semiconductor layer in the first through hole and a second via connecting the auxiliary gate electrode and the drain contact region of the semiconductor layer in the second through hole. In some embodiments, the conductive material in the first through hole and the second through hole can be the same metallic material, for example the same metallic material. In S205, a bit line is formed on the first through hole.

[0099] In some embodiments, step S105 may include fabricating a third metal layer and patterning the third metal layer to form a plurality of bit lines 20 electrically connected to the first through holes 107 and the source electrodes via the first through paths.

[0100] Through the above steps S201 to S205, another memory can be fabricated in which the transistor has a bottom gate structure and the main gate electrode and the auxiliary gate electrode are disposed on both sides of the semiconductor layer.

[0101] For ease of understanding, in this embodiment, a specific manufacturing method for a memory employing a top gate structure includes steps S301 to S310. In S301, a substrate 200 is provided, and a buffer layer 300 is formed on the substrate 200. The film layer structure after this step S301 is shown in FIG. In S302, a plurality of auxiliary gate electrodes 101 are formed on the substrate 200 by a patterning process, and the film layer structure after this step S302 is shown in FIG. In S303, the second medium layer 102 is formed on the auxiliary gate electrode 101, and the film layer structure after this step S303 is shown in FIG.

[0102] In S304, a metal oxide is deposited as the semiconductor layer 103 on the second medium layer 102, and the orthogonal projection of the semiconductor region in the semiconductor layer onto the substrate and the orthogonal projection of the source contact region in the semiconductor layer onto the substrate are partially overlapped with the orthogonal projection of the auxiliary gate electrode onto the substrate, respectively. The film layer structure after this step S304 is shown in FIG. In S305, the first medium layer 104 is formed on the semiconductor layer 103, and the film layer structure after this step S305 is shown in FIG.

[0103] In S306, a plurality of main gate electrodes 105 and word lines 30 connected to the main gate electrodes 105 are formed by patterning on the first medium layer 104. The film layer structure after this step S306 is shown in FIG. In S307, an insulating layer 106 is formed on the main gate electrode 105, and the film layer structure after this step S307 is shown in FIG.

[0104] In S308, a drain electrode is formed in a first through hole 107 penetrating the insulating layer 106 and the first medium layer 104, and a second through hole 108 penetrating the insulating layer 106, the first medium layer 104, the semiconductor layer 103, and the second medium layer 102. At least a part of the entire source contact region including the first through hole and the semiconductor layer forms a source electrode, and at least a part of the entire drain contact region including the second through hole and the semiconductor layer forms a drain electrode. The film layer configuration after this step S308 is shown in FIG.

[0105] In S309, a patterning process is performed to form a plurality of bit lines 20, and the bit lines 20 are electrically connected to the source electrodes of the source contact regions of the semiconductor layer through the first through holes 107. The configuration of the film layer after this step S309 is shown in FIG. In S310, a planarization layer 109 is formed on the side of the bit line 20 farther from the substrate 200. The film layer configuration after this step S310 is shown in FIG.

[0106] It should be noted that steps S302 to S310 are repeated on the planarization layer 109 to obtain a dynamic memory including a plurality of memory cells stacked in a direction perpendicular to the substrate. When forming the memory cell in the bottom layer, a plurality of auxiliary gate electrodes 101 are formed on the buffer layer 300 by a patterning process, and when forming other memory cells, a plurality of auxiliary gate electrodes 101 are formed on the planarization layer 109 of the memory cell in the next layer by a patterning process.

[0107] A read / write method according to an embodiment of the present disclosure is a read / write method for reading / writing from / to the memory in each of the above embodiments based on the same inventive idea, and includes T1-T2.

[0108] At T1, in a write state, a first level is applied to the main gate electrode 105 of the memory cell 10 to be written to via the word line 30 to turn on the transistor, a memory signal is transferred to the source electrode of the memory cell 10 to be written to via the bit line 20, and the memory signal is written to the memory cell 10 to be written to as memory data.

[0109] When the dynamic memory is in a write operation mode, a first level (e.g., 5V, the specific value being adjustable depending on the actual situation) is applied to the main gate electrode 105 via the word line 30 so that the transistor is turned on, and the magnitude of the first level is related to factors such as the structure of the transistor and the material of the semiconductor layer 103 in the transistor, and specifically can be adjusted depending on the actual situation.

[0110] When the transistor is turned on, a voltage is applied to the source electrode via the bit line 20 based on external input data, the source electrode and the drain electrode are conductive via the semiconductor layer 103, and the drain electrode and the auxiliary gate electrode 101 are electrically connected, so that the magnitude of the voltage at the source electrode and the drain electrode is the same as the magnitude of the voltage at the auxiliary gate electrode 101 (the potential of the drain electrode and the auxiliary gate electrode 101 is the same). The node capacitance of the auxiliary gate electrode 101 and the drain electrode constitutes the storage capacitance of the memory cell 10, and the magnitude of the charge amount in the storage capacitance is determined by the level of the voltage at the auxiliary gate electrode 101, and further, the binary number of the data signal stored in the memory cell 10 is determined to be 0 or 1. When a high voltage (for example, 5V) is applied to the source electrode via the bit line 20, data "1" is written to the memory cell 10, and when a low voltage (for example, 0V) is applied to the source electrode via the bit line 20, data "0" is written to the memory cell 10.

[0111] At T2, in a read state, a second level is applied to the main gate electrode 105 of the memory cell 10 to be read via the word line 30, thereby causing the bit line 20 to sense the stored data of the memory cell 10 to be read.

[0112] When the dynamic memory is in a read operation mode, a second level is applied to the main gate electrode 105 via the word line 30, a voltage difference is generated between the main gate electrode 105 and the source electrode, and the magnitude of the current on the bit line 20 (i.e., the output current of the transistor) is detected, thereby realizing data reading.

[0113] Specifically, when data "1" is stored before the memory cell 10, the potentials on the auxiliary gate electrode 101 and the drain electrode are high, and the transistor is in an on state due to the joint action of the first level and the second level, so a clear current is measured through the bit line 20. When a clear current is measured, it is determined that the data read is "1." When data "0" is stored before the memory cell 10, the potentials on the auxiliary gate electrode 101 and the drain electrode are low, and the transistor is in an off state even after the second level is applied to the main gate electrode 105, so the current measured by the bit line 2032 is very weak, and it is determined that the data read at this time is "0."

[0114] The threshold voltage of a transistor is correlated with the potential on the auxiliary gate electrode 101 and the drain electrode, and for an N-type field effect transistor (when the transistor is on, the carriers are electrons), the higher the potential on the auxiliary gate electrode 101 and the drain electrode, the smaller the threshold voltage, i.e., the transistor is on even when the voltage difference between the main gate electrode 105 and the source electrode is small. The lower the potential on the auxiliary gate electrode 101 and the drain electrode, the higher the threshold voltage.

[0115] As shown in FIG. 21, the horizontal axis in FIG. 21 is the voltage applied to the main gate electrode 105 (i.e., the second level), and the vertical axis is the output current of the transistor. When the second level applied to the main gate electrode 105 is a certain value (the position of the dotted line in FIG. 21), the voltage level at the auxiliary gate electrode 101 and the drain electrode (i.e., whether the data written by the transistor is "1" or "0") has a significant difference in the magnitude of the output current of the transistor (i.e., the current measured through the bit line 20). Reading data from the memory cell 10 can be achieved by detecting the current on the bit line 20. When the transistor writes data "1", the output current of the transistor is large, so the read data is also "1", and when the data written by the transistor is "0", the output current of the transistor is extremely weak, so the read data is also "0".

[0116] The value of the second level can be determined by the parameters of the transistor and the magnitude of the voltage applied to the auxiliary gate electrode 101 and the drain electrode during a write operation. The value of the second level must be appropriate (it must be between the threshold voltage when the transistor stores "1" and the threshold voltage when the transistor stores "0"). If the value of the second level is not appropriate, the magnitude of the output current of the transistor when the stored data is "1" (i.e., the potential on the drain electrode and the auxiliary gate electrode 101 is high) and the magnitude of the output current of the transistor when the stored data is "0" (i.e., the potential on the drain electrode and the auxiliary gate electrode 101 is low) will be very close. Therefore, when a read operation is performed, it becomes difficult to determine whether the read data is "0" or "1", which affects the performance of the dynamic memory. The optimal value of the second level can be obtained by experiment or simulation so that the difference in the output current when the transistor is read in different states is maximized, thereby improving the read performance. By applying the embodiments of the present disclosure, at least the following effects can be achieved.

[0117] 1. In the memory cell according to the present disclosure, the transistor is provided with a main gate electrode capable of realizing conductivity control for the semiconductor layer, and an auxiliary gate electrode is introduced to provide conductivity control for the semiconductor layer. By electrically connecting this auxiliary gate electrode to the drain electrode, the auxiliary gate electrode can obtain a fixed potential synchronized with the drain electrode, and this fixed potential provides supplementary control to the semiconductor layer. In addition, since the auxiliary gate electrode is not electrically connected to the source electrode, it can function as a negative bias for the threshold voltage in the read stage. This can improve the performance of the transistor and optimize the read / write performance of the memory.

[0118] 2. The memory cell according to the present disclosure includes a capacitive memory structure formed between the auxiliary gate electrode and the first electrode, which can realize data writing and can improve the problem of current leakage when the transistor is in the off state. The use of the auxiliary electrode as part of the capacitive memory structure is advantageous for achieving a relatively high degree of integration of the device.

[0119] 3. In the memory cell according to the present disclosure, the source electrode of the transistor is used as another part of the capacitive memory structure, and cooperates with the auxiliary gate electrode to write data, thereby further increasing the degree of integration of the memory. In other words, data can be read and written by simply providing one transistor in the memory cell of the memory, and there is no need to provide separate transistors or capacitive elements, which greatly simplifies the configuration of the memory cell and is advantageous in improving the degree of integration and storage density of the memory.

[0120] It should be understood by those skilled in the art that the steps, measures, and schemes in the various operations, methods, and flows discussed in this disclosure may be alternated, modified, combined, or deleted. Furthermore, the steps, measures, and schemes in the various operations, methods, and flows discussed in this disclosure may be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, the steps, measures, and schemes in the various operations, methods, and flows disclosed in this disclosure in the prior art may be alternated, modified, rearranged, decomposed, combined, or deleted.

[0121] In describing the present disclosure, the directions or positional relationships indicated by terms such as "upper," "lower," "vertical," and "horizontal" are based on the exemplary directions or positional relationships shown in the drawings, and are for the purpose of conveniently or simply explaining the embodiments of the present disclosure, and do not necessarily mean that the indicated devices or components must be configured and operated in a specific orientation, and cannot be understood as limiting the present disclosure.

[0122] The terms "first" and "second" are for explanatory purposes only and are not to be understood as indicating or suggesting the relative importance or number of technical features that are presented. Thus, a feature qualified with "first" or "second" may explicitly or implicitly include one or more features. In this disclosure, the meaning of "plurality" means two or more unless otherwise specified.

[0123] In the description of the present disclosure, the terms "mounted", "associated", and "connected" should be understood in a broad sense unless otherwise clearly specified and limited, and may mean, for example, a fixed connection, a detachable connection, an integral connection, a direct connection, an indirect connection via an intermediate medium, or internal communication between two elements. The above terms are specifically understood by those skilled in the art to have a specific meaning in the present disclosure. It is understood that the particular features, structures, materials, or characteristics described herein may be combined in any one or more embodiments or examples.

[0124] In addition, each step in the flowchart of the drawing is displayed in sequence according to the direction of the arrow, but it is understood that the order of execution of these steps is not limited to the order indicated by the arrow. In some implementation scenes of one embodiment of the present disclosure, the steps in each flow may be executed in other orders as necessary unless explicitly stated otherwise in this document. In addition, a part or all of each flowchart may include multiple sub-steps or multiple steps based on the actual implementation scene. Some or all of these sub-steps or phases may be executed at the same timing, or may be executed at different timings, or may be executed in different execution times, and the execution order of these sub-steps or phases may be flexibly configured according to needs, but the embodiment of the present disclosure is not limited thereto.

[0125] It should be noted that the above are only some embodiments of the present disclosure, and that other similar embodiments based on the technical idea of ​​the present disclosure that do not deviate from the technical idea of ​​the present disclosure and that can be adopted by those of ordinary skill in the art are also within the scope of protection of the embodiments of the present disclosure. [Explanation of symbols]

[0126] 10...memory cell, 101...auxiliary gate electrode, 102...second medium layer, 103...semiconductor layer, 1031...source contact region, 1032...drain contact region, 1033...semiconductor region, 104...first medium layer, 105...main gate electrode, 106...first insulating layer, 107...first through hole, 108...second through hole, 109...planarization layer, 110...first electrode, 20...bit line, 30...word line, 100...memory cell group, 200...substrate, 300...buffer layer, 1...memory, 2...electronic device

Claims

1. 1. A memory having a substrate and word lines, bit lines and memory cells on one side of the substrate, The memory cell includes a transistor. The transistor is a semiconductor layer formed by sequentially connecting a source contact region, a semiconductor region, and a drain contact region; a main gate electrode electrically connected to the word line; a source electrode electrically connected to the bit line and the source contact region of the semiconductor layer; a drain electrode electrically connected to the drain contact region of the semiconductor layer; an auxiliary gate electrode electrically connected to the drain electrode; a first orthogonal projection of the main gate electrode onto the substrate and a second orthogonal projection of the auxiliary gate electrode onto the substrate at least partially overlap with an orthogonal projection of the semiconductor region in the semiconductor layer onto the substrate,

2. The main gate electrode is provided between the substrate and the semiconductor layer, or The memory of claim 1 , wherein the main gate electrode is located on a side of the semiconductor layer remote from the substrate.

3. 3. The memory according to claim 1, wherein the main gate electrode and the auxiliary gate electrode are located on opposite sides of the semiconductor layer.

4. The memory cell further comprises a memory structure, The memory of claim 1 , wherein the memory structure comprises a capacitive memory structure formed between the auxiliary gate electrode and a first electrode.

5. the first electrode is a source electrode, The memory according to claim 4 , wherein an orthogonal projection of the source electrode onto the substrate and an orthogonal projection of the assist gate electrode onto the substrate partially overlap each other.

6. the main gate electrode is located on a side of the semiconductor layer farther from the substrate, the auxiliary gate electrode is located between the substrate and the semiconductor layer, The memory of claim 4 , wherein the first electrode is located between the substrate and the auxiliary gate electrode.

7. the main gate electrode is located between the substrate and the semiconductor layer; the auxiliary gate electrode is located on a side of the semiconductor layer farther from the substrate, The memory of claim 4 , wherein the first electrode is located on a side of the auxiliary gate electrode farther from the substrate.

8. The transistor further comprises: a first medium layer located between the semiconductor layer and the main gate electrode; 2. The memory of claim 1, further comprising a second medium layer located between the auxiliary gate electrode and the semiconductor layer and between the auxiliary gate electrode and the source electrode, the second medium layer partially overlapping an orthogonal projection of the source electrode onto the substrate and an orthogonal projection of the auxiliary gate electrode onto the substrate.

9. the main gate electrode is located on a side of the semiconductor layer farther from the substrate, the auxiliary gate electrode is located between the substrate and the semiconductor layer, the transistor includes a first insulating layer, a first through hole, and a second through hole; the first insulating layer is located on a side of the main gate electrode farther from the substrate, the bit line is located on a side of the first insulating layer farther from the main gate electrode, the first through hole penetrates the first insulating layer and the first medium layer, and is connected to the bit line and a source contact region of the semiconductor layer, respectively; the source electrode is formed in at least a part of the entire area including the first through hole and the source contact region of the semiconductor layer; 9. The memory of claim 8, wherein the second through hole penetrates the first insulating layer, the first medium layer and the second medium layer, respectively, and is connected to the drain contact region of the semiconductor layer and the auxiliary gate electrode, respectively, and the drain electrode is formed in at least a portion of the entire drain contact region including the second through hole and the semiconductor layer.

10. the main gate electrode is located between the substrate and the semiconductor layer; the auxiliary gate electrode is located on a side of the semiconductor layer farther from the substrate, the transistor includes a first insulating layer, a first through hole, and a second through hole; the first insulating layer is located on a side of the auxiliary gate electrode farther from the substrate, the bit line is located on a side of the first insulating layer farther from the auxiliary gate electrode; the first through hole penetrates the first insulating layer and the second medium layer, and is connected to the bit line and a source contact region of the semiconductor layer, respectively; the source electrode is formed in at least a part of the entire area including the first through hole and the source contact region of the semiconductor layer; 9. The memory of claim 8, wherein the second through hole penetrates the first insulating layer and the second medium layer and is connected to the auxiliary gate electrode and the drain contact region of the semiconductor layer, respectively, and the drain electrode is formed in at least a portion of the entire area including the second through hole and the drain contact region of the semiconductor layer.

11. 2. The memory according to claim 1, wherein said word lines are provided in the same layer as said main gate electrodes and in a different layer from said bit lines.

12. The semiconductor layer includes at least one of a metal oxide semiconductor, single crystal silicon, polycrystalline silicon, and amorphous silicon; The memory of claim 1 , wherein the metal oxide semiconductor comprises at least one of the elements indium, gallium, zinc, tin, and tungsten.

13. At least two of the memory cells are arranged in a stack vertically relative to the substrate; and / or the memory of claim 1, wherein at least two of the memory cells are arrayed on one side of the substrate, and the main gate electrodes of the transistors in at least two of the memory cells in the same row are electrically connected to the same word line, and the source electrodes of the transistors in at least two of the memory cells in the same column are electrically connected to the same bit line.

14. An electronic device comprising the memory according to any one of claims 1 to 13.

15. An auxiliary gate electrode, a second medium layer, a semiconductor layer, a first medium layer, a main gate electrode, a word line connected to the main gate electrode, and a first insulating layer are sequentially formed on one side of a substrate, and the semiconductor layer is configured to sequentially connect a source contact region, a semiconductor region, and a drain contact region; sequentially etching the first insulating layer and the first medium layer to obtain a first through hole exposing at least a portion of the source contact region of the semiconductor layer; sequentially etching the first insulating layer, the first medium layer, and the second medium layer to obtain a second through hole exposing at least a portion of the drain contact region of the semiconductor layer and a portion of the auxiliary gate electrode; forming a conductive material in the first through hole and the second through hole such that a first via connecting a source contact region of the semiconductor layer is formed in the first through hole and a second via connecting the auxiliary gate electrode and a drain contact region of the semiconductor layer is formed in the second through hole; A method of manufacturing a memory, wherein a bit line is fabricated over the first via.

16. The auxiliary gate electrode, the second medium layer, the semiconductor layer, the first medium layer, the main gate electrode, the word line connected to the main gate electrode, and the first insulating layer are sequentially formed on one side of the substrate. The auxiliary gate electrode is fabricated on one side of the substrate; the second medium layer is formed on the auxiliary gate electrode and the exposed substrate; the semiconductor layer is formed on the second medium layer such that an orthogonal projection of a semiconductor region of the semiconductor layer onto the substrate and an orthogonal projection of the source contact region of the semiconductor layer onto the substrate are partially overlapped with an orthogonal projection of the auxiliary gate electrode onto the substrate, The method of claim 15 , wherein the source contact region and the drain contact region of the semiconductor layer are made conductive.

17. 17. The method for manufacturing a memory according to claim 15, wherein the steps of sequentially etching the first insulating layer and the first medium layer to obtain a first through hole exposing at least a portion of the source contact region of the semiconductor layer and sequentially etching the first insulating layer, the first medium layer, and the second medium layer to obtain a second through hole exposing at least a portion of the drain contact region of the semiconductor layer and a portion of the auxiliary gate electrode are performed in a synchronous manner.

18. A main gate electrode, a word line connected to the main gate electrode, a first medium layer, a semiconductor layer, a second medium layer, an auxiliary gate electrode, and a first insulating layer are sequentially fabricated on one side of a substrate, and the semiconductor layer is formed by connecting a source contact region, a semiconductor region, and a drain contact region in this order; sequentially etching the first insulating layer and the second medium layer to obtain a first through hole exposing at least a portion of the source contact region of the semiconductor layer; sequentially etching the first insulating layer and the second medium layer to obtain a second through hole exposing a portion of the auxiliary gate electrode and at least a portion of the drain contact region of the semiconductor layer; forming a conductive material in the first through hole and the second through hole such that a first via connecting a source contact region of the semiconductor layer is formed in the first through hole and a second via connecting the auxiliary gate electrode and a drain contact region of the semiconductor layer is formed in the second through hole; A method of manufacturing a memory, wherein a bit line is fabricated over the first via.

19. A main gate electrode, a word line connected to the main gate electrode, a first medium layer, a semiconductor layer, a second medium layer, an auxiliary gate electrode, and a first insulating layer are sequentially formed on one side of the substrate; The main gate electrode and a word line connected to the main gate electrode are fabricated on one side of the substrate; The first medium layer is fabricated on the main gate electrode, the word line connected to the main gate electrode, and the exposed substrate; the semiconductor layer is formed on the first medium layer such that an orthogonal projection of a semiconductor region of the semiconductor layer onto the substrate and an orthogonal projection of the main gate electrode onto the substrate partially overlap each other; the source contact region and the drain contact region of the semiconductor layer are conductive; the second medium layer is formed on the semiconductor layer and the exposed first medium layer; 20. The method for manufacturing a memory according to claim 18, wherein an auxiliary gate electrode is fabricated on the second medium layer such that an orthogonal projection of the auxiliary gate electrode onto a substrate partially overlaps an orthogonal projection of the semiconductor region of the semiconductor layer onto the substrate and an orthogonal projection of the source contact region of the semiconductor layer onto the substrate.

20. 20. The method for manufacturing a memory according to claim 18 or 19, wherein sequentially etching the first insulating layer and the second medium layer to obtain a first via exposing at least a portion of the source contact region of the semiconductor layer and sequentially etching the first insulating layer and the second medium layer to obtain a second via exposing a portion of the auxiliary gate electrode and at least a portion of the drain contact region of the semiconductor layer are performed in synchronization.

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