Method for determining suitability of a wire bonding tool for a wire bonding application, and related methods - Patents.com

JP2025510531A5Pending Publication Date: 2026-03-04KULICKE & SOFFA IND INC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-02-27
Publication Date
2026-03-04

AI Technical Summary

Technical Problem

Existing wire bonding tools are not suitable for all wire bonding applications, making it difficult to determine compatibility between the tool and the specific application.

Method used

A method is provided to determine the compatibility of a wire bonding tool for a given application by simulating the specifications of the tool against the details of the application, including software tools that assess eligibility based on provided specifications and package data.

Benefits of technology

This method allows for early detection of design problems in semiconductor packages, reduces product time to market, and ensures proper clearance between the wire bonding tool and other structures within the application.

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Abstract

A method for determining suitability of a wire bonding tool for a given wire bonding application is provided, the method including the steps of: (a) providing a specification for a wire bonding tool; and (b) determining whether the wire bonding tool is suitable for the given wire bonding application using (i) a software tool and (ii) the specification provided in (a).
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Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 327,855, filed April 6, 2022, the contents of which are incorporated herein by reference.

[0002] The present invention relates to wire bonding operations, and more particularly to a method for determining whether a wire bonding tool is suitable for a given wire bonding application. [Background technology]

[0003] In semiconductor device processing and packaging, wire bonding continues to be the primary method of providing electrical interconnection between two locations in a package (e.g., between a die pad of a semiconductor die and a lead of a lead frame). Specifically, a wire bonder (also known as a wire bonding machine) forms a wire loop between the locations to be electrically interconnected. The primary methods for forming the wire loop are ball bonding and wedge bonding. Various types of bonding energy can be used in forming the bond between (a) the end of the wire loop and (b) the bonding area (e.g., die pad, lead, etc.), including, for example, ultrasonic energy, thermosonic compression energy, thermocompression energy. Wire bonding machines (e.g., stud bump machines, etc.) are also used to form conductive bumps.

[0004] In wire bonding processes, various wire bonding tools (e.g., capillary tools, wedge bonding tools, etc.) are used, but a particular wire bonding tool may not be suitable for all wire bonding applications. Therefore, it would be desirable to provide an improved method for determining whether a wire bonding tool is suitable for a given wire bonding application. Summary of the Invention [Means for solving the problem]

[0005] According to an exemplary embodiment of the present invention, there is provided a method for determining suitability of a wire bonding tool for a given wire bonding application, the method comprising the steps of: (a) providing a specification for a wire bonding tool; and (b) determining whether the wire bonding tool is qualified for the given wire bonding application using (i) a software tool and (ii) the specification provided in step (a).

[0006] The methods of the present invention may also be implemented in an apparatus (e.g., as part of the intelligence of a wire bonding apparatus) or as computer program instructions on a computer readable medium (e.g., a computer readable medium including a wire bonding program for use in conjunction with a wire bonding apparatus). [Brief description of the drawings]

[0007] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. According to common practice, the various elements of the drawings are not drawn to scale. Rather, dimensions of the various elements have been arbitrarily expanded or reduced for clarity. The figures include: [Figure 1A] 1A and 1B are side cross-sectional views showing a conventional wire bonding tool. [Figure 1B]1A and 1B are side cross-sectional views showing a conventional wire bonding tool. [Figure 2A] 2A and 2B are side cross-sectional views showing another conventional wire bonding tool. [Figure 2B] 2A and 2B are side cross-sectional views showing another conventional wire bonding tool. [Figure 3A] 3A-3B are side and top block diagrams of a semiconductor package useful for describing various exemplary embodiments of the present invention. [Figure 3B] 3A-3B are side and top block diagrams of a semiconductor package useful for describing various exemplary embodiments of the present invention. [Figure 4A] 4A-4D are various block diagrams of a simulation of a wire bonding tool used in connection with a given wire bonding application, according to various embodiments of the present invention. [Figure 4B] 4A-4D are various block diagrams of a simulation of a wire bonding tool used in connection with a given wire bonding application, according to various embodiments of the present invention. [Figure 4C] 4A-4D are various block diagrams of a simulation of a wire bonding tool used in connection with a given wire bonding application, according to various embodiments of the present invention. [Figure 4D] 4A-4D are various block diagrams of a simulation of a wire bonding tool used in connection with a given wire bonding application, according to various embodiments of the present invention. [Diagram 5] FIG. 5 is a flow diagram illustrating a method for determining suitability of a wire bonding tool for a given wire bonding application in accordance with an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In wire bonding (e.g., ball bonding), the overall shape and dimensions of the wire bonding tool (e.g., capillary tool) along with the wire pitch capabilities are important factors that affect the overall feasibility of the semiconductor package design. An exemplary embodiment of the present invention includes simulating the specifications (e.g., shape, geometry, dimensions, etc.) of the wire bonding tool to check for interference between the wire bonding tool and other structures (e.g., adjacent wire loops, components, dies, and other structures) involved in the wire bonding application.

[0009] As semiconductor packages become more complex (e.g., high pin count packages, stacked die packages, SiP, SMT, etc.), one aspect of the present invention helps improve semiconductor package designs by detecting design issues earlier in the development cycle and reducing product time to market.

[0010] Some aspects of the invention relate to detecting potential (and / or actual) interference between a wire bonding tool and other structures in a wire bonding application (e.g., adjacent wire loops, a die, an edge of a die, other electronic components, etc.) through software that applies the wire bonding tool specifications to other details of the wire bonding application (e.g., other details of a semiconductor package). For example, an "actual" interference determined in a simulation may be contact between the wire bonding tool and the other structure(s). For example, a "potential" interference determined in a simulation may be a situation in which the wire bonding tool is too close to the other structure(s) (e.g., there is not an acceptable level of clearance between the wire bonding tool and the other structure). Through such a process, a particular wire bonding tool may be approved (e.g., determined to be suitable) for a given wire bonding application, while another wire bonding tool may be determined to be inappropriate for the wire bonding application. Additionally, some aspects of the present invention can be used to simulate expected variability in wire bonding tools (e.g., dimensional variations in wire bonding tools, dimensional tolerance variations), thereby allowing designers to compensate for such variability.

[0011] Certain exemplary methods of the present invention include determining whether there is at least one of an actual interference between the wire bonding tool and other structures involved in the wire bonding application and a potential interference between the wire bonding tool and other structures involved in the wire bonding application. In other words, the methods can include determining whether there is an acceptable clearance between the wire bonding tool and other structures involved in the wire bonding application during the wire bonding operation.

[0012] These methods can include determining whether an acceptable clearance exists between the wire bonding tool and other structures involved in the wire bonding application during at least one of the following trajectories of the wire bonding tool: (i) during formation of a first wire bond of the wire loop, (ii) during formation of a second wire bond of the wire loop, and (iii) during formation of a wire loop between the first and second wire bonds. Of course, the methods are also applicable to wire loops having more than one bond location.

[0013] In certain embodiments, the wire bonding tool specifications (e.g., data related to the dimensions of the wire bonding tool) may be accessible by and / or integrated into the software tool, e.g., via a model number, etc. The software tool may be on the wire bonding machine (e.g., running on a computer of the wire bonding machine) or may be offline from the wire bonding machine.

[0014] As used herein, the term "semiconductor device" is intended to refer to any structure that includes (or is configured to include in a subsequent process) a semiconductor chip or die. Exemplary semiconductor devices include bare semiconductor die, semiconductor die on a substrate (e.g., lead frames, PCBs, carriers, semiconductor chips, semiconductor wafers, BGA substrates, semiconductor devices, etc.), packaged semiconductor devices, flip chip semiconductor devices, die embedded in a substrate, and stacks of semiconductor dies, among others. Additionally, semiconductor devices can include elements bonded to or otherwise configured to be included in a semiconductor package (e.g., spacers bonded in a stacked die structure, substrates, etc.).

[0015] As used herein, the term "substrate" is intended to refer to any structure to which a semiconductor device is bonded. Exemplary substrates include, for example, lead frames, PCBs, carriers, modules, semiconductor chips, semiconductor wafers, BGA substrates, other semiconductor devices, and the like.

[0016] As used herein, the term "package data" is intended to refer to data relating to a given semiconductor package. Exemplary information included in such package data includes the two-dimensional (and / or three-dimensional) wiring layout of the semiconductor package, the height of the semiconductor element (e.g., die), bonding locations on the semiconductor element (e.g., die pad locations), bonding locations on a substrate (e.g., lead locations on a lead frame), the relative distance between a first bonding location and a second bonding location, wire diameter, and wire type.

[0017] As used herein, the term "semiconductor package" is intended to refer to any workpiece that includes a semiconductor device. Although the invention is described herein in the context of simple semiconductor packages (e.g., a semiconductor device on a substrate such as a semiconductor die on a lead frame), the invention is not limited to such semiconductor packages. The invention, in some aspects, is particularly applicable to more complex semiconductor packages such as high pin count packages, stacked die packages, SiP packages, SMT packages, and the like.

[0018] As used herein, the term "wire bonding application" is intended to refer to the details of wire bonding in a semiconductor package. Thus, a wire bonding application includes details of the semiconductor package related to the wire loops formed in the semiconductor package (e.g., the location of the wire loops in the semiconductor package, the location of the bonds on the wire loops, the spacing between the wire loops, details of the wire bonding program for forming the multiple wire loops, etc.).

[0019] 1A-1B and 2A-2B are examples of wire bonding tools as shown and described in International Publication No. WO 2008 / 005684 (entitled "BONDING TOOL WITH IMPROVED FINISH"). With specific reference to FIG. 1A, wire bonding tool 100 includes a shaft portion 102 and a cone-shaped portion 104. Shaft portion 102 and cone-shaped portion 104 may collectively be referred to as the body portion of wire bonding tool 100. As is well known to those skilled in the art, a terminal portion of shaft portion 102 (i.e., the end of shaft portion 102 at the top of the view in FIG. 1A) is configured to engage a transducer (e.g., an ultrasonic transducer) of a wire bonding apparatus. The terminal end of the conical portion 104 (i.e., the end of the conical portion 104 at the bottom of the view in FIG. 1A) is configured to form a wire bond at a bonding location (e.g., a die pad of a semiconductor die, a lead of a lead frame / substrate, etc.). FIG. 1B is a detailed view of the terminal end of the conical portion 104. Specifically, tip portion 100a of wire bonding tool 100 is shown in FIG. 1B. Tip portion 100a defines, among other things, a hole portion 100b, an inner chamfer 100c, and a face portion 100d.

[0020] FIG 2A is a cross-sectional side view of another wire bonding tool 200. Wire bonding tool 200 includes a shaft portion 202 and a cone-shaped portion 204 (collectively, a body portion). FIG 2B is a detailed view of the terminal end of cone-shaped portion 204. Specifically, tip portion 200a of wire bonding tool 200 is shown in FIG 2B. Tip portion 200a defines, among other things, bore portion 200b, inner chamfer 200c, and face portion 200d.

[0021] 3A-3B show a semiconductor package 106. FIG. 3A is a side view of the semiconductor package 106, and FIG. 3B is a top view of the semiconductor package 106. The semiconductor package 106 includes a semiconductor element 108 (e.g., a semiconductor die) and a substrate 110 (e.g., a lead frame). Wire loops 114a, 114b, and 114c each include (i) a first wire bond bonded to a bonding location 108a (e.g., a die pad) on the semiconductor element 108, (ii) a second wire bond bonded to a bonding location 110a (e.g., a lead) on the substrate 110, and (iii) a portion of a wire extending between the first wire bond and the second wire bond.

[0022] As one skilled in the art will appreciate, the specifications of a wire bonding tool (e.g., the wire bonding tool of Figures 4A-4D) are important in ensuring proper clearance between the wire bonding tool and other structures in a wire bonding application when forming wire loops 114a, 114b, and 114c of semiconductor package 106. Similarly, the specifications of the wire bonding tool are important in designing the sequence for forming multiple wire loops in a semiconductor package (and in ensuring proper clearance between the wire bonding tool and other structures of the semiconductor package) in a wire bonding application.

[0023] 4A-4D, a method for determining the suitability of a wire bonding tool for a given wire bonding application is shown. Specifically, each of FIGS. 4A-4D shows a simulation in which a tip of a wire bonding tool contacts a portion of a semiconductor package (i.e., semiconductor package 106 of FIGS. 3A-3B) for purposes of determining, for example, whether there is adequate clearance between the wire bonding tool and other structures in the wire bonding application (where the wire bonding application is a semiconductor package in a state in which wire bonding is performed). That is, although FIGS. 4A-4D actually show tips of a wire bonding tool (e.g., tips 100a1, 100a2, 100a3, and 100a4) related to a wire bonding process, these figures show a portion of a simulation performed (e.g., in software) using the specifications of the wire bonding tool and package data of the semiconductor package to test whether the wire bonding tool is suitable for the wire bonding application.

[0024] While Figures 4A-4D show simulations for testing proper clearance in relation to one location within the semiconductor package 106, it will be understood that multiple (and potentially many) locations within the semiconductor package 106 will need to be tested to actually determine the suitability of a wire bonding tool for a particular wire bonding application.

[0025] With particular reference to FIG. 4A, a simulation of a wire bonding tool tip 100a1 is shown. Wire loops 114a, 114b, 114c have already been formed (e.g., simulated at their respective locations within a semiconductor package) between a semiconductor device 108 and a substrate 110. The wire bonding tool tip 100a1 is configured to bond a wire 114d' between the semiconductor device 108 and the substrate 110. FIG. 4A shows the tip 100a1 preparing to form another wire loop (see, e.g., wire loop 114d shown in dotted lines in FIG. 3B). In this simulation, it can be determined that the wire bonding tool (including tip 100a1) interferes (or may interfere) with the existing wire loop 114c. Thus, tip 100a1 is not suitable for wire bonding applications in semiconductor package 106, at least because it does not have adequate clearance for wire loop 114c.

[0026] Similarly, Figure 4B shows tip 100a2 preparing to form wire loop 114d (see Figure 3B). In this simulation, it can be determined that the wire bonding tool (including tip 100a2) interferes (or may interfere) with existing wire loop 114c. Thus, tip 100a2 is not suitable for wire bonding applications in semiconductor package 106, at least because it does not have adequate clearance for wire loop 114c.

[0027] However, in Fig. 4C, since there is no interference between tip 100a3 and existing wire loop 114c, it can be determined that the wire bonding tool (including tip 100a3) is compatible with the wire bonding application of semiconductor package 106. Similarly, in Fig. 4D, since there is no interference between tip 100a4 and existing wire loop 114c, it can be determined that the wire bonding tool (including tip 100a4) is compatible with the wire bonding application of semiconductor package 106. In a manner similar to the verification process shown in Figs. 4A-4D, the clearance between the wire bonding tool (including tip 100a3 / 100a4) and other structures within semiconductor package 106 can be verified.

[0028] 5 is a flow diagram illustrating a method for determining suitability of a wire bonding tool for a wire bonding application. Those skilled in the art will understand that certain steps included in the flow diagram may be omitted, certain additional steps may be added, and the order of steps may be changed from the order shown, all within the scope of the present invention.

[0029] At step 502, a wire bonding tool specification (e.g., including data regarding dimensions of the wire bonding tool) is provided. At optional step 504, package data for the wire bonding application is provided. For example, the package data provided includes at least one of (i) CAD data related to the wire bonding application, and / or (ii) package data derived using an online teaching reference system of the wire bonding machine. Details of the package data provided may include, among others, at least one of the following: a two-dimensional (and / or three-dimensional) wiring layout of the semiconductor package, a height of the semiconductor device, a position of the die pads of the semiconductor device, a position of the leads of the lead frame, a relative distance between a first bonding location and a second bonding location, a diameter of the wire, a type of wire, etc.

[0030] In step 506, it is determined whether the wire bonding tool is qualified for the wire bonding application using (i) the software tool and (ii) the specifications (and package data, if necessary) provided in step 502. For example, Figures 4A-4D illustrate determining whether four different wire bonding tools are qualified for a wire bonding application (including semiconductor package 106).

[0031] Steps 502 and 506 (and step 504) may be repeated for multiple wire bonding tools, e.g., until a qualified wire bonding tool for the wire bonding application is determined. For the wire bonding application shown in Figures 3A-3B, four different wire bonding tools have been examined and the detection of two different "qualified" wire bonding tools has been determined in Figures 4A-4D.

[0032] At optional step 508, aspects of the wire bonding application are adjusted to account for potential interference with the wire bonding tool during the wire bonding operation. Exemplary adjustments to aspects of the wire bonding application include (i) adjusting a wire bond location in a wire bonding program, (ii) adjusting a trajectory for forming a wire loop in the wire bonding application, (iii) adjusting a shape of a wire loop in the wire bonding application, (iv) adjusting an order for forming multiple wire loops in the wire bonding application, and (v) adjusting at least one bonding parameter during the formation of at least one wire bond in the wire bonding application.

[0033] Although the invention has been illustrated and described herein with reference to specific embodiments, it is not intended that the invention be limited to the details shown, but rather various changes in the details may be made within the scope of the claims and the equivalents thereof without departing from the invention.

Claims

1. 1. A method for determining suitability of a wire bonding tool for a given wire bonding application, comprising: (a) providing a specification for a wire bonding tool; (b) using (i) a software tool and (ii) the specifications provided in step (a) to determine whether the wire bonding tool is qualified for the wire bonding application; A method comprising:

2. 2. The method of claim 1, wherein the specifications provided in step (a) include data relating to dimensions of the wire bonding tool.

3. 2. The method of claim 1, wherein step (b) includes using a software tool on a wire bonding machine to determine whether the wire bonding tool is qualified for the wire bonding application.

4. 2. The method of claim 1, wherein step (b) includes using a software tool on a computer offline from a wire bonding machine to determine whether the wire bonding tool is suitable for the wire bonding application.

5. 2. The method of claim 1, wherein step (b) includes determining whether there is at least one of actual interference between the wire bonding tool and other structures involved in the wire bonding application and potential interference between the wire bonding tool and other structures involved in the wire bonding application.

6. 2. The method of claim 1, wherein step (b) includes determining whether an acceptable clearance exists between the wire bonding tool and other structures involved in the wire bonding application during a wire bonding operation.

7. The method of claim 6 , wherein the other structures include at least one of adjacent wire loops and other electronic components.

8. 2. The method of claim 1, wherein step (b) includes determining whether an acceptable clearance exists between the wire bonding tool and other structures involved in the wire bonding application during at least one of: (b1) forming a first wire bond of a wire loop; (b2) forming a second wire bond of the wire loop; and (b3) a trajectory of the wire bonding tool while forming a wire loop between the first wire bond and the second wire bond.

9. 10. The method of claim 1, wherein steps (a) and (b) are repeated for multiple wire bonding tools.

10. 2. The method of claim 1, wherein steps (a) and (b) are repeated for a plurality of wire bonding tools until a qualified wire bonding tool for the wire bonding application is determined.

11. The method of claim 1 further comprising: The method includes adjusting aspects of a wire bonding application to account for potential interference with a wire bonding tool during a wire bonding operation.

12. 12. The method of claim 11, wherein the adjusting step comprises adjusting wire bond locations in a wire bond program.

13. 12. The method of claim 11, wherein the adjusting step comprises adjusting a trajectory that forms a wire loop in the wire bonding application.

14. 12. The method of claim 11, wherein the adjusting step comprises adjusting a shape of a wire loop in the wire bonding application.

15. 12. The method of claim 11, wherein the adjusting step comprises adjusting an order in which multiple wire loops are formed in the wire bonding application.

16. 12. The method of claim 11, wherein the adjusting step comprises adjusting at least one bonding parameter during formation of at least one wire bond in the wire bonding application.

17. The method of claim 1 further comprising: providing package data for the wire bonding application; The method, wherein step (b) includes using the software tool, the specifications provided in step (a), and the package data to determine whether the wire bonding tool is qualified for the wire bonding application.

18. 20. The method of claim 17, wherein the provided package data includes at least one of (i) CAD data associated with the wire bonding application, and (ii) package data derived using an online teaching reference system of a wire bonding machine.

19. 20. The method of claim 17, wherein the provided package data includes at least one of a two-dimensional wiring layout of the semiconductor package, a three-dimensional wiring layout of the semiconductor package, a height of the semiconductor element, a bonding location on the semiconductor element, a bonding location on the substrate, a relative distance between a first bonding location and a second bonding location, a wire diameter, and a wire type.

20. 2. The method of claim 1, wherein the specifications provided in step (a) are integrated into the software tool.