Oversampling Analog-to-Digital Converter

Abstract

The ADC (100) includes a comparator (102) for providing a comparator output in response to the ADC input voltage and a DAC output voltage, a SAR circuit (108) including a SAR for storing an n-bit digital code initialized at the beginning of a conversion phase of the ADC, the SAR circuit for updating the digital code in response to the comparator output, and the ADC output being responsive to the digital code at the end of the conversion phase, and a DAC (106) for providing a DAC output voltage in response to the digital code and a reference voltage. The DAC includes an m-bit CDAC (204) and an (nm)-bit RDAC (202) for providing an intermediate voltage in response to the nm least significant bits of the digital code and the reference voltage. The CDAC provides a DAC output voltage in response to the m most significant bits of the digital code, the intermediate voltage, and the reference voltage.

Description

[Background technology]

[0001] An analog-to-digital converter (ADC) converts an analog input signal (e.g., a voltage) into a digital output signal (also called a "digital code" or simply "code"). An ADC uniquely represents all analog inputs within a certain range by a limited number of digital output codes. Because the analog scale is continuous, while the digital code scale is discrete, there is a quantization process that introduces errors. Thus, analog voltages of a small range will be resolved by the ADC into the same digital output code. As a result, a plot of analog input voltage versus digital output code has a stepped shape. The width of one step is defined as one least significant bit (LSB), and is often used as a reference unit for other quantities or units of the full analog range. For example, 1 / 2 LSB represents an analog quantity equal to 1 / 2 the analog resolution. Summary of the Invention

[0002] In one example of the present description, the ADC includes an input adapted to receive an input voltage, an output, and a comparator having a first input coupled to the input of the ADC, a second input, and an output. The comparator is configured to provide a comparator output at the output in response to the input voltage and a digital-to-analog converter (DAC) output voltage. The ADC also includes a successive approximation register (SAR) circuit, the SAR circuit including an input coupled to the output of the comparator, and a SAR for storing an n-bit digital code initialized to an initial value at the beginning of a conversion phase of the ADC. The SAR circuit provides an n-bit digital code as an output at an output of the SAR circuit and is configured to update the n-bit digital code in response to the comparator output, and the output of the ADC is responsive to the n-bit digital code at the end of the conversion phase. The ADC also includes a DAC having an input, the DAC having an output coupled to the second input of the comparator, the DAC configured to provide a DAC output voltage in response to the n-bit digital code and a reference voltage. The DAC includes an m-bit capacitive DAC (CDAC) and an (nm)-bit resistive DAC (RDAC) coupled between the input of the DAC and the m-bit CDAC, the RDAC configured to provide an intermediate DAC voltage in response to the nm least significant bits of the n-bit digital code and a reference voltage, and the m-bit CDAC configured to provide a DAC output voltage in response to the m most significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage.

[0003] In another example of the present description, a method is provided for operating an ADC including a digital-to-analog converter (DAC) including an m-bit capacitive DAC (CDAC) and an (nm)-bit resistive DAC (RDAC), the method includes: comparing an input voltage of the ADC to an output voltage of the DAC, updating an n-bit digital code in response to the comparison, the output of the ADC being responsive to the n-bit digital code at the end of a conversion phase; providing an intermediate DAC voltage by the RDAC in response to the nm least significant bits of the n-bit digital code and a reference voltage; and providing a DAC output voltage by the CDAC in response to the m most significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage.

[0004] In yet another example herein, an ADC includes an input operable to receive an input voltage and an output operable to provide a digital representation of the input voltage. The ADC also includes a comparator having a first input coupled to the input of the ADC, a second input, and an output, the comparator configured to provide a comparator output at the output in response to the input voltage and a digital-to-analog converter (DAC) output voltage. The ADC further includes a DAC having an input, the DAC having an output coupled to the second input of the comparator, the DAC configured to provide a DAC output voltage in response to an n-bit digital code from a successive approximation register (SAR) circuit and a reference voltage. The DAC includes an m-bit capacitive DAC (CDAC) and a (nm)-bit resistive DAC (RDAC) coupled between the input of the DAC and the m-bit CDAC, where m is an integer greater than 0 but less than n, and the RDAC configured to provide an intermediate DAC voltage in response to the nm least significant bits of the n-bit digital code and the reference voltage. The m-bit CDAC is configured to provide a DAC output voltage in response to the m most significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage. m The conversion is based on the sum of the n-bit digital codes at the end of each of the conversion sub-phases. [Brief description of the drawings]

[0005] [Figure 1] 1 is a schematic block diagram of an analog-to-digital converter (ADC) in accordance with various examples.

[0006] [Diagram 2] 2 is a schematic block diagram of the ADC of FIG. 1 in which, in various examples, a feedback digital-to-analog converter (DAC) is implemented as a combination of a resistive DAC and a capacitive DAC.

[0007] [Diagram 3] 3 is a schematic circuit diagram of the capacitive DAC of FIG. 2, in accordance with various examples.

[0008] [Figure 4] 3 is a schematic circuit diagram of the capacitive DAC of FIG. 2 including rotation logic, according to various examples.

[0009] [Diagram 5] 3 is a graph of operating waveforms of the ADC of FIG. 2 during a conversion phase that includes multiple conversion sub-phases, according to various examples.

[0010] [Figure 6A] 1 is a schematic circuit diagram of a 1-bit capacitive DAC illustrating the reduction in differential nonlinearity error resulting from various examples of the present description. [Figure 6B] 1 is a schematic circuit diagram of a 1-bit capacitive DAC illustrating the reduction in differential nonlinearity error resulting from various examples of the present description.

[0011] [Figure 7] 1 is a flowchart of a method according to various examples.

[0012] In the drawings, the same reference numbers and other reference characters are used to denote the same or similar (functional and / or structural) features. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] ADCs are useful for sampling and converting analog input signals (e.g., voltages) into digital output signals or codes. Integrated circuits (ICs) for power management (e.g., power ICs), such as those used in battery chargers for electronic devices, use ADCs to monitor various operating parameters (e.g., indicated by corresponding analog voltages). The ADC provides digital codes indicative of the operating parameters, and the power IC may adjust its operation in response to such digital codes. For example, a sensed signal (an analog signal representing voltage and / or current) may be provided to an ADC that converts the sensed signal into a digital representation of the sensed signal, and the digital signal is provided to a controller / processor that manipulates / processes the digital signal and returns a control signal to the power management device to control the operation of the power management device.

[0014] Various types of errors exist in ADCs. One such error is differential nonlinearity (DNL) error. As mentioned above, analog voltages are continuous signals and digital codes are discrete values, so the relationship between the digital output code of an ADC and the analog input voltage has a step shape. For a digital-to-analog converter (DAC), the analog output voltage is determined based on the digital input code, resulting in a step-like voltage increase from one digital code to the next. An ADC may include an internal DAC, and the linearity of such an internal DAC affects the linearity of the ADC. The width of each step for an ADC is a function of the resolution of the ADC as well as component mismatches within the ADC, including DAC components within the ADC. As explained further below, such component mismatches can result in DNL errors. DNL error refers to the difference between the actual step width between successive digital codes and the step width of an ideal ADC (or the difference in step height between the actual DAC and the ideal DAC). An ideal ADC step size is sometimes referred to as "1 LSB" (where "LSB" means least significant / lower bit). DNL error may be expressed in units of LSB. For example, a DNL error of +1 / 2 LSB means that the step size is 50% larger than the ideal ADC step size.

[0015] While the relationship between analog input code and digital output code is linear for an ideal ADC, DNL errors result in a nonlinear relationship between analog input code and digital output code. Therefore, it is useful to reduce the DNL errors in an ADC.

[0016] The present illustrative example addresses the above using an oversampling successive approximation register (SAR) ADC, where the sampling rate of the ADC exceeds the system timing constraints for the analog input voltage (e.g., the sampling period of the ADC is less than the system timing constraints). In an oversampling ADC, the analog input voltage is sampled by the ADC at a rate higher than the minimum sampling rate (e.g., the Nyquist sampling rate). For example, when using an n-bit ADC without oversampling, a 100 Hertz (Hz) input signal is sampled at 200 Hz (e.g., a Nyquist sampling rate at least equal to 2×100 Hz) to provide the digital output code of the ADC. However, when oversampling by a factor of, for example, k=4, the same 100 Hz input signal is sampled at 800 Hz (e.g., k×2×100 Hz). In this example, k=4 is referred to as the oversampling ratio or oversampling factor. In some examples, the output of the ADC may be the sum of the resulting digital codes for the k samples, while in other examples, the output of the ADC may be the average of the resulting digital codes for the k samples.

[0017] Regardless of the particular oversampling ratio of a SAR ADC, the ADC also includes a feedback DAC that provides part of the successive approximation function of the binary search implemented by such a SAR ADC. In general, the feedback DAC provides a DAC output voltage (e.g., an analog output) in response to an n-bit digital code input. The specific function of the feedback DAC is described in more detail below. However, in the example of this description, the feedback DAC includes both a resistive DAC (RDAC) and a capacitive DAC (CDAC). The RDAC and CDAC are in a cascaded arrangement, with the RDAC providing as its output an intermediate DAC voltage responsive to the (nm) LSBs of the n-bit digital code. In the cascaded arrangement, the CDAC provides as its output a DAC output voltage responsive to the intermediate DAC voltage from the RDAC and the m most significant bits (MSBs) of the n-bit digital code.

[0018] In some examples, the oversampling ratio of the SAR ADC is 2 m (For example, k=2 m The ADC conversion phase is m In each conversion subphase, the ADC provides an intermediate digital code, and the output of the ADC is m Based on the intermediate digital code from two conversion subphases. For example, the output of an ADC is m The output of the ADC may be the sum of the intermediate digital codes from the two conversion sub-phases, or m It may also be the average of the intermediate digital codes from the transform sub-phases.

[0019] In the example described below, CDAC is 2 m Ideally, it would contain two capacitors. mThe capacitors have equal capacitance. However, as mentioned above, component mismatch can occur in real-world applications, resulting in DNL errors (or an increase in the magnitude of the DNL errors). To address DNL errors caused or exacerbated by mismatch in the CDAC components, the CDAC is m In each of the conversion sub-phases, m The input capacitor includes a rotation logic configured to provide an intermediate DAC voltage from the RDAC to a different one of the capacitors.

[0020] In one example, m=2, and therefore there are four conversion sub-phases, and the CDAC includes four capacitors. In this example, during a first conversion sub-phase, the rotation logic is configured to provide an intermediate DAC voltage from the RDAC to a first capacitor of the CDAC. During a second conversion sub-phase, the rotation logic is configured to provide an intermediate DAC voltage from the RDAC to a second capacitor of the CDAC. During a third conversion sub-phase, the rotation logic is configured to provide an intermediate DAC voltage from the RDAC to a third capacitor of the CDAC. Finally, during a fourth conversion sub-phase, the rotation logic is configured to provide an intermediate DAC voltage from the RDAC to a fourth capacitor of the CDAC.

[0021] As will be explained further below, the rotation logic of the CDAC also rotates the remaining capacitors of the CDAC (e.g., the capacitors other than the capacitors on which the intermediate DAC voltage is provided, i.e., the two m The capacitors in the CDAC may be configured to be controlled in a rotational fashion as well. For example, the capacitors in the CDAC may be controlled by various control signals (e.g., m-1 control signal). Continuing with the above example where m=2, there are three control signals. In this example, during the first conversion sub-phase, the rotation logic is configured to control the coupling of the second capacitor with the first control signal. During the second conversion sub-phase, the rotation logic is configured to control the coupling of the third capacitor with the first control signal. During the third conversion sub-phase, the rotation logic is configured to control the coupling of the fourth capacitor with the first control signal. Finally, during the fourth conversion sub-phase, the rotation logic is configured to control the coupling of the first capacitor with the first control signal. The rotation logic is similarly configured to apply other control signals in a rotating manner, which is described further below.

[0022] As mentioned above, the output of the ADC is 2 m It may be the sum (or average) of the intermediate digital codes from the two transformation sub-phases. m By rotating the control signal for the capacitors of the CDAC for each of the conversion sub-phases, as well as rotating the capacitors to which the intermediate DAC voltage from the RDAC is provided, component mismatches that may be present in the capacitors of the CDAC are effectively cancelled out at the output of the ADC. Reducing the effect of component mismatches present in the CDAC also reduces the DNL errors of the ADC, which is useful as discussed above. These and other examples are further described below with reference to the accompanying figures.

[0023] 1 is a schematic block diagram of a device 100 that is an analog-to-digital converter (ADC) 100, in various examples. In particular, the ADC 100 is a SAR ADC 100, but for simplicity, will be referred to simply as ADC 100 below. The ADC 100 is illustrated generally, and the specific circuit implementation of the various functional blocks may differ from that shown in the figure. The ADC 100 is configured to receive an analog input voltage (VIN) as an input and provide a digital code as an output. The digital code output may generally be an n-bit digital code (e.g., (ADC_DATA_OUT[n-1:0]).

[0024] The ADC 100 includes a comparator 102 having a non-inverting input (+), an inverting input (-), and a comparator output (COMP_OUT). In the example of Figure 1, the ADC 100 includes a sample / hold circuit 104 configured to receive (e.g., sample) an analog input voltage and provide (e.g., hold) a stable output voltage corresponding to the analog input voltage. The output of the sample / hold circuit 104 is provided to the non-inverting input of the comparator 102, in this example.

[0025] The ADC 100 also includes a DAC 106 configured to provide a DAC output voltage. The output of the DAC 106 is provided to an inverting input of the comparator 102. The DAC 106 is described further below.

[0026] The ADC 100 includes a SAR circuit 108 that includes a register (e.g., a SAR) configured to store an n-bit digital code. The SAR circuit 108 is coupled to the output of the comparator 102 and is therefore configured to receive the output of the comparator 102. The n-bit digital code stored in the SAR circuit 108 is initialized to an initial value at the beginning of a conversion phase of the ADC 100 to facilitate implementation of a binary search algorithm (e.g., a successive approximation binary search). For example, the n-bit digital code stored in the SAR may be initialized to an MSB (most significant / high order bit) of 1 followed by all zeros (e.g., 10...0).

[0027] The SAR circuit 108 is configured to provide as an output the n-bit digital code stored in the SAR circuit 108. The SAR circuit 108 is also configured to update the n-bit digital code stored in the SAR in response to the value of the output of the comparator 102. The output of the ADC 100 is based on the n-bit digital code stored in the SAR circuit 108 at the end of the conversion phase.

[0028] The n-bit digital code stored in the SAR circuit 108 is provided to the DAC 106 (e.g., DAC_DATA_IN[n-1:0]), which is configured to convert the received n-bit digital code to an analog voltage and provide the resulting analog voltage as the DAC 106 output voltage. A reference voltage generator 110 provides a reference voltage (VREF), which may be a full-scale voltage, to the DAC 106. The DAC 106 uses the reference voltage to convert the n-bit digital code to the DAC 106 output voltage.

[0029] The comparator 102 effectively compares an analog input voltage (VIN) to the output of the DAC 106 and provides the result of the comparison to the SAR circuit 108. The SAR circuit 108 provides an n-bit digital code to the DAC 106 as an approximation digital code of VIN. The DAC 106 provides an analog voltage representing the approximation digital code from the SAR circuit 108 to the comparator 102.

[0030] As described above, the SAR circuit 108 can be initialized to store an n-bit digital code with all 0s following the MSB equal to 1. Thus, the DAC 106 initially provides the comparator 102 with an analog voltage corresponding to the n-bit digital code (e.g., 10...0) from the SAR circuit 108, and this voltage can be, for example, VREF / 2. The comparator 102 compares the voltage from the DAC 106 with the analog input voltage (VIN). Thus, when VIN > VREF / 2, the output of the comparator 102 is asserted (e.g., the output goes "high"). When VIN < VREF / 2, the output of the comparator 102 is de-asserted (e.g., the output goes "low"). The SAR circuit 108 is configured to set the MSB-1 bit in response to the output of the comparator 102. For example, following initialization, if the output of the comparator 102 is asserted, the SAR circuit 108 updates the MSB-1 bit of the n-bit digital code to 1. If the output of the comparator 102 is de-asserted, the SAR circuit 108 updates the second MSB of the n-bit digital code to 0. This binary search cycle is repeated until all bits of the n-bit digital code stored in the SAR circuit 108 have been tested. When all n bits of the n-bit digital code stored in the SAR circuit 108 have been tested, the conversion phase (or sub-phase) ends, and the n-bit digital code stored in the SAR circuit 108 becomes the output of the ADC 100.

[0031] FIG. 2 is a schematic block diagram of the ADC 100 of FIG. 1 in which, in various examples, the feedback DAC 106 is implemented as a combination of an RDAC 202 and a CDAC 204. In FIG. 2, elements with the same numbers as the elements of FIG. 1 have the same general functions as described above with respect to FIG. 1, and additional elements and their features specific to FIG. 2 are described below.

[0032] RDAC202 can be a resistor ladder-based RDAC, while CDAC204 will be described in more detail below. As described above, DAC106 is an n-bit DAC, and the SAR circuit 108 is configured to provide the n-bit digital code stored therein to DAC106 as an output (where, for example, m bits go to CDAC204 and n - m bits go to RDAC202). CDAC204 is an m-bit CDAC, while RDAC202 is an (n - m)-bit RDAC. Thus, of the n-bit digital code from the SAR circuit 108, (n - m) least significant bits (e.g., DAC_DATA_IN[n - m - 1:0]) are provided to RDAC202, while m most significant bits (e.g., DAC_DATA_IN[n - 1:n - m]) are provided to CDAC204. In some examples, m can be greater than 0 and m can be less than n (e.g., 0 < m < n, where m and n are integer values).

[0033] Also, as described above, RDAC202 and CDAC204 are in a cascaded arrangement, and the output of RDAC202 is an intermediate DAC voltage provided as an input to CDAC204.

[0034] RDAC202 provides an intermediate DAC voltage in response to the (n - m) least significant bits of the n-bit digital code received from the SAR circuit 108 and VREF from the reference voltage generator 110. In particular, RDAC202 is configured to convert DAC_DATA_IN[n - m - 1:0] to an analog voltage and provide the resulting analog voltage as the intermediate DAC voltage. RDAC202 also uses VREF to convert DAC_DATA_IN[n - m - 1:0] to the intermediate DAC voltage.

[0035] In the cascaded arrangement shown in FIG. 2, CDAC204 provides, as its output, a DAC106 output voltage corresponding to the intermediate DAC voltage from RDAC202, the m most significant bits of the n-bit digital code from the SAR circuit 108, and VREF from the reference voltage generator 110.

[0036] 2, the (nm)-bit LSB of the n-bit digital code from SAR circuit 108 is resolved by RDAC 202, while the m-bit MSB of the n-bit digital code from SAR circuit 108 is resolved by CDAC 204. In FIG. 2, the overall functionality of DAC 106 is as described above with respect to FIG.

[0037] As mentioned above, in some examples, the oversampling ratio of the ADC 100 is 2 m (For example, k=2 m ). Therefore, the conversion phase of the ADC100 is 2 m The conversion process includes two conversion sub-phases. At the end of each conversion sub-phase (e.g., when all n bits of the n-bit digital code stored in SAR circuit 108 have been tested), the n-bit digital code stored in SAR circuit 108 is provided to output register 206. The output of SAR circuit 108 at the end of each conversion sub-phase may be referred to as an intermediate digital code, and therefore output register 206 may be configured to store an intermediate digital code. m 2 corresponding to the conversion sub-phases m The intermediate digital code is configured to store the intermediate digital codes.

[0038] The output of ADC 100 is based on the intermediate digital codes stored in output register 206 after the last conversion sub-phase (e.g., the fourth conversion sub-phase, when m=2). Continuing with the example where m=2, the output of ADC 100 can be the sum of the four intermediate digital codes stored in output register 206, or the output of ADC 100 can be the average of the four intermediate digital codes stored in output register 206.

[0039] The oversampling ADC 100 described herein reduces DNL errors in one or more ways. First, in some examples, the cascaded arrangement of the DACs 106 of FIG. 2 reduces the linearity requirement of the RDAC 202 by 2. m This results in a factor of 1 reduction, thereby reducing the DNL error of the ADC 100. Second, as will be explained further below, the CDAC 204 includes rotation logic that rotates the ADC 204 by a factor of 2. m For each of the conversion sub-phases, the control signals for the capacitors in the CDAC 204 are rotated and the intermediate DAC voltage from the RDAC 202 is provided to rotate the capacitors of the CDAC 204. Thus, any component mismatch that may be present in the capacitors of the CDAC 204 is effectively cancelled out at the output of the ADC 100, thereby further reducing the DNL errors of the ADC 100.

[0040] Figure 3 is a schematic circuit diagram of the CDAC 204 of Figure 2, in various examples. In Figure 3, the CDAC 204 is shown without the rotation logic described above to introduce the general functionality of the CDAC 204. Figure 4, described below, shows the CDAC 204 including the rotation logic 402, in various examples.

[0041] 3, m=2, and therefore the CDAC 204 includes four capacitors, namely, a first capacitor 302, a second capacitor 304, a third capacitor 306, and a fourth capacitor 308, which may be unitary capacitors (e.g., having equal rated capacitance). The capacitors 302, 304, 306, and 308 may alternatively be referred to as C0, C1, C2, and C3, respectively. In this example, the DNL error of the ADC 100 depends on the matching between the unitary capacitors 302, 304, 306, and 308. Also, for purposes of illustration, n=12 in this example, and therefore the CDAC 204 receives DAC_DATA_IN[11:10] from the SAR circuit 108.

[0042] During the sample phase, signal S is asserted (e.g., has a logic "high" or logic "1" value to cause the switches to be "closed" or conductive), which causes each of the capacitors 302, 304, 306, 308 to be coupled to the input voltage node of the ADC 100 and therefore charged to the analog input voltage V. This effectively functions as a sample / hold circuit 104 shown generally in FIGS. 1 and 2, as described further below. The conversion phase of the ADC 100 begins following the sample phase, at which point signal S is deasserted (e.g., has a logic "low" or logic "0" value to cause the switches to be "opened" or non-conducting), which disconnects the capacitors 302, 304, 306, 308 from the input voltage nodes of the ADC 100. Also during the conversion phase, signal C is asserted. Signals S and C may be generated internally to the ADC 100, such as by the SAR circuit 108.

[0043] As mentioned above, the intermediate DAC voltage from RDAC 202 is provided to one of the capacitors of CDAC 204, which is the first capacitor 302 in Figure 3. Thus, capacitor 302 receives the output of RDAC 202 during the conversion phase since signal C is asserted. The remaining capacitors 304, 306, 308 are coupled to the reference voltage generator 110 (e.g., to receive VREF) or to ground based on various control signals.

[0044] In particular, the CDAC 204 derives three control signals (e.g., 2 control signals) from the m-bit MSBs of the n-bit digital code (e.g., DAC_DATA_IN[11:10]) from the SAR circuit 108. m -1). In FIG. 3, the control signals are b1, b2, and b3 (illustrated in FIG. 3 as C.b1, C.b2, and C.b3, respectively). The control signals may be thermometric-decoded values. For example, they may be: b1=DAC_DATA_IN

[11] +DAC_DATA_IN

[10] b2=DAC_DATA_IN

[11] and b3=DAC_DATA_IN

[11] .DAC_DATA_IN

[10] Here, "+" indicates a logical OR operation and "." indicates a logical AND operation.

[0045] Thus, the capacitors 304, 306, 308 are coupled to either the reference voltage generator 110 or a ground terminal based on the input code DAC_DATA_IN[11:10] from the SAR circuit 108.

[0046] As described above, the SAR circuit 108 may be initialized to store an n-bit digital code with an MSB equal to 1. Thus, the CDAC 204 initially receives DAC_DATA_IN[11:10] equal to 0b10. Then, initially, b1 is asserted (e.g., 1 OR 0 is 1) to couple the capacitor 304 (e.g., its bottom plate) to the reference voltage generator 110, b2 is asserted (e.g., DAC_DATA_IN

[11] is 1) to couple the capacitor 306 (e.g., its bottom plate) to the reference voltage generator 110, while b3 is deasserted (e.g., 1 AND 0 is 0) to couple the capacitor 308 (e.g., its bottom plate) to the ground terminal. Also, because DAC_DATA_IN[9:0] are initially all 0, the intermediate DAC voltage from the RDAC 202 is also the ground terminal voltage, and therefore the capacitor 302 (e.g., its bottom plate) is effectively coupled to the ground terminal. Thus, during conversion, when the bottom plates are coupled to either the reference voltage generator 110 or the ground terminal, due to the top plates of the capacitors 302, 304, 306, 308 floating, the top plates are biased accordingly since there is no change in the net charge on the respective capacitors. The net voltage at the DAC_OUT terminal is therefore VREF / 2-VIN (ignoring any parasitic capacitance for simplicity) based on the initialized value of DAC_DATA_IN[11:10].

[0047] As a result, when VIN > VREF / 2, the DAC_OUT terminal in FIG. 3 has a negative voltage, and thus the output of comparator 102 is asserted. When VIN < VREF / 2, the DAC_OUT terminal has a positive voltage, and thus the output of comparator 102 is de-asserted. In this way, capacitors 302, 304, 306, 308 implement the function of the sample / hold circuit 104 in FIGS. 1 and 2, and the function of comparator 102 is achieved by the exemplary single-ended coupling shown in FIG. 3, where the DAC_OUT terminal is coupled to the inverting input of comparator 102 while the non-inverting input of comparator 102 is coupled to the ground terminal. However, regardless of this particular implementation of comparator 102, comparator 102 provides its output based on the comparison of VIN and the DAC106 output voltage.

[0048] As described above, the SAR circuit 108 is configured to set the MSB-1 bit in response to the output of comparator 102. For example, following initialization, if the output of comparator 102 is asserted, the SAR circuit 108 updates DAC_DATA_IN

[10] to 1, and if the output of comparator 102 is de-asserted, the SAR circuit 108 updates DAC_DATA_IN

[10] to 0.

[0049] The SAR binary search algorithm continues to be implemented as described above, and in each iteration, the SAR circuit 108 sequentially sets the lower bits of the DAC_DATA_IN digital code until all n bits of the DAC_DATA_IN digital code are determined. The output of CDAC204 is the output of DAC106, which is based on the intermediate DAC voltage (e.g., RDAC_OUTPUT) from RDAC202, and the intermediate DAC voltage is based on DAC_DATA_IN[9:0].

[0050] In the example of FIG. 3, the CDAC 204 is implemented in a single-ended manner, since the comparator 102 compares the voltage at the DAC_OUT terminal with the voltage at the ground terminal. However, in other examples, the CDAC 204 may be implemented in a pseudo-differential manner by coupling the non-inverting input of the comparator 102 to the output of a second CDAC (not shown for simplicity), which is coupled to a ground terminal (or a common-mode terminal) during the sample phase (e.g., when the S signal is asserted) and to a ground terminal during the conversion phase (e.g., when the C signal is asserted). A pseudo-differential implementation may improve CDAC performance, such as in the presence of non-idealities including clock feedthrough and switch charge injection. In yet another example, the CDAC 204 may be implemented in a fully differential manner by coupling the non-inverting input of the comparator 102 to the output of a second DAC, which may be a mirror image of the DAC 106, but which receives a negative reference voltage (e.g., −VREF). In this example, the SAR circuit 108 may be modified to include logic that allows the output code to be a negative value.

[0051] 4 is a schematic circuit diagram of the CDAC 204 of FIGS. 2 and 3 including rotation logic 402 in various examples. The rotation logic 402 is configured to provide an intermediate DAC voltage (e.g., RDAC_OUTPUT) from the RDAC 202 to a different one of the capacitors 302, 304, 306, 308 in each of four conversion sub-phases (e.g., in the illustrated example where m=2). The rotation logic 402 also rotates the remaining capacitors of the CDAC 204 (e.g., the two capacitors other than the capacitor to which the intermediate DAC voltage is provided). m For example, the rotation logic 402 may be configured to control the coupling of each of the remaining capacitors of the CDAC 204 with a different one of the control signals (e.g., b1, b2, b3) in each of the four conversion sub-phases.

[0052] In Fig. 4, some elements are simplified for ease of illustration. For example, compared to Fig. 3, certain couplings of capacitors 302, 304, 306, 308 to either the reference voltage generator 110 (e.g., VREF) or the ground node are eliminated. However, control signals b1, b2, b3 may be applied in a manner similar to that described with respect to Fig. 3 (e.g., when b1 / b2 / b3 is asserted, the associated capacitor is coupled to the reference voltage generator 110, and when b1 / b2 / b3 is deasserted, the associated capacitor is coupled to the ground terminal).

[0053] The rotation logic 402, in one example, may be configured to implement a rotation algorithm 404. The rotation logic 402 is not necessarily limited to a particular rotation algorithm 404, but rather, the rotation algorithm 404 is one such example that may be implemented by the rotation logic 402.

[0054] Continuing with the example where m=2, with reference to the rotation algorithm 404, there are four conversion sub-phases. In the first conversion sub-phase, represented by block 406, the rotation logic 402 is configured to provide an intermediate DAC voltage to the first capacitor 302.

[0055] Also, during the first conversion sub-phase, the rotation logic 402 is configured to control the coupling of the second capacitor 304 with a first control signal b1. For example, when b1 is asserted, the second capacitor 304 is coupled to the reference voltage generator 110, and when b1 is deasserted, the second capacitor 304 is coupled to the ground terminal.

[0056] During the first conversion sub-phase, the rotation logic 402 is further configured to control the coupling of the third capacitor 306 with a second control signal b2. For example, when b2 is asserted, the third capacitor 306 is coupled to the reference voltage generator 110, and when b2 is deasserted, the third capacitor 306 is coupled to the ground terminal.

[0057] During the first conversion sub-phase, the rotation logic 402 is also configured to control the coupling of the fourth capacitor 308 with a third control signal b3. For example, when b3 is asserted, the fourth capacitor 308 is coupled to the reference voltage generator 110, and when b3 is deasserted, the fourth capacitor 308 is coupled to the ground terminal.

[0058] In a second conversion sub-phase, represented by block 408 , the rotation logic 402 is configured to provide an intermediate DAC voltage to the second capacitor 304 .

[0059] Also, during the second conversion sub-phase, the rotation logic 402 is configured to control the coupling of the third capacitor 306 with a first control signal b1. For example, when b1 is asserted, the third capacitor 306 is coupled to the reference voltage generator 110, and when b1 is deasserted, the third capacitor 306 is coupled to the ground terminal.

[0060] During the second conversion sub-phase, the rotation logic 402 is further configured to control the coupling of the fourth capacitor 308 with a second control signal b2. For example, when b2 is asserted, the fourth capacitor 308 is coupled to the reference voltage generator 110, and when b2 is deasserted, the fourth capacitor 308 is coupled to the ground terminal.

[0061] During the second conversion sub-phase, the rotation logic 402 is also configured to control the coupling of the first capacitor 302 with a third control signal b3. For example, when b3 is asserted, the first capacitor 302 is coupled to the reference voltage generator 110, and when b3 is deasserted, the first capacitor 302 is coupled to the ground terminal.

[0062] In a third conversion sub-phase, represented by block 410 , the rotation logic 402 is configured to provide an intermediate DAC voltage to the third capacitor 306 .

[0063] Also during the third conversion sub-phase, the rotation logic 402 is configured to control the coupling of the fourth capacitor 308 with a first control signal b1. For example, when b1 is asserted, the fourth capacitor 308 is coupled to the reference voltage generator 110, and when b1 is deasserted, the fourth capacitor 308 is coupled to the ground terminal.

[0064] During the third conversion sub-phase, the rotation logic 402 is further configured to control the coupling of the first capacitor 302 with a second control signal b2. For example, when b2 is asserted, the first capacitor 302 is coupled to the reference voltage generator 110, and when b2 is deasserted, the first capacitor 302 is coupled to the ground terminal.

[0065] During the third conversion sub-phase, the rotation logic 402 is also configured to control the coupling of the second capacitor 304 with a third control signal b3. For example, when b3 is asserted, the second capacitor 304 is coupled to the reference voltage generator 110, and when b3 is deasserted, the second capacitor 304 is coupled to the ground terminal.

[0066] In a fourth conversion sub-phase, represented by block 412 , the rotation logic 402 is configured to provide an intermediate DAC voltage to the fourth capacitor 308 .

[0067] Also during the fourth conversion sub-phase, the rotation logic 402 is configured to control the coupling of the first capacitor 302 with a first control signal b1. For example, when b1 is asserted, the first capacitor 302 is coupled to the reference voltage generator 110, and when b1 is deasserted, the first capacitor 302 is coupled to the ground terminal.

[0068] During the fourth conversion sub-phase, the rotation logic 402 is further configured to control the coupling of the second capacitor 304 with a second control signal b2. For example, when b2 is asserted, the second capacitor 304 is coupled to the reference voltage generator 110, and when b2 is deasserted, the second capacitor 304 is coupled to the ground terminal.

[0069] During the fourth conversion sub-phase, the rotation logic 402 is also configured to control the coupling of the third capacitor 306 with a third control signal b3. For example, when b3 is asserted, the third capacitor 306 is coupled to the reference voltage generator 110, and when b3 is deasserted, the third capacitor 306 is coupled to the ground terminal.

[0070] As mentioned above, the ADC100 has four outputs (e.g., 2 m The rotation logic 402 may be the sum (or average) of intermediate digital codes resulting from two (2) conversion sub-phases. m Because the control signals for the capacitors of CDAC 204, as well as the capacitors to which the intermediate DAC voltage from RDAC 202 is provided, are rotated for each of the conversion sub-phases, any component mismatch that may be present in the capacitors of CDAC 204 is effectively cancelled out at the output of ADC 100. Reducing the effects of component mismatch present in the CDAC also reduces the DNL errors of ADC 100, which is useful as discussed above.

[0071] FIG. 5 is a graph 500 of operating waveforms of the ADC 100 of FIG. 2 in various examples. In the example of FIG. 5, m=2 as described above, and therefore there are four conversion sub-phases. In the graph 500, the EN_ADC waveform is an enable signal for the ADC 100 as described above. The S and C signal waveforms are the S and C signal waveforms indicating the sample and conversion phases, respectively. The ADC_DONE waveform is a conversion complete signal indicating when the conversion phase (or sub-phase) is complete, and therefore the n-bit digital code of the SAR circuit 108 represents a determined digital code corresponding to the analog input voltage VIN. Finally, the ADC_DATA_OUT waveform indicates when the n-bit digital code resulting from a conversion sub-phase (e.g., an intermediate digital code for that sub-phase) is determined and therefore stored in the output register 206. For example, DATA1 is an n-bit digital code resulting from a first conversion sub-phase, DATA2 is an n-bit digital code resulting from a second conversion sub-phase, DATA3 is an n-bit digital code resulting from a third conversion sub-phase, and DATA4 is an n-bit digital code resulting from a fourth conversion sub-phase.

[0072] In graph 500, at time 502, the enable signal for ADC 100 is asserted, and therefore the S signal is also asserted, thereby starting the first sample phase. The first sample phase continues from time 502 to time 504, at which point the analog input voltage V has been sampled (e.g., capacitors 302, 304, 306, 308 are charged to V). At time 504, the S signal is deasserted, indicating the end of the sample phase. Also, the C signal is asserted, indicating the start of the first conversion sub-phase. At the start of the first conversion sub-phase, the SAR circuit 108 may be initialized to store an n-bit digital code with an MSB equal to 1. A SAR binary search algorithm is implemented as described above with respect to Figures 3 and 4, with the SAR circuit 108 progressively setting the less significant bits of the DAC_DATA_IN digital code in each iteration until all n bits of the DAC_DATA_IN digital code have been determined.

[0073] In graph 500, time 506 indicates the time when all n bits of the DAC_DATA_IN digital code have been determined in the first conversion sub-phase and therefore the ADC_DONE signal is asserted. As mentioned above, at the end of a conversion sub-phase, the DAC_DATA_IN digital code corresponds to the intermediate digital code provided to the output register 206 for that sub-phase. Thus, the ADC_DATA_OUT value (e.g., DATA1) also becomes available at time 506 and is therefore stored in the output register 206.

[0074] In graph 500, at time 508, the C signal is deasserted to indicate the end of the first conversion sub-phase, and the S signal is reasserted, thereby commencing the second sample phase, and the conversion process described above continues in a similar manner. Subsequent ADC_DATA_OUT values, DATA2, DATA3, and DATA4, are intermediate digital codes from the second, third, and fourth conversion sub-phases, respectively. The output of ADC 100 may be the sum (or average) of DATA1, DATA2, DATA3, and DATA4.

[0075] In the example of FIG. 5, one sample phase is included for each of the transform sub-phases. However, in other examples, fewer sample phases (e.g., one sample phase before the first transform sub-phase begins) may be implemented, thereby reducing the number of sample phases to four (e.g., two). m The bandwidth of the ADC 100 is further increased because multiple (or multiplexed) conversion sub-phases can be completed in a shorter amount of time.

[0076] 6A and 6B are schematic circuit diagrams of a 1-bit CDAC 600 illustrating the reduction in DNL error resulting from the example described herein. The CDAC 600 is generally similar to the CDAC 204 described above, but for a simplified example where m=1. The CDAC 600 thus includes two capacitors 602, 604. The capacitors 602, 604 may also be referred to as C0 and C1, respectively. In the example of FIG. 6A and FIG. 6B, the capacitor 602 has a capacitance of C, while the capacitor 604 has a capacitance of C+Δ. As mentioned above, such component mismatch is a source of DNL error for the DACs internal to the ADC, and therefore a source of DNL error for the ADC itself.

[0077] 6A and 6B, an (n-1)-bit RDAC 610 provides similar functionality to the RDAC 110 described above. For example, the RDAC 610 provides an intermediate DAC voltage in response to the (n-1) LSBs of the n-bit digital code received from the SAR circuit 108 and VREF from the reference voltage generator 110. In particular, the RDAC 610 is configured to convert DAC_DATA_IN[n-2:0] to an analog voltage and provide the resulting analog voltage as the intermediate DAC voltage.

[0078] Figure 6A is an example of the CDAC 600 in a first conversion sub-phase, and Figure 6B is an example of the CDAC 600 in a second conversion sub-phase. The sample phase is as described above, with signal S asserted to charge capacitors 602, 604 to the analog input voltage V. Although the rotation logic described above is not explicitly shown in Figures 6A and 6B, the functions implemented by the rotation logic in the conversion sub-phases are reflected by the various couplings of capacitors 602, 604.

[0079] 6A, the intermediate DAC voltage from the RDAC 610 is provided to the first capacitor 602 (e.g., because signal C is asserted). Also during the first conversion sub-phase, the second capacitor 604 is either coupled to the reference voltage generator 110 (e.g., to receive VREF) or coupled to a ground terminal based on a control signal. In this simplified example, the control signal is DAC_DATA_IN[n-1] from the SAR circuit 108.

[0080] 6B, the intermediate DAC voltage from the RDAC 610 is provided to the second capacitor 604 (e.g., because signal C is asserted). Also during the second conversion sub-phase, the first capacitor 602 is either coupled to the reference voltage generator 110 (e.g., to receive VREF) or coupled to a ground terminal based on DAC_DATA_IN[n-1] from the SAR circuit 108.

[0081] For ease of explanation, it may be assumed that there is no component mismatch in the RDAC 610. Under this assumption, DNL error is introduced by the CDAC 600 when V transitions between values ​​that results in an MSB transition in the ADC 100 output (and therefore a transition in the DAC_DATA_IN MSB). For example, DNL error occurs when V transitions from a first value with an expected result in a digital code of 0b10...1 to a second value with an expected result in a digital code of 0b10...0. This transition in the V value is referred to as the "MSB transition" for simplicity.

[0082] When the MSB transition occurs at VIN, the output value of the CDAC600 (DAC_OUT) is VREF / 2 n However, due to mismatch between capacitor 602 (having capacitance C) and capacitor 604 (having capacitance C+Δ), the actual magnitude of the DAC_OUT step in the first conversion subphase (FIG. 6A) is:

number

number

[0083] The actual magnitude of the DAC_OUT step in the second conversion sub-phase (FIG. 6B) is:

number

number

[0084] When Δ is equal to 0, DNL1 and DNL2 are both 0. However, even when Δ is non-zero, the rotation logic function implemented in Figures 6A and 6B effectively counteracts the effects of component mismatch to reduce or eliminate DNL error. For example, the average DAC_OUT step over the first conversion sub-phase and the second conversion sub-phase is:

number

[0085] 7 is a flow chart of a method 700 according to various examples. The method 700 begins in block 702 with comparing an input voltage of the ADC to an output voltage of a DAC of the ADC. For example, the analog input voltage V IN of the ADC 100 is compared to the output of the DAC 106 by the comparator 102 as described above. The DAC 106 also includes an m-bit CDAC 204 and an (nm)-bit RDAC 202, and is 0. <m<nである。

[0086] Method 700 continues with updating the n-bit digital code in response to the comparison at block 704. For example, SAR circuit 108 is configured to update the n-bit digital code in its SAR based on the output of comparator 102. The output of ADC 100 is based on the n-bit digital code stored by SAR circuit 108 when the conversion phase (or sub-phase) ends.

[0087] The method 700 further continues, at block 706, with the RDAC 202 providing an intermediate DAC voltage in response to the nm LSBs of the n-bit digital code from the SAR circuit 108 and a reference voltage, such as VREF, provided by the reference voltage generator 110. The method also continues, at block 708, with the CDAC 204 providing a DAC 106 output voltage in response to the m MSBs of the n-bit digital code, the intermediate DAC voltage from the RDAC 202, and the reference voltage VREF.

[0088] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B if device A generates a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0089] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or wired) at the time of manufacture by a manufacturer to perform such function and / or may be configurable (or reconfigurable) by a user after manufacture to perform such function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0090] A circuit or device described herein as including certain components may instead be coupled to such components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be coupled to at least some of such passive elements and / or sources, either during or after manufacture, by, for example, an end user and / or a third party, to form the described structure.

[0091] Although a component may be described herein as being of a particular process technology, such a component may be replaced with a component of another process technology. The circuits described herein are reconfigurable to include replacement components to provide at least partially similar functionality to that available prior to the replacement of the component. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as such a single resistor or capacitor.

[0092] As used herein, the terms "terminal," "node," "interconnect," "pin," "ball," and "lead" are used interchangeably. Unless otherwise noted, these terms are generally used to mean an interconnection between or termination of a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component. Some elements of the illustrated examples are included within the integrated circuit and others are external to the integrated circuit, while in other examples additional or fewer features may be incorporated within the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included within the integrated circuit and / or some features illustrated as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0093] Use of the phrase "ground potential" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a parameter means within + / - 10 percent of the parameter, or, if the parameter is zero, a reasonable range of values ​​around zero.

[0094] Modifications in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. An analog-to-digital converter (ADC), An input adapted to receive an input voltage, Outputs adapted to provide output signals, A comparator having a first input, a second input, and an output coupled to the input of the ADC, wherein the comparator is configured to provide a comparator output signal to the output in response to the input voltage and the output voltage of a digital-to-analog converter (DAC), A successive approximation register (SAR) circuit including an input coupled to the output of the comparator and an output coupled to the output of the ADC, the SAR being configured to store an n-bit digital code that is initialized to an initial value at the start of the conversion phase of the ADC, The n-bit digital code is provided as an output signal to the output of the SAR circuit. The n-bit digital code is updated in response to the comparator output signal. The SAR circuit is configured such that the output signal of the ADC responds to the n-bit digital code at the end of the conversion phase, A digital-to-analog converter (DAC) configured to provide the DAC output voltage in response to the n-bit digital code and a reference voltage, An m-bit capacitive DAC (CDAC) having a first input, a second input coupled to the output of the SAR circuit, and an output coupled to the second input of the comparator, An (n-m) bit resistive DAC (RDAC) having an input coupled to the output of the SAR circuit and an output coupled to the first input of the m-bit CDAC, wherein the (n-m) bit RDAC is configured to provide an intermediate DAC voltage in response to the n-m least significant bits of the n-bit digital code and the reference voltage, The DAC includes, Includes, The m-bit CDAC is configured to provide the DAC output voltage in response to the m most significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage, respectively.

2. The ADC according to claim 1, The aforementioned conversion phase is 2 ｍ It includes several conversion subphases, The ADC, An output register coupled to the output of the SAR circuit, the 2 ｍ The system further includes the output register, which is configured to store the n-bit digital code from the SAR circuit at the end of each of the individual conversion subphases. The output signal of the ADC is the 2 ｍ The two units stored in the output register at the end of each conversion subphase are ｍ An ADC based on the sum of n-bit digital codes.

3. The ADC according to claim 2, The output signal of the ADC is the 2 ｍ The two units stored in the output register at the end of each conversion subphase are ｍ ADC is the average of n-bit digital codes.

4. The ADC according to claim 2, The CDAC is 2 ｍ capacitors, and rotation logic configured to provide the intermediate DAC voltage to a different one of the 2 ｍ capacitors in each of the 2 ｍ conversion sub-phases, an ADC.

5. The ADC according to claim 4, The CDAC selects the m most significant bits from the n-bit digital code from the SAR circuit. ｍ - Configured to derive one control signal, The rotation logic is as follows: ｍ An ADC configured such that, in each of the individual conversion subphases, the coupling of each of the capacitors other than the capacitor to which the intermediate DAC voltage is provided is controlled by one of the different control signals.

6. The ADC according to claim 5, An ADC in which the coupling of the capacitor is either for receiving the reference voltage or for being coupled to the ground terminal.

7. The ADC according to claim 5, An ADC whose control signal is the thermometer-decoded value of the m most significant bits of the n-bit digital code.

8. The ADC according to claim 5, m is at least 2, the capacitor includes first to fourth capacitors, the conversion subphase includes first to fourth conversion subphases, and the control signal includes first to third control signals. The aforementioned rotation logic, During the first conversion subphase, the intermediate DAC voltage is supplied to the first capacitor, the coupling of the second capacitor is controlled by the first control signal, the coupling of the third capacitor is controlled by the second control signal, and the coupling of the fourth capacitor is controlled by the third control signal. During the second conversion subphase, the intermediate DAC voltage is supplied to the second capacitor, the coupling of the third capacitor is controlled by the first control signal, the coupling of the fourth capacitor is controlled by the second control signal, and the coupling of the first capacitor is controlled by the third control signal. During the third conversion subphase, the intermediate DAC voltage is supplied to the third capacitor, the coupling of the fourth capacitor is controlled by the first control signal, the coupling of the first capacitor is controlled by the second control signal, and the coupling of the second capacitor is controlled by the third control signal. During the fourth conversion subphase, the intermediate DAC voltage is supplied to the fourth capacitor, the coupling of the first capacitor is controlled by the first control signal, the coupling of the second capacitor is controlled by the second control signal, and the coupling of the third capacitor is controlled by the third control signal. The ADC is further configured in this way.

9. A method for operating an analog-to-digital converter (ADC) that includes a digital-to-analog converter (DAC) that includes an m-bit capacitive DAC (CDAC) and an (n-m)-bit resistive DAC (RDAC), The input voltage of the ADC is compared with the output voltage of the CDAC, Updating an n-bit digital code in response to the comparison, wherein the output of the ADC corresponds to the n-bit digital code at the end of the conversion phase. In response to the n-m least significant bits of the n-bit digital code and a reference voltage, the RDAC output provides an intermediate DAC voltage to the input of the CDAC, The CDAC provides the DAC output voltage in response to the m most significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage. Methods that include...

10. The method according to claim 9, The aforementioned conversion phase is 2 ｍ It includes several conversion subphases, The method described above is The aforementioned 2 ｍ The process further includes storing the n-bit digital code from a successive comparison register (SAR) circuit in an output register at the end of each of the individual conversion subphases. The output signal of the ADC is the 2 ｍ The two units stored in the output register at the end of each conversion subphase are ｍ A method based on the sum of n-bit digital codes.

11. The method according to claim 10, The output signal of the ADC is the 2 ｍ The two units stored in the output register at the end of each conversion subphase are ｍ A method that is the average of n-bit digital codes.

12. The method according to claim 10, The CDAC is 2 ｍ It includes several capacitors, The method described above is The aforementioned 2 ｍ In each of the conversion subphases, the 2 ｍ A method further comprising providing the intermediate DAC voltage to one of the different capacitors.

13. The method according to claim 12, The CDAC selects the m most significant bits of the n-bit digital code from the two most significant bits. ｍ - To derive one control signal, According to the CDAC, the 2 ｍ In each of the individual conversion subphases, the coupling of each of the capacitors other than the capacitor to which the intermediate DAC voltage is provided is controlled by one of the different control signals. Methods that further include the above.

14. The method according to claim 13, A method wherein the coupling of the capacitor is either for receiving the reference voltage or for being coupled to the ground terminal.

15. The method according to claim 13, A method wherein the control signal is the thermometer decoded value of the m most significant bits of the n-bit digital code.

16. The method according to claim 13, m is at least 2, the capacitor includes first to fourth capacitors, the conversion subphase includes first to fourth conversion subphases, and the control signal includes first to third control signals. The method described above is During the first conversion subphase, the intermediate DAC voltage is supplied to the first capacitor, the coupling of the second capacitor is controlled by the first control signal, the coupling of the third capacitor is controlled by the second control signal, and the coupling of the fourth capacitor is controlled by the third control signal. During the second conversion subphase, the intermediate DAC voltage is supplied to the second capacitor, the coupling of the third capacitor is controlled by the first control signal, the coupling of the fourth capacitor is controlled by the second control signal, and the coupling of the first capacitor is controlled by the third control signal. During the third conversion subphase, the intermediate DAC voltage is supplied to the third capacitor, the coupling of the fourth capacitor is controlled by the first control signal, the coupling of the first capacitor is controlled by the second control signal, and the coupling of the second capacitor is controlled by the third control signal. During the fourth conversion subphase, the intermediate DAC voltage is supplied to the fourth capacitor, the coupling of the first capacitor is controlled by the first control signal, the coupling of the second capacitor is controlled by the second control signal, and the coupling of the third capacitor is controlled by the third control signal. Methods that further include the above.

17. An analog-to-digital converter (ADC) having an input operable to receive an input voltage and an output operable to provide a digital representation of the input voltage, A comparator having a first input, a second input, and an output coupled to the input of the ADC, wherein the comparator is configured to provide a comparator output to the output in response to the input voltage and the output voltage of a digital-to-analog converter (DAC), A DAC configured to provide the DAC output voltage in response to an n-bit digital code, An m-bit capacitive DAC (CDAC) having an input and an output coupled to a second input of the comparator, configured to provide the DAC output voltage in response to the m most significant bit of the n-bit digital code, an intermediate DAC voltage, and a reference voltage, wherein m is an integer greater than 0 and less than n, and the m-bit CDAC, An (n-m) bit resistive DAC (RDAC) having an output coupled to the input of the m bit CDAC, configured to provide the intermediate DAC voltage to the m bit CDAC in response to the n-m least significant bits of the n bit digital code and the reference voltage, Includes, The output signal of the ADC is 2 ｍ An ADC based on the sum of the n-bit digital codes at the end of each of the n-bit conversion subphases.

18. ADC according to claim 17, The CDAC is 2 ｍ The capacitors and the two mentioned above ｍ In each of the conversion subphases, the 2 ｍ An ADC including rotation logic configured to provide the intermediate DAC voltage to one of several capacitors.

19. ADC according to claim 18, The CDAC selects the m most significant bits from the n-bit digital code from the successive approximation register (SAR) circuit. ｍ - Further configured to derive one control signal, The rotation logic is as follows: ｍ An ADC further configured to control the coupling of each of the capacitors other than the capacitor to which the intermediate DAC voltage is provided in each of the individual conversion subphases with one of the different control signals.

20. ADC according to claim 19, m is at least 2, the capacitor includes first to fourth capacitors, the conversion subphase includes first to fourth conversion subphases, and the control signal includes first to third control signals. The aforementioned rotation logic, During the first conversion subphase, the intermediate DAC voltage is supplied to the first capacitor, the coupling of the second capacitor is controlled by the first control signal, the coupling of the third capacitor is controlled by the second control signal, and the coupling of the fourth capacitor is controlled by the third control signal. During the second conversion subphase, the intermediate DAC voltage is supplied to the second capacitor, the coupling of the third capacitor is controlled by the first control signal, the coupling of the fourth capacitor is controlled by the second control signal, and the coupling of the first capacitor is controlled by the third control signal. During the third conversion subphase, the intermediate DAC voltage is supplied to the third capacitor, the coupling of the fourth capacitor is controlled by the first control signal, the coupling of the first capacitor is controlled by the second control signal, and the coupling of the second capacitor is controlled by the third control signal. During the fourth conversion subphase, the intermediate DAC voltage is supplied to the fourth capacitor, the coupling of the first capacitor is controlled by the first control signal, the coupling of the second capacitor is controlled by the second control signal, and the coupling of the third capacitor is controlled by the third control signal. The ADC is further configured in this way.

21. An analog-to-digital converter (ADC) having an analog input terminal and a digital output terminal, A comparator having an input and an output, A successive approximation register (SAR) circuit having an input coupled to the output of the comparator, a first output coupled to the digital output terminal, and a second output, A capacitive DAC (CDAC) having a reference input, a first input, a second input coupled to the second output of the SAR circuit, and an output coupled to the input of the comparator, A resistive DAC (RDAC) having a reference input, an input coupled to the second output of the SAR circuit, and an output coupled to the first input of the CDAC, A reference voltage generator having an output coupled to the reference input of the CDAC and the reference input of the RDAC, ADC, including.

22. The ADC according to claim 21, The aforementioned CDAC A first capacitor having a first terminal and a second terminal coupled to the input of the comparator, A second capacitor having a first terminal and a second terminal coupled to the input of the comparator, A circuit element, in the first conversion phase, In response to the first control signal, the first terminals of the first and second capacitors are coupled to the analog input terminal. In response to the second control signal, the first terminal of the first capacitor is coupled to the output of the RDAC. In response to the signal at the output of the SAR circuit, the first terminal of the second capacitor is coupled to the output of the reference voltage generator. The circuit element is configured as follows: ADC, including.

23. The ADC according to claim 22, The circuit elements of the CDAC, in the second conversion phase, In response to the second control signal, the first terminal of the second capacitor is coupled to the output of the RDAC. In response to the signal at the output of the SAR circuit, the first terminal of the first capacitor is coupled to the output of the reference voltage generator. The ADC is further configured in this way.

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