Method for feeding back channel information, electronic device and computer-readable medium

Abstract

The present disclosure provides a method for feedback of channel information, including: determining a target basis vector, the target basis vector being a basis vector conforming to a vector construction rule, determining vector row identification bits, determining an extension vector based on the target basis vector and the vector row identification bits, constructing a codebook based on the extension vector, and performing channel information feedback using the codebook. The present disclosure further provides an electronic device and a computer-readable medium.

Description

[Technical Field]

[0001] The present disclosure relates to the field of channel information feedback technology, and in particular to a method, an electronic device, and a computer-readable medium for feeding back channel information. [Background technology]

[0002] Distributed Multiple-Input Multiple-Output (Distributed MIMO) and Cell-Free Massive Multiple-Input Multiple-Output (CF-mMIMO) are gaining attention as potential key technologies in the multi-antenna direction of B5G / 6G (Beyond 5th Generation / 6th Generation). One of the notable features of these technologies is that the spatial distribution of access points (APs) in a given area is more dispersed than the centralized APs used in current New Radio (NR) (5th Generation mobile communication technology), and the number of APs is relatively large, with multiple APs simultaneously serving multiple user equipment (UE).

[0003] However, related art often fails to meet the requirement of feeding back channel information. Summary of the Invention

[0004] The present disclosure provides a method, an electronic device, and a computer-readable medium for feeding back channel information.

[0005] In a first aspect, an embodiment of the present disclosure comprises: determining target basis vectors that are basis vectors that conform to vector construction rules; determining vector row identification bits; determining an augmented vector based on the target basis vector and the vector row identification bits; constructing a codebook based on the extension vector; and performing channel information feedback using the codebook.

[0006] In some embodiments, before determining the target basis vector, the method further includes determining a basis vector set based on the vector construction rule, and the basis vector set includes at least one basis vector; Determining the target basis vectors includes selecting basis vectors from the set of basis vectors to be the target basis vectors.

[0007] In some embodiments, the vector construction rule is: It includes information on the dimension of the basis vector, information on the generation rule of the basis vector, and information on the number of basis vectors in the basis vector set.

[0008] In some embodiments, the vector row identification bits are: The vector row identification bits include at least one of a base vector row identification bit and an extension vector row identification bit.

[0009] In some embodiments, the basis vector row identification bits indicate an index of a row of the selected target basis vector; The extension vector row identification bits indicate the index of the row of the selected extension vector.

[0010] In some embodiments, determining the vector row identification bits comprises: determining the basis vector row identification bits based on bitmap signaling; Or, determining the basis vector row identification bits based on a basis vector row identification bit variable and a basis vector row identification bit mapping function;

[0011] In some embodiments, the basis vector row discrimination bit mapping function is determined based on the vector construction rule. Or, The basis vector row discrimination bit mapping function is configured by the base station.

[0012] In some embodiments, the basis vector row identification bit variable is composed of one element or a plurality of different elements, the element being an integer, and the integers of the plurality of different elements being consecutive integers or non-consecutive integers.

[0013] In some embodiments, determining the basis vector row identification bits based on the basis vector row identification bit variables and a basis vector row identification bit mapping function comprises: determining the basis vector row identification bits based on a set of basis vector row identification bit variables and a basis vector row identification bit mapping function; determining the basis vector row identification bits based on a set of basis vector row identification bit variables and a plurality of different basis vector row identification bit mapping functions; determining the basis vector row identification bits based on a plurality of sets of different basis vector row identification bit variables and a basis vector row identification bit mapping function; determining the basis vector row identification bits based on a plurality of sets of different basis vector row identification bit variables and a plurality of different basis vector row identification bit mapping functions.

[0014] In some embodiments, determining the extended vector row identification bits based on bitmap signaling. Or, The extended vector row identification bits are determined based on an extended vector row identification bit variable and an extended vector row identification bit mapping function.

[0015] In some embodiments, the extended vector row discrimination bit mapping function is determined by the vector construction rule. Or, The extended vector row discrimination bit mapping function is configured by the base station.

[0016] In some embodiments, the extended vector row identification bit variable is composed of one element or a plurality of different elements, the element being an integer, and the integers of the plurality of different elements being consecutive integers or non-consecutive integers.

[0017] In some embodiments, determining the extended vector row identification bits based on the extended vector row identification bit variable and an extended vector row identification bit mapping function comprises: determining the extended vector row identification bits based on a set of extended vector row identification bit variables and an extended vector row identification bit mapping function; determining the extended vector row identification bits based on a set of extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions; determining the extended vector row identification bits based on a plurality of sets of different extended vector row identification bit variables and an extended vector row identification bit mapping function; determining the extended vector row identification bits based on a plurality of sets of different extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions.

[0018] In some embodiments, determining an extended vector based on the target basis vector and the vector row identification bits comprises: determining an extension vector based on the target basis vector, basis vector row identification bits, and a basis vector row identification bit type, wherein the vector row identification bits include basis vector row identification bits; Or, determining an extended vector based on the target basis vector, basis vector row identification bits, basis vector row identification bit type, extended vector row identification bits, and extended vector row identification bit type, and the vector row identification bits include the basis vector row identification bits and extended vector row identification bits.

[0019] In some embodiments, determining the extension vector based on the target basis vector, the basis vector row identification bits, and the basis vector row identification bit type comprises: If the basis vector row identification bit type is a set-to-zero type, set elements of rows of the target basis vector corresponding to the basis vector row identification bits to zero according to the target basis vector and the basis vector row identification bits to obtain an extended vector; If the basis vector row identification bit type is a non-zero set type, based on the target basis vector and the basis vector row identification bits, set to zero elements of rows of the target basis vector that do not correspond to the basis vector row identification bits to obtain an extended vector.

[0020] In some embodiments, determining the extension vector based on the target basis vector, the basis vector row identification bits, the basis vector row identification bit type, the extension vector row identification bits, and the extension vector row identification bit type includes: If the basis vector row identification bit type is a set-to-zero type and the extended vector row identification bit type is a set-to-zero type, zero-setting elements of rows of the target basis vector corresponding to the basis vector row identification bits to obtain a first vector, and zero-setting elements of rows of the first vector corresponding to the extended vector row identification bits to obtain an extended vector; If the basis vector row identification bit type is a set-to-zero type and the extended vector row identification bit type is a non-set-to-zero type, zero-setting row elements of the target basis vector corresponding to the basis vector row identification bits to obtain a first vector, and zero-setting row elements of the first vector that do not correspond to the extended vector row identification bits to obtain an extended vector; If the basis vector row identification bit type is a non-zero type and the extended vector row identification bit type is a zero type, zeroing out row elements of the target basis vector that do not correspond to the basis vector row identification bits to obtain a second vector, and zeroing out row elements of the second vector that correspond to the extended vector row identification bits to obtain an extended vector; If the basis vector row identification bit type is a non-zero set type and the extended vector row identification bit type is a non-zero set type, zeroing out row elements of the target basis vector that do not correspond to the basis vector row identification bits to obtain a second vector, and zeroing out row elements of the second vector that do not correspond to the extended vector row identification bits to obtain an extended vector.

[0021] In some embodiments, the vector row identification bits can be dynamically adjusted over time.

[0022] In a second aspect, an embodiment of the present disclosure provides an electronic device including one or more memories and one or more processors, wherein the memories store a computer program to be executed by the processor, and the computer program, when executed by the processor, implements any one of the channel information feedback methods of the embodiment of the present disclosure.

[0023] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, the computer program, when executed by a processor, realizing any one of the methods for feeding back channel information in the embodiments of the present disclosure.

[0024] In the embodiment of the present disclosure, an extension vector is first determined based on the basis vector and the vector row identification bit, and then a codebook for channel information feedback is determined based on the extension vector, so that the codebook can better meet the current requirements for channel information feedback, thereby realizing better channel information feedback and further improving communication quality. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a flowchart of a method for feeding back channel information provided by an embodiment of the present disclosure. [Figure 2] FIG. 2 is a flowchart of another method for feeding back channel information provided by an embodiment of the present disclosure. [Figure 3] FIG. 3 is a block diagram of an electronic device provided by an embodiment of the present disclosure. [Figure 4] FIG. 4 is a block diagram of a computer-readable medium provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the channel information feedback method, electronic device, and computer-readable medium provided by the embodiments of the present disclosure are described in detail below in combination with the drawings.

[0027] The present disclosure will be described in more detail below with reference to the drawings, but the examples presented may be embodied in different forms and the present disclosure should not be construed as being limited to the examples described below. Rather, these examples are provided to ensure that the disclosure will be thorough and complete, and to allow those skilled in the art to fully understand the scope of the present disclosure.

[0028] The drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, constitute a part of the specification, and are used to interpret the present disclosure in conjunction with the detailed embodiments, but do not constitute limitations on the present disclosure. The above-mentioned and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the drawings.

[0029] The present disclosure can be described with reference to plan views and / or cross-sectional views with the aid of idealized schematic diagrams of the present disclosure. Therefore, the illustrations and diagrams may vary based on manufacturing techniques and / or tolerances.

[0030] Each embodiment and each feature in each embodiment of the present disclosure can be combined with each other unless there is a contradiction.

[0031] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in this disclosure, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise. As used in this disclosure, the terms "comprising," "comprising," and "consisting of" refer to the presence of said features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0032] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) shall have the same meaning as commonly understood by those skilled in the art. It will be further understood that those terms defined in common usage dictionaries shall have a meaning consistent with the meaning in the context of the relevant technical proposal and this disclosure, and shall not be construed as having an ideal or overly formal meaning unless expressly defined as such in this disclosure.

[0033] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications to the layout of components formed based on manufacturing processes. Therefore, the regions illustrated in the drawings have exemplary attributes, and the shapes of the regions shown in the drawings are intended to exemplify, but not to limit, the specific shapes of the regions of elements.

[0034] In future potential application scenarios for CF-mMIMO, such as large gymnasiums, shopping malls, airports, and automated factories, the spatial distribution of UEs will be very complex, with some areas densely populated with a large number of UEs, others sparsely populated with a small number of UEs, and still others with just the right amount of UE density and number, resulting in different service requirements depending on the spatial location.

[0035] Therefore, under the above circumstances, the channel conditions are also more complicated, and it is difficult for the related art to meet the requirements for channel information feedback under these circumstances, which will affect the communication quality.

[0036] In a first aspect, an embodiment of the present disclosure provides a method for feeding back channel information.

[0037] The method of the embodiment of the present disclosure is for a communication device (e.g., an AP, a UE, a base station, etc.) to feedback information of a corresponding communication channel to the other party. Specifically, the method first determines a feedback codebook for channel information feedback based on the current situation, and then feeds back the channel information based on the codebook.

[0038] Referring to FIG. 1, the method for feeding back channel information in an embodiment of the present disclosure includes the following steps.

[0039] S101: Determine the target basis vectors. Here, the target basis vectors are basis vectors that conform to the vector construction rules.

[0040] S102: Determine vector row identification bits. S103: Determine an extension vector based on the target basis vector and the vector row identification bits.

[0041] S104: Construct a codebook based on the extended vector. S105: Perform channel information feedback using the codebook.

[0042] In the embodiment of the present disclosure, one or more basis vectors (vectors) that meet the requirements (vector construction rules) are first determined as target basis vectors, vector row identification bits are determined, and an extended vector is obtained from the target basis vector based on the vector row identification bits (the specific method will be described later). After that, a codebook can be established based on the extended vector, and channel information feedback can be performed using the codebook.

[0043] It should be understood that the numerical order and description order of steps S101 and S102 above do not necessarily indicate the order in which they are executed; that is, it is sufficient that the target basis vectors and vector row identification bits are obtained before determining the extension vectors.

[0044] In some embodiments, the vector row identification bits can be dynamically adjusted over time. In the embodiments of the present disclosure, the vector row identification bits are determined according to the specific circumstances when the step is performed, so that the vector row identification bits may be different in different execution processes, i.e., the vector row identification bits may be dynamically adjusted over time, and the corresponding obtained extended vectors and codebooks may also be different. Therefore, the codebooks obtained in the embodiments of the present disclosure are "adaptive" to the circumstances when they are obtained.

[0045] In the embodiment of the present disclosure, an extension vector is first determined based on the basis vector and the vector row identification bit, and then a codebook for channel information feedback is determined based on the extension vector, so that the codebook can better meet the current requirements for channel information feedback, thereby realizing better channel information feedback and further improving communication quality.

[0046] Here, there are various specific methods for constructing a codebook based on vectors (extended vectors).

[0047]

number

[0048] In some embodiments, referring to FIG. 2, the method further includes the following steps before determining the target basis vectors (S101):

[0049] S100: A basis vector set is determined based on a vector construction rule. Here, the basis vector set includes at least one basis vector.

[0050] Determining the target basis vectors (S101) includes the following steps: S1001: A basis vector is selected from the basis vector set as a target basis vector.

[0051] In the embodiments of the present disclosure, a vector construction rule, i.e., a rule for selecting a target basis vector, is first set, and then a basis vector set is constructed based on the vector construction rule, which may include one basis vector or multiple different basis vectors. Therefore, when a target basis vector is subsequently determined, a basis vector can be selected from the basis vector set as the target basis vector.

[0052] In some embodiments, the vector construction rules include information on the dimensions of the basis vectors, information on the generation rules of the basis vectors, and information on the number of basis vectors in the basis vector set.

[0053] As one embodiment of the present disclosure, the above vector construction rules may include dimensional information of the basis vectors (specifying the dimensions of the basis vectors), generation rule information of the basis vectors (specifying how the basis vectors should be generated), and information on the number of basis vectors in the basis vector set (specifying how many basis vectors should be added to the basis vector set).

[0054] Here, the basis vector may specifically be an N*1 vector (N is an integer greater than 1), that is, a vector with one N rows.

[0055] Specifically, the basis vectors are Directly constructed from a single DFT (Discrete Fourier Transform) vector, After weighting the elements of each row of a single DFT vector, Obtained by calculating the Kronecker product of two DFT vectors: obtained by calculating the Kronecker product of two row-weighted DFT vectors, It can be generated by one of the following methods.

[0056] In some embodiments, the vector row identification bits are: The vector row identification bits include at least one of a base vector row identification bit and an extension vector row identification bit.

[0057] In one aspect of an embodiment of the present disclosure, the vector row identification bits may include vector row identification bits for the base vectors and may include extended vector row identification bits for the extended vectors.

[0058] In some embodiments, the basis vector row identification bits indicate the index of a row of the selected target basis vector; The extension vector row identification bits indicate the index of the row of the selected extension vector.

[0059] As an aspect of an embodiment of the present disclosure, the vector row identification bits can characterize which "index" is selected in the row of the corresponding vector.

[0060] In some embodiments, determining the vector row identification bits comprises: determining basis vector row identification bits based on the bitmap signaling; Or, Determining basis vector row identification bits based on the basis vector row identification bit variables and a basis vector row identification bit mapping function.

[0061] In some embodiments, determining the vector row identification bits comprises: determining extended vector row identification bits based on the bitmap signaling; Or, Determining the extended vector row identification bits based on the extended vector row identification bit variable and the extended vector row identification bit mapping function.

[0062] As one aspect of the embodiment of the present disclosure, it is possible to determine the basis vector row identification bits and the extended vector row identification bits by bitmap signaling.

[0063] For example, the number of bits in the bitmap may correspond to the number of rows in the basis vector, and the value that each bit can take indicates whether the corresponding row is selected or not.

[0064] For example, setting a value of a bit to 1 may indicate that the row of the basis vector corresponding to that bit has been selected, and setting a value of a bit to 0 may indicate that the row of the basis vector corresponding to that bit has been selected.

[0065] For example, suppose the basis vectors are 8*1 vectors and we want to select the second and fifth rows of the basis vector.

[0066] Then, when determining the basis vector row identification bits based on bitmap signaling, if the rule is that setting a value of a bit to 1 indicates that the row of the basis vector corresponding to that bit has been selected, then the bitmap signaling is 00010010, of which the second and fifth bits have the possible values ​​of 1, and the remaining bits have the possible value of 0. If the rule is that setting a value of a bit to 0 indicates that the row of the basis vector corresponding to that bit has been selected, then the bitmap signaling is 11101101, of which the second and fifth bits have the possible values ​​of 0, and the remaining bits have the possible value of 1.

[0067] Also, for example, suppose the basis vectors are 8*1 vectors and we want to select the 3rd, 6th and 7th rows of the basis vector.

[0068] Then, when determining the extension vector row identification bit based on bitmap signaling, if the rule is that setting a bit to a value of 1 indicates that the row of the extension vector corresponding to that bit has been selected, then the bitmap signaling is 01100100, of which the possible values ​​of bits 3, 6, and 7 are 1, and the possible values ​​of the remaining bits are 0. If the rule is that setting a bit to a value of 0 indicates that the row of the extension vector corresponding to that bit has been selected, then the bitmap signaling is 10011011, of which the possible values ​​of bits 3, 6, and 7 are 0, and the possible values ​​of the remaining bits are 1.

[0069] Alternatively, as another aspect of an embodiment of the present disclosure, it is also possible to determine the basis vector row identification bits based on a basis vector row identification bit variable and a basis vector row identification bit mapping function, or to determine the extended vector row identification bits based on an extended vector row identification bit variable and an extended vector row identification bit mapping function.

[0070] Specifically, a base / extension vector (referring to a base vector or an extension vector, the same applies below) row identification bit mapping function f(i) may be defined, where i is a base / extension vector row identification bit variable, and the execution result of f(i) indicates the base / extension vector row identification bit.

[0071] In some embodiments, the basis vector row identification bit variable is composed of one element or multiple distinct elements, where the element is an integer, and the integers of the multiple distinct elements are consecutive integers or non-consecutive integers.

[0072] In some embodiments, the extended vector row identification bit variable is composed of one element or multiple distinct elements, where the element is an integer, and the integers of the multiple distinct elements are consecutive integers or non-consecutive integers.

[0073] In one aspect of the embodiment of the present disclosure, the base / extended vector row identification bit variable may be a single integer or multiple integers, and is specifically determined based on the row desired to be selected.

[0074] If there are multiple integers, the multiple integers may be contiguous (i.e., follow a continuous mapping), or the multiple integers may be discontinuous (i.e., follow a discontinuous mapping).

[0075] For example, suppose the basis vector is an 8*1 vector and you want to select the second and fifth rows of the basis vector, you can define a basis vector row identification bit mapping function f(i)=i and a basis vector row identification bit variable i={2, 5}. Alternatively, you can define a basis vector row identification bit mapping function f(i)=i+1 and a basis vector row identification bit variable i={1, 4}.

[0076] For example, if the extended vector is an 8*1 vector and we want to select the third, fourth, fifth, and sixth rows of the extended vector, we can define the extended vector row identification bit mapping function f(i)=i and the extended vector row identification bit variable i={3, 4, 5, 6}. Alternatively, we can define the extended vector row identification bit mapping function f(i)=i+2 and the extended vector row identification bit variable i={1, 2, 3, 4}.

[0077] In some embodiments, the basis vector row discrimination bit mapping function is determined based on a vector construction rule. Or, The basis vector row discrimination bit mapping function is configured by the base station.

[0078] In some embodiments, the extended vector row discrimination bit mapping function is determined by a vector construction rule. Or, The extended basis vector row discrimination bit mapping function is configured by the base station.

[0079] As one aspect of an embodiment of the present disclosure, the basis / extension vector row identification bit mapping function may be determined in the above vector construction rules (rules for determining the basis vector set) and may be set by the base station (regardless of which side the method is performed on).

[0080] In some embodiments, determining the basis vector row identification bits based on the basis vector row identification bit variables and the basis vector row identification bit mapping function comprises: determining basis vector row distinction bits based on a set of basis vector row distinction bit variables and a basis vector row distinction bit mapping function; determining basis vector row distinction bits based on a set of basis vector row distinction bit variables and a plurality of different basis vector row distinction bit mapping functions; determining basis vector row discrimination bits based on a plurality of sets of different basis vector row discrimination bit variables and a basis vector row discrimination bit mapping function; determining the basis vector row identification bits based on a plurality of sets of different basis vector row identification bit variables and a plurality of different basis vector row identification bit mapping functions.

[0081] In some embodiments, determining the extended vector row identification bits based on the extended vector row identification bit variable and the extended vector row identification bit mapping function comprises: determining extended vector row identification bits based on a set of extended vector row identification bit variables and an extended vector row identification bit mapping function; determining extended vector row identification bits based on a set of extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions; determining extended vector row identification bits based on a plurality of sets of different extended vector row identification bit variables and an extended vector row identification bit mapping function; determining the extended vector row identification bits based on a plurality of sets of different extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions.

[0082] In one aspect of the embodiment of the present disclosure, when determining the base / extended vector row identification bits based on the base / extended vector row identification bit variables and the base / extended vector row identification bit mapping functions, the base / extended vector row identification bit variables may be one group or multiple groups, and the base / extended vector row identification bit mapping functions may be one or multiple.

[0083] Furthermore, a plurality of different combination methods are possible based on the number of base / extended vector row identification bit variables and base / extended vector row identification bit mapping functions.

[0084] For example, suppose the basis vector is a 16*1 vector and you want to select the 2nd, 3rd, 4th, 5th, 8th, 9th, 10th, and 11th rows of the basis vector, you can define basis vector row identification bit mapping functions f1(i)=i+1, f2(i)=i+7, and basis vector row identification bit variables i={1, 2, 3, 4}. Alternatively, you can define basis vector row identification bit mapping functions f1(i)=i+1, f2(j)=j+2, and basis vector row identification bit variables i={1, 2, 3, 4}, j={6, 7, 8, 9}. Alternatively, you can define basis vector row identification bit mapping function f(i)=i, and basis vector row identification bit variables i={2, 3, 4, 5, 8, 9, 10, 11}.

[0085] For example, if the extended vector is a 16*1 vector and the first, second, ninth, and tenth rows of the extended vector are to be selected, then the following extended vector row identification bit mapping functions can be defined: f1(i)=i, f2(i)=i+8, and extended vector row identification bit variable i={1, 2}. Alternatively, the following extended vector row identification bit mapping functions can be defined: f1(i)=i+1, f2(j)=j*2+2, and extended vector row identification bit variable i={0, 1, 8}, j={4}. Alternatively, the following extended vector row identification bit mapping function can be defined: f(i)=i-1, and extended vector row identification bit variable i={2, 3, 10, 11}.

[0086] In some embodiments, referring to FIG. 2, determining the extension vector based on the target basis vector and the vector row identification bits (S103) includes the following steps:

[0087] S1031: Determine an extension vector based on the target basis vector, the basis vector row identification bits, and the basis vector row identification bit type.

[0088] Here, the vector row identification bits include the basis vector row identification bits. Or, S1032: Determine an extension vector based on the target basis vector, the basis vector row identification bits, the basis vector row identification bit type, the extension vector row identification bits, and the extension vector row identification bit type.

[0089] Here, the vector row identification bits include base vector row identification bits and extended vector row identification bits.

[0090] If the vector row identification bits only have basis vector row identification bits, the target basis vector can be processed based on the basis vector row identification bits and the basis vector row identification bit type to obtain an extended vector.

[0091] When the vector row identification bits simultaneously include the basis vector row identification bits and the extended vector row identification bits, the target basis vector can be processed to obtain the extended vector according to the basis vector row identification bits and the extended vector row identification bits and their types.

[0092] In some embodiments, determining the extension vector based on the target basis vector, the basis vector row identification bits, and the basis vector row identification bit type (S1031) includes the following steps:

[0093] S10311: If the basis vector row identification bit type is a zero-set type, based on the target basis vector and the basis vector row identification bit, set the row elements of the target basis vector corresponding to the basis vector row identification bit to zero to obtain an extended vector.

[0094] S10312: If the basis vector row identification bit type is a non-zero setting type, based on the target basis vector and the basis vector row identification bit, set the row elements of the target basis vector that do not correspond to the basis vector row identification bit to zero to obtain an extended vector.

[0095] If the vector row identification bits only have basis vector row identification bits, and if the type is set to zero, the elements of the row corresponding to the basis vector row identification bits in the target basis vector are set to zero to obtain an extended vector.

[0096] For example, if the target basis vector V0 is an 8*1 vector, the basis vector row identification bit s={1,2,4}, and the basis vector row identification bit type is set to zero, then the first, second, and fourth row elements of V0 are set to zero, and the elements of other rows are kept as they are to obtain the extended vector V1, i.e., V1=P1*V0, P1=diag(0,0,1,0,1,1,1,1).

[0097] Correspondingly, if the type of the basis vector row identification bits is a non-zero set type, the elements of the rows of the target basis vector corresponding to the basis vector row identification bits are kept as they are, and the elements of other rows that do not correspond to the basis vector row identification bits are set to zero, thereby obtaining an extended vector.

[0098] For example, if the target basis vector V0 is an 8*1 vector, the basis vector row identification bit s={1,2,4}, and the basis vector row identification bit type is a non-zero set type, then the third, fifth, sixth, seventh, and eighth row elements of V0 are set to zero, and the elements of other rows are kept as they are to obtain the extended vector V1, i.e., V1=P1*V0, P1=diag(1,1,0,1,0,0,0,0).

[0099] In some embodiments, determining the extension vector based on the target basis vector, the basis vector row identification bits, the basis vector row identification bit type, the extension vector row identification bits, and the extension vector row identification bit type (S1032) includes the following steps:

[0100] S10321: If the base vector row identification bit type is a zero-set type and the extended vector row identification bit type is a zero-set type, set the row elements of the target basis vector corresponding to the base vector row identification bit to zero to obtain a first vector, and set the row elements of the first vector corresponding to the extended vector row identification bit to zero to obtain an extended vector.

[0101] S10322: If the base vector row identification bit type is a zero-set type and the extended vector row identification bit type is a non-zero-set type, set the row elements of the target basis vector corresponding to the base vector row identification bit to zero to obtain a first vector, and set the row elements of the first vector that do not correspond to the extended vector row identification bit to zero to obtain an extended vector.

[0102] S10323: If the basis vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a zero setting type, set the row elements of the target basis vector that do not correspond to the basis vector row identification bits to zero to obtain a second vector, and set the row elements of the second vector that correspond to the extended vector row identification bits to zero to obtain an extended vector.

[0103] S10324: If the base vector row identification bit type is a non-zero setting type and the extended vector row identification bit type is a non-zero setting type, set the row elements of the target basis vector that do not correspond to the base vector row identification bits to zero to obtain a second vector, and set the row elements of the second vector that do not correspond to the extended vector row identification bits to zero to obtain an extended vector.

[0104] When the vector row identification bits simultaneously include basis vector row identification bits and extended vector row identification bits, first, based on whether the type of the basis vector row identification bits is zeroed or non-zeroed, zero-set the rows of the target basis vectors corresponding to the basis vector row identification bits or other rows not corresponding to the basis vector row identification bits, and obtain a first vector (obtained after zero-setting the rows corresponding to the basis vector row identification bits) or a second vector (obtained after zero-setting the other rows not corresponding to the basis vector row identification bits), which is used as the intermediate vector.

[0105] Furthermore, based on whether the type of the extended vector row identification bit is set to zero or not, the row of the intermediate vector (first vector or second vector) that corresponds to the extended vector row identification bit or other row that does not correspond to the extended vector row identification bit can be set to zero to obtain the extended vector.

[0106] For example, if the target basis vector V0 is an 8*1 vector, the basis vector row identification bit s={1,2,4}, the basis vector row identification bit type is set to zero, and the extended vector row identification bit d={3}, the extended vector row identification bit type is set to zero. First, based on V0,s, and the basis vector row identification bit type, the first, second, and fourth row elements of V0 are set to zero and the elements of the other rows are left as they are to obtain a first vector T0, i.e., T0=P1*V0,P1=diag(0,0,1,0,1,1,1,1), and then, based on T0,d, the extended vector row identification bit type, the third row element of T0 is set to zero and the elements of the other rows are left as they are to obtain an extended vector V1, i.e., V1=P2*T0,P2=diag(1,1,0,1,1,1,1,1).

[0107] Furthermore, if the target basis vector V0 is an 8*1 vector, the basis vector row identification bit s={1,2,4}, the basis vector row identification bit type is zeroed, and the extended vector row identification bit d={1,2,3,4,5}, the extended vector row identification bit type is non-zeroed, then first, based on V0,s, and the basis vector row identification bit type, zero out the elements in the first, second, and fourth rows of V0 and keep the elements in the other rows unchanged to obtain a first vector T0, i.e., T0=P1*V0,P1=diag(0,0,1,0,1,1,1,1), and then, based on T0,d, and the extended vector row identification bit type, zero out the elements in the sixth, seventh, and eighth rows of T0 and keep the elements in the other rows unchanged to obtain an extended vector V1, i.e., V1=P2*T0,P2=diag(1,1,1,1,1,0,0,0).

[0108] Furthermore, for example, if the target basis vector V0 is a 12*1 vector, the basis vector row identification bits s={1,2,3,4,7,11,12}, the basis vector row identification bit type is non-zero-set type, and the extended vector row identification bits d={2,5,7,11}, the extended vector row identification bit type is non-zero-set type, first, based on V0, s, and the basis vector row identification bit type, zero out the 5th, 6th, 8th, 9th, and 10th row elements of V0, and keep the elements of other rows as they are to obtain a second vector Q0, i.e., Q0=P1*V0,P1=diag(1,1,1,1,0,0,1,0,0,0,1,1). Then, based on Q0, d, and the extended vector row identification bit type, we set the 2nd, 5th, 7th, and 11th row elements of Q0 to zero, and keep the elements of other rows as they are to obtain the extended vector V1, i.e., V1=P2*Q0,P2=diag(1,0,1,1,0,1,0,1,1,1,0,1).

[0109] Furthermore, for example, if the target basis vector V0 is a 16*1 vector, the basis vector row identification bits s={2,3,4,5,6,7,8,9,10,11,12,13}, the basis vector row identification bit type is non-zero, and the extended vector row identification bits d={1,2,4,8,12,13,14,15,16}, the extended vector row identification bit type is non-zero, first, based on V0, s, and the basis vector row identification bit type, zero out the elements of the first, 14th, 15th, and 16th rows of V0, and keep the elements of the other rows as they are to obtain a second vector Q0, i.e., Q0=P1*V0,P1=diag(0,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0). Then, based on Q0, d, and the extended vector row identification bit type, we set the 3rd, 5th, 6th, 7th, 9th, 10th, and 11th row elements of Q0 to zero, and keep the elements of other rows as they are to get the extended vector V1, i.e., V1=P2*Q0,P2=diag(1,1,0,1,0,0,0,1,0,0,0,1,1,1,1,1).

[0110] In a second aspect, referring to FIG. 3 , an embodiment of the present disclosure provides an electronic device including one or more memories and one or more processors, wherein the memories store a computer program to be executed by the processor, and when the computer program is executed by the processor, the electronic device realizes any one of the channel information feedback methods of the embodiment of the present disclosure.

[0111] In a third aspect, referring to FIG. 4 , an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, the computer program, when executed by a processor, realizing any one of the methods for feeding back channel information in the embodiments of the present disclosure.

[0112] In the embodiments of the present disclosure, a processor is a device capable of processing data, including, but not limited to, a central processing unit (CPU). A memory is a device capable of storing data, including, but not limited to, random access memory (RAM, more specifically, SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH). An I / O interface (read / write interface) is connected between a processor and memory to enable information exchange between the memory and the processor, including, but not limited to, a data bus.

[0113] Those skilled in the art will understand that all or some of the functional modules / units of the steps, systems, and apparatuses disclosed above may be implemented as software, firmware, hardware, or any suitable combination thereof.

[0114] In hardware embodiments, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components, for example, one physical component may have multiple functions, or one function or step may be performed by the cooperation of several physical components.

[0115] Some or all of the physical components may be implemented as software executed by a processor such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other magnetic disk memory, read-only optical disks (CD-ROM), digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic memory, and any other medium used to store desired information and accessible by a computer. Additionally, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media as known to those skilled in the art.

[0116] Although embodiments have been disclosed and specific terms have been used in this disclosure, they are used in a general and descriptive sense only and should be construed as such, and not for purposes of limitation. It will be apparent to those skilled in the art that, in some instances, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Accordingly, those skilled in the art will recognize that various changes in form and detail may be made without departing from the scope of the present disclosure, as defined by the appended claims.

Claims

1. determining a target basis vector, the target basis vector being a basis vector that conforms to a vector construction rule; determining vector row identification bits; determining an augmented vector based on the target basis vector and the vector row identification bits; constructing a codebook based on the extended vector; and performing channel information feedback using the codebook. A method for feeding back channel information.

2. and determining a basis vector set based on the vector construction rule before determining the target basis vector, the basis vector set including at least one basis vector; Determining the target basis vector includes selecting a basis vector from the set of basis vectors as the target basis vector. The method of claim 1.

3. The vector construction rule is: Includes information on the dimensions of the basis vectors, information on the generation rules of the basis vectors, and information on the number of basis vectors in the basis vector set. The method of claim 2.

4. The vector row identification bits are At least one of the base vector row identification bits and the extended vector row identification bits. The method of claim 1.

5. the basis vector row identification bits indicate an index of a row of a selected target basis vector; The extension vector row identification bits indicate the index of a row of the selected extension vector. The method according to claim 4.

6. Determining the vector row identification bits comprises: determining the basis vector row identification bits based on bitmap signaling; Or, determining said basis vector row discrimination bits based on a basis vector row discrimination bit variable and a basis vector row discrimination bit mapping function. The method according to claim 4.

7. the basis vector row discrimination bit mapping function is determined based on the vector construction rule; Or, The basis vector row discrimination bit mapping function is configured by a base station. The method according to claim 6.

8. The basis vector row identification bit variable is composed of one element or a plurality of distinct elements, the element being an integer, and the integers of the plurality of distinct elements being consecutive integers or non-consecutive integers. The method according to claim 6.

9. determining the basis vector row identification bits based on the basis vector row identification bit variables and a basis vector row identification bit mapping function, determining the basis vector row identification bits based on a set of basis vector row identification bit variables and a basis vector row identification bit mapping function; determining the basis vector row identification bits based on a set of basis vector row identification bit variables and a plurality of different basis vector row identification bit mapping functions; determining the basis vector row discrimination bits based on a plurality of sets of different basis vector row discrimination bit variables and a basis vector row discrimination bit mapping function; determining the basis vector row discrimination bits based on a plurality of sets of different basis vector row discrimination bit variables and a plurality of different basis vector row discrimination bit mapping functions. The method according to claim 6.

10. determining the extended vector row identification bits based on bitmap signaling; Or, determining the extended vector row identification bit based on an extended vector row identification bit variable and an extended vector row identification bit mapping function; The method according to claim 4.

11. the extended vector row discrimination bit mapping function is determined by the vector construction rules; Or, The extended vector row discrimination bit mapping function is configured by a base station. The method of claim 10.

12. The extended vector row identification bit variable is composed of one element or a plurality of distinct elements, the element being an integer, and the integers of the plurality of distinct elements being consecutive integers or non-consecutive integers. The method of claim 10.

13. determining the extended vector row identification bits based on the extended vector row identification bit variable and an extended vector row identification bit mapping function, determining the extended vector row identification bits based on a set of extended vector row identification bit variables and an extended vector row identification bit mapping function; determining the extended vector row identification bits based on a set of extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions; determining the extended vector row identification bits based on a plurality of sets of different extended vector row identification bit variables and an extended vector row identification bit mapping function; determining the extended vector row identification bit based on a plurality of sets of different extended vector row identification bit variables and a plurality of different extended vector row identification bit mapping functions. The method of claim 10.

14. Determining an extension vector based on the target basis vector and the vector row identification bits comprises: determining an extension vector based on the target basis vector, basis vector row identification bits, and a basis vector row identification bit type, the vector row identification bits including basis vector row identification bits; Or, determining an extension vector based on the target basis vector, basis vector row identification bits, basis vector row identification bit type, extension vector row identification bits, and extension vector row identification bit type, wherein the vector row identification bits include the basis vector row identification bits and the extension vector row identification bits. The method of claim 1.

15. determining an extension vector based on the target basis vector, basis vector row identification bits, and basis vector row identification bit type, If the basis vector row identification bit type is a set-to-zero type, set to zero elements of rows of the target basis vector corresponding to the basis vector row identification bits according to the target basis vector and the basis vector row identification bits to obtain an extended vector; if the basis vector row identification bit type is a non-zero set type, then based on the target basis vector, basis vector row identification bits, zero-setting elements of rows of the target basis vector that do not correspond to the basis vector row identification bits to obtain an extended vector. The method of claim 14.

16. determining an extension vector based on the target basis vector, basis vector row identification bits, basis vector row identification bit type, extension vector row identification bits, and extension vector row identification bit type, if the basis vector row identification bit type is a set-to-zero type and the extended vector row identification bit type is a set-to-zero type, set to zero elements of rows of the target basis vector corresponding to the basis vector row identification bits to obtain a first vector, and set to zero elements of rows of the first vector corresponding to the extended vector row identification bits to obtain an extended vector; if the basis vector row identification bit type is a set-to-zero type and the extended vector row identification bit type is a non-set-to-zero type, set to zero elements of rows of the target basis vector corresponding to the basis vector row identification bits to obtain a first vector, and set to zero elements of rows of the first vector that do not correspond to the extended vector row identification bits to obtain an extended vector; if the basis vector row identification bit type is a non-zero type and the extended vector row identification bit type is a zero type, zeroing out row elements of the target basis vector that do not correspond to the basis vector row identification bits to obtain a second vector, and zeroing out row elements of the second vector that correspond to the extended vector row identification bits to obtain an extended vector; if the basis vector row identification bit type is a non-zero type and the extended vector row identification bit type is a non-zero type, zeroing out elements of rows of the target basis vector that do not correspond to the basis vector row identification bits to obtain a second vector, and zeroing out elements of rows of the second vector that do not correspond to the extended vector row identification bits to obtain an extended vector. The method of claim 15.

17. The vector row identification bits can be dynamically adjusted over time. The method of claim 1.

18. The present invention relates to a method for feeding back channel information, comprising: one or more memories; and one or more processors, the memories storing a computer program executed by the processor; and, when the computer program is executed by the processor, implementing the method for feeding back channel information according to any one of claims 1 to 17. Electronic devices.

19. A computer program is stored, and when the computer program is executed by a processor, the method for feeding back channel information according to any one of claims 1 to 17 is realized. Computer-readable medium.

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