Circuit and method for gain control - Patents.com

Abstract

The integrated circuit (IC) includes a first input pin for receiving a first input signal, a first converter configured to convert the first input signal to a first output signal, a first gain stage configured to apply a first gain to the first output signal, and a gain update circuit configured to output a first external gain control signal to a first output pin of the IC, and subsequently output a first internal gain control signal to the first gain stage to update a first gain of the first gain stage, wherein the output of the first internal gain control signal is delayed by a first predetermined delay with respect to the output of the first external gain control signal, the first predetermined delay being to compensate for a signal chain delay between the first input pin and the first gain stage.

Description

[Technical field]

[0001] The present disclosure relates to an apparatus, system, and method for gain control. [Background technology]

[0002] Gain control circuits are widely used to vary the gain of signals from various sources. Such gain control circuits may be implemented as part of a signal chain that may include a converter, such as an analog-to-digital converter (ADC), that converts an analog input signal to a digital output signal. Such implementations may be found, for example, in a typical audio mixing desk to control the volume level of a signal received from an analog source (e.g., a microphone or other line in port).

[0003] Traditionally, gain control is implemented using analog potentiometers to continuously vary resistances in the signal chain to adjust the signal level of the output signal. Analog potentiometers cannot be easily controlled by digital means and therefore cannot be easily integrated into digital audio processing systems (such as digital mixing consoles). When digital control of gain is required, a combination of discrete resistors and switches may be implemented to adjust the resistance of the signal chain in low-resolution step changes based on digital control of the switches. Such gain control is typically combined with high-resolution gain control in digital audio processing systems, where the high-resolution gain control is used to allow fine adjustment of the gain between each low-resolution step. A challenge in such systems is the ability to synchronize the updates of the low-resolution and high-resolution gains applied to the input signal. Summary of the Invention

[0004] According to a first aspect of the present disclosure, there is provided an integrated circuit (IC) including: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal to generate a first amplified output signal; and a gain update circuit configured to output a first external gain control signal to a first output pin of the IC, and subsequently output a first internal gain control signal to the first gain stage to update a first gain of the first gain stage, wherein the output of the first internal gain control signal is delayed by a first predetermined delay with respect to the output of the first external gain control signal, the first predetermined delay being to compensate for a signal chain delay between the first input pin and the first gain stage.

[0005] The gain update circuit may be further configured to monitor the first input signal or the first output signal for a signal event that updates the first gain of the first gain stage, and time-align the output of the first internal gain control signal to coincide in time with the signal event arriving at the first gain stage.

[0006] The signal event may include a zero crossing of the first input signal or the first output signal. The gain update circuit may include a zero crossing detection circuit configured to monitor the first input signal or the first output signal for zero crossings.

[0007] The gain update circuit is configured to receive a first signal event flag at a signal event input pin of the IC and time the output of the internal gain control signal based on the time the signal event flag is received. The first signal event flag may indicate a zero crossing of the first input signal. The gain update circuit may include a level detection circuit configured to process the received first signal event flag. The level detection circuit may include a flash analog-to-digital converter (ADC).

[0008] The converter may include an analog-to-digital converter.

[0009] The IC may further include a filter circuit disposed between the first input pin and the converter, the filter circuit configured to filter a first input signal provided to the converter. The filter circuit may contribute to a signal chain delay. The filter circuit may be configured to low-pass filter the first input signal. The filter circuit may be configured to impedance match the first input signal to an input impedance of the converter. The first input signal may be an audio signal.

[0010] The IC may further include an interface for receiving the first gain setting from a host device and one or more registers for storing the first gain setting. The gain update circuit may be configured to read the first gain setting from the one or more registers and generate the first external gain control signal and / or the first internal gain control signal based on the first gain setting.

[0011] The first gain setting may include a first external gain setting and a first internal gain setting. The first internal gain setting and the first external gain setting may be stored in separate registers of the one or more registers. The first external gain setting and the internal gain setting may be handled atomically by the gain control circuit. For example, the gain control circuit may be configured to copy or read the first external gain setting and the internal gain setting if an update flag of one or more registers is set, indicating that the first external gain setting and the internal gain setting have been updated.

[0012] The IC may be configured to receive and process a first gain setting at the interface asynchronously with the output of the first external gain control signal and the first internal gain control signal.

[0013] The gain update circuit may be configured to determine whether the first gain setting is within a dynamic range of a first gain of the first gain stage, update the first internal gain control signal based on the first gain setting if the first gain setting is within the dynamic range of the first gain of the first gain stage, and update the first internal gain control signal and the first external gain control signal if the first gain setting is outside the dynamic range of the first gain of the first gain stage.

[0014] The interface may be a serial interface.

[0015] The IC may further include a second input pin for receiving a second input signal, a second converter configured to convert the second input signal to a second output signal, and a second gain stage configured to apply a second gain to the second output signal. The gain update circuit may be configured to output a second external gain control signal to a second output pin of the IC, and subsequently output a second internal gain control signal to the second gain stage to update a second gain of the second gain stage, where the output of the second internal gain control signal is delayed by a second predetermined delay with respect to the output of the second external gain control signal, the second predetermined delay being to compensate for a signal chain delay between the second input pin and the second gain stage.

[0016] The first converter may be configured to receive an indication of a time location of a transient in the first input signal and to provide, in the first output signal, a masking signal that bridges the time location of the transient to mask the transient.

[0017] The masking signal may be based on a portion of the input signal that precedes the transient.

[0018] The first converter may include an analog-to-digital converter, the first input signal is an analog input signal, and the first output signal is a digital output signal including a stream of samples of the analog input signal. The stream of samples may include a leading sample preceding a transient, a masking sample of a masking signal, and a trailing sample following the transient, the masking signal being based on the leading sample. The masking signal may include a first set of consecutive masking samples, each including a copy of one of the leading samples. The masking signal may include a first set of consecutive masking samples, the amplitude of each consecutive masking sample of the first set varying by a respective first difference relative to a previous masking sample of the first set, each of the respective first differences having the same signal. The respective first differences may decrease successively through the first set of consecutive masking samples. A rate of change of the successive first differences may be configurable. A rate of change of the successive first differences may be configurable based on a duration of the masking signal.

[0019] The amplitude of the first masked sample of the first set may be equal to the sum of the amplitude of a first one of the preceding samples immediately preceding the first masked sample and the difference between the amplitude of one of the preceding samples immediately preceding the first masked sample and the amplitude of a second one of the preceding samples immediately preceding the first one of the preceding samples.

[0020] The signal processing circuit may be configured to provide a plurality of transition samples in the processed output signal instead of the plurality of subsequent samples, where the amplitude of each successive transition sample differs from the immediately preceding transition sample by a respective second difference, and where each of the respective second differences has the same sign.

[0021] The rate of change of successive second differences may be configurable, for example based on the duration of the masking signal.

[0022] The amplitude A of each successive transition sampleT may be defined by the following formula: A T =A TP +(A VP -A TP )*F

[0023] Here, A TP is the amplitude of each transition sample immediately preceding each successive transition sample, and A VP is the amplitude of each subsequent sample that is substituted in the processed output signal at each transition sample immediately preceding each successive masking sample, and F is a factor that is successively increasing for each successive transition sample or successively decreasing for each successive transition sample.

[0024] The IC may be further configured to look ahead to a first subsequent sample of at least one of the subsequent samples, and the masking signal may be generated based on the at least one of the preceding samples and the first subsequent sample of the at least one of the subsequent samples.

[0025] Successive masking samples of the masking signal may have a ramping magnitude between the last preceding sample and the first succeeding sample to define a magnitude gradient. The amplitude gradient may be constant or may vary over time.

[0026] The IC may further include a level detection circuit configured to detect an amplitude of the first input signal, and the first converter is configured to provide the masking signal in the first output signal only if the amplitude of the input signal is less than an amplitude threshold. The level detection circuit may be configured to determine a perceived signal amplitude of the first input signal and set the amplitude threshold based on the perceived signal amplitude. The level detection circuit may be configured to determine the perceived signal amplitude by determining a root mean square moving average of the amplitude of the first input signal. The level detection circuit may be configured to determine the perceived signal amplitude by determining an exponential moving average of the magnitude of the first input signal.

[0027] According to another aspect of the present disclosure, there is provided a system including a first analog input for receiving a first analog input signal, a first analog gain stage configured to apply a first analog gain to the first analog input signal to generate a first input signal, and an IC according to any one of the preceding claims.

[0028] The first analog gain and the first gain may be adjustable in step changes, the step changes of the first analog gain being larger than the step changes of the first gain.

[0029] The first analog gain stage may include a zero-crossing detector configured to detect a zero-crossing event in the analog input signal.

[0030] The first analog gain stage may include a resistor network including a plurality of resistors and a plurality of switches.

[0031] The system may further include an external filter circuit disposed between the first analog gain stage and the IC, the external filter circuit configured to filter a first input signal provided to the IC, the filter circuit contributing to a signal chain delay. The filter circuit may be configured to low-pass filter the first input signal.

[0032] The filter circuit may be configured to impedance match the first input signal to an input impedance of the transducer.

[0033] The system may further include a synchronization input pin for receiving a plurality of synchronization signals, and a synchronization interface configured to process the plurality of synchronization signals.

[0034] Each of the multiple synchronization signals may include a zero-crossing detection flag.

[0035] According to another aspect of the present disclosure, there is provided a gain control circuit including: an input for receiving an analog input signal; a first gain stage that applies a first gain to the input signal to provide an intermediate signal, the first gain stage including an array of resistors and analog switches; an integrated circuit (IC), the IC including an analog-to-digital converter (ADC) configured to convert the intermediate signal to a digital signal, and a second gain stage configured to apply a second gain to the digital signal to provide an amplified output signal; and a synchronization module configured to generate a synchronization control signal for the first gain stage such that updates to the first gain may be synchronized with updates to the second gain to prevent artifacts in the amplified output signal.

[0036] The synchronization module may be configured to generate the synchronization control signal to prevent artifacts due to adjustments of the first gain and the second gain not coinciding in time with respect to the analog input signal.

[0037] According to another aspect of the present disclosure, there is provided an integrated circuit (IC) including an analog-to-digital converter (ADC), a gain stage, and a synchronization module configured to output a synchronization signal, the IC being for use in the gain control circuit described above.

[0038] According to another aspect of the present disclosure, there is provided an integrated circuit (IC) including: a converter configured to convert an input signal to an output signal; a gain function configured to apply a gain to the output signal to provide an amplified output signal, the gain function configured to update a level of the gain in response to receiving a first synchronization signal; and a delay circuit configured to implement a programmable time delay between receiving the first synchronization signal and updating the level of the gain.

[0039] The programmable time delay can be programmed to match the signal latency associated with the external circuitry that generates the input signal.

[0040] The IC may further include a memory for storing a user-definable delay value, the delay circuit being configured to set a programmable time delay based on the user-definable delay value.

[0041] The first synchronization signal may be generated on the IC, or alternatively may be generated external to the IC and received at an input pin of the IC.

[0042] The IC may be configured to receive a first synchronous signal and a second synchronous signal at input pins of the IC.

[0043] The converter may be an ADC, the output signal may be a digital signal, and the gain function may include a digital gain stage.

[0044] According to another aspect of the present disclosure, there is provided an integrated circuit (IC) including: a converter configured to convert an input signal to an output signal; a gain stage configured to apply a gain to the output signal to provide an amplified output signal; and a synchronization module configured to monitor the input signal or the output signal for a suitable period of time, update the gain based on the monitored input signal or the output signal, and generate an internal synchronization flag in response to determining that the suitable period exists, wherein in an internal synchronization mode, the gain stage is configured to update a level of gain in response to the internal synchronization flag, and in an external synchronization mode, the gain stage is configured to update a level of gain in response to receiving an external synchronization flag received at a synchronization input of the IC.

[0045] The IC may further include a sync select input for receiving a select signal, where selection between the internal sync mode and the external sync mode is performed based on the select signal.

[0046] The external synchronization flag may be received from a host device.

[0047] The synchronization module may be configured to detect zero crossings of the monitored input or output signals to determine the appropriate period.

[0048] According to another aspect of the disclosure, there is provided a signal processing circuit configured to receive an input signal and to output a processed output signal, the signal processing circuit being configured to receive an indication of a time location of a transient in the input signal and to provide, in the processed output signal, a masking signal that bridges the time location of the transient to mask the transient.

[0049] The masking signal may be based on a portion of the input signal that precedes the transient.

[0050] The input signal may be an analog input signal and the processed output signal may be a digital output signal comprising a stream of samples of the analog input signal. The signal processing circuitry may include an analog-to-digital converter (ADC) configured to convert the analog input signal to a digital output signal.

[0051] The stream of samples may include a leading sample preceding the transient, a masking sample of a masking signal, and a trailing sample following the transient. The masking signal may be based on the leading sample.

[0052] The masking signal may include a first set of successive masking samples, each of which includes a copy of one of the preceding samples.

[0053] The masking signal may include a first set of consecutive masking samples, the amplitude of each consecutive masking sample of the first set varying by a respective first difference relative to a previous masking sample of the first set, each of the respective first differences having the same sign. The respective first differences may decrease consecutively through the first set of consecutive masking samples. A rate of change of the consecutive first differences may be configurable. A rate of change of the consecutive first differences may be configurable based on a duration of the masking signal. The amplitude of the first masking sample of the first set may be equal to the sum of an amplitude of a first one of the preceding samples immediately preceding the first masking sample and a difference between an amplitude of one of the preceding samples immediately preceding the first masking sample and an amplitude of a second one of the preceding samples immediately preceding the first one of the preceding samples.

[0054] The signal processing circuit may be configured to provide a plurality of transition samples in the processed output signal instead of the plurality of subsequent samples. The amplitude of each successive transition sample differs by a respective second difference compared to the immediately preceding transition sample, each respective second difference having the same sign. The rate of change of the successive second differences may be configurable. The rate of change of the successive second differences may be configurable based on the duration of the masking signal.

[0055] The amplitude A of each successive transition sample T may be defined by the following formula: A T =A TP +(A VP -A TP )*F

[0056] Here, A TP is the amplitude of each transition sample immediately preceding each successive transition sample, and A VPis the amplitude of each subsequent sample that is substituted in the processed output signal at each transition sample immediately preceding each successive masking sample, and F is a factor that is successively increasing for each successive transition sample or successively decreasing for each successive transition sample.

[0057] The signal processing circuit may be configured to look ahead to a first subsequent sample of at least one of the subsequent samples. The masking signal may be generated based on at least one of the preceding samples and a first subsequent sample of at least one of the subsequent samples. The successive masking samples of the masking signal may have a ramping magnitude between the last preceding sample and the first subsequent sample to define a magnitude gradient. The amplitude gradient may be constant or may vary over time.

[0058] The signal processing circuit may include a level detection circuit configured to detect an amplitude of the input signal. The signal processing circuit may be configured to provide the masking signal in the processed output signal only if the amplitude of the input signal is below an amplitude threshold.

[0059] The level detection circuit may be configured to determine a perceived signal amplitude of the input signal and set an amplitude threshold based on the perceived signal amplitude.

[0060] The level detection circuit may be configured to determine the perceived signal amplitude by determining a root mean square moving average of the amplitude of the input signal. For example, the level detection circuit may be configured to determine the perceived signal amplitude by determining an exponential moving average of the magnitude of the input signal.

[0061] The signal processing circuit may include a zero-crossing detector circuit configured to receive the input signal. The signal processing circuit may be configured to provide a masking signal in the processed output signal after detecting zero-crossings of the input signal.

[0062] The signal processing circuitry may be configured to provide a masking signal in the processed output signal in response to an indication of a change in analog gain applied to the input signal.

[0063] The signal processing circuitry may be configured to provide a masking signal in the processed output signal in response to an indication of a change in state of an analog multiplexer or switch affecting the input signal.

[0064] The signal processing circuitry may include a digital gain stage circuit for applying a digital gain to the digital signal.

[0065] The signal processing circuitry may include a decimation filter circuit for decimating the digital signal.

[0066] The signal processing circuitry may be further configured to control a gain applied to the input signal by circuitry external to the signal processing circuitry.

[0067] The signal processing circuitry may be further configured to identify a time location of a transient within the input signal.

[0068] The signal processing circuitry may be configured to receive the input signal, simultaneously with receiving a second input signal, and to output a second processed output signal based on the received second input signal.

[0069] The masking signal may include a copy of the first portion of the second processed output signal time-aligned with the time position of the transient.

[0070] The input signal and the second input signal may be substantially correlated over time.

[0071] The input signal and the second input signal may form a stereo pair of signals.

[0072] The signal processing circuit may be further configured to receive an indication of a second time location of a second transient in the second input signal, and to provide a second masking signal in the second processed output signal at the second time location of the second transient to mask the second transient, where the second transient occurs after the first transient.

[0073] According to another aspect of the present disclosure, there is provided an integrated circuit (IC) including: a zero-crossing detector circuit configured to detect zero-crossing events of an analog input signal and output a control signal to an analog gain circuit; an analog-to-digital converter (ADC) that converts the amplified analog input signal amplified by the analog gain circuit to a digital output signal; a digital gain circuit configured to apply gain to the digital output signal; and a masking circuit configured to provide a masking signal in the digital output signal that is time-aligned with transients of the input signal.

[0074] According to another aspect of the present disclosure, there is provided an electronic device including an IC as described above, or a system as described above, or a gain control circuit as described above.

[0075] The electronic device may include a laptop, notebook, netbook or tablet computer, a gaming device, a game console, a controller for a game console, a virtual reality (VR) or augmented reality (AR) device, a mobile phone, a portable audio player, a portable device, an accessory device for a laptop, notebook, netbook or tablet computer, a gaming device, a game console, a VR or AR device, a mobile phone, a portable audio player, or other portable device, a mixing console, an audio mixing device, an audio recording device, a paging station, an audio input device for use with a computer, a musical instrument, an audio effects processor, an audio direction device, an audio capture device, an audio broadcasting device, a sound reinforcement device, a wireless electric musical instrument interface, a wireless microphone, a microphone with digital output, an ultrasonic sensing device, an ultrasonic recording device, or a sonar device.

[0076] Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to mean the inclusion of a stated element, integer or step, or group of elements, integers or steps, and not the exclusion of any other element, integer or step, or group of elements, integers or steps.

[0077] Embodiments of the present disclosure will now be described, by way of non-limiting examples, with reference to the drawings, in which: [Brief description of the drawings]

[0078] [Figure 1] FIG. 1 is a schematic diagram of a prior art signal chain. [Diagram 2] FIG. 2 is a schematic diagram of a signal chain according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a schematic diagram of a gain control system according to an embodiment of the present disclosure. [Figure 4] 4 is a graphical representation of a gain control scheme that may be implemented by the gain control system shown in FIG. 3. [Diagram 5] 4 is a flowchart of a process that may be performed by the gain control system of FIG. 3. [Figure 6] FIG. 4 is a timing diagram of various signals passing through the gain control system shown in FIG. [Figure 7A] FIG. 2 is a graphical representation of an example high resolution gain control scheme. [Figure 7B] FIG. 2 is a schematic diagram of a level detection circuit for processing a zero-crossing detection signal. [Figure 7C] FIG. 7C is a timing diagram of the level detection circuit shown in FIG. 7B. [Figure 7D] FIG. 2 is a schematic diagram of a level detection circuit for processing a zero-crossing detection signal. [Figure 7E] FIG. 1 is a schematic diagram of a flash analog-to-digital converter (ADC). [Figure 8] FIG. 2 is a schematic diagram of a gain control scheme that may be implemented by the gain control system. [Figure 9] 9 is a flowchart of a process that may be performed by the gain control system of FIG. 8. [Figure 10] FIG. 2 is a graph of a transient signal. [Figure 11] FIG. 11 is a graphical diagram of an exemplary digital representation of the transient signal shown in FIG. [Figure 12] FIG. 2 is a graphical representation of a digital signal including a transient. [Figure 13] FIG. 2 is a graphical representation of a digital signal including a transient. [Figure 14] 1 is a graphical illustration of an exemplary masked digital signal, in which transients in the signal are masked by a masking signal. [Figure 15] 1 is a graphical illustration of an exemplary masked digital signal, in which transients in the signal are masked by a masking signal. [Figure 16]1 is a graphical illustration of an exemplary masked digital signal, in which transients in the signal are masked by a masking signal. [Figure 17] 1 is a graphical illustration of an exemplary masked digital signal, in which transients in the signal are masked by a masking signal. [Figure 18] 1 is a graphical illustration of an exemplary masked digital signal, in which transients in the signal are masked by a masking signal. [Figure 19] FIG. 2 is a schematic diagram of a gain control scheme that may be implemented by the gain control system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] 1 is a schematic diagram of a conventional signal chain 100 for gain control of an analog input signal IN, in this example a differential input signal. The signal chain 100 includes a low-resolution switched analog gain stage 102, a filter module 104, an analog-to-digital converter (ADC) 106, and an audio processing system 108 that includes a high-resolution digital gain stage 110 and an audio signal processing module 112.

[0080] The input signal IN is provided to an analog gain stage 102 configured to apply a gain G to the input signal IN. The analog gain stage 102 may include a number of resistors and a number of switches configured to selectively adjust the gain of an amplifier in the signal chain. For example, the number of switches may be configured to switch one or more of the number of resistors into the signal chain to adjust the resistance in the signal chain between the input and the output of the analog gain stage 102. Additionally or alternatively, the number of switches may be configured to switch a resistor in or out of a feedback loop associated with an amplifier of the gain stage 102, thereby changing the gain of that amplifier. The analog gain stage 102 may be configured to adjust the gain applied to the signal chain in steps in this manner. Such steps are relatively larger than any step of resolution of the digital gain stage 110.

[0081] The signal G IN output from the analog gain stage 102 may then be provided to a filter module 104, which may include one or more analog filters for filtering the input signal IN and output a filtered input signal FIN to the ADC 106. The filter module 104 may be configured to perform one or more additional functions on the signal G IN output from the analog gain stage 102. The filter module 104 may be configured to anti-alias, i.e., remove signal content higher than the Nyquist frequency (half the sampling frequency). The filter module 104 may also be configured to impedance match the input signal to the input impedance of the ADC 106 (typically very low, hundreds to thousands of ohms). The ADC 106 then converts the filtered input signal FIN to the digital domain and outputs a digital representation D IN , which may be provided to the audio processing system 108 (e.g., a DSP). As mentioned above, the audio signal processing module 112 includes a high-resolution digital gain stage configured to implement a higher resolution (i.e., fine-tuning) gain.

[0082] In the above embodiment, two separate gain stages 102, 110 are implemented.

[0083] The analog gain stage 102 is used to provide a wide range of gain adjustment (e.g., between -12 dB and +60 dB in 3 dB increments). The analog gain stage 102 is provided to optimize the dynamic range of the signal path relative to the level of the input signal IN. The level of the input signal IN may vary over a wide range depending on the source of the input signal IN (e.g., an audio source). For example, if the signal chain is implemented as part of a mixing console, the input signal IN may be generated by devices with different maximum signal levels. For example, a dynamic microphone may generate a signal with a much lower maximum signal level than, for example, a direct injection audio interface. As much gain as possible may be applied in the analog gain stage 102 to minimize noise throughout the signal chain. In this way, the analog gain stage 102 may be designed to provide a large positive range compared to the digital gain stage 110.

[0084] A digital gain stage 110 implemented downstream of the ADC 106 allows fine adjustment of the gain level (e.g., between −3 dB and +3 dB attenuation in 0.5 dB or 1 dB increments). The gain level adjustment may be provided to the user through the use of an encoder (both not shown) coupled to a controller. The controller may convert the encoder output into a gain level to be applied by each of the analog gain stage 102 and the digital gain stage 110.

[0085] A challenge in systems such as that shown in FIG. 1 is the ability to synchronize the gain updates applied by the analog gain stage 102 and the digital gain stage 110. Such systems tend to rely on separate control units to control the timing of the gain updates, for example, by using a zero-crossing detection algorithm or the like. A challenge is illustrated in precisely controlling the timing between the transitions in gain applied by each of the analog gain stage 102 and the digital gain stage 110. Misaligned gain updates across the analog gain stage 102 and the digital gain stage 110 in the signal chain 100 can result in signal transients that can lead to audible artifacts in the digital audio signal output to the audio signal processing module 112.

[0086] Embodiments of the present disclosure aim to address or at least ameliorate one or more of the above problems by providing a converter integrated circuit (IC) with an associated gain control circuit that eliminates the need for a separate timing controller to control the gain updates. Converter ICs according to embodiments of the present disclosure provide hybrid gain control that uses a single circuit to control the gain applied by multiple gain stages in a signal chain.

[0087] 2 is a schematic diagram of an example signal chain 200 in accordance with an embodiment of the present disclosure. The signal chain 200 includes an analog gain stage 202, an optional filter module 204, an optional buffer 206, and a combined converter and gain integrated circuit (IC) 208.

[0088] An input signal IN, which in this non-limiting example is a differential input signal, is provided to the analog gain stage 202. The analog gain stage 202 is configured to apply a gain G to the input signal IN. Similar to the gain stage 102 shown in FIG. 1, the analog gain stage 202 may include a number of resistors and a number of switches configured to selectively adjust the gain of an amplifier in the signal chain. For example, the number of switches may be configured to switch one or more of the number of resistors into the signal chain to adjust the resistance in the signal chain between the input and output of the analog gain stage 102. Additionally or alternatively, the number of switches may be configured to switch a resistor in or out of a feedback loop associated with an amplifier of the gain stage 102, thereby changing the gain of that amplifier. The analog gain stage 102 may be configured to adjust the gain applied to the signal chain in steps in this manner. Such steps are relatively larger than any of the steps of resolution of the digital gain stage 110. For example, the analog gain stage 202 may be adjustable in 3 dB increments, while the digital gain stage may be adjustable in 0.5 dB or 1 dB increments. For example, the analog gain stage 202 may be adjustable from -12 dB to +60 dB in 3 dB increments, and the digital gain stage may be adjustable from -3 dB to +3 dB in 0.5 dB or 1 dB increments.

[0089] The signal G IN output from the analog gain stage 102 may then be provided to a filter module 204, which may include one or more analog filters for filtering the input signal IN and output a filtered input signal FIN. Similar to the filter module 104, the filter module 204 may be configured to perform one or more additional functions on the signal G IN output from the analog gain stage 102.

[0090] Optionally, the filtered input signal FIN may be buffered by a buffer 206 (if provided) before being provided to the combined converter and gain IC 208. In some embodiments, the filter module 204 and the buffer 206 may be implemented in a single circuit. For example, the filter module 104 may be implemented as an amplifier stage with one or more capacitors in its feedback network, such capacitors being selected to produce the desired filter characteristics while simultaneously impedance matching.

[0091] As described in more detail below, the combined converter and gain IC 208 is configured to both convert the received, filtered input signal FIN to the digital domain and to provide high resolution gain adjustment of the filtered input signal FIN. The combined converter and gain IC 208 includes a converter, in this case an ADC 210 (although alternative converters are envisioned), and a gain stage 212. The gain stage 212 may be configured to apply a programmable gain to the output of the ADC 210.

[0092] The combined converter and gain IC 208 may be configured to synchronize gain updates applied by the integrated gain stage 212 with gain updates applied by the analog gain stage 202. Such synchronization may include compensation for signal path latency between the analog gain stage 202 and the combined converter and gain IC 208. To assist in synchronizing gain updates between the analog gain stage 202 and the gain stage 212, the converter and gain IC may include control circuitry configured to (digitally) control the analog gain stage 202.

[0093] The combined ADC and gain IC 208 may effectively replace the digital gain stage 110 of the audio processing system 108 shown in FIG. 1, thereby simplifying the synchronization operations performed in the signal chain 200.

[0094] Various implementations of the above signal chain 200 will now be described with reference to Figures 3-6. The embodiments described below are described with respect to a two-channel converter. However, it should be understood that the embodiments of the present disclosure are not limited to two channels and may be extended to any number of channels without departing from the scope of the present disclosure. The embodiments described herein also include optional circuitry for internal zero-crossing detection and gain ramping, which will be described in more detail below.

[0095] In the embodiments described herein, the various ICs communicate using a serial interface, such as the well-known Serial Peripheral Interface (SPI), it should be understood that any conceivable interface may be used for communication. In embodiments in which more than one SPI is used, such interfaces may be daisy-chained, as described in more detail below.

[0096] 3 is a schematic diagram of a two-channel hybrid gain control system 300 according to an embodiment of the present disclosure. The control system 300 includes an analog gain circuit 302 and a converter integrated circuit (IC) 304.

[0097] The analog gain circuit 302 includes, for a first input channel, a first analog gain stage 306-1, a first gain controller 308-1, and an optional first filter module 310-1. For a second input channel, the analog gain circuit 302 includes a second analog gain stage 306-2, a second gain controller 308-2, and an optional second filter module 310-2.

[0098] In the first channel, a first gain stage 306-1 is configured to receive a first input signal IN1 and apply gain in a manner similar to that described above with reference to the analog gain stage 202 of Figure 2. The gain applied by the first gain stage 306-1 may be controlled by a first gain controller 308-1, as described in more detail below.

[0099] The first analog input signal GIN1 output from the first gain stage may then be provided to a first filter module 310-1. The first filter module 310-1 may be configured to filter the analog input signal GIN1 and / or drive an input signal A1 in a manner known in the art. The amplified and optionally filtered analog input signal GIN1 is then provided to the converter IC 304 as a first analog signal A1.

[0100] In the second channel, the second gain stage 306-2 is configured to receive a second input signal IN2 and apply gain in a manner similar to that described above with reference to the analog gain stage 202 of Figure 2. The gain applied by the second gain stage 306-2 may be controlled by a second gain controller 308-1, as described in more detail below.

[0101] The second analog input signal GIN2 output from the second gain stage 306-2 may then be provided to a second filter module 310-2. The second filter module 310-2 may be configured to filter the analog input signal GIN2 and / or drive a second input signal A2 in a manner known in the art. The amplified and optionally filtered analog input signal GIN2 is then provided as a second analog signal A2 to the converter IC 304.

[0102] 3, it should be understood that in other embodiments, the first gain controller 308-1 and the second gain controller 308-2 may be implemented as a single gain controller. It should also be understood that in other embodiments, the first gain controller 308-1 and the second gain controller 308-2 may be implemented on the converter IC 304. For example, a single gain controller may be provided to control both the analog gain of the analog gain circuit 302 and the digital gain of the converter IC 304.

[0103] The converter IC 304 includes a first signal chain 312 for a first channel, a second signal chain 314 for a second channel, and a control circuit 316 for monitoring the first and second signal chains and for controlling the digital gain of the first and second signal chains 312 and 314, as described in further detail below. The converter IC 304 may further include an interface circuit 317 for interfacing with a host device 319 (or in some embodiments, more than one host device).

[0104] The first signal chain 312 includes a first ADC 318-1, a first decimator 320-1, and a second digital gain stage 322-1. The first ADC 318-1 is configured to receive a first analog signal A1 from the analog gain circuit 302 and convert it into a first digital signal D1. The first digital signal D1 is decimated by the first decimator 320-1 before being provided to the digital gain stage 322-1. The digital gain stage 322-1 is configured to apply a digital gain based on a digital gain control signal DGC1 received from the control circuit 316.

[0105] The second signal chain 314 includes a second ADC 318-2, a second decimator 320-2, and a second digital gain stage 322-2. The second ADC 318-2 is configured to receive a second analog signal A2 from the analog gain circuit 302 and convert it to a second digital signal D2. The second digital signal D2 is decimated by the second decimator 320-2 before being provided to the second digital gain stage 322-2. The second digital gain stage 322-2 is configured to apply a digital gain based on a digital gain control signal DGC2 received from the control circuit 316.

[0106] The control circuit 316 includes a zero crossing detector (ZCD) 324, a ZCD multiplexer (MUX) 326, a gain control finite state machine (FSM) 328, and a master analog gain controller 330. The control circuit 316 may further include a first set of registers 332 for the gain control FSM 328 and a second set of registers 334 for the master analog gain controller 330. Separate first and second sets of registers 332, 334 may be provided in implementations where the size of each register 332, 334 is constrained (e.g., due to IC design constraints). In other embodiments, where no such constraints exist, the first and second sets of registers 332, 334 may be replaced with a single register or a single set of registers. In such implementations, the single register or single set of registers may be large enough to accommodate a single instruction associated with both the digital gain stages 322-1, 322-2 and the analog gain stages 306-1, 306-2.

[0107] The ZCD 324 is configured to detect zero crossings of the first zero-centered analog signal A1 and the second zero-centered analog signal A2. The ZCD MUX is configured to selectively couple one of the first analog signal A1 and the second analog signal A2 to the ZCD 324 in response to a MUX select signal SEL received from the gain control FSM 328. The ZCD 324 is configured to output a zero crossing signal to the gain control FSM 328 indicative of a zero crossing event in the signal received at the ZCD 324 (i.e., the first analog signal A1 or the second analog signal A2). In the illustrated embodiment, a single ZCD 324 is provided, but in other embodiments a ZCD may be provided for each channel and the output of each ZCD may be provided to a multiplexer to select between the outputs.

[0108] As described above, the gain control FSM 328 is configured to output a MUX select signal SEL to the MUX 326 to select between coupling the first analog signal A1 and the second analog signal A2 to the ZCD 324. Additionally, the gain control FSM 328 is configured to output a first digital gain control signal DGC1 and a second digital gain control signal DGC2 to the first digital gain stage 322-1 and the second digital gain stage 322-2, and to output a master analog gain control signal MAGC to the master analog gain controller 330.

[0109] The first and second gain control registers 332, 334 are configured to store gain parameters for the first and second analog gain stages 306-1, 306-2 and the first and second digital gain stages 322-1, 322-2, respectively. Such gain parameters may be written to the first and second registers 332, 334 in response to control signals received from the host device 319 via the interface circuit 317.

[0110] In operation, the FSM 328 is configured to monitor the ZCD signal received from the ZCD 324. Upon detecting a zero-crossing event, the FSM 328 may output a control signal to the master analog gain controller 330 to update the gain of the first analog gain stage 306-1 and the second analog gain stage 306-2. In response, the master analog gain controller 330 may output an update signal to the first gain controller 308-1 and the second gain controller 308-2 in addition to the gain parameters read by the master analog gain controller 330 from the second set of registers 334. Additionally, the FSM 328 may update the gain of the digital gain stages 322-1, 322-2 based on the gain parameters in the first set of registers 332. The control circuit 316 is configured to synchronize any updates to the gain in the analog gain stages 306-1, 306-2 on the one hand and the digital gain stages 322-1, 322-2 on the other hand within the signal chain.

[0111] The master analog gain controller 330 may communicate with the first gain controller 308-1 and the second gain controller 308-2 via a serial peripheral interface (SPI). In some embodiments, the serial interfaces of the first gain controller 308-1 and the second gain controller 308-2 may be daisy-chained such that data lines from the SPI of the master analog gain controller 330 pass through the SPIs of the first gain controller 308-1 and the second gain controller 308-2, respectively. In such implementations, bits of data may be clocked into the first gain controller 308-1 and the second gain controller 308-2 using a common clock signal, with the daisy-chain forming a shift register. A common select line may be provided to the first gain controller 308-1 and the second gain controller 308-2 controlled by the master analog gain controller 330. Assertion or deassertion of the common select line may trigger the reading of new gain values ​​provided on the data lines and shifted to the first gain controller 308-1 and the second gain controller 308-2. Thus, by controlling the select line, the master analog gain controller 330 may control the exact time at which gain updates are asserted by each of the first gain controller 308-1 and the second gain controller 308-2.

[0112] The control circuit 316 may be configured to account for any latency associated with the signal chain between the analog gain stages 306-1, 306-2 and the digital gain stages 322-1, 322-2.

[0113] As mentioned above, the external analog gain stages 306-1, 306-2 can be configured to apply step changes in gain. Such steps are relatively wide compared to those provided by the digital gain stages 322-1, 322-2. This allows a host controller in communication with the converter IC 304 (e.g., via the interface circuit 317) to set any gain value with the resolution of the internal digital gain stages 322-1, 322-2. The external analog gain stages 306-1, 306-2 may then be switched by the control circuit 316 to an appropriate gain setting for the required dynamic range, and the internal digital gain stages 322-1, 322-2 are adapted to set a fine gain.

[0114] In some embodiments, a user may set the gain of the first and second channels by rotating an encoder (not shown). In such embodiments, it should be understood that the gain change is therefore continuous. It is desirable to smoothly increase or decrease the gain while avoiding any audible artifacts (e.g., zipper noise, audible gain jumps, etc.).

[0115] Referring to the first channel of the system 300, FIG. 4 is a graphical illustration of the relative transitions of the commanded gain (e.g., the gain received from the host device 319 via the interface circuit 317), the external switching gain (i.e., the gain switched at the first analog gain stage 306-1), the digital fine gain (i.e., the gain applied by the first digital gain stage 322-1), and the overall system gain for the first channel. In this example, the external switching gain is switched in 6 dB increments, while in other examples, the external switching gain may be switched in smaller or larger increments. It can be seen that the transitions of the first analog gain stage 306-1 and the first digital gain stage 322-1 at times t1, t2, and t3 should preferably be aligned so that the system gains are substantially matched and system gain transients are avoided. Any misalignment of the transitions may lead to discontinuities, artifacts, and / or transients in the system gain and, therefore, in the output signal DO1.

[0116] Figure 5 illustrates an exemplary process 500 implemented by the system 300 of Figure 3, optionally in coordination with a host device 319 in communication with the system 300. This process 500 for updating gain settings will be described with reference to the first channel of the system 300 shown in Figure 3. However, it should be understood that it is equally applicable to the second channel.

[0117] In step 502 , a new gain setting is received, for example via an encoder in the host device 319 .

[0118] In step 504, it is determined whether the new gain setting is within the dynamic range of the digital gain stage 322-1 given the current setting of the analog gain stage 306-1.

[0119] If the new gain setting is within range, the updated gain value for the first digital gain stage 322-1 is written to the first register in step 506. The control circuit 316 (or the host device 319) activates the updated gain of the digital gain stage 322-1 and the process 500 is complete.

[0120] On the other hand, if it is determined that the new gain setting is not within the range of the current gain setting of the analog gain stage 306-1, then in step 510 the control circuit 316 (or host device 319) calculates new gain values ​​for the first analog gain stage 306-1 and the first digital gain stage 322-1.

[0121] It should be understood that steps 502-510 may be performed in the host device 319, in the IC 304 (eg, by the control circuitry 316), or in a combination of the host device 319 and the IC 304.

[0122] In step 512, the control circuit 316 or the host device 319 writes or updates the first register 332 and the second register 334 via the interface 317 with the new gain parameters to be subsequently applied in the first analog gain stage 306-1 and the first digital gain stage 322-1. The registers 332, 334 may contain the entire control bit pattern, for example the complete SPI register bit pattern for the first analog gain controller 308-1 connected via SPI. The format depends on the register format of the analog gain controller 308-1. The new analog and digital gain control settings are written to the respective first register 332 and second register 334, but neither is activated at this point.

[0123] In step 514 , the ZCD MUX select signal SEL is sent to the ZCD MUX 326 to couple each of the first analog signal A 1 and the second analog signal A 2 (in this case, the first analog signal A 1 ) to the ZCD 324 .

[0124] Optionally, if gain ramping is used, the gain step, direction, step size and / or ramp rate may be set in step 516 .

[0125] In step 518, an updated gain may be triggered, in response to which an analog gain setting may be sent to the first analog gain controller 308-1. For example, the FSM 328 causes the master analog gain controller 330 to write out the entire bit sequence contained in the second register of the first analog gain controller 308-1. At the end of the bit pattern, the signal SPI_CSb remains asserted (negative), ensuring that the gain control module 308-1 has not yet updated the gain of the first analog gain stage 306-1.

[0126] In step 520, the FSM 328 may monitor for a zero-crossing event based on the output from the ZCD 324. In addition, timeout monitoring may be used. For example, the ZCD may output a timeout signal associated with an extended period during which no zero crossing is detected. Such a timeout signal may be used as a trigger to control switching of subsequent steps of the process 500.

[0127] In step 522, when a zero-crossing event is detected in the first input signal A1, the FSM 328 controls the master analog gain controller 330 to deassert the signal SPI_CSb, thereby causing the first analog gain controller 308-1 to switch the first analog gain stage 306-1 to a new analog gain setting.

[0128] In step 524, the FSM 328 may wait a predetermined period of time. Such a delay may be pre-configured to compensate for the latency of the filters and / or ADCs associated with the first signal chain 312.

[0129] The FSM 328 then updates the digital gain value of the first digital gain stage 322-1 in step 526. If a gain step and ramp is used, this step may include first performing a gain step according to configured parameters (described above), followed by a gain ramp to the target gain value of the first digital gain stage 322-1.

[0130] 6 is an example timing diagram illustrating how timing errors in the switching of the first analog stage 306-1 and the gain stage 322-1 can lead to discontinuities in the converted output signal DO1. 1. An exemplary input signal IN, such as a first input signal IN received at a first analog gain stage 306-1. 2. The input signal IN is the same as that received at the zero-crossing detector ZCD. 3. The digital signal at the input of the first digital gain stage 322-1, delayed by the latency associated with the conversion in the first ADC 318-1 and the first decimator 320-1. 4. The digital signal at the output of the first digital gain stage 322-1, with discontinuities smoothed out by ramping the gain change of stage 322-1, first digital gain.

[0131] 6 illustrates how the latency compensation delay (i.e., the predetermined delay between activation of the gain change of the first analog gain stage 306-1 and activation of the gain change of the first digital gain stage 322-1) can be adjusted to account for the combined latency associated with the ADC 318-1 and the decimator 320-1, in addition to the latency associated with the first filter module 310-1 external to the converter IC 304. In doing so, the control circuit 316 can control the gain change of the digital gain stage 322-1 to match signal discontinuities caused by any zero-crossing errors associated with the external gain change. Furthermore, if the fine gain change is implemented as a step and ramp operation or other similar operation, the signal received at the first digital gain stage 322-1 can be compensated to remove any such discontinuities.

[0132] If the gain steps and ramps are implemented such that they are sufficient to compensate for signal discontinuities, gain changes that do not detect zero crossings may prove to be inaudible, in which case zero crossing detection may not be necessary.

[0133] In some cases, the signal discontinuity may not be complete, for example, due to phase distortion in the signal path (due to external filter 310-1, ADC 318-1, and decimator 320-1). In such cases, some residual audible signal artifact(s) may be present. If gain steps and ramps are used, it is preferable that the step size, step direction, and ramp rate are all set (e.g., by host device 319) before a gain update is triggered (e.g., in step 522 of process 500 of FIG. 5).

[0134] The adjustment of the latency compensation delay may be programmed by the user (eg, using a simple timer).

[0135] The latency associated with the first ADC 318-1 and the decimator 320-1 may be deterministic and dependent on a selected sample rate parameter of the decimator 320-1. Thus, data may be provided that indicates latency compensation values ​​to set for different combinations of sample rates and filter types used in the decimator 320-1.

[0136] The user may also adjust the delay to add any latency associated with the (external) filter module 310-1 to ensure that fine gain changes (or steps and ramps) are synchronized with discontinuities caused by the external analog gain stages.

[0137] As shown in Figure 6, the digital gain stage 322-1 may perform a step and ramp operation to reach a new commanded value for the fine gain. This step and ramp operation may have several user configurable parameters, as shown in Figure 7A. Such parameters may include: Gain step size - can be set to be the same as the gain step of the external analog gain stage 306-1. Gain step direction - may be set by the control circuit 316 depending on whether the external gain stage 306-1 is increasing or decreasing gain. If the analog gain stage 306-1 is increasing gain, the gain step may be set to negative. If the analog gain stage 306-1 is decreasing gain, the gain step is set to positive. Ramp Rate. - Fine gain goals.

[0138] As mentioned above, in the embodiment shown in FIG. 3, a first set of registers 332 and a second set of registers 334 are provided. In such an implementation, a host device 319 coupled via an interface 317 may be configured to update each of the first register 332 and the second register 334 to assert a new overall gain value on the system 300. It should be appreciated that the time it takes to complete a gain update may vary, for example up to 20 ms, due in part to the fact that each gain change is zero-cross aligned. Thus, it may happen that new gain values ​​are written to the registers 332, 334 by the host in the middle of a gain update by the gain control FSM 328 and the master analog gain controller 330. When such an update occurs, there is a risk of an error in the gain applied by the analog gain stages 306-1, 306-2 and / or the digital gain stages 322-1, 322-2. For example, the gain control FSM 328 may update the digital gain based on the most recent command received from the host device 319, while the master analog gain controller 330 may control the update of the analog gain based on the previous command received from the host device 319 (or vice versa).

[0139] Various solutions may be implemented to avoid errors due to register writes that are not synchronized with the gain stage updates. In some embodiments, the host device 319 may be configured to synchronize its writes to the registers 332, 334 with the gain updates by the gain control FSM 328 and the first and second gain controllers 308-1, 308-2 to avoid skewed updates. However, such synchronization may be process intensive on the host device 319. Additionally or alternatively, the host device 319 may not have the functionality required to perform such synchronization.

[0140] Accordingly, embodiments of the present disclosure may treat register entries in the first set of registers 332 and the second set of registers 334 (including the gain control FSM 328 and the master gain controller 330) atomically, i.e., as a single instruction. For example, the gain control FSM 328 may be configured to ensure that entries in the first set of registers 332 and the second set of registers 334 for an entire gain update are treated as a single unit.

[0141] To allow the entries in the first set of registers 332 and the second set of registers 334 to be treated atomically, the host device 319 may be configured to toggle one or more update flags to indicate that the entries in the first set of registers 332 and the second set of registers 334 have been updated. For example, a gain update bit may be toggled (e.g., written high or low) in the registers of the first set of registers 332 and the second set of registers 334 for each channel CH1, CH2.

[0142] The gain control FSM 328 or a separate gain update scheduler (not shown) may then continuously cycle through the register entries in the first set of registers 332 and the second set of registers 334 to check the state of the gain update flag for each channel. If the gain update bit is high (or low) for a particular channel, the gain control FSM 328 may proceed to read the new gain value written to the registers 332, 334, optionally store the value in logic, and then perform a gain update for that channel based on the new gain value. Once the new gain value is read from the registers 332, 334, the gain control FSM 238 may be configured to clear / reset the update bit to indicate that the new gain value has been performed by the control circuit 316.

[0143] It may be the case that the host device 319 is attempting to write a new gain value to the registers 332, 334 at the same time that the gain control FSM 328 (or gain update scheduler) is reading the update bits for a particular channel. To avoid simultaneous reading and writing of the same set of the first registers 332 and the second registers 334, the gain control FSM 328 may be stalled for the period during which the host device 319 is writing to a register that the gain control FSM 328 is attempting to check. The control circuitry 316 may determine the write status of the host device 319 by monitoring one or more signals at the interface 317.

[0144] By treating the first register 332 and the second register 334 atomically, the host device 319 is free to asynchronously update the gain values ​​in the registers 332, 334 without risking introducing errors due to asynchronous reading of the registers 332, 334 by the master analog gain controller 330 on the one hand and the gain control FSM 328 on the other hand. An implementation of this process is described in further detail below.

[0145] 3, zero-crossing detection is implemented on the converter IC 304, but in other embodiments, zero-crossing detection may be implemented external to the converter IC 304. For example, instead of providing a ZCD 324, one or more separate zero-crossing detectors may be provided external to the converter IC 304. In that case, the converter IC 304 may include one or more inputs for receiving one or more control signals from the one or more separate zero-crossing detectors.

[0146] In practice, it should be understood that some off-the-shelf gain switching devices incorporate zero-crossing detection. Such zero-crossing detection may be used internally to time the gain switch itself. Such implementations may reduce or ameliorate latency errors associated with zero-crossing detection (discussed above). Some such devices, for example, the THAT5173 digitally programmable gain controller IC offered by THAT Corporation, include a zero-crossing detection output, which signals the timing to the gain switch. An embodiment of the present disclosure may utilize such a device for timing digital gain switching within a converter IC such as those described herein.

[0147] In some embodiments, multiple zero-crossing detection signals received from one or more separate zero-crossing detectors may be provided to the converter IC 304 via a single pin.

[0148] 7B illustrates an example interface 702 between a first external zero-crossing detector 704 and a second external zero-crossing detector 706 and the converter IC 304. The first zero-crossing detector 704 is coupled to a zero-crossing input node 708 via a first resistor 710 having a first resistance R1. The second zero-crossing detector 706 is coupled to the zero-crossing input node 708 via a second resistor 712 having a second resistance R2. The converter IC 304 includes a level detection circuit 714 coupled to the zero-crossing input node 708 and configured to determine whether the first zero-crossing detector 704 or the second zero-crossing detector 706 has toggled.

[0149] The first resistor R1 and the second resistor R2 are selected to be different. For example, if the first resistor R1 and the second resistor R2 are selected such that R2=2R1, then a proportional logic high level will be seen on the zero-crossing input node 708 when either of the zero-crossing detectors 704, 706 outputs a logic high.

[0150] 7C graphically illustrates this scheme. When the first zero-crossing detector 704 outputs a logic high, the ZC input node 708 is toggled to a first voltage 2 / 3*VDD, where VDD is the supply voltage of the system 300. When the second zero-crossing detector 706 outputs a logic high, the ZC input node 708 is toggled to a second voltage 1 / 2*VDD. When both the first zero-crossing detector 704 and the second zero-crossing detector 706 are toggled high, the ZC input node is pulled up to VDD.

[0151] The above scheme can be scaled to connect more than two zero-crossing detectors to the sample pin. This can be achieved by increasing the complexity of the resistor network coupled between the zero-crossing detectors and the ZC input node, and by increasing the complexity of the level detection circuitry.

[0152] For example, a particular zero-crossing detector, such as that incorporated into the digitally programmable gain controller IC THAT5173, may be configured to transmit a zero-crossing signal or a non-zero-crossing signal. In such an example, it may be sufficient to distinguish between all inputs provided to the ZC input node 708 being ground or all but one of the inputs provided to the ZC input node 708 being ground.

[0153] 7D illustrates an exemplary interface 716, which is a variation of the interface 702 illustrated in FIG. 7B, for coupling six zero-crossing detectors (ZCDs) 718, 720, 722, 724, 726, 728 to the ZC input node 708. Each of the ZCDs 718-728 is coupled to the ZC input node 708 via a respective resistor R1, R2, R3, R4, R5, R6. A level detection circuit 730 is provided in the converter IC 304, and the level detection circuit 730 is configured to detect a voltage level at the ZC input node 708.

[0154] In some embodiments, it may be necessary to determine which of the ZCDs 718-724 triggered the ZC input node 708. FIG. 7E illustrates an exemplary implementation of a level detection circuit 730 as a flash converter. The circuit 730 includes a resistor string including a plurality of resistors R7, R8, R9, R10 coupled in series between a supply voltage VDD and ground GND. The circuit 730 further includes a plurality of comparators 732, 733, 734. A first input of each of the comparators 732, 733, 734 is coupled to the ZC input node 708. A second input of each of the comparators 732, 733, 734 is coupled to a respective node of the resistor string, and one second input is coupled to a respective node between each of the resistors R7, R8, R9, R10. By carefully selecting the values ​​of resistors R1-R6, different combinations of logic high and low outputs from ZCDs 718-728 lead to unique combinations of voltages that can be detected using the flash converter included in level detection circuit 730. It should be understood that other possible conversion techniques are known in the art.

[0155] Figure 8 is a schematic diagram of a two-channel hybrid gain control system 800 according to an embodiment of the present disclosure. The control system 800 is a variation of the system 300 shown in Figure 3, and like parts are numbered likewise. Similar to the control system 300 of Figure 3, the control system 800 includes an analog gain circuit 802 and a converter IC 804.

[0156] Converter IC 804 differs from converter IC 304 of control system 300 in that MUX 326 and ZCD 324 are replaced by a ZCD signal detector 806 .

[0157] 3 by providing a first analog gain stage 806-1 and a second analog gain stage 806-2 instead of the gain stages 306-1, 306-2, and further adding a first ZCD 808 and a second ZCD 810 configured to detect zero-crossing events with respect to a first input signal IN1 and a second input signal IN2 provided to the first analog gain stage 806-1 and the second analog gain stage 806-2, respectively. The outputs of the first ZCD 808 and the second ZCD 810 are coupled via a first resistor R1 and a second resistor R2, respectively, to a ZCD output node Z1 that is coupled to an input of a ZCD signal detector 806 of the converter IC 804. The output of the ZCD signal detector 806 is provided to the FSM 328.

[0158] The first gain stage 806-1 and the second gain stage 806-2 are further configured to change gain states upon detection of a zero crossing in the input signals IN1, IN2 by the ZCDs 808, 810.

[0159] Figure 9 shows an example process 900 implemented by the system 300 of Figure 3. This process 500 for updating gain settings will be described with reference to the first channel of the system 300 shown in Figure 3. However, it should be understood that it is equally applicable to the second channel.

[0160] In step 902 , a new gain setting is received, for example via an encoder in the host device 319 .

[0161] In step 904, it is determined whether the new gain setting is within the dynamic range of the current setting of the analog gain stage 306-1.

[0162] If the new gain setting is within range, the updated gain value for the first digital gain stage 322-1 is written to the first register in step 906. The control circuit 316 activates the gain of the updated digital gain stage 322-1 and the process 900 is complete.

[0163] On the other hand, if it is determined that the new gain setting is not within the range of the current gain setting of the analog gain stage 806-1, then in step 910 the control circuit 816 (or the host device 319) calculates new gain values ​​for the first analog gain stage 306-1 and the first digital gain stage 322-1.

[0164] In step 912, the control circuit 816 or a host (not shown) writes or updates the first register 332 and the second register 334 with the new gain parameters to be subsequently applied in the first analog gain stage 806-1 and the first digital gain stage 322-1. The registers 332, 334 may contain the entire control bit pattern, for example the complete SPI register bit pattern for the first analog gain controller 308-1 connected via SPI. The format depends on the register format of the analog gain controller 308-1. The new analog and digital gain control settings are written to the respective first register 332 and second register 334, but neither is activated at this point.

[0165] In step 914, an updated gain may be triggered, in response to which an analog gain setting may be sent to the first analog gain controller 308-1. For example, the FSM 328 causes the master analog gain controller 330 to write out the entire bit sequence contained in the second register of the first gain controller 308-1. At the end of the bit pattern, in step 916, the signal SPI_CSb is asserted positive, thereby immediately activating the new analog gain setting in the first analog gain stage 806-1.

[0166] In response to receiving the command to change the gain, in step 918 the first gain stage 806-1 waits for a zero-crossing event detected by the first ZCD 808.

[0167] When a zero crossing is detected, the ZCD 808 outputs a signal to the first gain stage 806-1 and the ZCD signal detector 806. In response, in step 920, the gain of the first gain stage 806-1 is changed and the FSM 328 receives an indication of a zero crossing in the input signal IN1 from the ZCD signal detector 806.

[0168] In step 924, the FSM 328 may wait a predetermined period of time. Such a delay may be pre-configured to compensate for the latency of the filters and / or ADCs associated with the first signal chain 312.

[0169] After a predetermined time delay, the FSM 328 then updates the digital gain value of the first digital gain stage 322-1 in step 926. If a gain step and ramp is used, this step may include first performing a gain step according to configured parameters (described above), followed by a gain ramp to the target gain value of the first digital gain stage 322-1.

[0170] If the zero crossing error is negligible, then the step and ramp feature described above may not be very useful since there is unlikely to be a signal discontinuity. The external gain step and fine gain adjustment should be substantially coincident at the zero crossings with respect to the signal.

[0171] In various signal chain systems, such as those described above, transients in the output signal caused by switching and switching-related events may result in audible artifacts in such output signals. Such transients may be caused by one or more of charge injection, misalignment between internal and external gain switching, and / or group delays associated with filter variations.

[0172] Embodiments of the present disclosure aim to address or at least ameliorate one or more of the above problems. In particular, embodiments of the present disclosure may ameliorate or prevent the occurrence of such artifacts in the output signal by configuring a converter IC to mask transients in the input signal with a masking signal.

[0173] FIG. 10 graphically illustrates an example transient of a signal provided to the input of an analog-to-digital converter (ADC). The example transient is typical of a transient caused by the switching action of an analog multiplexer. Two waveforms 1002, 1004 are shown. The first waveform 1002 is an initial transient event in the ADC. The second waveform 1004 is shown after some analog processing. Each boundary in the graphical illustration represents 5 microseconds. It can be seen that these transients are short compared to a typical audio sample rate (e.g., 48 kHz, equivalent sample period of about 20.8 microseconds). Thus, following decimation, the transients as shown tend to be close to the impulse response of the ADC and its decimation filter. Such transients also tend to have a fairly consistent amplitude.

[0174] 11 is a graphical representation of an exemplary converted and decimated digital representation of the transient shown in FIG. 10. The peak amplitude of the transient is approximately 3×10 -3 , or small compared to full scale at about -50 dBFS. It can also be seen that only the first few samples of the transient after decimation have significant amplitude and are therefore audible.

[0175] 12 is a graphical representation of a further example converted and decimated digital signal converted by an ADC such as that described above, with transient errors in the signal circled.

[0176] Figure 13 is an expanded graphical illustration of the circled area of ​​Figure 12. It can be seen that an unaffected valid sample (referred to herein as the leading valid sample) is followed by eight affected samples (referred to herein as the transient or masked samples), which are followed by eight unaffected samples (referred to herein as the trailing valid samples).

[0177] The embodiments of the present disclosure aim to mask or replace components of a received signal that are affected by transients. Such masking or replacement is done in such a way that the modified signal is improved compared to the unmodified signal. Such improvement causes the modified signal to be perceived by the human ear as closer to the signal before the transient was added compared to the unmodified signal. A further aim is that such improvement leads to little or no perceptible distortion when heard by the human ear. Several novel techniques with various performance vs. cost tradeoffs are described herein.

[0178] 14-17 graphically illustrate several masking techniques.

[0179] In the first exemplary technique, as shown in FIG. 14, each transient sample of the converted signal is replaced by a masking sample having an amplitude substantially equal to the preceding valid sample. In FIG. 14, the amplitude of the last preceding valid sample is used as the amplitude of each of the masking samples (i.e., the following eight samples). It should be understood that the embodiments of the present disclosure are not limited to the use of the last preceding valid sample. In addition, in other embodiments, the amplitude of the masking sample may not be set exactly to the amplitude of the preceding valid sample. For example, the amplitude of the masking sample may be set to be equal to the amplitude of the following valid sample (i.e., the sample immediately following the last transient sample, e.g., the first following valid sample).

[0180] It has been found that for optimal performance of this "sample-hold" technique, it may be preferable to mask only some of the transient samples. In particular, it may be preferable to mask only large amplitude transient samples. For example, transient samples below a certain threshold amplitude are inaudible, so masking such transient samples may not provide any perceived benefit to the human ear. In addition, the longer the input signal is held at a single amplitude (e.g., due to the sample-hold masking being extended as described above), the more audible any artifacts associated with such holding will be to the human ear. This is clearly shown in FIG. 13, which shows a large jump in amplitude between the final masked sample and the first valid sample following the masked sample, potentially leading to audible artifacts.

[0181] At a conventional bit rate of 48 kHz, the optimal hold time (i.e., masking period) for low latency design of the decimation filter was found to be 5 samples. In this example, low latency may be considered to be less than 10 samples. This hold time allows the strongest components of a typical transient to be hidden while at the same time minimizing any audible artifacts associated with the hold itself at the sample time. It should be appreciated that the optimal hold time duration may depend on the decimation filter characteristics, since the transients associated with the gain switching discussed above tend to be close to the impulse response of the decimation filter (by virtue of being relatively short in duration compared to the sample rate). In some embodiments, the hold duration may depend on the signal level. For example, for signal levels above a certain threshold, the hold time may be reduced to, for example, 2 or 3 samples.

[0182] It should be understood that in some input signal conditions, the implementation of sample hold masking may lead to undesirable artifacts, for example by causing signal errors to be more audible than the transient itself. Therefore, it may be preferable to apply this technique only under certain conditions. The audibility of the signal error is proportional to the product of the sample hold period and the rate of change of the signal. The higher the rate of change of the signal, the more audible the signal error associated with the sample hold will be. Thus, in some embodiments, the rate of change of the signal may be monitored, and a sample hold may be performed when the rate of change falls below a threshold rate.

[0183] As mentioned above, the higher the input signal level, the more audible the sample-retained masking is (because the absolute error resulting from retention is proportional to the signal level). In addition, the effects of temporal masking and spectral masking are stronger the louder the sound. As for the transient itself, the higher the input signal level, the less audible (often inaudible) the discontinuity caused by the transient is. This is because the transient amplitude tends to be small compared to the maximum (full-scale) signal amplitude. Thus, the relative error caused by the transient is smaller. In addition, unlike the amplitude error caused by sample-retained masking, which is closely related to the amplitude of the signal itself, the amplitude of the error caused by the transient is constant, so that the ratio of the transient error amplitude to the amplitude of the sample-retained masking error decreases as the signal amplitude increases. In view of the above, sample-retained masking can only be performed when the signal level is below a certain threshold.

[0184] In the embodiments described herein, the signal level may be defined as an approximation of the perceived signal level. There are several ways to approximate the perceived signal level. For example, the perceived signal level may be approximated as the root-mean-square (RMS) signal level over a period of time (time constant). For example, the time constant may be approximately equal to the tone resolution of human hearing. For example, the time constant may be set to be close to the period of the lowest audible frequency component in the signal. In some embodiments, the RMS time constant may be set to about 50 ms (i.e., 1 / 20 Hz), i.e., approximately the lower frequency limit of human hearing.

[0185] It should be understood that calculating the exact RMS of a signal over a period of time can be computationally intensive. Therefore, optimized RMS calculation techniques can be implemented to reduce the processor load. For example, instead of calculating the RMS, a moving average of the signal amplitude (e.g., the average of the signal absolute value) can be calculated. The value of the approximated perceived signal level may differ slightly from the exact RMS, but for the application described herein, the approximation is close enough. Using the average signal amplitude eliminates the need to perform square and square root functions in hardware (or software).

[0186] In further optimization, an exponential moving average amplitude algorithm may be implemented. Such implementation may save significant memory usage and processing power. In some embodiments, the exponential moving average signal threshold for triggering masking using the above sample-holding technique may be approximately -45 dB.

[0187] As mentioned above, the above-mentioned sample-and-hold techniques may lead to signal errors and discontinuities that may be audible. To address such issues, the above-mentioned sample-and-hold techniques may be adapted to apply a ramp at the beginning (i.e., ramp-in) and / or end (i.e., ramp-out) of the masking signal. In doing so, the transitions of the output signal between the preceding valid sample and the masking signal may be smoothed. In addition, the transitions of the output signal between the masking signal and the following valid sample may also be smoothed. These smoothed transitions at the beginning and after masking may reduce the audibility of the masking.

[0188] 15 is a graphical illustration of a smoothed sample hold masking signal that implements a ramp-in that smooths the transition between the previous valid sample and the hold sample amplitude (i.e., a fixed amplitude). As shown in FIG. 15, the ramp-in is preferably non-linear rather than linear. Such a non-linear ramp may ramp towards the hold amplitude over time, resulting in a smoother signal compared to a masking signal that holds at a fixed amplitude from the first masking sample of the masking signal.

[0189] There are various techniques for achieving the smooth ramp shown in FIG. 15. In some embodiments, the difference between the two preceding valid samples before the masking sample is calculated. The amplitude of the first masking sample may be set to be equal to the sum of the last of the two preceding valid samples and the difference. For example, referring to FIG. 15, the amplitude AMN of the nth masking sample MN may be defined by the following equation: A MN =A V2 +(A V2 -A V1 )*k MN where k MN is a scaling factor that decreases successively for each masked sample after k until the end of the retention period. In doing so, the change in masked signal amplitude from one masked sample to the next decreases over the retention period. In one example, k M1 = 1 and k M2 =0.8, k M3 =0.6, etc.

[0190] The rate of change of the scaling factor may be configurable. For example, the scaling factor k MN The rate of change of k can increase as the duration of the masking signal decreases. Similarly, the scaling factor k MN may decrease as the duration of the masking signal increases.

[0191] Figure 16 is a graphical illustration of a ramp-out or smoothing of the transition between the masked signal and the valid sample following the masked signal, which reduces the discontinuity associated with the abrupt release of the hold shown in Figure 14. As with the ramp-in, the ramp-out is preferably non-linear. Such a non-linear ramp may tend over time to the amplitude of the valid sample following the masked signal, resulting in a smoother signal compared to a masked signal that is held at a fixed amplitude before abruptly transitioning to the first valid sample.

[0192] It should be noted that in the illustrated example, the ramp-out is not performed on the masking signal itself, but on the valid sample following the masking signal. This is due to the fact that the illustrated technique utilizes the amplitude value of the valid sample following the invalid sample (masked sample) to ensure a smooth transition of the roll-out (ramp-out) towards the valid signal following the masking signal.

[0193] We now describe an exemplary technique for performing ramp-out, shown in FIG. 16. After the last masking sample, a set of transition samples may replace the valid samples following the masking signal. The amplitude of each transition sample may be calculated as the sum of the amplitude of the previous transition sample and the difference between the amplitude of the previous transition sample and the previous valid sample replaced by the previous transition signal. For example, A T =A TP +(A VP -A TP )*F Here, A T is the current transition sample amplitude, and A TP is the previous transition sample amplitude, and A VP is the previous valid sample amplitude (i.e., the amplitude of the sample replaced by the previous transition sample). F is a factor whose value may be changed (e.g., increased or decreased) for each successive transition sample to achieve the desired nonlinear ramp of the transition samples as shown in FIG.

[0194] It should be appreciated that in this embodiment, the amplitude of the sample of the first transition will be a weighted average of the amplitudes of the last masked sample and the last actual (non-valid / transient) sample. Thus, if the final sample masked by the masking signal is significantly distorted, it may be preferable to hold for further samples to remove the effects of such distortion on the transition / ramp-out.

[0195] It should be appreciated that combinations of the above ramp-in and ramp-out techniques may be implemented to achieve both ramp-in and ramp-out of the sample output signal.

[0196] A drawback of the above scheme is that the amplitude of the first valid sample after the masking sample is unknown. Therefore, any ramping performed during masking may be in a different direction than that of the actual (undistorted) signal. The above technique may lead to unexpected discontinuities in some implementations.

[0197] In a further exemplary masking technique, a look-ahead scheme may be employed. For example, the input signal may be delayed by a predetermined number of samples, so that the amplitude of the first sample after the transient is known and taken into account when calculating the masking signal. In some embodiments, the signal may be delayed by more samples than the hold period, for example, one more sample than the hold period, i.e., <hold period+1> samples. By looking ahead, different masking signals may be generated.

[0198] In a first example, linear interpolation may be used to generate a linear ramp between the last valid sample preceding the transient and the first valid sample following the transient, as shown in Figure 17. Combined with the zero-crossing technique described above, this solution provides superior performance and greatly reduces the need for signal level detection when applying masking. Masking using this technique may therefore be performed substantially independent of signal level.

[0199] It should be appreciated that in practice audio signals rarely take the shape of a linear ramp, and such a shape may lead to distortion of the signal.

[0200] To avoid this and improve performance (at the expense of complexity, processing power, and cost), nonlinear interpolation may be used to create a nonlinear ramp between the last valid sample preceding the transient and the first valid sample following the transient. Figure 18 shows an example of nonlinear interpolation.

[0201] The non-linear interpolation can be achieved in a variety of ways.

[0202] For example, higher order interpolation may be employed using valid samples before and after the masking sample.

[0203] In another example, the ramp-in and ramp-out technique described may be employed, but a more accurate masking signal may be achieved because both the start and end points of the ramp-in and ramp-out are known. In this example, the ramp-out may begin and be completed during the masking period T itself, rather than extending into the valid sample following the masking sample.

[0204] In a further example, n samples preceding application of the mask may be stored in memory and a signal pattern may be determined based on the n samples. Looking ahead, the amplitude of the first valid sample after the masking period may be determined. The first masked sample amplitude may be calculated based on the pattern of n samples and the first valid sample amplitude. Successive look-aheads may then be employed to look ahead the same number of samples. A second masked sample may then be calculated based on the signal pattern of n samples before the mask and the pattern of n valid samples after the mask.

[0205] In a further example, an approach may be to look ahead one or more valid samples following the masking signal and estimate the signal pattern during masking. Such an estimate is likely to be more accurate (knowing the difference between the valid samples following the masking signal). However, the further ahead one looks, the greater the delay of the implementation.

[0206] Any or all of the masking techniques described above may be implemented in combination with the above-described hybrid gain control systems 300, 800. In particular, the masking methods described herein may be implemented to remove or reduce any discontinuities associated with lag times of gain switching in a multiple gain stage system.

[0207] The masking embodiments above have been described with reference to a single channel, however it should be appreciated that in practice many audio signals and systems use multiple channels.

[0208] When processing multiple channels, a one-channel-at-a-time technique may be employed, in which any of the above masking techniques are performed asynchronously on each channel. As mentioned above, embodiments of the present disclosure aim to mask transients caused by gain updates (e.g., switching at gain stages 806, 322). Such gain updates in each channel are preferably zero-cross aligned to minimize the audibility of such transients. An advantageous effect of this is that a gain change (and thus a transient) in one channel is unlikely to coincide in time with a gain change (and thus a transient) in another channel. With this in mind, channels may be updated one at a time. An advantage of this scheme is that as the channels are updated, any distortion introduced by the masking of a transient only occurs in a single channel at a time, while other channels are undistorted. Thus, distortion introduced by masking in one channel may be less audible due to perceptual auditory masking of artifacts associated with masking by other channels. This may be particularly applicable when multiple channels contain correlated content (e.g., stereo signals, multi-microphone configurations.) In addition, hardware implementations are more computationally efficient by processing each channel sequentially, since respective processing power can be reused for each channel, avoiding duplication.

[0209] In another example, all channels may be processed in parallel, it being understood that such processing may be faster at the expense of processing power and cost.

[0210] In another example, only one channel may be monitored and a single masking signal may be generated based on the one monitored channel and applied to all channels.

[0211] In a further example, which may also be particularly applicable when multiple channels contain correlated content (e.g., stereo signals, multi-microphone configurations), the last n samples of a first channel may be used to mimic a second channel to mask transients in the second channel.

[0212] 19 is a schematic diagram of an exemplary two-channel hybrid gain control system 1900 according to an embodiment of the present disclosure. The control system 1900 is a variation of the system 300 shown in FIG. 3, where like parts are given like numbers. The control system 1900 is configured to perform transient masking with signal level thresholding, as described in more detail below.

[0213] Similar to the control system 300 of Figure 3, the control system 800 includes an analog gain circuit 302 and a converter IC 1904. The converter IC 1904 differs from the converter IC 300 of Figure 3 in that the converter IC 1904 further includes an exponential moving average (EMA) level detector 1906, and a first masking module 1908-1 and a second masking module 1908-2.

[0214] First and second masking modules 1908-1 are provided on respective first and second signal paths 312 and 314. The first masking module 1908-1 is coupled between an output of the first digital gain stage 322-1 and an output of the first signal chain 312. The second masking module 1908-2 is coupled between an output of the second digital gain stage 322-2 and an output of the second signal chain 314. Each of the first masking module 1908-1 and the second masking module 1908-2 may be configured to perform any one of the masking techniques described above with reference to FIGS. 14-18.

[0215] The outputs of the first decimator 320-1 and the second decimator 320-2 are provided to an EMA level detector 1906, which is configured to determine an exponential moving average signal level of each of the signals output from the first decimator 320-1 and the second decimator 320-2. In other embodiments, the EMA level detector 1906 may be replaced by a module configured to estimate the perceived signal level in any conceivable manner (such as RMS level detection).

[0216] Such EMA signal level is output to the FSM 328. The FSM 328 is configured to output one or more control signals to each of the masking modules 1908-1, 1908-2 based on one or more of the EMA signal level(s) provided from the EMA level detector 1906 and the ZCD module 324. As described above, masking may be triggered, for example, at a zero-crossing event in the input signal. In some embodiments, masking may be performed only when the perceived signal level is below a threshold. Thus, the FSM 328 may control the masking modules 1908-1, 1908-2 to trigger masking based on a zero-crossing event and, optionally, a determination that the perceived signal level is within a threshold range below a threshold level. A trigger signal indicating when transient masking should be performed may be generated based on the timing of an event causing a transient (e.g., using a combination of zero-crossing detection and known signal chain delays) or by detecting a transient. Optionally, one or more condition detectors may be used to enable and / or disable the transient masking or to modify one or more parameters of the transient masking. Any such transient masking may be optimized for the signal conditions.

[0217] It should be noted that, as used herein, the term module is used to refer to a functional unit or block that may be implemented at least in part by dedicated hardware components, such as custom-defined circuits, and / or that may be implemented at least in part by suitable code executed on one or more software processors or suitable general-purpose processors, etc. A module may itself contain other modules or functional units. A module may be provided by multiple components or sub-modules that need not be co-located, but may be provided on different integrated circuits and / or executed on different processors.

[0218] Embodiments may be implemented in a host device, particularly a mobile computing device, e.g. a portable and / or battery-powered host device such as a laptop computer or a tablet computer, a game console, a remote control device, a home automation controller or appliance including a home temperature or lighting control system, a toy, a machine such as a robot, an audio player, a video player, or a mobile phone, e.g. a smartphone, a mixing device or console (such as an audio mixing device or audio mixing console), an audio recording device, a paging station, an audio input device for use with a computer, a musical instrument, an audio effects processor, an audio director device, an audio capture device, an audio broadcasting device, an audio reinforcement device, a wireless electric musical instrument interface, a wireless microphone, a microphone with a digital output, an ultrasonic sensing device, an ultrasonic recording device, or a sonar device.

[0219] As used herein, when two or more elements are referred to as "coupled" to one another, such term indicates that such two or more elements are in electronic or mechanical communication, as applicable, with or without an indirect or direct connection, with or without intervening elements.

[0220] The present disclosure encompasses all changes, substitutions, variations, modifications, and alterations to the exemplary embodiments herein that would be understood by a person skilled in the art. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, modifications, and alterations to the exemplary embodiments herein that would be understood by a person skilled in the art. Furthermore, in the appended claims, reference to an apparatus or system, or an apparatus or system component that is adapted, arranged, enabled, configured, enabled ... Additionally, the operations of the systems and apparatus disclosed herein may be performed by more, fewer, or other components, and the methods described may include more, fewer, or other steps. Moreover, the steps may be performed in any suitable order. As used in this document, "each" refers to each member of a set, or each member of a subset of a set.

[0221] Although exemplary embodiments are shown in the drawings and described below, the principles of the present disclosure may be implemented using any number of technologies, whether currently known or not, and the present disclosure should in no way be limited to the exemplary implementations and technologies shown in the drawings and described above.

[0222] Unless otherwise indicated, items depicted in the drawings are not necessarily drawn to scale.

[0223] All examples and conditional language recited herein are intended for educational purposes to aid the reader in understanding the disclosure and the concepts contributed by the inventors to further the present technology, and are not to be construed as being limited to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.

[0224] While certain advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages will be readily apparent to one of ordinary skill in the art after reviewing the foregoing figures and description.

[0225] It should be noted that the above-mentioned embodiments are illustrative rather than limiting of the present invention, and those skilled in the art can design many alternative embodiments without departing from the scope of the appended claims. The word "comprises" does not exclude the presence of elements or steps other than those listed in the claim, and "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfill the functions of multiple units recited in the claim. Any reference signs or labels in the claims should not be interpreted as limiting their scope.

Claims

1. Integrated circuits (ICs) A first input pin for receiving a first input signal, A first converter configured to convert the first input signal into a first output signal, A first gain stage configured to generate a first amplified output signal by applying a first gain to the first output signal, This is a gain update circuit, The first external gain control signal is output to the first output pin of the IC, Next, a first internal gain control signal is output to the first gain stage to update the first gain of the first gain stage, wherein the output of the first internal gain control signal is delayed by a first predetermined delay relative to the output of the first external gain control signal, and the first predetermined delay is for compensating for the signal chain delay between the first input pin and the first gain stage. A gain update circuit configured to perform the following: An IC equipped with this feature.

2. The aforementioned gain update circuit With respect to a signal event that updates the first gain of the first gain stage, the first input signal or the first output signal is monitored. The output of the first internal gain control signal is time-aligned so that it coincides with the signal events reaching the first gain stage. The IC according to claim 1, further configured as follows.

3. The IC according to claim 2, wherein the signal event includes a zero-crossing of the first input signal or the first output signal, and the gain update circuit includes a zero-crossing detection circuit configured to monitor the first input signal or the first output signal for the zero-crossing.

4. The aforementioned gain update circuit The IC receives a first signal event flag at the signal event input pin. The timing of the output of the internal gain control signal is determined based on the time the aforementioned signal event flag is received. The IC according to claim 1, configured as described above.

5. The IC according to claim 4, wherein the first signal event flag indicates a zero-crossing of the first input signal.

6. The IC according to claim 4 or 5, wherein the gain update circuit includes a level detection circuit configured to process a received first signal event flag.

7. The IC according to claim 4, wherein the gain update circuit includes a level detection circuit configured to process a received first signal event flag, and the level detection circuit includes a flash analog-to-digital converter (ADC).

8. The IC according to claim 1, wherein the converter includes an analog-to-digital converter.

9. The IC according to claim 1, further comprising a filter circuit provided between the first input pin and the converter, wherein the filter circuit is configured to filter the first input signal provided to the converter, and the filter circuit contributes to the signal chain delay.

10. The IC according to claim 9, wherein the filter circuit is configured to perform low-pass filtering on the first input signal.

11. The IC according to claim 9, wherein the filter circuit is configured to impedance match the first input signal to the input impedance of the converter.

12. The IC according to claim 1, wherein the first input signal is an audio signal.

13. The IC is An interface for receiving a first gain setting from the host device, One or more registers for storing the first gain setting, Furthermore, The aforementioned gain update circuit Read the first gain setting from one or more registers, Based on the first gain setting, the first external gain control signal and / or the first internal gain control signal are generated. The IC according to any one of claims 1, configured as described above.

14. The IC according to claim 13, wherein the first gain setting includes a first external gain setting and a first internal gain setting, the first internal gain setting and the first external gain setting are stored in separate registers from the one or more registers, and the first external gain setting and the first internal gain setting are handled atomically by the gain control circuit.

15. The IC according to claim 13, wherein the IC is configured to receive and process the first gain setting at the interface asynchronously with respect to the output of the first external gain control signal and the first internal gain control signal.

16. The aforementioned gain update circuit Determine whether the first gain setting is within the dynamic range of the first gain of the first gain stage. If the first gain setting is within the dynamic range of the first gain of the first gain stage, the first internal gain control signal is updated based on the first gain setting. If the first gain setting is outside the dynamic range of the first gain of the first gain stage, the first internal gain control signal and the first external gain control signal are updated. The IC according to any one of claims 13 and 15, configured as described above.

17. The IC according to claim 13, wherein the interface is a serial interface.

18. The IC is A second input pin for receiving a second input signal, A second converter configured to convert the second input signal into a second output signal, A second gain stage configured to apply a second gain to the second output signal, Furthermore, The aforementioned gain update circuit The second external gain control signal is output to the second output pin of the IC, Next, a second internal gain control signal is output to the second gain stage to update the second gain of the second gain stage, wherein the output of the second internal gain control signal is delayed by a second predetermined delay relative to the output of the second external gain control signal, and the second predetermined delay is for compensating for the signal chain delay between the second input pin and the second gain stage. The IC according to claim 1, configured to perform the following:

19. A system, A first analog input for receiving a first analog input signal, A first analog gain stage is configured to generate the first input signal by applying a first analog gain to the first analog input signal, The IC described in claim 1, A system equipped with these features.

20. The system according to claim 19, wherein the first analog gain and the first gain are adjustable by stepwise changes, and the stepwise changes of the first analog gain are greater than the stepwise changes of the first gain.

21. The system according to claim 19, wherein the first analog gain stage includes a zero-crossing detector configured to detect zero-crossing events in the analog input signal.

22. The first analog gain stage is A resistor network containing multiple resistors, Multiple switches, The system according to claim 19, including the system described in claim 19.

23. The system according to claim 19, further comprising an external filter circuit provided between the first analog gain stage and the IC, wherein the external filter circuit is configured to filter the first input signal provided to the IC, and the filter circuit contributes to signal chain delay.

24. The system according to claim 23, wherein the filter circuit is configured to perform low-pass filtering on the first input signal.

25. The system according to claim 23, wherein the filter circuit is configured to impedance match the first input signal to the input impedance of the converter.

26. A sync input pin for receiving multiple sync signals, A synchronization interface configured to process the plurality of synchronization signals, The system according to claim 19, further comprising:

27. The system according to claim 26, wherein each of the plurality of synchronization signals includes a zero-crossing detection flag.

28. A gain control circuit, An input for receiving analog input signals, A first gain stage that applies a first gain to the input signal to provide an intermediate signal, the first gain stage including an array of resistors and analog switches, Integrated circuits (ICs) An analog-to-digital converter (ADC) configured to convert the aforementioned intermediate signal into a digital signal, A second gain stage configured to apply a second gain to the aforementioned digital signal to provide an amplified output signal, ICs, including, A synchronization module configured to generate a synchronization control signal for the first gain stage such that the update of the first gain can be synchronized with the update of the second gain to prevent artifacts in the amplified output signal, A gain control circuit equipped with the following features.

29. The gain control circuit according to claim 28, wherein the synchronization module is configured to generate the synchronization control signal in such a way that artifacts result from the adjustment of the first gain and the second gain not being timely in sync with the analog input signal.

30. Integrated circuits (ICs) Analog-to-digital converter (ADC), Gain stage and A synchronization module configured to output a synchronization signal, It is an IC equipped with, The IC is for use in the gain control circuit described in claim 28 or 29.

31. Integrated circuits (ICs) A converter configured to convert an input signal into an output signal, A gain function configured to apply a gain to the output signal to provide an amplified output signal, wherein the gain function is configured to update the level of the gain in response to the reception of a first synchronization signal, A delay circuit configured to implement a programmable time delay between the reception of the first synchronization signal and the updating of the gain level, An IC equipped with this feature.

32. The IC according to claim 31, wherein the programmable time delay is programmed to match the signal latency associated with an external circuit that generates the input signal.

33. A memory for storing a user-definable delay value, wherein the delay circuit is configured to set the programmable time delay based on the user-definable delay value. The IC according to claim 31, further comprising:

34. The IC according to claim 31, wherein the first synchronization signal is generated on the IC.

35. The IC according to claim 31, wherein the first synchronization signal is generated outside the IC and received at an input pin of the IC.

36. The IC according to claim 35, wherein the IC is configured to receive the first synchronization signal and at least one second synchronization signal at the input pins of the IC.

37. The IC according to claim 31, wherein the converter is an ADC, the output signal is a digital signal, and the gain function includes a digital gain stage.

38. Integrated circuits (ICs) A converter configured to convert an input signal into an output signal, A gain stage configured to apply gain to the output signal to provide an amplified output signal, It is a synchronization module, The input signal or the output signal is monitored for an appropriate period of time, and the gain is updated based on the monitored input signal or output signal. In response to determining that the aforementioned appropriate period exists, an internal synchronization flag is generated. A synchronization module configured in such a way, It is an IC equipped with, In internal synchronization mode, the gain stage is configured to update the gain level in response to the internal synchronization flag. In external synchronization mode, the gain stage is configured to update the gain level in response to the reception of an external synchronization flag received at the synchronization input of the IC.

39. A synchronous selection input for receiving a selection signal, wherein the selection between the internal synchronous mode and the external synchronous mode is performed based on the selection signal. The IC according to claim 38, further comprising:

40. The IC according to claim 38, wherein the external synchronization flag is received from the host device.

41. The aforementioned synchronization module The zero-crossing of the monitored input or output signal is detected to determine the appropriate period. The IC according to claim 38, configured as described above.

42. A signal processing circuit configured to receive an input signal and output a processed output signal, wherein the signal processing circuit is configured to receive an input signal and output a processed output signal. The input signal receives an indication of the time position of a transient. The processed output signal provides a masking signal that bridges the time position of the transient in order to mask the transient. A signal processing circuit configured in such a way.

43. Integrated circuits (ICs) A zero-crossing detector circuit configured to detect zero-crossing events in an analog input signal and output a control signal to an analog gain circuit, An analog-to-digital converter (ADC) that converts the amplified analog input signal, which has been amplified by the aforementioned analog gain circuit, into a digital output signal, A digital gain circuit configured to apply gain to the digital output signal, A masking circuit configured to provide a masking signal in the aforementioned digital output signal, wherein the masking signal is temporally aligned with the transients of the input signal. An IC equipped with this feature.

44. An electronic device comprising an IC according to claim 1, 30 to 41, or claim 43, or a system according to claim 19, or a gain control circuit according to any one of claims 28 to 29, or a signal processing circuit according to claim 42.

45. The electronic device according to claim 44, wherein the electronic device includes a laptop, notebook, netbook or tablet computer, gaming device, game console, controller for game console, virtual reality (VR) or augmented reality (AR) device, mobile phone, portable audio player, portable device, laptop, notebook, netbook or tablet computer, gaming device, game console, VR or AR device, mobile phone, portable audio player, or accessory device for other portable devices, mixing console, audio mixing device, audio recording device, paging station, audio input device for use with a computer, musical instrument, audio effects processor, audio supervision device, voice capture device, audio broadcasting device, sound enhancement device, wireless electric musical instrument interface, wireless microphone, microphone with digital output, ultrasonic sensing device, ultrasonic recording device, or sonar device.

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