Equalizer circuit

Abstract

To provide an equalizer circuit capable of shaping a multi-value PAM signal.SOLUTION: An equalizer circuit 600 comprises a variable gain equalizer circuit 610. A third transistor MN53 for gain adjustment is inserted between the source of a first transistor MN51 that configures an input differential pair of the variable gain equalizer circuit 610, and a first current source IB51. A fourth transistor MN54 for gain adjustment is inserted between the source of a second transistor MN52 that configures the input differential pair, and a second current source IB52. The gates of the third transistor MN53 and the fourth transistor MN54 are supplied with a first bias voltage Vb1 to be able to control the DC gain of the variable gain equalizer circuit 610.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to an equalizer circuit.

Background Art

[0002] In conventional serial data transmission, the NRZ (Non Return to Zero) method was the mainstream. However, in applications that require a higher transmission rate, a multi-level PAM method such as PAM (Pulse Amplitude Modulation) 4 is adopted.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In high-speed serial data transmission, waveform distortion that occurs during propagation through the transmission line becomes a problem. The main cause of waveform distortion in the transmission line is high-frequency attenuation. As a method for correcting waveform distortion, pre-emphasis that emphasizes the high frequency in advance on the transmitter side so as to cancel the attenuation in the transmission line, and de-emphasis that attenuates the low frequency in advance on the transmitter side so as to balance the high frequency attenuated in the transmission line are known.

[0005] Alternatively, another approach is to equalize the received signal and shape its waveform within the receiving device. Furthermore, the receiving device needs to amplify the received signal to match the input range of the subsequent A / D converter (quantizer). Therefore, the receiving device requires both amplification and equalization functions.

[0006] This disclosure is made in response to the circumstances described herein, and one of its exemplary purposes is to provide an equalizer circuit capable of appropriately receiving multi-level PAM signals. [Means for solving the problem]

[0007] Aspects of this disclosure relate to an equalizer circuit. The equalizer circuit comprises a variable-gain equalizer circuit and a first bias circuit that generates a first bias voltage. The variable-gain equalizer circuit comprises a first input terminal, a second input terminal, a first transistor whose gate is connected to the first input terminal, a second transistor whose gate is connected to the second input terminal, a first resistor connected to the drain of the first transistor, a second resistor connected to the drain of the second transistor, a first current source, a second current source, a third transistor connected between the source of the first transistor and the first current source and having a first bias voltage applied to its gate, a fourth transistor connected between the source of the second transistor and the second current source and having a first bias voltage applied to its gate, a third resistor connected between the connection node of the third transistor and the first current source, and the connection node of the fourth transistor and the second current source, and a capacitor connected in parallel with the third resistor.

[0008] Furthermore, any combination of the above components, or any substitution of components or expressions between methods, apparatus, systems, etc., are also valid as embodiments of the present invention or this disclosure. Moreover, the description in this section (means for solving the problem) does not describe all the indispensable features of the present invention, and therefore, subcombinations of these described features may also constitute the present invention. [Effects of the Invention]

[0009] According to certain aspects of this disclosure, multi-level PAM signals can be accurately received. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a circuit diagram of the equalizer circuit related to the comparative technology. [Figure 2] Figure 2 is a circuit diagram of an equalizer circuit according to an embodiment. [Figure 3] Figure 3 is a circuit diagram of the variable gain equalizer circuit according to Example 1. [Figure 4] Figure 4 is a circuit diagram of a receiving device equipped with the variable gain equalizer circuit shown in Figure 3. [Figure 5] Figure 5 is a circuit diagram showing an example configuration of a D / A converter that functions as a bias circuit. [Figure 6] Figure 6 is a circuit diagram of a variable gain equalizer circuit according to Example 2. [Figure 7] Figure 7 is a circuit diagram of a receiving device equipped with the variable gain equalizer circuit shown in Figure 6. [Figure 8] Figure 8 is a block diagram of the transmission system for an N-value PAM (PAM-N) signal according to the embodiment. [Modes for carrying out the invention]

[0011] This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow. It is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify essential elements of all embodiments or to delineate the scope of some or all aspects. For convenience, “one embodiment” may be used to refer to one or more embodiments (examples or variations) disclosed herein.

[0012] An equalizer circuit according to one embodiment includes a variable gain equalizer circuit and a first bias circuit that generates a first bias voltage. The variable gain equalizer circuit includes a first input terminal, a second input terminal, a first transistor whose gate is connected to the first input terminal, a second transistor whose gate is connected to the second input terminal, a first resistor connected to the drain of the first transistor, a second resistor connected to the drain of the second transistor, a first current source, a second current source, a third transistor connected between the source of the first transistor and the first current source and to which a first bias voltage is applied at its gate, a fourth transistor connected between the source of the second transistor and the second current source and to which a first bias voltage is applied at its gate, a third resistor connected between the connection node of the third transistor and the first current source, and the connection node of the fourth transistor and the second current source, and a capacitor connected in parallel with the third resistor.

[0013] In this configuration, the variable gain equalizer circuit functions as a high-frequency boost filter through a combination of a third resistor and a capacitor (also called a source-to-source capacitor). Furthermore, by changing the first bias voltage, the gain of the variable gain equalizer circuit can be changed, allowing it to function as a variable gain amplifier as well. In other words, this configuration allows for both amplification and equalization of the received signal in a single stage. This reduces the circuit area and power consumption compared to configuring the amplifier and equalizer as separate stages.

[0014] In the above configuration, excessive amplification of multi-level received waveforms can be suppressed, and equalization can be performed while maintaining uniform multi-level levels.

[0015] In one embodiment, the resistance value of the third resistor may be variable. This allows the equalizing characteristics to be adjusted according to the resistance value of the third resistor.

[0016] In one embodiment, the third resistor may be composed of a combination of multiple resistors and multiple switches, and the resistance value of the third resistor may be digitally controllable.

[0017] In one embodiment, the third resistor may include a field effect transistor. The equalizer circuit may further include a second bias circuit that supplies a second bias voltage to the gate of the field effect transistor.

[0018] In one embodiment, a plurality of variable gain equalizer circuits may be connected in series.

[0019] In one embodiment, a plurality of variable gain equalizer circuits may be connected in series. The third resistor may include a field effect transistor. The equalizer circuit may further include a second bias circuit that supplies a common second bias voltage to the gates of the field effect transistors that constitute the third resistors of the plurality of variable gain equalizer circuits.

[0020] In one embodiment, the first bias circuit may include at least one current D / A converter that converts a digital input into a tunable current output, and an I / V conversion circuit that converts the output current of the at least one current D / A converter into a first bias voltage.

[0021] In one embodiment, the second bias circuit may include at least one current D / A converter that converts a digital input into a tunable current output, and an I / V conversion circuit that converts the output current of the at least one current D / A converter into a second bias voltage.

[0022] In one embodiment, the equalizer circuit may be integrally integrated on a single semiconductor substrate. "Integral integration" includes cases where all components of the circuit are formed on the semiconductor substrate, or cases where the main components of the circuit are integrally integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting circuit constants. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0023] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the disclosure and invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and invention.

[0024] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0025] Similarly, "the state in which member C is connected (provided) between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the function or effect produced by their combination.

[0026] In this specification, the symbols attached to electrical signals such as voltage signals and current signals, or to circuit elements such as resistors, capacitors, and inductors, shall represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, and inductance) as needed.

[0027] In this embodiment, an equalizer circuit for shaping multi-level signals, including PAM4 signals, will be described. This equalizer circuit will be equipped with a variable gain amplification function (VGA) and an equalization function.

[0028] • VGA function A receiving device for multi-level signals includes a quantizer (A / D converter) that determines the level of the received signal, which has multiple levels. This received signal level is attenuated by the transmission path, and the amount of attenuation varies depending on the length of the transmission path. Therefore, the receiving device needs to amplify the received signal with an appropriate gain to match the input range of the quantizer. This is the VGA function.

[0029] • Equalizing function In a transmission line, the high-frequency components of a transmitted multi-level signal are attenuated relatively more significantly than the low-frequency components, which causes waveform distortion in the received signal. To correct this waveform distortion, it is necessary to correct the frequency components contained in the received signal. This is the equalization function.

[0030] First, the present inventor will describe the equalizer circuit 500 related to the comparative technology he investigated.

[0031] Figure 1 is a circuit diagram of the equalizer circuit 500 related to the comparative technology. The equalizer circuit 500 is a waveform shaping circuit consisting of two stages: an equalizer circuit 510 and a variable gain amplifier 520, which shapes the waveform of the input differential signal.

[0032] The basic configuration of the preceding equalizer circuit 510 and the subsequent variable gain amplifier 520 is the same, and they are both differential amplifiers. The differential amplifier includes input differential pairs MN#1, MN#2, load resistors RD#1, RD3#2, and bias current sources IB#1, IB#2. For the equalizer circuit 510, #=3, and for the variable gain amplifier 520, #=4.

[0033] The equalizer circuit 510 includes a parallel connection circuit of resistor RS3X and capacitor CS30 connected between the sources of the input differential pairs MN31 and MN32. The equalizer circuit 510 has a frequency characteristic determined by the circuit constants of resistor RS3X and capacitor CS30. For example, resistor RS3X is configured as a variable resistor, and the frequency characteristic can be adjusted according to its resistance value.

[0034] The variable gain amplifier 520 includes a resistor RS4X connected between the input differential pairs MN31 and MN32 and their sources. Resistor RS4X is a variable resistor, and the gain of the variable gain amplifier 520 can be adjusted according to its resistance value.

[0035] The inventors of the present invention have investigated the equalizer circuit 500 shown in Figure 1 and have come to recognize the following problems.

[0036] In multi-level PAM signaling, multiple signal levels corresponding to the multi-level states are evenly distributed. However, if the amplification capability of the MOS transistor in the preceding equalizer circuit 510 is high, the evenly distributed multi-level levels are excessively amplified as the multi-level PAM signal passes through the equalizer circuit 510, causing the waveform to deform into one where the multi-level levels are unevenly distributed.

[0037] Furthermore, because the equalizer circuit 510 and the variable gain amplifier 520 are configured as separate stages, there is a problem of large circuit area and high current consumption.

[0038] The following section describes an equalizer circuit that improves upon the shortcomings of the comparative technology shown in Figure 1.

[0039] Figure 2 is a circuit diagram of the equalizer circuit 600 according to the embodiment. The equalizer circuit 600 comprises a variable gain equalizer circuit 610 and a first bias circuit 620. The equalizer circuit 600 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate.

[0040] The first bias circuit 620 generates the first bias voltage Vb1.

[0041] The variable gain equalizer circuit 610 includes a first input terminal INP, a second input terminal INN, a first transistor MN51, a second transistor MN52, a third transistor MN53, a fourth transistor MN54, a first resistor RD51, a second resistor RD52, a third resistor RS5X, a first current source IB51, a second current source IB52, and a capacitor CS50.

[0042] The first transistor MN51 and the second transistor MN52 form an input differential pair, with the gate of the first transistor MN51 connected to the first input terminal INP and the gate of the second transistor MN52 connected to the second input terminal INN.

[0043] The first resistor RD51 is connected between the drain of the first transistor MN51 and the power supply line. The second resistor RD52 is connected between the drain of the second transistor MN52 and the power supply line.

[0044] The first current source IB51 and the second current source IB52 generate a constant current.

[0045] The third transistor MN53 is connected between the source of the first transistor MN51 and the first current source IB51, and the first bias voltage Vb1 generated by the first bias circuit 620 is applied to its gate. The fourth transistor MN54 is connected between the source of the second transistor MN52 and the second current source IB52, and the first bias voltage Vb1 is applied to its gate.

[0046] The third resistor RS5X is connected between the connection node of the third transistor MN53 and the first current source IB51 (the source of the third transistor MN53) and the connection node of the fourth transistor MN54 and the second current source IB52 (i.e., the source of the fourth transistor MN54). Capacitor CS50 is connected in parallel with the third resistor RS5X between the source of the third transistor MN53 and the source of the fourth transistor MN54. Capacitor CS50 is also called a source-to-source capacitor.

[0047] The third resistor RS5X may be a variable resistor with a variable resistance value. Alternatively, the capacitance value of capacitor CS50 may be made variable instead of, or in addition to, the resistance value of the third resistor RS5X.

[0048] The above describes the configuration of the equalizer circuit 600.

[0049] In this configuration, the variable gain equalizer circuit 610 functions as a high-frequency boost filter through the combination of the third resistor RS5X and the capacitor CS50. Furthermore, by changing the first bias voltage Vb1, the gain of the variable gain equalizer circuit 610 can be changed, thus allowing it to function as a variable gain amplifier. Specifically, when the first bias voltage Vb1 increases, in other words, when the gate-source voltage between the third transistor MN53 and the fourth transistor MN54 increases, the gain of the variable gain equalizer circuit 610 increases. Conversely, when the first bias voltage Vb1 decreases, and the gate-source voltage between the third transistor MN53 and the fourth transistor MN54 decreases, the gain of the variable gain equalizer circuit 610 decreases. This gain is the overall gain including the DC component and is also referred to as the DC gain.

[0050] In other words, this configuration allows for both amplification and equalization of the input signal in a single stage. This reduces the circuit area and power consumption compared to configuring the amplifier and equalizer as separate stages, as shown in the comparative technique in Figure 1.

[0051] Furthermore, the configuration shown in Figure 2 can suppress excessive amplification of multi-level received waveforms, allowing for equalization while maintaining uniform multi-level levels.

[0052] Furthermore, by making the third resistor RS5X a variable resistor, the equalizing characteristics of the variable gain equalizer circuit 610 become adjustable.

[0053] Figure 3 is a circuit diagram of the variable gain equalizer circuit 610A according to Embodiment 1. The third resistor RS5X is a variable resistor having a digitally controllable resistance value according to the control signal CNT_EQ, and is composed of a combination of multiple resistors r and multiple switches sw. The topology of the multiple resistors and multiple switches is not particularly limited, and known techniques may be used.

[0054] In actual applications, a single-stage variable-gain equalizer circuit 610 may not provide sufficient gain or adequate equalization characteristics. In such cases, multiple variable-gain equalizer circuits 610 can be connected in multiple stages.

[0055] Figure 4 is a circuit diagram of the equalizer circuit 600A, which includes the variable gain equalizer circuit 610A shown in Figure 3. The equalizer circuit 600A comprises a plurality of variable gain equalizer circuits 610A_1 to 610A_N connected in series, and a first bias circuit 620. In this example, N=4.

[0056] In this configuration, the DC gain of the multiple variable gain equalizer circuits 610A_1 to 610A_N is controlled by a common first bias voltage Vb1, and therefore, the multiple variable gain equalizer circuits 610A_1 to 610A_N have the same DC gain.

[0057] Specifically, the first bias circuit 620 is provided in common to multiple variable gain equalizer circuits 610A_1 to 610A_N, and the same first bias voltage Vb1 is supplied to the multiple variable gain equalizer circuits 610A_1 to 610A_N.

[0058] On the other hand, in this configuration, the equalizer characteristics of the multiple variable gain equalizer circuits 610A_1 to 610A_N can be adjusted independently. Each variable gain equalizer circuit 610A_i (i=1,2,…N) includes a digitally controllable variable resistor RS5X as shown in Figure 3, and is supplied with an individual equalizer setting value CNT_EQi.

[0059] For example, the first bias circuit 620 may include a D / A converter 622 that converts a digital gain setting value CNT_DCGAIN into an analog first bias voltage Vb1.

[0060] Figure 5 is a circuit diagram showing an example configuration of a D / A converter 622 that functions as a first bias circuit 620. The D / A converter 622 includes an encoder 624, a current DAC (D / A converter) circuit 626, and an I / V conversion circuit 628. The encoder 624 encodes the set value CNT_DCGAIN, and the current DAC circuit 626 generates a current Idac corresponding to the output of the encoder 624. The I / V conversion circuit 628 converts the current Idac into a first bias voltage Vb1. The configuration of the D / A converter 622 is not particularly limited, and a resistor divider method may be used.

[0061] Figure 6 is a circuit diagram of the variable gain equalizer circuit 610B according to Embodiment 2. In this Embodiment 2, similar to Embodiment 1, the DC gain of the variable gain equalizer circuit 610B can be controlled according to the first bias voltage Vb1 supplied to the gates of transistors MN53 and MN54.

[0062] On the other hand, the resistance value of the third resistor RS5X can be controlled according to the second analog bias voltage Vb2.

[0063] The third resistor RS5X includes resistor RS50 and transistor MN50 connected in parallel. Transistor MN50 is N-channel and is connected between the source of the third transistor MN53 and the source of the fourth transistor MN54.

[0064] The above describes the configuration of the variable gain equalizer circuit 610B. Depending on the analog second bias voltage Vb2, the impedance of the fifth transistor MN50 changes, and the combined impedance of the third resistor RS5X changes. This allows the equalizer characteristics of the variable gain equalizer circuit 610B to be adjusted according to the second bias voltage Vb2.

[0065] Figure 7 is a circuit diagram of the equalizer circuit 600B, which includes the variable gain equalizer circuit 610B shown in Figure 6. The equalizer circuit 600B comprises multiple variable gain equalizer circuits 610B_1 to 610B_N connected in series, a first bias circuit 620, and a second bias circuit 630. In this example, N=4.

[0066] In this configuration, the DC gain of the multiple variable gain equalizer circuits 610B_1 to 610B_N is controlled by a common first bias voltage Vb1, and therefore, the multiple variable gain equalizer circuits 610B_1 to 610B_N have the same DC gain. This is the same as in Figure 4. Specifically, the first bias circuit 620 is provided in common for the multiple variable gain equalizer circuits 610B_1 to 610B_N, and the same first bias voltage Vb1 is supplied to the multiple variable gain equalizer circuits 610B_1 to 610B_N.

[0067] The equalizer characteristics of the multiple variable-gain equalizer circuits 610B_1 to 610B_N are similarly controlled by a common second bias voltage Vb2, and therefore, the multiple variable-gain equalizer circuits 610B_1 to 610B_N have the same equalizer characteristics. In this respect, it differs from Figure 4.

[0068] Specifically, the second bias circuit 630 is provided in common to multiple variable gain equalizer circuits 610B_1 to 610B_N, and the same second bias voltage Vb2 is supplied to all of them. For example, the second bias circuit 630 may include a D / A converter 632 that converts a digital equalizer setting value CNT_EQ into an analog second bias voltage Vb2. The D / A converter 632 can have the same configuration as the D / A converter 622, and can be configured as shown in Figure 5, for example.

[0069] (Application) Figure 8 is a block diagram of a transmission system 100 of an N-value PAM (PAM-N) signal according to an embodiment. The transmission system 100 comprises a transmitting device 200 and a receiving device (deserializer) 300. The transmitting device 200 and the receiving device 300 are connected via a transmission cable 102.

[0070] (Transmitter) The transmitting device 200 is a serializer IC (Integrated Circuit) that receives data S1 to be transmitted to the receiving device 300 from an external circuit (not shown), converts it into an N-value PAM signal S2, and transmits it to the receiving device 300. The type of parallel data S1 is not limited, but examples include image data that requires high-speed transmission of large amounts of data.

[0071] (Receiving device) The receiving device 300 is a deserializer IC that receives a PAM-N signal S2 from the transmitting device 200 and outputs the received data S3 to another external circuit (not shown). Differential signals are used for signal transmission between the transmitting device 200 and the receiving device 300, but single-ended signals may also be used.

[0072] Here, a 4-level (N=4) PAM (PAM4) signal is used as an example of a PAM-N signal, but the number of gradations in a PAM signal is not limited, and this disclosure can also be applied to 8-level, 16-level, and 64-level signals.

[0073] First, the configuration of the transmitting device 200 will be described. The PAM encoder 210 converts data S1a into PAM format data S1b. In the PAM encoder 210, a clock signal is embedded in data S1b. The encoding method in the PAM encoder 210 is not particularly limited, but DC balanced encoding methods such as 8b10b, 10b12b, and 64b66b can be used.

[0074] The P / S converter 220 converts the data S1b generated by the PAM encoder 210 into serial data S1c. The PAM driver 230 converts the serial data S1c into an analog PAM-N signal S2 and outputs it.

[0075] Next, the configuration of the receiving device 300 will be described. The receiving device 300 includes a waveform shaping circuit 310, an A / D converter 320, a PAM phase comparator 330, a clock recovery circuit 340, an S / P converter 350, and a PAM decoder 360.

[0076] While the PAM-N signal S2 is transmitted through the transmission cable 102, the waveform of the PAM-N signal S2 becomes distorted. A waveform shaping circuit 310 is provided to improve this waveform distortion. Examples of waveform distortion include attenuation due to transmission loss and waveform distortion due to the low-pass effect of the transmission cable 102. The waveform shaping circuit 310 shapes the waveform of the PAM-N signal S2 so that it approaches the ideal PAM signal.

[0077] The waveform shaping circuit 310 can be equipped with a VGA (Variable Gain Amplification) function that amplifies the PAM-N signal S2 with a variable gain and adjusts the DC amplitude of the PAM-N signal S2, as well as an equalizing (EQ) function that corrects the frequency characteristics of the PAM-N signal S2.

[0078] The A / D converter 320 quantizes the PAM-N signal S2a, which has been waveform-shaped by the waveform shaping circuit 310, and converts it into a comparison signal S2b.

[0079] The PAM phase comparator 330 receives the comparison signal S2b and, in synchronization with the clock signal CLK (data strobe signal) generated by the clock recovery circuit 340, latches the multiple bits b1 to b3 that make up the comparison signal S2b. The PAM phase comparator 330 converts the comparison signal S2b latched by the clock signal CLK into a 2-bit binary code (symbol data) S2c.

[0080] The S / P converter 350 converts the binary code S2c into parallel data S2e. The PAM decoder 360 performs the reverse processing with the PAM encoder 210 of the transmitter 200, decodes the DC-balanced encoded parallel data S2e, and outputs data S3.

[0081] The 610 (610A, 610B) according to the above-described embodiment can be used as a waveform shaping circuit 310.

[0082] (Note) The technology disclosed herein can be understood in one respect as follows:

[0083] (Item 1) A variable gain equalizer circuit, A first bias circuit that generates a first bias voltage, Equipped with, The variable gain equalizer circuit described above is: First input terminal and, Second input terminal and, A first transistor whose gate is connected to the first input terminal, The gate of the second transistor is connected to the second input terminal, A first resistor connected to the drain of the first transistor, A second resistor connected to the drain of the second transistor, First current source and, The second current source and A third transistor is connected between the source of the first transistor and the first current source, and the first bias voltage is applied to its gate. A fourth transistor is connected between the source of the second transistor and the second current source, and the first bias voltage is applied to its gate. A third resistor connected between the connection node of the third transistor and the first current source, and between the connection node of the fourth transistor and the second current source, A capacitor connected in parallel with the third resistor, An equalizer circuit equipped with [this feature].

[0084] (Item 2) The equalizer circuit described in item 1, wherein the resistance value of the third resistor is variable.

[0085] (Item 3) The equalizer circuit described in item 2, wherein the third resistor is composed of a combination of multiple resistors and multiple switches, and the resistance value of the third resistor is digitally controllable.

[0086] (Item 4) The aforementioned third resistor includes a fifth transistor, The equalizer circuit according to item 2, further comprising a second bias circuit that supplies a second bias voltage to the gate of the fifth transistor.

[0087] (Item 5) The variable gain equalizer circuit is an equalizer circuit described in any of items 1 to 4, wherein multiple circuits are connected in series.

[0088] (Item 6) Multiple of the aforementioned variable gain equalizer circuits are connected in series. The third resistor includes a field-effect transistor, The equalizer circuit according to item 2, further comprising a second bias circuit that supplies a common second bias voltage to the gates of the field-effect transistors constituting the third resistors of a plurality of the variable gain equalizer circuits.

[0089] (Item 7) An equalizer circuit according to any one of items 1 to 6, wherein the capacitance value of the capacitor is variable.

[0090] (Item 8) The first bias circuit described above is: A current D / A converter that converts a digital input to a current output with gradation, An I / V conversion circuit that converts the output current of at least one current D / A converter into the first bias voltage, An equalizer circuit, including any of the items 1 through 7.

[0091] (Item 9) The second bias circuit is, A current D / A converter that converts a digital input to a current output with gradation, An I / V conversion circuit that converts the output current of at least one current D / A converter into the second bias voltage, An equalizer circuit as described in item 4 or 6, including the one described in item 4 or 6.

[0092] (Item 10) An equalizer circuit described in any of items 1 to 9, which is integrated into a single semiconductor substrate.

[0093] While the embodiments described herein have been explained using specific terminology, this explanation is merely illustrative to aid understanding and does not limit the scope of this disclosure or the claims. The scope of the present invention is defined by the claims, and therefore embodiments, examples, and modifications not described herein are also included within the scope of the present invention. [Explanation of Symbols]

[0094] 600 Equalizer Circuit 610 Variable Gain Equalizer Circuit 620 First bias circuit 622 D / A Converter 630 Second bias circuit 632 D / A Converter MN51 First Transistor MN52 Second Transistor MN53 Third Transistor MN54 4th Transistor MN50 Fifth Transistor IB51 1st current source IB52 2nd current source CS50 Capacitor RD51 1st resistor RD52 2nd resistor RS5X 3rd Resistor 100 Transmission Systems 102 Transmission Cable 200 Transmitter Circuit 210 PAM encoder 220 P / S converter 230 PAM Driver 300 Receiver 310 Waveform shaping circuit 320 A / D converter 330 PAM phase comparator 340 Clock Recovery Circuit 350 S / P converter 360 PAM Decoder S2 Multi-value PAM signal

Claims

1. A variable gain equalizer circuit, A first bias circuit that generates a first bias voltage, Equipped with, The variable gain equalizer circuit described above is: First input terminal and, Second input terminal and A first transistor whose gate is connected to the first input terminal, The gate of the second transistor is connected to the second input terminal, A first resistor connected to the drain of the first transistor, A second resistor connected to the drain of the second transistor, First current source and The second current source and A third transistor is connected between the source of the first transistor and the first current source, and the first bias voltage is applied to its gate. A fourth transistor is connected between the source of the second transistor and the second current source, and the first bias voltage is applied to its gate. A third resistor connected between the connection node of the third transistor and the first current source, and between the connection node of the fourth transistor and the second current source, A capacitor connected in parallel with the third resistor, An equalizer circuit equipped with [this feature].

2. The equalizer circuit according to claim 1, wherein the resistance value of the third resistor is variable.

3. The equalizer circuit according to claim 2, wherein the third resistor is composed of a combination of a plurality of resistors and a plurality of switches, and the resistance value of the third resistor is digitally controllable.

4. The aforementioned third resistor includes the fifth transistor, The equalizer circuit according to claim 2, further comprising a second bias circuit that supplies a second bias voltage to the gate of the fifth transistor.

5. The equalizer circuit according to any one of claims 1 to 4, wherein a plurality of the variable gain equalizer circuits are connected in series.

6. Multiple of the aforementioned variable gain equalizer circuits are connected in series. The aforementioned third resistor includes a field-effect transistor, The equalizer circuit according to claim 2, further comprising a second bias circuit that supplies a common second bias voltage to the gates of the field-effect transistors constituting the third resistors of the plurality of variable gain equalizer circuits.

7. The equalizer circuit according to any one of claims 1 to 4, wherein the capacitance value of the capacitor is variable.

8. The first bias circuit is, A current D / A converter that converts a digital input to a current output with gradation, An I / V conversion circuit that converts the output current of at least one current D / A converter into the first bias voltage, An equalizer circuit according to any one of claims 1 to 4, including the following:

9. The second bias circuit is, A current D / A converter that converts a digital input to a current output with gradation, An I / V conversion circuit that converts the output current of at least one current D / A converter into the second bias voltage, The equalizer circuit according to claim 4 or 6, including the following:

10. An equalizer circuit according to any one of claims 1 to 4, which is integrated as a single semiconductor substrate.

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