Display substrate and display device

Abstract

The present invention belongs to the display field and relates to a display substrate and a display device. The display substrate includes a driving substrate, an anode layer, a pixel definition layer, a light-emitting functional layer, a cathode layer and a package layer, the driving circuit includes at least one transistor, the transistor includes a semiconductor layer, the semiconductor layer is at least partially located inside a base, the anode layer includes a plurality of anodes, the display substrate includes a plurality of pixel openings located on the side of the plurality of anodes away from the driving substrate, the plurality of pixel openings are configured to at least overlap with the plurality of anodes, each anode includes a body portion and a protrusion portion, the protrusion portion is connected to the body portion, the size of the protrusion portion in a direction perpendicular to the driving substrate is larger than the size of the body portion in a direction perpendicular to the driving substrate, the light-emitting functional layer includes a plurality of light-emitting portions, and the plurality of light-emitting portions are arranged in contact with the body portion of the plurality of anodes, so that the display substrate can reduce or avoid crosstalk between adjacent sub-pixels.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202210423991.9, filed on April 22, 2022, the entire contents of which are incorporated herein by reference.

[0002] The embodiments of the present disclosure relate to a display substrate and a display device. [Background technology]

[0003] With the continuous development of display technology, the Micro Organic Light-Emitting Diode (abbreviated as Micro-OLED) display device is a new type of OLED display device based on silicon substrate, also called silicon-based organic light-emitting diode (abbreviated as silicon-based OLED) display device. Silicon-based OLED display device has advantages such as small volume and high resolution, and is manufactured by CMOS integrated circuit process, which can realize active addressing of pixels. In addition, various functional circuits including TCON (timing control) circuit, OCP (operation control) circuit, etc. can be manufactured on the silicon base, which can realize weight reduction.

[0004] Micro OLED displays have excellent display characteristics such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption, and are therefore expected to have a bright future. Summary of the Invention [Means for solving the problem]

[0005] An embodiment of the present disclosure provides a display substrate and a display device, the display substrate includes a driving substrate, an anode layer, a pixel definition layer, a light-emitting functional layer, a cathode layer and a package layer, the driving substrate includes a base and a driving circuit, the anode layer is located on the driving substrate, the pixel definition layer is located on a side of the anode layer away from the driving substrate, the light-emitting functional layer is located on a side of the anode layer away from the driving substrate, the cathode layer is located on a side of the light-emitting functional layer away from the driving substrate, the package layer is located on a side of the cathode layer away from the driving substrate, the driving circuit includes at least one transistor, the transistor includes a semiconductor layer, the semiconductor layer is at least partially located in the base, and the anode The layer includes a plurality of anodes, the display substrate includes a plurality of pixel openings, the plurality of pixel openings are located in the pixel definition layer and are located on the side of the plurality of anodes away from the driving substrate, the plurality of pixel openings are configured to at least overlap with the plurality of anodes, each anode includes a body portion and a protrusion portion, the protrusion portion is provided on the periphery of the body portion, and the size of the protrusion portion in a direction perpendicular to the driving substrate is larger than the size of the body portion in a direction perpendicular to the driving substrate, the light-emitting functional layer includes a plurality of light-emitting portions, the plurality of light-emitting portions are located in the plurality of pixel openings and are provided in contact with the body portions of the plurality of anodes, so that the display substrate can effectively avoid leakage current and crosstalk between adjacent sub-pixels.

[0006] At least one embodiment of the present disclosure provides a display substrate, comprising: a driving substrate including a base and a driving circuit; a first planar layer located on the driving circuit; an anode layer located on a side of the first planar layer away from the driving substrate; a pixel definition layer located on a side of the anode layer away from the driving substrate; a light-emitting function layer located on a side of the anode layer away from the driving substrate; a cathode layer located on a side of the light-emitting function layer away from the driving substrate; and a package layer located on a side of the cathode layer away from the driving substrate, wherein the driving circuit includes at least one transistor, the transistor including a semiconductor layer, the semiconductor layer being at least partially located inside the base; the anode layer including a plurality of anodes; the display substrate includes a plurality of pixel openings, and the plurality of anodes are separated from the driving substrate. a first electrode disposed on the first side of the first flat layer and configured to overlap with the first electrode, the first electrode including a first body portion and a protrusion portion, the protrusion portion being connected to the first body portion, a size of the protrusion portion in a first direction being larger than a size of the first body portion in the first direction, the light-emitting functional layer including a plurality of light-emitting portions which are provided in contact with the first body portions of the plurality of anodes, a distance between the base and a surface of the first flat layer away from the base at the position of the body portion is equal to a distance between the base and a surface of the first flat layer away from the base at the position of the protrusion portion, and a distance between the base and a surface of the first flat layer away from the base is less than a distance between a surface of the protrusion portion away from the base and a surface of the first flat layer away from the base.

[0007] For example, in a display substrate according to an embodiment of the present disclosure, the protrusions are provided on the periphery of the main body.

[0008] For example, in a display substrate according to an embodiment of the present disclosure, the orthogonal projection of the pixel definition layer on the driving substrate overlaps with the orthogonal projection of the protrusion on the driving substrate.

[0009] For example, in a display substrate according to an embodiment of the present disclosure, the pixel definition layer includes a pixel definition portion, which includes a pixel definition flat portion located between two adjacent anodes and a protrusion structure located on the side of the protrusion portion of each of the two adjacent anodes away from the driving substrate, and the pixel definition flat portion connects the protrusion structures.

[0010] For example, in the display substrate according to the embodiment of the present disclosure, the pixel definition portions are provided symmetrically with respect to the center of the space between the two adjacent anodes.

[0011] For example, in a display substrate according to an embodiment of the present disclosure, each of the protrusion structures includes a first side wall located on a side of the protrusion structure closer to the center of the main body portion, and a second side wall connected to the first side wall and farther from the drive substrate than the first side wall, and a slope angle of the first side wall is greater than a slope angle of the second side wall.

[0012] For example, in a display substrate according to an embodiment of the present disclosure, the slope angle of the first sidewall ranges from 75 to 89 degrees, and the slope angle of the second sidewall ranges from 15 to 45 degrees.

[0013] For example, in a display substrate according to an embodiment of the present disclosure, each of the protrusion structures further includes a third sidewall located on a side of the protrusion structure adjacent to the pixel-defining flat portion, and a slope angle of the third sidewall is greater than a slope angle of the second sidewall and less than a slope angle of the first sidewall.

[0014] For example, in a display substrate according to an embodiment of the present disclosure, each of the protrusion structures further includes a third sidewall located on a side of the protrusion structure adjacent to the pixel-defining flat portion, wherein a slope angle of the first sidewall is α, a slope angle of the second sidewall is β, and a slope angle of the third sidewall is γ, satisfying Equation 1.

number

[0015] For example, in a display substrate according to an embodiment of the present disclosure, the difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to i times the slope angle of the third sidewall, where i ranges from 0.8 to 1.2.

[0016] For example, in a display substrate according to an embodiment of the present disclosure, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 2.

number

[0017] For example, in a display substrate according to an embodiment of the present disclosure, the difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to j times the difference between the slope angle of the second sidewall and the slope angle of the third sidewall, where j is in the range of 1.5-3.

[0018] For example, in a display substrate according to an embodiment of the present disclosure, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 3.

number

[0019] For example, in a display substrate according to an embodiment of the present disclosure, the sum of the slope angle of the first sidewall and the slope angle of the second sidewall is equal to k times the slope angle of the third sidewall, where k ranges from 2-3.

[0020] For example, in the display substrate according to the embodiment of the present disclosure, the slope angle of the third sidewall ranges from 45 to 60 degrees.

[0021] For example, in a display substrate according to an embodiment of the present disclosure, the size of the third side wall in the second direction of the orthogonal projection on the drive substrate is larger than the size of the second side wall in the second direction of the orthogonal projection on the drive substrate, the size of the second side wall in the second direction of the orthogonal projection on the drive substrate is larger than the size of the first side wall in the second direction of the orthogonal projection on the drive substrate, the second direction is a direction from the protrusion to the main body portion or a direction from the main body portion to the protrusion, and the second direction is parallel to a surface of the drive substrate away from the anode layer.

[0022] For example, in a display substrate according to an embodiment of the present disclosure, the size of the first side wall in the first direction is H1, the size of the second side wall in the first direction is H2, and the size of the third side wall in the first direction is H3, where H1, H2, and H3 satisfy Equation 4.

number

[0023] For example, in a display substrate according to an embodiment of the present disclosure, the protrusion of each anode includes a fourth side wall located on a side closer to the center of the main body of the protrusion, and the slope angle of the fourth side wall is greater than the slope angle of the second side wall and less than the slope angle of the first side wall.

[0024] For example, in a display substrate according to an embodiment of the present disclosure, the protrusion of each anode includes a fourth side wall located on a side closer to the center of the body of the protrusion, and the slope angle of the fourth side wall is δ, which satisfies Equation 5.

number

[0025] For example, in a display substrate according to an embodiment of the present disclosure, the protrusion portion of each anode includes a first sub-anode layer located on a side away from the base of the drive circuit, a second sub-anode layer located on a side of the first sub-anode layer away from the drive substrate, and a third sub-anode layer located on a side of the second sub-anode layer away from the drive substrate.

[0026] For example, in a display substrate according to an embodiment of the present disclosure, the size of the first sub-anode layer in the second direction is larger than the size of the third sub-anode layer in the second direction, the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction, the second direction is a direction from the protrusion to the main body portion or a direction from the main body portion to the protrusion, and the second direction is parallel to a surface of the driving substrate away from the anode layer.

[0027] For example, in a display substrate according to an embodiment of the present disclosure, an end of the first sub-anode layer away from the main body portion includes a ridge, and the thickness of the ridge in the first direction is greater than the average thickness of the first sub-anode layer in the first direction.

[0028] For example, in the display substrate according to the embodiment of the present disclosure, the end of the third sub-anode layer away from the main body portion is curved in a direction approaching the first sub-anode layer.

[0029] For example, in a display substrate according to an embodiment of the present disclosure, the protrusion portion of each of the anodes further includes a fourth sub-anode layer located between the second sub-anode layer and the third sub-anode layer, and the size of the fourth sub-anode layer in the second direction is less than the size of the second sub-anode layer in the second direction.

[0030] For example, in a display substrate according to an embodiment of the present disclosure, the size by which the third sub-anode layer exceeds the fourth sub-anode layer in the second direction is less than the size in the second direction of an overlapping area between the orthogonal projection of the pixel definition layer on the driving substrate and the orthogonal projection of the protrusion on the driving substrate.

[0031] For example, in a display substrate according to an embodiment of the present disclosure, the second sub-anode layer includes a fifth sidewall located on a side of the second sub-anode layer away from the main body portion, and the fourth sub-anode layer includes a sixth sidewall located on a side of the fourth sub-anode layer away from the main body portion, and a slope angle of the fifth sidewall is greater than a slope angle of the fourth sidewall, a slope angle of the sixth sidewall is greater than a slope angle of the fourth sidewall, and a slope angle of the fifth sidewall is greater than a slope angle of the sixth sidewall.

[0032] For example, in the display substrate according to the embodiment of the present disclosure, the ratio of the thickness of the first sub-anode layer in the first direction to the thickness of the second sub-anode layer in the first direction ranges from 1 / 15 to 1 / 5.

[0033] For example, in the display substrate according to the embodiment of the present disclosure, the ratio of the thickness of the first sub-anode layer in the first direction to the thickness of the third sub-anode layer in the first direction ranges from 1 / 3 to 4 / 5.

[0034] For example, in the display substrate according to the embodiment of the present disclosure, the range of the ratio of the thickness of the first sub-anode layer in the first direction to the thickness of the fourth sub-anode layer in the first direction is 1 / 24-1 / 8.

[0035] For example, in the display substrate according to the embodiment of the present disclosure, the range of the ratio between the distance between two adjacent anodes and the length of the orthogonal projection of the protrusions of the anodes on the driving substrate is 2-4.

[0036] For example, in the display substrate according to the embodiment of the present disclosure, the range of the ratio between the distance between two adjacent anodes and the length of the orthogonal projection of the protrusions of the anodes on the driving substrate is 2.5-3.5.

[0037] For example, in the display substrate according to the embodiment of the present disclosure, the protrusion portion is provided surrounding the main body portion.

[0038] For example, in a display substrate according to an embodiment of the present disclosure, the shape of the orthogonal projection of the anode on the driving substrate includes a hexagon.

[0039] For example, a display substrate according to an embodiment of the present disclosure further includes a reflective electrode layer located on a side of the first flat layer adjacent to the anode layer, and a second flat layer located on a side of the reflective electrode layer adjacent to the anode layer.

[0040] For example, in a display substrate according to an embodiment of the present disclosure, the reflective electrode layer is continuously disposed within the pixel opening.

[0041] For example, in a display substrate according to an embodiment of the present disclosure, a first pore is present between the light-emitting functional layer and the main body, and at least one second pore is present between the light-emitting functional layer and the pixel definition layer, and the space occupied by the first pore is larger than the space occupied by the second pore.

[0042] For example, in a display substrate according to an embodiment of the present disclosure, the packaging layer includes an inorganic packaging layer located on a side of the cathode layer away from the driving substrate, and the inorganic packaging layer includes a plurality of sub-inorganic packaging layers.

[0043] For example, in a display substrate according to an embodiment of the present disclosure, at least two adjacent sub-inorganic package layers among the plurality of sub-inorganic package layers are made of different materials, and at least two adjacent sub-inorganic package layers among the plurality of sub-inorganic package layers are made of the same material.

[0044] For example, in the display substrate according to the embodiment of the present disclosure, in the direction away from the driving substrate, the refractive indexes of the multiple sub-inorganic package layers increase and then decrease.

[0045] For example, in the display substrate according to the embodiment of the present disclosure, the thicknesses of the sub inorganic package layers in the first direction gradually decrease in a direction away from the driving substrate.

[0046] For example, in a display substrate according to an embodiment of the present disclosure, each of the sub-inorganic package layers includes alternating flat regions and double arch spacing regions, a first arch region located on a side of the flat region away from the double arch spacing region, a second arch region located between the flat region and the double arch spacing region, and a third arch region located on a side of the flat region away from the second arch region, and the first arch region and the second arch region are arranged symmetrically with respect to the center of the flat region.

[0047] For example, in a display substrate according to an embodiment of the present disclosure, the size of the flat region in the second direction is L, the distance in the second direction between the center of the second arch region and the center of the third arch region is a first distance D1, the distance in the second direction between the center of the first arch region and the center of the second arch region is a second distance D2, and the radii of curvature of the first arch region, the second arch region, and the third arch region are all R, The first distance D1 satisfies Equation 6, The second direction is a direction from the protrusion to the main body or a direction from the main body to the protrusion, and the second direction is parallel to a surface of the drive substrate away from the anode layer.

number

[0048] For example, in a display substrate according to an embodiment of the present disclosure, the size of the flat region in the second direction is L, the distance in the second direction between the center of the second arch region and the center of the third arch region is a first distance D1, the distance in the second direction between the center of the first arch region and the center of the second arch region is a second distance D2, and the radii of curvature of the first arch region, the second arch region, and the third arch region are all R, The first distance D1 satisfies Equation 7, The second direction is a direction from the protrusion to the main body or a direction from the main body to the protrusion, and the second direction is parallel to a surface of the drive substrate away from the anode layer.

number

[0049] For example, in a display substrate according to an embodiment of the present disclosure, the orthogonal projection of the first arch region, the second arch region or the third arch region on the drive substrate overlaps with the orthogonal projection of the protrusion portion on the drive substrate, the orthogonal projection of the flat region on the drive substrate overlaps with the orthogonal projection of the main body portion on the drive substrate, and the distance between the face of the first arch region, the second arch region or the third arch region facing away from the drive substrate and the drive substrate is greater than the distance between the face of the flat region facing away from the drive substrate and the drive substrate.

[0050] For example, in the display substrate according to the embodiment of the present disclosure, the orthogonal projection of the double arch spacing region on the driving substrate overlaps with the orthogonal projection of the spacing region between two adjacent anodes on the driving substrate.

[0051] For example, in a display substrate according to an embodiment of the present disclosure, the multiple sub-inorganic package layers include a first sub-inorganic package layer located on the side of the cathode layer away from the driving substrate, a second sub-inorganic package layer located on the side of the first sub-inorganic package layer away from the driving substrate, a third sub-inorganic package layer located on the side of the second sub-inorganic package layer away from the driving substrate, and a fourth sub-inorganic package layer located on the side of the third sub-inorganic package layer away from the driving substrate.

[0052] For example, in a display substrate according to an embodiment of the present disclosure, the refractive index of the first sub-inorganic packaging layer is less than the refractive index of the second sub-inorganic packaging layer, and the refractive index of the fourth sub-inorganic packaging layer is less than the refractive index of the third sub-inorganic packaging layer.

[0053] For example, in the display substrate according to the embodiment of the present disclosure, the refractive index of the second sub-inorganic package layer is equal to that of the third sub-inorganic package layer.

[0054] For example, in a display substrate according to an embodiment of the present disclosure, the flat region of the first sub-inorganic package layer has a first width in the second direction, the flat region of the second sub-inorganic package layer has a second width in the second direction, the flat region of the third sub-inorganic package layer has a third width in the second direction, and the flat region of the fourth sub-inorganic package layer has a fourth width in the second direction, wherein the first width is greater than the second width, the second width is greater than the third width, and the third width is greater than the fourth width.

[0055] For example, in a display substrate according to an embodiment of the present disclosure, an included angle between first connection lines of an edge of the flat region of the first sub-inorganic package layer adjacent to the first arch region, an edge of the flat region of the second sub-inorganic package layer adjacent to the first arch region, an edge of the flat region of the third sub-inorganic package layer adjacent to the first arch region, and an edge of the flat region of the fourth sub-inorganic package layer adjacent to the first arch region, and a surface away from the anode layer of the driving substrate is a first included angle, and an included angle between second connection lines of an apex of the first arch region of the first sub-inorganic package layer, an apex of the first arch region of the second sub-inorganic package layer, an apex of the first arch region of the third sub-inorganic package layer, and an apex of the first arch region of the fourth sub-inorganic package layer, and a surface away from the anode layer of the driving substrate is a second included angle, and the first included angle is less than the second included angle.

[0056] For example, in a display substrate according to an embodiment of the present disclosure, the first included angle ranges from 60-85 degrees, and the second included angle ranges from 85-89 degrees.

[0057] For example, in a display substrate according to an embodiment of the present disclosure, the intersection of the first connecting line and the second connecting line is located within the driving substrate.

[0058] For example, in a display substrate according to an embodiment of the present disclosure, the driving circuit includes a semiconductor layer located in the base, a first conductive layer located on the semiconductor layer, a second conductive layer located on a side of the first conductive layer away from the base, a third conductive layer located on a side of the second conductive layer away from the base, and a fourth conductive layer located on a side of the third conductive layer away from the base.

[0059] For example, in a display substrate according to an embodiment of the present disclosure, the intersection point between the first connecting line and the second connecting line is located between the upper surface of the third conductive layer away from the base and the anode layer.

[0060] For example, in a display substrate according to an embodiment of the present disclosure, the distance between the intersection of the first connecting line and the second connecting line and the vertex of the upper surface of the protrusion structure of the pixel definition layer away from the base is greater than the thickness of the first sub-inorganic package layer in the first direction.

[0061] For example, in a display substrate according to an embodiment of the present disclosure, the distance between the intersection of the first connecting line and the second connecting line and the vertex of the upper surface away from the base of the protrusion structure of the pixel definition layer is less than the sum of the thickness of the first sub-inorganic packaging layer in the first direction and the thickness of the second sub-inorganic packaging layer in the first direction.

[0062] For example, in a display substrate according to an embodiment of the present disclosure, an included angle between a third connection line and a surface away from the anode layer of the driving substrate, the third included angle being less than the second included angle, and between an edge of the second arch region of the first sub-inorganic package layer adjacent to the double arch spacing region, the edge of the second arch region of the second sub-inorganic package layer adjacent to the double arch spacing region, the edge of the second arch region of the third sub-inorganic package layer adjacent to the double arch spacing region, and the edge of the second arch region of the fourth sub-inorganic package layer adjacent to the double arch spacing region.

[0063] For example, in a display substrate according to an embodiment of the present disclosure, the intersection of the first connecting line and the third connecting line is located between an upper surface of the second conductive layer away from the base and a lower surface of the third conductive layer close to the base.

[0064] For example, in a display substrate according to an embodiment of the present disclosure, the intersection of the second connecting line and the third connecting line is located between a lower surface of the first conductive layer close to the base and a lower surface of the base away from the first conductive layer.

[0065] For example, in a display substrate according to an embodiment of the present disclosure, an included angle between a fourth connecting line and a surface of the driving substrate away from the anode layer, between an edge of the third arch region of the first sub-inorganic package layer away from the double arch spacing region, between an edge of the third arch region of the second sub-inorganic package layer away from the double arch spacing region, between an edge of the third arch region of the third sub-inorganic package layer away from the double arch spacing region, and between an edge of the third arch region of the fourth sub-inorganic package layer away from the double arch spacing region, is a fourth included angle, and the fourth included angle is less than the second included angle.

[0066] For example, in a display substrate according to an embodiment of the present disclosure, the intersection point between the first connecting line and the fourth connecting line is located on a side of the base away from the first conductive layer.

[0067] For example, in a display substrate according to an embodiment of the present disclosure, the intersection point between the third connecting line and the fourth connecting line is located on the side of the base away from the first conductive layer.

[0068] For example, in a display substrate according to an embodiment of the present disclosure, an upper surface of the first arch region of the first sub-inorganic package layer away from the base has a first radius of curvature, an upper surface of the first arch region of the second sub-inorganic package layer away from the base has a second radius of curvature, an upper surface of the first arch region of the third sub-inorganic package layer away from the base has a third radius of curvature, and an upper surface of the first arch region of the fourth sub-inorganic package layer away from the base has a fourth radius of curvature, wherein the first radius of curvature is less than the second radius of curvature, the second radius of curvature is less than the third radius of curvature, and the third radius of curvature is less than the fourth radius of curvature.

[0069] For example, in a display substrate according to an embodiment of the present disclosure, the dummy center of the first arch region of the fourth sub-inorganic packaging layer is located between an upper surface of the first sub-inorganic packaging layer away from the base and a lower surface of the fourth sub-inorganic packaging layer close to the base.

[0070] For example, in a display substrate according to an embodiment of the present disclosure, the first sub-inorganic packaging layer has a first thickness in the first direction, the second sub-inorganic packaging layer has a second thickness in the first direction, the third sub-inorganic packaging layer has a third thickness in the first direction, and the fourth sub-inorganic packaging layer has a fourth thickness in the first direction, wherein the first thickness is greater than the second thickness, the second thickness is greater than the third thickness, and the third thickness is greater than the fourth thickness.

[0071] For example, in the display substrate according to the embodiment of the present disclosure, the ratio of the difference between the first thickness and the second thickness to the difference between the third thickness and the fourth thickness ranges from 1.5 to 2 times.

[0072] For example, in a display substrate according to an embodiment of the present disclosure, the ratio of the sum of the second thickness and the third thickness to the first thickness ranges from 0.8 to 1.2.

[0073] For example, in a display substrate according to an embodiment of the present disclosure, the first thickness range is 1000-1200 nanometers, the second thickness range is 500-660 nanometers, the third thickness range is 480-560 nanometers, and the fourth thickness range is 180-260 nanometers.

[0074] For example, in a display substrate according to an embodiment of the present disclosure, the material of the first sub-inorganic packaging layer includes silicon oxide and silicon oxynitride, the material of the second sub-inorganic packaging layer includes silicon nitride, the material of the third sub-inorganic packaging layer includes silicon nitride, and the material of the fourth sub-inorganic packaging layer includes silicon oxide.

[0075] For example, in a display substrate according to an embodiment of the present disclosure, the packaging layer further includes an organic packaging layer located on a side of the inorganic packaging layer away from the driving substrate, the organic packaging layer including a first region, a second region and a third region, the average thickness of the first region being less than the average thickness of the second region, and the average thickness of the second region being less than the average thickness of the third region.

[0076] For example, the display substrate according to an embodiment of the present disclosure further includes a color film layer located on a side of the package layer away from the driving substrate, the color film layer including a first color filter, a second color filter and a third color filter.

[0077] For example, in a display substrate according to an embodiment of the present disclosure, the first color filter and the second color filter have a first overlapping area, the second color filter and the third color filter have a second overlapping area, and the third color filter and the first color filter have a third overlapping area.

[0078] For example, in the display substrate according to the embodiment of the present disclosure, the orthogonal projections of the first overlapping region, the second overlapping region, and the third overlapping region on the driving substrate overlap with the orthogonal projections of the protrusions on the driving substrate.

[0079] For example, in a display substrate according to an embodiment of the present disclosure, the orthogonal projections of the first overlapping region, the second overlapping region, and the third overlapping region on the driving substrate overlap with the orthogonal projections of the gap region between two adjacent anodes on the driving substrate.

[0080] For example, in a display substrate according to an embodiment of the present disclosure, the size of the first overlapping region in the second direction is larger than the size of the second overlapping region in the second direction, and the size of the second overlapping region in the second direction is larger than the size of the third overlapping region in the second direction.

[0081] For example, in a display substrate according to an embodiment of the present disclosure, the first overlapping region has a size range in the second direction of 400-600 nanometers, the second overlapping region has a size range in the second direction of 250-350 nanometers, and the third overlapping region has a size range in the second direction of 100-200 nanometers.

[0082] For example, in a display substrate according to an embodiment of the present disclosure, the average size of the first color filter in the first direction is larger than the average size of the second color filter in the first direction and smaller than the average size of the third color filter in the first direction.

[0083] For example, in a display substrate according to an embodiment of the present disclosure, the first color filter has an average size range of 2.3-2.6 microns in the first direction, the second color filter has an average size range of 1.7-1.95 microns in the first direction, and the third color filter has an average size range of 2.3-2.7 microns in the first direction.

[0084] For example, in a display substrate according to an embodiment of the present disclosure, the range of the ratio of the difference between the average size of the first color filter in the first direction and the average size of the second color filter in the first direction to the difference between the average size of the first color filter in the first direction and the average size of the third color filter in the first direction is 2-3.

[0085] For example, in a display substrate according to an embodiment of the present disclosure, the first color filter includes a first edge portion, a second edge portion, and an intermediate portion located between the first edge portion and the second edge portion, and the average size of the intermediate portion in the first direction is less than the average size of the first edge portion in the first direction and the average size of the second edge portion in the first direction.

[0086] For example, in a display substrate according to an embodiment of the present disclosure, the first color filter includes a first contact surface in contact with the second color filter, the second color filter includes a second contact surface in contact with the third color filter, and the third color filter includes a third contact surface in contact with the first color filter, and a size of the first contact surface in a first direction perpendicular to the driving substrate is equal to a size of the second contact surface in the first direction and is less than a size of the third contact surface in the first direction.

[0087] For example, in a display substrate according to an embodiment of the present disclosure, the distance between the first color filter and the surface of the driving substrate away from the anode layer is greater than the distance between the third color filter and the surface of the driving substrate away from the anode layer, and is less than the distance between the second color filter and the surface of the driving substrate away from the anode layer.

[0088] For example, in a display substrate according to an embodiment of the present disclosure, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter.

[0089] For example, in the display substrate according to the embodiment of the present disclosure, the material of the color film layer includes a desiccant.

[0090] For example, in the display substrate according to the embodiment of the present disclosure, the color film layer contains aluminum element.

[0091] For example, the display substrate according to an embodiment of the present disclosure further includes a protective layer located on the side of the color film layer away from the driving substrate.

[0092] For example, in the display substrate according to the embodiment of the present disclosure, the color film layer further includes a black matrix located between any two adjacent ones of the first color filter, the second color filter, and the third color filter.

[0093] For example, a display substrate according to an embodiment of the present disclosure further includes a glass cover plate located on the side of the color film layer away from the driving substrate.

[0094] At least one embodiment of the present disclosure further provides a display device including the display substrate according to any one of the preceding claims.

[0095] At least one embodiment of the present disclosure further provides another display device including the display substrate according to any one of the above aspects.

[0096] For example, a display device according to an embodiment of the present disclosure further includes an opposing substrate arranged opposite the display substrate, the opposing substrate including a glass cover plate and a color film layer positioned on the glass cover plate, and the color film layer including a first color filter, a second color filter and a third color filter.

[0097] For example, in a display device according to an embodiment of the present disclosure, the first color filter and the second color filter have a first overlapping area, the second color filter and the third color filter have a second overlapping area, and the third color filter and the first color filter have a third overlapping area.

[0098] For example, in a display device according to an embodiment of the present disclosure, the orthogonal projections of the first overlapping region, the second overlapping region, and the third overlapping region on the drive substrate overlap with the orthogonal projection of the protrusion on the drive substrate.

[0099] For example, in a display device according to an embodiment of the present disclosure, the orthogonal projections of the first overlapping region, the second overlapping region, and the third overlapping region on the driving substrate overlap with the orthogonal projections of the gap region between two adjacent anodes on the driving substrate.

[0100] For example, in a display device according to an embodiment of the present disclosure, the size of the first overlapping area in the second direction is larger than the size of the second overlapping area in the second direction, and the size of the second overlapping area in the second direction is larger than the size of the third overlapping area in the second direction.

[0101] For example, in a display device according to an embodiment of the present disclosure, the first overlapping region has a size range in the second direction of 400-600 nanometers, the second overlapping region has a size range in the second direction of 250-350 nanometers, and the third overlapping region has a size range in the second direction of 100-200 nanometers.

[0102] For example, in a display device according to an embodiment of the present disclosure, the average size of the first color filter in the first direction is larger than the average size of the second color filter in the first direction and smaller than the average size of the third color filter in the first direction.

[0103] For example, in a display device according to an embodiment of the present disclosure, the first color filter has an average size range of 2.3-2.6 microns in the first direction, the second color filter has an average size range of 1.7-1.95 microns in the first direction, and the third color filter has an average size range of 2.3-2.7 microns in the first direction.

[0104] For example, in a display device according to an embodiment of the present disclosure, the range of the ratio of the difference between the average size of the first color filter in the first direction and the average size of the second color filter in the first direction to the difference between the average size of the first color filter in the first direction and the average size of the third color filter in the first direction is 2-3.

[0105] For example, in a display device according to an embodiment of the present disclosure, the first color filter includes a first edge portion, a second edge portion, and an intermediate portion located between the first edge portion and the second edge portion, and the average size of the intermediate portion in the first direction is less than the average size of the first edge portion in the first direction and the average size of the second edge portion in the first direction.

[0106] For example, in a display device according to an embodiment of the present disclosure, the first color filter includes a first contact surface in contact with the second color filter, the second color filter includes a second contact surface in contact with the third color filter, and the third color filter includes a third contact surface in contact with the first color filter, and the size of the first contact surface in a second direction perpendicular to the driving substrate is equal to the size of the second contact surface in the second direction and is less than the size of the third contact surface in the second direction.

[0107] For example, in a display device according to an embodiment of the present disclosure, the distance between the first color filter and the surface of the driving substrate away from the anode layer is greater than the distance between the third color filter and the surface of the driving substrate away from the anode layer, and is less than the distance between the second color filter and the surface of the driving substrate away from the anode layer.

[0108] For example, in a display device according to an embodiment of the present disclosure, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter.

[0109] For example, in a display device according to an embodiment of the present disclosure, the material of the color film layer includes a desiccant.

[0110] For example, in the display device according to the embodiment of the present disclosure, the color film layer contains aluminum element.

[0111] For example, in the display device according to the embodiment of the present disclosure, the color film layer further includes a black matrix located between any two adjacent ones of the first color filter, the second color filter, and the third color filter.

[0112] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. It is obvious that the drawings described below only relate to some embodiments of the present disclosure, but do not limit the present disclosure. [Brief description of the drawings]

[0113] [Figure 1] FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Figure 4A] FIG. 4A is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. [Figure 6]FIG. 6 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic diagram of a first color filter of a display substrate according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a structural schematic diagram of a driving substrate according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic diagram of a display device according to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a plan view of a display device according to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic diagram of another display device according to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 18] FIG. 18 is an equivalent schematic diagram of a driving circuit of a display substrate according to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a schematic plan view of a drive circuit of a display substrate according to an embodiment of the present disclosure. [Figure 20A] 20A to 20E are plan views of the layout of each layer of the display substrate shown in FIG. [Figure 20B] 20A to 20E are plan views of the layout of each layer of the display substrate shown in FIG. [Figure 20C] 20A to 20E are plan views of the layout of each layer of the display substrate shown in FIG. [Figure 20D]20A to 20E are plan views of the layout of each layer of the display substrate shown in FIG. [Figure 20E] 20A to 20E are plan views of the layout of each layer of the display substrate shown in FIG. [Figure 21] FIG. 21 is a schematic diagram of an area for providing a storage capacitor on a display substrate according to an embodiment of the present disclosure. [Figure 22] FIG. 22 is a layout diagram of a storage capacitor of a display substrate according to an embodiment of the present disclosure. [Figure 23A] 23A-23D are plan views of the layout of each layer in FIG. [Figure 23B] 23A-23D are plan views of the layout of each layer in FIG. [Figure 23C] 23A-23D are plan views of the layout of each layer in FIG. [Figure 23D] 23A-23D are plan views of the layout of each layer in FIG. [Figure 23E] FIG. 23E is a schematic cross-sectional view of a storage capacitor of a display substrate according to an embodiment of the present disclosure. [Figure 24A] FIG. 24A is a block diagram of a display substrate according to an embodiment of the present disclosure. [Figure 24B] FIG. 24B is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. [Figure 24C] FIG. 24C is a schematic diagram showing the latch-up effect occurring in the pixel circuit. [Figure 25A] FIG. 25A is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure. [Figure 25B] FIG. 25B is a circuit diagram of a specific embodiment of the pixel circuit shown in FIG. 24A. [Figure 25C] FIG. 25C is a signal timing diagram of the pixel circuit shown in FIG. 25B. [Figure 26A] FIG. 26A is a schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 26B] FIG. 26B is a cross-sectional view taken along line II' of FIG. 26A. [Figure 27A] FIG. 27A is a schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 27B] FIG. 27B is a schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 28A] 28A-28E show the process of forming the substrate structure shown in FIG. 27A. [Figure 28B] 28A-28E show the process of forming the substrate structure shown in FIG. 27A. [Figure 28C] 28A-28E show the process of forming the substrate structure shown in FIG. 27A. [Figure 28D] 28A-28E show the process of forming the substrate structure shown in FIG. 27A. [Figure 28E] 28A-28E show the process of forming the substrate structure shown in FIG. 27A. [Figure 29A] 29A-29C are schematic diagrams illustrating a process for forming a display substrate according to an embodiment of the present disclosure. [Figure 29B] 29A-29C are schematic diagrams illustrating a process for forming a display substrate according to an embodiment of the present disclosure. [Figure 29C] 29A-29C are schematic diagrams illustrating a process for forming a display substrate according to an embodiment of the present disclosure. [Figure 30A] FIG. 30A is a schematic diagram of a second conductive layer of a display substrate according to an embodiment of the present disclosure. [Figure 30B] FIG. 30B is a schematic diagram of the first conductive layer and the second conductive layer of the display substrate according to an embodiment of the present disclosure. [Figure 31A] FIG. 31A is a schematic diagram of a third conductive layer of a display substrate according to an embodiment of the present disclosure. [Figure 31B] FIG. 31B is a schematic diagram of the second conductive layer and the third conductive layer of the display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0114] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments that a person skilled in the art can obtain without creative labor belong to the protection scope of the present disclosure.

[0115] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning understood by those skilled in the art. The words "first", "second" and similar words used in this disclosure do not indicate order, number or importance, but are merely used to distinguish different components. Similar words such as "comprise" or "include" mean that the element or item appearing after the word covers the element or item listed before the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0116] Conventional large-sized organic light-emitting diode (OLED) displays reduce leakage current and crosstalk by insulating the anode. However, in micro-OLED displays, leakage current and crosstalk can be reduced by similar means, but the pixel definition layer of the micro-OLED display is thin and the pixel density is high, so the light-emitting layer cannot be completely insulated by the same means alone, and leakage current and crosstalk still exist.

[0117] In view of this, an embodiment of the present disclosure provides a display substrate and a display device, the display substrate includes a driving substrate, an anode layer, a pixel definition layer, a light-emitting functional layer, a cathode layer and a package layer, the driving substrate includes a base and a driving circuit, the anode layer is located on the driving substrate, the pixel definition layer is located on a side of the anode layer away from the driving substrate, the light-emitting functional layer is located on a side of the anode layer away from the driving substrate, the cathode layer is located on a side of the light-emitting functional layer away from the driving substrate, the package layer is located on a side of the cathode layer away from the driving substrate, the driving circuit includes at least one transistor, the transistor includes a semiconductor layer, the semiconductor layer is at least partially located inside the base, the anode layer includes a plurality of anodes, the display substrate includes a plurality of pixel openings and is located on a side of the plurality of anodes away from the driving substrate, the plurality of pixel openings are configured to at least overlap the plurality of anodes, the light-emitting functional layer includes a plurality of light-emitting parts, the plurality of light-emitting parts are arranged in contact with exposed parts of the plurality of anodes. Each anode includes a body and a protrusion, the protrusion is connected to the body, and the size of the protrusion in a first direction perpendicular to the driving substrate is larger than the size of the body in the first direction perpendicular to the driving substrate, so that the display substrate can provide a micro display substrate, and the silicon-based circuit substrate can be used as the driving substrate to drive the light-emitting functional layer to perform light emission display, and crosstalk between adjacent sub-pixels can be further reduced or avoided.

[0118] Hereinafter, a display substrate and a display device according to an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0119] An embodiment of the present disclosure provides a display substrate, Fig. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure, and Fig. 2 is a schematic partial structural view of another display substrate according to an embodiment of the present disclosure.

[0120] 1 and 2, the display substrate 500 includes a driving substrate 510, an anode layer 520, a pixel definition layer 530, a light-emitting functional layer 540, a cathode layer 550 and a package layer 560, the driving substrate 510 includes a base 512 and a driving circuit 514, the anode layer 520 is located on the driving substrate 510, the pixel definition layer 530 is located on the side of the anode layer 520 away from the driving substrate 510, the light-emitting functional layer 540 is located on the side of the anode layer 520 away from the driving substrate 510, the cathode layer 550 is located on the side of the light-emitting functional layer 540 away from the driving substrate 510, the package layer 560 is located on the side of the cathode layer 550 away from the driving substrate 510, the driving circuit 514 includes at least one transistor T, the transistor T includes a semiconductor layer 102, and the semiconductor layer 102 is at least partially located inside the base 512. That is, a part of the base 512 can function as a semiconductor layer. It should be noted that Figures 1 and 2 do not show all the structures of the driving circuit, and the driving circuit may include structures such as transistors, memory capacitors, current limiting resistors, and voltage dividing resistors. The specific circuit structure of the driving circuit can be set according to actual needs, and is not limited thereto in the embodiments of the present disclosure.

[0121] For example, the driving substrate 510 may be a silicon-based circuit substrate, which is advantageous for manufacturing a micro display device due to the mature semiconductor manufacturing process used for the silicon-based circuit substrate, its stable performance, small size, and high precision. Of course, the embodiment of the present disclosure is not limited thereto, and the driving substrate may use other types of driving substrates.

[0122] 1 and 2, the anode layer 520 includes a plurality of anodes 525, the display substrate 500 includes a plurality of pixel openings 535, the plurality of pixel openings 535 are located in the film layer where the pixel definition layer 530 is located and are surrounded by the pixel definition layer 530, the plurality of pixel openings 535 are located on the side of the plurality of anodes 525 away from the driving substrate 510, the plurality of pixel openings 535 are configured to at least overlap with the plurality of anodes 525, and the light-emitting functional layer 540 includes a plurality of light-emitting portions 545, the plurality of light-emitting portions 545 are at least partially located in the plurality of pixel openings 535 and are provided in contact with the exposed portions of the plurality of anodes 525. Thus, the plurality of anodes can drive the plurality of light-emitting portions to perform light-emitting display.

[0123] In the display substrate according to the embodiment of the present disclosure, the driving substrate can be manufactured by a semiconductor manufacturing process, so that a pixel driving circuit for driving each pixel to emit light and display can be integrated into the driving substrate, so that the display substrate can provide a micro display substrate, which has the advantages of high resolution, high brightness, rich colors, low driving voltage, fast response speed, low power consumption and the like.

[0124] 1 and 2, the multiple anodes 525 are provided in one-to-one correspondence with the multiple pixel openings 535, and the multiple pixel openings 535 are provided in one-to-one correspondence with the multiple light-emitting units 545. Note that the above "provided in one-to-one correspondence" means that one pixel opening is provided on one anode, one light-emitting unit is provided in one pixel opening, and the orthogonal projection of the anode on the drive substrate at least partially overlaps with the orthogonal projection of the corresponding pixel opening on the drive substrate, and the orthogonal projection of the pixel opening on the drive substrate at least partially overlaps with the orthogonal projection of the light-emitting unit on the drive substrate. Of course, the embodiments of the present disclosure are not limited thereto.

[0125] In some examples, as shown in FIG. 2 , the display substrate 100 further includes a first planar layer 591, a second planar layer 592 and a reflective electrode layer 593, where the first planar layer 591 is located between the driving circuit 514 and the anode layer 520, the reflective electrode layer 593 is located on the side of the first planar layer 591 adjacent to the anode layer 520, and the second planar layer 592 is located on the side of the reflective electrode layer 593 adjacent to the anode layer 520.

[0126] In some examples, the reflective electrode layer 593 is disposed continuously within the pixel aperture 535, as shown in FIG.

[0127] 1 and 2, the display substrate further includes a color film layer 570 located on the side of the package layer 560 away from the driving substrate 510. When the light-emitting functional layer is configured to emit white light, the color film layer may include a number of color filters to achieve a color display. Of course, the embodiments of the present disclosure are not limited thereto, and the light-emitting functional layer may be configured to directly emit light of different colors.

[0128] 1 and 2, the display substrate 500 further includes a protective layer 580 located on the side of the color film layer 570 away from the driving substrate 510. The protective layer 580 can achieve the effect of protecting the color film layer 570, thereby stabilizing the filtering performance of the color film layer 570 during long-term use, and thereby improving the display quality of the display substrate.

[0129] In some examples, as shown in FIGS. 1 and 2, the display substrate 500 further includes a glass cover plate 590 located on the side of the color film layer 570 away from the driver substrate 510 .

[0130] Fig. 3 is a schematic diagram of a part of a structure of another display substrate according to an embodiment of the present disclosure. Fig. 4A is a schematic diagram of a part of a structure of another display substrate according to an embodiment of the present disclosure. As shown in Fig. 3 and Fig. 4A, the display substrate shown in Fig. 3 does not show a light-emitting functional layer, and the display substrate shown in Fig. 4A shows a light-emitting functional layer.

[0131] As shown in FIG. 3 and FIG. 4A, each anode 525 includes a main body 525A and a protrusion 525B, the protrusion 525B is connected to the main body 525A, and the size of the protrusion 525B in the first direction is larger than the size of the main body 525A in the first direction, that is, the thickness of the protrusion 525B is larger than the thickness of the main body 525A. The distance between the face of the first flat layer 591 away from the base 512 at the position of the main body 525A and the base 512 is equal to the distance between the face of the first flat layer 591 away from the base 512 at the position of the protrusion 525B and the base 512, and the distance between the face of the main body 525A away from the base 512 and the face of the first flat layer 591 away from the base 512 is less than the distance between the face of the protrusion 525B away from the base 512 and the face of the first flat layer 591 away from the base 512. The first direction may be perpendicular to the drive substrate.

[0132] In the display substrate according to this embodiment, the size of the protrusion 525B in the direction perpendicular to the driving substrate 510 is larger than the size of the body 525A in the direction perpendicular to the driving substrate 510, so that the pixel definition layer 530 located between the two anodes 525 and overlapping the edge portion of the anode 525 can form a protrusion structure 532 corresponding to the protrusion 525. Thus, when forming the light-emitting functional layer 540, at least some of the sub-functional layers (e.g., charge generation layers) of the light-emitting functional layer 540 can be better cut at the position of the protrusion structure 532, that is, at least some of the sub-functional layers of the light-emitting parts 545 corresponding to the two adjacent anodes 525 are not connected, so that the leakage current or crosstalk between adjacent sub-pixels can be effectively avoided. Meanwhile, at this time, the height of the protrusion structure 532 of the pixel definition layer 530 is also higher, so that the effect of pixel definition can be better exerted, and the crosstalk between adjacent sub-pixels can be optically reduced or avoided.

[0133] In some examples, as shown in Figures 3 and 4A, each anode 525 includes a main body portion 525A and a protrusion portion 525B, and the protrusion portion 525B is provided around the periphery of the main body portion 525A, thereby allowing at least a portion of the functional layer of the light-emitting functional layer 540 to be better cut off by the edge of the main body portion 525A.

[0134] 3 and 4A, an orthogonal projection of the pixel definition layer 530 on the drive substrate 510 overlaps with an orthogonal projection of the protrusion 525B on the drive substrate 510. This allows the pixel definition layer 530 to form a protrusion structure 532 that corresponds to the protrusion 525 and is located on the side of the protrusion 525 that is away from the drive substrate 510.

[0135] In some examples, as shown in Figures 3 and 4A, the pixel defining layer 530 includes a pixel defining portion 530A, which includes a pixel defining flat portion 534 and two protrusion structures 532 located on both sides of the pixel defining flat portion 534, the pixel defining flat portion 534 is located between two adjacent anodes 525, the two protrusion structures 532 are respectively located on the sides away from the driving substrate 510 of the two protrusion portions 525B of the two adjacent anodes 525, and the pixel defining flat portion 534 connects the two protrusion structures 532. In other words, the pixel definition portion 530A includes a portion located between two adjacent anodes 525 and a portion overlapping the two anodes 525, and the portion between the two adjacent anodes 525 is flat, but the above-mentioned protrusion portion 525B is provided at the edge portion of the anode 525, so that the portion located between the two adjacent anodes 525 is formed as the above-mentioned pixel definition flat portion 534, but the portion overlapping with the two anodes 525 is formed as the above-mentioned protrusion structure 532.

[0136] In the display substrate according to this embodiment, when the light-emitting functional layer 540 is formed, due to the existence of the pixel definition portion 530A, at least some of the sub-functional layers (e.g., charge generation layers) of the light-emitting functional layer 540 can be better cut at the position of the protrusion structure 532, that is, at least some of the sub-functional layers of the light-emitting portion 545 corresponding to two adjacent anodes 525 are not connected, thereby effectively avoiding leakage or crosstalk between adjacent sub-pixels. Meanwhile, at this time, the height of the protrusion structure 532 is also increased, thereby better exerting the effect of pixel definition and optically reducing or avoiding crosstalk between adjacent sub-pixels.

[0137] 3 and 4A, pixel defining portion 530A is provided symmetrically with respect to the center of space region 522 between two adjacent anodes 525. Note that, because the two portions of the pixel defining portion on both sides of the center of the space region between two adjacent anodes may differ due to the presence of process errors, cases in which the pixel defining portion is provided symmetrically with respect to the center of the space region between two adjacent anodes include cases in which the overlap rate of the two portions of the pixel defining portion on both sides of the center of the space region between two adjacent anodes reaches 80%.

[0138] In some examples, as shown in Figures 3 and 4A, each protruding structure 532 includes a first side wall 532A and a second side wall 532B, the first side wall 532A is located on a side of the protruding structure 532 close to the center of the body part 525A of the anode 525, and the second side wall 532B is connected to the first side wall 532A and located on a side of the first side wall 532A away from the driving substrate 510, that is, the second side wall 532B is farther away from the driving substrate 510 than the first side wall 532A, and the slope angle of the first side wall 532A is larger than the slope angle of the second side wall 532B. Note that, since the first side wall or the second side wall is not a standard plane in an actual process, the above slope angle may be the slope angle of the connecting line of two end points of the first side wall or the second side wall.

[0139] In the display substrate according to this embodiment, in the process of forming the light-emitting functional layer, the slope angle of the first sidewall is larger than that of the second sidewall, and the first sidewall is steep due to the large slope angle, so that at least some sub-functional layers (e.g., charge generation layers) of the light-emitting functional layer can be better cut at the position of the first sidewall. Meanwhile, the slope angle of the second sidewall is smaller than that of the first sidewall, so that a gentle platform can be formed, and the second sidewall can play a role in guiding the material of the light-emitting functional layer, so that the light-emitting functional layer forms a poor adhesion area at the portion of the anode exposed by the pixel opening and the position adjacent to the protrusion structure, thereby reducing the luminance of the light-emitting functional layer at the portion of the anode exposed by the pixel opening and the position adjacent to the protrusion structure. Thus, the display substrate according to this embodiment can further reduce the crosstalk between adjacent sub-pixels.

[0140] In some examples, as shown in Fig. 4A, a first pore 5471 is present between the light-emitting functional layer 540 and the body 525A, and at least one second pore 5472 is present between the light-emitting functional layer 540 and the pixel defining layer 530, and the space occupied by the first pore 5471 is larger than the space occupied by the second pore 5472. As a result, the first pore 5471 and the second pore 5472 form a weakly conductive region in the common layer that transmits carriers laterally, which contributes to reducing lateral crosstalk of light. Of course, the embodiments of the present disclosure are not limited thereto, and the second pores may not be formed in the light-emitting functional layer and the pixel defining layer.

[0141] 4B is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure, as shown in FIG 4B, the light-emitting functional layer 540 and the pixel definition layer 530 are in close contact with each other.

[0142] In some examples, as shown in Figures 3 and 4A, the protrusion structure 532 further includes a third sidewall 532C located on the side away from the body portion 525A of the protrusion structure 532, and the slope angle of the third sidewall 532C is greater than the slope angle of the second sidewall 532B and less than the slope angle of the first sidewall 532A. This makes the slope angle of the third sidewall gentle, thereby reducing or avoiding the formation of pores in the light-emitting functional layer subsequently formed on the third sidewall, and further avoiding the formation of channels through which water or oxygen can invade. Meanwhile, the slope angle of the third sidewall is gentle, so that the pixel definition portion can easily form a complete integral structure, and peeling phenomenon is avoided on the third sidewall.

[0143] 3 and 4A, each protruding structure 532 further includes a third side wall 532C, which is located on a side of the protruding structure 532 away from the main body portion 525A. In this case, the slope angle of the first side wall 532A is α, the slope angle of the second side wall 532B is β, and the slope angle of the third side wall 532C is γ, which satisfies Equation 1.

number

[0144] In the display substrate according to this embodiment, the gradient angle γ of the third side wall 532C is gentler than the gradient angle α of the first side wall 532A, thereby reducing or avoiding the formation of pores in the light-emitting functional layer subsequently formed on the third side wall 532C, and further avoiding the formation of passages through which water or oxygen can penetrate. Meanwhile, since the gradient angle γ of the third side wall 532C is gentle, the pixel definition part can easily form a complete integral structure, and the peeling phenomenon is avoided from occurring on the third side wall. Meanwhile, since the gradient angle γ of the third side wall 532C is larger than the gradient angle β of the second side wall 532B, it is possible to avoid the protrusion structure occupying a large area, and thus to avoid the loss of aperture ratio.

[0145] In some examples, as shown in Figures 3 and 4A, the difference between the slope angle of the first sidewall 532A and the slope angle of the second sidewall 532B is equal to i times the slope angle of the third sidewall, where i ranges from 0.8 to 1.2, so that the protrusion structure can better achieve the effects of preventing crosstalk between the adjacent sub-pixels, preventing the intrusion of water or oxygen, and preventing the peeling phenomenon of the pixel defining portion.

[0146] In some examples, as shown in FIGS. 3 and 4A, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 2.

number

[0147] In the display substrate of this example, the slope angle α of the first side wall, the slope angle β of the second side wall, and the slope angle γ of the third side wall satisfy the relationship restricted by the above formula 2, so that the protrusion structure can better achieve the effects of preventing crosstalk between the adjacent sub-pixels, preventing the intrusion of water and oxygen, and preventing the peeling phenomenon of the pixel definition portion.

[0148] 3 and 4A, the difference between the slope angle of the first sidewall 532A and the slope angle of the second sidewall 532B is equal to j times the difference between the slope angle of the second sidewall 532B and the slope angle of the third sidewall 532C, where j ranges from 1.5 to 3. Thus, the protrusion structure can better achieve the effects of preventing crosstalk between the adjacent sub-pixels, preventing the intrusion of water or oxygen, and preventing the peeling phenomenon of the pixel defining portion.

[0149] In some examples, as shown in FIGS. 3 and 4A, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 3.

number

[0150] In the display substrate of this example, the slope angle α of the first side wall, the slope angle β of the second side wall, and the slope angle γ of the third side wall satisfy the relationship restricted by the above formula 3, so that the protrusion structure can better achieve the effects of preventing crosstalk between the adjacent sub-pixels, preventing the intrusion of water and oxygen, and avoiding the peeling phenomenon of the pixel definition portion.

[0151] 3 and 4A, in some examples, the sum of the slope angle of the first sidewall 532A and the slope angle of the second sidewall 532B is equal to k times the slope angle of the third sidewall 532C, where k ranges from 2 to 3. Thereby, the protrusion structure can better achieve the effects of preventing crosstalk between the adjacent sub-pixels, preventing the intrusion of water and oxygen, and preventing the peeling phenomenon of the pixel defining portion.

[0152] In some examples, as shown in FIGS. 3 and 4A, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 8.

number

[0153] In the display substrate of this example, the slope angle α of the first side wall, the slope angle β of the second side wall, and the slope angle γ of the third side wall satisfy the relationship limited by the above formula, so that the protrusion structure can better achieve the effects of preventing crosstalk between the adjacent sub-pixels, preventing the intrusion of water and oxygen, and avoiding the peeling phenomenon of the pixel definition portion.

[0154] In some examples, as shown in FIGS. 3 and 4A, the slope angle of the first side wall 532A may range from 75-89 degrees, the slope angle of the second side wall 532B may range from 15-45 degrees, and the slope angle of the third side wall 532C may range from 45-60 degrees.

[0155] In some examples, as shown in FIGS. 3 and 4A, the slope angle of the first side wall 532A may range from 75-89 degrees, the slope angle of the second side wall 532B may range from 25-35 degrees, and the slope angle of the third side wall 532C may range from 45-55 degrees.

[0156] 3 and 4A, the size of the second side wall 532B in the second direction of the orthogonal projection on the driving substrate 510 is larger than the size of the first side wall 532A in the second direction of the orthogonal projection on the driving substrate 510, so that the protrusion structure can better cut the charge generating layer of the light-emitting functional layer at the position of the first side wall.

[0157] In some examples, as shown in Figures 3 and 4A, the size of the third side wall 532C in the second direction of the orthogonal projection on the driving substrate 510 is larger than the size of the second side wall 532B in the second direction of the orthogonal projection on the driving substrate 510. Thereby, the protrusion structure can reduce or avoid the formation of pores in the light-emitting functional layer subsequently formed on the third side wall 532C, and further avoid the formation of a passage through which water or oxygen can enter. Meanwhile, since the slope angle γ of the third side wall 532C is gentle, the pixel definition part can easily form a complete integral structure, and the peeling phenomenon is avoided from occurring on the third side wall.

[0158] In some examples, as shown in FIGS. 3 and 4A, the size in the first direction of the first side wall 532A is H1, the size in the first direction of the second side wall 532B is H2, and the size in the first direction of the third side wall 532C is H3, where H1, H2, and H3 satisfy Equation 4.

number

[0159] As a result, the protrusion structure can better cut the charge generating layer of the light-emitting functional layer at the position of the first side wall, and the protrusion structure can reduce or avoid the formation of pores in the light-emitting functional layer subsequently formed at the third side wall, and further avoid the formation of paths through which water oxygen can enter.

[0160] In some examples, as shown in Figures 3 and 4A, the protrusion 525B of each anode 525 further includes a fourth side wall 525D located on a side of the protrusion 525B closer to the center of the body portion 525A, and the slope angle of the fourth side wall 525D is greater than the slope angle of the second side wall 532B and less than the slope angle of the first side wall 532A.

[0161] In some examples, as shown in FIGS. 3 and 4A, the protrusion 525B of the anode 525 includes a fourth sidewall 525D located on a side of the protrusion 525B closer to the center of the body 525A, and the slope angle of the fourth sidewall is δ, satisfying Equation 5.

number

[0162] In some examples, as shown in Figures 3 and 4A, the protrusion portion 525B of each anode 525 includes a first sub-anode layer 5251, a second sub-anode layer 5252 and a third sub-anode layer 5253, where the first sub-anode layer 5251 is located on the side away from the base 512 of the drive circuit 514, the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the drive substrate 510, and the third sub-anode layer 5253 is located on the side of the second sub-anode layer 5252 away from the drive substrate 510.

[0163] In some examples, as shown in Figures 3 and 4A, the size of the first sub-anode layer 5251 in the second direction is larger than the size of the third sub-anode layer 5253 in the second direction, and the size of the third sub-anode layer 5253 in the second direction is larger than the size of the second sub-anode layer 5252 in the second direction. As a result, since the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction and the edge of the third sub-anode layer is not supported, the third sub-anode layer 5253 can form a curved structure 5253S that curves toward the driving substrate 510, and when the pixel defining portion is subsequently formed, peeling phenomenon can be effectively prevented from occurring in the pixel defining portion. Note that, since the pixel defining portion is usually manufactured from an inorganic material, peeling phenomenon is likely to occur if the edge of the protrusion is too steep.

[0164] On the other hand, the third sub-anode layer may be made of a material with low conductivity, such as indium tin oxide. In this case, the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction, and the edges of the third sub-anode layer are not supported, so that the third sub-anode layer can form a curved structure that curves toward the driving substrate, thereby exerting the effect of wrapping the edges of the protrusion to a certain extent, and further preventing contact between the edges of the protrusion and the light-emitting functional layer when a defect occurs in the pixel definition portion, and also avoiding the occurrence of phenomena such as tip discharge.

[0165] For example, the second direction is the direction from the protrusion 525B to the main body 525A or the direction from the main body 525A to the protrusion 525B, and the second direction is a direction parallel to the surface of the drive substrate 510 away from the anode layer 520.

[0166] For example, the conductivity of the third sub-anode layer is less than the conductivity of the first sub-anode layer and the conductivity of the second sub-anode layer, thereby allowing for better matching with the work function of the light-emitting functional layer.

[0167] In some examples, as shown in Figures 3 and 4A, the size of the third sub-anode layer 5253 exceeding the second sub-anode layer 5252 in the second direction is less than the size of the overlapping area in the second direction between the orthogonal projection of the pixel definition layer 530 on the drive substrate 510 and the orthogonal projection of the protrusion 525B on the drive substrate 510.

[0168] In some examples, as shown in Figures 3 and 4A, the size of the third sub-anode layer 5253 exceeding the second sub-anode layer 5252 in the second direction is less than 1 / 4 of the size in the second direction of the overlapping area between the orthogonal projection of the pixel definition layer 530 on the drive substrate 510 and the orthogonal projection of the protrusion 525B on the drive substrate 510.

[0169] In some examples, as shown in Figures 3 and 4A, the end of the third sub-anode layer 5253 away from the main body portion 525A is curved in a direction approaching the first sub-anode layer 5251, so that the third sub-anode layer can wrap around the edge of the protrusion to a certain extent, and further prevent contact between the edge of the protrusion and the light-emitting functional layer when a defect occurs in the pixel definition portion, and also avoid the occurrence of phenomena such as tip discharge.

[0170] 3 and 4A, the protrusion 525B of each anode 525 further includes a fourth subanode layer 5254 located between the second subanode layer 5252 and the third subanode layer 5253. This allows the body and protrusion to have a height difference by retaining the fourth subanode layer located on the protrusion of the anode but etching away the fourth subanode layer located on the body of the anode.

[0171] 3 and 4A, the size in the second direction of the fourth sub-anode layer 5254 is less than the size in the second direction of the second sub-anode layer 5252. Thereby, the third sub-anode layer 5253 formed on the fourth sub-anode layer 5254 can better form the curved structure 5253S, thereby effectively preventing peeling from occurring in the pixel definition portion when the pixel definition portion is subsequently formed.

[0172] In some examples, as shown in Figures 3 and 4A, the size in the second direction of the third sub-anode layer 5253 exceeding the fourth sub-anode layer 5254 is less than the size in the second direction of the overlapping area between the orthogonal projection of the pixel definition layer 530 on the drive substrate 510 and the orthogonal projection of the protrusion 525B on the drive substrate 510.

[0173] In some examples, as shown in Figures 3 and 4A, the second sub-anode layer 5252 includes a fifth side wall 525E located on the side away from the main body 525A of the second sub-anode layer 525E, and the fourth sub-anode layer 5254 includes a sixth side wall 525F located on the side away from the main body 525A of the fourth sub-anode layer 5254, where the slope angle of the fifth side wall 525E is greater than that of the fourth side wall 525D, the slope angle of the sixth side wall 525F is greater than that of the fourth side wall 525D, and the slope angle of the fifth side wall 525E is greater than that of the sixth side wall 525F, thereby avoiding the formation of a tip structure on the second sub-anode layer and the third sub-anode layer. This can suppress the tip discharge phenomenon to a certain extent, thereby improving the yield and extending the service life of the product.

[0174] 3 and 4A, an end of the first sub-anode layer 5251 away from the body portion 525A includes a raised portion 5251A, and the thickness of the raised portion 5251A in a direction perpendicular to the driving substrate 510 is greater than the average thickness of the first sub-anode layer 5251 in a direction perpendicular to the driving substrate 510. As a result, the raised portion 5251A can also wrap the edge of the protrusion to some extent, and further prevent the edge of the protrusion from coming into contact with the light-emitting functional layer when a defect occurs in the pixel definition portion, and also avoid the occurrence of phenomena such as tip discharge.

[0175] In some examples, as shown in Figures 3 and 4A, when the protuberance 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 are present simultaneously, the protuberance 5251A and the curved structure 5253S can wrap the edge of the protrusion from two directions, top and bottom, and can better prevent the edge of the protrusion from contacting the light-emitting functional layer when a defect occurs in the pixel definition portion, and can also avoid the occurrence of phenomena such as tip discharge. Note that the embodiments of the present disclosure are not limited thereto, and when the protuberance 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253 are present alone, they can also wrap the edge of the protrusion to some extent.

[0176] In some examples, the ratio of the thickness of the first sub-anode layer 5251 in a direction perpendicular to the drive substrate 510 to the thickness of the second sub-anode layer 5252 in a direction perpendicular to the drive substrate 510 ranges from 1 / 15 to 1 / 5.

[0177] In some examples, the ratio of the thickness of the first sub-anode layer 5251 in a direction perpendicular to the drive substrate 510 to the thickness of the third sub-anode layer 5253 in a direction perpendicular to the drive substrate 510 ranges from 1 / 3 to 4 / 5.

[0178] In some examples, the range of the ratio between the thickness of the first sub-anode layer 5251 in a direction perpendicular to the drive substrate 510 and the thickness of the fourth sub-anode layer 5254 in a direction perpendicular to the drive substrate 510 is 1 / 24-1 / 8.

[0179] In some examples, the first sub-anode layer 5251 has a thickness range of 1-4 nanometers in a direction perpendicular to the drive substrate 510, the second sub-anode layer 5252 has a thickness range of 15-22 nanometers in a direction perpendicular to the drive substrate 510, the fourth sub-anode layer 5254 has a thickness range of 24-32 nanometers in a direction perpendicular to the drive substrate 510, and the third sub-anode layer 5253 has a thickness range of 3-5 nanometers in a direction perpendicular to the drive substrate 510.

[0180] In some examples, the first sub-anode layer 5251 has a thickness range of 2-3 nanometers in a direction perpendicular to the drive substrate 510, the second sub-anode layer 5252 has a thickness range of 17-20 nanometers in a direction perpendicular to the drive substrate 510, the fourth sub-anode layer 5254 has a thickness range of 26-30 nanometers in a direction perpendicular to the drive substrate 510, and the third sub-anode layer 5253 has a thickness range of 4 nanometers in a direction perpendicular to the drive substrate 510.

[0181] In some examples, the ratio of the distance between two adjacent anodes 525 to the length of the orthogonal projection of the protrusion 525B of the anode 525 on the driving substrate 510 ranges from 2 to 4. That is, the ratio of the distance between two adjacent anodes 525 to the length of the anode 525 in the second direction ranges from 2 to 4. Thereby, the display substrate can better avoid crosstalk between adjacent subpixels.

[0182] In some examples, the ratio of the distance between two adjacent anodes 525 to the length of the orthogonal projection of the protrusion 525B of the anode 525 on the driving substrate 510 ranges from 2.5 to 3.5. That is, the ratio of the distance between two adjacent anodes 525 to the length of the anode 525 in the second direction ranges from 2.5 to 3.5. Thus, the display substrate can better avoid crosstalk between adjacent subpixels.

[0183] In some examples, the distance between two adjacent anodes 525 may range from 0.6 to 1 micron, that is, the width of the spacing region 522 may range from 0.6 to 1 micron. Of course, the embodiments of the present disclosure are not limited thereto, and the width of the spacing region may range according to actual circumstances.

[0184] In some examples, the distance between two adjacent anodes 525 ranges from 0.7 to 0.9 microns. Of course, the embodiments of the present disclosure are not limited thereto, and the width range of the spacing region can be set according to the actual situation.

[0185] 5 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 5, the protrusion 525B is disposed around the body 525A, so that the display substrate can effectively avoid crosstalk between adjacent sub-pixels in any direction, and the display substrate can be adapted to different pixel array structures.

[0186] 5, the shape of the orthogonal projection of the anode 525 on the driving substrate 510 includes a hexagon. Of course, the embodiments of the present disclosure are not limited thereto, and the shape of the orthogonal projection of the anode 525 on the driving substrate 510 may have other suitable shapes. Note that the pixel aperture is provided corresponding to the anode, and thus the shape of the orthogonal projection of the pixel aperture on the driving substrate is similar to the shape of the orthogonal projection of the anode on the driving substrate.

[0187] In some examples, as shown in FIG. 5, a plurality of anodes 525 are arranged in an array on a driving substrate 510 to form anode rows 610, and in each anode row 610, a plurality of anodes 525 are arranged in sequence along a direction.

[0188] In some examples, the second direction may be a row direction, as shown in Fig. 5. In this case, the ratio of the size of each anode 525 in the second direction of the orthogonal projection on the driving substrate 510 to the distance between two adjacent anodes 525 ranges from 4 to 6. This allows the display substrate to achieve a large aperture ratio and effectively avoid crosstalk between adjacent sub-pixels.

[0189] In some examples, as shown in FIG. 5, each anode 525 may have a size of 4-5 microns in the second direction of orthogonal projection on the drive substrate 510 .

[0190] 6 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. As shown in FIG. 6, the protrusion 525B of each anode 525 includes a first sub-anode layer 5251, a second sub-anode layer 5252 and a third sub-anode layer 5253, where the first sub-anode layer 5251 is located on the side away from the base 512 of the driving circuit 514, the second sub-anode layer 5252 is located on the side away from the driving substrate 510 of the first sub-anode layer 5251, and the third sub-anode layer 5253 is located on the side away from the driving substrate 510 of the second sub-anode layer 5252. The difference between the display substrates shown in FIG. 3 and FIG. 4A is that the display substrate shown in FIG. 6 does not include a fourth sub-anode layer.

[0191] 6, the body portion 525A and the protrusion portion 525B of the anode 525 may have the same layer structure, i.e., including the same number of multiple film layers and similar stacking relationships, but are not limited to the thickness of each film layer being the same. In this case, the body portion and the protrusion portion having a height difference can be formed by etching the second sub-anode layer portion located in the body portion of the anode and retaining the second sub-anode layer located in the protrusion portion of the anode.

[0192] 6, the size of the first sub-anode layer 5251 in the second direction is larger than the size of the third sub-anode layer 5253 in the second direction, and the size of the third sub-anode layer 5253 in the second direction is larger than the size of the second sub-anode layer 5252 in the second direction, the second direction being a direction from the protrusion 525B to the body 525A or a direction from the body 525A to the protrusion 525B, and the second direction being a direction parallel to a surface of the driving substrate 510 away from the anode layer 520. As a result, since the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction and an edge of the third sub-anode layer is not supported, the third sub-anode layer 5253 can form a curved structure 5253S curved toward the driving substrate 510, and when a pixel definition portion is subsequently formed, peeling can be effectively prevented from occurring in the pixel definition portion. In addition, since the pixel definition portion is usually made of an inorganic material, if the edges of the protrusions are too sharp, peeling is likely to occur.

[0193] On the other hand, the third sub-anode layer may be made of a material with low conductivity, such as indium tin oxide. In this case, the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction, and the edges of the third sub-anode layer are not supported, so that the third sub-anode layer can form a curved structure that curves toward the driving substrate, thereby exerting the effect of wrapping the edges of the protrusion to a certain extent, and further preventing contact between the edges of the protrusion and the light-emitting functional layer when a defect occurs in the pixel definition portion, and also avoiding the occurrence of phenomena such as tip discharge.

[0194] For example, the conductivity of the third sub-anode layer is less than the conductivity of the first sub-anode layer and less than the conductivity of the second sub-anode layer.

[0195] In some examples, as shown in FIG. 6, the end of the third sub-anode layer 5253 away from the main body portion 525A is curved in a direction approaching the first sub-anode layer 5251, so that the third sub-anode layer can wrap around the edge of the protrusion to a certain extent and can prevent contact between the edge of the protrusion and the light-emitting functional layer in the event of a defect occurring in the pixel definition portion, and can also avoid phenomena such as tip discharge.

[0196] In some examples, as shown in FIG. 6, the second sub-anode layer 5252 includes a fifth sidewall 525E and a sixth sidewall 525F, and the sixth sidewall 525F is located on the side of the fifth sidewall 525E that is farther from the driving substrate 510 than the fifth sidewall 525E. The slope angle of the fifth sidewall 525E is greater than that of the fourth sidewall 525D, and the slope angle of the sixth sidewall 525F is greater than that of the fourth sidewall 525D, and the slope angle of the fifth sidewall 525E is greater than that of the sixth sidewall 525F, thereby avoiding the formation of a tip structure on the second sub-anode layer. This can suppress the tip discharge phenomenon to a certain extent, thereby improving the yield and extending the service life of the product. In addition, since a step structure including a fifth sidewall and a sixth sidewall is formed at the edge of the second sub-anode layer 5252, the third sub-anode layer located on the second sub-anode layer can form a more smoothly curved structure, thereby better preventing the peeling phenomenon of the pixel definition portion.

[0197] 6, an end of the first sub-anode layer 5251 away from the body portion 525A includes a raised portion 5251A, and the thickness of the raised portion 5251A in a direction perpendicular to the driving substrate 510 is greater than the average thickness of the first sub-anode layer 5251 in a direction perpendicular to the driving substrate 510. As a result, the raised portion 5251A can also wrap the edge of the protrusion to some extent, and further prevent contact between the edge of the protrusion and the light-emitting functional layer when a defect occurs in the pixel definition portion, and also avoid the occurrence of phenomena such as tip discharge.

[0198] 6, when the protuberance 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 are present simultaneously, the protuberance 5251A and the curved structure 5253S can wrap the edge of the protrusion from two directions, top and bottom, and can better prevent the edge of the protrusion from contacting the light-emitting functional layer when a defect occurs in the pixel definition portion, and can also avoid the occurrence of phenomena such as tip discharge. Note that the embodiments of the present disclosure are not limited thereto, and when the protuberance 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253 are present alone, they can also wrap the edge of the protrusion to some extent.

[0199] 7 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. As shown in FIG. 7, the protrusion 525B of each anode 525 includes a first sub-anode layer 5251, a second sub-anode layer 5252, a third sub-anode layer 5253 and a fourth sub-anode layer 5254, where the first sub-anode layer 5251 is located on the side away from the base 512 of the driving circuit 514, the second sub-anode layer 5252 is located on the side away from the driving substrate 510 of the first sub-anode layer 5251, the third sub-anode layer 5253 is located on the side away from the driving substrate 510 of the second sub-anode layer 5252, and the fourth sub-anode layer 5254 is located between the second sub-anode layer 5252 and the third sub-anode layer 5253.

[0200] 7, the body portion 525A and the protrusion portion 525B of the anode 525 may have the same layer structure, i.e., include the same number of multiple film layers and similar stacking relationships, but are not limited to the thickness of each film layer being the same. In this case, the body portion 525A of the anode 525 similarly includes a first sub-anode layer 5251, a second sub-anode layer 5252, a third sub-anode layer 5253, and a fourth sub-anode layer 5254, the first sub-anode layer 5251 being located on the side away from the base 512 of the driving circuit 514, the second sub-anode layer 5252 being located on the side away from the driving substrate 510 of the first sub-anode layer 5251, the third sub-anode layer 5253 being located on the side away from the driving substrate 510 of the second sub-anode layer 5252, and the fourth sub-anode layer 5254 being located between the second sub-anode layer 5252 and the third sub-anode layer 5253. At this time, the second sub-anode layer portion located on the main body of the anode is etched, but the second sub-anode layer portion located on the protrusion of the anode is reserved, thereby forming the main body and the protrusion with a height difference.

[0201] For example, as shown in FIG. 7, the thickness of the first sub-anode layer 5251 located in the main body 525A of the anode 525 in the direction perpendicular to the driving substrate 510 is the same as the thickness of the first sub-anode layer 5251 located in the protrusion 525B of the anode 525 in the direction perpendicular to the driving substrate 510.

[0202] For example, as shown in FIG. 7, the thickness of the third sub-anode layer 5253 located in the main body 525A of the anode 525 in a direction perpendicular to the driving substrate 510 is the same as the thickness of the third sub-anode layer 5253 located in the protrusion 525B of the anode 525 in a direction perpendicular to the driving substrate 510.

[0203] For example, as shown in FIG. 7, the thickness of the fourth sub-anode layer 5254 located in the main body 525A of the anode 525 in a direction perpendicular to the drive substrate 510 is the same as the thickness of the fourth sub-anode layer 5254 located in the protrusion 525B of the anode 525 in a direction perpendicular to the drive substrate 510.

[0204] 7, the size of the first sub-anode layer 5251 in the second direction is larger than the size of the third sub-anode layer 5253 in the second direction, the size of the third sub-anode layer 5253 in the second direction is larger than the size of the second sub-anode layer 5252 in the second direction, and the size of the fourth sub-anode layer 5254 in the second direction is smaller than the size of the second sub-anode layer 5252 in the second direction. The second direction is a direction from the protrusion 525B to the body 525A or a direction from the body 525A to the protrusion 525B, and the second direction is a direction parallel to a surface away from the anode layer 520 of the driving substrate 510. Thereby, the third sub-anode layer 5253 formed on the fourth sub-anode layer 5254 can better form a curved structure 5253S, thereby effectively avoiding the occurrence of peeling in the pixel definition portion when the pixel definition portion is subsequently formed.

[0205] On the other hand, the third sub-anode layer may be made of a material with low conductivity, such as indium tin oxide. In this case, the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction, and the edges of the third sub-anode layer are not supported, so that the third sub-anode layer can form a curved structure that curves toward the driving substrate, thereby exerting the effect of wrapping the edges of the protrusion to a certain extent, and further preventing contact between the edges of the protrusion and the light-emitting functional layer when a defect occurs in the pixel definition portion, and also avoiding the occurrence of phenomena such as tip discharge.

[0206] For example, the conductivity of the third sub-anode layer is less than the conductivity of the first sub-anode layer and less than the conductivity of the second sub-anode layer.

[0207] In some examples, as shown in FIG. 7, the end of the third sub-anode layer 5253 away from the main body portion 525A is curved in a direction approaching the first sub-anode layer 5251, so that the third sub-anode layer can wrap around the edge of the protrusion to some extent and further prevent contact between the edge of the protrusion and the light-emitting functional layer in the event of a defect occurring in the pixel definition portion, thereby avoiding phenomena such as tip discharge.

[0208] In some examples, as shown in FIG. 7, the second sub-anode layer 5252 includes a fifth side wall 525E located on the side away from the main body 525A of the second sub-anode layer 525E, and the fourth sub-anode layer 5254 includes a sixth side wall 525F located on the side away from the main body 525A of the fourth sub-anode layer 5254, where the slope angle of the fifth side wall 525E is greater than that of the fourth side wall 525D, the slope angle of the sixth side wall 525F is greater than that of the fourth side wall 525D, and the slope angle of the fifth side wall 525E is greater than that of the sixth side wall 525F, thereby avoiding the formation of a tip structure on the second sub-anode layer and the third sub-anode layer. This can suppress the tip discharge phenomenon to a certain extent, thereby improving the yield and extending the service life of the product.

[0209] 7, an end of the first sub-anode layer 5251 away from the body portion 525A includes a raised portion 5251A, and the thickness of the raised portion 5251A in a direction perpendicular to the driving substrate 510 is greater than the average thickness of the first sub-anode layer 5251 in a direction perpendicular to the driving substrate 510. As a result, the raised portion 5251A can also wrap the edge of the protrusion to some extent, and further prevent contact between the edge of the protrusion and the light-emitting functional layer when a defect occurs in the pixel definition portion, and also avoid the occurrence of phenomena such as tip discharge.

[0210] 7, when the protuberance 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 are present simultaneously, the protuberance 5251A and the curved structure 5253S can wrap the edge of the protrusion from two directions, top and bottom, and can better prevent the edge of the protrusion from contacting the light-emitting functional layer when a defect occurs in the pixel definition portion, and can also avoid the occurrence of phenomena such as tip discharge. Note that the embodiments of the present disclosure are not limited thereto, and when the protuberance 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253 are present alone, they can also wrap the edge of the protrusion to some extent.

[0211] 8 is a schematic diagram of a partial structure of another display substrate according to an embodiment of the present disclosure. As shown in FIG. 8, the package layer 560 includes an inorganic package layer 710, which is located on the side of the cathode layer 550 away from the driving substrate 510.

[0212] In some examples, as shown in Fig. 8, the inorganic package layer 710 includes a plurality of sub-inorganic package layers 7100, where at least two adjacent sub-inorganic package layers 7100 of the plurality of sub-inorganic package layers 7100 are made of different materials, and at least two adjacent sub-inorganic package layers 7100 of the plurality of sub-inorganic package layers 7100 are made of the same material. By having at least two adjacent sub-inorganic package layers 7100 between the plurality of sub-inorganic package layers 7100 made of different materials or made of the same material, the inorganic package layer can form a denser film layer, which can better prevent the intrusion of water and oxygen, and further extend the service life of the display device.

[0213] For example, the material of each sub-inorganic package layer 7100 may be at least one selected from silicon nitride, silicon oxide, and silicon oxynitride.

[0214] In some examples, as shown in Fig. 8, in the direction away from the driving substrate 510, the refractive index of the multiple sub-inorganic package layers 7100 increases and then decreases. When the emitted light emitted by the light-emitting functional layer 540 enters the sub-inorganic package layer with a high refractive index from the sub-inorganic package layer with a low refractive index, it is refracted at the interface therebetween, thereby reducing the diffusion angle of the emitted light, thereby reducing or avoiding crosstalk between adjacent sub-pixels inside the display substrate; then, the emitted light further enters the sub-inorganic package layer with a low refractive index from the sub-inorganic package layer with a high refractive index and is refracted at the interface therebetween, at which time the diffusion angle of the emitted light increases, but because the emitted light is already close to the light-emitting surface of the display substrate, it does not cause crosstalk between adjacent sub-pixels.

[0215] In some examples, as shown in FIG. 8, each sub-inorganic package layer 7100 includes alternating flat regions PTQ and double arch spacing regions JGQ, a first arch region GX1 located on the side of the flat region PTQ away from the double arch spacing region JGQ, a second arch region GX2 located between the flat region PTQ and the double arch spacing region JGQ, and a third arch region GX3 located on the side of the flat region PTQ away from the second arch region GX2, wherein the first arch region GX1 and the second arch region GX2 are arranged symmetrically with respect to the center of the flat region PTQ.

[0216] In some examples, as shown in FIG. 8, the orthogonal projection of the first arch region GX1, the second arch region GX2 or the third arch region GX3 onto the drive substrate 510 overlaps with the orthogonal projection of the protrusion portion 525B onto the drive substrate 510, and the orthogonal projection of the flat region PTQ onto the drive substrate 510 overlaps with the orthogonal projection of the main body portion 525A onto the drive substrate 510. That is, the orthogonal projection of the first arch region GX1, the second arch region GX2, or the third arch region GX3 of each sub-inorganic package layer 7100 on the driving substrate 510 overlaps with the orthogonal projection of the protrusion 525B on the driving substrate 510, the orthogonal projection of the flat region PTQ of each sub-inorganic package layer 7100 on the driving substrate 510 overlaps with the orthogonal projection of the main body 525A on the driving substrate 510, and the first arch region GX1, the second arch region GX2, and the third arch region GX3 of each sub-inorganic package layer 7100 overlap with the protrusion 525B of the different anodes 525. As a result, the light of each sub-pixel edge is refracted by the first arch region, the second arch region, or the third arch region and converges on the black matrix, thereby preventing crosstalk between adjacent sub-pixels. The black matrix may be a general black matrix, or may be a structure formed by stacking at least two color filters, which has a low light transmittance and exhibits the function of a black matrix.

[0217] In some examples, as shown in FIG. 8, the size in the second direction of flat region PTQ is L, the distance in the second direction between the center of second arch region GX2 and the center of third arch region GX3 is a first distance D1, the distance in the second direction between the center of first arch region GX1 and the center of second arch region GX2 is a second distance D2, the radii of curvature of the first arch region GX1, the second arch region GX2 and the third arch region GX3 are all R, and the first distance D1 satisfies Equation 6.

number

[0218] In the display substrate according to this embodiment, the first distance D1 satisfies the above formula, so that the pixel density or aperture ratio can be improved and the crosstalk between adjacent sub-pixels can be reduced, thereby achieving a better display effect. Note that the above-mentioned radius of curvature is the average radius of curvature, i.e., the reciprocal of the average curvature of the corresponding arc line. For example, the second direction is the direction from the protrusion to the main body or the direction from the main body to the protrusion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.

[0219] In some examples, as shown in FIG. 8, the size in the second direction of flat region PTQ is L, the distance in the second direction between the center of second arch region GX2 and the center of third arch region GX3 is a first distance D1, the distance in the second direction between the center of first arch region GX1 and the center of second arch region GX2 is a second distance D2, the radii of curvature of the first arch region GX1, the second arch region GX2 and the third arch region GX3 are all R, and the first distance D1 satisfies Equation 7.

number

[0220] In the display substrate of this example, the first distance D1 satisfies the above formula, so that the pixel density or aperture ratio can be improved and the crosstalk between adjacent sub-pixels can be reduced, thereby achieving a better display effect.

[0221] For example, the second direction is a direction from the protrusion to the main body or a direction from the main body to the protrusion, and the second direction is parallel to a surface of the drive substrate away from the anode layer.

[0222] 8, in each sub-inorganic package layer 7100, the distance between the face of the first arch region GX1, the second arch region GX2, or the third arch region GX3 facing away from the drive substrate 510 and the drive substrate 510 is greater than the distance between the face of the flat region PTQ facing away from the drive substrate 510 and the drive substrate 510. As a result, the first arch region GX1, the second arch region GX2, or the third arch region GX3 is an upward arch structure.

[0223] In some examples, as shown in FIG. 8, the orthogonal projection of the double arch spacing region JGQ on the drive substrate 510 overlaps with the orthogonal projection of the spacing region 522 between two adjacent anodes 525 on the drive substrate 510.

[0224] In some examples, as shown in FIG. 8 , the multiple sub-inorganic package layers 7100 include a first sub-inorganic package layer 711, a second sub-inorganic package layer 712, a third sub-inorganic package layer 713 and a fourth sub-inorganic package layer 714, where the first sub-inorganic package layer 711 is located on the side of the cathode layer 550 away from the driving substrate 510, the second sub-inorganic package layer 712 is located on the side of the first sub-inorganic package layer 711 away from the driving substrate 510, the third sub-inorganic package layer 713 is located on the side of the second sub-inorganic package layer 711 away from the driving substrate 510, and the fourth sub-inorganic package layer 714 is located on the side of the third sub-inorganic package layer 713 away from the driving substrate 510.

[0225] In some examples, as shown in FIG. 8, the refractive index of the first sub-inorganic package layer 711 is less than that of the second sub-inorganic package layer 712, and the refractive index of the fourth sub-inorganic package layer 714 is less than that of the third sub-inorganic package layer 713. Thus, when the emitted light emitted by the light-emitting functional layer 540 enters the second sub-inorganic package layer 712 having a high refractive index from the first sub-inorganic package layer 711 having a low refractive index, it is refracted at the interface between the first sub-inorganic package layer 711 and the second sub-inorganic package layer 712, thereby reducing the diffusion angle of the emitted light, thereby reducing or avoiding crosstalk between adjacent sub-pixels inside the display substrate; then, the emitted light further enters the fourth sub-inorganic package layer 714 having a low refractive index from the third sub-inorganic package layer 713 having a high refractive index and is refracted at the interface therebetween, at which time the diffusion angle of the emitted light increases, but because the emitted light is already close to the light-emitting surface of the display substrate, it does not cause crosstalk between adjacent sub-pixels.

[0226] In some examples, as shown in Figure 8, the refractive index of the second sub-inorganic package layer 712 and the refractive index of the third sub-inorganic package layer 713 are equal. In this case, the second sub-inorganic package layer 712 and the third sub-inorganic package layer 713 may be made of the same material. Of course, the embodiments of the present disclosure are not limited thereto, and the refractive index of the second sub-inorganic package layer and the refractive index of the third sub-inorganic package layer may not be equal.

[0227] In some examples, as shown in FIG. 8, the first sub-inorganic package layer 711 and the second sub-inorganic package layer 712 may be made of different materials, and the fourth sub-inorganic package layer 714 and the third sub-inorganic package layer 713 may be made of different materials.

[0228] For example, the first sub-inorganic package layer 711 is made from a silicon oxide or silicon oxynitride material, the second sub-inorganic package layer 712 is made from a silicon nitride material, the fourth sub-inorganic package layer 714 is made from a silicon oxide material, and the third sub-inorganic package layer 713 is made from a silicon nitride material.

[0229] In some examples, as shown in FIG. 8, the first sub-inorganic package layer 711 and the fourth sub-inorganic package layer 714 may be made of the same material or may be made of different materials.

[0230] For example, the first sub-inorganic package layer 711 and the fourth sub-inorganic package layer 714 are both made of a silicon oxide material, or the first sub-inorganic package layer 711 is made of a silicon oxynitride material and the fourth sub-inorganic package layer 714 is made of a silicon oxide material.

[0231] 8, the upper surface of the first arch region GX1 of the first sub-inorganic package layer 711 away from the base 512 has a first radius of curvature, the upper surface of the first arch region GX1 of the second sub-inorganic package layer 712 away from the base 512 has a second radius of curvature, the upper surface of the first arch region GX1 of the third sub-inorganic package layer 713 away from the base 512 has a third radius of curvature, and the upper surface of the first arch region GX1 of the fourth sub-inorganic package layer 714 away from the base 512 has a fourth radius of curvature, where the first radius of curvature is less than the second radius of curvature, the second radius of curvature is less than the third radius of curvature, and the third radius of curvature is less than the fourth radius of curvature. That is, in the direction away from the driving substrate 510, the radius of curvature of the first arch region of each sub-inorganic package layer gradually increases.

[0232] In some examples, as shown in FIG. 8, similar to the relationship satisfied by the radius of curvature of the top surface away from the base of the first arch region of each sub-inorganic package layer, the radius of curvature of the top surface away from the base of the second arch region of each sub-inorganic package layer also gradually increases in the direction away from the drive substrate.

[0233] In some examples, as shown in FIG. 8, similar to the relationship satisfied by the radius of curvature of the top surface away from the base of the first arch region of each sub-inorganic package layer, the radius of curvature of the top surface away from the base of the third arch region of each sub-inorganic package layer also gradually increases in the direction away from the drive substrate.

[0234] In some examples, as shown in FIG. 8, the shapes of the first arch region GX1, the second arch region GX2, and the third arch region GX3 of the first sub-inorganic package layer 711 are the same, the shapes of the first arch region GX1, the second arch region GX2, and the third arch region GX3 of the second sub-inorganic package layer 712 are the same, the shapes of the first arch region GX1, the second arch region GX2, and the third arch region GX3 of the third sub-inorganic package layer 713 are the same, and the shapes of the first arch region GX1, the second arch region GX2, and the third arch region GX3 of the fourth sub-inorganic package layer 714 are the same.

[0235] 8, the dummy center of the first arch region of the fourth sub-inorganic package layer 714 is located between the upper surface away from the base 512 of the first sub-inorganic package layer 711 and the lower surface close to the base 512 of the fourth sub-inorganic package layer 714. Note that the dummy center is a virtual circle formed by the arc line of the upper surface away from the base of the first arch region.

[0236] 8, the first sub-inorganic package layer 711 has a first thickness TH1 in a direction perpendicular to the driving substrate 510, the second sub-inorganic package layer 712 has a second thickness TH2 in a direction perpendicular to the driving substrate 510, the third sub-inorganic package layer 713 has a third thickness TH3 in a direction perpendicular to the driving substrate 510, and the fourth sub-inorganic package layer 714 has a fourth thickness TH4 in a direction perpendicular to the driving substrate 510, where the first thickness TH1 is greater than the second thickness TH2, the second thickness TH2 is greater than the third thickness TH3, and the third thickness TH3 is greater than the fourth thickness TH4. That is, the thickness of each sub-inorganic package layer gradually decreases in a direction away from the driving substrate 510.

[0237] 8, the ratio of the difference between the first thickness TH1 and the second thickness TH2 to the difference between the third thickness TH3 and the fourth thickness TH4 ranges from 1.5 to 2 times, that is, the first thickness TH1, the second thickness TH2, the third thickness TH3 and the fourth thickness TH4 satisfy Equation 9, and the value range of m is 1.2 to 2, so that the display substrate can better avoid crosstalk between adjacent sub-pixels.

number

[0238] 8, the ratio of the sum of the second thickness TH2 and the third thickness TH3 to the first thickness TH1 is in the range of 0.8-1.2, that is, the first thickness TH1, the second thickness TH2 and the third thickness TH3 satisfy Equation 10, and the value range of n is 0.8-1.2, so that the display substrate can better avoid crosstalk between adjacent sub-pixels.

number

[0239] In some examples, as shown in FIG. 8, the first thickness range is 1000-1200 nanometers, the second thickness range is 500-660 nanometers, the third thickness range is 480-560 nanometers, and the fourth thickness range is 180-260 nanometers.

[0240] In some examples, the material of the first sub-inorganic package layer includes silicon oxide or silicon oxynitride, the material of the second sub-inorganic package layer includes silicon nitride, the material of the third sub-inorganic package layer includes silicon nitride, and the material of the fourth sub-inorganic package layer includes silicon oxide. Of course, the embodiments of the present disclosure are not limited thereto, and the material of each sub-inorganic package layer may be other suitable materials.

[0241] In some examples, the first thickness is 1100 nanometers, the second thickness range is 580 nanometers, the third thickness range is 520 nanometers, and the fourth thickness range is 220 nanometers. Of course, embodiments of the present disclosure are not limited thereto, and the thickness of each sub-inorganic package layer may be other values.

[0242] 8, the package layer 560 further includes an organic package layer 720, which is located on a side of the inorganic package layer 710 away from the driving substrate 510. The organic package layer 720 includes a first region 7201, a second region 7202, and a third region 7203, where the average thickness of the first region 7201 is less than the average thickness of the second region 7202, and the average thickness of the second region 7202 is less than the average thickness of the third region 7203. This allows the organic package layer to better match color filters having different thicknesses that will be subsequently formed.

[0243] In some examples, as shown in FIG. 8, the display substrate 500 further includes a color film layer 570, which is located on the side of the package layer 560 away from the driving substrate 510, and which includes a first color filter 571, a second color filter 572 and a third color filter 573.

[0244] For example, the first color filter 571, the second color filter 572, and the third color filter 573 may be color filters of different colors.

[0245] For example, the first color filter 571, the second color filter 572, and the third color filter 573 may have different thicknesses, although the embodiments of the present disclosure are not limited thereto.

[0246] In some examples, as shown in FIG. 8, the first color filter 571 and the second color filter 572 have a first overlapping region OP1, the second color filter 572 and the third color filter 573 have a second overlapping region OP2, and the third color filter 573 and the first color filter 571 have a third overlapping region OP3. When two different color filters overlap, the light transmittance of the overlapping region is low, and therefore it can be used as a black matrix. Thus, the first overlapping region, the second overlapping region, and the third overlapping region of the display substrate can all be used as a black matrix to achieve the effect of light blocking. Of course, the embodiment of the present disclosure is not limited thereto, and adjacent color filters may not overlap, and a black matrix may be separately formed between adjacent color filters.

[0247] In some examples, as shown in Fig. 8, the orthogonal projections of the first overlapping region OP1, the second overlapping region OP2, and the third overlapping region OP3 on the driving substrate 510 overlap with the orthogonal projections of the gap region 522 between two adjacent anodes 525 on the driving substrate 510, which can be used as a black matrix to achieve a light blocking effect. Note that, although the display substrate shown in Fig. 8 forms an overlapping region corresponding to the black matrix by overlapping only two color filters, the display substrate according to the embodiment of the present disclosure may form an overlapping region corresponding to the black matrix by overlapping three color filters.

[0248] In some examples, as shown in FIG. 8, the orthogonal projections of the first overlapping region OP1, the second overlapping region OP2, and the third overlapping region OP3 on the drive substrate 510 overlap with the orthogonal projection of the protrusion 525B on the drive substrate 510.

[0249] In some examples, as shown in FIG. 8, the size of the first overlap region OP1 in the second direction is larger than the size of the second overlap region OP2 in the second direction, and the size of the second overlap region OP2 in the second direction is larger than the size of the third overlap region OP3 in the second direction.

[0250] In some examples, as shown in FIG. 8, the size range of the first overlap region OP1 in the second direction is 400-600 nanometers, the size range of the second overlap region OP2 in the second direction is 250-350 nanometers, and the size range of the third overlap region OP3 in the second direction is 100-200 nanometers.

[0251] 8, the average size of the first color filter 571 in the direction perpendicular to the drive substrate 510 is larger than the average size of the second color filter 572 in the direction perpendicular to the drive substrate 510 and is smaller than the average size of the third color filter 573 in the direction perpendicular to the drive substrate 510. Note that the above average size is the arithmetic mean value of the sizes of each portion of the color filter in the direction perpendicular to the drive substrate.

[0252] In some examples, as shown in FIG. 8, the average size range of the first color filter 571 in a direction perpendicular to the drive substrate 510 is 2.3-2.6 microns, the average size range of the second color filter 572 in a direction perpendicular to the drive substrate 510 is 1.7-1.95 microns, and the average size range of the third color filter 573 in a direction perpendicular to the drive substrate 510 is 2.3-2.7 microns.

[0253] In some examples, as shown in FIG. 8, the ratio of the difference between the average size of the first color filter 571 in a direction perpendicular to the driving substrate 510 and the average size of the second color filter 572 in a direction perpendicular to the driving substrate 510 to the difference between the average size of the first color filter 571 in a direction perpendicular to the driving substrate 510 and the average size of the third color filter 573 in a direction perpendicular to the driving substrate 510 is in the range of 2-3.

[0254] 9 is a schematic diagram of a first color filter of a display substrate according to an embodiment of the present disclosure. As shown in Fig. 8 and Fig. 9, the first color filter 571 includes a first edge portion 571A, a second edge portion 571B, and a middle portion 571C located between the first edge portion 571A and the second edge portion 571B, and the average size of the middle portion 571C in a direction perpendicular to the driving substrate 510 is less than the average size of the first edge portion 571A in a direction perpendicular to the driving substrate 510 and the average size of the second edge portion 571B in a direction perpendicular to the driving substrate 510.

[0255] In some examples, as shown in FIG. 8, the first color filter 571 includes a first contact surface 571C in contact with the second color filter 572, the second color filter 572 includes a second contact surface 572C in contact with the third color filter 573, and the third color filter 573 includes a third contact surface 573C in contact with the first color filter 571, and the size of the first contact surface 571C in a first direction perpendicular to the driving substrate 510 is equal to the size of the second contact surface 572C in the first direction and is less than the size of the third contact surface 573C in the first direction.

[0256] In some examples, as shown in FIG. 8, the distance between the first color filter 571 and the surface of the driving substrate 510 away from the anode layer 520 is greater than the distance between the third color filter 573 and the surface of the driving substrate 510 away from the anode layer 520, and is less than the distance between the second color filter 572 and the surface of the driving substrate 510 away from the anode layer 520.

[0257] In some examples, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter, as shown in Figure 8. Of course, the embodiments of the present disclosure are not limited thereto, and the first color filter, the second color filter, and the third color filter may be color filters of other colors.

[0258] In some instances, the material of color film layer 570 may contain a desiccant, which can achieve the effect of preventing external water or oxygen from penetrating the membrane layers below the color film layer.

[0259] In some examples, the color film layer 570 includes elemental aluminum.

[0260] 8, the display substrate 500 further includes a protective layer 580 located on the side of the color film layer 570 away from the driving substrate 510. The protective layer 580 can achieve the effect of protecting the color film layer 570, and stabilize the filtering performance of the color film layer 570 during long-term use, thereby improving the display quality of the display substrate.

[0261] In some examples, as shown in FIG. 8, the display substrate 500 further includes a glass cover plate 590 located on the side of the color film layer 570 away from the driver substrate 510 .

[0262] 8, the flat region PTQ of the first sub-inorganic package layer 711 has a first width in the second direction, the flat region PTQ of the second sub-inorganic package layer 712 has a second width in the second direction, the flat region PTQ of the third sub-inorganic package layer 713 has a third width in the second direction, and the flat region PTQ of the fourth sub-inorganic package layer 714 has a fourth width in the second direction, where the first width is greater than the second width, the second width is greater than the third width, and the third width is greater than the fourth width. That is, the first width, the second width, the third width, and the fourth width gradually decrease.

[0263] 8 and 10, the first connection lines L1 between the edge adjacent to the second arch region GX2 of the flat region PTQ of the first sub-inorganic package layer 711, the edge adjacent to the second arch region GX2 of the flat region PTQ of the second sub-inorganic package layer 712, the edge adjacent to the second arch region GX2 of the flat region PTQ of the third sub-inorganic package layer 713, and the edge adjacent to the second arch region GX2 of the flat region PTQ of the fourth sub-inorganic package layer 714 are connected to the driving substrate 510. The included angle between the second connecting line L2 and a surface away from the anode layer 520 of the driving substrate 510 is a first included angle, and the included angle between the apex of the second arch region GX2 of the first sub-inorganic packaging layer 711, the apex of the first arch region GX1 of the second sub-inorganic packaging layer 712, the apex of the second arch region GX2 of the third sub-inorganic packaging layer 713, and the apex of the second arch region GX2 of the fourth sub-inorganic packaging layer 714 and a surface away from the anode layer 520 of the driving substrate 510 is a second included angle, and the first included angle is less than the second included angle.

[0264] In some examples, the first included angle is in the range of 60-85 degrees and the second included angle is in the range of 85-89 degrees, as shown in FIGS.

[0265] In some examples, as shown in FIGS. 8 and 10, the intersection of the first connection line L1 and the second connection line L2 is located within the drive substrate 510.

[0266] 11 is a structural schematic diagram of a driving substrate according to an embodiment of the present disclosure. As shown in FIG. 11, the driving circuit 514 includes a semiconductor layer 102, a first conductive layer 301, a second conductive layer 302, a third conductive layer 303 and a fourth conductive layer 304, where the semiconductor layer 102 is located in the base 512, the first conductive layer 301 is located on the semiconductor layer 102, the second conductive layer 302 is located on the side of the first conductive layer 301 away from the base 512, the third conductive layer 303 is located on the side of the second conductive layer 302 away from the base 512, and the fourth conductive layer 304 is located on the side of the third conductive layer 303 away from the base 512.

[0267] In some examples, as shown in FIG. 11, the intersection of the first connection line L1 and the second connection line L2 is located between the top surface of the third conductive layer 303 away from the base 512 and the anode layer 520.

[0268] In some examples, as shown in FIG. 11, the distance between the intersection of the first connecting line L1 and the second connecting line L2 and the apex of the upper surface away from the base 512 of the protruding structure 535 of the pixel definition layer 530 is greater than the thickness in the first direction of the first sub-inorganic package layer 711.

[0269] In some examples, as shown in FIG. 11, the distance between the intersection of the first connecting line L1 and the second connecting line L2 and the vertex of the upper surface away from the base 512 of the protrusion structure 535 of the pixel definition layer 530 is less than the sum of the thickness in the first direction of the first sub-inorganic package layer 711 and the thickness in the first direction of the second sub-inorganic package layer 712.

[0270] In some examples, as shown in FIG. 11 , the angle between the third connecting line L3 and the surface away from the anode layer 520 of the driving substrate 510 between the edge adjacent to the double arch spacing region JGQ of the second arch region GX2 of the first sub-inorganic package layer 711, the edge adjacent to the double arch spacing region JGQ of the second arch region GX2 of the second sub-inorganic package layer 712, the edge adjacent to the double arch spacing region JGQ of the second arch region GX2 of the third sub-inorganic package layer 713, and the edge adjacent to the double arch spacing region JGQ of the second arch region GX2 of the fourth sub-inorganic package layer 714 is a third included angle, and the third included angle is less than the second included angle.

[0271] In some examples, as shown in FIG. 11, the intersection of the first connection line L1 and the third connection line L3 is located between an upper surface of the second conductive layer 302 away from the base 512 and a lower surface of the third conductive layer 303 close to the base 512.

[0272] In some examples, as shown in FIG. 11, the intersection of the second connection line L2 and the third connection line L3 is located between a lower surface of the first conductive layer 301 close to the base 512 and a lower surface of the base 512 away from the first conductive layer 301.

[0273] In some examples, as shown in FIG. 11 , the angle between the fourth connecting line L4 and the surface away from the anode layer 520 of the driving substrate 510 among the edge away from the double arch spacing region JGQ of the third arch region GX3 of the first sub-inorganic package layer 711, the edge away from the double arch spacing region JGQ of the third arch region GX3 of the second sub-inorganic package layer 712, the edge away from the double arch spacing region JGQ of the third arch region GX3 of the third sub-inorganic package layer 713, and the edge away from the double arch spacing region JGQ of the third arch region GX3 of the fourth sub-inorganic package layer 714 is a fourth included angle, and the fourth included angle is less than the second included angle.

[0274] In some examples, as shown in FIG. 11, the intersection point between the first connection line L1 and the fourth connection line L4 is located on the side of the base 512 away from the first conductive layer 301.

[0275] In some examples, as shown in FIG. 11, the intersection of the third connection line L3 and the fourth connection line L4 is located between an upper surface of the second conductive layer 302 away from the base 512 and a lower surface of the third conductive layer 303 close to the base 512.

[0276] 12 is a schematic diagram of a partial structure of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 12, the color film layer 570 further includes a black matrix 574 located between any two adjacent ones of the first color filter 571, the second color filter 572, and the third color filter 573.

[0277] In some examples, as shown in FIG. 12, the orthogonal projection of the black matrix 574 on the drive substrate 510 overlaps with the orthogonal projection of the space region 522 between two adjacent anodes 525 on the drive substrate 510 .

[0278] 12, the display substrate 500 further includes a protective layer 580 located on the side of the color film layer 570 away from the driving substrate 510. The protective layer 580 can achieve the effect of protecting the color film layer 570, and stabilize the filtering performance of the color film layer 570 during long-term use, thereby improving the display quality of the display substrate.

[0279] In some examples, as shown in FIG. 12, the display substrate 500 further includes a glass cover plate 590 located on the side of the color film layer 570 away from the driver substrate 510 .

[0280] An embodiment of the present disclosure further provides a display device, comprising any one of the display substrates described above. Fig. 13 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in Fig. 13, the display device 900 comprises the above-mentioned display substrate 500. Thus, the display device has technical effects corresponding to the beneficial technical effects of the display substrate.

[0281] For example, in the display substrate, the anode includes a body and a protrusion, and the size of the protrusion in a direction perpendicular to the driving substrate is larger than the size of the body in a direction perpendicular to the driving substrate, so that the pixel definition layer located between the two anodes and overlapping the edge portion of the anode can form a protrusion structure corresponding to the protrusion. When forming the light-emitting functional layer, at least some sub-functional layers (e.g., charge generation layers) of the light-emitting functional layer can be better cut at the position of the protrusion structure, that is, at least some sub-functional layers of the light-emitting parts corresponding to the two adjacent anodes are not connected, so that the leakage current and crosstalk between adjacent sub-pixels can be effectively avoided. Meanwhile, at this time, the height of the protrusion structure of the pixel definition layer is also higher, so that the effect of pixel definition can be better exerted, and the crosstalk between adjacent sub-pixels can be optically reduced or avoided. As a result, the display substrate can also reduce or avoid the crosstalk between adjacent sub-pixels, and thus has a better display quality.

[0282] For example, the driving substrate of the display substrate may be manufactured by a semiconductor manufacturing process, so that a pixel driving circuit for driving each pixel to emit light and display can be integrated into the driving substrate, so that the display device can provide a micro display device, which has the advantages of high resolution, high brightness, rich colors, low driving voltage, fast response speed, low power consumption, etc.

[0283] For example, the display device 900 may be a wearable display device, such as a smart watch, smart glasses, etc. Of course, the embodiments of the present disclosure are not limited thereto, and the display device may be other electronic products having a display function, such as a mobile phone, a television, a navigation device, an electronic album, an electronic photo frame, a computer monitor, etc.

[0284] 14 is a plan view of a display device according to an embodiment of the present disclosure. As shown in FIG. 14, the display device 900 includes a display area 910 and a peripheral area 920 located around the display area 910, and the peripheral area 920 of the display device 900 includes a wiring area 930. The display area 910 can be used to perform light emission display, while the wiring area 930 can be used to lead out various driving lines or signal lines from the display area 910.

[0285] FIG. 15 is a schematic diagram of another display device according to an embodiment of the present disclosure. As shown in FIG. 15, the display substrate 500 of the display device 900 does not include a color film layer. At this time, the display device 900 further includes a counter substrate 800, which is disposed opposite the display substrate 500, and which includes a glass cover plate 810 and a color film layer 570 located on the glass cover plate 810, and the color film layer 570 includes a first color filter 571, a second color filter 572 and a third color filter 573. Thus, the display substrate and the counter substrate are manufactured respectively first, and then the display substrate and the counter substrate are aligned, thereby forming the display device. And the display device has technical effects corresponding to the beneficial technical effects of the display substrate.

[0286] For example, in the display substrate, the anode includes a body and a protrusion, and the size of the protrusion in a direction perpendicular to the driving substrate is larger than the size of the body in a direction perpendicular to the driving substrate, so that the pixel definition layer located between the two anodes and overlapping the edge portion of the anode can form a protrusion structure corresponding to the protrusion. When forming the light-emitting functional layer, at least some sub-functional layers (e.g., charge generation layers) of the light-emitting functional layer can be better cut at the position of the protrusion structure, that is, at least some sub-functional layers of the light-emitting parts corresponding to the two adjacent anodes are not connected, so that the leakage current and crosstalk between adjacent sub-pixels can be effectively avoided. Meanwhile, at this time, the height of the protrusion structure of the pixel definition layer is also higher, so that the effect of pixel definition can be better exerted, and the crosstalk between adjacent sub-pixels can be optically reduced or avoided. As a result, the display substrate can also reduce or avoid the crosstalk between adjacent sub-pixels, and thus has a better display quality.

[0287] For example, the driving substrate of the display substrate may be manufactured by a semiconductor manufacturing process, so that a pixel driving circuit for driving each pixel to emit light and display can be integrated into the driving substrate, thereby providing a micro display device with advantages such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption.

[0288] For example, the display device 900 may be a wearable display device, such as a smart watch, smart glasses, etc. Of course, the embodiments of the present disclosure are not limited thereto, and the display device may be other electronic products having a display function, such as a mobile phone, a television, a navigator, an electronic album, an electronic photo frame, a computer monitor, etc.

[0289] In some examples, as shown in FIG. 15, the first color filter 571 and the second color filter 572 have a first overlapping region OP1, the second color filter 572 and the third color filter 573 have a second overlapping region OP2, and the third color filter 573 and the first color filter 571 have a third overlapping region OP3. When two different color filters overlap, the light transmittance of the overlapping region is low, and therefore it can be used as a black matrix. Thus, the first overlapping region, the second overlapping region, and the third overlapping region of the display substrate can all be used as a black matrix to achieve the effect of light blocking. Of course, the embodiment of the present disclosure is not limited thereto, and adjacent color filters may not overlap, and a black matrix may be separately formed between adjacent color filters.

[0290] 15, the orthogonal projections of the first overlapping region OP1, the second overlapping region OP2, and the third overlapping region OP3 on the driving substrate 510 overlap with the orthogonal projections of the gap region 522 between two adjacent anodes 525 on the driving substrate 510. Note that, although the display substrate shown in FIG. 14 forms an overlapping region corresponding to the black matrix by overlapping only two color filters, the display substrate according to the embodiment of the present disclosure may form an overlapping region corresponding to the black matrix by overlapping three color filters.

[0291] In some examples, as shown in FIG. 15, the size of the first overlap region OP1 in the second direction is larger than the size of the second overlap region OP2 in the second direction, and the size of the second overlap region OP2 in the second direction is larger than the size of the third overlap region OP3 in the second direction.

[0292] In some examples, as shown in FIG. 15, the size range of the first overlap region OP1 in the second direction is 400-600 nanometers, the size range of the second overlap region OP2 in the second direction is 250-350 nanometers, and the size range of the third overlap region OP3 in the second direction is 100-200 nanometers.

[0293] In some examples, as shown in FIG. 15, the average size of the first color filter 571 in a direction perpendicular to the driving substrate 510 is larger than the average size of the second color filter 572 in a direction perpendicular to the driving substrate 510, and is less than the average size of the third color filter 573 in a direction perpendicular to the driving substrate 510.

[0294] In some examples, as shown in FIG. 15, the average size range of the first color filter 571 in a direction perpendicular to the drive substrate 510 is 2.3-2.6 microns, the average size range of the second color filter 572 in a direction perpendicular to the drive substrate 510 is 1.7-1.95 microns, and the average size range of the third color filter 573 in a direction perpendicular to the drive substrate 510 is 2.3-2.7 microns.

[0295] In some examples, as shown in FIG. 15, the ratio of the difference between the average size of the first color filter 571 in a direction perpendicular to the driving substrate 510 and the average size of the second color filter 572 in a direction perpendicular to the driving substrate 510 to the difference between the average size of the first color filter 571 in a direction perpendicular to the driving substrate 510 and the average size of the third color filter 573 in a direction perpendicular to the driving substrate 510 is in the range of 2-3.

[0296] In some examples, as shown in Figures 10 and 15, the first color filter 571 includes a first edge portion 571A, a second edge portion 571B, and an intermediate portion 571M located between the first edge portion 571A and the second edge portion 571B, and the average size of the intermediate portion 571M in a direction perpendicular to the driving substrate 510 is less than the average size of the first edge portion 571A in a direction perpendicular to the driving substrate 510 and the average size of the second edge portion 571B in a direction perpendicular to the driving substrate 510.

[0297] In some examples, as shown in FIG. 15, the first color filter 571 includes a first contact surface 571C in contact with the second color filter 572, the second color filter 572 includes a second contact surface 572C in contact with the third color filter 573, and the third color filter 573 includes a third contact surface 573C in contact with the first color filter 571, and the size of the first contact surface in a first direction perpendicular to the driving substrate 510 is equal to the size of the second contact surface in the first direction and less than the size of the third contact surface in the first direction.

[0298] In some examples, as shown in FIG. 15 , the distance between the first color filter 571 and the surface of the driving substrate 510 away from the anode layer 520 is greater than the distance between the third color filter 573 and the surface of the driving substrate 510 away from the anode layer 520, and is less than the distance between the second color filter 572 and the surface of the driving substrate 510 away from the anode layer 520.

[0299] In some examples, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter, as shown in Figure 15. Of course, the embodiments of the present disclosure are not limited thereto, and the first color filter, the second color filter, and the third color filter may be color filters of other colors.

[0300] In some instances, the material of color film layer 570 may include a desiccant to prevent the effects of external water or oxygen penetrating the membrane layers below the color film layer.

[0301] In some examples, the color film layer 570 includes elemental aluminum.

[0302] At least one embodiment of the present disclosure further provides a display substrate. Fig. 16 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. As shown in Fig. 16, the display device 900 includes a plurality of pixel units PU arranged in an array in a display area 910, and at least one of the plurality of pixel units PU may include one of the driving circuits and one of the anodes.

[0303] 16 , the display device 900 further includes a row driving circuit 200 fabricated in a base, and the row driving circuit 200 is configured to provide a first scanning signal SCAN1, a second scanning signal SCAN2 and an emission control signal EN to driving circuits of a plurality of pixel units PU in the display device 900. For example, the row driving circuit 200 is provided in a peripheral area 920 surrounding the display area 910.

[0304] At least one embodiment of the present disclosure further provides a display substrate. Fig. 17 is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in Fig. 17, the display substrate 500 includes a driving substrate 510, which includes a driving circuit 514, which is electrically connected to an anode 525 and is used to drive a light-emitting functional layer 540 in contact with the anode 525 to emit light. In addition, the structures of the anode, the light-emitting functional layer, the package layer, etc. in the display substrate shown in Fig. 17 can use the related designs of the display substrate according to the above embodiment.

[0305] 17, the driving substrate 510 includes a transistor T, which includes a gate electrode G, a source electrode S, and a drain electrode D. The three electrodes correspond to three electrode connection parts. For example, the gate electrode G is electrically connected to the gate electrode connection part 610g, the source electrode S is electrically connected to the source electrode connection part 610s, and the drain electrode D is electrically connected to the drain electrode connection part 610d. For example, the three electrodes are all electrically connected to the three electrode connection parts through tungsten vias 605.

[0306] For example, as shown in FIG. 17, the source electrode connection 610s is electrically connected to the anode 525 through a tungsten via. For example, the source electrode connection 610s is electrically connected to the metal reflective layer 593 through a tungsten via, and the anode 525 is electrically connected to the metal reflective layer 593 through a via 624a in the inorganic insulating layer 624. When the transistor T is in a conductive state, an electric signal provided by a power line can be transmitted to the anode 525 through the source electrode S of the transistor T, the source electrode connection 610s, and the metal reflective layer 593. Since a voltage difference is formed between the anode 525 and the cathode 550, an electric field is formed between them, and holes and electrons are injected into the light-emitting functional layer 540, and the light-emitting functional layer 540 emits light under the action of the electric field. As can be understood, in the transistor T, the positions of the source electrode S and the drain electrode D may be exchanged with each other (correspondingly, the positions of the source electrode connection 610s and the drain electrode connection 610d may also be exchanged with each other).

[0307] For example, the materials of the gate electrode connection portion 610g, the source electrode connection portion 610s, and the drain electrode connection portion 610d may include a metal material. For example, as shown in FIG. 17, an anti-oxidation layer 607 may be provided on at least one side (e.g., upper side and / or lower side) of each of the gate electrode connection portion 610g, the source electrode connection portion 610s, and the drain electrode connection portion 610d, thus effectively preventing these electrode connection portions from being oxidized and improving their conductivity.

[0308] For example, as shown in FIG. 17 , the display substrate 500 further includes a pixel definition layer 530 for defining an organic light-emitting functional layer 540 within its pixel aperture 535, thereby avoiding crosstalk between adjacent sub-pixels.

[0309] 17, the via 624a in the inorganic insulating layer 624 may be provided between the anode 525 and the edge region of the metal reflective layer 593. For example, in some examples, the orthogonal projection of the light-emitting functional layer 540 on the driving substrate 510 and the orthogonal projection of the via 624a on the driving substrate 510 are both within the orthogonal projection of the metal reflective layer 593 on the driving substrate 510, and the orthogonal projection of the light-emitting functional layer 540 on the driving substrate 510 and the orthogonal projection of the via 624a on the driving substrate 510 do not overlap, so that when the metal reflective layer reflects the light emitted by the light-emitting functional layer 540, the via 624a has almost no effect on the reflection process.

[0310] Fig. 18 is an equivalent schematic diagram of a driving circuit of a display substrate according to an embodiment of the present disclosure, and Fig. 19 is a plan view schematic diagram of the driving circuit of a display substrate according to an embodiment of the present disclosure. As shown in Fig. 18 and Fig. 19, the driving circuit 514 includes a driving transistor 140, a first transistor 110, a second transistor 120, and a third transistor 130. It should be noted that in some embodiments, the driving circuit may not include the third transistor 130, and the embodiments of the present disclosure are not limited thereto.

[0311] For example, the driving transistor 140 includes a control pole 143, a first pole 141, and a second pole 142, and the driving transistor 140 is configured to control a driving current for driving the light-emitting element LE to emit light, which flows through the first pole 141 of the driving transistor 140 and the second pole 142 of the driving transistor 140, according to the voltage of the control pole 143 of the driving transistor 140. The light-emitting element LE can emit light of different intensities according to the magnitude of the driving current.

[0312] In addition, the source and drain structures of the transistors used in the embodiments of the present disclosure may be symmetrical, so that the source and drain structures may be the same. In the embodiments of the present disclosure, in order to distinguish between the two poles of the transistors excluding the gate, one pole is directly described as the first pole and the other pole as the second pole, and therefore, in the embodiments of the present disclosure, the first pole and the second pole of all or some of the transistors may be exchanged with each other as necessary. For example, the first pole of the transistor described in the embodiments of the present disclosure may be the source and the second pole may be the drain, or the first pole of the transistor may be the drain and the second pole may be the source. In the following embodiments, the first pole of the transistor is described as the drain and the second pole is described as the source, and detailed description is omitted.

[0313] For example, the first transistor 110 is connected to the control pole 143 of the drive transistor 140 and is configured to write a data signal DATA to the control pole 143 of the drive transistor 140 in response to a first scan signal SCAN1.

[0314] For example, the second transistor 120 is connected to the control pole 143 of the driving transistor 140 and is configured to write a data signal DATA to the control pole 143 of the driving transistor 140 in response to a second scan signal SCAN2.

[0315] For example, the third transistor 130 is connected to the first electrode 141 of the driving transistor 140, and is configured to apply the first power supply voltage ELVDD to the first electrode 141 of the driving transistor 140 in response to the light emission control signal EN. For example, the first power supply voltage ELVDD in the embodiment of the present disclosure is a high-level voltage, for example, the first power supply voltage ELVDD is 5V.

[0316] As shown in FIG. 18, in some embodiments, the first pole 111 (e.g., a drain) of the first transistor 110 and the first pole 121 (e.g., a drain) of the second transistor 120 are connected to obtain a common electrode, which is connected to the control pole 143 of the driving transistor 140 via the common electrode.

[0317] In the above embodiment, a first scanning signal line SL1, a second scanning signal line SL2, a data line DL, a first power supply voltage line VL1 and an emission control line EL are further provided to provide corresponding electrical signals. The control pole 113 of the first transistor 110 is configured to receive a first scanning signal SCAN1 from the first scanning signal line SL1, and the second pole 112 (e.g., source) of the first transistor 110 is configured to receive a data signal DATA from the data line DL. The control pole 123 of the second transistor 120 is configured to receive a second scanning signal SCAN2 from the second scanning signal line SL2, and the second pole 122 (e.g., source) of the second transistor 120 is configured to receive a data signal DATA from the data line DL. A control pole 133 of the third transistor 130 is configured to receive an emission control signal EN from the emission control line EL, a first pole 131 (e.g., a drain) of the third transistor 130 is configured to receive a first power supply voltage ELVDD from the first power supply voltage line VL1, and a second pole 132 (e.g., a source) of the third transistor 130 is connected to a first pole 141 (e.g., a drain) of the drive transistor 140.

[0318] The second electrode 142 (e.g., a source) of the driving transistor 140 is configured to be connected to the first electrode of the light-emitting element LE. For example, if the light-emitting element LE is an OLED, the second electrode 142 of the driving transistor 140 may be connected to the anode of the OLED. For example, the second electrode of the light-emitting element LE is configured to receive a fourth power supply voltage VCOM. For example, the fourth power supply voltage VCOM in the embodiment of the present disclosure is a low-level voltage.

[0319] For example, in the embodiments of the present disclosure, the light-emitting element LE may use an OLED, and when a plurality of pixel units constitute a pixel array of a display panel, the second electrodes (e.g., cathodes) of the plurality of light-emitting elements OLED in the plurality of pixel units may be electrically connected, for example, respectively connected to the same electrode or integrally formed, to receive a fourth power supply voltage VCOM, that is, the plurality of light-emitting elements OLED in the plurality of pixel units use a cathode common connection scheme.

[0320] For example, the light-emitting element OLED may be of various types, such as top emission type, bottom emission type, etc., and may emit red light, green light, blue light, or white light, etc., and the embodiments of the present disclosure are not limited thereto.

[0321] For example, as shown in FIG. 18, the driving circuit further includes a storage capacitor CST, which stores a data signal DATA written to the control electrode 143 of the driving transistor 140, so that the driving transistor 140 can control the magnitude of the driving current for driving the light-emitting element LE according to the voltage of the stored data signal DATA. A first electrode of the storage capacitor CST is connected to the control electrode 143 of the driving transistor 140, and a second electrode of the storage capacitor CST is configured to receive a third power supply voltage AVSS. For example, the third power supply voltage AVSS in the embodiment of the present disclosure is a low-level voltage. Note that, in the embodiment of the present disclosure, the third power supply voltage AVSS may be the same as the fourth power supply voltage VCOM, for example, the third power supply voltage AVSS and the fourth power supply voltage VCOM may both be grounded, and the embodiment of the present disclosure is not limited thereto.

[0322] As shown in FIG. 18, in some embodiments of the present disclosure, the first transistor 110 may use a P-type MOS transistor, and the second transistor 120, the third transistor 130 and the driving transistor 140 may use N-type MOS transistors, for example, the first transistor 110, the second transistor 120, the third transistor 130 and the driving transistor 140 are formed in the base.

[0323] For example, as shown in FIG. 18, the third electrode of the first transistor 110 is configured to receive the second power supply voltage VDD, for example, the third electrode of the first transistor 110 is connected to the second power supply voltage line VL2 and receives the second power supply voltage VDD.

[0324] For example, the third electrodes of the second transistor 120, the third transistor 130, and the driving transistor 140 are configured to be grounded (GND). In the embodiment of the present disclosure, the third electrode of one transistor is a pole facing the control electrode (gate) 113 of the transistor, and each of the following embodiments is similar to this, so detailed description will be omitted.

[0325] In the embodiment of the present disclosure, the first transistor 110 and the second transistor 120 use MOS transistors having opposite semiconductor types, so that the first transistor 110 and the second transistor 120 form a transmission gate switch having complementary characteristics. In this case, for example, the first scanning signal SCAN1 provided to the first transistor 110 and the second scanning signal SCAN2 provided to the second transistor 120 may be opposite in phase to each other, thus ensuring that one of the first transistor 110 and the second transistor 120 is always in a conductive state at the same time, thereby transmitting the data signal DATA to the storage capacitor CST without voltage loss, thereby improving the reliability and stability of the driving circuit.

[0326] 19, in the embodiment of the present disclosure, the direction from the first pole 111 of the first transistor 110 to the second pole 112 of the first transistor 110 is called a first direction D1, the direction from the first pole 121 of the second transistor 120 to the second pole 122 of the second transistor 120 is called a second direction D2, the direction from the first pole 131 of the third transistor 130 to the second pole 132 of the third transistor 130 is called a third direction D3, and the direction from the first pole 141 of the driving transistor 140 to the second pole 142 of the driving transistor 140 is called a fourth direction D4. Note that the first direction in FIGS. 1 to 15 is different from the first direction in this embodiment, and the second direction in FIGS. 1 to 15 may be the same as or different from the second direction in this embodiment.

[0327] For example, at least one of the first direction D1 and the second direction D2 crosses the fourth direction D4. For example, when the driving circuit includes the third transistor 130, at least one of the first direction D1, the second direction D2, and the third direction D3 crosses the fourth direction D4. For example, the fourth direction D4 is a horizontal direction from left to right in FIG. 19.

[0328] In the driving circuit, since the size of the driving transistor 140 is generally larger than that of the switching transistors (e.g., the first transistor 110, the second transistor 120 and the third transistor 130), when laying out the position of the transistors, the driving transistor 140 may be arranged along the fourth direction D4, and at least one of the first direction D1, the second direction D2 and the third direction D3 may intersect with the fourth direction D4, so that the layout of the four transistors can be made more compact, thereby reducing the layout area occupied by the display substrate 500, and thereby the display substrate 500 can more easily achieve high PPI.

[0329] In some embodiments of the present disclosure, the first direction D1 and the second direction D2 may all intersect with the fourth direction D4, and for example, the first direction D1, the second direction D2, and the third direction D3 may all intersect with the fourth direction D4. For example, as shown in FIG. 19, the fourth direction D4 is a horizontal direction, and the first direction D1, the second direction D2, and the third direction D3 are all vertical directions perpendicular to the horizontal direction in FIG.

[0330] For example, in some implementations of the present disclosure, the first direction D1 and the second direction D2 are all perpendicular to the fourth direction D4, and for example, the first direction D1, the second direction D2 and the third direction D3 are all perpendicular to the fourth direction D4. In this way, when a plurality of pixel units in a display area of ​​a display device are arranged in a plurality of rows and a plurality of columns, the layout of the display substrate 500 can be made more compact, so that the layout area occupied by the display substrate 500 can be further reduced, and so that the display substrate 500 can more easily achieve a high PPI.

[0331] For example, as shown in FIG. 19, the first transistor 110 includes a first active region 114 extending along a first direction D1, and the first active region 114 includes a first pole 111 of the first transistor 110, a second pole 112 of the first transistor 110, and a channel region formed between the first pole 111 of the first transistor 110 and the second pole 112 of the first transistor 110.

[0332] The second transistor 120 includes a second active region 124 extending along the second direction D2, and the second active region 124 includes a first pole 121 of the second transistor 120, a second pole 122 of the second transistor 120, and a channel region formed between the first pole 121 of the second transistor 120 and the second pole 122 of the second transistor 120.

[0333] The third transistor 130 includes a third active region 134 extending along a third direction D3, and the third active region 134 includes a first pole 131 of the third transistor 130, a second pole 132 of the third transistor 130, and a channel region formed between the first pole 131 of the third transistor 130 and the second pole 132 of the third transistor 130.

[0334] The driving transistor 140 includes a fourth active region 144 extending along a fourth direction D4, and the fourth active region 144 includes a first pole 141 of the fourth transistor 140, a second pole 142 of the fourth transistor 140, and a channel region formed between the first pole 141 of the fourth transistor 140 and the second pole 142 of the fourth transistor 140.

[0335] For example, the base of the display substrate 500 according to the embodiment of the present disclosure is silicon-based, and the first active region 114, the second active region 124, the third active region 134 and the fourth active region 144 are all silicon-based doped regions, which are obtained, for example, by an ion implantation process or an ion diffusion process, and in the case of amorphous silicon, P-type doping may be achieved by boron (B) doping, and N-type doping may be achieved by phosphorus (P) or arsenic (As) doping, which is not limited in the embodiment of the present disclosure.

[0336] For example, in some embodiments of the present disclosure, the doping types of the first active region 114 and the second active region 124 are opposite, e.g., the doping type of the first active region 114 is P-type and the doping type of the second active region 124 is N-type.

[0337] 19, two ends of the first active region 114 and two ends of the second active region 124 are aligned with each other in the fourth direction D4, for example, the two ends of the first active region 114 and the second active region 124 are adjacent to each other, thereby simplifying the layout design of the display substrate 500.

[0338] A connection line between one edge of the first active region 114 along the first direction D1 and one edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4, and a connection line between another edge of the first active region 114 along the first direction D1 and another edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4. In this way, the layout design of the display substrate 500 can be simplified.

[0339] Compared with a silicon-based analog CMOS circuit used for non-display applications, the driving current for the light emitting element LE in the display substrate 500 according to the embodiment of the present disclosure is smaller by 1 to 2 orders of magnitude.

number

[0340] As can be seen from the above formula, in order to achieve a low driving current, it is necessary to increase the L value when designing the size of the driving transistor 140, which is disadvantageous in reducing the layout area of ​​the display substrate 500 using the driving transistor 140.

[0341] The driving circuit 514 according to some embodiments of the present disclosure can improve or avoid the above problem by adjusting the relative relationship of the doping concentrations of the first active region 114, the second active region 124, the third active region 134 and the fourth active region 144.

[0342] For example, the doping concentration of the fourth active region 144 is less than the doping concentration of the third active region 134. For example, the doping concentration of the third active region 134 is about 10 17 cm -3 and the doping concentration of the fourth active region 144 is about 10 13 cm -3 and the doping concentration of the fourth active region 144 is four orders of magnitude smaller than that of the third active region 134. In the embodiment of the present disclosure, by reducing the doping concentration of the fourth active region 144, the driving current output by the driving transistor 140 can be made smaller and the change in the output driving current can be made more gradual without changing the size of the driving transistor 140 (e.g., without changing the aspect ratio W / L), so that the gray scale value can be more uniform when the driving circuit using the driving transistor 140 drives the light emitting element LE (e.g., OLED) to emit light.

[0343] For example, in the display substrate 500 according to some embodiments of the present disclosure, the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region 134 .

[0344] For example, the doping concentration of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region. For example, the doping concentration of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region. 20 cm -3 where the doping concentration of the first active region 114 and the second active region 124 is three orders of magnitude greater than the doping concentration of the third active region 134 .

[0345] 18, the first transistor 110 and the second transistor 120 are used as switching transistors in the driving circuit, so they need to have good switching characteristics. When the doping concentration of the first active region 114 or / and the second active region 124 is high, a large driving current can be obtained, and the change of the driving current is faster, so that the first transistor 110 or / and the second transistor 120 have better switching characteristics.

[0346] For example, in the embodiment of the present disclosure, the first transistor 110 is a MOS transistor of a first semiconductor type, the second transistor, the third transistor and the driving transistor are all MOS transistors of a second semiconductor type, and the first semiconductor type and the second semiconductor type are opposite, for example, the first semiconductor type is P-type and the second semiconductor type is N-type, and the embodiment of the present disclosure is not limited thereto.

[0347] As shown in FIG. 19, a display substrate 500 according to some embodiments of the present disclosure further includes a first scanning signal line SL1 for transmitting a first scanning signal SCAN1 and a second scanning signal line SL2 for transmitting a second scanning signal SCAN2, and the first scanning signal line SL1 and the second scanning signal line SL2 are arranged in parallel.

[0348] For example, the first scan signal line SL1 is connected to the control pole 113 of the first transistor 110 and provides a first scan signal SCAN1, and the second scan signal line SL2 is connected to the control pole 123 of the second transistor 120 and provides a second scan signal SCAN2.

[0349] For example, the extension directions of the first scanning signal line SL1 and the second scanning signal line SL2 are both parallel to the fourth direction D4. The orthogonal projection of the first scanning signal line SL1 at the base and the orthogonal projection of the second scanning signal line SL2 at the base are parallel to each other, for example, both of them are parallel to the fourth direction D4. For example, the region where the orthogonal projection of the driving circuit 514 on the base 512 is located is the pixel region, and the first scanning signal line SL1 and the second scanning signal line SL2 are located in parallel on one side of the pixel region.

[0350] As shown in FIG. 19, the display substrate 500 according to some embodiments of the present disclosure further includes a data line DL for transmitting a data signal DATA, and the orthogonal projection of the second scanning signal line SL2 at the base and the orthogonal projection of the data line DL at the base at least partially overlap. For example, the second scanning signal line SL2 and the data line DL overlap in a direction perpendicular to the base. For example, as shown in FIG. 19, the plane on which FIG. 19 is located can be regarded as the plane on which the base is located, and in this case, being perpendicular to the base means being perpendicular to the plane on which FIG. 19 is located. In the embodiments of the present disclosure, the second scanning signal line SL2 and the data line DT overlap in a direction perpendicular to the base, so that the data line DL does not occupy an additional layout area, which can further reduce the layout area occupied by the display substrate 500, and is further advantageous in realizing a high PPI.

[0351] As shown in FIG. 19, a display substrate 500 according to some embodiments of the present disclosure further includes a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD and an emission control line EL for transmitting an emission control signal EN.

[0352] For example, the extension direction of the first power supply voltage line VL1 and a portion of the emission control line EL is parallel to the fourth direction D4, and the orthogonal projections of the first scanning signal line SL1, the second scanning signal line SL2, the first power supply voltage line VL1, and the emission control line EL at the base are sequentially arranged along a direction perpendicular to the fourth direction D4.

[0353] In addition, in the display substrate 500 according to some embodiments of the present disclosure, as shown in FIG. 19, the orthogonal projection at the base of the first power supply voltage line VL1 is located between the orthogonal projection at the base of the second scanning signal line SL2 and the orthogonal projection at the base of the emission control line EL, the first power supply voltage ELVDD transmitted by the first power supply voltage line VL1 is a DC signal, and the second scanning signal SCAN2 transmitted by the second scanning signal line SL2 and the emission control signal EN transmitted by the emission control line EL are both jump signals, so that the above arrangement can effectively shield the mutual interference between the second scanning signal SCAN2 and the emission control signal EN.

[0354] 19, the display substrate 500 according to some embodiments of the present disclosure further includes a second power supply voltage line VL2 for transmitting a second power supply voltage VDD, and the third electrode of the first transistor 110 is electrically connected to the second power supply voltage line VL2 to receive the second power supply voltage VDD. For example, the second power supply voltage VDD in the embodiments of the present disclosure is a high-level voltage, for example, the second power supply voltage is 5V.

[0355] For example, the first transistor 110 is a P-type MOS transistor, and the channel region is P-type doped. As shown in Fig. 19, a third electrode facing the control electrode (gate) 113 of the first transistor 110 receives a second power supply voltage VDD. For example, the second transistor 120, the third transistor 130, and the driving transistor 140 are all N-type MOS transistors, and the channel regions are N-type doped, and the third electrodes of the second transistor 120, the third transistor 130, and the driving transistor 140 are all configured to be grounded (GND).

[0356] For example, the orthogonal projection at the base of the second power supply voltage line VL2 is located between the orthogonal projection at the base of the first power supply voltage line VL1 and the orthogonal projection at the base of the light emission control line EL, and the extension direction of a portion of the second power supply voltage line VL2 is parallel to the fourth direction D4.

[0357] 19, the second power supply voltage line VL2 has one bending region when it extends along the fourth direction D4, and the emission control line EL also has one bending region when it extends along the fourth direction D4, and the bending directions of the second power supply voltage line VL2 and the emission control line EL are different. This wiring form can leave a layout space for the first adapter electrode AE1, which will be described later.

[0358] For example, as shown in FIG. 19, the first transistor 110 and the second transistor 120 are both arranged between the second scanning signal line SL2 and the light-emitting control line EL, and the first transistor 110 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2, and the second transistor 120 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2.

[0359] For example, the orthogonal projection at the base of the first active region 114 of the first transistor 110 and the orthogonal projection at the base of the second active region 124 of the second transistor 120 are both between the orthogonal projection at the base of the second scanning signal line SL2 and the orthogonal projection at the base of the light emission control line EL.

[0360] The orthogonal projection of the base of the first active area 114 of the first transistor 110 intersects with the orthogonal projection of the base of the first power supply voltage line VL1, and the orthogonal projection of the base of the first active area 114 of the first transistor 110 intersects with the orthogonal projection of the base of the second power supply voltage line VL2.

[0361] The orthogonal projection of the base of the second active area 124 of the second transistor 120 intersects with the orthogonal projection of the base of the first power supply voltage line VL1, and the orthogonal projection of the base of the second active area 124 of the second transistor 120 intersects with the orthogonal projection of the base of the second power supply voltage line VL2.

[0362] As shown in FIG. 19, the display substrate 500 according to some embodiments of the present disclosure further includes a first adapter electrode AE1 provided on a first side of the emission control line EL, and a second adapter electrode AE2 extending from the first side of the emission control line EL to a second side of the emission control line EL.

[0363] For example, the orthogonal projection at the base of the second adaptor electrode AE2 intersects with the orthogonal projection at the base of the emission control line EL. The two ends of the first adaptor electrode AE1 are respectively electrically connected to the first pole 111 of the first transistor 110 and the first pole 121 of the second transistor 120, the first adaptor electrode AE1 is electrically connected to the second adaptor electrode AE2, and the second adaptor electrode AE2 is electrically connected to the control pole 143 of the driving transistor 140.

[0364] For example, the extension direction of the second adaptor electrode AE2 is perpendicular to the extension direction of the first adaptor electrode AE1 and perpendicular to the fourth direction D4.

[0365] Since the second adaptor electrode AE2 is connected to the storage capacitor CST, the level of the second adaptor electrode AE2 may fluctuate greatly during the operation of the driving circuit, and the fluctuation may cause crosstalk to the first power supply voltage line VL1 and generate noise. In the display substrate 500 according to the embodiment of the present disclosure, the second power supply voltage line VL2 is used to separate the first power supply voltage line VL1 and the second adaptor electrode AE2, thereby reducing the crosstalk to the first power supply voltage line VL1 caused by the level fluctuation in the second adaptor electrode AE2 and blocking the noise.

[0366] In addition, in the display substrate 500 according to some embodiments of the present disclosure, the first active area 114 of the first transistor 110 and the second active area 124 of the second transistor 120 are extended to leave a wiring path for the second power supply voltage line VL2.

[0367] For example, the layout size of the driving circuit (rectangular shape) according to the embodiment of the present disclosure is about 4.5 um×2.9 um.

[0368] 20A-20E each show a plan view of the layout of each layer of the display substrate 500 shown in FIG.

[0369] FIG. 20A shows the first active area 114 of the first transistor 110, the second active area 124 of the second transistor 120, the third active area 134 of the third transistor 130, and the fourth active area 144 of the drive transistor 140, and the layer shown in FIG. 4A may be referred to as the effective display (AA) layer.

[0370] 20B shows the control pole 113 of the first transistor 110, the control pole 123 of the second transistor 120, the control pole 133 of the third transistor 130, and the control pole 143 of the driving transistor 140. The layer shown in FIG. 4B may be called the first conductive layer, and the first conductive layer will be further described below. For example, the material of the first conductive layer may use polycrystalline silicon.

[0371] Fig. 20C shows a first power supply voltage line VL1, a second power supply voltage line VL2, a light emission control line EL, a data line DL, a ground line GND, and a first adaptor electrode AE1, etc. The layer shown in Fig. 20C may be called a first metal layer (metal1).

[0372] Fig. 20D shows a second adapter electrode AE2, an electrode connecting the first scanning signal line SL1 and the first transistor 110, and an electrode connecting the second scanning signal line SL2 and the second transistor 120. The layer shown in Fig. 20D may be called a second metal layer (metal2).

[0373] FIG. 20E shows the first scanning signal line SL1 and the second scanning signal line SL2, and the layer shown in FIG. 20E may be called a third metal layer (metal3).

[0374] It should be noted that in the embodiment of the present disclosure, for clarity of illustration, the storage capacitor CST is not shown in FIG. 19, and the storage capacitor CST shown in FIG. 18 will be further described below with reference to FIGS. 21-23E.

[0375] As shown in Fig. 21, a region 850 shown in Fig. 21 is a region in which a storage capacitor CST is provided. For clarity of illustration, not all structures are shown with corresponding reference symbols, and the omitted parts may be referred to with the corresponding reference symbols in Fig. 19.

[0376] FIG. 22 is a layout diagram of the storage capacitor CST, FIGS. 23A to 23D are plan views of the layout of each corresponding layer in FIG. 22, and FIG. 23E is a schematic cross-sectional view of the storage capacitor CST.

[0377] Figure 22 shows a four-layer structure, which is the third metal layer metal3, the fourth metal layer metal4, the auxiliary metal layer metal4', and the fifth metal layer metal5, and further shows the first via V1 and the second via V2. Below, the first via V1 and the second via V2 will be explained with reference to a schematic cross-sectional diagram, and a detailed explanation will be omitted here.

[0378] For example, Fig. 23A shows a third metal layer metal3, which is the same layer as that shown in Fig. 20E. As shown in Fig. 23A, the third metal layer metal3 includes two parts, an electrode 811 serving as a first pole of the first capacitor C1, and an electrode 812 serving as a second pole of the first capacitor C1. For example, the electrode 811 is configured to receive a third power supply voltage AVSS, and the electrode 812 is electrically connected to an electrode 840 in the fifth metal layer metal5 through a second via V2, thereby realizing an electrical connection with the control pole 143 of the driving transistor 140.

[0379] The electrode 811 includes a plurality of strip electrodes, the electrode 812 includes a plurality of strip electrodes, the plurality of strip electrodes of the electrode 811 and the plurality of strip electrodes of the electrode 812 are alternately arranged, and the electrodes 811, 812 and the space between them form a first capacitor C1. For example, the first capacitor C1 is a part of a storage capacitor CST, and for example, the first capacitor C1 and a second capacitor C2 below are connected in parallel to form the storage capacitor CST.

[0380] For example, FIG. 23B shows an electrode 820 located on the fourth metal layer metal4, for example, the electrode 820 is a planar electrode, and the electrode 820 functions as a first pole of the second capacitor C2.

[0381] For example, FIG. 23C shows an electrode 830 located on the auxiliary metal layer metal4', for example, the electrode 830 is a planar electrode, and the electrode 830 functions as the second pole of the second capacitor C2.

[0382] For example, FIG. 23D shows an electrode 840, a first via V1, and a second via V2 located on the fifth metal layer metal5.

[0383] Fig. 23E shows a schematic cross-sectional view of a partial structure of the storage capacitor CST, and as shown in Fig. 23E, an electrode 840 located in the fifth metal layer metal5 is electrically connected to an electrode 830 located in the auxiliary metal layer metal4' through a first via V1, and the electrode 840 located in the fifth metal layer metal5 is electrically connected to an electrode 812 located in the third metal layer metal3 through a second via V2. Note that, as shown in Fig. 23E, the second via V2 passes through the fourth metal layer metal4.

[0384] As shown in FIG. 23E, electrode 820 located on the fourth metal layer metal4, electrode 830 located on the auxiliary metal layer metal4', and the space between them form a second capacitor C2, and for example, the first capacitor C1 and the second capacitor C2 are connected in parallel to jointly form a storage capacitor CST.

[0385] In an embodiment of the present disclosure, as shown in FIG. 23E, an auxiliary metal layer metal4' is provided between the fourth metal layer metal4 and the fifth metal layer metal5, thereby making the distance between the fourth metal layer metal4 and the auxiliary metal layer metal4', for example, approximately 1 / 10 of the distance between the fourth metal layer metal4 and the fifth metal layer metal5, thereby effectively increasing the capacitance value per unit area of ​​the second capacitor C2.

[0386] 18 and 19, an embodiment of the present disclosure further provides a display substrate 500 including a base and at least one driving circuit formed on the base. The driving circuit includes a driving transistor 140, a first transistor 110, a second transistor 120 and a third transistor 130.

[0387] The driving transistor 140 includes a control pole 143, a first pole 141 and a second pole 142, and is configured to control a driving current for driving the light-emitting element LE to emit light, which flows through the first pole 141 of the driving transistor 140 and the second pole 142 of the driving transistor 140, depending on the voltage of the control pole 143 of the driving transistor 140.

[0388] The first transistor 110 is connected to the control pole 143 of the driving transistor 140 and configured to write a data signal DATA to the control pole 143 of the driving transistor 140 in response to a first scan signal SCAN1. The second transistor 120 is connected to the control pole 143 of the driving transistor 140 and configured to write a data signal DATA to the control pole 143 of the driving transistor 140 in response to a second scan signal SCAN2. The third transistor 130 is connected to the first pole 141 of the driving transistor 140 and configured to apply a first power supply voltage ELVDD to the first pole 141 of the driving transistor 140 in response to an emission control signal EN.

[0389] The display substrate 500 further includes a first scanning signal line SL1 for transmitting a first scanning signal SCAN1, a second scanning signal line SL2 for transmitting a second scanning signal SCAN2, a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD, and an emission control line EL for transmitting an emission control signal EN, and the orthogonal projections of the first scanning signal line SL1, the second scanning signal line SL2, the first power supply voltage line VL1 and the emission control line EL at a base are sequentially arranged along a direction perpendicular to the fourth direction D4.

[0390] For example, the direction from the first pole 111 of the first transistor 110 to the second pole 112 of the first transistor 110 is a first direction D1, the direction from the first pole 121 of the second transistor 120 to the second pole 122 of the second transistor 120 is a second direction D2, the direction from the first pole 131 of the third transistor 130 to the second pole 132 of the third transistor 130 is a third direction D3, and the direction from the first pole 141 of the driving transistor 140 to the second pole 142 of the driving transistor 140 is a fourth direction D4, and the first direction D1, the second direction D2, and the third direction D3 all intersect with the fourth direction D4. For example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4.

[0391] A display substrate according to at least one embodiment of the present disclosure can achieve a sub-pixel area of ​​5.45um x 13.6um through an optimized layout wiring design process during design, thereby achieving high resolution (PPI) and optimized pixel circuit array layout, and having a better display effect.

[0392] FIG. 24A is a block diagram of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 24A, the display substrate 10 includes a plurality of sub-pixels 100 distributed in an array, a plurality of scan lines 11, and a plurality of data lines 12. Each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element. The plurality of scan lines 11 and the plurality of data lines 12 cross each other to define a plurality of pixel regions distributed in an array in the display area, and a pixel circuit of one sub-pixel 100 is provided in each pixel region. The pixel circuit is, for example, a general pixel circuit, such as a 2T1C (i.e., two transistors and one capacitor) pixel circuit, an nTmC (n, m are positive integers) pixel circuit such as 4T2C, 5T1C, 7T1C, etc., and in different embodiments, the pixel circuit may further include a compensation sub-circuit, the compensation sub-circuit may include an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include a transistor, a capacitor, etc. For example, the pixel circuit may further include a reset circuit, a light emission control sub-circuit, and a detection circuit, etc., if necessary. For example, the display substrate may further include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in the non-display area. The gate driving sub-circuit 13 is connected to the pixel circuit via the scan line 11 to provide various scanning signals, and the data driving sub-circuit 14 is connected to the pixel circuit via the data line 12 to provide data signals. The positional relationship between the gate driving sub-circuit 13, the data driving sub-circuit 14, the scan line 11 and the data line 12 on the display substrate shown in Figure 24A is merely exemplary, and the actual arrangement positions can be designed as needed.

[0393] For example, the display substrate 10 may further include a control circuit (not shown). For example, the control circuit is configured to control the data driving sub-circuit 14 to apply the data signal and control the gate driving sub-circuit to apply the scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and a memory, the memory including executable code, and the processor executes the executable code to perform the detection method.

[0394] For example, a processor may be a central processing unit (CPU) or other form of processing device having data processing and / or instruction execution capabilities including, for example, a microprocessor, a programmable logic controller (PLC), and the like.

[0395] For example, the storage device may include one or more computer program products, which may include various forms of computer readable storage media, such as, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer readable storage medium, and the processor may perform the functions desired by the program instructions. Various application programs and various data may also be stored on the computer readable storage medium.

[0396] The pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a storage sub-circuit as required, and may further include a light emission control sub-circuit, a reset circuit and the like as required.

[0397] 24B shows a schematic diagram of a pixel circuit. As shown in FIG. 24B, the pixel circuit includes a data writing sub-circuit 111, a driving sub-circuit 112 and a storage sub-circuit 113.

[0398] The data write sub-circuit 111 is electrically connected to a first terminal of the storage sub-circuit 113 and configured to transmit a data signal Vd to the first terminal of the storage sub-circuit 113 in response to a control signal (first control signal SEL). A second terminal of the storage sub-circuit 113 is configured to receive, for example, a second power supply voltage VSS.

[0399] The driving sub-circuit 112 includes a control electrode 150, a first electrode 151 and a second electrode 152, where the control electrode 150 of the driving sub-circuit is electrically connected to a first terminal of the storage sub-circuit, the first electrode 151 of the driving sub-circuit 112 is configured to receive a first power supply voltage VDD, and the second electrode 152 of the driving sub-circuit 112 is electrically connected to a first node S and connected to a first electrode 121 of the light-emitting element 120. The driving sub-circuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage of the first terminal of the storage sub-circuit. The second electrode 122 of the light-emitting element 120 is configured to receive, for example, a first common voltage Vcom1.

[0400] In at least some embodiments of the present disclosure, as shown in FIG. 24B, the pixel circuit further includes a bias sub-circuit 114. The bias sub-circuit 114 includes a control terminal, a first terminal and a second terminal, the control terminal of the bias sub-circuit 114 is configured to receive a bias signal, the first terminal of the bias sub-circuit 114 is configured to receive, for example, a second power supply voltage VSS, and the second terminal of the bias sub-circuit 114 is electrically connected to a first node S. For example, the bias signal is a second common voltage Vcom2. For example, the bias signal Vcom2 is a constant voltage signal, for example, 0.8V-1V, and the bias sub-circuit 114 is in a normally open state under the action of the bias signal and is configured to provide a constant current, so that the voltage applied to the light-emitting element 120 and the data signal have a linear relationship, which contributes to realizing high-precision control over the grayscale, thereby improving the display effect. This will be further described later with reference to a specific circuit.

[0401] For example, when the data signal (voltage) Vd goes from high to low, the gray scale voltage written to the first electrode 121 of the light-emitting element 120 needs to be changed quickly, and the bias sub-circuit 114 further enables the first electrode 121 of the light-emitting element 120 to discharge charge quickly, thereby achieving better dynamic contrast.

[0402] The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure take metal-oxide semiconductor field effect transistors as an example for description. The source and drain structures of the transistors used herein may be symmetrical, so that the source and drain structures may be the same. In the embodiments of the present disclosure, in order to distinguish between the two poles of the transistors, excluding the gate, one pole is directly described as the first pole and the other pole as the second pole. In addition, the transistors can be distinguished into N-type and P-type transistors according to the characteristics of the transistors. If the transistor is a P-type transistor, the on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltage), and the off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltage), and if the transistor is an N-type transistor, the on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltage), and the off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltage).

[0403] The display substrate according to the embodiment of the present disclosure may be a rigid substrate such as a glass substrate or a silicon substrate, or may be made of a flexible material having excellent heat resistance and durability such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylic ester, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC). The embodiments of the present disclosure are described using a silicon substrate as an example, that is, the pixel structure is manufactured on a silicon substrate, but the embodiments of the present disclosure are not limited thereto.

[0404] For example, the pixel circuit includes a complementary metal oxide semiconductor circuit (CMOS circuit), i.e., the pixel circuit is fabricated on a single crystal silicon-based substrate. With the mature CMOS integrated circuit technology, the silicon-based process can achieve high precision (e.g., PPI can reach 6500 or 10000 or more).

[0405] For example, if a process variation in the display substrate causes a short circuit between the first electrode 121 and the second electrode 122 of the light-emitting element 120 in a subpixel, and the voltage of the first electrode 121 of the light-emitting element 120 is too high (e.g., the first common voltage Vcom1 is a high potential) or too low (e.g., the first common voltage Vcom1 is a low potential), a latch-up effect will be caused at the first node S, resulting in failure of the CMOS circuit, and as a result, defects such as dark lines will occur on the display substrate.

[0406] In some examples, for example, the data write sub-circuit includes a first data write transistor P1, and the driving sub-circuit includes a driving transistor N2, for example, the first data write transistor is a P-type metal-oxide semiconductor field effect transistor (PMOS), and the driving transistor N2 is an N-type metal-oxide semiconductor field effect transistor (NMOS), and the gate, the first pole, and the second pole of the driving transistor N2 respectively function as the control electrode 150, the first electrode 151, and the second electrode 152 of the driving sub-circuit 112. In this case, for example, when the first common voltage Vcom1 provided to the second electrode 122 of the light-emitting element 120 is at a low potential, and the first electrode 121 and the second electrode 122 of the light-emitting element 120 are shorted, it causes the potential of the second pole of the driving transistor directly connected to the first electrode 121 to be too low.

[0407] 24C is a schematic diagram showing the latch-up effect in the pixel circuit. The N-type active region (e.g., second pole) of the driving transistor N2, the P-type silicon-based base, the N-type well region in which the first data write transistor P1 is located, and the P-type active region (e.g., first pole) of the first data write transistor P1 form two parasitic transistors Q1 and Q2 connected to each other to form an NPNP structure. If the potential of the second pole (i.e., the first node S) of the driving transistor N2 is too low, the PN junction (emitter junction) between the second pole (N-type high-concentration doping region) and the P-type base of the driving transistor N2 will be forward biased, Q1 will be conductive, and a sufficiently large current will be provided to make the parasitic transistor Q2 conductive, which will in turn feed back the current to the parasitic transistor Q1, forming a vicious circle. Eventually, most of the current will reach VSS directly from VDD via the parasitic transistor, and will no longer be controlled by the gate voltage of the transistor, causing the failure of the CMOS pixel circuit. In addition, the latch-up effect will cause the parasitic transistor Q2 to continue to draw current from the emitter, i.e., the data line, thereby causing the failure of one column of sub-pixels connected to the data line, and causing defects such as dark lines on the display substrate, greatly impairing the display effect.

[0408] In at least some embodiments of the present disclosure, at least one subpixel further includes a resistor connected between the second electrode 152 of the driving sub-circuit 112 and the first electrode 121 of the light-emitting element 120, which can act to increase or decrease the potential of the first node S, thereby reducing or avoiding the latch-up effect, improving the reliability of the circuit, and improving the display effect.

[0409] 25A is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. As shown in FIG. 25A, the pixel circuit further includes a resistor 130, a first terminal 131 of the resistor 130 is electrically connected to the second electrode 152 of the driving sub-circuit 112, and a second terminal 132 of the resistor 130 is electrically connected to the first electrode 121 of the light-emitting element 120, i.e., the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 through the resistor 130.

[0410] For example, resistor 130 may be a fixed resistor or a variable resistor, or may have an equivalent resistor formed by other devices (eg, transistors).

[0411] For example, the resistor 130 is insulated from the control electrode 150 of the drive subcircuit 112 on the same layer, and the resistivity of the resistor is higher than the resistivity of the control electrode of the drive subcircuit, e.g., the resistivity of the resistor is 10 times or more higher than the resistivity of the control electrode.

[0412] In addition, "provided in the same layer" as described in the present disclosure means that two (or more) types of structures are formed by the same deposition process and patterned by the same patterning process, and the materials may be the same or different. For example, the precursor materials forming the multiple types of structures provided in the same layer may be the same, and the materials finally formed may be the same or different. In the present disclosure, "integral structure" means that two (or more) types of structures are formed by the same deposition process and patterned by the same patterning process, and are connected to each other, and the materials may be the same or different.

[0413] So provided, the control electrodes and resistors of the drive sub-circuits can be formed in the same patterning process, thereby providing process savings.

[0414] For example, the material of the resistor and the control electrode of the drive sub-circuit are both polysilicon materials, and the doping concentration of the resistor is less than the doping concentration of the control electrode, so the resistor has a higher resistivity than the control electrode, For example, the resistor may be intrinsic polysilicon or lightly doped polysilicon, and the control electrode is heavily doped polysilicon.

[0415] In some other examples, the materials of the control electrode and the resistor may be different. For example, the materials of the control electrode and the resistor may each include a metal and a metal oxide corresponding to the metal. For example, the metal may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combining the above metals.

[0416] In at least one embodiment of the present disclosure, the data write sub-circuit 111 may include a transmission gate circuit formed by connecting two complementary transistors in parallel, and the control signal includes two control signals in opposite phases to each other. The data write sub-circuit 111 contributes to transmitting the data signal to the first terminal of the storage sub-circuit 113 without loss by using a transmission gate structure circuit.

[0417] For example, the data write subcircuit includes a first control electrode, a second control electrode, a first terminal and a second terminal, the first control electrode and the second control electrode of the data write subcircuit are configured to receive a first control signal and a second control signal, respectively, the first terminal of the data write subcircuit is configured to receive a data signal, and the second terminal of the data write subcircuit is electrically connected to the first terminal of the storage subcircuit and configured to transmit the data signal to the first terminal of the storage subcircuit in response to the first control signal and the second control signal.

[0418] However, in the description of the embodiments of the present disclosure, the first node S does not necessarily represent an actually existing component, but represents a junction at which related circuits in a circuit diagram are connected.

[0419] In the description of the embodiments of the present disclosure, the symbol Vd may represent a data signal terminal or may represent a data signal level, the symbol SEL may represent a control signal or may represent a control signal terminal, the symbols Vcom1 and Vcom2 may represent a first common voltage and a second common voltage or may represent a first common voltage terminal and a second common voltage terminal, the symbol VDD may represent a first voltage terminal or may represent a first power supply voltage, the symbol VSS may represent a second voltage terminal or may represent a second power supply voltage. The following embodiments are similar to this, and detailed descriptions are omitted.

[0420] Figure 25B shows a circuit diagram of a specific implementation of the pixel circuit shown in Figure 24A. As shown in Figure 25B, the data write sub-circuit 111 includes a first data write transistor P1 and a second data write transistor N1 connected in parallel to each other. The first data write transistor P1 and the second data write transistor N1 are a P-type metal-oxide semiconductor field effect transistor (PMOS) and an N-type metal-oxide semiconductor field effect transistor (NMOS), respectively. The control signals include a first control signal SEL and a second control signal SEL_B in opposite phases to each other, and the gate of the first data write transistor P1 serves as a first control electrode of the data write sub-circuit and is configured to receive the first control signal SEL, and the gate of the second data write transistor N1 serves as a second control electrode of the data write sub-circuit and is configured to receive the second control signal SEL_B. A first pole of the second data write transistor N1 is electrically connected to a first pole of the first data write transistor P1, functions as a first terminal of the data write sub-circuit, and is configured to receive a data signal Vd, and a second pole of the second data write transistor N1 is electrically connected to a second pole of the first data write transistor P1, functions as a second terminal of the data write sub-circuit, and is electrically connected to a control electrode 150 of the drive sub-circuit 112.

[0421] For example, the first data write transistor P1 and the second data write transistor N1 have the same size and the same channel aspect ratio.

[0422] The data write sub-circuit 111 utilizes the complementary electrical characteristics of transistors to have a low on-resistance, whether transmitting a high level or a low level, thereby having the advantage of integrity of electrical signal transmission, and can transmit the data signal Vd to the first terminal of the storage sub-circuit 113 without loss.

[0423] 25B, the driving sub-circuit 112 includes a driving transistor N2, e.g., the driving transistor N2 is an NMOS. The gate, the first electrode, and the second electrode of the driving transistor N2 function as a control electrode, a first electrode, and a second electrode of the driving sub-circuit 112, respectively.

[0424] For example, the memory subcircuit 113 includes a memory capacitor Cst, which includes a first capacitance electrode 141 and a second capacitance electrode 142, and the first capacitance electrode 141 and the second capacitance electrode 142 function as a first terminal and a second terminal of the memory subcircuit 113, respectively.

[0425] For example, the resistor 130 includes a resistor R. For example, a PN junction is formed between the second electrode 152 of the driving sub-circuit 112 and the base substrate, and the resistance value of the resistor 130 is set so that the PN junction is turned off when the driving transistor N2 operates in a saturation region, that is, when the pixel circuit operates to drive the light-emitting element 120 to emit light. In this case, even if a short circuit occurs between the two electrodes of the light-emitting element 120, the potential of the second electrode 152 can be protected because there is a voltage drop across the resistor 130, thereby avoiding the occurrence of the latch-up effect.

[0426] For example, the light-emitting element 120 is specifically realized as an organic light-emitting diode (OLED). For example, the light-emitting element 120 may be an OLED with a top emission structure, and may emit red light, green light, blue light, or white light, etc. For example, the light-emitting element 120 is a micro OLED. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode 121 of the light-emitting element 120 is an anode of the OLED, and the second electrode 122 is a cathode of the OLED, that is, the pixel circuit is a common cathode structure. However, the embodiments of the present disclosure are not limited thereto, and the pixel circuit may be a common anode structure according to the change of the circuit structure.

[0427] For example, the bias sub-circuit 114 includes a bias transistor N3, the gate, the first pole and the second pole of which serve as the control terminal, the first terminal and the second terminal of the bias sub-circuit 114, respectively.

[0428] Figure 25C shows a signal timing diagram of the pixel circuit shown in Figure 25B, and the operation principle of the pixel circuit shown in Figure 25C will be described below with reference to the signal timing diagram shown in Figure 25B. For example, the second data write transistor, the driving transistor, and the bias transistor are all N-type transistors, and the first data write transistor is a P-type transistor, but this is not limited to the embodiments of the present disclosure.

[0429] FIG. 25C shows waveforms of each signal in two consecutive display periods T1 and T2. For example, the data signal Vd is a high gradation voltage in the display period T1 and a low gradation voltage in the display period T2.

[0430] For example, as shown in Fig. 25C, the display process of an image of each frame includes a data writing stage 1 and a light emitting stage 2. The operation process of the pixel circuit includes: in the data writing stage 1, the first control signal SEL and the second control signal SEL_B are both ON signals, the first data writing transistor P1 and the second data writing transistor N1 are conductive, and the data signal Vd is transmitted to the gate of the driving transistor N2 through the first data writing transistor P1 and the second data writing transistor N1; in the light emitting stage 2, the first control signal SEL and the second control signal SEL_B are both OFF signals, and due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst does not change, the driving transistor N2 operates in a saturated state and the current does not change, so that the light emitting element 120 is driven to emit light. When the pixel circuit goes from the display period T1 to the display period T2, the data signal Vd goes from the high gray scale voltage to the low gray scale voltage, and the bias transistor N3 generates a stable drain current controlled by the second common voltage Vcom2, which can quickly discharge the charge accumulated in the anode of the OLED when the display gray scale of the OLED needs to be changed quickly. For example, the discharge process occurs in the data writing stage 1 of the display period T2, so that in the light emission stage 2 of the display period T2, the voltage of the anode of the OLED is quickly lowered, thereby realizing a better dynamic contrast and improving the display effect.

[0431] For example, when the first node S is directly electrically connected to the light-emitting element 120, the voltage V0 is directly applied to the first electrode 121 of the light-emitting element 120, for example, the anode voltage of an OLED; when the first node S is electrically connected to the light-emitting element 120 through a resistor 130, the current flowing through the light-emitting element 120 is extremely small, so that the voltage of the first node S can be approximately equal to the voltage of the first electrode 121 of the light-emitting element 120, that is, the voltage of the first electrode 121 of the light-emitting element 120 and the data signal (data voltage) Vd show a linear relationship, thereby realizing high-precision control of the gradation and improving the display effect.

[0432] For example, the first control signal SEL and the second control signal SEL_B are differential complementary signals, with the same amplitude but opposite phase. Thus, it contributes to improving the interference resistance of the circuit. For example, the first control signal SEL and the second control signal SEL_B may be output by the same gate driving circuit unit (e.g., GOA unit), thereby simplifying the circuit.

[0433] For example, as shown in Fig. 24A, the display substrate 10 may further include a data driving circuit 13 and a scan driving circuit 14. The data driving circuit 13 is configured to transmit a data signal, such as the above-mentioned data signal Vd, according to need (e.g., an image signal input to a display device). The scan driving circuit 14 is configured to output various scan signals, such as the above-mentioned first control signal SEL and second control signal SEL_B, and is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly fabricated on the display substrate.

[0434] For example, the display substrate uses a silicon substrate as the base substrate 101, and the pixel circuit, the data driving circuit 13 and the scan driving circuit 14 are all integrated on the silicon substrate. In this case, since the silicon-based circuit can achieve high accuracy, the data driving circuit 13 and the scan driving circuit 14 are not necessarily located in the non-display area, but may be formed, for example, in an area corresponding to the display area of ​​the display substrate.

[0435] For example, the display substrate 10 further includes a control circuit (not shown). For example, the control circuit is configured to control the data driving circuit 13 to apply the data signal Vd and control the gate driving circuit 13 to apply various scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and a memory, the memory including executable code, and the processor executes the executable code to perform the detection method.

[0436] For example, a processor may be a central processing unit (CPU) or other form of processing device having data processing and / or instruction execution capabilities including, for example, a microprocessor, a programmable logic controller (PLC), and the like.

[0437] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as, for example, volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored in the computer-readable storage medium, and the processor 121 may execute the functions desired by the program instructions. The computer-readable storage medium may further store various application programs and various data, such as, for example, electrical characteristic parameters obtained in the above detection method.

[0438] Hereinafter, a display substrate according to at least one embodiment of the present disclosure will be described by taking the pixel circuit shown in FIG. 25B as an example, but the embodiments of the present disclosure are not limited thereto.

[0439] Fig. 26A is a schematic diagram of a display substrate 10 according to at least one embodiment of the present disclosure. For example, as shown in Fig. 26A, the display substrate 10 includes a base substrate 101, and a plurality of sub-pixels 100 are located on the base substrate 101. The plurality of sub-pixels 100 are arranged as a sub-pixel array, in which the row direction of the sub-pixel array is a first direction D1, the column direction of the sub-pixel array is a second direction D2, and the first direction D1 and the second direction D2 cross, for example, perpendicular to each other. Fig. 26A exemplarily illustrates two rows and six columns of sub-pixels, i.e., two pixel rows 20 and six pixel columns 30 are illustrated, and dashed boxes are illustrated to indicate the regions of three pixel columns separated from each other.

[0440] For example, the base substrate 101 may be a rigid substrate such as a glass substrate or a silicon substrate, or may be made of a flexible material having excellent heat resistance and durability such as polyimide (PI), PC (polycarbonate) (PC), polyethylene terephthalate (PET), polyethylene, polyacrylic acid ester, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC). Although the embodiments of the present disclosure are described with reference to the base substrate 101 being a silicon substrate, the embodiments of the present disclosure are not limited thereto.

[0441] For example, the base substrate 101 includes single crystal silicon or high purity silicon. The pixel circuit is formed on the base substrate 10 by a CMOS semiconductor process, for example, forming an active region of a transistor (including a channel region, a first pole, and a second pole of the transistor) in the base substrate 101 by a doping process, forming each insulating layer by a silicon oxidation process or a chemical vapor deposition process (CVD), forming multiple conductive layers by a sputtering process, thereby forming a wiring structure, etc. The active region of each transistor is located inside the base substrate 101.

[0442] Fig. 26B is a cross-sectional view taken along line II' in Fig. 26A. For clarity, some wiring or electrode structures that are not directly connected are omitted in Fig. 26B.

[0443] For example, as shown in Fig. 26B, the display substrate 10 includes a base substrate 101, a first insulating layer 201, a polycrystalline silicon layer 102, a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304, which are arranged in this order on the base substrate 101. Hereinafter, the structure of the display substrate 10 will be described layer by layer, and Fig. 26B will be used for reference.

[0444] For clarity of illustration and convenience of explanation, Fig. 27A shows the part located under the first conductive layer 301 of the display substrate 10, i.e., the base substrate 101 and the first insulating layer 201 and polysilicon layer 102 thereon, including the transistors (P1, N1-N3), the storage capacitor Cst and the resistor 130, Fig. 27B is an enlarged schematic diagram of one sub-pixel 100 in Fig. 27A, and for clarity of illustration, the cut line I-I' in Fig. 26A is correspondingly shown in Fig. 27A. Figs. 28A-28E show the process of forming the substrate structure shown in Fig. 27A.

[0445] As shown in Figure 27B, for example, in a direction parallel to the plate surface of the base substrate 101, the first data write transistor P1 and the drive transistor N2 are located on opposing sides of the storage capacitor Cst, and for example, are located on opposing sides of the storage capacitor Cst in the second direction D2.

[0446] Referring to FIG. 24C in conjunction with this, this arrangement contributes to increasing the distance between the first data write transistor P1 and the drive transistor N2, thereby increasing the resistance of the parasitic circuit and further reducing the risk of latch-up effects in the CMOS circuit.

[0447] For example, the material of the second capacitance electrode 142 of the storage capacitor 140 is a conductor or a semiconductor. For example, as shown in FIG. 26B and FIG. 27B, the second capacitance electrode 142 of the storage capacitor 140 is the first region 401 of the base substrate 101, for example, the base substrate 101 is a P-type silicon-based base, and the material of the second capacitance electrode 142 is P-type single crystal silicon. When a voltage is applied to the first capacitance electrode 141, the first region 401 having a semiconductor property located below the first capacitance electrode 141 in the base substrate 101 forms an inversion region and becomes a conductor, thereby forming an electrical connection with the contact hole regions on both sides of the first region 401 (for example, the contact hole regions 145a, 145b shown in FIG. 4B). In this case, no separate process such as doping is performed on the first region 401.

[0448] In another example, the first region 401 may be a conductive region, such as a high-concentration doped region, in the base substrate 101, so that the second capacitance electrode 142 can have a stable high conductivity.

[0449] For example, the base wafer 101 further includes a second region 402, and the second region 402 is an N-type well region in the base wafer 101. As shown in Fig. 27B, for example, the first data write transistor P1 and the resistor 130 are provided in parallel in the second direction D2 in the second region 402. The resistor 130 made of a polycrystalline silicon material is provided in the N-type base, which contributes to reducing parasitic effects and improving circuit characteristics.

[0450] For example, in a direction parallel to the plate surface of the base substrate 101, the resistor (R) 130 and the first data write transistor P1 are located on the same side of the second capacitance electrode 142. For example, in a direction parallel to the plate surface of the base substrate 101, the drive transistor N2 and the bias transistor N3 are located on the same side of the second capacitance electrode 142.

[0451] 27B, the first data write transistor P1 and the second data write transistor P1 are arranged in parallel in the first direction D1 and are symmetrical with respect to the symmetry axis along the second direction D2. For example, the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor N1 are arranged in parallel in the first direction D1 and are symmetrical with respect to the symmetry axis along the second direction D2.

[0452] For example, resistor 130 has a U-shaped structure, for example an asymmetric U-shaped structure, for example the two branches of the U-shaped structure have different lengths, for example, as shown in FIG. 27B, the second terminal 132 of resistor 130 is closer to drive transistor N2.

[0453] The resistor 130 is provided as a U-shaped structure, which contributes to reducing the layout area occupied by the resistor, thereby improving the space utilization of the layout and improving the resolution of the display substrate. For example, in the same space, the resistor with the U-shaped structure can increase the length of the resistor, thereby achieving a desired resistance value.

[0454] In addition, the resistor 130 is designed to have an asymmetric structure to utilize the layout space rationally as well. For example, as shown in FIG. 27B, a contact hole region 411a is designed above the short branch of the U-shaped resistor, and the contact hole region 411a is arranged in parallel with the second terminal 132 of the resistor 130 in the first direction D1. For example, the contact hole region 411a is an N-type high concentration doping region (N+). For example, the contact hole region 411 is for biasing the well region 401 in which the first data write transistor P1 is located, thereby avoiding the threshold voltage change caused by the latch-up effect and the substrate bias effect, and improving the stability of the circuit. For example, as shown in FIG. 26B, a low voltage bias is applied to the P-type base 101 and a high voltage bias is applied to the N-type well region 402, thereby reverse biasing the parasitic PN junction between them, electrically isolating the devices, reducing the parasitic effect between the devices, and improving the stability of the circuit.

[0455] For example, the opening of the U-shaped structure faces the first capacitance electrode 141, and the first terminal 131 and the second terminal 132 of the resistor 130 are located at two ends of the U-shaped structure, respectively. As shown in the figure, the first terminal 131 of the resistor 130 is provided with a contact hole region 133 for electrically connecting with the gate 150 of the driving transistor N2, and the second terminal 132 of the resistor 130 is provided with a contact hole region 134 for electrically connecting with the first electrode 121 of the light-emitting element 120.

[0456] For example, the material of the resistor 130 includes a polycrystalline silicon material, the contact hole regions 133, 134 are doped regions used to reduce contact resistance, and the body region of the resistor 130 excluding the contact hole regions is, for example, an intrinsic region or a lightly doped region, thereby obtaining a desired resistance value.

[0457] For example, the first capacitive electrode 141 of the storage capacitor 140 and the resistor 130 are insulated from each other in the same layer and both include polysilicon material, and the doping concentration of the first capacitive electrode 141 of the storage capacitor 140 is higher than the doping concentration of the body region of the resistor 130. For example, the body region of the resistor 130 is an intrinsic polysilicon material.

[0458] For example, the gates 160, 170, 150, 180 of each of the transistors P1, N1-N3 and the first capacitance electrode 141 of the storage capacitor 140 are provided in the same layer and all include polycrystalline silicon material. For example, as shown in FIG. 27B, the gate 150 and the first capacitance electrode 141 of the driving transistor N2 are connected to each other to form an integral structure.

[0459] Figure 27B further shows the active areas P1a, N1a, N2a and N3a of each transistor P1, N1-N3, respectively, and also shows the first pole 161 and second pole 162 of the first data write transistor P1, the first pole 171 and second pole 172 of the second data write transistor N1, the first pole 151 and second pole 152 of the drive transistor N2, and the first pole 181 and second pole 182 of the bias transistor N3.

[0460] 27B further shows a gate contact region 165, a first contact region 163, and a second pole contact region 164 of the first data write transistor P1, a gate contact region 175, a first contact region 173, and a second pole contact region 174 of the second data write transistor N1, a gate contact region 155, a first contact region 153, and a second pole contact region 154 of the drive transistor N2, and a gate contact region 185, a first contact region 183, and a second pole contact region 184 of the bias transistor N3. For example, each first pole contact region is an area for a corresponding first pole to make electrical contact, each second pole contact region is an area for a corresponding second pole contact region to make electrical contact, and each gate contact region is an area for a corresponding gate to make electrical contact.

[0461] For example, the active region P1a of the first data write transistor P1 and the active region N1a of the second data write transistor N1 are provided in parallel in the first direction D1 and are symmetrical with respect to a symmetry axis along the second direction D2.

[0462] As shown in FIG. 27B, the area of ​​the active area N2a of the driving transistor N2 is larger than the areas of the active areas of other transistors, and a large aspect ratio can be obtained, which contributes to improving the driving capability of the driving transistor N2, and thereby improving the display effect.

[0463] As shown in FIG. 27B, for a transistor with a large active area, such as the driving transistor N2 or the bias transistor N3, there is enough space to provide at least two contact hole areas at its first pole and second pole, respectively, so that it can fully contact the connected structure to form a parallel structure, thereby reducing the contact resistance.

[0464] 27B further shows contact hole regions 144 on the first capacitance electrode 141 and contact hole regions 145a, 145b configured to be electrically connected to the second capacitance electrode 142. As shown in FIG 27B, at least two contact hole regions are provided in the first capacitance electrode 141 and the second capacitance electrode 142 in correspondence with each other, thereby reducing contact resistance.

[0465] 27A , the distribution of transistors (e.g., including the shape, size, etc. of each transistor) and storage capacitors and resistors in two subpixels 100 adjacent to each other in the first direction D1 is symmetrical with respect to an axis of symmetry along the second direction D2, i.e., the corresponding structures in the two subpixels are symmetrical with respect to an axis of symmetry along the second direction D2. The distribution of transistors in two subpixels 100 adjacent to each other in the second direction D2 is axially symmetrical with respect to the first direction.

[0466] This symmetrical arrangement can minimize the uniformity of process errors, thereby improving the uniformity of the display substrate, and also allows some structures that are arranged on the same layer of the substrate and can be connected to each other to be integrally formed, which makes the pixel layout more compact than if they were arranged separately, improving the space utilization rate, and thereby improving the resolution of the display substrate.

[0467] 27A , the second regions 402 of two subpixels 100 adjacent in the first direction D1 have an integral structure, and the second regions 402 of two subpixels 100 adjacent in the second direction D2 have an integral structure, i.e., the first data write transistors N1 and resistors 130 in the four adjacent subpixels 100 are located in the same well region. By providing them in this manner, compared to the case where they are provided in independent well regions, the pixel arrangement can be made more compact, provided that the design rules are satisfied, which contributes to improving the resolution of the display substrate.

[0468] For example, as shown in FIG. 27A, the active regions P1a of the first data writing transistors P1 of two subpixels adjacent in the second direction D2 are connected to each other to form an integral structure, i.e., the active regions P1a of the two first data writing transistors P1 are located in the same doping region A1 (P well) of the same second region 402, and the first electrodes of the two first data transistors P1 are connected to each other to form an integral structure and receive the same data signal Vd.

[0469] For example, as shown in FIG. 27A, the active regions N1a of the second data write transistors N1 of two subpixels adjacent in the second direction D2 are connected to each other to form an integral structure, i.e., the active regions N1a of the two second data write transistors N1 are located in the same doping region A2 (N-well) of the base substrate 101, and the first electrodes of the two second data write transistors N1 are connected to each other to form an integral structure and receive the same data signal Vd.

[0470] For example, as shown in FIG. 27A, the gates of the first data write transistor P1 or the gates of the second data write transistor N2 of two subpixels 100 adjacent to each other in the first direction D1 are connected to each other to form an integrated structure.

[0471] For each row of pixels, the gates of the first data write transistors P1 are configured to receive the same first control signal SEL, and the gates of the second data write transistors N1 are configured to receive the same second control signal SEL_B. In addition, since the transistor mirrors of two subpixels adjacent in the first direction D1 are symmetrical, the first write transistors P1 and the second write transistors N1 of the two subpixels are alternately adjacent in the first direction D1. Therefore, the gates of the two adjacent first data write transistors P1 may be directly connected to each other to form an integral structure, forming the first control electrode group 191, and the gates of the adjacent second data write transistors N1 may be directly connected to each other to form an integral structure, forming the second control electrode group 192. This arrangement allows the arrangement of pixels to be more compact, provided that the design rules are satisfied, and contributes to improving the resolution of the display substrate.

[0472] As shown in FIG. 27A , for two subpixels 100 adjacent in the first direction D1, when the driving transistors N2 are adjacent, the active regions N2a of the two driving transistors N2 are connected to each other to form an integrated structure, i.e., the active regions N2a of the two driving transistors N2 are located in the same doping region B (N well) of the base substrate 101, and the first electrodes of the two driving transistors N2 are connected to each other to form an integrated structure, form the third control electrode group 193, and receive the same first power supply voltage VDD; when the bias transistors N3 are adjacent, the gates of the two bias transistors N3 are connected to each other to form an integrated structure, and receive the same second common voltage Vcom2; and the active regions N3a of the two bias transistors N3 are connected to each other to form an integrated structure, i.e., the active regions N3a of the two bias transistors N3 are located in the same doping region C (N well) of the base substrate 101, and the first electrodes of the two bias transistors N3 are connected to each other to form an integrated structure, and receive the same second power supply voltage VSS.

[0473] By providing the pixels in this manner, the arrangement of the pixels can be made more compact, provided that the design rules are satisfied, which contributes to improving the resolution of the display substrate.

[0474] 28A-28D show a process of forming the structure of the substrate shown in FIG. 27A, and for clarity, only two rows and two columns of sub-pixels are shown, i.e., four adjacent sub-pixels 100. Hereinafter, a process of forming a display substrate according to an embodiment of the present disclosure will be described by way of example with reference to FIGS. 28A-28D, but this is not intended to limit the present disclosure.

[0475] For example, provide a silicon-based base substrate, the material of which is P-type single crystal silicon, and an N-type transistor (e.g., a driving transistor) may be directly fabricated on the P-type silicon base, i.e., the P-type base serves as the channel region of the N-type transistor, which is advantageous in realizing the high speed advantage of the NMOS device and improving the performance of the circuit.

[0476] As shown in FIG. 28A, for example, a P-type silicon base substrate is N-type doped to form a second region 402 which is an N-type well region, and serves as the base of the first data write transistor P1 and the resistor 130.

[0477] For example, the second regions 402 of two sub-pixels adjacent in the first direction D1 may be connected to each other, and the second regions 402 of two sub-pixels adjacent in the second direction D2 may be connected to each other. For example, when the N-type doping is performed, the non-doped regions of the base substrate 101 are shielded.

[0478] As shown in FIGS. 27B and 28B, for example, a first insulating layer 201 is formed on the base substrate 101, and then a polycrystalline silicon layer 102 is formed on the first insulating layer 201.

[0479] The first insulating layer 201 includes the gate insulating layers of each transistor, and further includes the dielectric layer 104 of the storage capacitor Cst. The polysilicon layer 102 includes the first capacitance electrode 141, the resistor 130, and the gates 150, 160, 170, 180 of each transistor (P1, N1-N3).

[0480] The gate of the first data write transistor P1 is located in the second region 402, and the N-type well region functions as a channel region of the P-type transistor. The resistor 130 is also located in the second region 402, and the resistor 130 made of polysilicon material is formed in the N-type base, which contributes to reducing parasitic effects and improving circuit characteristics. Each N-type transistor is formed directly on the P-type base.

[0481] As shown in Figure 28B, the patterns of the polycrystalline silicon layer in two subpixels adjacent in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D2, and the patterns of the polycrystalline silicon layer in two subpixels adjacent in the second direction D2 are symmetrical with respect to the axis of symmetry along the first direction D1.

[0482] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two subpixels adjacent to each other in the first direction D1 may be integrally formed.

[0483] For example, the first insulating layer is formed on the base substrate by thermal oxidation, and the material of the first insulating layer is, for example, silicon nitride, silicon oxide or silicon oxynitride.

[0484] For example, a polysilicon material layer is formed on the first insulating layer by a chemical vapor deposition process (PVD), and then a lithography process is performed on the polysilicon material layer to form the polysilicon layer 102 .

[0485] FIG. 28C shows a doping window region 103 (left) of the base substrate, and the doping window region (right) is shown in the substrate structure shown in FIG. 28B. For example, the doping is high concentration doping, thereby forming contact hole regions for electrical connection on the base substrate. For example, the doping window region includes the source region and drain region of each transistor. For example, the doping window region further includes each contact hole region of the base and the contact hole region of the resistor 130, for example, including the contact hole regions 400a, 400b, 411a, 411b, 145a, 145b, 133, 134 shown in FIG. 27B. For example, the gate of the transistor is formed from polysilicon material, so it is also necessary to dope the polysilicon gate. When doping, a barrier layer needs to be formed to shield the non-doped region and expose only the corresponding doping window region and the amorphous silicon region.

[0486] 28C shows only each doping window region as an example, but when actually performing the doping process, a corresponding barrier layer / mask layer may be provided to expose the corresponding doping window region and polysilicon region for doping. For example, the material of the barrier layer / mask layer may be a photoresist or an oxide material.

[0487] As shown in Fig. 28D, a barrier layer 135 is formed on the corresponding resistor 130. In order to protect the resistance value of the resistor 130, it is necessary to shield the resistor 130 during doping to avoid the resistor 130 being damaged by doping. The barrier layer 135 shields the body part of the resistor 130, and only exposes the contact hole regions 133, 134 at both ends of the resistor 130.

[0488] For example, the barrier layer 135 may be a nitride, oxide, or oxynitride of silicon, or may be a photoresist material. After the doping process is completed, the barrier layer 135 may be retained in the display substrate or may be removed.

[0489] In some other examples, the barrier layer 135 of the resistor 130 may be formed together with the barrier layer / mask layer of other regions during doping, and the embodiments of the present disclosure are not limited thereto.

[0490] For example, in the doping process, it is necessary to perform N-type doping and P-type doping, respectively, thereby forming, for example, the source region and drain region of an N-type transistor and the source region and drain region of a P-type transistor. When performing the N-type doping process, it is necessary to form a barrier layer to shield the region that is not N-type doped, and when performing the P-type doping process, it is necessary to form a barrier layer to shield the region that is not P-type doped.

[0491] In Fig. 28E, a different hatching pattern (left) is used to indicate N-type doped regions SN and P-type doped regions SP, and in Fig. 28D, the substrate is shown to have N-type doped regions SN and P-type doped regions SP (right), which are also shown in Fig. 27B, for which reference may also be made.

[0492] For example, performing an N-type doping process includes forming a barrier layer to cover the P-type doping region SP and to cover the region other than the doping window region and the polysilicon region in the N-type doping region SN, and only reserving the doping window region and the polysilicon region in the N-type doping region SN, i.e., the overlap region of the SN region with the doping window region 103 and the polysilicon region shown in FIG. 28C, and then performing an N-type doping process. As can be seen by comparing with FIG. 27B, the gate, the first pole, the second pole, and the contact hole regions 411a, 411b, 145a, 145b of the transistors N1-N3 can be formed by the N-type doping process. The N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, a boron element.

[0493] For example, performing a P-type doping process includes forming a barrier layer to cover the N-type doping region SN and to cover the region other than the doping window region and the polysilicon region in the P-type doping region SP, and reserving only the doping window region and the polysilicon region in the P-type doping region SP, i.e., the overlap region between the SP region and the doping window region 103 and the polysilicon region shown in FIG. 28C, and then performing a P-type doping process. As can be seen by comparing with FIG. 27B, the gate, the first pole, the second pole, and the contact holes 400a, 400b, 133, 134 of the transistor P1 can be formed by the P-type doping process. The P-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, a phosphorus element.

[0494] In the doping process, for example, an ion implantation process is used, and the polysilicon pattern can act as a mask, so that ion implantation into the silicon-based base occurs just on both sides of the polysilicon, thereby forming the first pole and the second pole of each transistor, and realizing self-alignment. In addition, the resistivity of the polysilicon, which originally has a high resistance, is reduced by the doping process, so that the gate of each transistor and the first capacitance electrode can be formed. Therefore, using polysilicon material as the material of the resistor and the gate has various beneficial effects and reduces the process cost.

[0495] In this manner, the display substrate structure shown in FIG. 27A is formed, including transistors P1, N1-N3, resistor 130, and storage capacitor Cst.

[0496] For example, corresponding transistors, resistors and storage capacitors Cst in two subpixels adjacent in the first direction D1 are each symmetrical with respect to an axis of symmetry along the second direction D2, and corresponding transistors, resistors and storage capacitors Cst in two subpixels adjacent in the second direction D2 are each symmetrical with respect to an axis of symmetry along the first direction D1.

[0497] In this embodiment, the memory capacitor Cst is a capacitor formed by the field effect, and when a voltage is applied to the first capacitance electrode 141, an inversion charge is generated in the region located below the first capacitance electrode 141 in the base substrate 101, causing the lower plate of the memory capacitor Cst, i.e., the second capacitance electrode 142, to become a conductor.

[0498] In some other embodiments, a conductive process (e.g., a doping process) may be performed in advance on a region of the base substrate 101 located below the first capacitance electrode 141 to form the second capacitance electrode 142. The embodiments of the present disclosure are not limited to this.

[0499] By sequentially forming the second insulating layer 202, the first conductive layer 301, the third insulating layer 203, the second conductive layer 302, the fourth insulating layer 204, the third conductive layer 303, the fifth insulating layer 205 and the fourth conductive layer 304 on the substrate shown in Figure 27A, the display substrate shown in Figure 26A is formed.

[0500] 29A and 29B respectively show a pattern of the first conductive layer 301 and the first conductive layer 301 when provided on the substrate structure shown in FIG. 27A, and FIG. 29C shows a cross-sectional view taken along line IV-IV' in FIG. 29B, in which vias in the second insulating layer 202 are further shown, which correspond one-to-one to each contact region in FIG. 27B and are used to electrically connect each contact hole region to the pattern in the first conductive layer 301. For clarity of illustration, only two rows and six columns of sub-pixels are shown, and the area of ​​one sub-pixel 100 is indicated by a dashed box, and FIG. 29B further shows the corresponding position of the line I-I' in FIG. 26A.

[0501] 29A, the patterns of the first conductive layers in two subpixels adjacent in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D2, and the patterns of the first conductive layers in two subpixels adjacent in the second direction D2 are symmetrical with respect to the axis of symmetry along the first direction D1. Hereinafter, the pattern of the first conductive layer will be illustratively described using one subpixel as an example.

[0502] As shown in FIG. 29A , the first conductive layer 301 includes a connecting electrode 313 , which is used to electrically connect the first terminal 131 of the resistor 130 and the second electrode 152 of the driving sub-circuit 112 .

[0503] For example, referring to FIG. 29B, a first terminal of the connection electrode 313 is electrically connected to a first terminal 131 of the resistor 130 via a via 225 in the second insulating layer 202, and a second terminal of the connection electrode 313 includes a first branch 331 and a second branch 332; referring to FIG. 26B, the first branch 331 is electrically connected to a first pole 151 of the drive transistor N2 via a via 226a in the second insulating layer 202, and the second branch 332 is electrically connected to a first pole 181 of the bias transistor N3 via a via 226b in the second insulating layer 202.

[0504] For example, as shown in FIG. 29B, in the second direction D2, the via 225 and the via 226a are respectively located on opposite sides of the first capacitance electrode 141, i.e., the orthogonal projection of the connection electrode 313 on the base substrate 101 penetrates the orthogonal projection of the first capacitance electrode 141 on the base substrate 101 in the second direction D2.

[0505] For example, at least two of the vias 226a and 226b may be provided, thereby reducing the contact resistance.

[0506] For example, referring to Figures 29A and 29B, the first conductive layer 301 further includes a connection electrode 314, which is electrically connected to the second terminal 132 of the resistor 130 through a via 229 in the second insulating layer 202, and the connection electrode 314 is used to electrically connect to the first electrode 121 of the light-emitting element 120.

[0507] For example, the connecting electrode 314 is L-shaped, one branch of which is electrically connected to the second terminal 132 of the resistor 130 , and the other branch of which is used to electrically connect to the first electrode 121 of the light emitting element 120 .

[0508] For example, as shown in Figures 29B and 29C, the first conductive layer 301 further includes a third capacitance electrode 315, which overlaps with the first capacitance electrode 141 in a direction perpendicular to the base substrate. The third capacitance electrode 315 is electrically connected to the contact hole region 145a through the via 227 in the second insulating layer 202, and is thus electrically connected to the second capacitance electrode 142, that is, in a direction perpendicular to the base substrate, the second capacitance electrode 142 and the third capacitance electrode 315 are located on both sides of the first capacitance electrode 141 respectively, and are electrically connected to each other, thereby forming a parallel capacitor structure and increasing the capacitance value of the storage capacitor Cst.

[0509] 29B and 29C, the first conductive layer 301 further includes a fourth capacitance electrode 316, which overlaps both the first capacitance electrode 141 and the second capacitance electrode 142 in a direction perpendicular to the base substrate. The fourth capacitance electrode 316 is electrically connected to the contact hole region 145b through the via 228 in the second insulating layer 202, and is thereby electrically connected to the second capacitance electrode 142. The fourth capacitance electrode 316 can further increase the capacitance value of the storage capacitor Cst and improve the performance of the circuit.

[0510] For example, the third capacitance electrode 315 and the fourth capacitance electrode 316 are located on both sides of the connection electrode 313 in the first direction D1.

[0511] For example, as shown in FIG. 29A, adjacent third capacitance electrodes 315 in two adjacent subpixels in the first direction D1 may be integrally formed to receive the same second power supply voltage VSS, and adjacent fourth capacitance electrodes 316 in two adjacent subpixels in the first direction D1 may be integrally formed to receive the same second power supply voltage VSS.

[0512] For example, at least two of the vias 227 and at least two of the vias 228 may be provided, thereby reducing the contact resistance, for example, the at least two vias 227 are arranged along the second direction D2, and the at least two vias 228 are arranged along the second direction D2.

[0513] For example, the first conductive layer 301 further includes a connecting electrode 317, which electrically connects the second terminal of the data write sub-circuit and the first terminal of the memory sub-circuit, i.e., is used to electrically connect the second pole 161 of the first data write transistor P1, the second pole 171 of the second data write transistor N1, and the first capacitance electrode 141.

[0514] 29A and 29B, the connection electrode 317 includes three ends, for example a T-shaped structure. Referring to FIG. 26B, a first terminal of the connection electrode 317 is electrically connected to the second pole of the first data write transistor P1 through a via 261a in the second insulating layer 202, a second terminal of the connection electrode 317 is electrically connected to the second pole of the second data write transistor N1 through a via 261b in the second insulating layer 202, and a third end of the connection electrode 317 is electrically connected to the first capacitance electrode 141 through a via 261c in the second insulating layer 202.

[0515] 29B, in the second direction D2, the connecting electrode 314 at least partially overlaps with the third end of the connecting electrode 317. This arrangement makes the pixel layout more compact, thereby improving the space utilization rate of the display substrate and improving the resolution of the display substrate.

[0516] 29A and 29B, the first conductive layer 301 further includes a first scan line connecting portion 311 and a second scan line connecting portion 312, the first scan line connecting portion 311 is used for electrically connecting the gate of the first data write transistor P1 to the first scan line so as to receive a first control signal SEL, and the second scan line connecting portion 312 is used for electrically connecting the gate of the second data write transistor N1 to the second scan line so as to receive a first control signal SEL_B.

[0517] For example, the first scanning line connection portion 311 is electrically connected to the gate of the first data write transistor P1 through a via 221 in the second insulating layer 202, and the second scanning line connection portion 312 is electrically connected to the gate of the second data write transistor N1 through a via 222 in the second insulating layer 202.

[0518] For example, as shown in FIG. 29A, sub-pixels adjacent to each other in the first direction D1 share the first scan line connecting portion 311 or the second scan line connecting portion 312.

[0519] As shown in FIG. 29A, the first conductive layer 301 further includes a data line connection portion 245 (an example of a third connection electrode in the present disclosure), which is used to electrically connect the first electrode of the first data write transistor P1 and the first electrode of the second data write transistor N1 to a data line so as to receive a data signal Vd transmitted by the data line.

[0520] As shown in FIG. 29B, the data line connection portion 245 is electrically connected to the first electrode 161 of the first data write transistor P1 through a via 223 in the second insulating layer 202, and is electrically connected to the first electrode 171 of the second data write transistor N1 through a via 224 in the second insulating layer 202.

[0521] 29A, the data line connection portions 245 are spaced apart in the first direction D1, for example, at the boundary between two subpixel rows, and for example, two subpixels adjacent in the second direction D2 share one data line connection portion 245.

[0522] 29A and 29B, the first conductive layer 301 further includes a connection electrode 318, which is electrically connected to the first electrode of the driving transistor N2 through a via 230 in the second insulating layer 202.

[0523] Referring to Figures 27A and 27B, the first conductive layer 301 further includes connection electrodes 319a, 319b, and 319c, all of which are provided for biasing the base of the transistor, for example, the N-type base is connected to a first power supply voltage terminal to receive a first power supply voltage VDD (high voltage), or the P-type base is connected to a second power supply voltage terminal to receive a second power supply voltage VSS (low voltage), thereby avoiding parasitic effects such as the substrate bias effect and improving the stability of the circuit.

[0524] 27B, the connection electrodes 319a, 319b are electrically connected to the contact hole regions 411a, 411b of the second region (N-well region) 402 of the base substrate 101 through the vias 262a, 262b in the second insulating layer 202, respectively, and the connection electrodes 319a and 319b are used to connect to the first voltage terminal VDD so as to bias the N-type base of the first data write transistor P1. The connection electrode 319c is electrically connected to the contact hole region 400a in the base substrate 101 through the via 262c in the second insulating layer 202, and the connection electrode 319c is used to connect to the second voltage terminal VSS so as to bias the P-type base where the second data write transistor N1 is located.

[0525] 29A-29B, the first conductive layer 301 further includes a bias voltage line 250 extending along a first direction D1 and electrically connected to the gate of the bias transistor N3 through a via 263 in the second insulating layer 202, thereby providing a second common voltage Vcom2.

[0526] 27B and 29A-29B, the first conductive layer 301 further includes a power line 260 (an example of a ninth power line in the present disclosure), which extends along a first direction D1 and is used to transmit a second power supply voltage VSS. The power line 260 is electrically connected to a first pole of the bias transistor N3 through a via 264a in the second insulating layer 202, thereby providing a second power supply voltage VSS, and is electrically connected to a contact hole region 400b in the base substrate 101 through a via 264b in the second insulating layer 202, thereby biasing a P-type base (an example of a second doping region in the present disclosure) in which the second data write transistor N1 is located.

[0527] Fig. 30A shows a schematic diagram of the second conductive layer 302, Fig. 30B shows the second conductive layer 302 based on the first conductive layer 301, and Fig. 30B further shows a via in the third insulating layer 203, which is used to connect the pattern in the first conductive layer 301 and the pattern in the second conductive layer 302. For clarity of illustration, only 4 rows and 6 columns of sub-pixels are shown, and the boundary between two sub-pixel rows is indicated by a dashed line, and Fig. 30B also correspondingly shows the position of the cutting line I-I' in Fig. 26A.

[0528] 30A, the patterns of the second conductive layer in two subpixels adjacent in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D2, and the patterns of the second conductive layer in two subpixels adjacent in the second direction D2 are symmetrical with respect to the axis of symmetry along the first direction D1. Hereinafter, the pattern of the second conductive layer will be illustratively described using one subpixel as an example.

[0529] 30A, the second conductive layer 302 includes power lines 270a, 270b, 280a, 280b extending along a first direction D1, the power lines 270a, 270b are used to transmit a second power voltage VSS, and the power lines 280a, 280b are used to transmit a first power voltage VDD. The power lines 270a, 280a, 270b, 280b are arranged alternately in a second direction D2.

[0530] 26B, 30A and 30B, the power line 270a (an example of the first power line of the present disclosure) is electrically connected to the power line 260 in the first conductive layer 301 through a plurality of vias 235 in the third insulating layer 203, thereby forming a parallel structure and effectively reducing the resistance of the wiring, and the plurality of vias 235 are arranged along the first direction D1. For example, the power line 270b is electrically connected to the fourth capacitance electrode 316 through the vias 236 in the third insulating layer 203, thereby providing the second power supply voltage VSS, and for example, the plurality of vias 236 are arranged along the second direction D2. For example, the power line 270b is further electrically connected to the third capacitance electrode 315 through the vias 267 in the third insulating layer 203, thereby providing the second power supply voltage VSS, and for example, the plurality of vias 267 are arranged along the second direction D2.

[0531] For example, in the second direction D2, the average line width of the power line 270b (an example of the seventh power line of the present disclosure) is larger than the average line width of the power line 270a because the fourth capacitive electrode 316 and the third capacitive electrode 315 electrically connected to the power line 270b both have large areas, and by arranging the power line 270b to have a large width, multiple connection holes 236, 267 can be easily formed between the fourth capacitive electrode 316 and the third capacitive electrode 315, thereby effectively reducing the contact resistance.

[0532] 30A and 30B, the power supply line 280a (an example of the second power supply line of the present disclosure) is electrically connected to the connection electrode 318 (an example of the fifth connection electrode of the present disclosure) of the first conductive layer 301 through the via 237 in the third insulating layer 203, thereby connected to the first pole of the driving transistor N2 to provide the first power supply voltage VDD. The power supply line 280b is electrically connected to the connection electrode 319a of the first conductive layer 301 through the via 238 in the third insulating layer 203, thereby providing a high voltage bias to the second region (N-well region) 402 (an example of the first doping region of the present disclosure) in the base substrate 101, for example, the multiple vias 238 are arranged along the second direction D2.

[0533] For example, in the second direction D2, the average line width of power line 280b (an example of the eighth power line of the present disclosure) is larger than the average line width of power line 280a, because the connection electrode 319a electrically connected to power line 280b has a large size in the second direction D2, and power line 280b is arranged to have a large width, making it possible to easily form multiple connection holes 238 between power line 280b and connection electrode 319a, thereby increasing the contact area with connection electrode 319a and effectively reducing contact resistance.

[0534] For example, the second conductive layer 302 further includes a plurality of first scan lines 210 and a plurality of second scan lines 220 extending along a first direction D1. For example, the scan line 11 shown in FIG.

[0535] 29A and 29B, the first scanning line 210 is electrically connected to the first scanning line connection portion 311 through a via 231 in the third insulating layer 203, and the second scanning line 220 is electrically connected to the second scanning line connection portion 312 through a via 232 in the third insulating layer 203.

[0536] For example, referring to Figures 26B, 30A and 30B, the second conductive layer 302 further includes a connection electrode 323, which is electrically connected to the connection electrode 314 of the first conductive layer 301 through a via 239 in the third insulating layer 203, and is thereby connected to the second terminal 132 of the resistor 130. The connection electrode 323 is used to electrically connect to the first electrode 121 of the light emitting element 120. For example, the number of the vias 239 is at least two.

[0537] For example, referring to Figures 30A and 30B, the second conductive layer 302 further includes a connection electrode 324, which is electrically connected to the connection electrode 319b in the first conductive layer 301 through a via 265 in the third insulating layer 203, and thereby electrically connected to a contact hole region 411b of the second region (N-well region) 402 in the base substrate 101.

[0538] For example, referring to Figures 30A and 30B, the second conductive layer 302 further includes a connection electrode 325, which is electrically connected to the connection electrode 319c in the first conductive layer 301 through the via 266 in the third insulating layer 203, and thereby electrically connected to the contact hole region 400a in the base substrate 101.

[0539] For example, the connecting electrode 325 has a cross structure, for example, the connecting electrodes 324 and the connecting electrodes 325 are alternately distributed in the first direction D1 and located at the boundary between two sub-pixel rows.

[0540] 30A, the second conductive layer 302 further includes a data line connection portion 244 (an example of a fourth connection electrode of the present disclosure). Referring to FIG. 30B, the data line connection portion 244 is electrically connected to a data line connection portion 245 in the first conductive layer 301 through a via 233.

[0541] For example, as shown in FIG. 30A, a plurality of data line connecting portions 244 are arranged at intervals in the first direction D1, and one connection electrode 324 or one connection electrode 325 is provided between two adjacent data line connecting portions 244.

[0542] For example, the data line connection portion 244 is located at the boundary between two sub-pixel rows, and two sub-pixels adjacent to each other in the second direction D2 share one data line connection portion 244.

[0543] For example, referring to Figures 30A and 30B, in the second direction D2, the data line connection parts 244 located in the sub-pixels of each column are alternately located on both sides of the data line connection part 245 and are electrically connected to the first terminal and the second terminal of the data line connection part 245 through vias 233, 234, respectively, thereby connecting the data line connection parts 245 to different data lines.

[0544] Fig. 31A shows a schematic diagram of third conductive layer 303, Fig. 31B shows third conductive layer 303 based on second conductive layer 302, and Fig. 31B further shows vias in fourth insulating layer 204, which are used to connect a pattern in second conductive layer 302 and a pattern in third conductive layer 303. For clarity of illustration, only conductive patterns corresponding to sub-pixels of 4 rows and 6 columns are shown, and Fig. 31A shows boundary lines of two rows of sub-pixels by dashed lines, and Fig. 31B further shows the position of cutting line I-I' in Fig. 26A.

[0545] For example, the third conductive layer 303 includes a plurality of data lines extending along the second direction D2, and the data lines are used to connect with first terminals of data writing sub-circuits in the sub-pixels to provide data signals Vd. For example, the plurality of data lines shown in FIG. 31A includes a plurality of first data lines 241 and a plurality of second data lines 242, and the first data lines 241 and the second data lines 242 are alternately arranged one by one in the first direction D1. For example, the data line 12 shown in FIG. 24A may be the first data line 241 or the second data line 242.

[0546] For example, the data lines are divided into a plurality of data line groups, and each data line group includes one first data line 241 and one second data line 242. For example, each sub-pixel column is connected to one corresponding data line group, i.e., connected to one first data line 241 and one second data line 242, that is, one column of sub-pixels is driven by two data lines, thus contributing to reducing the load on each data line, thereby improving the driving ability of the data lines, reducing the signal delay, and improving the display effect.

[0547] 31B, the first data line 241 is electrically connected through a via 403 in the fourth insulating layer 204 to a data line connection portion 244 located between the first row subpixel and the second row subpixel in the second conductive layer 302 shown in FIG. 30B, thereby providing data signals to the first and second row subpixels, and the second data line 242 is electrically connected through a via 404 in the fourth insulating layer 204 to a data line connection portion 244 located between the third row subpixel and the fourth row subpixel in the second conductive layer 302 shown in FIG. 30B, thereby providing data signals to the third and fourth row subpixels.

[0548] A few points need to be explained:

[0549] (1) In the drawings of the embodiments of the present disclosure, only structures related to the embodiments of the present disclosure are shown, and other structures may refer to the general design.

[0550] (2) Features in the same and different embodiments of the present disclosure may be combined with each other, if not inconsistent.

[0551] Although the specific embodiments of the present disclosure have been described above, the scope of protection of the present disclosure is not limited thereto, and any modifications or replacements that a person skilled in the art can easily conceive without departing from the technical scope disclosed in the present disclosure belong to the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be in accordance with the scope of the claims.

Claims

1. a drive substrate including a base and a drive circuit; a first planar layer located on the driving circuit; an anode layer located on a side of the first flat layer away from the drive substrate; a pixel definition layer located on a side of the anode layer away from the drive substrate; a light-emitting functional layer located on a side of the anode layer away from the driving substrate; a cathode layer located on a side of the light-emitting functional layer away from the driving substrate; a package layer located on a side of the cathode layer away from the driving substrate; the driving circuit includes at least one transistor, the transistor including a semiconductor layer; the anode layer includes a plurality of anodes, the display substrate includes a plurality of pixel openings located on a side of the plurality of anodes away from the drive substrate, the plurality of pixel openings being configured to at least overlap with the plurality of anodes; a display substrate, wherein each of the anodes includes a main body portion and a protrusion portion, the protrusion portion is connected to the main body portion, a size of the protrusion portion in a first direction is larger than a size of the main body portion in the first direction, the light-emitting functional layer includes a plurality of light-emitting portions, and the plurality of light-emitting portions are arranged in contact with the main body portions of the plurality of anodes.

2. The display substrate according to claim 1 , wherein the protrusions are provided on the periphery of the main body.

3. The display substrate of claim 1 , wherein an orthogonal projection of the pixel definition layer on the driving substrate overlaps with an orthogonal projection of the protrusion on the driving substrate.

4. the pixel definition layer includes a pixel definition portion, The pixel definition unit a pixel defining flat portion located between two adjacent anodes; a protrusion structure located on a side of the protrusion portion of each of the two adjacent anodes that is away from the driving substrate, The display substrate of claim 3 , wherein the pixel-defining flat portion connects the protruding structure.

5. The display substrate of claim 4 , wherein the pixel definition portions are provided symmetrically with respect to a center of the space between the adjacent anodes.

6. Each of the protruding structures is a first side wall located on a side of the protrusion structure adjacent to a center of the body portion; a second side wall connected to the first side wall, The display substrate of claim 4 , wherein the second sidewall is farther away from the driving substrate than the first sidewall, and a slope angle of the first sidewall is larger than a slope angle of the second sidewall.

7. 7. The display substrate of claim 6, wherein the first sidewall has a slope angle ranging from 75 to 89 degrees, and the second sidewall has a slope angle ranging from 15 to 45 degrees.

8. Each of the protruding structures is a third sidewall disposed on a side of the protrusion structure adjacent to the pixel-defining flat portion, The display substrate of claim 6 , wherein a slope angle of the third sidewall is greater than a slope angle of the second sidewall and less than a slope angle of the first sidewall.

9. Each of the protruding structures is a third sidewall disposed on a side of the protrusion structure adjacent to the pixel-defining flat portion, The display substrate of claim 6 , wherein the first sidewall has a slope angle of α, the second sidewall has a slope angle of β, and the third sidewall has a slope angle of γ, satisfying Equation 1. [0010]

10. 9. The display substrate of claim 8, wherein a difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to i times the slope angle of the third sidewall, where i ranges from 0.8 to 1.

2.

11. The display substrate of claim 9 , wherein the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 2. [0025] In the formula, the range of values ​​for i is 0.8-1.

2.

12. 9. The display substrate of claim 8, wherein a difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to j times a difference between the slope angle of the second sidewall and the slope angle of the third sidewall, and j is in the range of 1.5-3.

13. The display substrate of claim 9 , wherein the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 3. [0030] In the formula, j ranges in value from 1.5 to 3.

14. 9. The display substrate of claim 8, wherein the sum of the slope angle of the first sidewall and the slope angle of the second sidewall is equal to k times the slope angle of the third sidewall, where k ranges from 2-3.

15. The display substrate of claim 9 , wherein the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy Equation 8. [0045] In the formula, k ranges from 2 to 3.

16. 9. The display substrate of claim 8, wherein the third sidewall has a slope angle ranging from 45 to 60 degrees.

17. 9. The display substrate of claim 8, wherein a size of the third side wall in the second direction of orthogonal projection on the driving substrate is larger than a size of the second side wall in the second direction of orthogonal projection on the driving substrate, and a size of the second side wall in the second direction of orthogonal projection on the driving substrate is larger than a size of the first side wall in the second direction of orthogonal projection on the driving substrate.

18. 10. The display substrate of claim 9, wherein the first sidewall has a size H1 in the first direction, the second sidewall has a size H2 in the first direction, and the third sidewall has a size H3 in the first direction, where H1, H2, and H3 satisfy Equation 4. [0050]

19. the projection of each of the anodes includes a fourth sidewall located on a side of the projection adjacent a center of the body portion; The display substrate of claim 8 , wherein a slope angle of the fourth sidewall is greater than a slope angle of the second sidewall and less than a slope angle of the first sidewall.

20. the projection of each of the anodes includes a fourth sidewall located on a side of the projection adjacent a center of the body portion; The display substrate of claim 9 , wherein the slope angle of the fourth sidewall is δ and satisfies Equation 5. [006]

21. The protrusion of each of the anodes is a first sub-anode layer located on a side of the driving circuit away from the base; a second sub-anode layer located on a side of the first sub-anode layer away from the driving substrate; 20. The display substrate of claim 19, further comprising: a third sub-anode layer located on a side of the second sub-anode layer away from the driving substrate.

22. 22. The display substrate of claim 21, wherein the size of the first sub-anode layer in the second direction is larger than the size of the third sub-anode layer in the second direction, and the size of the third sub-anode layer in the second direction is larger than the size of the second sub-anode layer in the second direction.

23. 23. The display substrate of claim 22, wherein a size of the third sub-anode layer exceeding the second sub-anode layer in the second direction is less than a size of an overlapping area between a normal projection of the pixel definition layer on the driving substrate and a normal projection of the protrusion on the driving substrate in the second direction.

24. 22. The display substrate of claim 21, wherein an end of the first sub-anode layer away from the body portion includes a ridge, the thickness of the ridge in the first direction being greater than the average thickness of the first sub-anode layer in the first direction.

25. The display substrate of claim 21 , wherein an end of the third sub-anode layer away from the body portion is curved toward the first sub-anode layer.

26. The protrusion of each of the anodes is 22. The display substrate of claim 21, further comprising a fourth sub-anode layer located between the second sub-anode layer and the third sub-anode layer, wherein the size of the fourth sub-anode layer in the second direction is less than the size of the second sub-anode layer in the second direction.

27. 27. The display substrate of claim 26, wherein a size of the third sub-anode layer exceeding the fourth sub-anode layer in the second direction is less than a size of an overlapping area between a normal projection of the pixel definition layer on the driving substrate and a normal projection of the protrusion on the driving substrate in the second direction.

28. the second sub-anode layer includes a fifth sidewall located on a side of the second sub-anode layer away from the body portion, and the fourth sub-anode layer includes a sixth sidewall located on a side of the fourth sub-anode layer away from the body portion, 27. The display substrate of claim 26, wherein a slope angle of the fifth sidewall is greater than a slope angle of the fourth sidewall, a slope angle of the sixth sidewall is greater than a slope angle of the fourth sidewall, and a slope angle of the fifth sidewall is greater than a slope angle of the sixth sidewall.

29. The display substrate of claim 26, wherein a ratio of a thickness of the first sub-anode layer in the first direction perpendicular to the driving substrate to a thickness of the second sub-anode layer in the first direction perpendicular to the driving substrate is in a range of 1 / 15-1 / 5.

30. 27. The display substrate of claim 26, wherein a ratio of a thickness of the first sub-anode layer in the first direction perpendicular to the driving substrate to a thickness of the third sub-anode layer in the first direction perpendicular to the driving substrate is in a range of 1 / 3-4 / 5.

31. The display substrate of claim 26, wherein a ratio of a thickness of the first sub-anode layer in the first direction perpendicular to the driving substrate to a thickness of the fourth sub-anode layer in the first direction perpendicular to the driving substrate is in a range of 1 / 24-1 / 8.

32. 22. The display substrate of claim 21, wherein a ratio of a distance between two adjacent anodes to a length of an orthogonal projection of the protrusions of the anodes on the driving substrate is in a range of 2-4.

33. 33. The display substrate of claim 32, wherein a ratio of a distance between two adjacent anodes to a length of an orthogonal projection of the protrusions of the anodes on the driving substrate is in a range of 2.5-3.

5.

34. The display substrate according to any one of claims 1 to 33, wherein the protrusion portion is provided surrounding the main body portion.

35. The display substrate of claim 34 , wherein a shape of the orthogonal projection of the anode on the drive substrate comprises a hexagon.

36. a reflective electrode layer located on a side of the first flat layer adjacent to the anode layer; The display substrate of any one of claims 1 to 35, further comprising: a second planar layer located on a side of the reflective electrode layer adjacent to the anode layer.

37. 37. The display substrate of claim 36, wherein the reflective electrode layer is disposed continuously within the pixel opening.

38. The display substrate of any one of claims 1 to 37, wherein a first pore is present between the light-emitting functional layer and the body portion, and at least one second pore is present between the light-emitting functional layer and the pixel definition layer, and a space occupied by the first pore is larger than a space occupied by the second pore.

39. The package layer comprises: an inorganic package layer located on a side of the cathode layer away from the driving substrate; The display substrate of any one of claims 1 to 38, wherein the inorganic packaging layer comprises a plurality of sub-inorganic packaging layers.

40. 40. The display substrate of claim 39, wherein at least two adjacent sub-inorganic package layers of the plurality of sub-inorganic package layers are made of different materials, and at least two adjacent sub-inorganic package layers of the plurality of sub-inorganic package layers are made of the same material.

41. 40. The display substrate of claim 39, wherein the refractive index of the plurality of sub-inorganic package layers increases and then decreases in a direction away from the driving substrate.

42. The display substrate of claim 39 , wherein the thicknesses of the sub-inorganic package layers in the first direction gradually decrease in a direction away from the driving substrate.

43. Each of the sub-inorganic package layers includes a flat region and a double arch spacing region that are alternately provided, a first arch region located on a side of the flat region that is away from the double arch spacing region, a second arch region located between the flat region and the double arch spacing region, and a third arch region located on a side of the flat region that is away from the second arch region, The display substrate of claim 39 , wherein the first arch region and the second arch region are disposed symmetrically with respect to a center of the flat region.

44. a size of the flat region in a second direction is L, a distance in the second direction between a center of the second arch region and a center of the third arch region is a first distance D1, a distance in the second direction between the center of the first arch region and the center of the second arch region is a second distance D2, and radii of curvature of the first arch region, the second arch region, and the third arch region are all R, The display substrate of claim 43 , wherein the first distance D1 satisfies Equation 6. [0070]

45. a size of the flat region in a second direction is L, a distance in the second direction between a center of the second arch region and a center of the third arch region is a first distance D1, a distance in the second direction between the center of the first arch region and the center of the second arch region is a second distance D2, and radii of curvature of the first arch region, the second arch region, and the third arch region are all R, The display substrate of claim 43 , wherein the first distance D1 satisfies Equation 7. [0080]

46. an orthogonal projection of the first arch region, the second arch region, or the third arch region on the drive substrate overlaps with an orthogonal projection of the protrusion portion on the drive substrate, and an orthogonal projection of the flat region on the drive substrate overlaps with an orthogonal projection of the main body portion on the drive substrate, 44. The display substrate of claim 43, wherein a distance between a surface of the first arch region, the second arch region or the third arch region facing away from the drive substrate and the drive substrate is greater than a distance between a surface of the flat region facing away from the drive substrate and the drive substrate.

47. 44. The display substrate of claim 43, wherein an orthogonal projection of the double arch spacing region on the drive substrate overlaps with an orthogonal projection of a spacing region between two adjacent anodes on the drive substrate.

48. The plurality of sub-inorganic package layers include: a first sub-inorganic package layer located on a side of the cathode layer away from the driving substrate; a second sub-inorganic package layer located on a side of the first sub-inorganic package layer away from the driving substrate; a third sub-inorganic package layer located on a side of the second sub-inorganic package layer away from the driving substrate; The display substrate of claim 43 , further comprising: a fourth sub-inorganic package layer located on a side of the third sub-inorganic package layer away from the driving substrate.

49. 49. The display substrate of claim 48, wherein a refractive index of the first sub-inorganic package layer is less than a refractive index of the second sub-inorganic package layer, and a refractive index of the fourth sub-inorganic package layer is less than a refractive index of the third sub-inorganic package layer.

50. The display substrate of claim 49 , wherein the second sub-inorganic packaging layer and the third sub-inorganic packaging layer have the same refractive index.

51. the flat region of the first sub-inorganic package layer has a first width in the second direction, the flat region of the second sub-inorganic package layer has a second width in the second direction, the flat region of the third sub-inorganic package layer has a third width in the second direction, and the flat region of the fourth sub-inorganic package layer has a fourth width in the second direction; The display substrate of claim 48 , wherein the first width is greater than the second width, the second width is greater than the third width, and the third width is greater than the fourth width.

52. an included angle between a first connection line of an edge of the flat region of the first sub-inorganic package layer adjacent to the second arch region, an edge of the flat region of the second sub-inorganic package layer adjacent to the second arch region, an edge of the flat region of the third sub-inorganic package layer adjacent to the second arch region, and an edge of the flat region of the fourth sub-inorganic package layer adjacent to the second arch region, and a surface of the driving substrate away from the anode layer is a first included angle; an included angle between a second connection line of an apex of the second arch region of the first sub-inorganic package layer, an apex of the second arch region of the second sub-inorganic package layer, an apex of the second arch region of the third sub-inorganic package layer, and an apex of the second arch region of the fourth sub-inorganic package layer and a surface of the driving substrate away from the anode layer is a second included angle; 49. The display substrate of claim 48, wherein the first included angle is less than the second included angle.

53. 53. The display substrate of claim 52, wherein the first included angle is in the range of 60-85 degrees and the second included angle is in the range of 85-89 degrees.

54. The display substrate of claim 52 , wherein an intersection of the first connection line and the second connection line is located within the driving substrate.

55. The drive circuit includes: a semiconductor layer located within the base; a first conductive layer located on the semiconductor layer; a second conductive layer located on a side of the first conductive layer away from the base; a third conductive layer located on a side of the second conductive layer away from the base; 55. The display substrate of claim 54, further comprising: a fourth conductive layer located on a side of the third conductive layer away from the base.

56. 56. The display substrate of claim 55, wherein an intersection of the first connecting line and the second connecting line is located between an upper surface of the third conductive layer away from the base and the anode layer.

57. 56. The display substrate of claim 55, wherein a distance between an intersection of the first connecting line and the second connecting line and a vertex of a top surface away from the base of the protrusion structure of the pixel definition layer is greater than a thickness of the first sub-inorganic package layer in the first direction.

58. 56. The display substrate of claim 55, wherein a distance between an intersection of the first connecting line and the second connecting line and a vertex of a top surface away from the base of the protrusion structure of the pixel definition layer is less than a sum of a thickness of the first sub-inorganic package layer in the first direction and a thickness of the second sub-inorganic package layer in the first direction.

59. 56. The display substrate of claim 55, wherein an included angle between a third connection line of an edge of the second arch region of the first sub-inorganic package layer adjacent to the double arch spacing region, an edge of the second arch region of the second sub-inorganic package layer adjacent to the double arch spacing region, an edge of the second arch region of the third sub-inorganic package layer adjacent to the double arch spacing region, and an edge of the second arch region of the fourth sub-inorganic package layer adjacent to the double arch spacing region, and a surface of the driving substrate away from the anode layer is a third included angle, and the third included angle is less than the second included angle.

60. 60. The display substrate of claim 59, wherein an intersection of the first connecting line and the third connecting line is located between an upper surface of the second conductive layer away from the base and a lower surface of the third conductive layer adjacent to the base.

61. 60. The display substrate of claim 59, wherein an intersection of the second connecting line and the third connecting line is located between a lower surface of the first conductive layer adjacent to the base and a lower surface of the base away from the first conductive layer.

62. 60. The display substrate of claim 59, wherein an included angle between a fourth connecting line and a surface of the driving substrate away from the anode layer is a fourth included angle, the fourth included angle being less than the second included angle, the fourth included angle being an edge of the third arch region of the first sub-inorganic package layer away from the double arch spacing region, the second sub-inorganic package layer away from the double arch spacing region, the third sub-inorganic package layer away from the double arch spacing region, and the third sub-inorganic package layer away from the double arch spacing region.

63. The display substrate of claim 62 , wherein an intersection between the first connection line and the fourth connection line is located on a side of the base away from the first conductive layer.

64. 63. The display substrate of claim 62, wherein an intersection of the third connecting line and the fourth connecting line is located on a side of the base away from the first conductive layer.

65. an upper surface of the first arch region of the first sub-inorganic package layer away from the base has a first radius of curvature, an upper surface of the first arch region of the second sub-inorganic package layer away from the base has a second radius of curvature, an upper surface of the first arch region of the third sub-inorganic package layer away from the base has a third radius of curvature, and an upper surface of the first arch region of the fourth sub-inorganic package layer away from the base has a fourth radius of curvature; 49. The display substrate of claim 48, wherein the first radius of curvature is less than the second radius of curvature, the second radius of curvature is less than the third radius of curvature, and the third radius of curvature is less than the fourth radius of curvature.

66. 66. The display substrate of claim 65, wherein a dummy center of the first arch region of the fourth sub-inorganic package layer is located between an upper surface of the first sub-inorganic package layer away from the base and a lower surface of the fourth sub-inorganic package layer adjacent to the base.

67. the first sub-inorganic package layer has a first thickness in the first direction, the second sub-inorganic package layer has a second thickness in the first direction, the third sub-inorganic package layer has a third thickness in the first direction, and the fourth sub-inorganic package layer has a fourth thickness in the first direction; 49. The display substrate of claim 48, wherein the first thickness is greater than the second thickness, the second thickness is greater than the third thickness, and the third thickness is greater than the fourth thickness.

68. 68. The display substrate of claim 67, wherein a ratio of the difference between the first thickness and the second thickness to the difference between the third thickness and the fourth thickness is in the range of 1.5 to 2 times.

69. 68. The display substrate of claim 67, wherein a ratio of the sum of the second thickness and the third thickness to the first thickness is in the range of 0.8-1.

2.

70. 68. The display substrate of claim 67, wherein the first thickness range is 1000-1200 nanometers, the second thickness range is 500-660 nanometers, the third thickness range is 480-560 nanometers, and the fourth thickness range is 180-260 nanometers.

71. 71. The display substrate of claim 70, wherein the material of the first sub-inorganic packaging layer includes silicon oxide and silicon oxynitride, the material of the second sub-inorganic packaging layer includes silicon nitride, the material of the third sub-inorganic packaging layer includes silicon nitride, and the material of the fourth sub-inorganic packaging layer includes silicon oxide.

72. The package layer comprises: The driving substrate further includes an organic package layer located on a side of the inorganic package layer away from the driving substrate, 40. The display substrate of claim 39, wherein the organic package layer includes a first region, a second region, and a third region, an average thickness of the first region being less than an average thickness of the second region, and an average thickness of the second region being less than an average thickness of the third region.

73. a color film layer disposed on a side of the package layer away from the driving substrate; 73. The display substrate of claim 1, wherein the color film layer comprises a first color filter, a second color filter and a third color filter.

74. 74. The display substrate of claim 73, wherein the first color filter and the second color filter have a first overlapping region, the second color filter and the third color filter have a second overlapping region, and the third color filter and the first color filter have a third overlapping region.

75. The display substrate of claim 74 , wherein orthogonal projections of the first overlapping region, the second overlapping region, and the third overlapping region on the driving substrate overlap with orthogonal projections of the protrusions on the driving substrate.

76. 75. The display substrate of claim 74, wherein orthogonal projections of the first overlapping region, the second overlapping region, and the third overlapping region on the driving substrate overlap with orthogonal projections of gap regions between two adjacent anodes on the driving substrate.

77. 75. The display substrate of claim 74, wherein a size of the first overlapping region in the second direction is larger than a size of the second overlapping region in the second direction, and a size of the second overlapping region in the second direction is larger than a size of the third overlapping region in the second direction.

78. 78. The display substrate of claim 77, wherein the first overlapping region has a size range of 400-600 nanometers in the second direction, the second overlapping region has a size range of 250-350 nanometers in the second direction, and the third overlapping region has a size range of 100-200 nanometers in the second direction.

79. 75. The display substrate of claim 74, wherein an average size of the first color filter in the first direction is greater than an average size of the second color filter in the first direction and less than an average size of the third color filter in the first direction.

80. 80. The display substrate of claim 79, wherein the first color filters have an average size range of 2.3-2.6 microns in the first direction, the second color filters have an average size range of 1.7-1.95 microns in the first direction, and the third color filters have an average size range of 2.3-2.7 microns in the first direction.

81. 81. The display substrate of claim 80, wherein a ratio of a difference between an average size of the first color filter in the first direction and an average size of the second color filter in the first direction to a difference between an average size of the first color filter in the first direction and an average size of the third color filter in the first direction is in a range of 2-3.

82. 80. The display substrate of claim 79, wherein the first color filter includes a first edge portion, a second edge portion, and an intermediate portion located between the first edge portion and the second edge portion, and an average size of the intermediate portion in the first direction is less than an average size of the first edge portion in the first direction and an average size of the second edge portion in the first direction.

83. the first color filter includes a first contact surface in contact with the second color filter, the second color filter includes a second contact surface in contact with the third color filter, and the third color filter includes a third contact surface in contact with the first color filter; 80. The display substrate of claim 79, wherein a size of the first contact surface in a first direction perpendicular to the driving substrate is equal to a size of the second contact surface in the first direction and is less than a size of the third contact surface in the first direction.

84. 75. The display substrate of claim 74, wherein a distance between the first color filter and a surface of the driving substrate away from the anode layer is greater than a distance between the third color filter and a surface of the driving substrate away from the anode layer, and is less than a distance between the second color filter and a surface of the driving substrate away from the anode layer.

85. 75. The display substrate of claim 74, wherein the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter.

86. 75. The display substrate of claim 74, wherein the color film layer material includes a desiccant.

87. 75. The display substrate of claim 74, wherein the color film layer comprises an aluminum element.

88. 75. The display substrate of claim 74, further comprising a protective layer located on a side of the color film layer away from the driving substrate.

89. The color film layer is 75. The display substrate of claim 74, further comprising a black matrix disposed between any two adjacent ones of the first color filter, the second color filter, and the third color filter.

90. 75. The display substrate of claim 74, further comprising a glass cover plate located on the side of the color film layer away from the driver substrate.

91. The drive circuit includes: a drive transistor including a control pole, a first pole and a second pole; a first transistor including a control pole, a first pole, and a second pole; a second transistor including a control pole, a first pole, and a second pole; the first pole of the first transistor and the first pole of the second transistor are connected to a control pole of the drive transistor, the second pole of the first transistor and the second pole of the second transistor are configured to receive a data signal, and the control pole of the first transistor and the control pole of the second transistor are configured to receive a scan signal; The display substrate of any one of claims 1-90, wherein the second electrode of the driving transistor is electrically connected to the anode and configured to drive the light-emitting functional layer in contact with the anode to emit light.

92. A display device comprising a display substrate according to any one of claims 1 to 91.

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