Dual In-Line Power Module

Abstract

The power module includes a substrate, a power device, and a housing. The power device is mounted on a device pad of the substrate and arranged to provide a power circuit having a first input, a second input, and at least one output. The first and second power terminals provide the first and second inputs to the power circuit. The at least one output power terminal provides the at least one output. The housing encloses the substrate, the power device, and a portion of the first and second input power terminals as well as a portion of the at least one output power terminal.

Description

Detailed Description of the Invention

[0001] [Priority claim] This application is based on and claims the benefit of priority to U.S. Patent Application No. 17 / 736,487, filed May 4, 2022. This application claims priority to and the benefit of the entire contents of the cited applications, which are incorporated by reference. [Field of Disclosure] The present disclosure relates to power modules for high power applications. [Background to disclosure] In high power applications, many components for all or a portion of a circuit are often packaged into electronic modules. These modules are generally referred to as power modules and are housed in a molded housing of thermoplastic, epoxy, or the like that encapsulates the components and the circuit board or substrate on which they are mounted. Input / output connections for the power module are provided by terminal assemblies that extend from the housing for easy assembly and connection to other systems. Such systems may include electric vehicles, power conversion, and control. [overview] The power module includes a substrate, a power device, and a housing. The power device is mounted on a device pad of the substrate and arranged to provide a power circuit having a first input, a second input, and at least one output. The first and second power terminals provide first and second inputs to the power circuit. The at least one output power terminal provides at least one output. The housing encloses the substrate, the power device, and portions of the first and second input power terminals as well as a portion of the at least one output power terminal.

[0002] In one embodiment, the housing contains the substrate, the power devices, and a portion of the first input power terminal, the second input power terminal, and the at least one output power terminal, where the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing. The at least one first input power terminal may provide a first V- terminal and a second V- terminal extending from the first side of the housing. The at least one second input power terminal may provide a first V+ terminal and a second V+ terminal extending from the first side of the housing. The first V+ terminal and the second V+ terminal may be between the first V- terminal and the second V- terminal. The at least one output power terminal may be between the first V+ terminal and the second V+ terminal.

[0003] The at least one output power terminal may provide a first output power terminal providing a first output of the power circuit, a second output power terminal providing a second output of the power circuit, and a third output power terminal providing a third output of the power circuit.

[0004] The plurality of signal terminals may provide a plurality of control signals to the power circuit, with a portion of the plurality of signal terminals extending from a second side of the housing opposite the first side of the housing. The plurality of signal terminals may include a first plurality of gate signal terminals providing gate control signals to gates of a first set of the plurality of power devices and a second plurality of gate signal terminals providing gate control signals to gates of a second set of the plurality of power devices.

[0005] The plurality of signal terminals may further comprise a first plurality of Kelvin source signal terminals for providing Kelvin source control signals to sources of a first set of the plurality of power devices and a second plurality of Kelvin source signal terminals for providing Kelvin source control signals to sources of a second set of the plurality of power devices. Each gate signal terminal of the first plurality of gate signal terminals may be adjacent to a corresponding Kelvin source signal terminal of the first plurality of Kelvin source signal terminals and each gate signal terminal of the second plurality of gate signal terminals may be adjacent to a corresponding Kelvin source signal terminal of the second plurality of Kelvin source signal terminals. Additional terminals may be used for various types of sensors to monitor temperature, current, voltage, etc.

[0006] The pin heads of adjacent pairs of the first and second pluralities of gate terminals and the first and second pairs of Kelvin source signal terminals may be staggered with respect to one another. Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal may have a first pin head and a second pin head staggered with respect to the first pin head.

[0007] The substrate may provide at least one jumper pad, a first bond wire, and a second bond wire, the first bond wire may extend from at least one of the plurality of signal terminals to the at least one jumper pad, and the second bond wire may extend from the at least one jumper pad to a power circuit.

[0008] At least one first input power terminal and / or at least one second input power terminal is directly mechanically coupled to the substrate. At least one output power terminal may not be directly mechanically coupled to the substrate, and a bond wire couples the at least one output power terminal to the power circuit. At least one of the plurality of signal terminals may be directly mechanically coupled to the substrate, and at least one other of the plurality of signal terminals may be directly coupled to the power circuit with a bond wire, while the others are not.

[0009] In selected embodiments, a thermal pad is provided on the bottom surface of the substrate, and the thermal pad is exposed through the housing. The power circuit is a three-phase circuit, full bridge, half bridge, etc. A temperature circuit may be provided on the substrate.

[0010] One or more sides of the housing may be recessed for mounting the power module to another device. At least one of the top and bottom surfaces of the housing may be provided with a creepage extender. One or more recesses may be provided on a first side of the housing between adjacent terminals of the at least one first input power terminal, the at least one second input power terminal, or the at least one output power terminal to reduce creepage.

[0011] In one embodiment, a power module includes a substrate, a power device, and a housing. The power device is mounted on a device pad of the substrate and arranged to provide a power circuit having a first input, a second input, and at least one output. The first and second power terminals provide the first and second inputs to the power circuit. The at least one output power terminal provides the at least one output. The housing contains the substrate, the power device, and a portion of the first and second input power terminals as well as a portion of the at least one output power terminal, and at least one of the at least one first input power terminal and / or the at least one second input power terminal is directly and mechanically coupled to the substrate. The at least one first input power terminal and the at least one second input power terminal are directly and mechanically coupled to the substrate.

[0012] At least one of the plurality of signal terminals may also be directly mechanically coupled to the substrate, and at least one other of the plurality of signal terminals is coupled to the power circuit with a bond wire.

[0013] Based on the above, the present disclosure relates to next generation silicon carbide (SiC) and other material based power devices and compact, high voltage, high current, low inductance power modules designed for power electronics applications. The present disclosure utilizes a novel layout incorporating size and cost optimized power substrates.

[0014] A feature of this design is its scalability and modularity. The layout can be widened or stretched to either (1) accommodate larger devices or (2) place more devices in parallel. In essence, the package concept can be scaled up or down to fit the power handling needs without losing any performance advantage the package offers. These packages can also be easily placed in parallel to increase the converter current and / or form topologies such as three-phase circuits (used in motor drives and inverters) in addition to half and full bridges (often used in DC-DC power conversion).

[0015] Those skilled in the art will appreciate the scope of the present disclosure and realize further aspects of the present disclosure after reading the following detailed description in conjunction with the accompanying drawings. [Brief description of the drawings]

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Figure 1A] 1 shows a schematic diagram of a three-phase circuit. [Figure 1B] 1 illustrates a temperature circuit. [Diagram 2] FIG. 2 is an isometric view of the top surface of a power module according to a first embodiment of the present disclosure. [Diagram 3] FIG. 2 is an isometric view of the bottom surface of the power module according to the first embodiment of the present disclosure. [Figure 4] FIG. 2 is a plan view seen from above of the power module according to the first embodiment of the present disclosure. [Diagram 5] 4A to 4C are corresponding side views of the power module according to the first embodiment of the present disclosure. [Figure 6] 4A to 4C are corresponding side views of the power module according to the first embodiment of the present disclosure. [Figure 7] 4A to 4C are corresponding side views of the power module according to the first embodiment of the present disclosure. [Figure 8] FIG. 2 is a plan view of the power module according to the first embodiment of the present disclosure as viewed from the bottom. [Figure 9] FIG. 2 is a top plan view of a power module according to a first embodiment of the present disclosure, excluding the housing or bond wires. [Figure 10] FIG. 2 is a top isometric view of a power module, excluding the housing or bond wires, according to a first embodiment of the present disclosure. [Figure 11] FIG. 2 is a side plan view of a power module excluding a housing or bond wires according to a first embodiment of the present disclosure. [Figure 12] FIG. 2 is a top plan view of a power module having bond wires, excluding a housing, according to a first embodiment of the present disclosure. [Figure 13] FIG. 2 is a top isometric view of a power module, excluding a housing, having bond wires, according to a first embodiment of the present disclosure. [Figure 14] FIG. 2 is a side plan view of a power module having bond wires, excluding a housing, according to a first embodiment of the present disclosure. [Figure 15] 1 illustrates a terminal pin according to two embodiments of the present disclosure. [Figure 16] 1 illustrates a terminal pin according to two embodiments of the present disclosure. [Figure 17] FIG. 2 is a bottom plan view of the power module excluding the housing according to the first embodiment of the present disclosure. [Figure 18] FIG. 2 is a bottom isometric view of a power module excluding a housing according to a first embodiment of the present disclosure. [Figure 19] FIG. 1 is an exploded view of a first embodiment of the present disclosure. [Figure 20] 1 illustrates an example power loop for a first embodiment of the present disclosure. [Figure 21] 2 illustrates an exemplary signal loop according to a first embodiment of the present disclosure. [Figure 22] 1 illustrates an exemplary embodiment of a power module when used with a larger power device. [Diagram 23] 1 illustrates an exemplary embodiment of a power module when used with smaller power devices. [Figure 24] 1 illustrates an exemplary embodiment of a power module for use with parallel power devices. [Diagram 25] 1 illustrates an exemplary embodiment of a power module in which certain available locations for power devices are unused. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] [Detailed Description] The embodiments described below provide the necessary information to enable one skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description in light of the accompanying drawing figures, one skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically mentioned herein. These concepts and applications should be understood to be within the scope of the present disclosure and the appended claims.

[0018] Although terms such as first, second, etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] When an element, e.g., a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that the element may be directly on or extending directly onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Similarly, when an element, e.g., a layer, region, or substrate, is referred to as being "across" or extending "across" another element, it will be understood that the element may be directly on or extending directly across the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly across" or extending "directly across" another element, there are no intervening elements. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] For example, relative terms such as "lower," "upper," "top," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms and those described above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates the singular. It will be further understood that the words "comprise", "comprising", "including" and / or "comprising", when used herein, specify the presence of stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Furthermore, it will be understood that terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and related technology, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0023] The present disclosure relates to power modules used in high power applications. A power module may include one or more power semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), diodes, etc., arranged in various circuit topologies. Typical circuit topologies include, but are not limited to, a single switch, a half H-bridge circuit, a full H-bridge circuit, and a three-phase switching circuit, often referred to as a six-pack.

[0024] In the following discussion, a three-phase circuit is used to facilitate understanding of the packaging concepts disclosed herein. An exemplary three-phase circuit according to one embodiment of the present disclosure is illustrated in FIG. 1A. Those skilled in the art will recognize that other circuits, such as half-bridge circuits and full-bridge circuits, may be employed. For this example, transistors Q1-Q6 are power silicon carbide (SiC) MOSFETs, each having a drain (D), gate (GX), source (S) and Kelvin source (KX) terminal. For the embodiment described below, transistors Q1-Q6 are vertical N-channel MOSFETs, with the drain contact on the bottom surface of the device and the source, gate and Kelvin source contacts on the top surface of the device.

[0025] Each high-side transistor Q1, Q3, Q5 is coupled in series with a corresponding low-side transistor Q2, Q4, Q6. The drains D of the high-side transistors Q1, Q3, Q5 are coupled to the V+ terminal, and the sources S of the low-side transistors Q2, Q4, Q6 are coupled to the V- terminal. For a first leg of the three-phase circuit, the source S of the high-side transistor Q1 is coupled to the drain D of the low-side transistor Q2 to provide a first output, which is designated as terminal U. For a second leg of the three-phase circuit, the source S of the high-side transistor Q3 is coupled to the drain D of the low-side transistor Q4 to provide a second output, which is designated as terminal V. For a third leg of the three-phase circuit, the source S of the high-side transistor Q5 is coupled to the drain D of the low-side transistor Q6 to provide a third output, which is designated as terminal W. Each of the transistors Q1-Q6 also has an independent gate terminal G1-G6 (collectively GX) and a Kelvin source signal terminal K1-K6 (collectively KX).

[0026] Diodes D1-D6 may be coupled between the drain and source of each of transistors Q1-Q6. In either case, the anodes of diodes D1-D6 will be coupled to the sources of respective transistors Q1-Q6, and the cathodes of diodes D1-D6 will be coupled to the drains of transistors Q1-Q6. Diodes D1-D6 may be separate devices or may be incorporated into the packages of transistors Q1-Q6.

[0027] As shown in FIG. 1B, additional circuitry may be provided in association with the three-phase circuit, such as a temperature circuit 16 for detecting internal device temperature, which may be as simple as a thermistor, a negative temperature coefficient (NTC) device, or a resistance temperature detector (RTD) having terminals TEMP1 and TEMP2. In such an embodiment, the resistance of the thermistor or RTD will change with temperature and be measurable between terminals TEMP1 and TEMP2. A thermistor will generally have a negative temperature coefficient whose resistance is negatively correlated to temperature, while an RTD will generally have a positive temperature coefficient whose resistance is positively correlated to temperature. Additional circuitry, such as a current sensor, may be implemented using functional elements and dedicated pins.

[0028] 2-8 are various isometric and plan views of a power module 10, which provides the electronics necessary to implement various power circuits, such as the three-phase and temperature circuits 16 of FIGS. 1A and 1B according to the first embodiment. FIGS. 2 and 3 are top and bottom isometric views. FIG. 4 is a top plan view. FIGS. 5, 6 and 7 are opposing side and end views, respectively. FIG. 8 is a bottom plan view. The power module 10 has a housing 12, which may include a thermal pad 14 visible in FIGS. 3 and 5-8. The housing 12 may be molded as described below, although other types of housings are contemplated, such as housings having one or more machined or preformed components. The thermal pad 14 is electrically isolated from any internal circuitry and facilitates heat transfer from the power module 10 to surrounding heat sink structures, not depicted, or the like. Other referenced features in these figures are described further below following a description of the internal structure of the power module 10.

[0029] 9-11 illustrate various isometric and plan views of the internal architecture of the power module 10, with the housing 12 and bond wires BW (or similar interconnects) removed to more clearly illustrate the various components of the internal architecture. FIGS. 12-14 illustrate various isometric and plan views of the internal architecture of the power module 10 with the bond wires BW appropriately positioned for an embodiment for a three-phase circuit. The following description will first be directed to FIGS. 9-11, where the bond wires BW are not shown, and will then transition to FIGS. 12-14 when the connections provided by the bond wires BW are discussed. Although the bond wires BW are generically numbered, care has been taken to clearly depict the connections provided by all illustrated bond wires BW. FIGS. 17 and 18 are plan and isometric views of the top surface of the power module 10 with the housing 12 removed.

[0030] 9-11, the center of the internal architecture is a substrate S with a number of conductive device pads 18, 20, 22, 24, 26, 28 formed on one side. A thermal pad 14 is formed on the opposite side, as best shown in FIG. 11. The device pads 18-28 and thermal pad 14 may be formed from any conductive material, such as copper. For the three-phase circuit of FIG. 1A, the high-side transistors Q1, Q3, Q5 are mounted on an elongated device pad 18 that extends along the side adjacent the power terminals V-, V+, U, V, W. The low-side transistor Q2 resides on device pad 20. The low-side transistor Q6 resides on device pad 24. The low-side transistor Q4 resides on device pad 22. The temperature circuit 16 resides on device pad 26, which is formed on the substrate and, in this embodiment, is formed between device pads 20 and 22. Each of the device pads 18 to 26 is electrically isolated from the others.

[0031] In one embodiment, the drains D of the various transistors Q1-Q6 are attached directly to respective device pads 18-24 forming the respective mechanical and electrical connections of transistors Q1-Q6 to device pads 18-24. Temperature circuit 16 may be mechanically and electrically connected to device pad 26 in a similar manner.

[0032] The various terminals can be divided into power terminals and signal terminals. As mentioned above, the power terminals include power terminals V+, V-, U, V, and W. The signal terminals include signal terminals G1-G6, K1-K6, TEMP1, and TEMP2. While each of these terminals can take any shape necessary to operate in the intended application, the terminals shown are adapted to be soldered, pressed, or snapped into corresponding holes in a printed circuit board (not shown). As shown, direct current (DC) input power terminals V- and V+, and alternating current (AC) output power terminals U, V, and W extend from a first side of the power module 10. The signal terminals G1-G6, K1-K6, TEMP1, and TEMP2 extend from a second side of the power module 10, the first side of the power module 10 being opposite the second side of the power module 10.

[0033] There are two power terminals V- at either end of a first side of the power module 10. Each of the power terminals V- extends to either end of an elongated jumper pad J9. Each of the power terminals V- has a pair of power pins P- and legs L- that extend from the power pins P- to the jumper pad J9. In this embodiment, the power terminals V- are directly and mechanically attached to the substrate via the jumper pad J9. Most, if not all, of the legs L- of the power terminals V- are in the housing 12, and the power pins P- extend outside the housing 12 and bend approximately 90 degrees toward the top surface of the power module 10.

[0034] The power terminals V+ are located between the power terminals V− along a first side of the power module 10, with each of the power terminals V+ adjacent to a corresponding one of the power terminals V−. The power terminals V+ extend across the device pads 18 such that the transistors Q1, Q3, and Q5 and the diodes D1, D3, and D5 are located on the device pads 18 between the power terminals V+. Each of the power terminals V+ has a pair of power pins P+ and legs L+ extending from the power pins P+ to the device pads 18. Most, if not all, of the legs L+ of the power terminals V+ are located in the housing 12, and the power pins P+ extend outside the housing 12 and bend approximately 90 degrees toward the top surface of the power module 10. In this embodiment, the power terminals V+ are directly and mechanically attached to the substrate via the device pads 18.

[0035] Each of the power terminals U, V, W is located between the power terminals V+ along a first side of the power module 10. Each of the power terminals U, V, W has a pair of power pins PU, PV, PW and legs LU, LV, LW, respectively. The legs LU, LV, LW do not directly contact any pads on the substrate S. Instead, a group of bond wires BW are used to facilitate the electrical connections.

[0036] 12-14, which include bond wires BW. For power terminal U, a first group of bond wires BW extend from legs LU of power terminal U to source pad SP on the top of transistor Q1 and further to jumper pad J3, which is an extension of device pad 20 and is electrically connected to device pad 20. A second group of bond wires BW extend from legs LU to an anode on the top of diode D1 and further to jumper pad J3. In this way, the first and second groups of bond wires BW connect the source of transistor Q1 to the drain of transistor Q2, the anode of diode D1, and power terminal U.

[0037] For power supply terminal V, a second group of bond wires BW extend from leg LV of power supply terminal V to source pad SP on the top of transistor Q3 and then to jumper pad J4, which is an extension of and electrically connected to device pad 22. The second group of bond wires BW extend from leg LV to an anode on the top of diode D3 and then to jumper pad J4. In this manner, the first and second groups of bond wires BW connect the source of transistor Q3 to the drain of transistor Q4, the anode of diode D3, and power supply terminal V.

[0038] For power terminal W, a third group of bond wires BW extend from leg LW of power terminal W to source pad SP on the top of transistor Q5 and then to jumper pad J6, which is an extension of and electrically connected to device pad 24. A second group of bond wires BW extend from leg LW to an anode on the top of diode D5 and then to jumper pad J6. In this manner, the first and second groups of bond wires BW connect the source of transistor Q5 to the drain of transistor Q6, the anode of diode D3, and power terminal W.

[0039] Signal terminal G1 is electrically coupled to gate pad GP of transistor Q1 via a first bond wire BW extending from signal terminal G1 to jumper pad J1 and a second bond wire BW extending from jumper pad J1 to gate pad GP of transistor Q1. The first bond wire BW is coupled to leg LG1 of signal terminal G1 at a point opposite signal pin PG1.

[0040] Signal terminal K1 is electrically coupled to source pad SP of transistor Q1 via a first bond wire BW extending from signal terminal K1 to jumper pad J2 and a second bond wire BW extending from jumper pad J2 to source pad SP of transistor Q1. The first bond wire BW is coupled to leg LK1 of signal terminal K1 at a point opposite signal pin PK1.

[0041] Signal terminal K2 is coupled to the source pad SP of transistor Q2 via a first bond wire BW. Additional bond wires BW are used to couple the source pad SP of transistor Q2 to a jumper pad J9, which is coupled to the V- terminal. In this embodiment, these additional bond wires BW may have an intermediate connection to the anode of diode D2, which rests on device pad 20 such that its cathode is electrically coupled to device pad 20. The first bond wire BW is coupled to leg LK2 of signal terminal K2 at a point opposite signal pin PK2. Signal terminal G2 is coupled to gate pad GP of transistor Q2 via a second bond wire BW. The second bond wire BW is coupled to leg LG2 of signal terminal G2 at a point opposite signal pin PG2.

[0042] As shown, the temperature circuit 16 may be a vertically oriented semiconductor mounted on and in electrical contact with a device pad 26. A signal terminal TEMP1 is coupled to a top contact of the temperature circuit 16 with a first bond wire BW. The first bond wire BW is coupled to a leg LT1 of the signal terminal TEMP1 at a point opposite the signal pin PT1. The signal terminal TEMP2 extends to the device pad 26 and is directly coupled to the device pad 26 without the use of a bond wire BW. In this manner, the signal terminal TEMP2 is directly and mechanically attached to the substrate via the device pad 26.

[0043] Signal terminal G3 extends to device pad 26 and is directly coupled to device pad 26 without the use of bond wire BW. Signal terminal G3 is thus directly and mechanically attached to the substrate via device pad 28. A bond wire is used to couple device pad 28 to gate pad GP of transistor Q3. Signal terminal K3 is electrically coupled to source pad SP of transistor Q3 via a first bond wire BW extending from signal terminal K3 to jumper pad J5 and a second bond wire BW extending from jumper pad J5 to source pad SP of transistor Q3. The first bond wire BW is coupled to leg LK3 of signal terminal K3 at a point opposite signal pin PK3.

[0044] Signal terminal K4 is coupled to the source pad SP of transistor Q4 via a first bond wire BW. Additional bond wires BW are used to couple the source pad SP of transistor Q4 to a jumper pad J9, which is coupled to the V- terminal. In this embodiment, these additional bond wires may have an intermediate connection to the anode of diode D4, which rests on device pad 22 such that its cathode is electrically coupled to device pad 22. The first bond wire BW is coupled to leg LK4 of signal terminal K4 at a point opposite signal pin PK4. Signal terminal G4 is coupled to gate pad GP of transistor Q4 via a second bond wire BW. The second bond wire BW is coupled to leg LG4 of signal terminal G4 at a point opposite signal pin PG4.

[0045] Signal terminal G5 is electrically coupled to gate pad GP of transistor Q5 via a first bond wire BW extending from signal terminal G5 to jumper pad J8 and a second bond wire BW extending from jumper pad J8 to gate pad GW of transistor Q5. The first bond wire BW is coupled to leg LG5 of signal terminal G5 at a point opposite signal pin PG5.

[0046] Signal terminal K5 is electrically coupled to source pad SP of transistor Q5 via a first bond wire BW extending from signal terminal K5 to jumper pad J7 and a second bond wire BW extending from jumper pad J7 to source pad SP of transistor Q5. The first bond wire BW is coupled to leg LK5 of signal terminal K5 at a point opposite signal pin PK5.

[0047] Signal terminal K6 is coupled to the source pad SP of transistor Q6 via a first bond wire BW. Additional bond wires BW are used to couple the source pad SP of transistor Q6 to jumper pad J9, which is directly coupled to the V- terminal. In this embodiment, these additional bond wires may have an intermediate connection to the anode of diode D6, which rests on device pad 24 such that its cathode is electrically coupled to device pad 24. The first bond wire BW is coupled to leg LK6 of signal terminal K6 at a point opposite signal pin PK6. Signal terminal G6 is coupled to gate pad GP of transistor Q6 via a first bond wire BW. The first bond wire BW is coupled to leg LG6 of signal terminal G6 at a point opposite signal pin PG6.

[0048] In the illustrated embodiment, each of the pins P-, P+, U, V, W of each power terminal V-, V+, U, V, W has dual pin heads that are staggered with respect to each other. For higher voltage power devices, additional power terminals may be employed as power terminals V-, V+, U, V, W. The first pin head of each power terminal V-, V+, U, V, W is linearly aligned with the first pin head of the other power terminal V-, V+, U, V, W, and the second pin head of each terminal is linearly aligned with the second pin head of the other power terminal V-, V+, U, V, W.

[0049] Unlike the power terminals V-, V+, U, V, and W, each of the signal terminals G1-G6, K1-K6, TEMP1, and TEMP2 terminates in a single pin head in the illustrated embodiment. Adjacent pairs of signal terminals are configured such that the pin heads of those signal terminals are staggered. As shown, the pin heads of signal terminals G1, K2, TEMP1, K4, G3, G6, and K5 are linearly aligned with one another while signal terminals K1, G2, TEMP2, G4, K3, K6, and G5 are staggered with signal terminals G1, K2, TEMP1, K4, G3, G6, and K5 while being linearly aligned with one another. Staggered is defined to mean aligned in at least two different planes parallel to the sides of the housing 12 from which the various terminals extend. In alternative embodiments, the pin heads may be all aligned or staggered in a manner different than that shown.

[0050] 15 and 16 show two exemplary pin configurations for any of the various pins (P+, P-, PU, ​​PV, PW, PG1-PG6, PK1-PK6) described above. Pin P1 in FIG. 15 has a straight body B narrowing to a straight head H1 configured to be inserted into a corresponding opening in a printed circuit board or the like and soldered to facilitate a mechanical and electrical connection between the printed circuit board and the head H1. Pin P2 in FIG. 16 has a press-fit head H2 at the end of the straight body B. The press-fit head H2 is designed to radially shrink when inserted into a corresponding opening in the printed circuit board to provide a solderless mechanical and electrical connection between the printed circuit board and the head H1. Once inserted, the press-fit head exerts a radially outward pressure, securing the press-fit head H2 within the corresponding opening. Various press-fit head styles can be used depending on the metal thickness and insertion process. Pin P1 will typically have a curvature of about 90 degrees (i.e., 80-100 degrees) as shown in Figures 9-14. The curvature is not shown in Figures 15 and 16 to better illustrate the linear body and configuration of heads H1, H2.

[0051] 17 and 18, the underside of the substrate S includes a large thermal pad 14 that covers most of the substrate S and is intended to be attached directly to a heat sink, cold plate, or similar heat removal device. Such attachment may be made by either bolting with a thermally conductive material, sintering metal (silver, copper, or other metal), soldering, conductive gluing, welding, or other thermally conductive attachment. Other embodiments of the design may be attached in a similar manner to an interposer base plate, which may then be bolted or welded to the cold plate.

[0052] Reference is now made to an exploded view of the power module 10 in FIG. 19. Starting at the bottom of the figure, the drain pads of the transistors Q1-Q6 and the temperature circuit 16 are electrically and mechanically attached to the device pads 18-26 on the substrate S using device attachment material 40. The device attachment material 40 may be solder, adhesive, sintered metal, laser welding, ultrasonic welding, etc., which provides mechanical structure, high current interconnection, and high thermal conductivity. The power terminals V+, V-, U, V, W, signal terminals G1-G6, K1-K6, and temperature circuit signal terminals TEMP1, TEMP2 may be formed from a single lead frame 44. As detailed above, bond wires BW are used to connect the various components and terminals required to implement the three-phase and temperature circuits of FIGS. 1A and 1B. The lead frame 44 is typically a metal contact strip for high current external and internal interconnections. Any contacts are bonded and processed as an array on a single sheet, often with multiple products per sheet, before being formed and singulated. The bond wires BW may be ultrasonically bonded or thermosonically bonded large diameter wires capable of supporting relatively high current electrical interconnections.

[0053] The housing 12 may be formed using a transfer or injection molding process to provide mechanical structure, high voltage isolation. The housing 12 encapsulates the internal components of the power module 10. The molding compound used for the housing 12 may be a transfer or compression molded epoxy molding compound (EMC) that can provide mechanical structure, high voltage isolation, coefficient of thermal expansion (CTE) matching, and low moisture absorption.

[0054] As illustrated in Figures 3 and 8, the thermal pad 14 on the backside of the power module 10 is exposed, not covered by the housing material. During manufacturing, the epoxy resin used in the housing 12 may seep into the thermal pad 14, leaving a small amount of flashing on the thermal pad 14. To ensure that the molding compound or other encapsulant does not cover the outer surface of the thermal pad 14, retaining pins may be used to press against the edge or other surface of the substrate S to enhance the sealing of the molding die. These pins may be removed as the material cures, leaving marks 42 in the compound. Ejector pins are used to remove the product from the die, and will also leave small marks. The number and location of the retaining and ejector pins will vary based on the design of the embodiment, as more or fewer retaining and ejector pins may be needed as the width of the module changes.

[0055] Clearance and creepage distances are important aspects for high voltage products. Between conductors of different potentials, clearance is the shortest direct path between them in air. Creepage is the shortest direct path between them along a surface. Meeting safety standards is a challenge and often conflicts with manufacturing (molds, epoxy flow, etc.) and product size (footprint and power density). For small transfer molded packages, especially for low profile, high voltage SiC-based products, it is necessary to reach the right balance between module size and voltage safety.

[0056] Regarding creepage, as shown in Figures 2, 3, 4 and 8, the housing 12 may be formed with recesses 46 and / or bumps 48 that increase the surface distance between the various voltage nodes provided by the various signal and power terminals. Creepage between the signal terminals G1-G6, K1-K6, the power terminals V+, V-, U, V, W, and / or the thermal pad 14 may be addressed in a first manner by adding elongated shelves 48 and bumps to the surface of the compound or by placing elongated grooves between the voltage nodes. The specific features will depend on the size and voltage class of a given design embodiment.

[0057] As shown in FIG. 8, dimples 46 may be disposed between each pair of adjacent signal terminals G1 / K1 through G6 / K6 and on either side of the TEMP1 / TEMP2 signal terminal pair. Additional dimples 46 may be disposed between adjacent ones of the power terminals V1-, V+, U, V, and W. Also shown are mounting dimples 52 on both terminal-free sides of the housing. These mounting dimples 52 allow the power module 10 to be rigidly attached to a PCB or other structure using bolts, screws, or other fasteners. The mounting dimples 52 may also function as creepage extenders. In the illustrated embodiment, the transistors Q1-Q6 are aligned on their respective device pads 18, 20, 22, and 24 based on the switch position. The overall layout, length, width, aspect ratio, and number of transistors for each switch position may be parametrically altered to scale up or down to the desired output power of the power module 10. Transistors Q1-Q6 and any other devices may be attached by either (1) metal sintering (silver, copper, or other metal), (2) soldering, (3) conductive adhesive, or (4) other electrically and thermally conductive attachments. A temperature sensor, represented by temperature circuit 16, is included and may be located either on an isolated device pad 26 as shown, or immediately adjacent to one of transistors Q1-Q6, depending on the sensor technology or characteristics of temperature circuit 16. The illustrated temperature sensor is generally attached in a similar manner to transistors Q1-Q6. Depending on the attachment method, the substrate metal used for device pads 18-26 may be fully or partially plated with silver, nickel, nickel / gold, or similar metals, depending on material compatibility.

[0058] Fiducials may be added to aid in automated pick-and-place of transistors Q1-Q6 and / or any other integrated components, as well as to aid in subsequent processing steps requiring determination of relative position. Fiducials may be provided by local plating, etched features or edges, laser marked symbols, or other visually distinct features that may be recognized by a machine vision system.

[0059] Generally, there are two categories of electrical loops in a power module: power loops and signal loops. The power loop is a high voltage, high current path through the transistors Q1-Q6 between the power supply terminals V+, V- to provide power to a load via the drain (or collector) and source (or emitter) of the transistors Q1-Q6, which are connected to the terminals U, V, W of the three-phase circuit. The signal loop is a low voltage, low current path through the gates G1-G6 (or base) and sources (or emitters) of the transistors Q1-Q6. The gate-source (or base-emitter) signal path operates the transistors Q1-Q6 to effectively turn them on or off. The signal loop may also involve the Kelvin source connections K1-K6 of the transistors Q1-Q6.

[0060] The power loop effectively passes between the power terminals V+, V-, which are typically connected across a DC power source, such as a battery, in parallel with a large-capacitor. An exemplary power loop for the illustrated power module 10 is shown in FIG. 20. FIG. 20 illustrates an exemplary power communication loop for the three-phase embodiment described above. The internal and external layout allows power to be transferred in and out of the power module 10 efficiently and with effective flux cancellation. Power flows in (1) through the power terminal V+, (2) into the device pad 18 of the substrate S, (3) to the drains D of the high side transistors Q1, Q3, and Q5, (4) through the high side transistors Q1, Q3, and Q5 to their respective source pads SP, (5) through the bond wires BW and jumper pads J3, J4, and J6 to the respective device pads 20, 22, and 24 of the substrate S, (6) to the drains D of the respective low side transistors Q2, Q4, and Q6, (7) through the low side transistors Q2, Q4, and Q6 to their respective source pads SP, (8) through the bond wires BW to the jumper pad J9, and (9) directly to the power terminal V-. For the various outputs, the power terminals U, V, and W are coupled to the source pads SP of the high side transistors Q1, Q3, and Q5, respectively, using daisy-chained bond wires BW. The loop is well balanced for each device in parallel. The low profile, compact module size, flux cancellation, and balanced loops of the power module 10 result in very low loop inductance and clean, efficient switching.

[0061] The signal loop for each transistor location preferably provides low impedance to minimize voltage stress on the device gate during switching. While voltage stress can be mitigated or reduced by adding resistors, adding resistors often comes at the cost of increased complexity, increased cost, and reduced switching speed. To enhance switching performance, the power and signal loops can be substantially, if not completely, independent of each other to enable low switching losses with fast, well-controlled dynamics.

[0062] In one embodiment, both the drain-source (or collector-emitter) and gate-source (or gate-emitter) loops share the same connection at the source (or emitter) of the various transistors Q1-Q6. When the power path is coupled to the signal path, additional dynamics are introduced through either positive or negative feedback. Negative feedback usually results in extra losses because the power path coupling conflicts with the control signal. In essence, the power path coupling tries to turn the transistor off when the control signal tries to turn it on. Positive feedback usually causes instability because the power path coupling amplifies the control signal until the transistor is destroyed. Ultimately, any significant coupling between the power path and the signal path results in poor switching quality, slower switching speed, increased losses, and possible destruction.

[0063] Therefore, one way to improve switching quality is to ensure the independence of the power and control loops. The power supply connections have separate paths from the signal source (called a Kelvin source) so that one does not overlap or interfere with the other. The closer the separate connections can be to the transistors Q1-Q6, the better the switching performance.

[0064] FIG. 21 illustrates the internal signal loops for the high-side and low-side positions, where the gate signal takes one of two general paths. The first is a direct path, which is used for the signal loops associated with signal terminals G2, G4, and G6, and a single bond wire is used to connect each of signal terminals G2, G4, and G6 to the gate pad GP of transistors Q2, Q4, and Q6. The second path employs a jumper and multiple bond wire jumps. Signal terminal G1 is connected to gate pad GP via jumper pad J1 using two bond wires. Signal terminal G5 is connected to gate pad GP via jumper pad J8 using two bond wires. Signal terminal G3 is slightly different in that it connects directly to device pad 26, and a bond wire BW connects device pad 26 to gate pad GP of transistor Q3.

[0065] The returning Kelvin source signal follows a similar path. The first is a direct path, which is used for the signal loops associated with signal terminals K2, K4, and K6, and a single bond wire is used to connect each of signal terminals K2, K4, and K6 to the source pads SP of transistors Q2, Q4, and Q6. The second path employs one jumper and multiple bond wire jumps. Signal terminal K1 is connected to gate pad GP via jumper pad J1 using two bond wires. Signal terminal K3 is connected to source pad SP via jumper pad J5 using two bond wires. Signal terminal K5 is connected to source pad SP via jumper pad J7 using two bond wires.

[0066] In the illustrated embodiment, a true Kelvin source implementation is provided with completely separate power and signal loops. In some embodiments, transistor devices may be paralleled to increase the output current. When paralleled, an additional problem arises in the mismatch of transconductance between the transistor devices. Transconductance is essentially the current gain of the device, i.e. the relationship between the output current and the input voltage. During switching, the input voltage rises, causing an associated rise in the output current. If there is a transconductance difference between the paralleled transistor devices (as is common in silicon carbide, SiC power devices), the paralleled transistor devices will each have slightly different turn-on characteristics. With different currents flowing through each device, the paralleled transistor devices will have slightly different voltages across them. This voltage mismatch will result in a "balancing current" flowing between the devices during switching.

[0067] This balancing current will prefer the path of least impedance, which may be through the signal loop instead of the power loop. If the balancing current flows through the signal loop, it may affect the switching quality. Introducing this uncontrolled high current through the signal loop may also raise reliability concerns since the signal loop is not intended to carry high current. For these paralleled devices, a jumper bond wire BW may be connected between their source pads SP to create a very low impedance path for these balancing currents.

[0068] Modularity is a beneficial feature of the concepts described herein. As illustrated in FIGS. 22 and 23, within a given footprint, transistors Q1-Q6 and / or other devices of various sizes may be incorporated. For a given footprint, the transistors Q1-Q6 of FIG. 22 are much larger and more power than the smaller, lower power transistors Q1-Q6 of FIG. 23. Such flexibility allows the designer to optimize device sizes and operating parameters for a given system and operating conditions. Device size often correlates with the overall cost of the power module 10, so using appropriately sized devices is key to keeping costs down.

[0069] In some embodiments, the substrate S may be expanded to accommodate a larger number of paralleled devices to improve power handling capabilities. Figures 24 and 25 illustrate the option of either a full implementation (Figure 24) occupying all possible locations, or a reduced implementation (Figure 25) leaving selected possible locations unoccupied. This is a useful approach to tailor device area for a given application, with the added benefit of not having to develop or manufacture new custom devices. Further embodiments and combinations are possible with various device permutations depending on bond pad layout, various device sizes, and larger or smaller numbers of paralleled devices.

[0070] In addition to being highly modular, the layout of the power module 10 is easily scalable to be as compact as possible for the required device size and number of devices. Parametric scalability gives product designers many variables to tune to streamline thermal performance and product size to desired electrical performance parameters.

[0071] As the power module 10 scales up or down, the internal layout scales up or down with it. Since the current will vary based on the total device area, the wider electrical paths dynamically expand to adequately carry the current without excessive resistive losses. Scaling the electrical paths helps ensure that the effective current path to each device is substantially uniform. In some situations, as the size scales up or down, the width of the power terminals and the number of power wire bonds may be increased or decreased as needed or desired.

[0072] The concepts disclosed herein provide an optimized three-phase package design for next generation power modules 10. A module layout is possible where multiple device areas can be fully or partially populated with the same structure. The scalable layout supports a variety of optimized products by simply increasing or decreasing its length and its width to achieve the desired power device area and / or size. The layout may be optimized for high current by grouping the power and signal terminals. In-line edges may be used for the power terminal areas instead of relying on voltage isolation.

[0073] The architecture provides power logic flow with minimal or reduced power loop inductance, which results in clean and efficient switching. The architecture provides a low inductance structure with minimal voltage overshoot to facilitate higher bus voltages and higher voltage operation. The layout also supports paralleling two or more power devices per switch position while providing nearly identical power loop inductance for each power device.

[0074] The signal and power terminals may be arranged and organized with DC input connections on one side and AC output connections on the other, with signal contacts grouped by potential, depending on the application. The dual arrangement of the DC input terminals allows for equal power distribution and low inductance connections to external buses. The internal layout may be configured to minimize bond wire distances with direct bonding of terminals to device pads.

[0075] The concepts herein also provide the option of making electrical connections from the power terminals to the power board via wire bonds or by direct soldering. Staggered power and signal terminals can provide voltage isolation clearance between the various signal and power terminals. In-line power and signal terminals allow for regularly spaced pin pitch for headers, PCBs, etc.

[0076] The architecture provides true Kelvin implementation for the signal loop, resulting in clean and efficient switching. Integrated temperature sensors etc. may be placed close to the power devices. Circuitry such as temperature sensors may be placed on isolated board traces (for non-isolated upright sensors) or on the same trace as the device (for sideways isolated sensors). There is an option for an overcurrent / desaturation signal pin to detect overcurrent events.

[0077] The architecture can reduce costs by minimizing the number of unique components, minimizing power board area, maximizing semiconductor real estate utilization, and high volume processing using lead frames, transfer molding, and manufacturing automation.

[0078] The power module 10 may have molded voltage creepage extenders on the top and bottom of the package. The power module 10 may also include power terminals that can be configured for solder attachment, connection to a header, clipping or soldering to wires, laser welding, or integration with press-fit contacts for solderless connections. The signal terminals can be configured for solder attachment, connection to a header, clipping or soldering to wires, laser welding, or integration with press-fit contacts for solderless connections. The exposed thermal pads on the backside of the power module 10 can be configured for permanent silver sintering, copper sintering, or soldering directly to a cold plate or heat sink. Recesses on the edges of the molding compound of the housing 14 may function as bolt holes to allow for direct, non-permanent bolting to a cold plate or heat sink using thermally conductive materials, thermal gap pads, phase change materials, or the like.

[0079] The above concepts may address one, some, or all of the above to provide a unique and novel power module 10. Those skilled in the art will recognize improvements and modifications to the present disclosure, and all such improvements and modifications are deemed to be within the scope of the concepts disclosed herein.

Claims

1. It is a power module, A circuit board having a bottom surface and a top surface equipped with multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and a portion of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing, Multiple signal terminals for supplying multiple control signals to the power circuit, wherein a portion of the multiple signal terminals extends from a second side of the housing opposite to the first side of the housing, and A power module equipped with this feature.

2. A power module according to claim 1, A power module wherein the at least one first input power terminal comprises a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal comprises a first V+ terminal and a second V+ terminal extending from the first side of the housing.

3. A power module according to claim 2, The first V+ terminal and the second V+ terminal are located between the first V- terminal and the second V- terminal in the power module.

4. A power module according to claim 3, The power module wherein the at least one output power terminal is located between the first V+ terminal and the second V+ terminal.

5. A power module according to claim 4, A power module wherein the at least one output power terminal comprises a first output power terminal that provides a first output of the power circuit, a second output power terminal that provides a second output of the power circuit, and a third output power terminal that provides a third output of the power circuit.

6. A power module according to claim 1, The power module comprises a plurality of signal terminals, each including a first plurality of gate signal terminals that supply gate control signals to the gates of a first set of the plurality of power devices, and a second plurality of gate signal terminals that supply gate control signals to the gates of a second set of the plurality of power devices.

7. A power module according to claim 6, The power module further comprises a plurality of signal terminals, each of which includes a first plurality of Kelvin source signal terminals that supply Kelvin source control signals to the sources of the first set of the plurality of power devices, and a second plurality of Kelvin source signal terminals that supply Kelvin source control signals to the sources of the second set of the plurality of power devices.

8. A power module according to claim 7, A power module in which each gate signal terminal of the first plurality of gate signal terminals is adjacent to a corresponding Kelvin source signal terminal among the first plurality of Kelvin source signal terminals, and each gate signal terminal of the second plurality of gate signal terminals is adjacent to a corresponding Kelvin source signal terminal among the second plurality of Kelvin source signal terminals.

9. A power module according to claim 8, A power module in which the adjacent pairs of pinheads of the first and second plurality of gate signal terminals and the first and second plurality of Kelvin source signal terminals are arranged in an alternating pattern.

10. A power module according to claim 9, A power module in which each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin head and a second pin head arranged alternately with the first pin head.

11. A power module according to claim 1, The substrate comprises at least one jumper pad, a first bond wire, and a second bond wire. A power module in which the first bond wire extends from at least one of the plurality of signal terminals to at least one jumper pad, and the second bond wire extends from the at least one jumper pad to the power circuit.

12. A power module according to claim 1, A power module in which at least one first input power terminal or at least one second input power terminal is directly and mechanically coupled to the circuit board.

13. A power module according to claim 1, A power module in which the at least one first input power terminal and the at least one second input power terminal are directly and mechanically coupled to the circuit board.

14. A power module according to claim 13, A power module in which the at least one output power terminal is not directly and mechanically coupled to the circuit board, and a bond wire couples the at least one output power terminal to the power circuit.

15. A power module according to claim 14, A power module in which at least one of the plurality of signal terminals is directly and mechanically coupled to the substrate, and at least one of the plurality of signal terminals is coupled to the power circuit by a bond wire.

16. A power module according to claim 1, A power module in which at least one of the plurality of signal terminals is directly and mechanically coupled to the substrate, and at least one of the plurality of signal terminals is coupled to the power circuit by a bond wire.

17. The power module according to claim 1, further, A power module comprising a thermal pad on the bottom surface of the substrate, wherein the thermal pad is exposed through the housing.

18. A power module according to claim 1, The aforementioned power circuit is a three-phase power module.

19. A power module according to claim 1, A power module having recesses in one or more sides of the housing for mounting the power module to another device.

20. A power module according to claim 1, A power module in which each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal is terminated with at least one linear pin configured to be soldered to another device.

21. A power module according to claim 1, A power module in which a creepage distance extender is provided on at least one of the upper and lower surfaces of the housing.

22. A power module according to claim 1, A power module in which at least one recess is provided on the first side of the housing between adjacent terminals among the at least one first input power terminal, the at least one second input power terminal, or the at least one output power terminal.

23. A power module according to claim 1, A power module having a temperature circuit provided on the aforementioned substrate.

24. A power module according to claim 1, A power module in which each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin head and a second pin head arranged alternately with the first pin head.

25. It is a power module, A circuit board having a bottom surface and a top surface having multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and a portion of the at least one output power terminal, wherein the at least one first input power terminal or the at least one second input power terminal is directly and mechanically coupled to the substrate, and A power module equipped with this feature.

26. A power module according to claim 25, A power module in which the at least one first input power terminal and the at least one second input power terminal are directly and mechanically coupled to the circuit board.

27. A power module according to claim 26, A power module in which the at least one output power terminal is not directly and mechanically coupled to the circuit board, and a bond wire couples the at least one output power terminal to the power circuit.

28. A power module according to claim 27, A power module in which at least one of a plurality of signal terminals is directly and mechanically coupled to the substrate, and at least one of the plurality of signal terminals is coupled to the power circuit by a bond wire.

29. The power module according to claim 25, further, A power module comprising a plurality of signal terminals for supplying a plurality of control signals to the power circuit, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing, and a portion of the plurality of signal terminals extend from a second side of the housing opposite to the first side of the housing.

30. A power module according to claim 29, A power module in which at least one of the plurality of signal terminals is directly and mechanically coupled to the substrate, and at least one of the plurality of signal terminals is coupled to the power circuit by a bond wire.

31. It is a power module, A circuit board having a bottom surface and a top surface having multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and a portion of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin head and a second pin head arranged alternately with the first pin head, and A power module equipped with this feature.

32. A power module, A circuit board having a bottom surface and a top surface equipped with multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and a portion of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing and Equipped with, A power module wherein the at least one first input power terminal comprises a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal comprises a first V+ terminal and a second V+ terminal extending from the first side of the housing.

33. A power module, A circuit board having a bottom surface and a top surface equipped with multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and a portion of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing and Equipped with, A power module in which at least one first input power terminal or at least one second input power terminal is directly and mechanically coupled to the circuit board.

34. A power module, A circuit board having a bottom surface and a top surface equipped with multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and a portion of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing and Equipped with, A power module in which each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal is terminated with at least one linear pin configured to be soldered to another device.

35. A power module, A circuit board having a bottom surface and a top surface equipped with multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and a portion of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing and Equipped with, A power module in which a creepage distance extender is provided on at least one of the upper and lower surfaces of the housing.

36. A power module, A circuit board having a bottom surface and a top surface equipped with multiple device pads, Multiple power devices are mounted on the aforementioned multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, At least one first input power supply terminal that brings the first input to the power circuit, At least one second input power supply terminal that brings the second input to the power circuit, At least one output power terminal that provides the aforementioned at least one output to the power circuit, A housing for the substrate, the plurality of power devices, and a portion of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing and Equipped with, A power module in which each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin head and a second pin head arranged alternately with the first pin head.

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