Network-on-chip architecture for handling different data sizes

Abstract

The integrated circuit (IC) includes a network-on-chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected to communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. During operation, the plurality of switches are configured to receive data of different widths and to implement different operating modes for forwarding the data based on the different widths.

Description

[Technical field]

[0001] The present disclosure relates to integrated circuits (ICs), and more particularly to a Network-on-Chip (NoC) architecture in an IC that is capable of handling different data sizes. [Background technology]

[0002] A network-on-chip (NoC) refers to a network-based communication subsystem implemented in an integrated circuit (IC). A NoC is capable of transferring data between different data producer and data consumer circuits implemented in the IC. A NoC is often implemented in an IC using multiple interconnected router circuits, e.g., switches, where each router circuit is capable of performing packet switching operations to move data between data producer and data consumer circuits. Summary of the Invention

[0003] In one or more exemplary implementations, an integrated circuit (IC) includes a network-on-chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and to implement different operating modes for forwarding the data based on the different widths.

[0004] In one or more example implementations, a method includes receiving data at a switch of a NoC. The method includes determining, using the switch, a width of the data. The method includes implementing, using the switch, a selected operational mode for processing the data based on the width. The selected operational mode is selected from a plurality of different operational modes. The method includes passing the data through the switch using the selected operational mode.

[0005] This summary section is provided merely to introduce certain concepts, and is not intended to identify any key or essential features of the claimed subject matter. Other features of the inventive subject matter will be apparent from the accompanying drawings and the detailed description that follows. [Brief description of the drawings]

[0006] Arrangements of the present invention are illustrated by way of example in the accompanying drawings. However, the drawings should not be construed as limiting the arrangements of the present invention to only the particular implementations shown. Various aspects and advantages will become apparent upon consideration of the following detailed description and upon reference to the drawings. [Figure 1] 1 illustrates an example of a network-on-chip (NoC) that may be implemented in an integrated circuit (IC). [Diagram 2] Illustrates an example of a deadlock situation that can occur in a conventional NoC. [Diagram 3] 1 illustrates an exemplary implementation of a switch of a NoC in accordance with the inventive arrangements described herein. [Figure 4] 1 illustrates another exemplary implementation of a switch of a NoC in accordance with the inventive arrangements described herein. [Diagram 5] 1 illustrates another exemplary implementation of a switch of a NoC in accordance with the inventive arrangements described herein. [Figure 6] 1 illustrates certain operational characteristics of a mask circuit included in a switch of a NoC in accordance with the inventive arrangements described herein. [Figure 7]1 illustrates an example of connectivity of marking circuits with respect to arbitrators in a switch of a NoC in accordance with the inventive arrangements described herein. [Figure 8] 1 illustrates another exemplary implementation of a switch of a NoC in accordance with the inventive arrangements described herein. [Figure 9] 1 illustrates another exemplary implementation of an NoC. [Figure 10] 1 illustrates another exemplary implementation of an NoC. [Figure 11] 1 illustrates an example method of processing data using a switch of a NoC as described within this disclosure. [Figure 12] 1 illustrates an example architecture for an IC including a NoC in accordance with the inventive arrangements described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present disclosure relates to integrated circuits (ICs), and more particularly to network-on-chip (NoC) architectures in ICs that are capable of handling different data sizes. In one aspect, different flit sizes of data can be dynamically scalable during operation of the NoC. That is, the NoC can handle and route data of different sizes simultaneously during operation, e.g., in real time. A "flit" of data refers to a flow control unit, which is a link-level atomic piece of information. A packet is formed, e.g., from multiple flits. A flit of data is typically sent as multiple parallel, e.g., synchronized, bits.

[0008] A NoC can transfer data between data producer circuits and data consumer circuits within an IC. Within this disclosure, the term "endpoint circuit" may be used to refer to a data producer circuit and / or a data consumer circuit. A NoC may be communicatively linked to various endpoint circuits via certain interface circuits where data enters and leaves the NoC. These interface circuits are connected to multiple switch circuits. Typically, data enters the NoC from a data producer circuit via a first interface circuit, is routed using a switch circuit to a second interface where the data exits the NoC, and is carried from the second interface circuit to a data consumer circuit. In a conventional NoC, the connections between the interface circuits and the switch circuits, and between the switch circuits themselves, are typically fixed in width and therefore operate at a single, predefined data width.

[0009] As an example, a conventional NoC may be implemented with a data width of 128 bits. In this example, each interface circuit and switch circuit is configured to carry a portion of data called a "flit." To traverse the NoC, each flit is created to be the same size. That is, if the NoC is configured to operate with a 128-bit width, then each flit must be 128 bits wide. The NoC cannot carry flits of data of different sizes. If a flit of data is of a different width than that supported by the NoC, such a flit is width converted by the interface circuitry to the width supported by the NoC. For example, a 256-bit flit is converted into two 128-bit flits. These two 128-bit flits traverse the NoC independently as two unrelated 128-bit flits.

[0010] Some conventional NoCs are capable of carrying flits of data of two different widths. However, in such cases, the NoC is bifurcated into different partitions, with each partition configured to carry only flits of data of a particular width. This means that flits of data of a first width stay within a first partition of the NoC configured to carry flits of the first width, while flits of data of a second width stay within a second partition of the NoC configured to carry flits of the second width. The only way that a flit can cross from one partition of the NoC to another is if the NoC includes a data width conversion circuit disposed between the two bifurcated partitions. In order for a flit to move from one partition of the NoC to another partition, the flit must be width converted.

[0011] In accordance with the inventive configurations described herein, a NoC is disclosed that is capable of forwarding data including flits of different widths. That is, the NoC includes circuit nodes that are capable of automatically determining the width of a received flit. In certain aspects, in response to determining the width of the flit, the NoC circuit node can dynamically adjust to the detected width by implementing a particular operating mode that is adapted to the determined width of the flit. The NoC circuit node can forward the flit toward the next circuit node of the NoC. The NoC circuit node can dynamically change between different operating modes for each flit such that flits of different sizes can be handled simultaneously by the NoC without using width conversion circuitry and / or branching of the NoC. Thus, any given switch circuit of the NoC can handle flits of data of different sizes (e.g., widths).

[0012] In one or more other exemplary implementations, the switches of the NoC may include configuration registers that may be programmed to place certain ports of the switch into different operating modes. The particular operating mode in which a given port of the switch is placed depends on the values ​​programmed into the configuration registers that control that port and the width of the data processed or handled by the port. Whether the width of the flit is determined by a flag or indicator contained within the flit itself or using a configuration register, it should be understood that the inventive configurations contemplate switch circuits having one or more ports that operate in a first operating mode carrying flits of a first size simultaneously with one or more other ports of the switch that operate in a second operating mode carrying flits of a second, different size. Further aspects of the inventive configurations are described below with reference to the figures.

[0013] 1 illustrates an example of an NoC 100 that may be implemented within an IC. The NoC 100 is capable of transporting data between endpoint circuits 102 (e.g., 102-1, 102-2, 102-3, and / or 102-4) and endpoint circuits 104 (e.g., 104-1, 104-2, 104-3, and / or 104-4). In this example, for purposes of illustration, endpoint circuit 102 may represent a data producer circuit, while endpoint circuit 104 may represent a data consumer circuit.

[0014] The NoC 100 includes a number of NoC Master Circuits (NMCs) 106 (e.g., 106-1, 106-2, 106-3, and 106-4), a number of NoC slave circuits (NSCs) 108 (e.g., 108-1, 108-2, 108-3, and 108-4), and a number of switches 110 (e.g., 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8, 110-9, 110-10, 110-11, and 110-12). In this example, the NMCs 106 and NSCs 108 are examples of interface circuits through which data may enter and / or exit the NoC 100. Of course, each NMC 106 and each NSC 108 may be implemented as a bidirectional interface that allows data to enter and exit the NoC 100. In general, the NMC 106 is an example of an interface that can receive data from the endpoint circuit 102, while the NSC 108 is an example of an interface that can output data to the endpoint circuit 104. Of course, each NMC 106 and each NSC 108 may be implemented as a bidirectional interface, thereby allowing the endpoint circuit 104 to respond to the endpoint circuit 102 (e.g., allowing data to enter and exit the NoC 100 via each NMC 106 and / or NSC 108).

[0015] In this example, each switch 110 may be connected to neighboring circuits of NoC 100 in the up (north), left (west), right (east), and down (south) directions, so long as there are neighboring circuits in NoC 100. For example, switch 110-3 may receive data via any of the illustrated directions (e.g., from NMC 106-2, switch 110-2, switch 110-9, and / or switch 110-4) and route or forward the received data to circuits in any of the other three directions.

[0016] In this example, each NMC 106, NSC 108, and switch 110 is capable of receiving data having a first width and data having a second, different width. In the case of switch 110, the different width data may be received sequentially or simultaneously by different ports of the switch. In other cases, data of a first width may be received by a given port of switch 110, and immediately thereafter data of a second, different width may be delivered to the same and / or different ports of switch 110.

[0017] In general, the NMC 106, the NSC 108, and the switch 110 can operate in different operating modes. The operating mode implemented can be selected based on the size of the data received or to be processed. In the example of FIG. 1, each different operating mode that can be implemented by the NMC 106, the NSC 108, and the switch 110 can be correlated to a particular data width. In one aspect, each switch 110 can dynamically, e.g., in real time, switch between these different operating modes during operation based on the size of the flit of data received by the respective circuit at any given time. This allows the architecture of the NoC 100 to dynamically scale the flit width of the channels of the NoC 100 based on the required data width and / or bandwidth of the requesting circuits (e.g., the endpoint circuits 102). Thus, the NoC 100 can support multiple different flit widths at full bandwidth.

[0018] The example of Figure 1 illustrates an implementation that supports multiple, e.g., two or more, different data widths being carried through NoC 100 simultaneously at full bandwidth. For example, a given switch 110 may carry data of a first width out of a selected port of the switch and a different width out of a different port of the switch. Similarly, for example, a given switch 110 may carry data of a first width out of a selected port of the switch and then carry data of the same, different width out of the switch. NoC 100 is capable of routing mixed-mode data traffic (e.g., mixed in terms of width) at full bandwidth.

[0019] In conventional NoC architectures that support data with a fixed flit width, interfaces such as the NMC and NSC width convert any incoming data to ensure that the resulting data fits into the fixed width of the NoC. In other conventional NoC architectures, a larger flit of data may be transferred simultaneously as two smaller, independent flits of data (e.g., a 256-bit flit is sent as two independent 128-bit flits). This means that the two 128-bit flits are considered independent within a conventional NoC as if they were from different packets, and do not travel together through the NoC as a unified piece of data, despite being part of the same packet of data. This can lead to a deadlock condition where one half of the data arrives before the other half of the data.

[0020] 2 illustrates an example of a deadlock condition that may occur in a conventional NoC where a larger data flit can be sent as two smaller data flits simultaneously. In the example of FIG. 2, NMC 206-1 forwards flits of data 222, 224, and 226 through switch 210 to NSC 208. Each of flits 222, 224, and 226 is forwarded to NSC 208 as two smaller, independent flits of data corresponding to a first portion A1 and a second portion A2. That is, for flit 222, portion 222-A1 is forwarded as a first flit that is half the size of flit 222, and portion 222-A2 is forwarded as a second, independent flit that is half the size of flit 222. The same is true for flits 224, 226. NMC 206-2 forwards flits of data 228, 230, and 232 through switch 210 to NSC 208. Each of the flits 228, 230, and 232 is transferred to the NSC 208 as two smaller, independent flits of data corresponding to a first portion B1 and a second portion B2, in a manner similar to that of the NSC 206. That is, with respect to the flit 228, the portion 228-B1 is transferred as a first flit that is half the size of the flit 228, and the portion 228-B2 is transferred as a second, independent flit that is half the size of the flit 228. Similarly for the flits 230, 232.

[0021] As shown, in some cases, due to data routing priorities observed by switch 210, only the first portion A1 of flits 222, 224, and 226 arrives at NSC 208, and the first portion B1 of flits 228, 230, and 232 arrives, thereby filling two available buffers. A deadlock condition occurs because the first-in-first-out (FIFO) memory buffers of NSC 208 are full and there is no space to receive the second portion A2 of flits 222, 224, and 226 or the first portion B1 of flits 228, 230, and 232 so that a complete flit (formed from A1 and A2, or B1 and B2) can be output. The operation of NSC 208 effectively freezes and is unable to process any further data.

[0022] FIG. 3 illustrates an exemplary implementation of the switch 110 of FIG. 1. The diagram illustrated in FIG. 3 is simplified for illustrative purposes. In the example of FIG. 3, the switch 110 includes a sub-switch 302 and a sub-switch 304. The sub-switch 302 includes ports 0, 1, 2, 3, and 4. The sub-switch 304 includes ports 5, 6, 7, 8, and 9. As shown, port 4 of the sub-switch 302 is connected to port 9 of the sub-switch 304. In this example, the channel formed by ports 4 and 9 is capable of carrying a flit of data of the same size as a flit of data carried by any one of ports 0-3 or 5-9. The sub-switches 302 and 304 are also connected via a synchronization channel 308, through which the sub-switches 302 and 304 communicate with each other to operate in coordination. Connectivity between sub-switches 302 and 304 via ports 4 and 9 allows flits of data to traverse from one sub-switch to another. It should be understood that each of the sub-switches 302, 304 may have fewer or more ports than shown. In some examples, each sub-switch 302, 304 includes one or more additional ports. Such additional ports may be one or more third-dimensional ports that may be connected to other layers and / or circuits above and / or below a particular layer of an IC in which the sub-switches 302, 304 are implemented.

[0023] Generally, the switch 110 can operate in a number of different operating modes. In a first one of the different operating modes, the switch 110 processes data of a first width. In the first operating mode, selected ports of the sub-switches 302 and 304 can operate independently of each other. In a second one of the different operating modes, the switch 110 processes data of a second width, which is greater than the first width. In the second operating mode, selected ports of the sub-switches 302 and 304 can operate in cooperation, e.g., as a pair.

[0024] As will be discussed, the first and second operating modes are used to process flits of data of different widths. Generally, the first operating mode processes flits of a first width, where the first width corresponds to or is equal to the width of sub-switch 302 (e.g., or sub-switch 304). That is, the first width may be the width of port 0, 1, 2, 3, or 4. The second operating mode processes flits of a second, different width. The second width corresponds to or is equal to the combined width of sub-switch 302 and sub-switch 304. That is, the second width may be the combined width of ports 0 and 5, the combined width of ports 1 and 6, etc.

[0025] 3 is generally described with respect to the switch 110 operating in a particular mode of operation, it should be understood that the mode of operation may be implemented for a selected group of ports. From the perspective of describing the operation of the switch 110, a group of complementary ports is formed from the ports of the sub-switch 302 and the ports of the sub-switch 304. For example, the group of complementary ports present in the switch 110 includes the following pairs (0,5), (1,6), (2,7), and (3,8). As defined herein, the term "group of complementary ports" means a plurality of ports, where the plurality includes one port of each sub-switch of the switch, and each port of the plurality of ports is configured to send data to the same destination outside the switch and to receive data from the same source outside the switch. With reference to the group of complementary ports 0,5, for example, both ports can receive flits of data from the same source outside the switch 110 from the North and can send flits of data to the same destination outside the switch 110 from the North. Similarly, referring to the group of complementary ports 2, 7, both ports are capable of receiving flits of data from the same source outside switch 110 to the South and sending flits of data to the same destination outside switch 110 to the South.

[0026] Although the examples described herein show two sub-switches, it should be understood that the configurations of the present invention are not so limited. In one or more other exemplary implementations, each switch 110 may include three or more sub-switches. For example, each switch 110 may include four sub-switches. In another example, each switch 110 may include eight sub-switches. Thus, rather than each group of complementary ports including only one pair of ports as in the example of FIG. 3, each group of complementary ports includes one port from each of the sub-switches. A complementary group of ports in the four sub-switch example includes four ports, one port of the complementary group taken from each sub-switch. A complementary group of ports in the eight sub-switch example includes eight ports, one port of the complementary group taken from each sub-switch.

[0027] In forming the complementary ports, ports 4 and 9 are excluded. In the example of Figure 3, ports 4 and 9 may be used to transport flits of data of the first size or smaller size between the sub-switches 302, 304. Ports 4 and 9 are not utilized to transport flits of data of larger size.

[0028] For purposes of illustration, consider an example in which each of ports 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9 is a 128-bit port. Each of the ports may include additional signals intended to carry control data, Quality of Service (QoS) data, bit widths, etc. However, for ease of discussion, the width of the data portion of each flit of data will be used to refer to the width of the ports of the sub-switches 302, 304. In a first mode of operation, each of ports 0, 1, 2, 3, 4, 5, 6, 7, and 9 is capable of carrying a 128-bit flit of data.

[0029] In one or more examples, in the first mode of operation, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, only one port of the selected group of complementary ports may pass a single flit of data at a time. For example, for a selected group of complementary ports (2,7), only port 2 or port 7 outputs a 128-bit flit at a given time. Port 7 may pass the 128-bit flit of data in the subsequent or next clock cycle.

[0030] In one or more other examples, in the first mode of operation, for a selected group of complementary ports of the first sub-switch 302 and sub-switch 304, each port of the selected group of complementary ports may pass a single flit of data, either as described or simultaneously. For example, for a selected group of complementary ports (2,7), both port 2 and port 7 may output a 128-bit flit simultaneously. In the first mode of operation, the flits output from ports 2 and 7 may be independent in that the flits belong to different packets of data.

[0031] Figure 4 illustrates another exemplary implementation of the system 110 of Figure 1. The diagram illustrated in Figure 4 is simplified for illustrative purposes. The example of Figure 4 illustrates the switch 110 having ports operating in a second mode of operation. In the second mode of operation, the sub-switches 302, 304 operate in cooperation. Continuing with the example where ports 0, 1, 2, 3, 5, 6, 7, and 8 are each implemented as a 128-bit port, the switch 110 is operable to carry flits that are 256 bits wide by treating a group of complementary ports as a single larger port.

[0032] In the example of FIG. 4 where a 256-bit flit is presented to ports 0, 1, 2, or 3 of sub-switch 304, the flit occupies the port to which it is presented and the complementary port of sub-switch 302. For example, when a 256-bit flit is presented on port 0, the 256-bit flit occupies ports 0 and 5, e.g., a group of ports that are complementary and behave as a single larger port. In this case, port 5 acts or operates as a data buffer. For illustrative purposes, consider an example where a 256-bit flit is directed south to ports 2 and 7. This means that arbitration involving the 256-bit flit is only between ports of sub-switch 302 and may exclude ports of sub-switch 304, e.g., since ports 5 and 7 act as data buffers. Thus, to handle the larger flit size, port 7 does not participate in arbitration when a 256-bit flit is received and routed south. As a corollary, switch 110 only routes 256-bit flits to one of ports 0, 1, 2, or 3. To maintain ordering consistency, 256-bit read request and / or 256-bit write response flits are only routed on ports 0, 1, 2, or 3. 256-bit flits are never routed on ports 4 or 9.

[0033] In one aspect, when operating in the second mode of operation, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, each port of the selected group is configured to simultaneously pass a portion of a single flit of data. For example, consider an example where a 256-bit flit is received by port 0 and routed to port 2. In this example, the selected group of complementary ports is (2,7), which corresponds to the destination port. In this case, port 2 passes a first portion (e.g., 128 bits) of the 256-bit flit simultaneously, and port 7 passes a second portion (e.g., 128 bits) of the 256-bit flit simultaneously. Because the two portions of the 256-bit flit are routed together as a single larger flit, the portions of the 256-bit flit travel together from switch 110 to switch 110 through NoC 100, thereby avoiding the deadlock situation illustrated in FIG. 2.

[0034] In another aspect, when operating in the second mode of operation, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, a selected group of ports from sub-switch 304 are excluded from arbitration. Referring to the previous example where a 256-bit flit is received on port 0 and routed to port 2, port 7 does not participate in arbitration. That is, arbitration occurs only between ports 0, 1, 2, and 3 of sub-switch 302.

[0035] In another aspect, in the second operating mode, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, in response to a first port (e.g., port 0) of the selected group winning arbitration for a flit of data corresponding to a second width (e.g., 256 bits), the first port (e.g., port 0) passes the flit of data only in response to determining that a second port (e.g., port 7) of the selected group has sufficient credits to forward the data.

[0036] In one or more exemplary implementations, each flit of received data may include a particular bit, e.g., a flag bit. The flag bit indicates whether the flit corresponds to a first width or a second, larger width (e.g., 128 bits and 256 bits in this example). That is, the flag bit specifies the width of the flit of data. The flag bit may be included in the payload portion of the flit. In response to any port, referred to as a receiving port on the sub-switch 302 receiving a 256-bit flit, the complementary port of the receiving port operates in a data buffer mode and does not participate in arbitration, as determined by inspecting the state of the flag bit (e.g., if the flag bit is set indicating a second, larger flit width). In the case of a 256-bit flit, for purposes of illustration, both the receiving port and the destination port refer to ports of the sub-switch 302. The destination port of the sub-switch 302 for the 256-bit flit may win arbitration only when the complementary port in the sub-switch 304 of the destination port in the sub-switch 302 has enough credits to make the data transfer.

[0037] To illustrate, referring to the previous example where a 256-bit flit is received at port 0 and routed to port 2, the receiving port is port 0 and the destination port is port 2. The complementary port of receiving port 0 is port 5. Port 5 operates in a buffered mode to process the 256-bit flit and does not participate in arbitration. Furthermore, as stated, destination port 2 wins arbitration for the 256-bit flit only if the complementary port 7 to the destination port has enough credits to make the data transfer. Furthermore, when a destination port wins arbitration for a 256-bit flit, the complementary port of the winning destination port may not win arbitration for a 128-bit flit. Thus, if destination port 2 wins arbitration for a 256-bit flit of data, complementary port 7 does not win arbitration for a 128-bit flit of data.

[0038] FIG. 5 illustrates another exemplary implementation of the system 110 of FIG. 1. In this example, sub-switches 302 and 304 are shown in more detail. In this example, ports 0, 1, 2, 3, 5, 6, 7, and 8 each include an arbiter through which data is output from the sub-switch and a FIFO memory (shown as "FIFO mem") through which data is received into the sub-switch. In the example of FIG. 5, each FIFO memory has an output connected to each arbiter in the same sub-switch with a different port number. That is, FIFO memory 0 is connected to arbiters 1, 2, 3. FIFO memory 1 is connected to arbiters 0, 2, 3, etc.

[0039] In some respects, the diagram illustrated in FIG. 5 has been simplified for purposes of illustration. For example, in some exemplary implementations, each port may support multiple virtual channels, with each virtual channel connected to its own FIFO memory. Thus, for example, if port 0 supports four virtual channels, port 0 will include four FIFO memories (e.g., one for each virtual channel). Additionally, for purposes of illustration, ports 4 and 9 are not shown. However, it should be understood that ports 4 and 9 may be implemented as other ports, where each of ports 4 and 9 includes an arbiter for sending data and a FIFO memory for receiving data.

[0040] Each FIFO memory can present a request to one arbiter at a time for valid requests received by a port. For example, if a FIFO memory has a valid request at the head of its queue (e.g., each FIFO memory has at most one valid request at the head of its queue), the FIFO memory presents the request to the particular arbiter (e.g., one arbiter) to which the request is directed. A request to transfer data from FIFO memory 0 to port 2 will cause FIFO memory 0 to present a request only to arbitrator 2 (e.g., FIFO memory 0 will not submit any requests to arbiters 0, 1, 3, or 4).

[0041] In this example, connections between sub-switches 302 are illustrated through mask circuits 502 (e.g., 502-0, 502-1, 502-2, and 502-3). In one aspect, the previously described synchronization channel 308 between sub-switches 302 and 304 may be implemented by the connections shown through the various mask circuits 502. In the example of FIG. 5, the arbiters for each group of complementary ports are communicatively linked by mask circuits 502. For example, arbiter 0 is communicatively linked to arbiter 5 via mask circuits 502-0. Arbiter 1 is communicatively linked to arbiter 6 via mask circuits 502-1, etc.

[0042] Each mask circuit 502 can ensure that the ports of the group of complementary ports operate as described when operating in the first or second operating modes. For example, referring to an example where a 256-bit flit is output to port 2, mask circuit 502-2 can ensure that a 128-bit flit is not output to port 7 at the same time as a 256-bit flit from port 2. In one or more example implementations, each mask circuit 502 can be implemented as a two-port arbiter where both ports are assumed by mask circuit 502 to have a valid transaction. Each mask circuit 502 can determine which port of the group of complementary ports to select if both ports win arbitration.

[0043] 5, each mask circuit 502 may also be communicatively linked to a data output of each arbiter to which it is coupled by a control signal. For example, mask circuit 502-0 is coupled to arbiters 0 and 5 by a control signal (shown using a dashed line) that is used to select which of arbiters 0, 5 will win arbitration if both win when arbiter 0 carries a 256-bit flit. Mask circuit 502-0 is also coupled to a data output from each of arbiters 0, 5 for purposes of monitoring the status of the outputs of arbiters 0, 5 and updating any state machine circuitry that may be included in mask circuit 502-0 that tracks arbitration winning ports, tokens, and / or port credits, etc.

[0044] FIG. 6 illustrates certain aspects of the operation of the mask circuit 502. In this example, the mask circuit 502-2 is illustrated. As shown, the mask circuit 502-2 can provide a control signal, e.g., one or more mask bits, to each of the arbiters 2 and 7. In this example, the mask circuit 502-2 couples to each of the arbiters 2 and 7 via a register 602. In this example, the inclusion of the register 602, e.g., a clock circuit component, illustrates that the mask circuit 502 does not need to be in the same clock cycle as the arbiters being controlled by the mask circuit. In other words, the calculations performed by the mask circuit 502 to perform arbitration between the arbiters of each group of complementary ports can be separate calculations.

[0045] In one or more examples, the mask circuit 502 may perform a calculation using data from a previous clock cycle to determine the action to be taken in the next clock cycle. The addition of the clock register 602 facilitates the performance of multiple calculations by the mask circuit 502. It also provides a one clock cycle delay for routing data through the switch 110.

[0046] In an example where port 2 outputs 256-bit flits and port 7 also outputs 128-bit flits, mask circuit 502-2 may select port 2. For example, mask circuit 502-2 may output a 0 value via the control signal to provide arbitration or select port 2, or output a 1 value via the control signal to provide arbitration or select port 7. Referring again to this example, the control signals (e.g., mask bits) from mask circuit 502-2 may be used as follows: If port 2 is not the arbitration winner for the 256-bit flit, the mask bits are ignored. If port 7 is not the winner, the mask bits are ignored. If the mask bit is set to 1, authentication is given to port 7, otherwise authentication is given to port 2.

[0047] In one or more examples, each mask circuit 502 may operate as a registered late select. In the fall-through case (when the port arbiter is bypassed), the overhead is limited to that of a 2-to-1 multiplexer. For example, to ensure that the user circuit design can operate at a high clock rate, the mask circuit is designed to utilize an entire clock cycle. Thus, the output of the mask circuit 502 is fed to the register 602 and read in the next clock cycle. In some cases, if the switch has one data flow for a given clock cycle, the switch does not require arbitration. In such cases, the overhead incurred to route data using the mask circuit 502 corresponds to the overhead of a multiplexer, e.g., a clock cycle.

[0048] As illustrated, the mask circuit 502-2 may receive input signals specifying token and / or transaction credit (TC) usage by each of the ports being arbitrated (e.g., ports 2 and 7 in this example). FIG. 7 below illustrates an example of the connectivity of the mask circuit 502-2 to each of the data outputs of arbiters 2 and 7. In one aspect, each mask circuit 502 may implement a state machine capable of tracking token and credit usage by the ports arbitrated by the mask circuit 502. In this example, the mask circuit 502-2 implements a state machine capable of tracking token and transaction credit usage of ports 2 and 7 based on data and / or other information (e.g., traffic class, virtual channel, other control signal information) output from each of arbiters 2 and 7.

[0049] For example, in response to the selection of a winner from port 2 or port 7, the state machine of the mask circuit 502-2 is updated. The information described above (e.g., data, traffic class, virtual channel, and / or other control signal information) may be provided to the mask circuit 502-2 via inputs illustrated in Figures 6 and 7. The mask circuit 502-2 may maintain tokens for ports 2 and 7 and track token (e.g., transaction credit) availability for each of the two ports. Thus, the mask circuit 502-2 may perform QoS tokenization to select the next arbitration winner.

[0050] In one aspect, the mask circuit 502 may be configured to perform a relatively simple arbitration that alternates between arbiters of a group of complementary ports every clock cycle. In other examples, the arbitration may be more complex where the mask circuit 502 collects tokens from each port of the group of complementary ports and continues to select one of the ports as the arbitration winner until that port's tokens are exhausted, at which point the mask circuit 502 begins selecting the other port of the group of complementary ports until that port's tokens are exhausted, and so on.

[0051] Additionally, the exemplary arbitration schemes presented herein are provided for purposes of illustration and are not intended as limitations on the described inventive configurations. More or less complex arbitration schemes may be used that may or may not utilize tokenization of transaction credits and / or QoS.

[0052] Figure 7 illustrates another example implementation of the switch 110 of Figure 1. In the example of Figure 7, arbiters 0, 1, 3, 5, 6, and 8 and FIFO memories 2 and 7 have been removed for ease of illustration. Figure 7 illustrates an example implementation in which the FIFO memory in each sub-switch is coupled to an arbiter in the same sub-switch (e.g., each arbiter has a different port number than the FIFO memory) and also coupled to an arbiter of a complementary port in another sub-switch, as described above.

[0053] The example of Figure 7 is intended to illustrate only the connectivity to arbiters 2 and 7. That is, FIFO memories 0, 1, 3, 5, 6, and 8 are coupled to arbiter 2 and also to arbiter 7. Although not shown in the overall view of switch 110 of Figure 7, FIFO memories 0 and 5 are connected to arbiters 1, 2, 3, 6, 7, and 8, respectively. FIFO memories 1 and 6 are connected to arbiters 0, 2, 3, 5, 7, and 8, respectively, and so on. Neither FIFO memory 0 nor FIFO memory 5 is coupled to arbiter 0 or arbiter 5 (port 5 is the complementary port of port 0). Similarly, neither FIFO memory 1 nor FIFO memory 6 is coupled to arbiter 1 or arbiter 6 (port 6 is the complementary port of port 1), and so on.

[0054] The connectivity described with reference to Figure 7 allows a 128-bit flit of data to be received into one subswitch of switch 110 and output via another subswitch of switch 110. The example of Figure 7 may be used to transport a flit of data from one subswitch to another subswitch within the same switch. As also described, ports 4 and 9 may be used to transport a flit of data from one subswitch to another subswitch. The example of Figure 7 also illustrates where mask circuit 502 may provide control signals to the respective arbiters through register 602.

[0055] In one or more example implementations, with respect to QoS, for every 256-bit flit, the corresponding token value may be updated by 2 (e.g., as opposed to 1 for a 128-bit flit) so that the 128-bit and 256-bit have the same definition of the QoS token.

[0056] In one aspect, each 128-bit flit may be implemented as in a conventional 128-bit NoC implementation, except that an additional flag bit is added to indicate whether the flit is 128 bits wide or 256 bits wide, as discussed above. Table 1 illustrates one example of a data structure that may be used to implement a 256-bit flit for a write transaction.

[0057] [Table 1]

[0058] Table 2 illustrates an example of a data structure that may be used to implement a 256-bit flit for a read transaction (eg, a read response).

[0059] [Table 2]

[0060] Referring to the examples of Tables 1 and 2, for a 256-bit flit, the NoC packet protocol may utilize two 128-bit ports providing a total of 365 available bits (this example considers 256 bits of data and additional control bits). In this example, only 323 bits are available for use. The remaining 42 bits may be left blank or may be reserved. The example data structures of Tables 1 and 2 also illustrate that flag bits may be included in the payload portion of the flit. For a 128-bit flit, the flag bits may be included in the payload portion of the flit.

[0061] FIG. 8 illustrates another exemplary implementation of the system 110. In the example of FIG. 8, the sub-switch 302 includes configuration registers 802 (e.g., 802-0, 802-1, 802-2, and 802-3) corresponding to ports 0, 1, 2, and 3. Each control register 802 can control a corresponding port. For example, control register 802-0 can control port 0. In the example of FIG. 8, a value written to each control register 802 determines whether the port should handle 128-bit flits or 256-bit flits. The example of FIG. 8 does not require the inclusion of a flag bit in the flit itself to indicate the width of the flit. Rather, a controller can be used to program a value into the configuration register 802 to specify whether a given port should operate in a first operating mode or a second operating mode.

[0062] For example, programming configuration register 802-0 for a first mode of operation allows ports 0 and 5 to operate independently, each capable of transporting 128-bit flits independently of the other. Programming configuration register 802-0 for a second mode of operation causes ports 0 and 5 to operate cooperatively to send / receive 256-bit flits.

[0063] In one aspect, the configuration register 802 may be programmed prior to run-time of the NoC 100 where different sets of ports of the sub-switches 302, 304 are programmed to operate in selected modes. As discussed, some ports of the sub-switch 302 may be programmed to operate in a first mode of operation and other ports are programmed to operate in a second mode of operation. In another aspect, the controller 804 may continually program the configuration register 802 during operation to change the mode of operation used by the ports of the sub-switches 302, 304 during run-time or operation of the NoC 100.

[0064] FIG. 9 illustrates another exemplary implementation of the NoC 100. In this example, the NoC 100 includes one or more NMCs 106 implemented as 128-bit NMCs with a single 128-bit port and one or more NMCs 106 implemented as 256-bit NMCs with two 128-bit ports. In the example of FIG. 8, the NMC 106-1 is a 256-bit NMC and the NMCs 106-2, 106-3, 106-4 are 128-bit NMCs. The NoC 100 includes one or more NSCs 108 implemented as 128-bit NSCs with a single 128-bit port and one or more NSCs 108 implemented as 256-bit NSCs with two 128-bit ports. In the example of FIG. 9, the NSC 108-1 is implemented as a 128-bit NSC and the NSC 108-2 is implemented as a 256-bit NSC.

[0065] The 256-bit NMC 106 may receive transactions from the endpoint circuit 102 (not shown) that specify a destination identifier (ID). The destination ID indicates whether the target (e.g., the NSC 108 to which the transaction is to be directed) is a 256-bit NSC or a 128-bit NSC. In response to determining that the target is a 128-bit NSC 108, the 256-bit NMC creates a 128-bit flit of data formatted according to a packet protocol (e.g., the NoC Packet Protocol or NPP) used by the NoC. The 128-bit flits for a given packet of data are forwarded from the NMC to the same port of the switch connected to it. The 128-bit flits may be sent to the switch sequentially; that is, the NMC may forward 128-bit flits of the same packet to the same port of the switch connected to it, thereby avoiding the potential deadlock condition illustrated in FIG. 2.

[0066] In response to determining that the target is a 256-bit NSC 108, the 256-bit NMC 106 may create 256-bit flits of data. The 256-bit NMC 106 may be updated such that the number of flits sent depends on whether the flits sent are 256 bits wide or 128 bits wide. That is, the number of 128-bit flits sent by the 256-bit NMC 106 will be twice the number of 256-bit flits sent out.

[0067] It should be appreciated that the 256-bit NMC is capable of sending two 128-bit flits simultaneously if the two 128-bit flits correspond to different packets. Each of the simultaneously sent 128-bit flits may be sent to a different port of the switch 110 connected to it (e.g., a 128-bit flit is sent to each of complementary ports). Thus, the 256-bit NMC 106 does not require a dedicated arbiter to handle two simultaneous flits.

[0068] In the example of FIG. 9, the 256-bit NSC 108 may receive data specifying a source ID from the endpoint circuit 104 (not shown). The source ID indicates whether the target (e.g., the NMC 106 to which the response is directed) is a 256-bit NMC or a 128-bit NMC. In response to determining that the target is a 128-bit NMC, the 256-bit NSC 108 may create a 128-bit flit of data. In response to determining that the target is a 256-bit NMC, the 256-bit NSC may create a 256-bit flit of data. The 256-bit NSC 108 may be updated such that the number of flits sent out depends on whether the flits are 256 bits or 128 bits wide. That is, the 256-bit NSC 108 may send out two 128-bit flits or one 256-bit flit.

[0069] The 256-bit NSC 108 may include two ports each capable of processing 128 bits of data. The 256-bit NSC 108 can accept a single 256-bit flit or two 128-bit flits simultaneously (e.g., when the two simultaneous 128-bit flits are from different packets). In the example of FIG. 9, when two 128-bit flits are presented, any flit received through port 0, 1, 2, or 3 of the connected switch 110 is routed to a first port of the 256-bit NSC 108, and any flit received from port 5, 6, 7, or 8 of the connected switch 110 is routed to a second port of the 256-bit NSC 108. As a result, the 256-bit NSC 108 does not need a dedicated arbiter to handle two simultaneous flits.

[0070] The 256-bit NSC 108 may also send data to the NMC and generate a flit size based on the size of the received NMC. That is, in response to determining that the destination of the data is a 128-bit NMC, the 256-bit NSC 108 generates 128-bit flits (e.g., for a given packet) that are output to the same port of the switch connected to it. The flits may be output to the ports sequentially. In response to determining that the destination of the data is a 256-bit NMC, the 256-bit NSC 108 generates 256-bit flits.

[0071] The example of Figure 9 illustrates that NoC 100 may simultaneously route both 128-bit and 256-bit flits therein. The example illustrates the state of NoC 100 as both types of flits are routed from one switch 110 to another. The source of each flit is shown, e.g., the particular NMC 106 where the flit entered NoC 100. In the example of Figure 8, each 128-bit flit traverses a single port corresponding to a single sub-switch of each switch 110. Each 256-bit flit traverses a pair (or group) of complementary ports of both sub-switches of each switch 110 simultaneously, with each group of complementary ports behaving as a single larger port.

[0072] Figure 10 illustrates another example implementation of NoC 100. The example of Figure 10 is substantially similar to the example of Figure 9, but illustrates different locations and routing for the respective 128-bit and 256-bit flits contained therein.

[0073] FIG. 11 illustrates an example method 1100 for processing data using a switch 110 of an NoC 100 as described within this disclosure.

[0074] At block 1102, a switch 110 of NoC 100 receives data. At block 1104, switch 110 determines a width of the data. At block 1106, the switch implements a selected operational mode for processing the data based on the width. The selected operational mode is selected from a plurality of different operational modes. At block 1108, switch 110 passes the data using the selected operational mode.

[0075] Each of these and other implementations can optionally include one or more of the following features, either alone or in combination. Some example implementations include all of the following features in combination.

[0076] In one aspect, each operating mode may correspond to one of the possible widths of data. As discussed, different operating modes may be applied independently to different groups of complementary ports of switch 110. That is, complementary ports 2 and 7 may implement a first operating mode, and complementary ports 1 and 6 may implement a second operating mode.

[0077] As stated, the data may include or be formed from one or more flits, and the switch 110 may implement a selected mode of operation for each flit based on the width of the one or more flits.

[0078] In another aspect, determining the width of the data includes determining a state of a flag included in each of the one or more flits. For example, a particular sub-switch 302, 304 receiving the data, e.g., a flit of data, can evaluate a flag bit of the flit to determine whether the flit is a first width or a second width. For purposes of illustration, the first width can be 128 bits and the second width is 256 bits. The state of the flag bit indicates the width of the data.

[0079] In another aspect, determining the width of the data includes programming one or more registers included in the switch, the state of which, when programmed, indicates the width of the data and specifies a selected mode of operation for one or more ports of the switch.

[0080] In one aspect, the switch 110 includes a sub-switch 302 and a sub-switch 304 coupled to the sub-switch 302 by a synchronization channel, where the switch is capable of processing flits of data by operating in a first of a plurality of operating modes in which ports of one or more groups of complementary ports of a first sub-switch and a second sub-switch operate independently.

[0081] In another aspect, the first flit of data has a first width that corresponds to either the width of sub-switch 302 or the width of sub-switch 304 .

[0082] In another aspect, in the first mode of operation, for a selected group of complementary ports, each port of the selected group of complementary ports is configured to pass a flit of data.

[0083] In one example, in a first operating mode, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, only one port of the selected group passes a first flit of data, and the other port of the selected group does not simultaneously pass another flit of data.

[0084] In another example, in the first mode of operation, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, a first port of the selected group is configured to pass a first flit of data and a second port of the selected group is configured to pass another flit of data simultaneously with the first flit of data, where the two flits passed simultaneously may be of different packets.

[0085] In another aspect, the method includes further processing the flit of data by operating in a second operating mode of a plurality of operating modes in which ports of one or more groups of complementary ports of the first sub-switch and the second sub-switch operate in cooperation to send the flit.

[0086] In another aspect, the method includes, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, excluding a selected group of ports from a second sub-switch from participating in the arbitration.

[0087] In another aspect, in the second mode of operation, for a selected group of complementary ports of sub-switch 302 and sub-switch 304, each port of the selected group of complementary ports is configured to simultaneously pass a portion of the same flit of data.

[0088] In another aspect, the second flit of data has a width that corresponds to the width of sub-switch 302 combined with the width of sub-switch 304 .

[0089] FIG. 12 illustrates an example architecture 1200 for an IC including a NoC according to the inventive configurations described herein. The architecture 1200 may also be used to implement a programmable IC, an adaptive system, and / or a System-on-Chip (SoC). In the example of FIG. 12, the architecture 1200 is implemented on a single die provided in a single package. In other examples, the architecture 1200 may be implemented using multiple interconnected dies in a single package, with various resources of the architecture 1200 (circuitry) illustrated in FIG. 12 being implemented across different interconnected dies.

[0090] In this example, architecture 1200 includes a number of different subsystems, including a data processing array 1202, a programmable logic (PL) 1204, a processor system (PS) 1206, a network on chip (NoC) 1208, a platform management controller (PMC) 1210, and one or more hardwired circuit blocks 1212. With the exception of NoC 1208, the various subsystems illustrated in FIG. 12 are provided for purposes of illustration. One or more of the different subsystems may be omitted and / or other subsystems may be added.

[0091] The data processing array 1202 is implemented as a plurality of interconnected programmable computational tiles. The computational tiles may be arranged in an array and are hardwired. Each computational tile may include one or more cores and a data memory. In one exemplary implementation, the cores of the computational tiles may be implemented as custom circuits that do not execute program code. In another exemplary implementation, the cores of the computational tiles may execute program code stored in a core-specific program memory included within each respective core.

[0092] Each computational tile further includes a dedicated multi-bit data movement channel connecting the computational tiles. Each computational tile may further include support for direct memory access (DMA) operations and locks to move data to and from the data memories of other computational tiles. In one or more other exemplary implementations, the data processing array 1202 may include one or more memory tiles that replace one or more of the computational tiles.

[0093] The data processing array 1202 includes an interface block 1222 that connects the computational or memory tiles to other resources of the architecture 1200. In the example of FIG. 12, the interface block 1222 includes a number of interconnected interface tiles organized in a row. In one example, each of the interface tiles may have the same architecture. In another example, the interface tiles may be implemented with different architectures, each different interface tile architecture supporting communication with a different type of resource of the architecture 1200. The interface tiles 1224 are connected such that data may be propagated bidirectionally from one interface tile to another. Each interface tile may act as an interface for the row of computational and / or memory tiles immediately above it.

[0094] PL 1204 is circuitry that can be programmed to perform a specified function. As an example, PL 1204 can be implemented as a field programmable gate array type circuitry. PL 1204 can include an array of programmable circuit blocks. As defined herein, the term "programmable logic" means circuitry used to build reconfigurable digital circuits. Programmable logic is formed from many programmable circuit blocks that provide basic functions. The topology of PL 1204 is highly configurable, unlike hardwired circuitry. In one aspect, each programmable circuit block of PL 1204 includes programmable elements 1226 (e.g., functional elements) and programmable interconnects 1242. Programmable interconnects 1242 provide the highly configurable topology of PL 1204. The programmable interconnect 1242 may be configured on a wire-by-wire basis to provide connectivity between the programmable elements 1226 of the programmable circuit blocks of the PL 1204, unlike the connectivity between the computational tiles and / or memory tiles of the data processing array 1202, which may be configurable on a bit-by-bit basis (e.g., where each wire carries a single bit of information).

[0095] Examples of programmable circuit blocks in PL1204 include configurable logic blocks with lookup tables and registers. Unlike hardwired circuitry, described below and sometimes referred to as hardwired circuit blocks, these programmable circuit blocks have undefined functions at the time of manufacture. PL1204 may include other types of programmable circuit blocks that also provide basic defined functions with more limited programmability. Examples of these circuit blocks may include digital signal processing blocks (DSPs), phase lock loops (PLLs), and block random access memories (BRAMs). These types of programmable circuit blocks, like others in PL1204, are numerous and intermingled with other programmable circuit blocks in PL1204. These circuit blocks may also have architectures that generally include programmable interconnects 1242 and programmable elements 1226, and are therefore part of the highly configurable topology of PL1204.

[0096] The PS 1206 is implemented as hardwired circuitry that is fabricated as part of the architecture 1200. The PS 1206 may be implemented as or include any of a variety of different processor types, each capable of executing program code. For example, the PS 1206 may be implemented as an individual processor, e.g., a single core capable of executing program code. In another example, the PS 1206 may be implemented as a multi-core processor. In yet another example, the PS 1206 may include one or more cores, modules, co-processors, I / O interfaces, and / or other resources. The PS 1206 may be implemented using any of a variety of different types of architectures. Example architectures that may be used to implement the PS 1206 may include, but are not limited to, an ARM processor architecture, an x86 processor architecture, a graphics processing unit (GPU) architecture, a mobile processor architecture, a DSP architecture, a combination of the foregoing architectures, or any other suitable architecture capable of executing computer-readable instructions or program code.

[0097] NoC 1208 is a programmable interconnect network for sharing data between endpoint circuits in architecture 1200. The endpoint circuits may be disposed in DP array 1202, PL 1204, PS 1206, and / or selected hardwired circuit blocks 1212. NoC 1208 may include high-speed data paths with dedicated switching. In one example, NoC 1208 includes one or more horizontal paths, one or more vertical paths, or both horizontal and vertical paths. The configuration and number of regions shown in FIG. 12 are merely examples. NoC 1208 is an example of a common infrastructure that may be used in architecture 1200 to connect selected components and / or subsystems.

[0098] 12, the nets to be routed through NoC 1208 are unknown until a design is created for implementation in architecture 1200. NoC 1208 can be programmed by loading internal configuration registers with configuration data that defines how elements in NoC 1208, such as switches and interfaces, are configured and how they operate to pass data from switch to switch and between NoC interfaces that connect endpoint circuits.

[0099] In one aspect, NoC 1208 is fabricated (e.g., hardwired) as part of architecture 1200 and is not physically modifiable, but may be programmed to establish connectivity between various master circuits and various slave circuits of a user circuit design. NoC 1208 does not implement any data paths or routes therein upon power-on. However, once configured by a master circuit, such as PMC 1210, NoC 1208 implements data paths or routes between endpoint circuits. In one or more example implementations, NoC 1208 may be implemented as described herein in connection with NoC 100.

[0100] PMC 1210 is responsible for managing architecture 1200. PMC 1210 is a subsystem within architecture 1200 that can manage other programmable circuit resources throughout architecture 1200. PMC 1210 can maintain a safe and secure environment, boot architecture 1200, and manage architecture 1200 during normal operation. For example, PMC 1210 can provide unified programmable control over power-on, boot / configuration, security, power management, safety monitoring, debugging, and / or error handling for different subsystems of architecture 1200 (such as DP array 1202, PL 1204, PS 1206, and NoC 1208). PMC 1210 acts as a dedicated platform manager that decouples PS 1206 from PL 1204. Thus, PS 1206 and PL 1204 can be managed, configured, and / or powered on and / or off independently of each other.

[0101] In one aspect, PMC 1210 can act as a root of trust for the entire architecture 1200. As an example, PMC 1210 is responsible for authenticating and / or verifying device images, including configuration data, that may be loaded into architecture 1200 for any of the programmable resources of architecture 1200. PMC 1210 can further protect architecture 1200 from tampering during operation. By operating as a root of trust for architecture 1200, PMC 1210 can monitor the operation of PL 1204, PS 1206, and / or any other programmable circuit resources that may be included in architecture 1200. The root of trust capabilities performed by PMC 1210 are distinct and separate from PS 1206 and PL 1204, and / or any operations performed by PS 1206 and / or PL 1204.

[0102] Hardwired circuit blocks 1212 are special purpose circuit blocks fabricated as part of architecture 1200. Although hardwired, hardwired circuit blocks 1212 may be configured by loading configuration data into control registers to implement one or more different modes of operation. Examples of hardwired circuit blocks 1212 may include input / output (I / O) blocks, transceivers for sending and receiving signals to circuits and / or systems external to architecture 1200, memory controllers, etc. Examples of various I / O blocks may include single-ended and pseudo differential I / O. Examples of transceivers may include high speed differential clock transceivers. Other examples of hardwired circuit blocks 1212 include, but are not limited to, crypto engines, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), etc. Generally, hardwired circuit blocks 1212 are application specific circuit blocks.

[0103] The various programmable circuit resources illustrated in FIG. 12 may be initially programmed as part of the boot process of the architecture 1200. During run-time, the programmable circuit resources may be reconfigured. In one aspect, the PMC 1210 may initially configure the DP array 1202, the PL 1204, the PS 1206, and the NoC 1208. At any point during run-time, the PMC 1210 may reconfigure all or a portion of the architecture 1200. In some cases, the PS 1206, once initially configured by the PMC 1210, may configure and / or reconfigure the PL 1204 and / or the NoC 1208. The PMC 1210, the PS 1206, the hardwired circuit block 1212, and / or the circuitry implemented within the PL 1204 are examples of a controller, such as the controller 804, which may control the state of the control register 802 of the switch 110.

[0104] The present disclosure concludes with claims defining novel features, but it is believed that the various features described within the present disclosure will be better understood from a consideration of the description in conjunction with the drawings. The processes, machines, manufactures, and any variations thereof described herein are provided for illustrative purposes. The specific structural and functional details described within the present disclosure should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to employ the described features in various ways in virtually any appropriately detailed structure. Moreover, the terms and phrases used within the present disclosure are not intended to be limiting, but rather to provide an understandable description of the described features.

[0105] For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding, similar or like features.

[0106] As defined herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0107] As defined herein, the terms "at least one," "one or more," and "and / or" are open-ended expressions that are both conjunctive and disjunctive in operation unless expressly stated otherwise. For example, each of the phrases "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," and "A, B, and / or C" means A alone, B alone, C alone, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C.

[0108] As defined herein, the term "automatically" means without human intervention. As defined herein, the term "user" means a human being.

[0109] As defined herein, the term "if" means "when" or "when" or "in response to" or "depending on," depending on the context. Thus, the phrase "when it is determined that" or "when [a described condition or event] is detected" may be interpreted to mean "upon determining" or "in response to determining," or "upon detecting [a described condition or event]" or "in response to detecting [a described condition or event]," depending on the context.

[0110] As defined herein, the term "in response to" and similar phrases as explained above, such as "when," "when," or "upon," means to readily respond or react to an action or event. The response or reaction is performed automatically. Thus, when a second action is performed "in response to" a first action, there is a causal relationship between the occurrence of the first action and the occurrence of the second action. The term "in response to" indicates a causal relationship.

[0111] As defined herein, the term "real-time" means a level of processing responsiveness that a user or system perceives as immediate enough for a particular process or decision to occur, or that allows the processor to keep up with some external process.

[0112] As defined herein, the term "substantially" means that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations including, for example, tolerances, measurement errors, measurement accuracy limitations, and other factors known to those of ordinary skill in the art may occur in an amount that does not eliminate the effect that the characteristic is intended to provide.

[0113] Terms such as first, second, etc. may be used herein to describe various elements. These elements should not be limited by these terms, as these terms are only used to distinguish one element from another, unless otherwise stated or clearly indicated by context.

[0114] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various aspects of the disclosed configurations. In some alternative implementations, the operations noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. In other examples, the blocks may be executed in a generally ascending numerical order, and in yet other examples, one or more blocks may be executed in various orders, with the results stored and utilized in a subsequent block or in another block that does not immediately follow.

Claims

1. It is an integrated circuit, Network-on-a-chip (NoC), Multiple NoC master circuits, Multiple NoC slave circuits, It includes a NoC, which includes a plurality of switches, the plurality of switches are interconnected, and the plurality of NoC master circuits are linked to communicate with the plurality of NoC slave circuits. An integrated circuit in which the plurality of switches are configured to receive data of different widths during operation and to perform different operating modes for transferring the data based on the different widths.

2. The data received by the aforementioned multiple switches is compiled into a frit, The integrated circuit according to claim 1, wherein each of the plurality of switches is configured to determine the width of the data based on a flag contained in each frit, and to perform a selected operating mode for each frit, selected from the different operating modes based on the state of the flag.

3. The first of the different operating modes processes the data of the first width, The integrated circuit according to claim 1 or 2, wherein the second operating mode among the different operating modes processes data with a second width greater than the first width.

4. Each of the aforementioned multiple switches The first sub-switch and A second subswitch coupled to the first subswitch by a synchronization channel, The integrated circuit according to claim 3, wherein one or more groups of complementary ports of the first sub-switch and the second sub-switch operate independently in a first operating mode and cooperate as a group in a second operating mode.

5. In the first operating mode described above, with respect to a selected group of complementary ports, each port in the selected group of complementary ports is configured to pass data frit. The integrated circuit according to claim 4, wherein, in the second operating mode, with respect to a selected group of complementary ports, each port in the selected group is configured to simultaneously transmit the same portion of the data frit.

6. The integrated circuit according to claim 4, wherein each of one or more groups of the complementary ports is configured to operate in the first operating mode or the second operating mode based on a value stored in a programmable register that controls the group of complementary ports.

7. The first width corresponds to the width of the first sub-switch, and the second width corresponds to the combined width of the first sub-switch and the second sub-switch. The integrated circuit according to claim 4, wherein, in the second operating mode, with respect to a selected group of complementary ports, the ports of the selected group from the second sub-switch are excluded from arbitration.

8. The integrated circuit according to claim 7, wherein, in the second operating mode, with respect to a selected group of complementary ports, the first port of the selected group of complementary ports passes the data frit only in response to the first port determining that the second port of the selected group of complementary ports has sufficient credit to transfer the data, in response to the first port winning arbitration for data frit.

9. A method for routing data in a network-on-a-chip (NoC), In the aforementioned No.C switch, receiving data and The width of the data is determined using the aforementioned switch, Using the switch, perform a selected operating mode for processing the data based on the width, wherein the selected operating mode is selected from a plurality of different operating modes. A method comprising passing the data via the switch using the selected operating mode.

10. The method according to claim 9, wherein the data includes one or more frits, and the switch performs the selected operating mode based on the width of each of the one or more frits.

11. Determining the width of the aforementioned data is The method according to claim 9, comprising programming one or more registers included in the switch, wherein the state of the one or more registers, when programmed, indicates the width of the data and specifies the selected operating mode for one or more ports of the switch.

12. The switch includes a first sub-switch and a second sub-switch coupled to the first sub-switch by a synchronization channel, and the method is To process data frit, the ports of one or more groups of complementary ports of the first sub-switch and the second sub-switch operate in a first operating mode among a plurality of operating modes in which the ports operate independently, The method according to any one of claims 9 to 11, further comprising processing data frit by operating in a second operating mode of a plurality of operating modes in which the ports of one or more groups of complementary ports of the first sub-switch and the second sub-switch cooperate to send frit.

13. The method according to claim 12, wherein, in the first operating mode, with respect to a selected group of complementary ports, each port of the selected group of complementary ports is configured to pass data frit.

14. The method according to claim 12, further comprising, in the second operating mode, excluding a selected group of complementary ports from participation in arbitration from the second subswitch.

15. The method according to claim 12, wherein, in the second operating mode, with respect to a selected group of complementary ports, each port in the selected group is configured to simultaneously transmit the same portion of the data frit.

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