Circuit Package for Connection to an Electronic Photonic Memory Fabric

Abstract

The present disclosure relates to thermal control systems, photonic memory fabrics, and electroabsorption modulators (EAMs). For example, thermal control systems efficiently move data within memory fabrics based on utilizing and controlling thermally controlled optical components. As another example, EAMs are examples of optical modulators used to efficiently move data within digital circuits while maintaining thermally stable optical modulation over a wide temperature range.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims priority to U.S. Patent Application No. 17 / 903,455, filed on September 6, 2022, entitled "PHOTONIC MEMORY FABRIC SUPPORTING MEMORY INTERCONNECTION", which claims priority to U.S. Patent Application No. 63 / 321,453, entitled "PHOTONIC MEMORY FABRIC FOR MEMORY INTERCONNECTION", filed on March 18, 2022; U.S. Patent Application No. 17 / 807,694, filed on June 17, 2022, entitled "MULTI - CHIP ELECTRO - PHOTONIC NETWORK"; U.S. Patent Application No. 63 / 420,330, filed on October 28, 2022, entitled "THERMALLY STABLE OPTICAL MODULATION ELEMENTS COUPLED TO ELECTRONIC ELEMENTS"; and U.S. Patent Application No. 63 / 420,323, filed on October 28, 2022, entitled "THERMAL CONTROL OF AN OPTICAL COMPONENT". Further, this application claims priority to U.S. Patent Application No. 18 / 123,170, filed on March 17, 2023, entitled "THERMAL CONTROL OF AN OPTICAL COMPONENT", and this application claims priority to U.S. Patent Application No. 18 / 123,161, filed on March 17, 2023, entitled "CIRCUIT PACKAGE FOR CONNECTING TO AN ELECTRO - PHOTONIC MEMORY FABRIC". All of these prior applications are hereby incorporated by reference in their entirety.

Background Art

[0002] Applications such as machine learning (ML), deep learning (DL), natural language processing (NLP), and machine vision (MV) have become more complex over time and are being developed to handle more advanced tasks. However, computing devices have not advanced at a pace that can effectively handle the needs of these new applications. For example, ML, DL, NLP, and MV applications cannot fully realize their potential without a sufficiently advanced computing paradigm.

[0003] One solution is to connect multiple chips to a system and enable the chips to send data to each other with low latency and high speed. In one approach, the connections between chips are made using serializer / deserializer (SerDes) blocks that convert parallel messages into serial bit streams that can be transmitted over electrical interconnects or optical fibers between chips. In such a system, on-chip communication and off-chip communication are distinguished. For example, the arithmetic elements on a chip use metal interconnects, but messages destined for another chip must travel through the chip-level interconnects to the interface to the SerDes where the data is converted into a bit stream and transmitted optically. In the receiving direction, the bits arrive at the optical fiber or electrical interconnect, are assembled, and then transmitted via the metal interconnects inside the chip to the destination processor or memory. Considerable energy is consumed both when moving data within the chip to the SerDes and when moving it from the SerDes to other chips in the system.

[0004] Furthermore, the performance of the system when processing the workload is limited by the memory and the bandwidth of the interconnect. In particular, with the rapid increase in AI workloads, the data movement that leads to huge power consumption, performance degradation, and excessive latency exacerbates this problem. The conventional digital computing environment that relies on electrical interconnects is insufficient for the data movement required for AI workloads. Therefore, some existing systems employ hybrid electronic photonic computing. However, these existing systems are troubled by inefficiencies due to long-distance data movement and insufficient thermal environment management.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0006] This application discloses a circuit package for connecting to an n-dimensional electronic photonic memory fabric and / or a method, apparatus, and system for thermal control (e.g., a thermal control system) of an optical component. With respect to the circuit package and the n-dimensional electronic photonic memory fabric, the circuit package has various configurations and is configured to receive message packets from at least one client computing element such as a microprocessor (MPU), a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) accelerator, or other digital application-specific integrated circuits (ASICs).

[0007] Incidentally, when moving data within or between chips, a photonic fabric (e.g., an electro-photonic memory fabric) enables low-latency and low-power data transfer. For example, this fabric is formed from nodes connected by optical links both within and between chips. Data moves from a source node to a destination node within the fabric by moving between the source node and any intermediate nodes until it reaches the destination node. At each node, a message router moves the data along the next hop of the path. For example, when a node receives data along an optical link, the message router performs conversions from optical to electrical and from electrical to optical and transfers the data to the next node along the optical link. At the destination node, the signal is converted to an electrical form and used by the processor and / or memory associated with the destination node.

[0008] As described above, the present disclosure describes an n-dimensional electro-photonic memory fabric that improves the movement of data processed by computing elements (e.g., client computing elements). In particular, the electro-photonic memory fabric provides a hybrid electro-photonic computing environment that moves data or instructions via optical communication by transmitting data packets as electromagnetic waves within an optical carrier such as a waveguide or fiber. By transmitting data or instructions optically, the system is fast and power consumption is minimized. Further, as will be further described below, the electro-photonic memory fabric achieves an efficient balance of data transmission, reception, conversion, processing, and change in both the optical and electrical domains.

[0009] As described above, embodiments of the present disclosure are aimed at solving one or more of the above-described problems and other problems in the relevant technical field. For example, various systems, devices, components, methods, and approaches have provided improved movement of data utilizing an n-dimensional electronic photonic memory fabric. In particular, embodiments of the present disclosure describe connecting a circuit package to a memory fabric that provides an improved hybrid electronic photonic computing environment.

[0010] As shown in various embodiments, an electronic photonic memory fabric achieves optimal system performance by quickly and efficiently processing a workload. For example, the electronic photonic memory fabric described herein reduces the amount of movement required when processing a workload by minimizing the distance between data and computing functions, and maximizes the use of the optical domain when processing a workload. In some embodiments, the electronic photonic memory fabric described herein manages the thermal environment of the hardware layer so that the system operates efficiently without wasting available package space.

[0011] As explained in the foregoing discussion, the present disclosure uses various terms to describe the features and advantages of the one or more embodiments described. For example, this specification often refers to a chiplet. As used herein, a chiplet refers to a small or extremely small integrated circuit (IC) that performs one or more functions. Chiplets are often combined with other chiplets on an interposer in a single package (e.g., a circuit package).

[0012] Additional details related to exemplary embodiments of a chiplet or memory fabric described in connection with the following figures. As shown in FIG. 1, FIG. 1 is a block diagram of an exemplary memory fabric for connecting one or more circuit packages according to one or more embodiments disclosed in the present disclosure. As shown in FIG. 1, FIG. 1 includes a system 100 having a server 102 and circuit packages (i.e., circuit package 104 and circuit package 106). As shown in FIG. 1, system 100 includes a memory fabric (shown as an n-dimensional electronic photonic memory fabric 108) having two nodes (i.e., node 110 and node 112). Although a specific number of nodes and circuit packages are shown in FIG. 1, system 100 can include any number of nodes and circuit packages.

[0013] The components of FIG. 1 show various interconnections. As shown in FIG. 1, the interconnections shown in FIG. 1 include photonic channels 114. Although not explicitly shown in FIG. 1, the memory fabric and circuit packages generally include electronic integrated circuits (EICs) and / or photonic integrated circuits (PICs), and each of the nodes and each of the circuit packages have at least one photonic transceiver whose functionality is partially in the EIC and / or partially in the PIC. Thereby, the photonic transceiver can transmit and receive data packets in the optical domain as electromagnetic waves modulated via the photonic channel 114 or as digital packets via electrical interconnections.

[0014] Various embodiments of the photonic transceiver include, for example, active or passive components within the EIC or active or passive components within the PIC, such as elements that are directly bonded or stacked on top of each other as an inter-chip configuration. For example, copper pillars or another electrical connection connect the active components of the EIC to the passive components of the PIC. In this way, the copper pillars typically bridge a gap from 2 millimeters to 50 microns. In these embodiments, the copper pillar connections are substantially perpendicular to the planes of the EIC and PIC. Further, by directly bonding, directly coupling, or stacking the electrical interconnections between electrical and optical components in this way, the bandwidth of the photonic transceiver is maximized.

[0015] FIG. 2 shows a more detailed example of FIG. 1. In particular, FIG. 2 shows an embodiment of a server-based memory fabric 290 that uses circuit packages to move data within a memory fabric (e.g., to or from compute elements and memory / compute resources).

[0016] As shown, system 200 includes server 102, additional memory / compute resources 206, switch 208, and circuit package 104. Server 102 includes node 110. Although not shown, system 200 and / or server 102 can include additional nodes extending in one or more dimensions. As shown, node 110 includes memory connection region 212, memory controller 232, compute connection region 214, interface controller 234 (e.g., a memory and / or compute interface controller), message router 238 (i.e., a router), routing controller 236, photonic interface 230, and thermal control block 242.

[0017] Also, as shown, node 110 (e.g., server 102) is connected to circuit package 104 via photonic channel 204 and switch 208. Circuit package 104 includes an interposer 222 that connects chiplet 216 and arithmetic element 224 via interconnect 220 and / or connection region 218. In FIG. 2, chiplet 216 includes a photonic interface 228, a message router 226, a switch 210, and a thermal control block 240. Further, circuit package 104 and server 102 are connected to additional memory / arithmetic resources 206 via photonic channel 202 and switch 208 as shown.

[0018] In various embodiments, circuit package 104 is connected to server 102 and additional memory / arithmetic resources 206 via photonic channels (e.g., photonic channel 202 and photonic channel 204). In various embodiments, a switch (e.g., switch 208 or switch 210) is used to determine the timing of using the photonic channel, and thus is used to determine whether circuit package 104 accesses the server-based memory fabric 290 on server 102 or accesses additional memory / arithmetic resources 206.

[0019] FIG. 2 is simplified to show a single node of server 102 (i.e., node 110), but in many embodiments, the chips of server 102 include hundreds of nodes. Further, a multi-chip configuration may have hundreds of thousands (or more) of nodes connected via photonic channels in an n-dimensional memory fabric. In such cases, each of the nodes may have the characteristics of node 110 including a memory connection region 212 and / or an arithmetic connection region 214.

[0020] The memory connection region 212 and the arithmetic connection region 214 are designed to provide a standard interface to arithmetic elements or memory elements integrated into the system 200. In various embodiments, the memory connection region 212 and the arithmetic connection region 214 are configured to accommodate memory elements or arithmetic elements using electrical connections such as copper wires, bump - attach units, copper pillars, through - silicon vias, and / or other connections.

[0021] Examples of memory elements include, but are not limited to, NAND flash memory, solid - state drive (SSD) memory, NOR flash memory, complementary metal - oxide - semiconductor (CMOS) memory, thin - film transistor - based memory, phase - change memory (PCM), storage - class memory (SCM), read - only memory (ROM), random access memory (RAM), magnetoresistive RAM (MRAM), resistive RAM, static random access memory (SRAM), dynamic RAM (DRAM), synchronous dynamic random access memory (SDRAM), double - data - rate (DDR) - based DRAM, high - bandwidth memory (HBM), dual - in - line memory module (DIMM) memory, etc.

[0022] Examples of arithmetic elements include, but are not limited to, CPU, GPU, MPU, tensor engine, load unit, store unit, neural arithmetic engine, dot product, convolution engine, field - programmable gate array (FPGA), and / or AI accelerator.

[0023] The circuit package 104 includes a chiplet 216 and a connection region 218 connected via an interconnect 220. In various embodiments, the chiplet 216 has a bottom surface that is coupled to the connection region 218 via an electrical connection through an interposer 222. In some embodiments, the interconnect 220 can function as an electrical connection. Further, in various embodiments, the interconnect 220 is a standard electrical connection through the interposer 222. In one or more embodiments, the interconnect 220 includes a plurality of channels that correspond to a plurality of ports of either the memory connection region 212 or the arithmetic connection region 214.

[0024] The arithmetic element 224 can be attached to the connection region 218 using various means. The chiplet 216 further includes a message router 226 for controlling the flow of packets between the chiplet and the rest of the system 200. For example, the router forms a digital packet that includes a message request from the arithmetic element in addition to corresponding routing information. In various embodiments, the photonic interface 228 of the circuit package 104 and the photonic interface 230 of the node 110 form an optical bi-directional path for optical signals representing digital packets and can be reconfigured and / or converted into digital form when routed to the electrical port of the message router of the final destination between the server 102 and the circuit package 104.

[0025] Although not particularly shown in FIG. 2, a photonic interface generally includes a photonic transceiver having both a transmitting unit and a receiving unit. In various examples, the transmitting unit converts digital packets into optical signals and transmits them through a photonic channel. Similarly, the receiving unit converts optical signals into digital packets and transmits them through an electrical channel. For example, the photonic interface 228 of the circuit package 104 uses the transmitting unit to connect to the receiving unit of the photonic interface 230 of the node 110 via a first photonic channel, and the transmitting unit of the photonic interface 230 of the node 110 connects to the receiving unit of the photonic interface 228 of the circuit package 104 via a second photonic channel. This enables bidirectional optical communication between the circuit package 104 and the server 102.

[0026] In some embodiments, within a router, the transmitting unit is partially within the dielet 216 and partially within the interposer 222. In these examples, the transmitting unit transmits digital packets in optical form via a fiber array unit (FAU) to the photonic interface in order to move towards the destination indicated in the routing information of the digital packets. Similarly, in various embodiments, the receiving unit is partially within the dielet 216 and partially within the interposer 222. For example, the receiving unit is partially within the dielet 216 and partially within the interposer 222 in order to receive optical signals in digital form via the FAU at the router.

[0027] In one or more embodiments, circuit package 104 requests an item stored in the memory connection area 212 of node 110 and / or utilizes the computing resources available in the computing connection area 214. In such cases, photonic interface 230 receives a request from circuit package 104 via photonic channel 204, converts the request into a digital packet, and provides it to either memory controller 232, interface controller 234, or routing controller 236.

[0028] In various embodiments, memory controller 232 is an electrical interface such as a JEDEC (Joint Electron Device Engineering Council)-compliant or CXL (Compute Express Link)-compliant interface and can be used to access data items stored in memory elements connected to memory connection area 212. In one or more embodiments, interface controller 234 is an electrical interface, device, or module that controls and configures the interfaces of the connected computing elements within computing connection area 214. In some embodiments, interface controller 234 provides an implementation of an algorithm that executes configurations, processes faults, transfers data to and from the interface, and / or generates interrupt events that send signals to computing connection area 214 when events related to the interface occur.

[0029] Further, in one or more embodiments, routing controller 236 is used in the memory fabric when the current node is not the destination node (not shown). In these cases, routing controller 236 modifies the digital packet to update the routing information before transmitting it to a transmission unit connected to an adjacent or next node on the path to the destination node.

[0030] In various embodiments, the message router 238 optically transmits digital packets using one of its optical ports when the current node is not the destination node. Further, in one or more embodiments, the message router 238 outputs digital packets along its electrical ports when computational resources or memory resources are being used at the current node.

[0031] FIG. 2 also includes a thermal control block. As shown in the figure, the server 102 includes a thermal control block 242 and the circuit package 104 includes a thermal control block 240. In various embodiments, the thermal control block provides thermal control to the circuit package 104 and the server base memory fabric 290.

[0032] In some embodiments, a thermally stable optical component such as an electro-absorption modulator (EAM) is used in a photonic integrated circuit (PIC). These optical components are generally manufactured to have an operating range exceeding 30 degrees Celsius. These optical components have a direct connection with active electronic components within an EIC such as a driver, serializer / deserializer (SERDES) blocks, a controller via copper pillars, or another interconnect that can directly bond chips layer-to-layer.

[0033] Since the gap between the active and passive components of a photonic transceiver is relatively small, heat generated by the EIC is often radiated to the PIC, affecting the thermal operating environment of the EAM. In some embodiments, the EAM is designed taking into account the thermal behavior expected of the EIC. In these embodiments, the thermal impact of the EIC operating at maximum load determines the operating range of the EAM to which it is directly coupled.

[0034] Accordingly, one role of the thermal control blocks (e.g., thermal control block 240 and thermal control block 242) is to provide a voltage input to the EAM when necessary to extend its operating range in accordance with the current thermal conditions under which the EAM is operating. Further details regarding the thermal control blocks are provided below.

[0035] FIG. 3 is a diagram illustrating the use of a memory fabric for connecting circuit packages. As shown, FIG. 3 includes a memory fabric 330 and circuit packages (i.e., circuit package 118 and circuit package 120). The memory fabric 330 is conceptually shown from a top view. As shown, the memory fabric 330 is part of the server 302 and includes a plurality of nodes 304 interconnected via photonic channels 318. One or more of the plurality of nodes 304 are also directly connected to the circuit packages via photonic channels 320. In various embodiments, the photonic channels include inter-chip links and intra-chip links. FIGS. 5 and 6 provide further details regarding the photonic channels. FIG. 9 provides further details and internal components of the nodes.

[0036] As shown in the figure, the memory fabric 330 includes 16 nodes (i.e., a plurality of nodes 304) arranged in a 4×4 two-dimensional grid. In other embodiments, the memory fabric 330 is of a higher dimension and has additional ports or switches that enable the connection of n-dimensional nodes. In embodiments where a 4×4 grid is used for the memory fabric 330, each of the plurality of nodes 304 has at least four optical ports and one electrical port. In these embodiments, the optical ports enable the interconnection of all the internal nodes. For example, the transmission unit and the reception unit of adjacent nodes are optically connected by a photonic channel, realizing a bidirectional optical connection between the nodes. The nodes at the periphery of the grid can have optical ports dedicated to the circuit package and / or can be used for inter-chip or intra-chip links with other nodes (not shown). Alternatively, if additional ports are not required, the optical ports of the nodes may not be used or fabricated (e.g., the nodes have only two or three optical ports), such as in the case of corner nodes.

[0037] In various embodiments, each of the plurality of nodes 304 of the memory fabric 330 includes one or more message routers (not shown) that are used with the photonic channels 318 to form an electro-photonic network. In these embodiments, the message routers are arranged in a two-dimensional quadrilateral array or grid. The message routers of two nodes that are immediately adjacent to each other (e.g., in either the horizontal or vertical direction) are connected by a bi-directional channel. In this way, each message router inside the array includes at least four photonic channel interfaces, and the interfaces correspond to each of at least four bi-directional photonic channels (e.g., one for each direction that can be called "north", "south", "east", and "west"). Further, along the periphery of the array, the routers only need to have two (at the corners) or three (at the edges between the corners) photonic channel interfaces in order to function as the memory fabric 330. In various embodiments, as shown with respect to the circuit package 118 and the circuit package 120, some or all of the photonic channel interfaces of the corner nodes and edge nodes that are not dedicated to the memory fabric 330 are used for point-to-point connections to the circuit packages.

[0038] In various embodiments, the message routers use various addressing schemes to route messages between the circuit packages and the plurality of nodes 304. Regardless of the addressing scheme, the messages may be transferred primarily or exclusively through the memory fabric 330 via the photonic channels 318 and / or the photonic channels 320 within the PIC (with optoelectronic conversion and electro-optic conversion at each router along the path).

[0039] In one or more embodiments, packet data is provided between multiple nodes 304 and / or between circuit packets and includes routing information indicating their destinations. For example, signed 5-bit packet data (e.g., extracted from a message header or payload) provides the relative position (or distance) in the horizontal direction (east / west) to the destination node. As another example, signed 5-bit packet data provides the relative position (or distance) in the vertical direction (north / south) to the destination node. In various embodiments, packet data of different sizes (e.g., number of bits) is used (e.g., depending on the number of nodes and the resulting size of the address space).

[0040] When a message passes through a router and reaches different nodes, the routing information can be changed. For example, the horizontal or vertical coordinates of the routing information are decremented for each hop according to the dimension in which the message is being transferred. In this example, when the packet data providing an indication to the destination node decrements or decreases to zero, it means the message has arrived at the destination node. It is then transferred to the local electrical port of the router of that node and utilized by computing resources or memory resources. In some cases, the message is used for reading and writing memory transactions between nodes or between circuit packages.

[0041] In one or more embodiments, the server 302 includes a thermal control block 332. As described above, the thermal control block will be described in detail later. In various embodiments, the thermal control block responds to changes in the thermal state of the PIC in one or all of the multiple nodes 304. In one example, the thermal control block cycles through each of the multiple nodes 304 and supplies the input voltage of the node to the PIC (when necessary). For example, the thermal control block provides the input voltage in a magnitude set to return the EAM of the node to peak operating conditions during each cycle time.

[0042] FIG. 4 is a diagram showing a high-dimensional memory fabric such as a three-dimensional memory fabric for connecting circuit packages. As shown, FIG. 4 shows a perspective view of a high-dimensional memory fabric 400 for connecting a circuit package 118.

[0043] In FIG. 4, the high-dimensional memory fabric 400 has a plurality of layers 404 including a first layer 404a and a second layer 404b. Each of the plurality of layers 404 includes a router 402. In particular, the first layer 404a includes routers 402a, 402b, 402c, and 402d, and the second layer 404b includes routers 402e and 402f.

[0044] In the illustrated embodiment, the router 402 includes an optical port. For example, the optical ports between the routers (i.e., routers 402a - d) on the first layer 404a are enhanced by high-dimensional links 405a, 405b, 405c, and 405d. As shown in FIG. 4, the circuit package 118 is connected to the high-dimensional memory fabric 400 via one of the routers 402a on the first layer 404a. Further, depending on the nature and topology of the high-dimensional memory fabric 400, any number of additional circuit packages can be connected to any number of additional routers and ports.

[0045] In various embodiments, the high-dimensional memory fabric 400 forms a mesh or a different shape. Further, the high-dimensional memory fabric 400 forms a wrapped mesh, a toroidal, a wrapped toroidal, or an extensible wrapped toroidal.

[0046] As described above, FIGS. 5 and 6 show further details regarding inter-chip links and intra-chip links. FIG. 5 shows an example of an intra-chip link, and FIG. 6 shows an example of an inter-chip link.

[0047] As described with reference to FIG. 5, FIG. 5 shows an example of a photonic link (i.e., an "intra-chip link") that connects nodes of a memory fabric. As shown, FIG. 5 includes a light engine 500, a first splitter tree 502a, a second splitter tree 502b, a set of optical modulators 510a, 510b, 510c, and 510d, a set of respective waveguides (e.g., waveguides 512a, 512b, 512c, and 512d), and a set of photodetectors 514a, 514b, 514c, and 514d.

[0048] For intra-chip optical communication, the light engine 500 can be an on-chip or off-chip laser light source, and the light engine 500 outputs light 504 (e.g., carrier light) of a single wavelength (e.g., λa1). The first splitter tree 502a can split the light 504 into a plurality of optical paths 506 leading to optical modulators associated with different nodes and photonic channels on the chip.

[0049] As shown, FIG. 5 shows light branching and moving along a plurality of optical paths 506, and one of the optical paths (i.e., the central optical path) leads to the illustrated components. The other optical paths (terminated with arrows) may lead to other nodes and photonic channels (not shown) on the chip.

[0050] In various embodiments, the light traveling along one of the plurality of optical paths 506 is further split. For example, the second splitter tree 502b splits the light in the optical path into additional optical paths 508 to provide light to the set of optical modulators 510a-d. In some embodiments, the second splitter tree is a demultiplexer (demux). As shown, the set of optical modulators 510a-d corresponds to the set of photodetectors 514a-d via the set of respective waveguides 512a-d.

[0051] In some embodiments, the set of optical modulators 510a - d is associated with a set of unidirectional photonic links that are coupled to form a bonding group. For example, the bonding group of unidirectional photonic links runs in the same direction within a unidirectional photonic channel from one node of the memory fabric to another node.

[0052] In some embodiments, there are two such unidirectional photonic channels, each formed in opposite directions between the same node pair of the memory fabric, forming an in - chip bidirectional photonic channel. As shown in the figure, the set of optical modulators 510a - d represents EAMs and / or modulates light to have a single wavelength (e.g., λa1), and transmits the modulated light to photodetectors 514a - d located at different nodes of the same chip via respective waveguides 512a - d.

[0053] As described above, FIG. 6 provides an example of an inter - chip link. For example, FIG. 6 shows a connection between two adjacent nodes (e.g., the first chip 600a and the second chip 600b) in different chips, or a point - to - point connection between the memory fabric and the circuit package (i.e., an "inter - chip link") according to some embodiments. In various embodiments, the chips implement one or more machine - learning processors and / or photonic integrated circuits (PICs).

[0054] As shown, the first chip 600a includes a light engine 650, a splitter tree 602 that generates a plurality of optical paths 606, a demultiplexer 654, optical modulators 656a, 656b, 656c, 656d connected to a multiplexer 680 (mux) via different waveguides 672a, 672b, 672c, 672d, and a grating coupler 640. The first chip 600a is connected to a second chip 600b via a fiber connector 642. Further, the second chip 600b includes a grating coupler 645, a waveguide 646, a demultiplexer 682, and photodetectors 692a, 692b, 692c, 692d connected via different waveguides 674a, 674b, 674c, 674d.

[0055] More specifically, the first chip 600a includes a light engine 650, which can be an on-chip or off-chip laser light source. The light engine 650 provides light having a plurality of wavelengths (e.g., between 2 and 16 wavelengths). For example, the light engine 650 provides light having four wavelengths λb1, λb2, λb3, and λb4. The splitter tree 602 (e.g., similar to the first splitter tree 502 in FIG. 5) can split the light into a plurality of wavelengths among a plurality of optical paths 606. Only one of the plurality of optical paths 606 is shown leading to different nodes of the first chip 600a having additional components, but each of the plurality of optical paths 606 may lead to different sets of similar components.

[0056] For the illustrated optical paths, they lead to optical modulators 656a - d associated with different photonic channel interfaces within the nodes. For example, the carrier light of wavelengths λb1, λb2, λb3, λb4 is supplied to the optical modulators 656a - d associated with a plurality of peripheral photonic channel interfaces. Before reaching the optical modulators 656a - d, the light is separated by the demultiplexer 654 for each wavelength (e.g., λb1, λb2, λb3, and λb4). For example, the optical modulators 656a - d each represent a different modulator (e.g., EAM).

[0057] In various embodiments, the optical modulators 656a - d modulate the carrier light at different wavelengths λb1, λb2, λb3, and λb4, and supply the modulated optical signals having respective wavelengths to a multiplexer 680 (e.g., a WDM multiplexer) via different waveguides 672a - d (e.g., via different optical links). The multiplexer 680 generates a multiplexed output including four data streams each encoded at a different wavelength. As shown, the multiplexed output is supplied to a grating coupler 640 on a single waveguide 639, where the multiplexed modulated optical signal is coupled out of the chip via a first optical fiber 641.

[0058] As shown, the first chip 600a and the second chip 600b are connected via a fiber connector 642. In particular, the grating coupler 640 of the first chip 600a is connected to the fiber connector 642 via the first optical fiber 641. The fiber connector 642 is connected to the grating coupler 645 of the second chip 600b via a second optical fiber 643. In this way, the first chip 600a can supply one or more optical signals to the second chip 600b and / or other chips via an inter - chip link.

[0059] Also as shown, the second chip 600b receives the multiplexed modulated optical signal from the fiber connector 642 via the second optical fiber 643. In some embodiments, a coupled fiber may be used instead of or in addition to the fiber array unit (FAU) and the grating coupler.

[0060] In the second chip 600b, the grating coupler 645 supplies the multiplexed modulated optical signal to the demultiplexer 682 via a single waveguide. The demultiplexer 682 demultiplexes the multiplexed modulated optical signal and outputs four separate modulated signals having four different wavelengths such as λb1, λb2, λb3, and λb4 (or the corresponding number of 2 to 16 wavelengths). In various embodiments, these four signals are supplied to the photodetectors 692a - d corresponding to different wavelengths via different waveguide optical waveguides 674a - d.

[0061] In various embodiments, the chip of FIG. 6 represents a system - in - package (SIP) that uses wavelength - division multiplexing (WDM) for inter - chip optical communication. For example, the components shown in FIG. 6 form one - way photonic channels between nodes of different SIPs. In some cases, there are two such one - way photonic channels that are formed between the same node pair of the SIP, forming an inter - chip bidirectional photonic channel.

[0062] The above - described embodiments are directed to a photonic channel showing four one - way optical links and a WDM multiplexer that receives four different wavelengths, but in other embodiments, two or more optical links and a WDM multiplexer that receives two or more different wavelengths may be used. In these embodiments, the demultiplexer outputs two or more different wavelengths in a manner similar to the above.

[0063] In various embodiments, one or more processing elements within one or more EICs of one or more SIPs can be connected to an electro - photonic network using photonic channels within and between chips as described above, such as including one or more links for each direction. In such cases, the resulting network topology generally depends on the selection of node pairs that are directly connected via the associated photonic channels. Indeed, examples of various topologies are possible. Further, the present disclosure generally refers to bidirectional photonic channels, which, compared to unidirectional photonic channels, result in a network structure that provides more flexibility for implementing machine learning (ML) and other computational models, although an electro - photonic network can in principle also be formed with unidirectional photonic channels. Further, such a network can retain many of the advantages described in the present disclosure (e.g., power savings through longer - distance optical data transfer).

[0064] Figures 7 and 8 show different embodiments of a circuit package (including chiplets) for optically connecting client computing elements via a photonic interface. As shown, Figures 7 and 8 each include a photonic fabric interface chiplet 701, a computing element 702, and a PIC interposer 704 (i.e., a photonic integrated circuit interposer). Figure 7 further includes a standard interposer 706, which is not included in Figure 8 and will be described later. As described above, the computing element 702 (e.g., a client computing element) may represent an MPU, GPU, CPU, AI accelerator, or other digital ASIC.

[0065] Furthermore, the photonic fabric interface chiplet 701 of FIGS. 7 and 8 includes a router 710, a thermal control block 712, a driver 714, and an amplifier 716 for forming digital packets including message requests from the arithmetic elements. The PIC interposer 704 includes a modulator 718 for transmission, a photodiode 720 for reception, and a multiplexer / demultiplexer 722 connected to a fiber array unit 724 (FAU) connected to the PIC interposer 704. Also, as shown in the figure, the modulator 718 and the photodiode 720 of the PIC interposer 704 are connected to the driver 714 and the amplifier 716 of the photonic fabric interface chiplet 701, respectively. The modulator 718 of the PIC interposer 704 is also connected to the thermal control block 712 of the photonic fabric interface chiplet 701.

[0066] As described above, FIG. 7 includes a standard interposer 706. More specifically, the circuit package 700 shows an arithmetic element 702 connected to the photonic fabric interface chiplet 701 via the connection region 708 of the standard interposer 706. The standard interposer 706 routes the connection from the arithmetic element 702 to the router 710 of the photonic fabric interface chiplet 701 via the PIC interposer 704 as shown in the figure. In various embodiments, the thermal control block 712 (e.g., a photothermal control block) sends an input to the modulator 718 as needed.

[0067] FIG. 8 does not include a standard interposer. Instead, as shown, circuit package 800 includes a PIC interposer 704 that interfaces between arithmetic element 702 and photonic fabric interface chiplet 701. For example, PIC interposer 704 includes a connection area 709 that receives messages from arithmetic element 702 and provides them via an electrical connection to router 710 of photonic fabric interface chiplet 701. In fact, in FIG. 8, the bottom surface of photonic fabric interface chiplet 701 is electronically connected to connection area 709 of PIC interposer 704.

[0068] In various embodiments, each router 710 of FIGS. 7 and 8 is a message router that is partially in PIC interposer 704 and partially in photonic fabric interface chiplet 701. In these embodiments, router 710 is configured to convert an optical signal into a digital packet in a receiving unit and / or convert a digital packet into an optical signal in a transmitting unit.

[0069] By coupling to arithmetic element 702, photonic fabric interface chiplet 701 can be optically connected to another photonic interface in another device (e.g., via an inter-chip link or an intra-chip link). For example, photonic fabric interface chiplet 701 optically connects arithmetic element 702 to a server and / or a memory fabric. Also, although FIGS. 7 and 8 show a fiber array unit 724, photonic fabric interface chiplet 701 may be optically connected bi-directionally to other devices via waveguides or other optical means. In fact, the fiber array unit facilitates bi-directional communication with connected nodes and devices (e.g., laser light and / or messages are transmitted and received to and from a photodiode via fiber array unit 724).

[0070] Figure 9 shows the nodes of the memory fabric in more detail. As shown, Figure 9 includes a plurality of nodes (e.g., nodes 900, 902, 904, 906, and 908), but only node 900 is shown with its internal components, elements, and connections. Thus, the description of node 900 can also apply to the other nodes shown.

[0071] As shown, node 900 includes various components such as a routing controller 920, a memory 922, a thermal control block 924, an electrical port 926, a message router 928, an optical port 930, a FIFO register 932, and a thermally stable optical modulation element 934. Some or all of these components have been described above. Further, node 900 communicates with other nodes via one or more photonic channels 940, as previously explained.

[0072] As shown, node 900 also includes one or more memory connection regions and / or arithmetic connection regions (shown as connection region 912). As shown, connection region 912 includes a memory controller and / or an arithmetic controller (shown as memory / arithmetic controller 914) and a memory and / or an arithmetic element (shown as memory / arithmetic element 916). In various embodiments, the memory and arithmetic connection regions use standard electrical interconnect technologies such as copper wires, bump attach units, copper pillars, through-silicon vias, etc. to house the memory elements or arithmetic elements. Examples of memory elements and / or arithmetic elements are described above with reference to Figure 2.

[0073] In one or more embodiments, the connection region 912 is coupled to a memory device such as an HBM into which data (e.g., an embedding table) for use in machine learning (e.g., training and / or inference) is loaded. For example, the circuit package can communicate with the data in the HBM in response to requests of the running AI workload. In some examples, the output of the circuit package is an optical signal converted from a digital packet, and the digital packet is formed on the chiplet in response to a request for data from the computing element. In such a case, the memory fabric has an inter-chip or intra-chip link to the circuit package at one port of one of its external 12 nodes.

[0074] In various embodiments, a node is a destination node when it is located in a memory fabric having an HBM with the requested data. In one or more embodiments, when the circuit package requests data from a destination node having a direct photonic link, the data is communicated using the memory or computing controller (e.g., memory / compute controller 914) of node 900.

[0075] In some embodiments, if the destination node where the data resides is not directly connected by the next FAU (or waveguide, or another type of single photonic link), the routing controller 920 (e.g., routing control block) of node 900 modifies the packet and outputs the modified packet to the next node in the path towards the destination node. In such a case, the process is repeated until the packet reaches the destination node, and the memory controller of the destination node can communicate with the data. For example, data in the form of an embedding table is provided to the requesting client computing device via an electrical port.

[0076] In some embodiments, node 900 also includes computing elements (e.g., CPU, GPU, MPU, etc.). For example, the communication with data can include a tensor engine, a neural computing engine, and / or another type of processor within the node that executes computations and / or converts data. In this example, the converted data can be stored again in the HBM of the memory portion (e.g., memory element) of connection region 912 or in the HBM of another node. Further, this process can continue until the AI workload is completed.

[0077] In various embodiments, the computing device requests data from the server's HGM and / or the converted data processed by the computing elements of the node. In these embodiments, the data is routed through the photonic interface of the node directly connected to the circuit package to which the computing device is connected. For example, the data is routed from the current node to a node that shares a circuit package and a photonic channel.

[0078] In some embodiments, this request is returned to the client ASIC by using the memory controller of the current node to obtain data from the HBM and forming a packet in the message router that includes the routing information along with the data indicating the destination location. In these embodiments, the digital packet is converted into an optical signal and transmitted to the next node. When routed to the destination node, the result can be transmitted along the photonic connection between the client computing device and the edge of the memory fabric (e.g., via a fiber and two FAUs). When the optical signal arrives, the message router within the die can convert the result into a digital packet usable by the computing device as described above.

[0079] In various embodiments, node 900 includes a message router 928 that includes an interface having a bidirectional photonic channel (not shown) via optical port 930. In one or more embodiments, a message including packet data arrives via a photonic channel of the PIC and is received at an optical-to-electrical (OE) interface between the PIC and message router 928. In various embodiments, the OE interface is implemented using a photodetector (e.g., a photodiode) of the PIC that converts an optical signal to an electrical signal, as described above. For example, this occurs in connection with using the associated electronics circuitry of message router 928, which may include a transimpedance amplifier (TIA), an optional gain control that normalizes the signal level, and / or a slicer that extracts the bitstream. Further, the message may be buffered in electronic form in a register such as FIFO register 932.

[0080] In one or more embodiments, the routing controller 920 (e.g., a routing control block) of node 900 includes circuitry for examining an incoming message. For example, the routing controller 920 identifies an address included in the message header (or message payload) and determines the port and / or destination node to which the message should be routed. As will be explained, in some examples, the message router 928 determines that the destination of the message is the memory 922 of node 900 (e.g., a memory element within a memory connection area). In such a case, the message is routed to the electrical port 926.

[0081] In other examples, the message router 928 determines that the destination of the message is another node within the memory fabric. In such cases, the message is routed to its destination node via the EO interface between the message router 928 and the PIC, where the message is converted to the optical domain for transmission over another photonic channel. In various embodiments, the EO interface is implemented using an optical modulator within the PIC in combination with a related driver circuit (e.g., a modulator driver) of the message router 928. Some examples of applicable modulator technologies include electro-absorption modulators (EAMs), Mach-Zehnder modulators, ring modulators, and quantum-confined Stark effect EAMs (QCCE EAMs).

[0082] FIG. 10 provides further details regarding the use of a memory fabric according to one or more embodiments. In particular, FIG. 10 is an exemplary flowchart showing how data moves within the memory fabric. For ease of explanation, FIG. 10 is described as a series of operations or actions 1000.

[0083] As shown in the figure, the series of actions 1000 includes an action 1010 of receiving a request at the die. In particular, action 1010 can include receiving a request within the die for an operation at the destination node of the memory fabric or for a memory controller. For example, the request here is a message request and / or an electrical request provided from an arithmetic element electrically interconnected to a circuit package including the die to a node of the memory fabric. In one embodiment, the die receives a message request from the arithmetic element requesting access to a memory controller or an arithmetic controller associated with the photonic interface.

[0084] Also, as shown in the figure, a series of operations 1000 includes an operation 1020 of forming a packet including request and routing information. In some implementations, a die of a circuit package connected to a connection area via an electrical connection of an interposer forms a digital packet related to the connection area.

[0085] Furthermore, a series of operations 1000 includes an operation 1030 of optically transmitting the packet to an interface of the memory fabric as a modulated electromagnetic wave. For example, operation 1030 may include optically transmitting the packet from a first optical interface of the die to a second optical interface of a node of the memory fabric, and the first and second interfaces are connected via an optical fiber, a waveguide, a combination of an optical fiber and a waveguide, an intra-chip link or an inter-chip link, other suitable optical connections and / or optical paths, or a combination thereof. For example, the packet is imposed on an optical carrier signal by a photonic transceiver of the circuit package and transmitted to a port of a node of the memory fabric connected to the circuit package. In one embodiment, the transmitting unit is partially within the die and partially within the interposer to optically transmit the digital packet to the photonic interface through a fiber array unit (FAU).

[0086] A series of operations 1000 also includes an operation 1040 of converting the packet into a digital format at an electrical port of the node. For example, the node receives the packet and reconverts the packet from an optical signal to an electrical format at a photonic transceiver of the node. In some cases, the routing controller transmits a modified digital output to an adjacent node of the memory fabric by converting the digital output into an optical signal and transmitting the optical signal to the adjacent node via a photonic interface of the memory fabric. For example, in various embodiments, the receiving unit is partially within the die and partially within the interposer to receive an optical signal from the FAU and supply the optical signal to an electrical area of the die in digital form.

[0087] Furthermore, the series of operations 1000 also includes an operation 1050 of determining whether the current node is the destination node. For example, the routing controller of the current node determines whether the current node is the destination of the request. As shown in the figure, in the case of "Yes", the series of operations 1000 includes an operation 1060 of communicating with the memory or arithmetic controller of the node. For example, using the electrical port of the node, access is made to the memory or interface controller associated with the memory or arithmetic resources coupled to the node (depending on the nature of the initial request).

[0088] If the operation 1050 determines that the current node is not the destination node (i.e., "No"), the series of operations 1000 includes an operation 1070 of modifying the packet. For example, the routing controller modifies the packet (e.g., by decrementing or changing the value of the routing information). Furthermore, the series of operations 1000 also includes an operation 1080 of optically transmitting the packet to the next node. For example, the electrical port transmits the modified packet to the optical transceiver, converts it into an optical signal, and transmits it to the next node within the memory fabric. For example, the modified packet is transmitted along the photonic link within the memory fabric connecting the current node and the next node (along the path to the destination node). Furthermore, this operation 1050 is repeated until the destination node is reached.

[0089] Next, a further discussion regarding a method, apparatus, and system for thermal control of an optical component (e.g., a thermal control system) is provided.

[0090] As further described below, the present disclosure includes a thermal control system including one or more embodiments, the thermal control system including a semiconductor having an optical layer laminated with an electrical layer, the semiconductor being divided into an electrical dedicated region and an optoelectrical region. Further, the thermal control system includes one or more nodes in the optoelectrical region, each of the nodes being present in the optical layer and the electrical layer. In some embodiments, a first portion of each node is present in the optical layer and has a modulator or a heat generating element present in the electrical layer that radiates heat toward the optical layer. The thermal control system also includes a temperature sensing region in a second portion of each node, the temperature sensing region having a temperature sensor for sending a heat signal to the electrical dedicated region, the heat signal being associated with the current temperature of at least one modulator. Further, the thermal control system includes a controller in the electrical dedicated region having electrical interconnections to each node for receiving the heat signal from the temperature sensor and transmitting a new voltage signal to the optoelectrical region based on the heat signal.

[0091] In some embodiments, the present disclosure includes a system-in-package (SIP) including a photonic integrated circuit (PIC), an electronic integrated circuit (EIC) having an electrical connection to the PIC, nodes where a first portion of the node is present in the EIC and a second portion of the node is present in the PIC, a plurality of heat generating elements provided in the first portion of the node that radiate heat (cause a heat change) toward the second portion of the node, a plurality of modulators provided in the second portion of the node, and a temperature sensing region provided in the second portion of the node for sending the current temperature to the controller. In some examples, the controller transmits a first signal to each of the modulators based on the current temperature.

[0092] In one or more embodiments, the present disclosure includes a method for controlling thermal variables associated with a plurality of optical components. For example, the method includes applying a first signal to an anode of each of the plurality of optical components and applying a second signal to a cathode of each of the plurality of optical components. Further, the method includes detecting a temperature of a region associated with the plurality of optical components and receiving a current temperature associated with the region. The method also includes determining when to initiate thermal control for the plurality of optical components using the current temperature.

[0093] In various embodiments, when a first optical component of the optical components is an inter-chip modulator, the method includes obtaining a first voltage and sending the first voltage to the anode of the inter-chip modulator. In an alternative embodiment, when a second optical component of the optical components is an intra-chip modulator, the method includes obtaining a second voltage and sending the second voltage to the anode of the intra-chip modulator, where the second voltage has a value different from the first voltage.

[0094] As further shown in the figures, FIG. 11A shows some of the elements and features of a system-in-package (SIP1102) that provides a suitable environment for obtaining benefits from various embodiments. For ease of reference, FIG. 11A may be referred to as a multi-processor system or SIP1102, although various parts, elements, and features of SIP1102 are not explicitly shown in FIG. 11A.

[0095] As shown in FIG. 11A, the SIP 1102 includes 16 nodes 1104 arranged in a 4×4 two-dimensional grid. Each node 1104 includes a heat generating element 1175 that generates heat 1180. Although a 4x4 grid is shown in FIG. 11A, the number and arrangement of the nodes 1104, as well as the type of heat generating elements 1175 included, may vary in different embodiments of the SIP 1102. Further, the SIP 1102 includes a laser light source (not shown), a photonic integrated circuit (PIC 1192), and an ASIC 1188 (e.g., a mixed signal IC). In this specification, the ASIC is interchangeably referred to as an electronic integrated circuit (EIC).

[0096] In various embodiments, the laser light source may be implemented on the SIP 1102 or externally. When implemented on the SIP 1102, two alternative embodiments may include an interposer that includes a plurality of lasers that can be co-packaged with the PIC 1192 and edge-coupled, and directly integrating the lasers into the PIC 1192 using hybrid integration or heterogeneous integration. In heterogeneous integration, the lasers can be directly implemented on a silicon photonic substrate, enabling lasers of different materials such as InP (indium phosphide) and lasers of architectures such as quantum dot lasers. The lasers in the hybrid assembly in the PIC 1192 can precisely attach III-V semiconductors and other materials to the PIC 1192 and couple them to the waveguides implemented in the PIC 1192. When implemented externally, the connection to the SIP 1102 is made by optical coupling, which may be a grating coupler and fiber or an edge coupler.

[0097] Furthermore, although not shown explicitly in FIG. 11A, SIP 1102 includes optical links and connections for one or more fiber connections. The fiber connections can be made by several means. For example, a fiber array unit is placed on a grating coupler (e.g., the first fiber array unit 1132a and the second fiber array unit 1132b shown in FIG. 11B), or an edge coupler provides the connection. Further, in many embodiments, SIP 1102 functions as a network-on-chip (NOC), more particularly, a hybrid electronic-photonic network-on-chip (EP-NOC).

[0098] FIG. 11B shows a side view of SIP 1102 and further shows an assembly form of an embodiment using the grating coupler and the fiber array unit described later. Note that FIG. 11A generally shows a part of the ASIC 1188 and the PIC 1192 used in SIP 1102, but the optical coupler and the laser light source are omitted from FIG. 11A (FIG. 11B shows the omitted part of SIP 1102).

[0099] In various embodiments, PIC 1192 provides a photonic network, among other things, for interconnecting some of the electronic elements of ASIC 1188 (while some other electronic elements of ASIC 1188 are electrically interconnected). As shown in FIG. 11B, the electronic elements of ASIC 1188 include a heat generating element 1175 that emits heat 1180. The heat 1180 can be radiated through PIC 1192, as a result of which the thermal characteristics within PIC 1192 change. In various embodiments, this occurs when ASIC 1188 is executing an arithmetic process, or otherwise operating under load, performing an operation, and / or otherwise operating as intended.

[0100] Often, heat 1180 affects the performance of the optical components within PIC1192. For example, the optical components of PIC1192 are sensitive to temperature changes and may affect their operating characteristics. Further, the optical components of PIC1192 are directly coupled to ASIC1188 in a die - to - die fashion without using an interposer or having another means of dissipating heat far away.

[0101] Accordingly, in the present embodiment, the heat - generating elements 1175 can be stacked while minimizing the distance or spacing (typically in microns) between the optical components. The advantages of the die - to - die connection of SIP1102 include bearing the additional heat generation to the optical components and shortening the latency. This creates an exemplary environment suitable for various embodiments such that thermal control of the optical components of PIC1192 is beneficial to maximize and / or optimize the performance of SIP1102. Further details regarding a thermally stable optical modulator (e.g., electro - absorption modulator) that operates efficiently over a temperature range are described below in connection with FIGS. 18A, 18B, and 19.

[0102] As shown, PIC1192 includes a first fiber array unit 1132a that transmits and receives optical data from a first optical fiber 1133a, and a second fiber array unit 1132b that also transmits and receives optical data from a second optical fiber 1133b. For example, the first optical fiber 1133a is connected to a first node, and the second optical fiber 1133b is connected to a second node.

[0103] According to various embodiments, the heat - generating elements 1175 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a memory unit, a memory controller, a message router, a tensor engine, a digital neural network (DNN), a field - programmable gate array (FPGA), and a generalized processing element. In some embodiments, the semiconductor may include an optical layer laminated with an electrical layer.

[0104] In many cases, both electrical signal routing and optical signal routing are used. As will be described later, the signal routing task is distributed in different ways between electrical (or electronic) paths and photonic paths. For example, in the present disclosure, a plurality of processors are interconnected (e.g., interconnected between chips or between SIPs) to realize a single system called an accelerator or a multiprocessor system. The photonic networks within the plurality of processors, together with optical connections on a printed circuit board (PCB), laser light sources, passive optical components, and external optical fibers that can be utilized in various combinations and configurations with other photonic elements, form the photonic fabric of the accelerator and interconnect the plurality of processors.

[0105] In addition to FIGS. 11A and 11B, FIG. 12 includes exemplary nodes of heat generating elements that can be used in a photonic fabric according to one or more embodiments disclosed in the present disclosure. As shown, FIG. 12 includes many of the components introduced above, such as node 1104 of SIP1102, PIC1192, heat generating element 1175, ASIC1188, and corresponding components. Further description of the components of ASIC1188 will be provided below.

[0106] As shown in FIG. 12, node 1104 of FIG. 12 includes DNN1106. For example, DNN1106 is present within ASIC1188 and is implemented in electronic form. In some embodiments, DNN1106 executes a convolution function or a dot product function as requested by the neural network of the accelerator, such as part of the inference operations executed by the accelerator. The multiprocessor system of SIP1102 including DNN1106 is a configuration suitable for various embodiments and is used for illustrative purposes but is not essential. In fact, various embodiments are suitable for various environments including, for example, those configured for general computing and including optical components closely coupled to the heat generating element and / or the EP-NOC.

[0107] As further shown in FIG. 12 (and FIG. 11A), node 1104 includes a tensor engine 1108, a message router 1110, a level 1 SRAM (L1SRAM 1112), and a level 2 SRAM (L2SRAM 1114). In various embodiments, L1SRAM 1112 functions as scratch pad memory for each of nodes 1104, while L2SRAM 1114 functions as primary memory for each of nodes 1104 and can store the weights of the machine learning model in physical proximity to DNN 1106 and tensor engine 1108. L2SRAM 1114 can also store intermediate results that may be required to execute the machine learning model. In one embodiment, L1SRAM 1112 is optional. In certain embodiments, the weights are used in each layer of the neural network within each SIP 1102. This may include performing inference operations. Each layer of the neural network can be implemented by some of the nodes 1104 of SIP 1102, and each of nodes 1104 is composed of one or more neural nodes or neurons.

[0108] During operation, the components of ASIC 1188 generate heat when the neural network processes data and / or executes more computationally intensive tasks. To that end, DNN 1106, tensor engine 1108, message router 1110, L1SRAM 1112, and L2SRAM 1114 are referred to as heat generating elements 1175. These heat generating elements 1175 can be configured in any number of manners suitable for ASIC 1188, which will generate heat during normal operation whether it is an AI accelerator or a general-purpose computer.

[0109] Returning to FIG. 11A, SIP 1102 includes optional elements such as bus interface 1122, CPU / GPU 1124, and memory controller 1126. Bus interface 1122 is, for example, a PCIE (Peripheral Component Interconnect Express) interface. CPU / GPU 1124 can be an Advanced RISC Machine (ARM) core, an image processor, or other processing elements. The external memory controller can support DRAM, NVRAM, SRAM, or other types of memory.

[0110] In various embodiments, bus interface 1122 enables an electrical interconnection between SIP 1102 and external components. In particular, the weights stored in L2SRAM 1114 are received from external components such as dynamic random access memory (DRAM) via bus interface 1122. CPU / GPU 1124 can interface with a memory device (not shown) that may be external to SIP 1102 and can process image data or perform other arithmetic tasks. The memory controller can communicate with high bandwidth memory (HBM 1189, for example shown in FIG. 11B), which may be external to SIP 1102 or integrated into SIP 1102. Other forms of memory, such as non-volatile memory, can also be attached in a similar manner using the corresponding memory controller within the block.

[0111] In one or more embodiments, the thermal controller 1128 includes one or more control circuits having an electrical connection to the PIC 1192 to take one or more actions and / or send one or more signals to the PIC 1192. This can, for example, respond to thermal characteristics and / or thermal changes in the PIC 1192, and the signals that the thermal controller 1128 can send are configured to change the operating characteristics of one or more optical components of the PIC 1192 and / or attenuate thermal changes occurring in the PIC 1192. This typically occurs when the PIC 1192 requires some action to keep the optical components operating in a more efficient and / or enhanced manner and there is a change in the thermal characteristics within the PIC 1192.

[0112] Returning to FIG. 12, in one or more embodiments, a message containing packet data arrives over a photonic network located on the PIC 1192 and is received at the optical / electrical interface 1134. In some embodiments, the optical / electrical interface 1134 is a photodiode or related circuitry, at least a portion of which is present in the ASIC 1188. In various embodiments, the message is buffered in electronic form in a register such as the FIFO register 1136 (“first in, first out” register). Further, the address contained in the message header is examined by the message router 1110, and the message router 1110 (e.g., an electronic message router) determines to which port and to which destination the message should be routed. For example, the message is routed to the destination node via the electrical / optical interface 1138, which can be a driver for an optical component (not shown).

[0113] In the current example, the optical modulator (not shown) is in proximity but is generally laminated either below or above the driver in the electrical / optical interface 1138. For example, the lamination distance between the optical modulator and the driver in the electrical / optical interface 1138 is measured in microns.

[0114] In various embodiments, due to the proximity of the coupling between the optical modulator and the driver in the electro - optical interface 1138, and due to the heat generated by the heat - generating element 1175, radiation occurs that changes the thermal environment of the optical components within the PIC 1192.

[0115] With respect to FIG. 12, the optical components are not visible because they are hidden below the optical / electrical interface 1134 and the electro - optical interface 1138 within the ASIC 1188 and / or are stacked below. For example, a portion of the optical components stacked below the electro - optical interface 1138 includes various different optical modulators. Examples of applicable modulator technologies include electro - absorption modulators (EAMs) including quantum - confined stark effect (QCSE) EAMs, or other modulators having optical absorption characteristics that change based on the thermal characteristics of the operating environment.

[0116] FIG. 13A shows a cross - sectional view, and FIG. 13B shows a top view of a portion of the SIP 1102 that can be used to thermally control one or more optical components according to various embodiments. Referring to FIG. 13A, the ASIC 1188 is shown to be located on top of or stacked on the PIC 1192. Examples of nodes 1304a, 1304b, 1304c, and 1304d of the ASIC 1188 are shown together with modulator drivers 1341a, 1341b, and 1341c located at nodes 1304a, 1304b, and 1304c (e.g., ASIC nodes), respectively. Trans - impedance amplifiers (TIAs) 1342b, 1342c, 1342d are located at nodes 1304b, 1304c, 1304d (e.g., ASIC nodes), respectively. Optical modulators 1345a, 1345b, and 1345c fabricated within the PIC 1192 are located directly below respective instances of the modulator drivers 1341a, 1341b, and 1341c.

[0117] Also, within PIC1192, there are photodetectors (e.g., PD1346b, 1346c, and 1346d) located directly below each instance of TIA1342b, 1342c, and 1342d. Optical links such as waveguides 1343ab, 1343bc, and 1343cd provide optical paths within PIC1192 that are part of a photonic network for in-chip communication between nodes 1304a, 1304b, 1304c, and 1304d within SIP1102.

[0118] Furthermore, FIG. 13A includes optical couplings that connect between nodes. The optical couplings can be implemented using edge coupling or, as shown in FIG. 13A, using an optical fiber 1133 that is located on the fiber array unit 1132 (FAU) and PIC1192 and provides an optical input to the grating coupler 1340 within PIC1192. The optical fiber 1133 may be connected to an off-chip laser light source and / or the FAU of another processor that provides an optical input to PIC1192.

[0119] Each of optical modulators 1345a, 1345b, and 1345c can be of a first optical component type 1395 or a second optical component type 1396 of an optical modulator, where the type depends on its position within the system topology. For example, the first optical component type (e.g., related to optical modulators 1345b and 1345c) has internal connections within PIC1192 and is routed by waveguides within PIC1192 (e.g., in-chip modulation). As shown, optical modulators 1345b and 1345c are of the first optical component type 1395. Furthermore, the second optical component type 1396 of the optical modulator is an edge or corner optical modulator that couples at least partially to the fiber array unit 1132 (e.g., inter-chip modulation). As shown, optical modulator 1345a has the second optical component type 1396.

[0120] In many embodiments, due to differences in the hardware used to couple the first and second optical modulator types, the requirements regarding heat for optimally operating the two optical modulator types will be different. For example, an inter-chip modulator receives and / or absorbs more light than an intra-chip modulator and operates at a higher temperature during normal operation. This is due in part to the fact that since the laser light is multiplexed together in the fiber array unit 1132, the inter-chip modulator (e.g., optical modulator 1345a) may receive and / or absorb more light than the intra-chip modulators (e.g., optical modulators 1345b and 1345c). As a result, the inter-chip controller 1300 and the intra-chip controller 1305 may be used to operate in the ASIC 1188 with respect to two different types of optical modulators (e.g., the first optical component type 1395 and the second optical component type 1396) present in the SIP 1102.

[0121] In one or more embodiments, the laser light source may be on-chip as described above. For example, the laser light need not be supplied through the fiber array unit 1132. In various embodiments, optical links such as the waveguide 1344 and additional waveguides not visible in the cross-sectional view of FIG. 13A supply the light received by the grating coupler 1340 to the optical modulators 1345a, 1345b, and 1345c located in the PIC 1192. The connections between the grating coupler 1340 and the other connections of the optical modulators 1345b, 1345c are not explicitly shown in FIG. 13A, but since FIG. 13A is a partial cross-sectional view of FIG. 13B, these connections are shown in FIG. 13B.

[0122] As shown in FIG. 13B, the waveguide 1344 conveys the laser light source from the fiber array unit 1132 to the splitter 1382a via an optional splitter 1347 (the splitter 1382a is not shown in FIG. 13A). From the splitter 1382a within the node 1304a, one optical path is supplied to the optical modulator 1345a, and another optical path is supplied to the splitter 1382b within the node 1304b through the continuation of the waveguide 1344 (the splitter 1382b is not shown in FIG. 13A). From the splitter 1382b within the node 1304b, one optical path is supplied to the optical modulator 1345b, and another optical path is supplied to the optical modulator 1345c within the node 1304c through the continuation of the waveguide 1344.

[0123] FIG. 13B further shows a top view of the waveguides 1343ab connecting the optical modulator 1345a to the PD 1346b, the waveguides 1343bc connecting the optical modulator 1345b to the PD 1346c, and the waveguides 1343cd connecting the optical modulator 1345c to the PD 1346d. The top view of FIG. 13B corresponds to the cross-sectional view of FIG. 13A. In addition to what is shown in the cross-sectional view of FIG. 13A, FIG. 13B also shows a top view of other optical paths within the PIC 1192 as an additional example of the optical connections between various nodes within the SIP 1102.

[0124] In various embodiments, the ASIC 1188 is electrically coupled to the PIC 1192 and includes a thermal controller 1128 as shown in FIGS. 13A and 13B. For example, the thermal controller 1128 includes an inter-chip controller 1300 (e.g., an inter-chip thermal controller), an intra-chip controller 1305 (e.g., an intra-chip thermal controller), a DC bias signal 1310, and an AC swing signal 1330. In various embodiments, the DC bias signal 1310 has an electrical connection 1370 to the anode of one of the optical modulators.

[0125] In one or more embodiments, the electrical connection 1370 is implemented using a through-silicon via (TSV), a wire, or any other suitable electrical connection capable of transmitting a voltage signal to the anode of one of the optical modulators. In some embodiments, the AC swing signal 1330 has an electrical connection 1375 to the cathode of one of the optical modulators. Further, in various embodiments, the electrical connection 1375 is implemented using a TSV, a wire, or any other suitable electrical connection capable of transmitting a voltage signal to the cathode of one of the optical modulators.

[0126] In many embodiments, for node-to-node communication between a first node and a second node, the streaming of activation values from the first node in the first SIP to the second node in the second SIP is performed using a photonic network in the PIC1192 by using optical components including modulators and photodetectors, where the modulators and photodetectors are located directly below their respective modulator drivers and TIAs on the ASIC1188. In many cases, the optical modulators and photodetectors are connected by an optical path on the PIC1192, such as a waveguide. Thus, in many cases, most or all of the node-to-node communication is not performed electronically in the ASIC1188 but is performed optically by the photonic network provided by the PIC1192.

[0127] Further, in various embodiments, on-chip optical communication is generally performed using light of a single wavelength. However, in some embodiments, on-chip optical communication is performed using multiple wavelengths.

[0128] FIG. 14 is a partial cross-sectional view of an exemplary SIP for thermally controlling an optical component according to an embodiment disclosed herein. FIG. 14 shows an exemplary node having the components described above. For example, FIG. 14 includes an ASIC 1188 having nodes 1304a, 1304b, and 1304c, and modulator drivers 1341a, 1341b, and 1341c are located at their respective nodes. As shown, optical modulators 1345a, 1345b, and 1345c are located directly below their respective instances of modulator drivers 1341a, 1341b, and 1341c.

[0129] Also, as shown, temperature sensors 1400, 1401, and 1402 are associated with optical modulators 1345a, 1345b, and 1345c. For example, each of temperature sensors 1400, 1401, and 1402 can monitor the temperature of their respective instances of optical modulators 1345a, 1345b, and 1345c and are arranged within PIC 1192 to be able to do so. In some embodiments, optical modulators 1345a, 1345b, and 1345c generally have a wide operating temperature range (e.g., a difference of several degrees Celsius has a minimal impact on the performance of optical modulators 1345a, 1345b, and 1345c).

[0130] In some embodiments, optical modulators 1345a, 1345b, and 1345c are manufactured to operate when the ambient temperature is at the specification's maximum temperature and / or when the ASIC 1188 is operating at full throttle up to its maximum power (e.g., when all of nodes 1304a, 1304b, and 1304c are being executed at maximum load). When the operation of the ASIC 1188 decreases, the ambient temperature drops, and optical modulators 1345a, 1345b, and 1345c may not operate optimally. In this scenario, it may be possible to return optical modulators 1345a, 1345b, and / or 1345c to an optimal performance state by taking measures to correct the situation with respect to their thermal environment.

[0131] During operation, ASIC 1188 optically encodes bits and transmits them optically to the destination using optical modulators 1345a, 1345b, and 1345c. As an example, the following scheme is implemented to control the operation of optical modulators 1345a, 1345b, and 1345c to enable consistent performance regardless of the thermal effects of ASIC 1188. Illustratively, an AC swing signal (such as a ±0.9 volt swing) from AC swing signal 1330 is applied to optical modulators 1345a, 1345b, and 1345c at a first terminal. A DC bias signal from DC bias signal 1310 is applied to a second terminal of optical modulators 1345a, 1345b, 1345c.

[0132] In some embodiments, the application of a plus or minus 0.9 voltage swing signal (or other swing signal depending on how the optical modulator is constructed) from AC swing signal 1430, when combined with a default minus 1 volt DC signal (e.g., a minus DC bias voltage) sent from DC bias signal 1310, results in optical modulators 1345a, 1345b, and 1345c having a swing between 0.1 and -1.9 volts. As the system operates, thermal energy may be transferred from ASIC 1188 to PIC 1192. When the operation of ASIC 1188 decreases, a portion of ASIC 1188 idles, and / or the load on ASIC 1188 changes during the execution of a process, the temperature associated with optical modulators 1345a, 1345b, and 1345c also changes. Temperature sensors 1400, 1401, and 1402 continuously monitor each instance of optical modulators 1345a, 1345b, and 1345c. The outputs of temperature sensors 1400, 1401, 1402 are sent to controller 1420.

[0133] In various embodiments, the controller 1420 is a software, hardware, or firmware module (or any combination thereof) that implements logic capable of determining when thermal variables, such as heat, deviate from an optimal range. For example, the controller 1420 can utilize a look-up table, access a database, use an activation function to compute values, or use some other means in the bias determination module 1440 to determine when and how much voltage to apply to the optical modulators 1345a, 1345b, and 1345c via the DC bias signal 1310. As the temperature within the PIC 1192 changes, the temperature sensors 1400, 1401, and 1402 continue to send relevant signals to the controller 1420. When the thermal thresholds deviate sufficiently and / or the thermal state of the optical modulators 1345a, 1345b, and 1345c requires intervention, the controller 1420 sends an input to the DC bias signal 1410 (which can cause the DC bias signal 1410 to send a bias signal different from the default -1 volt signal, which corresponds to a different value). In response, the DC bias signal 1410 outputs a new bias signal and provides it as an input to the optical modulators 1345a, 1345b, and 1345c, thereby changing their performance.

[0134] In one or more embodiments, the new DC bias signal is obtained by the bias determination module 1440 by using a table, a database, or another suitable data structure. In these embodiments, when using a table, it can have multiple rows and columns, with at least a first column in each row representing temperature and a corresponding second column representing related voltage values or voltage values. The bias determination module 1440 can find, select, or otherwise determine the row in the table corresponding to the current temperature, and select the corresponding new DC bias voltage signal in the related column of that row, and access or otherwise use the new DC bias voltage signal. For example, the bias determination module 1440 uses the current temperature received from the temperature sensors 1400, 1401, and 1402 and compares the current temperature with each row in the table until a match is found. Then, a new voltage can be obtained by accessing the column related to the selected row having the new voltage value. This can be the new voltage signal, and this new signal can be transmitted to the optoelectronic region.

[0135] In some embodiments, the bias determination module 1440 is used to apply the current temperature to an activation function that can perform multiplication and / or multiply the current temperature using the activation function to obtain the current voltage required for use as the new DC bias signal. For example, if the new DC bias voltage signal obtained by the bias determination module 1440 is -2 volts, the new swing signals of the optical modulators 1345a, 1345b, and 1345c will be between -2.9 volts and -1.1 volts. It should be noted that the value of the DC bias signal transmitted from the DC bias signal 1310 is for illustrative purposes only.

[0136] Furthermore, the DC bias signal 1410 can vary in different embodiments depending on system properties, how the optical components are configured, the type of load expected to be utilized by the ASIC 1188, and the like. For example, the amount of heat generated by the ASIC 1188, the thermal environment of the computing device including the optical components, the type of application using the computing system, the type of optical components, and other factors determine the value that the DC bias signal 1410 should transmit, and the type of activation function, database, or look-up table utilized by the bias determination module 1440, as well as the actual values contained therein.

[0137] Generally, as the temperature cools, the bias signal sent by the thermal signal block can be applied to cause the optical modulators 1345a, 1345b, and 1345c to absorb more of the light sent via the optical fiber 1133 or carried by the waveguide. Similarly, as the temperature rises, the bias signal sent by the thermal signal block can be changed to cause the optical modulators 1345a, 1345b, and 1345c to absorb less of the light sent via the optical fiber 1133 or carried by the waveguide. In this way, DC voltage control can be used to compensate for temperature drift. Thus, the temperature range of the optical modulators 1345a, 1345b, and 1345c can be extended by changing the DC bias via the DC bias signal 1410 when the controller 1420 takes action regarding the thermal state and / or when otherwise providing an input to the optical modulators 1345a, 1345b, and 1345c.

[0138] FIG. 15 shows another top view of an exemplary SIP (e.g., SIP 1102) having the function of thermally controlling an optical component according to various embodiments. In the configuration of FIG. 15, the PIC 1192 is stacked with an ASIC 1188 having an electrical-only portion 1570 and an optoelectronic portion 1575. The PIC 1192 may be divided into an electrical-only region and an optoelectronic region. The electrical-only portion 1570 of the ASIC 1188 generally corresponds to a processing region (EDs that are stacked with, adjacent to, and / or directly below the heat-generating elements) that does not depend on the photonic elements within the PIC 1192. Therefore, the electrical-only portion 1570 does not need to have thermal control in this region.

[0139] In various embodiments, the electrical-only portion 1570 includes an AC swing signal 1530, a controller 1520, and a DC bias signal 1510. In some embodiments, these blocks (e.g., the DC bias signal 1510, the controller 1520, and the AC swing signal 1530) use a CPU or other suitable processor and / or memory within this region (not shown). Further, the controller 1520 can be a single unit or multiple controllers or control circuits, and includes, for example, the function of controlling a first optical component type 1395 of an optical modulator using an in-chip controller 1305 and / or controlling a second optical component type 1396 of an optical modulator using an inter-chip controller 1300.

[0140] As shown in FIG. 15, the first optical component type 1395 of the optical modulator includes only optical connections to other adjacent nodes within the node 1104 and is called an in-chip optical component as described above. Also, as described above, the second optical component type 1396 of the optical modulator includes, for example, an optical connection to the edge of the node 1104 to other chips and / or nodes via the FAU. In various examples, both the first optical component type 1395 and the second optical component type 1396 of the optical modulator are independently controlled by the same controller or different controllers (e.g., the controller 1520).

[0141] Often, since the hardware for powering the first optical component type 1395 and the second optical component type 1396 of the optical modulator is different, the changes to the DC bias signal 1510 caused by the inter-chip controller 1300 or the intra-chip controller 1305 are typically different even when the thermal conditions are the same in the associated temperature sensing region. In the current example, each node has 16 EAMs, 8 of which are of the first optical component type 1395 and 8 of which are of the second optical component type 1396. Also, the electrical dedicated part 1570 includes a communication coupling (either electrical or optical or both) to the two optical modulator types in the optoelectronic part 1575 of the ASIC 1188. In the current embodiment, each ASIC 1188 has, although not essential, 1,256 EAMs. In other embodiments, other configurations may be used.

[0142] Each node also includes a temperature sensing region 1580. As shown, the PIC 1192 has 16 instances of the temperature sensing region 1580, each including the first optical component type 1395 and the second optical component type 1396 of the optical modulator. Typically, since the spacing between the first optical component type 1395 and the second optical component type 1396 of the optical modulator is measured in millimeters or fractions of a millimeter, the temperature difference between the individual ones of the optical modulators within each node does not vary by a large amount.

[0143] In some embodiments, instead of high-resolution temperature sensors, rather than sensing the temperature at each of the optical modulators, a bias signal (a new bias for the inter-chip optical modulators of the first optical component type 1395 and a new bias for the intra-chip optical modulators of the second optical component type 1396) is adjusted for the 16 optical modulators at a time at each node.

[0144] In some embodiments, and where applicable as shown in FIG. 15, each of the optical components can have an associated temperature sensor. Further, the temperature sensing regions can be placed on the nodes by advantageously utilizing the available real estate on the chip. As such, an instance of the temperature sensing region 1580 need not be at the center of the node and can be placed off-center depending on the other components of the node that are present there. As shown in FIG. 15, the temperature sensing region is off-center and thus not equidistant from the modulators at the four corners of the node 1104.

[0145] During operation, a default version of the AC swing signal 1530 is provided to each of the 1,256 optical modulators (e.g., of the first optical component type 1395 and the second optical component type 1396) on the PIC1192 at the cathode. In various embodiments, a default negative bias signal is also supplied by the DC bias signal 1510 to each of the 1,256 optical modulators at the anode. As a result, the default operation of all of the optical modulators 1 on the PIC1192 is obtained, enabling bits to be encoded and otherwise performing optical processing of data or packets in a typical manner.

[0146] Indeed, each of the 16 instances of the temperature sensing region 1580 has an associated temperature sensor placed within the region. Each of the temperature sensors transmits an output to the controller 1520 in the form of data representing the current temperature at a particular instance of the temperature sensing region 1580. Thus, the controller 1520 of the present embodiment periodically receives 16 signals regarding the current temperature at each instance of the temperature sensing region 1580.

[0147] In various embodiments, controller 1520 includes inter-chip controller 1300 and intra-chip controller 1305. For example, inter-chip controller 1300 is configured to control the thermal characteristics of the second optical component type 1396 of the optical modulator. In some examples, intra-chip controller 1305 is configured to control the thermal characteristics of the first optical component type 1395 of the optical modulator. For purposes of illustration, it is assumed that node 1104 transmits data from the temperature sensor in its temperature sensing region to controller 1520. Additionally, controller 1520 uses bias determination module 1540, which may optionally be coupled to database 1595 or other data store.

[0148] In some embodiments, bias determination module 1540 uses the current temperature received from temperature sensing region 1580 of node 1104 to determine whether the optical modulator (e.g., of the first optical component type 1395 and / or the second optical component type 1396) needs to have a bias signal modified to maximize its performance based on the current thermal conditions. Bias determination module 1540 can use database 1595 to access a table or other data structure that matches temperature to a new bias signal for each of the first and second types of optical modulators.

[0149] In some embodiments, any suitable function or linear transformation can be used if the product of the current temperature and the activation value results in a new bias value. Next, when a new bias value is obtained from bias determination module 1540, inter-chip controller 1300 sends the new voltage value to the anode of each of the optical modulators of the second optical component type 1396. Similarly, intra-chip controller 1305 sends the new voltage value to the anode of each of the optical modulators of the first optical component type 1395. This process is repeated so that SIP 1102 operates as intended.

[0150] Figure 16 is a flowchart showing the operation related to the thermal control of an optical component according to an embodiment. In operation 1600, an AC swing signal related to the optical component is applied to each first terminal of the optical components within the EP-NOC. In operation 1610, a default DC bias signal related to the optical component is applied to each second terminal of the optical components within the EP-NOC. In one embodiment, operations 1600 and 1610 include applying a high-speed AC signal to the cathode of each optical component and applying a default DC bias of a negative voltage to the anode of each optical component. As a result of operations 1600 and 1610 in the current example, when encoding bits based on the applied signals, the optical component will alternately change between 0.1 V and -1.9 V.

[0151] In operation 1620, the temperature is detected in the temperature detection region of the EP-NOC related to the optical component. This may include, for example, an EP-NOC having 16 nodes per chip and 16 optical components per node. In some embodiments, the temperature detection region is arranged in relation to the 16 optical components of each region, but it is not necessary to be arranged at the same distance from each optical component. In some embodiments, other configurations can be used. The temperature sensor can be any device suitable for this purpose, but since the temperature difference within a given node is minimized when the spacing between the optical modulators is relatively small, in some systems, the cost can be saved by reducing the accuracy of the temperature sensor.

[0152] In operation 1630, a signal related to the detected temperature is sent to the controller. In one embodiment, the controller can be implemented on a processor separate from the nodes of the photonic fabric, such as an ARM or other family of CPUs. This signal represents, for example, the current temperature of the temperature sensing region. In operation 1640, the controller determines whether thermal control is necessary at the node based on the data received from the temperature sensing region. For example, the controller determines the timing to initiate thermal control for the optical component. This may include, for example, using a database, data structure, lookup table, and / or a bias determination module that uses an activation function to determine whether the current temperature has a value assigned to a different DC bias voltage than the default DC bias voltage transmitted in operation 1610.

[0153] In operation 1650, if thermal control is necessary, in operation 1660, a new voltage is obtained based on the current operating temperature of the temperature sensing region. In operation 1670, the new voltage is sent to the second terminal of the optical component associated with the temperature sensing region. If thermal control is not required in operation 1650 or after the new voltage is sent in operation 1670, the process is repeated in operation 1620. The SIP continues to repeat these operations whenever there is a load on the ASIC within the SIP and / or the system is operating as intended.

[0154] Figure 17 is a flowchart showing operations related to thermal control of an optical modulator according to another embodiment. In operation 1700, an AC swing signal related to the EAM is applied to the cathode of each of the EAMs of one node, a part of the nodes, or all of the nodes within the EP-NOC. In operation 1705, a default DC bias signal related to the EAM is applied to the anode of each of the EAMs of one node, a part of the nodes, or all of the nodes within the EP-NOC.

[0155] In operation 1710, the temperature is detected in the temperature detection region of the EP-NOC associated with the node where the EAM exists. The temperature sensor can be any device suitable for this purpose, and various accuracies are possible. In operation 1715, a signal related to the detected temperature is sent to the controller. In one embodiment, the controller may be in the electrical dedicated part of the EP-NOC where the ASIC is stacked with the PIC but has no optical components interconnected within the electrical dedicated region, and thus does not require thermal control. The hybrid optoelectronic region is stacked on the part of the PIC having optical components from which the analog components of the ASIC can benefit from thermal control, and this electrical dedicated region may have an electrical interconnection to this hybrid optoelectronic region via the ASIC.

[0156] In operations 1720 and 1725, the controller determines whether thermal control is required at the associated node based on the data received from the temperature detection region. This may include, for example, a determination that adjustments should be made to the inter-chip EAM, the intra-chip EAM, or both. Usually, the inter-chip EAM and the intra-chip EAM have different hardware feeding their operations. For example, the inter-chip EAM may receive less-divided and higher-power light compared to the intra-chip EAM. Due to such differences, if it is determined that a signal should be sent, usually different thermal signals will be sent to the two types of optical components.

[0157] In operation 1730, the controller determines whether thermal-based adjustment is required for the inter-chip EAM. In that case, in operation 1735, a new voltage is obtained based on the current operating temperature in the temperature detection region and the new bias signal related thereto that needs to be added to the inter-chip EAM based on the current thermal conditions. In operation 1740, the new voltage is sent to the anode of the inter-chip EAM in the associated temperature detection region.

[0158] In operation 1730, or after operation 1740, if the inter-chip EAM does not require thermal adjustment, the controller determines, in operation 1745, whether the intra-chip EAM requires thermal-based adjustment. If necessary, in operation 1750, a new voltage is obtained based on the current operating temperature in the temperature sensing region and a new bias signal that needs to be added to the intra-chip EAM based on the current thermal conditions and related to the new bias signal.

[0159] In operation 1755, the new voltage is sent to the anode of the intra-chip EAM in the temperature sensing region to which it is related. Thereafter, or if the intra-chip EAM did not require temperature adjustment in operation 1745, the process is repeated in operation 1710. The SIP continues to repeat these operations whenever the ASIC within the SIP is loaded and / or whenever the system is operating as intended.

[0160] As described herein, the EP-NOC here includes a novel scheme for controlling the thermal characteristics of one or more optical modulators within the receiving unit of the EP-NOC. In fact, this document describes an EP-NOC that brings about a significant improvement in the performance of the receiving unit.

[0161] Next, further discussion is provided regarding an apparatus, system, and method for an electro-absorption modulator (EAM) that provides stable operation over a wide temperature range for the optical components of an arithmetic unit. As described above, the EAM is a semiconductor-based optical modulator and is often used to control a light source using a voltage. For example, the EAM uses a low voltage to modulate a laser beam. As previously mentioned, the EAM is based on the utilization of the Franz-Keldysh effect on changes in electrically induced optical absorption.

[0162] Incidentally, the heat-generating electronic elements within the ASIC exhibit significant variations in heat generation under different loads. The optical modulation elements within the PIC are designed to operate within a defined temperature range. Since the amount of heat generated by the electronic elements directly coupled to the optical modulation elements varies greatly, the impact of this variation is an important consideration when designing the optical components within the PIC to meet the requested operating parameters and be reliable under these conditions.

[0163] This becomes even more important in a photonic fabric environment where thousands of electronic elements are adjacent (e.g., within 50 microns) to the corresponding optical modulation elements. While implementing a direct coupling between the electronic elements and the optical modulation elements offers significant advantages in terms of computing speed and energy efficiency, the impact of various levels of heat on the PIC can also be a drawback.

[0164] In fact, the photonic fabric is designed to have optical modulation elements that can operate efficiently within a temperature range that matches the temperature range experienced when the ASIC is operating at or near its maximum load. Similarly, when operating at a lower load, the amount of heat generated by the ASIC that affects the PIC is smaller, and the temperature in the region where the optical modulation elements operate is lower. Therefore, it is important to have efficient optical modulation elements even under such low-temperature conditions.

[0165] Specifically, the materials and types of optical modulators used will affect the temperature conditions expected within the PIC. Also, the optical modulators will affect not only other characteristics of the system that can cause changes in the thermal operating environment of the optical modulation elements but also the temperature fluctuations indirectly generated from the idling ASIC. Therefore, the EAM described in this specification affects these factors and operates efficiently over a wide range of operating conditions.

[0166] In various embodiments, to achieve stable operation over a wide temperature range, the EAM is made of a bulk semiconductor material. For example, the EAM is made of one or more materials such as pure germanium or silicon (or alloys thereof), or various so-called III-V materials including primarily indium phosphide (InP) or gallium arsenide (GaAs) material systems.

[0167] One use case that utilizes a thermally stable optical modulation element is, as described above, to accommodate operation over a wide temperature range. Another use case involves situations with high optical modulation amplitude (OMA) output, in which case there is typically a narrower operating range but still thermally stable. An optical modulation element designed to operate over a wide temperature range typically operates over a range exceeding 30 degrees Celsius (although optical modulation elements with a narrower operating range are also possible). An optical modulation element designed for high OMA output generally operates over a range less than 30 degrees Celsius (although optical modulation elements with a wider operating range are also possible).

[0168] As described above, the present disclosure describes an EAM that operates over a wide temperature range. In some embodiments, the EAM is based on a quantum confinement architecture and achieves enhanced performance in that a higher OMA output is obtained from the EAM over a narrower temperature range. For example, an EAM based on the quantum confinement Stark effect (QCSE) achieves such results particularly when made from bulk semiconductor materials (e.g., alloys using germanium and silicon alloys, as well as III-V materials based on indium phosphide and gallium arsenide systems).

[0169] In various embodiments, the EAM disclosed herein utilizes a thermal control loop that applies a voltage (bias voltage) to the optical modulation element in response to the changing thermal state within the PIC. In this way, through voltage application, the optical modulation element operates as if the actual temperature of its region were lower and / or outside the normal temperature range of the optical modulation component (e.g., even without the provided voltage signal) and close to what it would experience at maximum load. Further, even if the temperature conditions exceed the operating range of the device, the temperature range of the optical modulation component is extended via the applied additional voltage.

[0170] In some embodiments, the thermally stable optical modulator operates over a temperature range greater than 30 degrees Celsius. For example, the thermally stable optical modulator is an EAM that is approximately 50 microns in size and operates at a data rate of 50 - 115 Gbps with a power of less than 1.0 volt. In these embodiments, the EAM enables direct silicon photonics packaging to a processor, ASIC, memory chip. Further, the EAM provides optical connectivity not only within the chip but also between chips. Additionally, in one or more embodiments, the EAM (i.e., the thermally stable optical modulator) operates stably while having a narrow (or fairly narrow) operating range, which can be further enhanced by the thermal control loop.

[0171] In various embodiments, the EAM (i.e., the thermally stable optical modulator) operates over a temperature range less than 30 degrees Celsius. For example, the EAM is based on a quantum confinement architecture as described above. In these examples, the higher optical OMA output from the EAM is used over a narrower temperature range (e.g., less than 30 degrees Celsius) to achieve enhanced performance. Further, as described above, in some of these embodiments, the EAM is made (e.g., composed) of a material selected from germanium, silicon, alloys of germanium, alloys of silicon, III - V materials based on InP, and / or III - V materials based on GaAs.

[0172] As mentioned above, in certain embodiments, an EAM (i.e., a thermally stable optical modulator) uses the quantum-confined Stark effect (QCSE) for changes in electrically induced optical absorption. In this way, the EAM outputs a higher optical modulation amplitude. For example, the EAM utilizes a QCSE modulator with a high OMA to achieve a wide or fairly wide operating range, which can be further enhanced by a thermal control loop.

[0173] Here, further details regarding the environment in which the EAM operates are provided. More specifically, the embodiments described herein include chip hardware that includes features and functions that provide one or more thermally stable optical modulation elements coupled to one or more electronic elements. In one or more embodiments, the hardware is a device that includes an electronic integrated circuit (EIC) and a photonic integrated circuit (PIC). The PIC may be directly coupled and stacked with the EIC.

[0174] As illustrated in the figures, FIG. 18A shows a side view of a system-in-package (SIP). As shown, FIG. 18A shows a SIP 1102 having a PIC 1192 coupled to an EIC that is part of the ASIC 1188. For example, the SIP 1102 is directly coupled and stacked with the EIC.

[0175] In various embodiments, the PIC 1192 is a silicon photonic IC. Further, FIG. 18A includes an HBM 1189 (high-bandwidth memory). As described above, the components of the ASIC 1188 generate heat when performing processing operations such as neural network processing and various other arithmetic tasks.

[0176] FIG. 18A also includes, as described above, a SIP 1102 having a first optical fiber 1133a, a first fiber array unit 1132a, a second optical fiber 1133b, and a second fiber array unit 1132b. For example, a fiber array unit (FAU) and its corresponding optical fiber are located on the PIC 1192 and provide an optical input to the PIC 1192. In various embodiments, the optical fiber is connected to an FAU of an off-chip laser light source (e.g., a light engine) and / or another processor that provides an optical input to the PIC 1192.

[0177] In the flow of these descriptions, the apparatus may further include a node with a router each having a transmission unit and a reception unit, where the transmission unit and the reception unit are partially present in the EIC and partially present in the PIC. In various embodiments, each transmission unit includes a thermally stable optical modulator (e.g., an EAM) in the portion present in the PIC. Data may be optically moved within the PIC via an optical carrier between one of the thermally stable optical modulators in the first node and one of the reception units in the second node.

[0178] As described above, in one or more embodiments, the thermally stable optical modulator is an EAM that operates in a temperature range less than 30 degrees Celsius. In this example, the thermally stable optical modulator may include a material selected from the group consisting of germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), and a III-V material based on gallium arsenide (GaAs) (e.g., may be composed of a material selected from the group). In one or more embodiments, the thermally stable optical modulator uses a quantum confinement Stark effect (QCSE) for changes in electrically induced optical absorption. Further, in various embodiments, the EAM (e.g., the thermally stable optical modulator) has an output with a high optical modulation amplitude.

[0179] Figure 18B is a more detailed side view of the SIP. As shown, Figure 18B includes a SIP 1102 having a first fiber array unit 1132a and coupled to an ASIC 1188. In various embodiments, the ASIC 1188 is a 5nm system-on-chip (SOC).

[0180] Further, Figure 18B shows a waveguide 1344 (e.g., a channel waveguide) as part of the SIP 1102. The waveguide 1344 includes a grating coupler attached to the first fiber array unit 1132a, a splitter tree 1852, and an EAM 1860 (electro-absorption modulator) having a contact 1862 with the ASIC 1188 via an attachment 1864. In various embodiments, this attachment is a pillar attachment such as a 50μm pillar. The waveguide 1344 also includes a photodiode 1854 attached to the ASIC 1188.

[0181] As shown, the ASIC 1188 includes an EAM driver 1866 electronically connected to the EAM 1860. Further, the ASIC 1188 includes a TIA 1856 (transimpedance amplifier) electronically connected to the photodiode 1854.

[0182] In various embodiments, in a design such as a photonic fabric, as shown in Figure 18B, the ASIC is directly coupled to the PIC. Figure 18B shows a particular configuration of the direct coupling between the electronic and photonic elements, but many other examples are possible. For example, a copper pillar attachment connects the EAM driver to the EAM and the photodiode to the TIA, but other embodiments for direct coupling (inter-chip packaging) can also be used.

[0183] In various embodiments, the EAM is an optical modulation element that allows light to pass between the cathode and the anode. Further, the EAM provides thermal stability above 30 degrees Celsius and enables direct packaging of the SIP with one or more processors of the ASIC and / or memory chip. In fact, the EAM provides optical connectivity both within and between chips. Further, the EAM may be about 50 microns in size and / or the EAM may operate at a data rate of 50 - 115 Gbps with a power of less than 1.0 volts (but up to 2.0 volts maximum).

[0184] FIG. 19 is another top view of a portion of a thermal control system for an optical component according to one or more embodiments disclosed in the present disclosure. FIG. 19 includes the components described so far, such as PIC 1192, ASIC 1188, optical modulators 1345a, 1345b, and 1345c, and nodes 1304a, 1304b, 1304c, and 1304c.

[0185] As described above, in various embodiments, nodes 1304a, 1304b, 1304c, and 1304c each include a router. Further, in many examples, each of the routers includes a transmission unit and a reception unit. For example, the transmission unit corresponds to modulator drivers 1341b and 1341c combined with optical modulators 1345b and 1345c (e.g., EAM). Also, the reception unit corresponds to TIAs 1342b and 1342c combined with PDs 1346b and 1346c. In fact, as shown in FIG. 19, the transmission unit and the reception unit are partially present in the EIC (e.g., ASIC 1188) and partially present in the PIC 1192.

[0186] Furthermore, as described above, in various embodiments, each of the transmission units includes a thermally stable optical modulator (i.e., EAM) in a portion existing within the PIC1192. Further, data is optically moved within the PIC1192 via an optical carrier (e.g., waveguide 1344) between a thermally stable optical modulator (e.g., the first EAM or optical modulator 1345a) within the first node (e.g., node 1304a) and one of the receiving units (e.g., TIA1342b and PD1346b) within the second node (e.g., node 1304b).

[0187] FIG. 20 is a flowchart showing data moving within a digital circuit in a photonic fabric according to one or more embodiments disclosed in the present disclosure. For ease of explanation, FIG. 20 is described as a series of operations or actions 2000.

[0188] As shown, the series of actions 2000 includes an action 2010 of providing data from a first router of a first node. For example, action 2010 may include providing data from a first router of a first node, and the first router includes a transmission unit that is partially present within a photonic integrated circuit (PIC) of the first node, and the transmission unit includes a thermally stable optical modulator that is partially present within an electronic integrated circuit (EIC).

[0189] Also, as shown, the series of actions 2000 includes an action 2020 of carrying data from the first node to the second node. For example, action 2020 can include carrying data from the first node to the second node via an optical carrier such as an optical channel waveguide.

[0190] Also shown, the series of actions 2000 includes an action 2030 of receiving data at a second router of the second node. For example, action 2030 may include receiving data at a second router of the second node, and the second router includes a receiving unit that is partially present within the EIC and partially present within the PIC.

[0191] A computer-readable medium can be any available medium that can be accessed by a general-purpose or special-purpose computer system. A computer-readable medium storing computer-executable instructions is a non-transitory computer-readable storage medium (device). A computer-readable medium transmitting computer-executable instructions is a transmission medium. Thus, by way of example and not limitation, embodiments of the present disclosure can include at least two different types of computer-readable media, namely, non-transitory computer-readable storage media (devices) and transmission media.

[0192] Both non-transitory computer-readable storage media (devices) and transmission media can be temporarily used to store or transmit software instructions in the form of computer-readable program code that enables the execution of embodiments of the present disclosure. A non-transitory computer-readable storage medium can further be used to permanently or persistently store such software instructions. Examples of non-transitory computer-readable storage media include physical memories (e.g., RAM, ROM, EPROM, EEPROM, etc.), optical disk storage (e.g., CD, DVD, HDDVD, Blu-ray, etc.), storage devices (e.g., magnetic disk storage, tape storage, floppy disk, etc.), flash and other solid-state storage or memory, or any other non-transmission medium that can be used to store program code in the form of computer-executable instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, regardless of whether such program code is stored as software, hardware, firmware, or a combination thereof, or is stored in software, hardware, firmware, or a combination thereof.

[0193] "Network" or "communication network" is generally defined as one or more data links that enable the transmission of electronic data between computer systems and / or modules, engines, and / or other electronic devices. When information is transferred or provided to a computing device via a communication network or other communication connection (either hardwired, wireless, or a combination of hardwired or wireless), the computing device appropriately views this connection as a transmission medium. The transmission medium can include communication networks and / or data links, carrier waves, wireless signals, etc., which can be used to transmit desired program or template code means or instructions in the form of computer-executable instructions or data structures, and to which general-purpose or special-purpose computers can access.

[0194] Furthermore, upon reaching the components of various computer systems, program code in the form of computer-executable instructions or data structures can be automatically or manually transferred from the transmission medium to a non-transitory computer-readable storage medium (or vice versa). For example, computer-executable instructions or data structures received via a network or data link can be buffered in a memory (e.g., RAM) within a network interface module (NIC) and then ultimately transferred to the RAM of the computer system and / or a less volatile non-transitory computer-readable storage medium in the computer system. Therefore, it should be understood that non-transitory computer-readable storage media can include components of a computer system that also (or primarily) utilize the transmission medium.

[0195] The articles "a", "an", and "the" are intended to mean that one or more of the elements in the foregoing description exist. The terms "comprising", "including", and "having" are intended to be inclusive and mean that additional elements other than the recited elements may exist. Further, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be construed as excluding the existence of additional embodiments that also include the recited features. For example, any element described in connection with an embodiment herein can be combined with any element of any other embodiment described herein. Numerical values, percentages, ratios, or other values described herein are intended to include not only the value itself, but also "approximate" or "proximate" values with respect to the recited value that would be included by one of ordinary skill in the art in embodiments of the present disclosure. Accordingly, the recited values should be construed broadly enough to include at least values that are sufficiently close to the recited values to perform the desired function or achieve the desired result. The recited values include at least the errors expected in a suitable manufacturing or production process and may include values within 5%, 1%, 0.1%, or 0.01% of the recited value.

[0196] As used herein, the terms "about", "approximately", and "substantially" represent an amount close to the recited amount that performs the desired function or achieves the desired result. For example, the terms "about", "approximately", and "substantially" may refer to an amount within less than 5%, less than 1%, less than 0.1%, or less than 0.01% of the recited amount. Further, it should be understood that any direction or reference frame in the foregoing description is merely a relative direction or movement. For example, the expressions "up", "down", "above", and "below" merely describe the relative position and movement of the relevant elements.

[0197] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as exemplary forms of implementing the claims.

[0198] Industrial Applicability Claim 1: A circuit package comprising an interposer having a connection area for accommodating arithmetic elements, a chiplet connected to the connection area via an electrical connection of the interposer and forming a digital packet related to the connection area, and a transmission unit partly in the chiplet and partly in the interposer for transmitting the digital packet in optical form to a photonic interface via an optical fiber array unit (FAU).

[0199] Claim 2: The circuit package according to claim 1, further comprising a receiving unit partly in the chiplet and partly in the interposer for receiving an optical signal from the FAU and supplying the optical signal in digital form to an electrical area of the chiplet.

[0200] Claim 3: The circuit package according to claim 1, wherein the chiplet receives a message request requesting access from an arithmetic element to a memory controller or an arithmetic controller related to the photonic interface.

[0201] Claim 4: The circuit package according to claim 3, wherein the chiplet includes a router that receives a message request from an arithmetic element via an electrical connection of the interposer, and the router of the chiplet forms a digital packet including the message request from the arithmetic element and routing information of the message request indicating a destination of the requested memory controller or arithmetic controller.

[0202] Item 5: The circuit package according to Item 4, wherein the transmission unit transmits a message request in optical form to the photonic interface via the FAU based on the routing information.

[0203] Item 6: The circuit package according to Item 1, wherein the router of the chiplet includes a transmission unit and a reception unit.

[0204] Item 7: The circuit package according to Item 1, wherein the photonic interface is part of an electronic photonic memory fabric including a plurality of nodes.

[0205] Item 8: The circuit package according to Item 1, wherein the interposer is a photonic integrated circuit interposer (PIC interposer), and the chiplet has a bottom surface coupled to the connection region of the PIC interposer via an electrical connection.

[0206] Item 9: The circuit package of Item 1, wherein the interposer is a standard interposer connected to the PIC interposer, the chiplet has a bottom surface coupled to the PIC interposer, and this bottom surface is coupled to the connection region of the standard interposer, and the electrical connection passes through the PIC interposer and the standard interposer.

[0207] Claim 10: A memory fabric comprising: a plurality of nodes connected via photonic channels; a connection area provided for each of the plurality of nodes for accommodating corresponding arithmetic elements; a message router provided for each of the plurality of nodes having an electrical port for receiving a digital input from an optical reception unit and providing a digital output to an optical transmission unit; a routing controller provided for each of the plurality of nodes for generating a modified digital input from the digital input and providing the modified digital input as a modified digital output to the electrical port when the current node among the plurality of nodes is not the destination node; and a memory controller or an arithmetic controller provided for each node for receiving the digital output from the electrical port in the connection area when the current node is the destination node.

[0208] Claim 11: The memory fabric according to Claim 10, wherein a first node among the plurality of nodes has a first optical transmission unit connected to a second optical reception unit of a second node via a first photonic channel, and the second node has a second optical transmission unit connected to a first optical reception unit of the first node via a second photonic channel.

[0209] Claim 12: The memory fabric according to Claim 11, wherein the first photonic channel and the second photonic channel include an intra-chip link or an inter-chip link.

[0210] Claim 13: The memory fabric according to Claim 10, wherein the memory controller or the arithmetic controller provides data to the electrical port in response to communication with the connection area.

[0211] Claim 14: The memory fabric according to Claim 10, wherein modifying the digital input includes modifying routing information of a packet including a message request and routing information.

[0212] Item 15: The memory fabric according to Item 14, wherein modifying the routing information of a packet includes decrementing the value of the routing information corresponding to the position of the destination node among a plurality of nodes of the memory fabric.

[0213] Item 16: The memory fabric according to Item 10, wherein the routing controller transmits the modified digital output to an adjacent node of the memory fabric by converting the digital output into an optical signal and transmitting the optical signal to the adjacent node via the photonic interface of the memory fabric.

[0214] Item 17: A method of using a memory fabric, including receiving, by a chiplet, a request for an arithmetic controller or a memory controller of a destination node of the memory fabric, forming a packet including the request and the routing information of the request, optically transmitting the packet from a first optical interface of the chiplet to a second optical interface of a node of the memory fabric, wherein the first and second interfaces are connected via an optical fiber, converting the packet into a digital format at an electrical port of the node, communicating with the requested memory controller or the requested arithmetic controller of the destination node based on a determination that the node of the memory fabric is the destination node, and optically transmitting the packet to the next node based on a determination that the node of the memory fabric is not the destination node.

[0215] Item 18: The method according to Item 17, further including modifying the packet to update the routing information of the request based on a determination that the node of the memory fabric is not the destination node.

[0216] Item 19: The method according to Item 18, wherein optically transmitting the packet to the next node includes reconverting the digital format into a photonic format after modifying the packet and before providing the packet to the next node.

[0217] Item 20: The method according to item 17, wherein the request is received from an arithmetic element electrically interconnected to a circuit package including chiplets.

[0218] Item 21: A semiconductor having an optical layer laminated with an electrical layer, the semiconductor being divided into an electrical dedicated region and an electro-optical region, and one or more nodes in the electro-optical region, each of the one or more nodes being present in the optical layer and the electrical layer, a first portion of each of the one or more nodes being present in the optical layer and having at least one optical modulator and one or more heat generating elements present in the electrical layer and radiating heat towards the optical layer, a temperature sensing region in a second portion of each of the one or more nodes, the temperature sensing region having therein a temperature sensor for transmitting a heat signal to the electrical dedicated region, the heat signal being related to the current temperature of at least one optical modulator, a controller in the electrical dedicated region having an electrical interconnection to each of the one or more nodes for receiving the heat signal from the temperature sensor and transmitting a new voltage signal to the electro-optical region based on the heat signal.

[0219] Item 22: The thermal control system according to item 21, wherein the controller includes a control circuit constituted by hardware, software, or firmware.

[0220] Item 23: The thermal control system according to item 21, wherein at least one optical modulator is selected from the group consisting of an electro-absorption modulator (EAM) and a quantum-confined stark effect (QCSE) electro-absorption modulator.

[0221] Item 24: The thermal control system according to item 21, wherein the new voltage signal is a negative DC bias voltage related to the value of the heat signal.

[0222] Item 25: The thermal control system according to item 21, wherein at least one optical modulator has an anode and a cathode, and the controller transmits an AC swing signal to the cathode and a new voltage signal to the anode.

[0223] Claim 26: The thermal control system according to claim 21, further comprising a table including a plurality of voltage values associated with a plurality of temperatures, wherein the controller selects a voltage value of a new voltage signal using the table and the current temperature.

[0224] Claim 27: The thermal control system according to claim 21, further comprising a function for calculating a new voltage signal using a product of the current temperature and an activation function.

[0225] Claim 28: The thermal control system according to claim 21, wherein one or more heat generating elements are selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), a memory unit, a message router, a tensor engine, a digital neural network, a field programmable gate array (FPGA), and a processing element.

[0226] Claim 29: A system in package (SIP) comprising a photonic integrated circuit (PIC), an electronic integrated circuit (EIC) electrically connected to the PIC, a node having a first portion of the nodes present in the EIC and a second portion of the nodes present in the PIC, a plurality of heat generating elements provided in the first portion of the node and causing a thermal change in the second portion of the node by radiating heat toward the second portion of the node, a plurality of optical modulators provided in the second portion of the node, and a temperature sensing region provided in the second portion of the node for sending the current temperature to the controller, wherein the controller sends a first signal to each of the plurality of optical modulators based on the current temperature.

[0227] Claim 30: The SIP according to claim 29, wherein the first signal is a DC bias voltage signal.

[0228] Claim 31: The SIP according to claim 29, wherein each of the plurality of optical modulators includes a cathode and an anode, and the first signal is sent to the anode of each of the plurality of optical modulators.

[0229] Item 32: The controller is further configured to transmit a second signal to the cathode of each of the plurality of optical modulators, and the second signal includes an AC swing signal, and the SIP according to Item 31.

[0230] Item 33: The controller includes a control circuit composed of hardware, software, or firmware, and the SIP according to Item 29.

[0231] Item 34: The plurality of optical modulators are selected from the group consisting of an electro-absorption modulator (EAM) and a quantum-confined stark effect (QCSE) electro-absorption modulator, and the SIP according to Item 29.

[0232] Item 35: The controller transmits an AC swing signal to the cathodes of the plurality of optical modulators, and the SIP according to Item 31.

[0233] Item 36: Further includes a table including a plurality of voltage values associated with a plurality of temperatures, and the controller selects the voltage value of the first signal using the table and the current temperature, and the SIP according to Item 29.

[0234] Item 37: Further includes a function for calculating the first signal using the product of the current temperature and the activation function, and the SIP according to Item 29.

[0235] Item 38: The plurality of heat generation elements are selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), a memory unit, a message router, a tensor engine, a digital neural network, a field programmable gate array (FPGA), and a processing element, and the SIP according to Item 29.

[0236] Item 39: The temperature sensing region is off-center within the node, and the SIP according to Item 29.

[0237] Item 40: A method for controlling thermal variables related to a plurality of optical components, comprising applying a first signal to the cathode of each of the plurality of optical components, applying a second signal to the anode of each of the plurality of optical components, detecting the temperature of a region related to the plurality of optical components, receiving the current temperature related to the region, determining the start timing of thermal control for the plurality of optical components using the current temperature, when a first optical component among the plurality of optical components is an inter-chip modulator, obtaining a first voltage and transmitting the first voltage to the anode of the inter-chip modulator, when a second optical component among the plurality of optical components is an intra-chip modulator, obtaining a second voltage and transmitting the second voltage to the anode of the intra-chip modulator, wherein the second voltage has a value different from that of the first voltage.

[0238] Item 41: The method according to Item 40, wherein determining the start timing of thermal control for the plurality of optical components is performed using a control circuit.

[0239] Item 42: The method according to Item 40, wherein the second signal is a DC bias voltage signal.

[0240] Item 43: The method according to Item 40, wherein the first signal includes an AC swing signal.

[0241] Item 44: The method according to Item 41, wherein the control circuit includes hardware, software, or firmware.

[0242] Item 45: The method according to Item 41, wherein the plurality of optical components are selected from the group consisting of an electro-absorption modulator (EAM) and a quantum-confined stark effect (QCSE) electro-absorption modulator.

[0243] Item 46: The method according to item 40, further comprising a table including a plurality of voltage values associated with a plurality of temperatures, and determining the start timing of thermal control for a plurality of optical components further includes accessing the table.

[0244] Item 47: The method according to item 46, wherein determining the start timing of thermal control for a plurality of optical components further includes comparing the current temperature with a plurality of temperatures.

[0245] Item 48: Transmitting the first voltage and the second voltage includes selecting one or more rows in the table and obtaining values from one or more columns associated with the one or more rows, the method according to item 47.

[0246] Item 49: The method according to clause 40, further comprising one or more functions, wherein sending the first voltage to the anode of the inter-chip modulator and sending the second voltage to the anode of the inter-chip modulator includes calculating the first voltage and the second voltage by multiplying the current temperature by the activation function.

[0247] Item 50: An apparatus including an electronic integrated circuit (EIC), a photonic integrated circuit (PIC) stacked in direct connection with the EIC, and a plurality of nodes having a plurality of routers, each of the plurality of routers including a transmission unit and a reception unit, the transmission unit and the reception unit being partially present in the EIC and partially present in the PIC, each transmission unit including a thermally stable optical modulator in the portion present in the PIC, and data being optically moved within the PIC via an optical carrier between the thermally stable optical modulator of the first node and the reception unit of the second node.

[0248] Claim 51: The thermally stable optical modulator is the device according to claim 50, which operates in a temperature range greater than 30 degrees Celsius and is composed of a material selected from germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs).

[0249] Claim 52: The thermally stable optical modulator is the device according to claim 51, which is an electro-absorption modulator (EAM) that uses the Franz-Keldysh effect for the change in electrically induced optical absorption.

[0250] Claim 53: The thermally stable optical modulator is the device according to claim 50, which is an EAM that operates in a temperature range less than 30 degrees Celsius.

[0251] Claim 54: The thermally stable optical modulator is the device according to claim 53, which is an EAM composed of a material selected from the group consisting of germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on InP, and a III-V material based on GaAs.

[0252] Claim 55: The thermally stable optical modulator is the device according to claim 53, which uses the quantum confinement Stark effect (QCSE) for the change in electrically induced optical absorption.

[0253] Claim 56: The thermally stable optical modulator is the device according to claim 50, which has an output with a high optical modulation amplitude and is composed of a material selected from the group consisting of germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on InP, and a III-V material based on GaAs.

[0254] Claim 57: The thermally stable optical modulator is the device according to claim 56, which uses the QCSE for the change in electrically induced optical absorption.

[0255] Item 58: The thermally stable optical modulator is configured to operate stably over a wide temperature range and is composed of a material selected from the group consisting of germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on InP, and a III-V material based on GaAs, the device described in Item 50.

[0256] Item 59: The provision of data from the first router of the first node, wherein the first router includes a transmission unit that is partially present within the photonic integrated circuit (PIC) of the first node, the transmission unit including a thermally stable optical modulator that is partially present within an electronic integrated circuit (EIC); the conveyance of data via an optical carrier from the first node to the second node; and the reception of data at the second router of the second node, wherein the second router includes a reception unit that is partially present within the EIC and partially present within the PIC, a method for moving data within a digital circuit in a photonic fabric.

[0257] Item 60: The thermally stable optical modulator is an EAM optical modulator, an electro-absorption modulator (EAM) that uses the Franz-Keldysh effect for changes in electrically induced optical absorption, the method described in Item 59.

[0258] Item 61: The thermally stable optical modulator is an EAM that operates in a temperature range less than 30 degrees Celsius, the method described in Item 60.

[0259] Item 62: The method described in Item 60, wherein the EIC is directly coupled to the PIC.

[0260] Item 63: The EAM of the PIC is thermally stable within 50 microns from the EIC, the method described in Item 62.

[0261] Item 64: The method described in Item 59, wherein the first node and the second node are the same node.

[0262] Item 65: The method according to item 59, wherein the first node and the second node are different nodes.

[0263] Item 66: The method according to item 59, wherein the thermally stable optical modulator uses the quantum confinement Stark effect (QCSE) for the change in the electrically induced light absorption.

[0264] Item 67: The method according to item 59, wherein the thermally stable optical modulator has an output with a high optical modulation amplitude.

[0265] Item 68: The method according to item 67, wherein the thermally stable optical modulator uses the QCSE for the change in the electrically induced light absorption.

[0266] Item 69: The method according to any one of items 59 to 68, wherein the thermally stable optical modulator operates in a temperature range greater than 30 degrees Celsius and is composed of a material selected from germanium, silicon, an alloy of germanium, an alloy of silicon, a group III-V material based on indium phosphide (InP), or a group III-V material based on gallium arsenide (GaAs).

[0267] Item 70: The method according to item 59, wherein the EIC operates on a digital application-specific integrated circuit (ASIC).

Claims

1. A circuit package comprising: an interposer having a connection region for housing computing elements; a chiplet connected to the connection region via an electrical connection of the interposer for forming packets related to the connection region; and a transmitting unit partially located in the chiplet and partially in the interposer for providing the packets in optical format; In order to receive the packet from the transmitting unit, a first photonic channel connected to the circuit package at a first end, A memory fabric having multiple nodes, wherein the first photonic channel is connected to at least one of the multiple nodes at a second end, A system that includes this.

2. The system according to claim 1, further comprising a receiving unit partially located in the chiplet and partially located in the interposer for receiving an optical signal via the first photonic channel and supplying the optical signal in digital form to the electrical domain of the chiplet.

3. The system according to claim 1, wherein the chiplet receives a message request from the arithmetic element requesting access to a memory controller or arithmetic controller related to the memory fabric.

4. The chiplet includes a router that receives the message request from the computing element via the electrical connection of the interposer. The system according to claim 3, wherein the router of the chiplet forms a packet including a message request from the computing element and routing information of the message request indicating the destination of the memory controller or the computing controller to which the request is being made.

5. The system according to claim 4, wherein the transmitting unit transmits the message request in optical form via the first photonic channel based on the routing information.

6. The system according to claim 1, wherein the chiplet router includes the transmitting unit and the receiving unit.

7. The system according to claim 1, wherein the first photonic channel is part of an electronic photonic memory fabric including a plurality of nodes.

8. The aforementioned interposer is a photonic integrated circuit interposer (PIC interposer), The system according to claim 1, wherein the chiplet has a bottom surface coupled to the connection area of ​​the PIC interposer via the electrical connection.

9. The aforementioned interposer is a standard interposer connected to a PIC interposer. The chiplet has a bottom surface coupled to the PIC interposer, and the bottom surface is coupled to the connection area of ​​the standard interposer. The system according to any one of claims 1 to 8, wherein the electrical connection passes through the PIC interposer and the standard interposer.

10. Multiple nodes, Connection regions provided in each of the plurality of nodes for housing the corresponding computing elements, Each of the plurality of nodes is provided with a message router having an electrical port for receiving digital input from an optical receiving unit and providing digital output to an optical transmitting unit, Routing controllers provided in each of the plurality of nodes for generating a modified digital input from the aforementioned digital input and providing the modified digital input as a modified digital output to an electrical port, A memory controller or arithmetic controller provided in each node for receiving the digital output from the electrical port in the connection area, A memory fabric that includes this.

11. The optical transmission unit of the first node among the plurality of nodes includes a first portion of a bidirectional photonic channel having a first unidirectional link and a second unidirectional link, The first unidirectional link is connected to the optical receiving unit of the first node and is configured to receive optical signals from the optical interface of a second node among the plurality of nodes and the first waveguide. The second unidirectional link is connected to the optical transmission unit of the first node and is configured to transmit optical signals to the optical interface of the second node through the second waveguide. The optical transmission unit includes a driver and an optical modulator. The memory fabric according to claim 10, wherein the optical receiving unit comprises an optical photodiode and an electric transimpedance amplifier.

12. The memory fabric according to claim 11, wherein the first unidirectional link and the second unidirectional link include an inter-chip link.

13. The memory fabric according to claim 10, wherein the memory controller or the arithmetic controller provides data to the electrical port in response to mutual communication with the connection area.

14. The memory fabric according to claim 10, wherein modifying the digital input includes modifying the routing information of a packet, which includes message requests and routing information.

15. The memory fabric according to claim 14, wherein modifying the routing information of the packet includes decrementing the value of the routing information corresponding to the location of the destination node among the plurality of nodes of the memory fabric.

16. The routing controller then uses the modified digital output to Converting the aforementioned digital output into an optical signal, By transmitting an optical signal to an adjacent node via the photonic interface of the memory fabric, The memory fabric according to any one of claims 10 to 15, which transmits to an adjacent node of the memory fabric.

17. The chiplet receives requests to the arithmetic controller or memory controller of the destination node in the memory fabric, Forming a packet containing the aforementioned request and routing information for the aforementioned request, The packet is optically transmitted from the first optical interface of the chiplet to the second optical interface of the node of the memory fabric, wherein the first optical interface and the second optical interface are connected via an optical fiber. Converting the packet into a digital format at the electrical port of the node, Based on determining that the node of the memory fabric is the destination node, the node communicates with the arithmetic controller or memory controller of the destination node, wherein the node includes a message router that performs optical-electric conversion. Based on the determination that the node in the memory fabric is not the destination node, the packet is optically transmitted to the next node, wherein the message router of the node performs electro-optical conversion when transferring data to the next node along the optical link. A method of using a memory fabric, including [this].

18. The method of claim 17, further comprising modifying the packet to update the routing information of the request based on the determination that the node of the memory fabric is not the destination node.

19. The method of claim 18, wherein optical transmission of the packet to the next node includes modifying the packet and then converting the digital format back to a photonic format before providing the packet to the next node.

20. The method according to any one of claims 17 to 19, wherein the request is received from a computing element electrically interconnected to a circuit package including the chiplet.

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