Partial Address Translation Invalidation Request

Abstract

The cache control circuit is caused to identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, where the target cache entry includes a cache entry including partial address translation data indicating an address of a next-level page table specified by a table address of a target page table entry when the address translation data is used as a branch page table entry, and when the given cache entry is identified as the target cache entry, a partial address translation invalidation request for triggering invalidation of the given cache entry. The given cache entry is permitted to be retained when the given cache entry provides full address translation data indicating an address of a corresponding area of an address space corresponding to an output address specified by the target page table entry when used as a leaf page table entry.

Description

Technical Field

[0001] This technology relates to the field of data processing.

Background Art

[0002] In a data processing system, an input address can be translated into an output address using address translation data that depends on a page table entry of a page table structure in memory. The page table structure can be a multi-level page table structure where each level of the table structure specifies either an output address for address translation or an address of a next-level page table within a multi-level page table structure. This enables the address translation data to be stored across multiple individual regions of memory (without the need to allocate a contiguous block of memory large enough to hold, for example, a linear page table with enough entries to cover the entire address space). An address translation cache can also be provided to store a subset of the address translation data.

Summary of the Invention

[0003] Viewed from one embodiment, this technology provides an apparatus that includes a plurality of cache entries, each cache entry for storing address translation data that depends on one or more page table entries of a multi-level page table structure in memory, and each page table entry of the multi-level page table structure can be used as at least one of a branch page table entry that specifies a table address of a next-level page table, and a leaf page table entry that specifies an output address for an address translation mapping for a corresponding region of the address space, an address translation cache comprising the plurality of cache entries, and a cache control circuit, where A target cache entry for which a given cache entry in an address translation cache is to be invalidated, the target cache entry including a cache entry including partial address translation data indicating an address of a next-level page table whose address translation data indicates an address of a target page table entry when used as a branch page table entry, performing an invalidation lookup operation to identify whether the target cache entry is a target cache entry; A cache control circuit that responds to a partial address translation invalidation request to perform invalidating a given cache entry when the given cache entry is identified as a target cache entry. The partial address translation invalidation request indicates that a given cache entry is permitted to be held when the given cache entry provides full address translation data indicating an address of a corresponding region of an address space corresponding to an output address specified by a target page table entry when used as a leaf page table entry.

[0004] Viewed from another embodiment, the present technology provides a method, the method comprising: Storing, in each of a plurality of cache entries in an address translation cache, address translation data depending on one or more page table entries of a multi-level page table structure in memory, each page table entry of the multi-level page table structure being A branch page table entry specifying a table address of a next-level page table; and A leaf page table entry specifying an output address for an address translation mapping for a corresponding region of an address space, the address translation data depending on one or more page table entries of the multi-level page table structure that can be used as at least one of the branch page table entry and the leaf page table entry; In response to a partial address translation invalidation request, Performing an invalidation lookup operation to identify whether a given cache entry of an address translation cache is a target cache entry to be invalidated, where the target cache entry includes a cache entry containing partial address translation data indicating an address of a next-level page table specified by a table address of a target page table entry when the address translation data is used as a branch page table entry, and when a given cache entry is identified as a target cache entry, triggering invalidation of the given cache entry, The partial address translation invalidation request indicates that when a given cache entry provides full address translation data indicating an address of a corresponding area of the address space corresponding to an output address specified by a target page table entry when the given cache entry is used as a leaf page table entry, the given cache entry is permitted to be retained.

[0005] Viewed from another embodiment, the present technology provides a computer program including instructions that, when executed on a host data processing device, address translation logic for performing address translation based on a multi-level page table structure in memory, the address translation logic being configured to maintain an address translation data structure including a plurality of data structure entries, each data structure entry being for storing address translation data dependent on one or more page table entries of the multi-level page table structure, and each page table entry of the multi-level page table structure a branch page table entry specifying a table address of a next-level page table entry, and address translation logic that can be used as at least one of a leaf page table entry specifying an output address for an address translation mapping for a corresponding area of the address space, Control logic, executing an invalidation lookup operation to identify whether a given data structure entry of an address translation data structure is a target data structure entry to be invalidated, where the target data structure entry includes partial address translation data indicating an address of a next-level page table specified by a table address of the target page table entry when the target page table entry is used as a branch page table entry; triggering invalidation of the given data structure entry when the given data structure entry is identified as a target data structure entry, and controlling a host data processing device to provide control logic for responding to a partial address translation invalidation request; The partial address translation invalidation request indicates that the given data structure entry is permitted to be retained when providing full address translation data indicating an address of a corresponding area of the address space corresponding to an output address specified by a target page table entry when the given data structure entry is used as a leaf page table entry.

[0006] Viewed from another embodiment, the present technology provides a non-transitory computer-readable storage medium storing the above computer program. In an alternative embodiment, the computer-readable storage medium can be a transitory computer-readable storage medium.

[0007] Further aspects, features, and advantages of the present technology will become apparent from the following description of examples to be read in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] Before considering exemplary implementations with reference to the accompanying drawings, the following description is provided of exemplary implementations and related advantages.

[0010] According to one exemplary configuration, there are a plurality of cache entries, each cache entry being for storing address translation data that depends on one or more page table entries of a multi-level page table structure in memory, and each page table entry of the multi-level page table structure is · a branch page table entry that specifies the table address of the next-level page table, and · a leaf page table entry that specifies an output address for address translation mapping for a corresponding region of the address space, and an address translation cache is provided that includes a plurality of cache entries that can be used as at least one of them.

[0011] The apparatus also includes a cache control circuit, · performing an invalidation lookup operation to identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, the target cache entry including a cache entry that contains partial address translation data indicating the address of the next-level page table specified by the table address of the target page table entry when the address translation data is used as a branch page table entry, · triggering the invalidation of the given cache entry when the given cache entry is identified as a target cache entry, and includes a cache control circuit that responds to a partial address translation invalidation request.

[0012] The partial address translation invalidation request indicates that the given cache entry is permitted to be retained when the given cache entry provides full address translation data indicating the address of the corresponding region of the address space corresponding to the address specified by the target page table entry when the given cache entry is used as a leaf page table entry.

[0013] As described above, the page table is used to define address translation data for converting an input address to an output address. For example, the input address can be an address within an input address space, and the output address can be an address within an output address space different from the input address space. However, it will be understood that it is also possible to convert an input address within one address space to an output address within the same address space. Typically, a large amount of address translation data needs to be defined in the page table to provide translations for all accessible pages in memory. Therefore, it may be difficult to find a contiguous region of memory large enough to store all of the address translation data.

[0014] To address this problem, the address translation data can be defined in a set of nested page tables referred to as a multi-level page table structure. In a multi-level page table structure, each page table entry can be interpreted as specifying either an output address for address translation for a corresponding region of the address space (in which case the page table entry is used as a leaf page table entry), or a table address for the next-level page table (in which case the page table entry is used as a branch page table entry).

[0015] In some embodiments, each page table entry within a multi-level page table structure includes either a branch page table entry or a leaf page table entry (but not both), although in some other embodiments, note that a given page table entry may be usable as both a branch page table entry and a leaf page table entry. For example, in some implementations, one or more page table entries within a given page table of a multi-level page table structure may be defined as "self-referencing" by software so as to provide a pointer corresponding to the address of the given page table itself. This means that the same page table can be used at two or more levels of the lookup in the multi-level page table structure. Thus, if a self-referencing entry exists at the second-to-last level of the lookup in the page table structure, the same page table entry can be used as both a branch page table entry (when referenced at the second-to-last level) and a leaf page table entry (when referenced at the final level of the lookup). In another example, the self-referencing entry may be at the first level of the lookup (e.g., this may be referred to as level 0 in L0). In this embodiment, an address can be constructed that "dereferences" that entry. For example, consider a system with four lookup levels (e.g., L0, L1, L2, and L3). Once the self-referencing entry is dereferenced once, the level 2 (L2) page table entry containing the table address will be treated as a level 3 (L3) page table containing the output address, while the original L3 entry will be treated as a data page. The self-referencing entry can be dereferenced multiple times to access other levels. For example, the L2 table is treated as a data page when the entry is dereferenced twice.

[0016] Whether a page table is self-referential depends on a specific value of a pointer defined by software within an entry of that page table. The hardware may not be able to know whether the table is self-referential. For example, the address translation cache may cache information from the same page table multiple times for different levels of page table lookups.

[0017] A leaf page table entry can be considered the final level of the page table structure (although in an implementation that supports early termination of the page table walk based on a leaf entry indicator within a higher-level page table entry, a leaf page table entry may also be seen at a higher level of the table), and provides an output address corresponding to a specific input address to be translated. On the other hand, a branch page table entry does not provide an output address, but instead points to a further page table at a subsequent level of the multi-level table structure (e.g., provides its table address). The further page table may itself contain either a leaf page table entry or a branch page table entry.

[0018] The apparatus of the present technology includes an address translation cache. The address translation cache is a storage circuit that stores address translation data corresponding to a subset of page table entries in a multi-level page table structure, enabling subsequent translations that use the address translation data to be executed with reduced latency. The address translation cache can store full address translation (e.g., a translation lookaside buffer, TLB) to enable the input address to be translated to an output address without accessing the page table in memory. Alternatively, the address translation cache can store partial address translation data (e.g., a page walk cache (PWC)) to reduce the number of memory accesses required to translate a given input address (since the partial address translation data can allow one or more levels of the multi-level page table structure to be skipped). Thus, the full address translation data specifies the output address specified by the leaf page table entry (or information indicating the output address) corresponding to a given input address. On the other hand, the partial address translation data specifies the table address (or information indicating the table address) specified by the branch page table entry corresponding to a given input address. Further, some address translation caches store both full address translation data and partial address translation data. Other implementations may have separate address translation caches for caching full address translation data and partial address translation data, respectively. The address translation cache can take any form, for example, a fully associative cache, a direct map cache, or a set associative cache, each including a plurality of entries that store address translation data dependent on one or more page table entries in a multi-level page table structure.

[0019] This technology provides a partial-address-translation-invalidation (PATI) request, which is a request for a cache control circuit to invalidate partial address translation data stored in an address translation cache without invalidating full address translation data. In particular, in response to a PATI request, the cache control circuit identifies any target cache entries in the address translation cache that store partial address translation data corresponding to one or more target page table entries used as branch page table entries, and performs an invalidation lookup to trigger the invalidation of those target cache entries. For example, a target cache entry can be invalidated by clearing the "valid" bit (or setting the valid bit to a value indicating that the entry is invalid), as a result of which the partial address translation data can no longer be used when performing address translation. However, the PATI request also indicates that the cache control circuit is permitted to retain any entry that provides full address translation data (corresponding to one or more target page table entries used as leaf page table entries), even if the entry was or could have been identified as a target cache entry in the invalidation lookup.

[0020] When the address translation changes (e.g., when the address mapping from the input address to the output address changes), this typically involves a change to the output address stored in the leaf page table entry. Thus, it might be thought that there is no need to provide support for PATI requests that invalidate partial address translation data without invalidating full address translation data. Therefore, it is expected that not only partial address translation data but also full conversion data needs to be invalidated. However, the inventors of the present technology have noticed that while the partial address translation for a given address mapping can change, the full address translation data (e.g., the output address) might remain the same. This can be due to, for example, the rearrangement of the page table or the movement of the page table from one part of the memory to another. In this case, each table address of the page table might change without the output address changing. Thus, in such a case, even if the partial address translation data stored in the address translation cache is no longer up-to-date, any full address translation data held in the address translation cache remains correct. In this case, the inventors have noticed that there is no need to invalidate the full address translation data.

[0021] Accordingly, a PATI request is provided that enables partial address translation data to be invalidated without invalidating full address translation data. This allows any full conversion data stored in the address translation cache to remain available for use when performing address translation, reducing the latency associated with those translations (since the output address does not need to be fetched from memory every time). Thus, supporting the PATI request helps to improve performance compared to a system that does not support the PATI request.

[0022] In some embodiments, the partial address invalidation request specifies a table level identifier that indicates a subset of the page table levels of the multi-level page table structure, and the target page table entry includes a page table entry in one of the subsets of the page table levels specified by the table level identifier.

[0023] For a given address translation mapping (e.g., the translation of a given input address to a given output address), the partial address translation data stored in the address translation cache can indicate the table address of a page table at any level of the multi-level page table structure. However, in practice, since the top-level page table address may already be accessible from the base address register, it may not be necessary to cache the table address of the top-level page table (e.g., level 0). Thus, in some embodiments, the partial address translation data indicates the table address of a page table at any level of the multi-level page table structure other than the top level.

[0024] The inventors have noticed that in some cases, not all of the partial address translation data associated with a given address translation mapping needs to be invalidated using a PATI request. For example, in some cases, only a subset of the branch page table used to identify the address translation mapping is remapped (e.g., only some levels of a multi-level page table structure are changed). Thus, the inventors have found it useful that partial address translation data corresponding to a subset of levels of a multi-level page table structure can be invalidated without invalidating the partial address translation data associated with other levels. Thus, in this embodiment, a table level identifier can be specified by a PATI request, indicating that only the partial address translation data corresponding to one or more page table levels specified by the table level identifier should be invalidated (e.g., partial address translation data corresponding to levels other than the level identified by the table level identifier is permitted to be retained).

[0025] Other embodiments may not support such a table level identifier and can provide a PATI request that targets partial address translation associated with a target page table entry at any level.

[0026] In some embodiments, the apparatus includes processing circuitry that responds to a partial address translation invalidation instruction to issue a partial address translation invalidation request.

[0027] Therefore, in this embodiment, an instruction may be defined in an instruction set architecture (ISA) to cause a cache control circuit of an address translation cache to issue a PATI request. For example, the instruction can be a dedicated PATI instruction or a more general address translation invalidation instruction that includes a parameter (e.g., in instruction encoding or a control register) that distinguishes whether an address translation instruction should operate as a PATI instruction or as another type of address translation instruction.

[0028] In this embodiment, the processing circuit may be configured to perform data processing in response to an instruction decoded by an instruction decoder. The format of the instruction encoding and the function represented by each instruction may be defined according to an instruction set architecture (ISA). The ISA represents an agreed framework between a hardware manufacturer who manufactures processing hardware for a given processor implementation and a software developer who writes code to execute on that hardware, such that code written according to the ISA functions correctly on the hardware that supports the ISA.

[0029] When designing an ISA, there can be significant design challenges in determining the set of processing operations to be supported in the ISA and the encoding of instructions to represent those operations. In principle, there can be a wide variety of different types of processing operations that may be useful for supporting some program applications, but within the available encoding space, it may not be possible to represent all possible data processing operations that can be useful to a particular programmer. Increasing the instruction bit width will incur additional circuit area and power consumption each time an instruction is stored somewhere in the processor or transferred via a wired processing path between logic elements, so there can be a limit to the number of bits available for encoding each instruction. To limit hardware and power costs, the instruction bit width can be selected to leave an opcode space that is insufficient to represent all possible data processing operations that may be desired when considering the need to encode operand values through register specifiers and / or immediate values. Therefore, design decisions need to be made regarding which subset of operations is most important to support, and any operation that cannot be supported by a single instruction must be executed using a set of multiple instructions that have equivalent functionality when executed together.

[0030] Therefore, providing an instruction in the ISA that triggers the processing circuit to issue a PATI request can be considered a waste of the encoding space that can be used to define other more useful instructions, especially if the instruction is a dedicated PATI instruction, and thus the provision of a dedicated PATI instruction may seem counterintuitive. However, the inventors of the present technology have noticed that in some situations, for example, when low latency in address translation is important and when the structure of the multi-level address translation table is expected to be updated frequently without updating the address translation mapping itself, the PATI instruction can be valuable enough to justify the cost of implementing the instruction in the ISA.

[0031] In some embodiments, the partial address translation invalidation request includes a write request that requests the write of a partial address translation invalidation command to a region of memory accessible by the cache control circuit.

[0032] For example, a PATI request may request that a PATI command be written to a command queue in memory, the cache control circuit may monitor the command queue to identify any newly issued commands, and may respond to a PATI command written to the command queue to perform the PATI process described above. According to this approach, the PATI request can be implemented without necessarily defining a PATI instruction within the ISA, thereby avoiding occupying the encoding space within the ISA (although it will be understood that it is possible to define a PATI instruction that is converted to a write request by the processing circuit). Further, this approach can be particularly useful for invalidating cached partial address translations in an address translation cache external to the processor core (e.g., an address translation cache accessible by a device MMU such as an I / O MMU (input / output memory management unit) or an MMU within a GPU (Graphics Processing Unit)). The I / O MMU may also be referred to as a system MMU (SMMU).

[0033] In some embodiments, the cache control circuit is configured to detect a partial address translation invalidation command issued on the memory system interconnect, and the partial address translation invalidation request includes the partial address translation invalidation command.

[0034] Another way in which the PATI command can be issued to the cache control circuit is via the memory system interconnect (e.g., an interconnect that couples an address translation cache to memory and may also couple one or more request agents (such as processing elements) to each other and to memory). For example, the PATI request can be issued via the interconnect as the write request described above, but the interconnect can support a command encoding (different from the encoding used for write requests) that indicates the PATI command (e.g., unlike the write option, the PATI command can be indicated by the encoding on the request channel of the interconnect rather than the write data transmitted on the data channel associated with the write request). Again, the PATI command can be, but need not necessarily be, a command issued by the processing circuit in response to the execution of a PATI instruction.

[0035] In some embodiments, the apparatus includes a page table walk circuit responsive to an input address to look up a given page table entry within a multi-level page table structure based on an index portion of a given table address and the input address, and the page table walk circuit is configured to determine the size of the index portion to be used for at least one level of the multi-level page table structure depending on whether a table merge indication is set.

[0036] A page table walk circuit can be provided within the memory system of a device to find and retrieve a given output address for the translation of a given input address. For example, the page table walk circuit may derive some index portions from the input address (or the address translation circuit may derive the index portions and provide them to the page table walk circuit). Each index portion may be based on, for example, a subset of bits within the input address. The page table walk circuit then uses these index portions to "walk" a multi-level page table structure until it reaches the leaf page table entry corresponding to the input address. For example, this walk includes identifying the base address of a given page table (e.g., for the first level page table, this base address may be obtained from a base address storage location, while for each subsequent page table level, the base address is the table address specified by the branch page table entry of the page table at the previous level) and using the corresponding index portion to identify a particular page table entry within a given page table. This page table entry (if it is a branch page table entry) is then used in combination with another index portion to identify the next level page table entry, and this process is repeated until the leaf page table entry corresponding to the input address is identified.

[0037] The size of each index portion depends on the size of the corresponding page table, and a page table with more entries requires a larger index portion to enable the page table walk circuit to identify the necessary page table entries within that page table. Since it can be assumed that the size of the page table remains constant at each level, it can be expected that the index portions corresponding to each level of the multi-level page table structure remain constant. However, the inventors have noticed that in some cases it can be useful to be able to merge two or more levels of page tables together. For example, if a sufficiently large contiguous region of the address space becomes available for storing the merged L1 / L2 page table, it may be advantageous to move the L1 and L2 tables to that contiguous region of the address space and merge them into a single table (e.g., having a shared base address). The entries within the merged L1 / L2 page table can then be identified based on an updated base address (obtained from the L0 page table and thus needing to be updated after the merge) and a larger index portion (e.g., which can be an index portion comprising the previous L1 and L2 portions). This can be advantageous as the table address obtained from the merged L1 / L2 page table can be used to identify the L3 page table, thus avoiding a separate lookup of the L2 table and reducing the number of memory accesses required to obtain the address translation.

[0038] Accordingly, the page table walk circuit may use a table merge indication (e.g., which can be set to a predetermined value when two or more levels of a multi-level page table structure are merged) to determine which bits of the input address are to be used to determine each index portion to be used in the page table walk.

[0039] The merging of multiple levels of a multi-level page table structure is one example of a situation where partial address translation data for some input addresses can be updated without updating the full address translation data. For example, in the given example above, the partial address translation data indicating the base address of the L2 table may be old because the merged L1 / L2 table is being used, and the partial address translation indicating the base address of the L1 table may be old because the merged L1 / L2 page table may be stored at a different location in memory. However, although the structure of the L1 / L2 table has changed, the output address defined for a given input address has not necessarily changed. Thus, this is a specific example of a situation where the PATI requirement of the present technology may be useful. Similarly, if a previously merged table is split back into separate L1 and L2 tables from the merged L1 / L2 table, this can cause the cached partial address translation data to become stale.

[0040] While the given example above considers the merging of the L1 and L2 tables, it will be understood that it is also possible to merge other levels of the page table and to merge more than three levels. Further, while the merging of the page table has been described above as one exemplary use case for the PATI requirement, it will be understood that there are other possible use cases for the requirement. For example, memory defragmentation may, in some cases, lead to the need for one or more page tables to be moved from one location in memory to another. Thus, the base addresses of those tables being moved (and thus the corresponding partial address translation data) can be updated without updating the associated address translation mapping, even if no merging is being performed. Thus, the PATI requirement can be useful even in systems that do not support page table level merging.

[0041] The target cache entries to be invalidated can be identified in any of several ways.

[0042] In some embodiments, the partial address translation invalidation request specifies target address information corresponding to a target page table entry.

[0043] Thus, the target address information can be used to identify target cache entries, for example, by comparing the target address information with the address information associated with each of the cache entries in the address translation cache. This enables partial address translation data associated with a particular address translation mapping to be specified by a PATI request and invalidated in response to the PATI request, while avoiding the need to invalidate partial address translations for other address translation mappings for which the partial address translation data may still be valid. This helps to improve performance since the partial address translation data for those other address translation mappings can remain available in the cache for use by the address translation circuitry.

[0044] In some embodiments, when the PATI request specifies target address information, the cache control circuit responds to the partial address translation invalidation request by performing a prefetch operation to prefetch updated partial address translation data corresponding to the target address information.

[0045] Therefore, the partial address translation data updated in the memory (which leads to the need to issue a PATI request) can be updated in the address translation cache and the old partial address translation data can be invalidated. This reduces the latency of subsequent address translations based on the updated address translation data. The cache control circuit may execute a prefetch operation after all partial address invalidation operations have been performed (for example, after the partial address translation data stored in each of the target cache entries has been invalidated), or the cache control circuit may be able to execute the prefetch operation and the PATI operation in parallel.

[0046] In some embodiments, the cache control circuit is configured to restrict the prefetch operation to the prefetch of updated partial address translation data for an address corresponding to an invalidated cache entry invalidated in response to a partial address invalidation request.

[0047] In this way, the cache eviction policy applied by the cache control circuit (e.g., when trying to find an entry in the address translation cache for storing the prefetched updated address translation data) can be restricted so that no valid address translation data is evicted from the cache in response to a PATI request. Thus, the updated partial address translation data prefetched in response to a PATI request is restricted to the data corresponding to the address for which the corresponding target cache entry has been invalidated. This is useful because the cache eviction policy implemented by the address translation cache can be based on the currency of access to the address associated with the cached translation. The issuance of an invalidation request may not give any clue as to which address is most likely to be accessed again in the near future, but may only reflect that the management process has reorganized the page table structure. Therefore, it can be better that the prefetch executed in response to a PATI request does not disrupt the normal way of managing cache eviction. Therefore, on average, performance can be improved if the address translation data prefetched in response to a PATI request can replace only the invalidated address translation data without causing the eviction of other non-invalidated address translation data.

[0048] In these embodiments, the target address information specified by a PATI request can be any address information that enables a particular cache entry to be identified as the target cache entry.

[0049] In some embodiments, the address translation mapping is between an input address in an input address space and an output address in an output address space, and the target address information includes the input address information.

[0050] This can be useful because many address translation caches are indexed and / or tagged based on the input address to be translated. Thus, identification of the target cache entry based on the input address information (information indicating one or more input addresses) can use logic (e.g., comparison logic) that is likely already present within the cache and / or the cache control circuitry.

[0051] However, the target address information can also take different forms.

[0052] In some embodiments, the address translation mapping is between an input address in an input address space and an output address in an output address space, and the target address information includes an address in the output address space or in a further address space translated from the output address space.

[0053] For example, a target page table entry can be a page table entry stored in a memory address region corresponding to the address specified by a PATI request (e.g., the target page table entry can be an entry in a page table stored in a memory address region corresponding to the address specified in the PATI request). In fact, any address indicating target partial address translation data to be invalidated can, in principle, be used as target address information specified by a PATI request. For example, invalidation can be by a physical address (PA), and the partial address translation data is invalidated when it corresponds to an entry in a page table having a base address corresponding to the specified PA. In another embodiment, invalidation can be by an intermediate physical address (IPA), and the partial address translation data is invalidated when it corresponds to an entry in a page table having a base address corresponding to the specified IPA. Also, invalidation can be by a physical address (PA), and the target page table entry is an entry associated with a guest translation from a virtual address (VA) to an intermediate physical address (IPA) corresponding to a memory region corresponding to the specified physical address. This embodiment can be useful when a PATI request is issued by a hypervisor responsible for stage 2 mapping from IPA to PA.

[0054] In some embodiments, the target address information includes a target range of addresses that can span multiple pages.

[0055] Thus, instead of specifying an address indicating a single page (e.g., a single output address defined in a single leaf page table entry, or a corresponding single input address), a range of target addresses can be specified.

[0056] The above embodiments consider the PATI request that specifies the target address information, but this is not essential, and the PATI request can indicate the target cache entry in different ways.

[0057] For example, in some embodiments, the PATI request can be a global PATI request indicating that all partial address translation data in the address translation cache should be invalidated. In other embodiments, the PATI request can be a request to invalidate any partial address translation data corresponding to a specific level of the multi-level page table structure (e.g., identified by the above-mentioned table level indicator) regardless of the address.

[0058] In some embodiments, the partial address translation invalidation request specifies a context identifier, and the cache control circuit is configured to identify the target cache entry depending on the context identifier.

[0059] Therefore, in this embodiment, the cache control circuit is arranged to invalidate the partial address translation data corresponding to a specific context. For example, the PATI request can specify a context identifier (context ID) without specifying the target address information, or can specify both the target address information and the context identifier, so that the cache control circuit is made to identify any cache entry corresponding to both the target address information and the context identifier as the target cache entry.

[0060] Each cache entry in the address translation cache can be associated with a corresponding context identifier. In that case, the target cache entry can be identified by the cache control circuit by comparing the context identifier specified by the PATI request context identifier associated with the cache entry of the address translation cache.

[0061] In some embodiments, the context identifier is · a virtual machine identifier, and · an address space identifier, and · a secure state, indicating at least one of them.

[0062] The specified context identified by a given context identifier can include any instruction execution context that the device can support. For example, if the device can support the execution of virtual machines, the context identifier can include instructions for a specific virtual machine (e.g., virtual machine identifier, VMID). If the device supports conversion from input addresses within multiple different address spaces, the context identifier may include an address space identifier (ASID) for identifying a specific one of the multiple address spaces. If the device can operate in multiple security states (e.g., a secure state and a low-security state (sometimes referred to as an "insecure" state, although it will be understood that the "insecure" state can still be supported by some security means)), the context identifier can also identify a given security state.

[0063] The device may be capable of operating in an instruction execution context defined by multiple factors. For example, the device may be capable of supporting any combination of multiple virtual machines, multiple address spaces, and multiple security states. Thus, the context identifier can be based on any combination of two or more of VMID, ASID, and security state.

[0064] The context identifier can directly identify one or these variables (for example, the context identifier can be a virtual machine identifier (VMID), an address space identifier (ASID), or an indication of a security state, or can be a concatenation of multiple of these identifiers), or can indirectly indicate one or a combination of these variables.

[0065] In some embodiments, the partial address translation data is · the address of the next-level page table, and · a further address converted from the address of the next-level page table, and indicates one of them.

[0066] For example, the address translation data can identify an address (for example, it can be all or part of the address), or can identify a further address converted from that address. For example, in an apparatus that supports the conversion from a virtual address to a physical address via an intermediate physical address (for example, two-stage address translation), the partial address translation data can identify a physical table address (for example, a table address that directly points to the next-level page table) or an intermediate physical table address (for example, an address that is converted to a physical table address using a stage 2 conversion table).

[0067] The full address translation data can similarly be represented in multiple ways.

[0068] In some embodiments, the full address translation data is · the output address, and · a further address converted from the output address, and indicates one of them.

[0069] The above-described technology can be implemented in a hardware device having circuit hardware that implements the above-described address translation cache and cache control circuit (and optionally, any of the additional features provided by some embodiments, such as an address translation circuit, a processing circuit, and a page table walk circuit). For example, this can include support for PATI instructions as part of a native instruction set architecture supported by a decode circuit and a processing circuit.

[0070] However, in another example, the same technology can be implemented in a computer program (e.g., an architecture simulator or model) provided to control a host data processing device to provide an instruction execution environment for executing instructions from target code. The computer program includes address translation program logic for performing address translation based on a multi-level page table structure in memory (e.g., in memory accessible to the host data processing system), and the address translation program logic maintains an address translation data structure corresponding to the above-described address translation cache. The address translation data structure can be implemented in memory (e.g.) when the computer program is executed by the host data processing circuit, but is arranged to store a subset of the address translation data defined in the multi-level page table structure (e.g., including partial address translation data). The program also includes control logic for emulating the above-described cache control circuit to support PATI requests. Thus, when executed, the computer program controls the host data processing device to provide an instruction execution environment corresponding to the above-described device. Thus, the computer program of the present technology can enable the host data processing system to provide all of the above-described technical advantages.

[0071] Thus, such a simulator computer program can present an instruction execution environment similar to that provided by an actual hardware device capable of directly executing a target instruction set for target code executed on the simulator computer program, even if there is no actual hardware in the host computer executing the simulator program that provides these functions.

[0072] This can be useful for executing code written for one instruction set architecture on a host platform that does not actually support that architecture. Also, the simulator can be useful during the development of software for a new version of an instruction set architecture while software development is being carried out in parallel with the development of a hardware device that supports the new architecture. This can enable software to be developed and tested on the simulator so that software development can be started before a hardware device that supports the new architecture becomes available.

[0073] In some particular embodiments, the computer program may also include instruction decode program logic for decoding the instructions of the target code in order to control the host data processing device to perform data processing. Thus, the instruction decode program logic emulates the functionality of the instruction decoder of the hardware device as described above. The instruction decode program logic may include support for the PATI instructions described in some of the above embodiments. However, even if dedicated PATI instructions are not provided, control program logic is provided to emulate the above-described cache control logic in order to support PATI requests.

[0074] Furthermore, in some embodiments, the computer program described above can be stored in a computer-readable storage medium, which can be a temporary storage medium or a non-temporary storage medium.

[0075] Here, a specific example will be described with reference to the drawings.

[0076] FIG. 1 schematically illustrates an embodiment of a data processing system 102 having at least one processing element (PE) 104, which can be, for example, a CPU (central processing unit) or a GPU (graphics processing unit) having an instruction decoder 106 for decoding program instructions and a processing circuit 108 controlled to execute a processing operation in response to an instruction decoded by the instruction decoder 106. The PE 104 has a cache 110 for caching data from memory for faster access by the PE, and a memory management unit (MMU) 112 that functions as an address conversion circuit for converting an input address (e.g., a virtual address specified by an instruction executed by the PE 104) to an output address (e.g., a physical address identifying a location within the memory system). The MMU can have at least one address translation cache 114 for storing address translation data (which can include one or both of partial address translation data and full address translation data) that depends on page table data from a page table structure stored in the memory system. The page table structure defines an address mapping between the input address and the output address, and can also define a memory access permission that defines whether a particular software process running on the PE 104 is permitted to access a particular address. The MMU 112 can support two-stage address translation, where the mapping of a virtual address to a physical address depends on both stage 1 address translation data that maps the virtual address (VA) to an intermediate physical address (IPA) and stage 2 translation data that maps the IPA to a physical address (PA). The stage 1 address translation data can be set by an operating system or a virtual machine. The stage 2 translation data can be set by a hypervisor. This will be discussed in more detail below.

[0077] PE104 is an example of a claimant device capable of executing program instructions. Although FIG. 1 shows only one such claimant device, it will be understood that system 102 can include additional PEs, such as CPUs, GPUs, or other types of instruction execution devices, and can have two or more such devices.

[0078] In addition to the PE104 or other instruction-executable devices having their own internal MMU112, the system may also include a requesting device 120 that may not have an internal MMU (for example, these devices can be I / O devices, hardware accelerators, etc., and for example, they can include devices that do not execute their own instructions but can be configured by the PE to perform functions instead of the PE). Therefore, in order to access memory and provide an address translation function, such a device may communicate with the rest of the system via a system memory management unit (SMMU) 122 that includes an address translation circuit for controlling address translation and memory permissions based on translation data defined within a page table structure in memory. Also in this case, the SMMU122 may have one or more address translation caches 124 having a function similar to the address translation cache 114 within the MMU112 of the PE104. The device 120 accessing memory via the SMMU122 can include a cached device including an internal cache 126 and an uncached device having no cache. For example, the device 120 can include a display controller for controlling the display of image frames on a display, a network controller for controlling the input or output of data via a network, a hardware accelerator for performing a specific dedicated processing function in a more efficient way than can be achieved using software executed on a general-purpose processor such as the PE104, etc. Similar to the address translation cache 114 within the MMU112, the SMMU address translation cache 124 can cache one or both of partial address translation data and full address translation data. It should be noted that the PATI requests discussed herein are requests for invalidation of partial address translation data, but the requester issuing the PATI request does not know the form of the address translation cache present in any recipient of the request and simply issues the request.A recipient having only an address translation cache that caches full address translations can simply ignore the request, for example, while a recipient having an address translation cache that caches partial address translations operates in accordance with the request.

[0079] All of the requesting devices 104, 120 communicate with each other via an interconnect 130 that serves to route transactions between the requesting devices and the memory 132. The interconnect 130 may also serve to manage coherence between data cached in the respective caches 110, 126 of the system. FIG. 1 is a simplified diagram, and it will be understood that system 102 may have many other components not shown in FIG. 1 for the sake of brevity.

[0080] Figure 2 schematically illustrates some of the components within a data processing apparatus 102, such as the data processing apparatus shown in Figure 1. The data processing apparatus has a processing pipeline 108 (e.g., an example of a processing circuit that can form part of a PE such as a CPU or GPU), and in this case, the instruction decoder 106 is considered to be part of the processing circuit 108. It should be noted that whether the instruction decoder 106 is regarded as part of the processing circuit is a matter of semantics. The processing circuit 108 is for executing instructions defined in an instruction set architecture (ISA) in order to perform data processing operations represented by instructions. The processing pipeline 108 includes several pipeline stages. In this embodiment, the pipeline stages include a fetch stage 205 for fetching instructions from the instruction cache 207, a decode stage (instruction decoder) 106 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline, an issue stage 209 for checking whether the operands required for a micro-operation are available in the register file 215 and issuing the micro-operation for execution when the required operands for a given micro-operation become available, an execution stage 216 for performing the data processing operation corresponding to the micro-operation by processing the operands read from the register file 215 to generate a result value, and a write-back stage 218 for writing back the result of the processing to the register file 215. This is merely an example of a possible pipeline architecture, and it will be understood that other systems may have additional stages or stages with different configurations. For example, in an out-of-order processor, a register renaming stage may be included for mapping architectural registers specified by program instructions or micro-operations to physical register specifiers that identify physical registers within the register file 215.In some embodiments, there may be a one-to-one relationship between the program instructions defined by the ISA decoded by the decode stage 106 and the corresponding micro-operations processed by the execution stage. Also, there may be a one-to-many or many-to-one relationship between the program instructions and the micro-operations. For example, a single program instruction may be split into two or more micro-operations, or two or more program instructions may be fused and processed as a single micro-operation.

[0081] The execution stage 216 includes several processing units for performing different classes of processing operations. For example, the execution units may include a scalar arithmetic / logic unit (ALU) 240 for performing arithmetic or logic operations on scalar operands read from the register 215, a floating-point unit 242 for performing operations on floating-point values, a branch unit 244 for evaluating the result of a branch operation and adjusting the program counter representing the current execution point accordingly, and a load / store unit 246 for performing load / store operations to access data in the memory systems 207, 250, 252, 132.

[0082] As shown in FIG. 1, the memory management unit (MMU) 112 controls memory access permission checks and performs address translation between the virtual address specified by the load / store unit 246 based on the operand of the data access instruction and the physical address identifying the storage location of the data in the memory system. Although the MMU 112 is shown as being associated with the load / store unit 246, the MMU 112 may also be looked up during instruction fetch triggered by the fetch stage 205 (or, separately from the data-side MMU used by the load / store unit 246 for data access, a separate instruction-side MMU may be implemented to process instruction fetch, in which case both MMUs may cache information from a shared set of page tables in their address translation caches 114).

[0083] In this embodiment, the memory system includes a level 1 data cache 250, a level 1 instruction cache 207, a shared level 2 cache 252, and a main system memory 132. Caches 207, 250, 252 are examples of cache 110 shown in FIG. 1. It should be understood that this is only one example of a possible memory hierarchy and that other arrangements of caches can be provided. The specific types of processing units 240-246 shown in execution stage 216 are merely one example, and other implementations may have different sets of processing units or may include multiple instances of the same type of processing unit so that multiple micro-operations of the same type can be processed in parallel. FIG. 2, like FIG. 1, is only a simplified representation of some of the components of a possible processor pipeline implementation, and it should be understood that the processor may include many other elements not shown for simplicity.

[0084] FIG. 3 schematically illustrates a page table walk operation performed by a page table walk circuit to identify an output address corresponding to an input address to be translated, assuming a single-stage address translation mechanism is used. In this embodiment, the virtual address is 48 bits, and virtual address 300 is assumed to have a series of 9-bit portions associated with different levels of the page table walk process, with the 12 least significant bits indicating the page offset.

[0085] At the start of the page table walk process, the base register is accessed to identify the base address 310 that is used to identify page table 315. The 9 bits 305 associated with level 0 of the page table walk process identify an index into that page table 315 and are thus used to identify a branch page table entry that stores the intermediate level descriptor 317. This intermediate level descriptor 317 provides the base address 320 (also referred to as the table address) that is used to identify a further page table 330, and the virtual address bits 325 at level 1 are used to identify an index into that table. This identifies an intermediate level descriptor 332 that provides a further base address (table address) 335 for identifying page table 345. Then the virtual address bits 340 at level 2 are used to provide an index into that table 345 for identifying intermediate level descriptor 347, which then provides the base address (table address) 350 for identifying the final page table 360. Then the virtual address bits 355 at level 3 provide an index into that table 360, which identifies a leaf page table entry that specifies the final level descriptor 362 (also referred to as the page descriptor or leaf descriptor). Using the information provided by the page descriptor, it is then possible to generate full address translation data for storage in one of the entries of address translation cache 114, which enables conversion of virtual page number 355 to physical page number 370 and thus enables identification of the required page in memory. This enables a particular data item (or instruction) corresponding to the virtual address to be accessed by the core that issues the required physical address to the memory system. An example of an address translation cache 114, 124 that stores such full address translation data is a translation lookaside buffer (TLB).

[0086] In addition, partial address translation data corresponding to one or more of the base addresses 320, 335, 350 can also be stored in the address translation caches 114, 124. An example of the address translation caches 114, 124 that store partial address translation data is a page walker cache. Further, it is also possible to provide address translation caches 114, 124 that store both full address translation data and partial address translation data.

[0087] Note that in some embodiments, the final level descriptor (output address) can be specified at an earlier level during the page table walk process. For example, descriptor 347, when set, can have a block field that indicates that the descriptor is a block descriptor of the type of the final level descriptor (e.g., the output address for the address translation mapping for the corresponding block of memory) rather than an intermediate level descriptor (e.g., indicating a table address). Thus, the information in descriptor 347 can be used to generate full address translation data, and an entry in page table 345 that stores the block descriptor is a leaf page table entry in such embodiments.

[0088] Therefore, it will be appreciated that the full address translation information returned to the address translation circuit to enable address translation data to be assigned to the address translation cache can be related to a variety of different page sizes. For example, if the final level descriptor is descriptor 362, i.e., a leaf descriptor, the received translation information can be related to a page size of, for example, 4KB. Conversely, if the final level descriptor is a block descriptor, the associated page size is likely to be much larger. For example, if descriptor 347 in FIG. 3 is such a block descriptor, it can be related to a page size of 2MB in one embodiment. Further, as will be discussed in more detail below, it is also possible to cache partial address translation data indicating one of the base addresses 320, 335, 350 within the address translation cache.

[0089] For example, FIG. 4 schematically illustrates the use of a page walker cache 400 (an example of address translation caches 114, 124 that includes a plurality of cache entries 412) in an address translation circuit when converting from a virtual address (VA) as an input address to a physical address (PA) as an output address. The address translation circuit receives a virtual address and performs an initial lookup within the page walker cache 400. The lookup within the page walker cache 400 determines whether the virtual address or a portion thereof has already been most recently translated by the address translation circuit. The lookup within the page walker cache 400 results in a hit if any sequential most significant portion of the input address hits within the cache. Thus, if the most significant N-bit portion of the virtual address (e.g., the L0 index portion 305 in FIG. 3) hits within the page walker cache 400, there is a cache hit. There is also a hit if two of the most significant N-bit portions of the virtual address (e.g., the L0 index portion 305 and the L1 index portion 325) hit within the page walker cache 400. There is also a hit if three of the most significant N-bit portions of the virtual address (e.g., the L0, L1, and L2 index portions 305, 325, 340) hit within the page walker cache. If the page walker cache 400 is a shared structure that also caches full translations, there is also a hit if four of the most significant N-bit portions of the virtual address (e.g., the L0, L1, L2, and L3 index portions 305, 325, 340, 355) hit within the page walker cache. On the other hand, other implementations may cache full translations in a structure separate from partial translations, in which case the page walker cache 400 may not detect a hit based on combinations of the L0, L1, L2, and L3 index portions 305, 325, 340, 355.

[0090] In this way, the page walker cache can determine multiple hits for a single virtual address. If there are multiple hits in the page walker cache 400, the address translation circuit is configured to use the most specific match, i.e., the hit that matches the most significant N bits of the virtual address. Unless the match spans the full set of the index portions 305, 325, 340, 355 (in which case the result of the lookup is full address translation data), this lookup result is partial address translation data, enabling the address translation to be performed with reduced latency without identifying the output PA regardless of how many of the most significant N-bit portions match.

[0091] If the lookup in the page walker cache 400 misses, the address translation circuit performs the address translation by executing a maximum predetermined number of sequential lookups at the page table level, for example, by instructing the page walk circuit to perform a page walk as shown in FIG. 3. In this case, the page walk circuit performs L0 level lookup 402, L1 level lookup 404, L2 level lookup 406, and L3 level lookup 408 to determine the physical address.

[0092] If the best hit in the page walker cache 400 matches only the most significant N-bit portion of the virtual address, the address translation circuit can retrieve the result of the L0 lookup from the page walker cache, so there is no need to perform this lookup. Therefore, the address translation circuit performs L1 lookup 404, L2 lookup 406, and L3 lookup 408 to determine the physical address.

[0093] If the best hit in the page walker cache 400 matches the two most significant N-bit portions of the virtual address, the address translation circuit can retrieve the result of the L0 lookup or the L1 lookup from the page walker cache, so there is no need to perform these lookups. Therefore, the address translation circuit performs the L2 lookup 406 and the L3 lookup 408 to determine the physical address.

[0094] If the best hit in the page walker cache 400 matches the three most significant N-bit portions of the virtual address, the address translation circuit does not need to perform the L0 lookup, the L1 lookup, or the L2 lookup, and the results of these lookups can be retrieved from the page walker cache. Therefore, the address translation circuit performs only the L3 lookup 408 to determine the physical address.

[0095] FIG. 5 demonstrates a specific use case for the PATI requirements of the present technology. In particular, FIG. 5 schematically illustrates the details of the address translation circuit 540 in some exemplary configurations. The address translation circuit includes a partial translation storage circuit 550 for caching information related to previous address translations (e.g., this can be a page walker cache (PWC) 400, or a general-purpose address translation cache 114 that stores both full address translation data and partial address translation data). The address translation circuit 540 is also provided with at least one base register 552 (e.g., in some embodiments, there may be separate privileged and non-privileged base registers). The base register 552 includes, in sequence, the address of the first (e.g., L0) page table level, and optionally, size information indicating the size of the first page table level in sequence (e.g., depending on whether merging of the L0 page table is supported, if only the L1 / L2 page tables can be merged, this size information may not be required).

[0096] The address translation circuit 540 receives an input address 542 and performs a translation to output an output address 544. The address translation circuit 540 performs the translation by passing either the input address and a base address, or partial address translation data stored in the address translation cache 550, to the page table walk circuit 549, and the page table walk circuit 549 performs a page table walk that includes several sequential lookups in several page tables. A page table walk that includes several sequential lookups within a loop is performed. The page table includes a normal page table level 548 and a large (e.g., merged) page table level 546. Each lookup uses information from a previous lookup (or, in the case of an L0 lookup, the base address stored in a base address register) and information from the input address. The lookup includes an intermediate lookup that generates the address of the next sequential lookup in the next page table level in sequence and page table level size information indicating the size of the next page table level in sequence.

[0097] The address translation circuit also includes a cache control circuit 551 for controlling the address translation cache 550. The cache control circuit is configured to perform a partial address translation invalidation (PATI) process in response to a PATI request (e.g., a command written to the command queue, detected by the cache control circuit, or issued on the memory system interconnect 130). The PATI process includes identifying a target cache entry in the address translation cache (e.g., based on a target address and / or context ID specified by the PATI request), and invalidating the target cache entry if the target cache entry stores partial address translation data rather than full address translation data. For example, a PATI request can be issued when a plurality of normal page tables 548 are merged to form a large / merged page table 546. In this situation, any partial address translation data corresponding to the merged page table may no longer be correct even if the address translation itself remains correct. Therefore, in such a situation, it can be useful to be able to invalidate the partial address translation data without invalidating the full address translation data.

[0098] FIG. 6 schematically illustrates details of address translation performed by an address translation circuit 540 with various configurations. The address translation circuit 540 receives an input address. The input address includes 48 bits including a series of indexed portions (bits 47 to 39, bits 38 to 30, bits 29 to 21, and bits 20 to 12). Each indexed portion of the series of indexed portions corresponds to (is used for) a corresponding lookup level. In the illustrated configuration, four lookups are shown, and the first address includes one indexed portion for each of the lookups.

[0099] Bits 47 to 39 of the input address are L0 indexing bits used to index the page table level accessed during the L0 lookup (the first intermediate lookup in sequence). The L0 lookup is performed at the page table level at the page table address (L0 base address) stored in the storage circuit of the address translation circuit (e.g., the base address register). The storage circuit further includes size information indicating that the L0 lookup is a lookup at the normal page table level. The lookup performed based on the L0 base address and the L0 indexing bits returns, in sequence, the base address used for the next lookup, the L1 lookup, and the size information indicating that the L1 lookup is a lookup at the normal page table level.

[0100] Bits 38 to 30 of the input address are L1 indexing bits used to index the page table level accessed during the L1 lookup (the second intermediate lookup in sequence among a predetermined number of lookups). The L1 lookup is performed at the page table level at the base address (L1 base address) obtained during the L0 lookup. The lookup performed based on the L1 base address and the L1 indexing bits returns, in sequence, the next lookup, the L2 lookup, and the base address used for the size information indicating that the L2 lookup is a lookup at the normal page table level.

[0101] Bits 29 through 21 of the input address are L2 indexing bits that are used to index into the page table level accessed during the L2 lookup (the third intermediate lookup of a predetermined number of lookups). The L2 lookup is performed at the page table level at the base address (L2 base address) obtained during the L1 lookup. The lookup performed based on the L2 base address and the L2 indexing bits returns a base address that is used in the size information indicating that the next lookup, the L3 lookup, and the L3 lookup are normal lookups at the page table level.

[0102] Bits 20 through 12 of the input address are L3 indexing bits that are used to index into the page table level accessed during the L3 lookup (the final lookup of a predetermined number of lookups). The L3 lookup is performed at the page table level at the base address (L3 base address) obtained during the L2 lookup. The lookup performed based on the L3 base address and the L3 indexing bits returns an address that is combined with the address specification part (bits 11 through 0) of the input address to obtain the output address.

[0103] Figure 7 schematically illustrates details of how an input address can be translated to an output address when the L1 table and the L2 table are merged. As shown in Figure 6, the address translation circuit 540 receives an input address. The input address includes a 48-bit input address that includes a series of indexing portions (bits 47 to 39, bits 38 to 21, and bits 20 to 12). Each indexing portion of the series of indexing portions corresponds to (and is used for) a corresponding lookup level. However, the input address in this embodiment is treated as including only three index portions. The second indexing portion (bits 38 to 21) is a combination of two sequential indexing portions (i.e., the combination of bits 38 to 30 and bits 29 to 21, more generally, the normal (unmerged) page table indexed using N bits has 2 N entries, and when the large (merged) page table has 2 N*M entries, the index of the large lookup corresponds to the large lookup of the (large / merged) page table indexed using M sequential N-bit index portions of the input address). To ensure that the indexing portions of the input address are correctly interpreted by the address translation circuit, the corresponding page table level stores size information indicating when the next page table level is the large page table level. In the embodiment of Figure 7, the size information is indicated in the L0 page table entry identified in the first lookup to indicate that the L1 and L2 tables are merged.

[0104] As in the embodiment shown in FIG. 6, bits 47 to 39 of the input address are L0 indexing bits used to index to the page table level accessed during the L0 lookup (the first intermediate lookup in a predetermined number of sequential lookups). The L0 lookup is performed at the page table level at a table address (L0 base address) stored in the storage circuit (e.g., base address register) of the address translation circuit. The storage circuit further includes size information indicating that the L0 lookup is a lookup at the normal page table level. The lookup performed based on the L0 base address and the L0 indexing bits returns, in sequence, the base address used for the next lookup, the merged L1 / L2 lookup, and the size information indicating that the L1 / L2 lookup is a lookup at the large page table level.

[0105] Unlike the embodiment shown in FIG. 6, bits 38 to 21 of the input address are L1 / L2 indexing bits used to index to the large page table level accessed during the L1 / L2 lookup (a single lookup within the large page table, equivalent to the L1 lookup and L2 lookup in FIG. 6, which is the second lookup in sequence). The L1 / L2 lookup is performed at the large (merged) page table level at the base address (L1 / L2 base address) obtained during the L0 lookup. The lookup performed based on the L1 / L2 base address and the L1 / L2 indexing bits returns, in sequence, the base address used for the next lookup, the L3 lookup, and the size information indicating that the L3 lookup is a lookup at the normal page table level.

[0106] Bits 20 through 12 of the first address are L3 indexing bits that are used to index into the page table level accessed during an L3 lookup (the final lookup of a predetermined number of lookups), as in the embodiment of FIG. 6. The L3 lookup is performed at the page table level at the base address (L3 base address) obtained during the L1 / L2 lookup. The lookup performed based on the L3 base address and the L3 indexing bits returns an address that is combined with the addressing portion (bits 11 through 0) of the first address to obtain a second address.

[0107] In the illustrated configuration, the L1 and L2 lookups are combined to form a single lookup within a large page table. It will be readily apparent to those skilled in the art that, based on the techniques disclosed herein, any sequential page table level lookups can be combined. Further, the illustrated configuration shows that 9 bits are used for each of the N-bit portions. However, in alternative configurations, different numbers of bits can be provided, providing different lookup levels each using a different number of bits.

[0108] As described above, the present technology can also be implemented in a system using two-stage address translation. For example, the two-stage address translation can be implemented for memory accesses that occur when the processing circuit is in a particular subset of the execution state. Thus, virtual addresses from these execution states are translated using two sets of tables. These tables support virtualization and allow the hypervisor to virtualize the view of physical memory as seen by a given virtual machine (VM) (the virtual machine corresponding to the guest operating system and the applications controlled by that guest operating system). The set of translations controlled by the OS is called stage 1 (S1). The stage 1 table translates the virtual address to an intermediate physical address (IPA - an example of the intermediate address described above). At stage 1, the OS behaves as if the IPA were the physical address space. However, the hypervisor controls a second set of translations called stage 2 (S2). This second set of translations translates the IPA to a physical address.

[0109] The stage 1 translation table and the stage 2 translation table are implemented as a hierarchical table structure that includes several levels of translation tables as shown in FIGS. 3-7 for a single stage of translation (e.g., one of stage 1 and stage 2). In this embodiment, both the stage 1 table and the stage 2 table can have a four-level page table, i.e., level 0 (L0), level 1 (L1), level 2 (L2), and level 3 (L3). FIG. 8 does not show table integration for either stage 1 or stage 2, but can be supported as shown in the embodiment of FIG. 7.

[0110] As shown in FIG. 8, in fact, when a full conversion table walk including both stage 1 conversion and stage 2 conversion is executed, each stage 1 table base address obtained from the TTBR (translation table base register), and the table descriptors accessed in the stage 1 L0, L1, L2 conversion tables, become intermediate addresses that themselves need to be converted using the stage 2 conversion table. Therefore, if the conversion table walk does not encounter a block descriptor and proceeds all the way to L3 where a page descriptor is found, and there is no table merge applied, the full page table walk process may include accessing multiple levels of page tables in the following sequence. · Stage 2 conversion of the base address of the stage 1 L0 page table to a physical address (since stage 1 conversion is configured by the operating system, the stage 1 L0 base address is usually an intermediate physical address). The stage 2 conversion includes four lookups (stage 2 L0; stage 2 L1; stage 2 L2; stage 2 L3). · Stage 1 L0 lookup of the entry at the address obtained based on the L0 index part "a" of the target virtual address and the converted stage 1 L0 base address to obtain the stage 1 L1 base address (intermediate physical address). · Stage 2 conversion of the stage 1 L1 base address to a physical address (also including four lookups here). · Stage 1 L1 lookup of the entry at the address obtained based on the L1 index part "b" of the target virtual address and the converted stage 1 L1 base address to obtain the stage 1 L2 base address (intermediate physical address). · Stage 2 conversion of the stage 1 L2 base address to a physical address (also including four lookups here). · Stage 1 L2 lookup of the entry at the address obtained based on the L2 index part "c" of the target virtual address and the converted stage 1 L2 base address to obtain the stage 1 L3 base address (intermediate physical address). · Stage 2 conversion of the stage 1 L3 base address to a physical address (also including four lookups here). · Stage 1 L3 lookup of the entry at the address obtained based on the L3 index part "d" of the target virtual address and the converted stage 1 L3 base address to identify the target intermediate physical address corresponding to the target virtual address. · Stage 2 conversion of the target intermediate physical address to a target physical address (also including four lookups here) to represent the location in memory to access corresponding to the original target virtual address.

[0111] Thus, assuming no caching and a stage 2 start level of L0, the translation would involve a total of 24 lookups. If the start level for stage 2 is L1, this can reduce the number of lookups to 19 (one less lookup for each of the 5 stage 2 translations performed). Nevertheless, as can be seen from the above sequence, the execution of the entire page table walk process can be very slow because it may require a large number of accesses to memory to step through each level of the page table for each stage of address translation. This is often the reason for caching the information derived from the translation table walk in the address translation cache 114. The cached information can include full address translation data that can be the final stage 1 address mapping from VA to IPA, the final stage 2 mapping from IPA to PA, or the combined stage 1 and stage 2 mapping from VA directly to PA (derived from previous lookups in the stage 1 and stage 2 structures). Alternatively (or in addition, if the address translation cache 114 stores both partial address translation data and full address translation data), the cached information can include partial address translation data that can be based on entries from higher level page tables of the stage 1 table and the stage 2 table. This allows bypassing at least some steps of the full page table walk even if the final level address mapping for a given target address is not currently in the address translation cache.

[0112] Just as full address translation data can indicate a translation from VA to IPA, from IPA to PA, or from VA to PA, partial address translation data can also indicate a mapping from either VA or IPA to IPA or PA. For example, an address translation cache can store partial address translation data that maps an input VA to a corresponding L2 base address, and this partial address translation data can be represented as either IPA800 returned by the S1 L1 table, or PA802 returned by the S2 L3 table following a lookup of the IPA returned by the S1 L1 table. Alternatively, the partial address translation data stored in the address translation cache can map IPA to PA, for example, for a given IPA, indicating the PA of the S2 L2 table corresponding to that IPA.

[0113] The address translation cache can cache both stage 1 address translation data and stage 2 address translation data (for use, for example, when converting VA to PA without representing the intervening IPA), or separate address translation caches can be provided for stage 1 and stage 2 conversions. Thus, the output address identified by the full address translation data can be the physical address obtained from the stage 2 conversion table, or the intermediate address obtained from the stage 1 address translation table. Similarly, each cache entry can be associated with all or part of the input address, which can be a virtual address or an intermediate physical address.

[0114] FIG. 9 is a flowchart illustrating an example of a method executed by the cache control circuit 551 in response to a PATI request.

[0115] This method includes step 900 of determining whether a PATI request has been issued. When it is determined that a PATI request has been issued, the cache control circuit performs an invalidation lookup in the address translation cache to identify the target cache entry (902). For example, the invalidation lookup can be based on a comparison of the index / tag associated with the cache entry and the information specified by the PATI request (such as the target address), or it can be based on walking through the entire cache to check each entry and determine whether it is a hit. The walk method can be useful when the PATI request is invalidated by other parameters than the output address, table level, or input address (although it will be understood that this walk method can also be used when the PATI request specifies target input address information). For example, the invalidation lookup can determine whether a hit is detected for a specific entry depending on the information specified by the PATI address. For example, the PATI address can specify one or more of the following. · An input address or range of input addresses (e.g., this can be a virtual address (VA) or a range of VAs within the virtual address space, or an intermediate physical address (IPA) or a range of IPAs within the intermediate physical address space), in which case a hit is not detected unless the input address information associated with a given entry matches the input address information specified by the PATI request. · An output address or range of output addresses within the output address space (e.g., this can be a physical address (PA) or a range of PAs within the physical address space, or an intermediate physical address (IPA) or a range of IPAs within the intermediate physical address space), in which case a hit is not detected unless the output address information associated with a given entry matches the output address information specified by the PATI request. ·An additional address or range of additional addresses within an additional address space converted from the output address space (e.g., when invalidating a stage 1 partial conversion that provides a table address for use when converting VA to IPA, the PA can invalidate the PATI request). ·A table level indicator that identifies one or more levels of the lutilevel page table structure, in which case a hit is not detected unless a given entry holds partial address translation data corresponding to the identified one or more levels specified by the table level indicator in the PATI request. ·A context identifier (e.g., based on one or more of a virtual machine identifier (VMID), an address space identifier (ASID), or a security state identifier), in which case a hit is not detected unless the context identifier associated with a given entry in the cache matches the context identifier specified by the PATI request.

[0116] Further, in some embodiments, the PATI request can be a global PATI request that triggers invalidation of all partial address translation data in the address translation cache. In this case, a hit can be detected for entries in which the partial address translation data is stored.

[0117] At 904, if the lookup misses in the address translation cache (e.g., no hit is detected), the process ends and the control circuit signals completion (e.g., to the processing circuit) (906). On the other hand, at 904, if at least one hit is detected (e.g., if hits are detected for N entries), after initializing the index 'i' to 0 at (908), a set of the following steps is performed for each hit entry. ·At 910, it is determined whether the i-th hit entry holds partial address translation data that is indicated to be currently valid (e.g., as opposed to holding full address translation data). · If so, the i-th hit entry is invalidated at 912; otherwise, step 912 is skipped for the i-th hit entry (e.g., it is not invalidated). · It is determined at 914 whether there is still at least one entry to be processed (e.g., if i < N - 1). · If so, the process ends and completion is signaled at 906; otherwise, the value of i is incremented by 1 at 916 (e.g., i++ can also be written as i += 1 or i = i + 1), and the process repeats from step 910.

[0118] Steps 902 to 916 collectively are the PATI process 918.

[0119] Thus, by this approach, the cache control circuit responds to a PATI request by invalidating the partial address translation data within any hit entry without invalidating the full address translation data, even when the full address translation data meets the filter conditions specified by the PATI request (e.g., specified based on the input / output address and / or context identifier).

[0120] FIG. 10 is a flowchart illustrating a prefetch operation 1000 executed by a cache control circuit in response to a PATI request. This process can be executed in parallel with the PATI process 918 or after executing the PATI process.

[0121] Similar to the PATI process, the cache control circuit executes a partial address translation invalidation (PATI) process 918 and, if an entry has been invalidated during the PATI process, prefetches the updated partial address translation data at 1002 to respond to the PATI request. When the prefetch operation is complete, the cache control circuit signals completion at 1004.

[0122] Thus, the latest partial address translation data can be placed in the address translation cache without evicting valid entries of the cache that hold address translation data for other address translation mappings.

[0123] FIG. 11 shows an example of a method executed by a processing circuit in response to receiving a decoded PATI instruction. The method includes determining 1100 whether the PATI instruction has been decoded, and triggering 1101 a partial address translation invalidation (PATI) process 918 that is executed in the MMU of the processing element itself when it is determined that the PATI instruction has been decoded, and issuing 1102 a PATI command to a cache control circuit. A PATI command, which is an example of a PATI request, may be issued by writing the command to a command queue in memory (e.g., an area of memory accessible to the cache control circuit), or by issuing the command on the memory system interconnect 130.

[0124] FIG. 12 shows how a cache control circuit may receive a PATI command via a command queue. For example, the cache control circuit may monitor 1200 the command queue for updates to determine 1202 when a PATI command has been written to the command queue. When it is determined that a PATI command has been written to the command queue, the cache control circuit executes the PATI process 918 and removes 1204 the PATI command from the command queue.

[0125] FIG. 13 illustrates a simulator implementation that can be used. The above-described embodiments implement the present invention in terms of an apparatus and method for operating specific processing hardware that supports the technology, but it is also possible to provide an instruction execution environment according to the embodiments described herein implemented by the use of a computer program. Such a computer program is often referred to as a simulator as long as the computer program provides a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators including dynamic binary translators. Typically, the simulator implementation can be executed on a host processor 1330 and, optionally, execute a host operating system 1320 to support a simulator program 1310. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or there may be multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that execute at a reasonable speed, but such an approach may be justified in certain situations, such as when it is desired to execute native code for another processor for reasons of compatibility or reuse. For example, the simulator implementation may provide an instruction execution environment having additional functionality not supported by the host processor hardware, or may provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is described in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, 1990 Winter USENIX Conference, pages 53-63.

[0126] Previously, embodiments have been described with reference to specific hardware components or features, but in simulated embodiments, equivalent functionality can be provided by suitable software components or features. For example, a particular circuit may be implemented as computer program logic in a simulated embodiment. For example, this may include processing program logic 1312 that emulates processing circuit 108, address translation program logic 1314 that emulates address translation circuits 112, 540, and table access program logic 1318 that emulates a page table walk circuit. Similarly, memory hardware such as registers or caches can be implemented in embodiments simulated as software data structures, and register emulation logic 1313 can be provided to control the emulation of registers. For example, address translation caches 114, 124, 550 can be implemented as software data structures. In an arrangement where one or more of the hardware elements referred to in the foregoing embodiments are present in host hardware (e.g., host processor 1330), some simulated embodiments can use the host hardware where appropriate.

[0127] The simulator program 1310 can be stored in a computer-readable storage medium (which can be a temporary or non-temporary medium), and provides a program interface (instruction execution environment) to target code 1300 (which can include applications, operating systems, and hypervisors) that is the same as the interface of the hardware architecture modeled by the simulator program 1310. Thus, in some embodiments, the program instructions of target code 1300 that may include the above-described PATI instructions can be executed from within the instruction execution environment using the simulator program 1310, such that a host computer 1330 that does not actually have the hardware functions of the above-described apparatus 1022 can emulate these functions.

[0128] For example, a software-maintained address translation cache may be provided to cache translation data and provide faster access to partial / full translations than when a full page table walk process (such as that shown in FIG. 8) is executed. This software-maintained cache is a data structure maintained by address translation program logic 1314 in host memory by a simulator program to emulate a TLB that would be provided in a hardware embodiment, by storing a subset of the address translation data represented by a multi-level page table structure and by being a flat table to provide reduced latency for address translation. Then, according to an embodiment of the present technology, cache control program logic (which can be considered part of address translation program logic 1314) invalidates partial translations from the software-maintained cache structure when a PATI request (which can be in the form of a PATI instruction or can be indirectly requested, for example, by requesting a write of a PATI command to a command queue) is encountered in the target code.

[0129] In this application, the term "configured to..." is used to mean that an element of a device has a configuration capable of performing a defined operation. In this context, "configuration" means a way of arranging or interconnecting hardware or software. For example, a device may have dedicated hardware to provide a defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that an element of a device needs to be changed in any way to provide a defined operation.

[0130] Exemplary embodiments of the present invention are described in detail herein with reference to the accompanying drawings, but it is to be understood that the present invention is not limited to these exact embodiments and that various changes and modifications can be made by those skilled in the art without departing from the scope of the present invention as defined by the appended claims.

Claims

1. It is a device, Multiple cache entries, each cache entry for storing address translation data that depends on one or more page table entries of a multilevel page table structure in memory, and each page table entry of the multilevel page table structure is A branch page table entry that specifies the table address of the next-level page table, An address translation cache comprising multiple cache entries, each of which can be used as at least one of the following: a leaf page table entry specifying an output address for address translation mapping to a corresponding region of the address space; A cache control circuit, Performing an invalidation lookup operation to identify whether a given cache entry in the address translation cache is a target cache entry to be invalidated, wherein the target cache entry includes a cache entry containing partial address translation data indicating the address of the next-level page table specified by the table address of the target page table entry when the address translation data is used as the branch page table entry, The system includes a cache control circuit that responds to a partial address translation invalidation request in order to trigger the invalidation of a given cache entry when the given cache entry is identified as the target cache entry, The partial address translation invalidation request indicates that the given cache entry is permitted to be retained when it provides full address translation data indicating the address of the corresponding region of the address space corresponding to the output address specified by the target page table entry when the given cache entry is used as the leaf page table entry.

2. The apparatus according to claim 1, wherein a partial address translation invalidation request specifies a table-level identifier indicating a subset of page table levels of the multilevel page table structure, and the target page table entry includes a page table entry in one of the subsets of page table levels specified by the table-level identifier.

3. The apparatus according to claim 1 or 2, further comprising a processing circuit that responds to a partial address translation disablement command in order to issue the aforementioned partial address translation disablement request.

4. The apparatus according to claim 1 or 2, wherein the partial address translation disable request includes a write request requesting the writing of a partial address translation disable command to a memory region accessible by the cache control circuit.

5. The apparatus according to claim 1 or 2, wherein the cache control circuit is configured to detect a partial address translation invalidation command issued on the memory system interconnect, and the partial address translation invalidation request includes the partial address translation invalidation command.

6. The system includes a page table walk circuit that responds to an input address, for looking up a given page table entry in the multilevel page table structure based on a given table address and an index portion of the input address, The apparatus according to claim 1 or 2, wherein the page table walk circuit is configured to determine the size of the index portion to be used for at least one level of the multilevel page table structure, depending on whether a table merge instruction is set.

7. The apparatus according to claim 1 or 2, wherein the request to disable partial address translation specifies target address information corresponding to the target page table entry.

8. The apparatus according to claim 7, wherein the cache control circuit responds to the partial address translation invalidation request in order to perform a prefetch operation to prefetch updated partial address translation data corresponding to the target address information.

9. The apparatus according to claim 8, wherein the cache control circuit is configured to limit the prefetch operation to prefetching updated partial address translation data for addresses corresponding to invalidated cache entries that have been invalidated in response to the partial address translation invalidation request.

10. The address translation mapping is located between the input address in the input address space and the output address in the output address space. The apparatus according to claim 7, wherein the target address information includes input address information.

11. The address translation mapping is located between the input address in the input address space and the output address in the output address space. The apparatus according to claim 7, wherein the target address information includes an address in the output address space or in a further address space converted from the output address space.

12. The apparatus according to claim 7, wherein the target address information includes a target range of addresses that can span multiple pages.

13. The apparatus according to claim 1 or 2, wherein the partial address translation invalidation request specifies a context identifier, and the cache control circuit is configured to identify the target cache entry depending on the context identifier.

14. The aforementioned context identifier is Virtual machine identifier and Address space identifier, The apparatus according to claim 13, which exhibits at least one of a secure state and

15. The aforementioned partial address translation data is The address of the next-level page table, The apparatus according to claim 1 or 2, which indicates one of the following: a further address converted from the address in the next-level page table.

16. The aforementioned full address translation data is The aforementioned output address and, The apparatus according to claim 1 or 2, which indicates one of the following: a further address converted from the output address.

17. It is a method, Each of the multiple cache entries of the address translation cache contains one or more page table entries of a multilevel page table structure in memory, where each page table entry of the multilevel page table structure is A branch page table entry that specifies the table address of the next-level page table, A leaf page table entry that specifies an output address for address translation mapping to a corresponding region of the address space, and a storage of address translation data that depends on one or more page table entries of a multilevel page table structure, which can be used as one of these leaf page table entries. In response to a request to disable partial address translation, Perform an invalidation lookup operation to identify whether a given cache entry in the address translation cache is a target cache entry to be invalidated, wherein the target cache entry includes a cache entry in which the address translation data includes partial address translation data indicating the address of the next-level page table specified by the table address of the target page table entry when the target page table entry is used as the branch page table entry, The process includes, when the given cache entry is identified as the target cache entry, triggering the invalidation of the given cache entry, A method for indicating that the given cache entry is permitted to be retained when the given cache entry provides full address translation data indicating the address of the corresponding region of the address space corresponding to the output address specified by the target page table entry when the target page table entry is used as the leaf page table entry.

18. A computer program that includes instructions, wherein the instructions, when executed on a host data processing device, Address translation program logic for performing address translation based on a multilevel page table structure in memory, wherein the address translation logic is configured to maintain an address translation data structure comprising a plurality of data structure entries, each data structure entry for storing address translation data that depends on one or more page table entries of the multilevel page table structure, and each page table entry of the multilevel page table structure is A branch page table entry that specifies the table address of the next-level page table entry, Address translation program logic, which can be used as at least one of: a leaf page table entry that specifies an output address for address translation mapping to a corresponding region of the address space; Control program logic, Performing an invalidation lookup operation to identify whether a given data structure entry of the address translation data structure is a target data structure entry to be invalidated, wherein the target data structure entry includes a data structure entry in which the address translation data includes partial address translation data indicating the address of the next-level page table specified by the table address of the target page table entry when the target page table entry is used as the branch page table entry, To provide control program logic that responds to a partial address translation invalidation request, when the given data structure entry is identified as the target data structure entry, the host data processing device controls the host data processing device to trigger the invalidation of the given data structure entry, and to perform the following: A computer program that indicates that the given data structure entry is permitted to be retained when the given data structure entry provides full address translation data indicating the address of the corresponding region of the address space corresponding to the output address specified by the target page table entry when the target page table entry is used as the leaf page table entry.

19. A computer-readable storage medium for storing the computer program described in claim 18.

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