A memory array that uses flying bit lines to increase the effective bit line length and support higher performance and increased memory density, and related methods

Abstract

A memory array and related method that utilize flying bit lines to increase the effective bit line length and support higher performance and increased memory density. To increase memory density, the memory array has a first memory sub-bank and one or more second memory sub-banks. The first memory sub-bank includes a first bit line for each of its memory column circuits. To avoid the need to extend the length of the first bit line coupled to the second memory bit cells of the second memory sub-bank, each memory sub-bank has dedicated first and second bit lines that couple their respective memory bit cells to the access circuit. The second bit line effectively "flies" independently from the first bit line of the first memory sub-bank. The first bit line of the first memory sub-bank does not need to be extended to provide a bit line for the second memory sub-bank.

Description

Technical Field

[0001] The technology of the present disclosure relates to computer memory systems, and more particularly to memory arrays implemented with multiple memory banks to improve memory performance and power consumption.

Background Art

[0002] A processor-based system including a memory system that supports read and write operations. The memory can be used not only for storing data but also for storing program code for storing instructions to be executed. Such a processor-based system has conventionally employed both cache memory and non-cache memory, and may also be referred to as "main memory" or "system memory". For example, a CPU within a processor-based system can access an on-chip local private cache memory. In a processor-based system, multiple CPUs can also access a shared cache memory. The processor-based system also employs a main memory or system memory that includes memory storage units (i.e., memory bit cells) across the entire physical address space of the processor-based system. Each of these different types of memory generally employs a memory array including memory bit cells organized in a matrix structure for storing data. Memory rows including memory bit cells in each column are accessed to read a data word from the memory or to write a data word to the memory. The memory bit cells can be provided in memories of various technologies, such as static random access memory (RAM) (SRAM) bit cells and dynamic RAM (DRAM) bit cells.

Summary of the Invention

[0003] In the cache memory of a processor-based system, it is becoming increasingly important to be able to provide a larger density of memory arrays. This is to increase the chance that accesses to memory are supplied from the cache memory rather than being long-latency, high-access to system memory. However, as the cache memory grows, it can reduce power, performance, and area (PPA). A larger cache memory consumes more semiconductor die area than a smaller cache memory using the same memory bit cell technology. A larger cache memory can also increase the access latency compared to a smaller cache memory. This is because the column bit lines connected to the support-side access circuits (e.g., write driver circuits and read sense circuits) are lengthened to reach the expanded area of the memory array. Thus, the overall memory access latency can increase by just the access time to the memory bit cell located farthest from the support-side access circuits. Also, a larger cache memory can increase the cache latency by providing longer bit lines to reach the increased number of memory bit cells coupled to the bit lines. This increases the capacitance of the bit lines and thus the access latency. Manufacturing design rules and the associated manufacturing process may limit the overall length of the bit lines in the memory array, effectively limiting the density of the memory array despite the trade-off of allowing an increase in access latency.

[0004] Exemplary aspects disclosed herein include a memory array that utilizes flying bit lines to increase the effective bit line length and support higher performance and increased memory density. Related methods are also disclosed. In an exemplary aspect, to increase the density of the memory array rather than providing the memory capacity of one memory sub-bank, the memory array includes a first memory sub-bank and one or more second memory sub-banks. In one example, the first memory sub-bank is physically closer to the support side access circuit than the second memory sub-bank. The first memory sub-bank includes a first bit line for each of its first memory column circuits. The first bit line couples the first memory bit cells in each of the first memory column circuits within the first memory sub-bank to an access circuit (e.g., a column multiplexer circuit, a read sense circuit). To avoid the need to extend the length of the first bit line coupled to the second memory sub-bank, which could increase access latency, the second memory sub-bank includes a separate second bit line. In this way, each memory sub-bank has dedicated first and second bit lines that couple their respective memory bit cells to the access circuit. The second bit line of the second memory sub-bank can substantially "fly" independently of the first bit line of the first memory sub-bank, and the second bit line is independently coupled to the access circuit. The first bit line of the first memory sub-bank need not be extended to provide a bit line for the second memory sub-bank. In this way, the memory density can be increased without incurring the cost of increased access latency due to high bit line capacitance, high dynamic energy consumption, and / or violation of manufacturing design rules that could limit the memory density. The memory density can also be increased based on savings in high-latency accesses without sacrificing power consumption. Also, in another example, to avoid contention in the shared access circuit by the first and second memory sub-banks not sharing bit lines and sharing the access circuit, the first and second memory sub-banks are not accessed simultaneously for memory operations.However, memory accesses to different memory sub-banks are managed to benefit from the increased memory density without the need to extend the bit line lengths of the first memory sub-bank.

[0005] In another example, it is desirable to avoid the need for the cell circuit of the first memory bit cell in the first memory sub-array to support a separate metal wire path for the second bit line to extend there towards the access circuit. In this regard, the cell circuit of the first memory bit cell of the memory row circuit of the first memory sub-bank adjacent to the second memory sub-bank is provided as a flying bit line cell circuit. The flying bit line cell circuit is a dedicated cell circuit that includes not only the first memory bit cell and the metal wire for the first bit line, but also a jumper circuit. The jumper circuit extends the coupled second bit line to a different metal layer from an adjacent memory bit cell row in the second memory sub-bank. Then, the second bit line "flies over" the first memory sub-bank to the access circuit and is extended within this different metal layer. In this way, the flying bit line cell circuit facilitates extending the coupled second bit line of the second memory sub-bank to the access circuit without the second bit line being coupled to the first bit line of the first memory sub-bank (which could result in extending the length of the first bit line). Extending the length of the bit lines of the memory array can increase the latency of memory accesses to the memory array. Further, by providing the flying bit line, each first memory row circuit in the first memory sub-bank can avoid the need to support a separate metal wire for the second metal wire to pass through the first memory sub-bank to the access circuit (which could potentially violate design and manufacturing rules).

[0006] In this regard, in one exemplary embodiment, a memory system is provided. The memory system includes a memory column access circuit. The memory system also includes a memory array. The memory array includes a first metal layer and a second metal layer different from the first metal layer, and the second metal layer includes a plurality of flying bit lines each coupled to the memory column access circuit. The memory system also includes a first memory sub-bank including a plurality of first memory row circuits each including a plurality of first memory bit cell circuits respectively disposed in each of the plurality of first memory column circuits. The first memory sub-bank also includes a plurality of first bit lines disposed in the first metal layer and respectively coupled to the first memory column circuits and the memory column access circuit among the plurality of first memory column circuits. The memory array also includes a second memory sub-bank including a plurality of second memory row circuits each including a plurality of second memory bit cell circuits respectively disposed in each of the plurality of second memory column circuits. The second memory sub-bank also includes a plurality of second bit lines respectively disposed in the first metal layer and respectively coupled to the second memory column circuits among the plurality of second memory column circuits. The memory array also includes a first jumper row circuit including a plurality of first jumper cell circuits respectively coupled to a second bit line among the plurality of second bit lines in the second memory column circuit and a first flying bit line among the plurality of first flying bit lines in the second metal layer in the second memory column circuit among the plurality of second memory column circuits in the first metal layer.

[0007] Those skilled in the art will understand the scope of the present disclosure and its further aspects upon reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. The accompanying drawings incorporated herein and constituting a part of this specification illustrate some aspects of the present disclosure and are useful for explaining the principles of the present disclosure together with the description.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

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DETAILED DESCRIPTION OF THE INVENTION

[0009] Exemplary aspects disclosed herein include a memory array that utilizes flying bit lines to increase an effective bit line length and support higher performance and increased memory density. Related methods are also disclosed. In an exemplary aspect, to increase the density of the memory array rather than providing the memory capacity of one memory sub-bank, the memory array includes a first memory sub-bank and one or more second memory sub-banks. In one example, the first memory sub-bank is physically closer to the support-side access circuitry than the second memory sub-bank. The first memory sub-bank includes a first bit line for each of its first memory column circuits. The first bit line couples a first memory bit cell in each of the first memory column circuits within the first memory sub-bank to an access circuit (e.g., a column multiplexer circuit, a read sense circuit). To avoid the need to extend the length of the first bit line coupled to the second memory sub-bank, which could increase access latency, the second memory sub-bank includes a separate second bit line. In this way, each memory sub-bank has dedicated first and second bit lines that couple their respective memory bit cells to the access circuit. The second bit line of the second memory sub-bank can substantially "fly" independently of the first bit line of the first memory sub-bank, and the second bit line is independently coupled to the access circuit. The first bit line of the first memory sub-bank does not need to be extended to provide a bit line for the second memory sub-bank. In this way, the memory density can be increased without incurring the cost of increased access latency due to high bit line capacitance, high dynamic energy consumption, and / or violation of manufacturing design rules that could limit the memory density. The memory density can also be increased based on savings in high-latency accesses without sacrificing power consumption. Also, in another example, to avoid contention in the shared access circuitry by having the first and second memory sub-banks not share bit lines and share the access circuitry, the first and second memory sub-banks are not accessed simultaneously for memory operations.However, memory accesses to different memory sub-banks are managed to benefit from the increased memory density without the need to extend the bit line length of the first memory sub-bank.

[0010] In another example, it is desirable to avoid the need for the cell circuit of the first memory bit cell in the first memory sub-array to support a separate metal line path for the second bit line to extend therefrom towards the access circuit. In this regard, the cell circuit of the first memory bit cell of the memory row circuit of the first memory sub-bank adjacent to the second memory sub-bank is provided as a flying bit line cell circuit. The flying bit line cell circuit is a dedicated cell circuit that includes not only the first memory bit cell and the metal line for the first bit line, but also a jumper circuit. The jumper circuit extends the coupled second bit line to a different metal layer from an adjacent memory bit cell row in the second memory sub-bank. Then, the second bit line "flies over" the first memory sub-bank towards the access circuit and extends within this different metal layer. In this way, the flying bit line cell circuit facilitates extending the coupled second bit line of the second memory sub-bank to the access circuit without the second bit line being coupled to the first bit line of the first memory sub-bank (which could result in an extension of the length of the first bit line). Extending the length of the bit lines of the memory array can increase the latency of memory accesses to the memory array. Further, by providing the flying bit line, each first memory row circuit in the first memory sub-bank can avoid the need to support (which may violate design and manufacturing rules, for example) a separate metal line for the second metal line to pass through the first memory sub-bank to the access circuit.

[0011] In this regard, FIG. 1 is a diagram of an exemplary processor-based system 100 that includes a processor 102 and a memory system 108. As will be described in more detail below, the memory system 108 can include a memory array that includes flying bit lines that couple access circuitry to second bit lines within a second memory sub-bank, increasing the effective bit line length to support higher performance. Before discussing such an exemplary memory array, first, the exemplary processor-based system 100 and its components are discussed below.

[0012] Continuing to refer to FIG. 1, the processor 102 includes one or more respective CPUs 104(0) to 104(N), where "N" is a positive integer representing the number of CPUs included in the processor 102. The processor 102 may be packaged in an integrated circuit (IC) chip 106. The CPUs 104(0) to 104(N) within the processor 102 are configured to issue memory requests (i.e., data read requests and data write requests) to the memory system 108. The memory system 108 includes a cache memory system 110 and a system memory 112. The system memory 112 is a memory that can be fully addressed by the physical address (PA) space of the processor-based system 100. For example, the system memory 112 may be a dynamic random access memory (DRAM) provided in separate DRAM chips. The cache memory system 110 within the memory system 108 includes one or more cache memories 114(1) to 114(X), where "X" is a positive integer representing the number of cache memories included in the processor 102. The cache memories 114(1) to 114(X) may exist at different levels within the processor-based system 100 and are logically arranged between the CPUs 104(0) to 104(N) and the system memory 112. The memory controller 116 controls access to the system memory 112. For example, the CPUs 104(0) to 104(N) as requesting devices can issue a data request 118 to read data in response to processing a load instruction. The data request 118 includes the target address of the data to be read from the memory. Taking CPU 104(0) as an example, if the requested data is not in the private cache memory 114(1) which can be considered as a level 1 (L1) cache memory (i.e., a cache miss for the cache memory 114(1)), the private cache memory 114(1) sends the data request 118, via the interconnect bus 120 in this example, to a shared cache memory 114(X) which can be a level 3 (L3) cache memory shared by all of the CPUs 104(0) to 104(N).The requested data within the data request 118 is ultimately satisfied either in the cache memories 114(1) to 114(X) or, if not contained in any of the cache memories 114(1) to 114(X), in the system memory 112.

[0013] The cache memories 114(1) to 114(X) and / or the system memory 112 within the memory system 108 of FIG. 1 can employ a memory array including memory bit cells generally organized in a matrix structure to store data. A memory row including the memory bit cells of each column is accessed to read a data word from the memory or to write a data word thereto. The memory bit cells may be provided by memories of different technologies such as static random access memory (RAM) (SRAM) bit cells and DRAM. As another example, the system memory 112 may be implemented with multiple large-sized memory arrays using multiple memory banks to improve memory performance and power consumption. By providing multiple memory banks in the memory within the memory system 108, the memory capacity can be divided among different arrays that can be independently accessed by the CPUs 104(1) to 104(N). Also, providing separate memory banks in the memory system 108 means that the power consumption can be managed independently for each memory bank from the other memory banks. Thus, for example, if software or data is persistent in one part of the memory but not in another, these separate parts of the memory may be divided into separate memory banks, thereby saving power without affecting other parts that may be fully powered for memory access while each is separately powered down or put into an idle state.

[0014] FIG. 2 is an exemplary memory system 200 including a four-column multiplexed (CM4) memory array 202 that may be employed in any memory within the memory system 108 of FIG. 1 as an example. The memory array 202 of FIG. 2 does not include flying bit lines and is described to show a memory array 202 that does not employ flying bit lines.

[0015] In this regard, as shown in FIG. 2, the memory array 202 includes a first memory bank 204(1) and a second memory bank 204(2). The first memory sub-bank includes a plurality of first memory row circuits 206(0) to 206(X), each of which includes a plurality of first memory bit cell circuits 208(0) to 208(X). "X + 1" is the number of the memory row circuits 206(0) to 206(X). Each memory row circuit 206(0) to 206(X) includes each set of the memory bit cell circuits 208(0) to 208(X). The sets of the memory bit cell circuits 208(0) to 208(X) within each of the memory row circuits 206(0) to 206(X) in the first memory bank 204(1) are organized into memory column circuits 210(0) to 210(Y). Thus, each set of the memory bit cell circuits 208(0) to 208(X) includes "Y + 1" memory bit cells. The first memory bank 204(1) has interleaved memory column circuits 210(0) to 210(Y) configured to store interleaved data words A, B, C, D according to interleaved memory column circuits labeled A1, B1, C1, D1, ..., A4, B4, C4, D4. In this regard, the data words A1 to A4 are interleaved among the memory column circuits 210(0) to 210(Y) corresponding to the memory column circuits A1, A2, A3, A4. By interleaving the storage of data words within the memory array, the bit error rate (BER) can be reduced.

[0016] When the first memory bank 204(1) is accessed in response to a memory read operation, the word line WL1 is activated for the selected memory row circuits 206(0) to 206(X) according to the decoded memory address for the memory access operation. Next, a column selection CS is generated for a plurality of column multiplexer circuits 212(0) to 212(3) coupled to respective bit lines coupled to each of the memory bit cell circuits 208(0) to 208(X) in respective memory column circuits 210(0) to 210(Y) representing the interleaved bits from the selected memory row circuits 206(0) to 206(X). Each of the column multiplexer circuits 212(0) to 212(3) couples one of the coupled bit lines from its coupled memory column circuits 210(0) to 210(Y) and provides the corresponding bit to respective memory column access circuits 214(0) to 214(3) (e.g., sense amplifiers). In this way, the column multiplexer circuits 212(0) to 212(3) are controlled to multiplex the selected bits from the interleaved data words within the selected memory row circuits 206(0) to 206(X) to respective memory column access circuits 214(0) to 214(3). For example, in a memory read operation, when it is desired to select interleaved data words A1 to A4 from the selected memory row circuits 206(0) to 206(X), the column multiplexer circuits 212(0) to 212(3) are controlled by the column selection CS to multiplex the bits A1 to A4 on respective bit lines BL1 to BL4 from the selected memory row circuits 206(0) to 208(X) to respective memory column access circuits 214(0) to 214(3). Thus, in this example, the first memory bank 204(1) is configured in a 4-bit column multiplexing (CM4) arrangement.

[0017] The second memory bank 204(2) is configured in the same way as the first memory bank 204(1). As shown in FIG. 2, the second memory bank 204(2) is designed to store interleaved data words E, F, G, H according to interleaved memory column circuits labeled E1, F1, G1, H1, ..., E4, F4, G4, H4. The second memory bank 204(2) is also configured in a CM4 interleaved arrangement. Since the operation of the second memory bank 204(2) is the same as that of the first memory bank 204(1), no explanation will be given. Note that since the first and second memory banks 204(1), 204(2) are coupled to the shared memory column access circuits 214(0) to 214(3), only one of the first and second memory banks 204(1), 204(2) is accessed at a time.

[0018] There may be a case where it is desired to increase the memory capacity of the memory array 202 in FIG. 2 to increase the memory storage capacity. For example, one way to achieve this is to increase the number of memory row circuits. Thus, taking the first memory bank 204(1) as an example, the number of memory row circuits 206(0) to 206(Y) can be increased, for example, from 256 to 512 memory row circuits. However, increasing the number of memory row circuits 206(0) to 206(Y) will also extend the length of the corresponding bit lines (e.g., BL1 to BL4) that connect each of the memory bit cell circuits 208(0) to 208(X) in the corresponding memory column circuits 210(0) to 210(Y).

[0019] If the length of the bit lines BL in the memory banks 204(1) and 204(2) within the memory array 202 is extended, it may reduce the power, performance, and area (PPA) of the memory system 200. A memory with longer bit lines BL may have a larger access latency compared to a memory with shorter bit lines BL. This is because the bit lines coupled to the support-side access circuits (e.g., write driver circuits and read sense circuits) are extended in length to reach the enlarged area within the memory array. Thus, as an example, the overall memory access latency may increase by only the access time to the memory bit cell circuits 208(0) to 208(X) located in the memory row circuit 206(X) of the first memory bank 204(0) that is farthest from the support-side memory column access circuits 214(0) to 214(3). Also, increasing the length of the bit lines in the memory banks 204(1) and 204(4) increases the capacitance of each bit line and results in a larger access latency. Manufacturing design rules and the associated manufacturing process may also limit the overall length of the bit lines in the memory array 202 of the memory system 200, effectively limiting the density of the memory array 202 despite the trade-off of allowing an increase in access latency.

[0020] FIG. 3 is a memory system 300 in an exemplary CM4 interleaved arrangement similar to the memory system 200 of FIG. 2. However, as will be described later, the memory system 300 includes a memory array 302 with a higher memory density than the memory bank 204(2) of FIG. 2. In this regard, the memory array 302 of FIG. 3 includes a first memory sub-bank 304(1) with the memory density of the first memory bank 204(1) in the memory array 202 of FIG. 2. A memory bank is a local unit of memory storage (e.g., memory bit cells), and access for reading and writing is controlled by a memory controller. A memory bank includes a memory bit cell array and an access circuit (e.g., a write driver, a sense amplifier, a column multiplexer circuit, a charge circuit, and a write assist circuit) used to address the bit cell array for read and write operations. When memory is divided into multiple memory banks, the multiple memory banks typically share some common support-side access circuits, so usually only one memory bank can be accessed at a time to avoid data contention. A memory bank may be divided into multiple memory sub-banks. A memory sub-bank is a division of memory bit cells from a memory bank. Memory sub-banks within a memory bank share a common access circuit with another memory sub-bank within that memory bank. Thus, at a given time, only one memory sub-bank within a memory bank may be accessible.

[0021] Memory sub-bank 304(1) is coupled to column multiplexer circuits 312(0) to 312(3) and multiplexes data bits from the first memory sub-bank 304(1) to respective memory column access circuits 314(0) to 314(3). The memory column access circuits 314(0) to 314(3) are sense amplifier circuits in this example and can sense the memory state regarding signals on respective bit lines BL(1)(0) to BL(1)(Y) multiplexed from the memory state from respective column multiplexer circuits 312(0) to 312(3). However, the memory array 302 of FIG. 3 also includes a second memory sub-bank 304(2) that is also coupled to column multiplexer circuits 312(0) to 312(3) to multiplex data bits from bit lines BL(2)(0) to BL(2)(Y) from the second memory sub-bank 304(3) to respective memory column access circuits 314(0) to 314(3). Also, the memory column access circuits 314(0) to 314(3) can sense the memory state regarding signals on respective bit lines BL(2)(0) to BL(2)(Y) multiplexed from the memory state from respective column multiplexer circuits 312(0) to 312(3). In this way, the memory density of the memory array 302 having two memory sub-banks 304(1) and 304(2) sharing common column multiplexer circuits 312(0) to 312(3) and memory column access circuits 314(0) to 314(3) is increased. However, even if the second memory sub-bank 304(2) is added, it is desirable that the length of the bit lines of the first memory sub-bank 304(1) does not increase.

[0022] In this regard, as shown in FIG. 3, the first inner memory sub-bank 304(1) is arranged closer to the column multiplexer circuits 312(0) to 312(3) and the memory column access circuits 314(0) to 314(3) than the second outer memory sub-bank 304(2). The inner memory sub-bank 304(1) includes X + 1 memory row circuits 306(0) to 306(X), each including a plurality of memory bit cell circuits 308(0)(0) to 308(X)(Y). For example, the memory row circuit 306(0) includes Y + 1 memory bit cell circuits 308(0)(0) to 308(0)(Y). The memory row circuit 306(X) includes Y memory bit cell circuits 308(X)(0) to 308(X)(Y). As a non-limiting example, the memory bit cell circuits 308(0)(0) to 308(X)(Y) may be static random access memory (SRAM) bit cells employing 6 transistors (6-T) or more transistor counts. As another example, the memory bit cell circuits 308(0)(0) to 308(X)(Y) can also be dynamic random access memory (DRAM) bit cells. The arrangement of the memory bit cell circuits 308(0)(0) to 308(X)(Y) is such that one memory bit cell circuit 308()(0) to 308()(Y) from each of the memory row circuits 306(0) to 306(X) is arranged in the same respective memory column circuits 310(0) to 310(Y). In FIG. 2, only the memory column circuits 310(0), 310(Y) are labeled. For example, the inner memory sub-bank 304(1) may be provided with 256 memory column circuits 310(0) to 310(255).

[0023] Continuing to refer to FIG. 3, the inner memory sub-bank 304(1) includes Y first bit lines BL(1)(0) to BL(1)(Y) respectively coupled to the memory bit cell circuits 308(0)(0) to 308(X)(Y) within each of the memory row circuits 306(0) to 306(X). The first bit lines BL(1)(0) to BL(1)(Y) can be precharged to write data to the memory bit cell circuits 308(0)(0) to 308(X)(Y) of the selected memory row circuits 306(0) to 306(Y) under the control of the activation of the word line WL by the memory driver circuit 318 for the selected memory row circuits 306(0) to 306(X) according to the decoded memory address 316. Although only one WL is shown in FIG. 3, it should be noted that in each of the memory row circuits 306(0) to 306(X), a separate WL is provided for each of the memory row circuits 306(0) to 306(X) coupled to the respective memory bit cell circuits 308(0)(0) to 308(X)(Y). Only one of the WLs for a given memory row circuits 306(0) to 306(X) is activated to select the memory row circuits 306(0) to 306(X) for a memory access operation. The memory bit cell circuits 308(0)(0) to 308(X)(Y) of the selected memory row circuits 306(0) to 306(X) can also assert data on the respective bit lines BL(1)(0) to BL(1)(Y) for the memory read operation provided by the column multiplexer circuits 312(0) to 312(3) and the memory column access circuits 314(0) to 314(3).

[0024] As described above, in order to increase the memory density of the memory array 302, a second, outer memory sub-bank 304(2) is also included in the memory system 300. The outer memory sub-bank 304(2) is arranged at a location farther from the column multiplexer circuits 312(0) to 312(3) and the memory column access circuits 314(0) to 314(3) than the inner memory sub-bank 304(1). Similar to the inner memory sub-bank 304(1), the outer memory sub-bank 304(2) includes X + 1 memory row circuits 326(0) to 326(X), each including a plurality of memory bit cell circuits 328(0)(0) to 328(X)(Y). For example, the memory row circuit 326(0) includes Y + 1 memory bit cell circuits 328(0)(0) to 328(0)(Y). The memory row circuit 326(X) includes Y memory bit cell circuits 328(X)(0) to 328(X)(Y). As a non-limiting example, the memory bit cell circuits 328(0)(0) to 328(X)(Y) may be SRAM bit cells employing 6 transistors (6-T) or more transistor counts. As another example, the memory bit cell circuits 328(0)(0) to 328(X)(Y) can also be DRAM bit cells. The arrangement of the memory bit cell circuits 328(0)(0) to 328(X)(Y) is such that one memory bit cell circuit 328()(0) to 328()(Y) from each of the memory row circuits 326(0) to 326(X) is arranged in each of the same memory column circuits 330(0) to 330(Y). In FIG. 3, only the memory column circuits 330(0), 330(Y) are labeled. For example, the outer memory sub-bank 304(2) may be provided with 256 memory column circuits 330(0) to 330(255).

[0025] Continuing to refer to FIG. 3, the outer memory sub-bank 304(2) also includes Y second bit lines BL(2)(0) to BL(2)(Y) respectively coupled to the memory bit cell circuits 328(0)(0) to 328(X)(Y) within each of the memory row circuits 326(0) to 326(X). The second bit lines BL(2)(0) to BL(2)(Y) can be precharged to write data to the memory bit cell circuits 328(0)(0) to 328(X)(Y) of the selected memory row circuits 326(0) to 326(Y) controlled by the activation of the word line WL by the memory driver circuit 318 for the selected memory row circuits 326(0) to 326(X) according to the decoded memory address 316. Note that in each of the memory row circuits 326(0) to 326(X), a separate WL is provided for each of the memory row circuits 326(0) to 326(X) coupled to the respective memory bit cell circuits 328(0)(0) to 328(X)(Y). Only one of the WLs of the given memory row circuits 326(0) to 326(X) in the outer memory sub-bank 304(2) and the memory row circuits 306(0) to 306(X) in the inner memory sub-bank 304(1) is activated to select either the memory row circuits 326(0) to 326(X) or the memory row circuits 306(0) to 306(X) for a memory access operation. The memory bit cell circuits 328(0)(0) to 328(X)(Y) of the selected memory row circuits 326(0) to 326(X) can also assert data to the respective bit lines BL(2)(0) to BL(2)(Y) for a memory read operation provided by the column multiplexer circuits 312(0) to 312(3) and the memory column access circuits 314(0) to 314(3).

[0026] The first and second memory sub-banks 304(1), 304(2) are designed to store interleaved data words A, B, C, D according to an interleaved memory column circuit labeled A1, B1, C1, D1, ..., A4, B4, C4, D4. Therefore, the memory array 302 is also configured in a CM4 interleaved arrangement. Thus, in this example, there are four columns of multiplexer circuits 312(0) to 312(3) to support the CM4 interleaved arrangement. The number of column multiplexer circuits 312(0) to 312(3) can be two or more to match the interleaving scheme.

[0027] When the inner memory sub-bank 304(1) and the outer memory sub-bank 304(2) are accessed in response to a memory read operation, the word line WL is activated for the selected memory row circuits 306(0) to 306(X), 326(0) to 326(X) according to the decoded memory address 316 for the memory access operation. The column selection CS1 is generated for each column multiplexer circuit 312(0) to 312(3) coupled to the respective first and second bit lines BL(1)(0) to BL(1)(Y), BL(2)(0) to BL(2)(Y) that are coupled to the respective memory bit cell circuits 308(0)(0) to 308(0)(Y), 328(0)(0) to 328(0)(Y) within the respective memory column circuits 310(0) to 310(Y), 330(0) to 330(Y) representing the interleaved bits from the selected memory row circuits 306(0) to 306(X), 326(0) to 326(X). Each column multiplexer circuit 312(0) to 312(3) couples one of the coupled first and second bit lines BL(1)(0) to BL(1)(Y), BL(2)(0) to BL(2)(Y) from the coupled memory column circuits 310(0) to 310(Y), 330(0) to 330(Y) to the respective multiplexed outputs 320(0) to 320(3) to provide the corresponding bits to the respective memory column access circuits 314(0) to 314(3) (e.g., sense amplifiers). In this way, the column multiplexer circuits 312(0) to 312(3) are controlled to multiplex the selected bits from the interleaved data words within the selected memory row circuits 306(0) to 306(X), 326(0) to 326(X) according to the respective memory column access circuits 314(0) to 314(3). The memory column access circuits 314(0) to 314(3) are configured to provide the bits of the data output word 324 on the respective column outputs 322(0) to 322(3) for the memory read operation.

[0028] For example, in a memory read operation, when it is desired to select interleaved data words A1 to A4 from the selected memory row circuits 306(0) to 306(X), the column multiplexer circuits 312(0) to 312(3) are controlled by a column selection CS1 and select bits A1 to A4 on respective first bit lines BL(1)(0), BL(1)(3), BL(1)(7), BL(1)(11) from the selected memory row circuits 306(0) to 306(X) and multiplex them onto respective multiplexed outputs 320(0) to 302(3) to respective memory column access circuits 314(0) to 314(3). The memory column access circuits 314(0) to 314(3) are configured to provide signals indicating the read bits on the first bit lines BL(1)(0), BL(1)(3), BL(1)(7), BL(1)(11) as data output word 324 onto respective column outputs 322(0) to 322(3).

[0029] As shown in FIG. 3 and as described above, the first and second bit lines BL(1)(0) to BL(1)(Y), BL(2)(0) to BL(2)(Y) are provided for each of the memory column circuits 310(0) to 310(Y), 330(0) to 330(Y) of the respective memory sub-banks 304(1), 304(2). The length of the first bit lines BL(1)(0) to BL(1)(Y) can be extended to provide bit lines for each of the memory column circuits 330(0) to 330(Y) of the outer memory sub-bank 304(2). For example, the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 304(1) can extend within or above the first metal layer (e.g., M0 or M2) within the memory bit cell circuits 308(0)(0) to 308(X)(Y). Extending the length of the first bit lines BL(1)(0) to BL(1)(Y) increases the capacitance of the first bit lines BL(1)(0) to BL(1)(Y), thereby undesirably degrading the memory performance with respect to the memory array 302.

[0030] Therefore, in order to avoid the need to lengthen the first bit lines BL(1)(0) to BL(1)(Y) of the inner memory sub-bank 304(1) to provide bit lines for the outer memory sub-bank 304(2), the second bit lines BL(2)(0) to BL(2)(Y) for the outer memory sub-bank 304(2) in the memory system 300 of FIG. 3 are provided as separate bit lines. The second bit lines BL(2)(0) to BL(2)(Y) for the outer memory sub-bank 304(2) are separate bit lines and are coupled to their respective column multiplexer circuits 312(0) to 312(3) separately from the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 304(1). However, a path must be provided between the second bit lines BL(2)(0) to BL(2)(Y) for the outer memory sub-bank 304(2) and the column multiplexer circuits 312(0) to 312(3). The memory bit cell circuits 308(0)(0) to 308(X)(Y) can be redesigned to accommodate the coupling of the second bit lines BL(2)(0) to BL(2)(Y) within an additional metal wire routing path in the first metal layer that houses the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 304(1), and this coupling extends through the inner memory sub-bank 304(2) alongside BL(1)(0) to BL(1)(Y) to the column multiplexer circuits 312(0) to 312(3). However, manufacturing limitations may prevent changing the cell design of all the memory bit cell circuits 308(0)(0) to 308(X)(Y) to accommodate the coupling of the first bit lines BL(1)(0) to BL(1)(Y) to the first metal layer and providing an additional metal wire routing path for the second bit lines BL(2)(0) to BL(2)(Y) alongside the first bit lines BL(1)(0) to BL(1)(Y), or it may be undesirable to do so.

[0031] In this regard, as shown in FIG. 3, in order to avoid the need to extend the first bit lines BL(1)(0) to BL(1)(Y) of the inner memory sub-bank 304(1) long enough to reach the outer memory sub-bank 304(2), jumper cell circuits 332(0) to 332(Y) are provided. In this example, as the jumper cell circuits 332(0) to 332(Y), the outermost memory bit cell circuits 308(X)(0) to 308(X)(Y) adjacent to the outer memory sub-bank 304(2) are provided. The jumper cell circuits 332(0) to 332(Y) are each coupled to the second bit lines BL(2)(0) to BL(2)(Y) for the outer memory sub-bank 304(2) and are also each coupled to the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 304(1). The jumper cell circuits 332(0) to 332(Y) each include respective metal interconnections 334(0) to 334(Y) that couple the respective second bit lines BL(2)(0) to BL(2)(Y) for the outer memory sub-bank 304(2) to the respective flying bit lines FBL(0) to FBL(Y). In this example, the metal interconnections 334(0) to 334(Y) of each of the jumper cell circuits 332(0) to 332(2) couple each of the second bit lines BL(2)(0) to BL(2)(Y) of the first metal layer for the outer memory sub-bank 304(2) to the respective flying bit lines FBL(0) to FBL(Y) of the second metal layer ML2 (e.g., M4). For example, the second metal layer ML2 may be disposed in a metal layer higher than the first metal layer ML1 in which the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 304(1) are disposed. In this way, the flying bit lines FBL(0) to FBL(Y) can be coupled to the respective column multiplexer circuits 312(1) to 312(3) by "jumping over" the first metal layer ML1 in which the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 304(1) are disposed vertically.

[0032] To further illustrate an exemplary detail of wiring the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 304(1) and the flying bit lines FBL(0) to FBL(Y) coupled to the outer memory sub-bank 304(2) in separate metal layers, FIGS. 4A and 4B are provided. FIG. 4A is a top view of an exemplary layout of a portion of the first lower metal layer ML1 of the memory array 302 of FIG. 3. FIG. 4A shows the metal lines of four first bit lines BL(1)(0) to BL(1)(3) of the inner memory sub-bank 304(1) and four second bit lines BL(2)(0) to BL(2)(3) of the outer memory sub-bank 304(2) in the first metal layer ML1. FIG. 4B is a top view of an exemplary layout of a portion of the second upper metal layer ML2 of the memory array 302 of FIG. 3. FIG. 4B shows the connection of the second bit lines BL(2)(0) to BL(2)(3) of the outer memory sub-bank 304(2) and the metal lines of the flying bit lines BLY(0) to BL(Y) wired to the column multiplexer circuits 312(1) to 312(3) in the second metal layer ML2.

[0033] In this regard, as shown in FIG. 4A, the first bit lines BL(1)(0) to BL(1)(3) of the inner memory sub-bank 304(1) extend in the Y-axis direction within their respective metal tracks MT0 to MT3 in the first metal layer ML1 toward the column multiplexer circuit 312(0). The second bit lines BL(2)(0) to BL(2)(3) of the outer memory sub-bank 304(2) also extend in the Y-axis direction within their respective metal tracks MT0 to MT3 in the first metal layer ML1. As shown in FIG. 4A, the second bit lines BL(2)(0) to BL(2)(3) are coupled to their respective jumper cell circuits 332(0) to 332(Y) as part of the inner memory sub-bank 304(1). In this example, the jumper cell circuits 332(0) to 332(Y) are directly adjacent to the second memory sub-bank 304(2), but this is not required. The jumper cell circuits 332(0) to 332(Y) have respective metal interconnections 334(0) to 334(3) coupled to the second bit lines BL(2)(0) to BL(2)(3). The second bit lines BL(2)(0) to BL(2)(3) do not extend further in the first metal layer ML1 toward the column multiplexer circuit 312(0). Instead, as shown in FIG. 4B, the metal interconnections 334(0) to 334(3) extend to the second metal layer ML2 (via vias, metal lines, etc.) and are coupled to the flying bit lines FBL(0) to FLB(3). The second metal layer ML2 includes metal tracks MT0 to MT5 extending in the Y-axis direction. The flying bit lines FBL(0) to FBL(3) extending in the Y-axis direction are provided as metal lines disposed in the respective metal tracks MT0, MT1, MT4, MT5 of the first metal layer ML1 to extend to and be coupled to the column multiplexer circuit 312(0).

[0034] Therefore, in this example, the flying bit lines FBL(0) to FBL(3) of the second metal layer ML2 extend (i.e., fly over) over the first bit lines BL(1)(0) to BL(1)(Y) in the first metal layer ML1. The flying bit lines FBL(0) to FBL(3) at least partially overlap the first bit lines BL(1)(0) to BL(1)(Y) in the vertical Z-axis direction.

[0035] Note that the flying bit lines FBL(0) to FBL(Y) in the memory system 300 of FIG. 3 can be wired in other ways than those shown in FIGS. 4A and 4B. For example, as shown in the exemplary layout of the memory system 300 of FIG. 5, the flying bit lines FBL(0) to FBL(Y) can be wired to return toward the outer memory row circuit 326(X) in the outer memory sub-bank 304(2) in a third metal layer ML3 that can be between the first and second metal layers ML1 and ML2. Then, the flying bit lines FBL(0) to FBL(Y) can be coupled to the metal lines of the second metal layer ML2 and wired to the column multiplexer circuits 312(0) to 312(Y).

[0036] FIG. 6 is another exemplary memory system 600 that includes a memory array 602 similar to the memory system 300 of FIG. 3. However, in the memory system 600 of FIG. 6, two additional memory sub-banks, an inner memory sub-bank 604(1) and an outer memory sub-bank 604(2), are provided to further increase the size of the memory array 602. Since inner and outer memory sub-banks 304(1), 304(2) are provided that are coupled to respective column multiplexer circuits 312(0)-312(3) and memory column access circuits 314(0)-314(3), no further description will be made. Also, in this example, as will be described later, the memory array 602 is configured in an 8-column multiplexing (CM8) arrangement such that one of the memory sub-banks 304(1), 304(2) and one of the memory sub-banks 604(1), 604(2) are accessed, for example, to read memory word A, and thus requires two word lines WL1, WL2 to be activated. Also, in this example, as will be described later, similar to the inner memory sub-bank 304(1), the inner memory sub-bank 604(1) is coupled to the second bit lines BL(4)(0)-BL(4)(Y) of the outer memory sub-bank 604(2) and also to respective jumper cell circuits 632(0)-632(Y) that are coupled to respective column multiplexer circuits 612(0)-612(3) that are also coupled to the shared memory column access circuits 314(0)-314(3) and to respective flying bit lines SFBL(0)-SFBL(Y).

[0037] Referring to FIG. 6, the inner memory sub-bank 604(1) is arranged closer to the column multiplexer circuits 612(0) to 612(3) and the memory column access circuits 314(0) to 314(3) than the outer memory sub-bank 604(2). The inner memory sub-bank 604(1) includes X + 1 memory row circuits 606(0) to 606(X), each including a plurality of memory bit cell circuits 608(0)(0) to 608(X)(Y). The memory row circuit 306(X) includes Y memory bit cell circuits 308(X)(0) to 308(X)(Y). As a non-limiting example, the memory bit cell circuits 608(0)(0) to 608(X)(Y) may be static random access memory (SRAM) bit cells employing 6 transistors (6-T) or more transistor counts. As another example, the memory bit cell circuits 608(0)(0) to 608(X)(Y) can be dynamic random access memory (DRAM) bit cells. The arrangement of the memory bit cell circuits 608(0)(0) to 608(X)(Y) is such that one memory bit cell circuit 608()(0) to 608()(Y) from each memory row circuit 606(0) to 606(X) is arranged in each of the same memory column circuits 610(0) to 610(Y). In FIG. 6, only the memory column circuits 610(0) and 610(Y) are labeled. For example, the inner memory sub-bank 604(1) may be provided with 256 memory column circuits 610(0) to 610(255).

[0038] Continuing to refer to FIG. 6, the inner memory sub-bank 604(1) includes Y first bit lines BL(3)(0) to BL(3)(Y) respectively coupled to the memory bit cell circuits 608(0)(0) to 608(X)(Y) within each of the memory row circuits 606(0) to 606(X). The first bit lines BL(3)(0) to BL(3)(Y) can be precharged to write data to the memory bit cell circuits 608(0)(0) to 608(X)(Y) of the selected memory row circuits 606(0) to 606(Y) controlled by activation of the word line WL2 for the selected memory row circuits 606(0) to 606(X) according to the decoded memory address 316. Note that in each of the memory row circuits 606(0) to 606(X), a separate WL is provided for each of the memory row circuits 606(0) to 606(X) coupled to the respective memory bit cell circuits 608(0)(0) to 608(X)(Y). Only one of the WLs for a given memory row circuit 606(0) to 606(X) within the outer memory sub-bank 604(2) is activated to select the memory row circuits 606(0) to 606(X) for a memory access operation. The memory bit cell circuits 608(0)(0) to 608(X)(Y) of the selected memory row circuits 606(0) to 606(X) can also assert data on the respective bit lines BL(3)(0) to BL(3)(Y) for a memory read operation provided by the column multiplexer circuits 612(0) to 612(3) and the memory column access circuits 314(0) to 314(3).

[0039] The outer memory sub-bank 604(2) is arranged at a location farther from the column multiplexer circuits 612(0) to 612(3) and the memory column access circuits 314(0) to 314(3) than the inner memory sub-bank 604(1). Similar to the inner memory sub-bank 604(1), the outer memory sub-bank 604(2) has X + 1 memory row circuits 626(0) to 626(X), each including a plurality of memory bit cell circuits 628(0)(0) to 628(X)(Y). As a non-limiting example, the memory bit cell circuits 628(0)(0) to 628(X)(Y) may be SRAM bit cells employing 6 transistors (6-T) or more transistor counts. As another example, the memory bit cell circuits 628(0)(0) to 628(X)(Y) can also be DRAM bit cells. The organization of the memory bit cell circuits 628(0)(0) to 628(X)(Y) is such that one memory bit cell circuit 628()(0) to 628()(Y) from each memory row circuit 626(0) to 626(X) is arranged in the same respective memory column circuits 630(0) to 630(Y). In FIG. 2, only the memory column circuits 630(0), 630(Y) are labeled. For example, the outer memory sub-bank 604(2) may be provided with 256 memory column circuits 630(0) to 630(255).

[0040] Continuing to refer to FIG. 6, the outer memory sub-bank 604(2) also includes Y second bit lines BL(4)(0) to BL(4)(Y) respectively coupled to the memory bit cell circuits 628(0)(0) to 628(X)(Y) within each of the memory row circuits 626(0) to 626(X). The second bit lines BL(4)(0) to BL(4)(Y) can be precharged to write data to the memory bit cell circuits 628(0)(0) to 628(X)(Y) of the selected memory row circuits 626(0) to 626(Y) controlled by activation of the word line WL2 for the selected memory row circuits 626(0) to 626(X) according to the decoded memory address 316. Note that within each of the memory row circuits 626(0) to 626(X), a separate WL is provided for each of the memory row circuits 626(0) to 626(X) coupled to the respective memory bit cell circuits 628(0)(0) to 628(X)(Y). Only one of the WLs of the given memory row circuits 626(0) to 626(X) within the outer memory sub-bank 604(2) and the memory row circuits 606(0) to 606(X) within the inner memory sub-bank 604(1) is activated to select either the memory row circuits 626(0) to 626(X) or the memory row circuits 606(0) to 606(X) for a memory access operation. The memory bit cell circuits 628(0)(0) to 628(X)(Y) of the selected memory row circuits 626(0) to 626(X) can also assert data to the respective bit lines BL(4)(0) to BL(4)(Y) for a memory read operation provided by the column multiplexer circuits 612(0) to 612(3) and the memory column access circuits 314(0) to 314(3).

[0041] Memory sub-banks 304(1), 304(2), 604(1), 604(2) are designed to store interleaved data words A, B, C, D, E, F, G, H according to an interleaved memory column circuit labeled A1, B1, C1, D1, E1, F1, G1, H1, ..., A4, B4, C4, D4, E4, F4, G4, H4. Therefore, memory array 602 is also configured in a CM8 interleaved arrangement. Thus, in this example, there are eight columns of multiplexer circuits 312(0) to 312(3), 612(0) to 612(3) to support the CM8 interleaved arrangement. The number of column multiplexer circuits 312(0) to 312(3), 612(0) to 612(3) can be two or more to match the interleaving scheme.

[0042] When the inner memory sub-bank 604(1) and the outer memory sub-bank 604(2) are accessed in response to a memory read operation, the word line WL is activated for the selected memory row circuits 606(0) to 606(X), 626(0) to 626(X) according to the decoded memory address 316 for the memory access operation. The column selection CS2 is generated for each column multiplexer circuit 612(0) to 612(3) coupled to the first and second bit lines BL(1)(0) to BL(1)(Y), BL(2)(0) to BL(2)(Y) respectively, which are coupled to the respective memory bit cell circuits 608(0)(0) to 608(0)(Y), 628(0)(0) to 628(0)(Y) within each memory column circuit 610(0) to 610(Y), 630(0) to 630(Y) representing the interleaved bits from the selected memory row circuits 606(0) to 606(X), 626(0) to 626(X). Each column multiplexer circuit 612(0) to 612(3) couples one of the coupled first and second bit lines BL(1)(0) to BL(1)(Y), BL(2)(0) to BL(2)(Y) from the respective coupled memory column circuits 610(0) to 610(Y), 630(0) to 630(Y) to the respective multiplexed outputs 620(0) to 620(3) to provide the corresponding bits to the respective memory column access circuits 314(0) to 314(3) (e.g., sense amplifiers). In this way, the column multiplexer circuits 612(0) to 612(3) are controlled to multiplex the selected bits from the interleaved data words within the selected memory row circuits 606(0) to 606(X), 626(0) to 626(X) according to the respective memory column access circuits 314(0) to 314(3). The memory column access circuits 314(0) to 314(3) are configured to provide the bits of the data output word 324 on the respective column outputs 322(0) to 322(3) for the memory read operation (see FIG. 3).

[0043] For example, in a memory read operation, if it is desired to select interleaved data words A1 to A4 from the memory array 602, two memory read operations are performed. First, in a first operation for selecting the desired memory row circuits 306(0) to 306(X), 326(0) to 326(X), the first word line WL1 is activated. The column multiplexer circuits 312(0), 312(2) are controlled by the column select CS1 and, according to the activated word line WL1, multiplex the bits A1, A3 on the respective first bit lines BL(1)(0), BL(1)(7) from the selected memory row circuits 306(0) to 306(X) onto the respective multiplexed outputs 320(0), 320(2) to the respective memory column access circuits 314(0), 314(2). The memory column access circuits 314(0), 314(2) are configured to provide signals indicating the read bits on the first bit lines BL(1)(0), BL(1)(2) for A1, A3 on the respective column outputs 322(0), 322(2) as part of the data output word 324. Next, in a second access operation, the second word line WL2 is activated to select the desired memory row circuits 606(0) to 606(X), 626(0) to 626(X). The column multiplexer circuits 612(0), 612(3) are controlled by the column select CS2 and, according to the activated word line WL2, multiplex the bits A2, A4 on the respective first bit lines BL(3)(1), BL(3)(3) from the selected memory row circuits 606(0) to 606(X) onto the respective multiplexed outputs 620(1), 620(3) to the respective memory column access circuits 314(1), 314(3). The memory column access circuits 314(1), 314(3) are configured to provide signals indicating the read bits on the first bit lines BL(3)(4), BL(3)(11) for A1, A3 as the data output word 324 on the respective column outputs 622(0), 622(2).

[0044] In a memory read access, by activating each of the word lines WL1 and WL2, all the memory bit cell circuits in the selected memory row circuit are activated, and it should be noted that the data from each bit line is coupled to each of the column multiplexer circuits 312(0) to 312(3), 612(0) to 612(3). That is, only one of the word lines WL1 and WL2 is activated at a time so that the memory column access circuits 314(1) and 314(3) can be shared. Activating two separate word lines WL1 and WL2 for the memory read operation to the memory array 602 activates twice as many memory bit cell circuits as activating only one word line for the memory operation as in the memory system 300 of FIG. 3. Nevertheless, in this example, the memory density of the memory array 602 in FIG. 6 is twice that of the memory array 302 in FIG. 3. Therefore, the power consumption normalized per density in the memory array 602 in FIG. 6 remains substantially the same as that of the memory array 302 in FIG. 3.

[0045] Continuing to refer to FIG. 6, the first and second bit lines BL(3)(0) to BL(3)(Y), BL(4)(0) to BL(4)(Y) are provided for each of the memory column circuits 610(0) to 610(Y), 630(0) to 630(Y) of the respective memory sub-banks 604(1), 604(2). The length of the first bit lines BL(3)(0) to BL(3)(Y) can be extended to provide bit lines for each of the memory column circuits 630(0) to 630(Y) of the outer memory sub-bank 604(2). For example, the first bit lines BL(1)(0) to BL(1)(Y) for the inner memory sub-bank 604(1) can extend within or above the first metal layer (e.g., M0 or M2) in the memory bit cell circuits 608(0)(0) to 608(X)(Y). Extending the length of the first bit lines BL(3)(0) to BL(3)(Y) increases the capacitance of the first bit lines BL(3)(0) to BL(3)(Y), thus undesirably degrading the memory performance with respect to the memory array 602.

[0046] Therefore, in order to avoid the need to lengthen the first bit lines BL(3)(0) to BL(3)(Y) of the inner memory sub-bank 604(1) to provide bit lines for the outer memory sub-bank 604(2), the second bit lines BL(4)(0) to BL(4)(Y) for the outer memory sub-bank 604(2) in the memory system 600 of FIG. 6 are provided as separate bit lines. The second bit lines BL(4)(0) to BL(4)(Y) for the outer memory sub-bank 604(2) are separate bit lines and are coupled to their respective column multiplexer circuits 612(0) to 612(3) separately from the first bit lines BL(3)(0) to BL(3)(Y) for the inner memory sub-bank 604(1). However, a path must be provided between the second bit lines BL(4)(0) to BL(4)(Y) for the outer memory sub-bank 604(2) and the column multiplexer circuits 612(0) to 612(3). The memory bit cell circuits 608(0)(0) to 608(X)(Y) can be redesigned to accommodate the connection of the second bit lines BL(4)(0) to BL(4)(Y) within an additional metal wire routing path in the first metal layer that houses the first bit lines BL(3)(0) to BL(3)(Y) for the inner memory sub-bank 604(1), and this connection extends through the inner memory sub-bank 604(2) alongside the BL(3)(0) to BL(3)(Y) to the column multiplexer circuits 612(0) to 612(3). However, manufacturing limitations may prevent or may be undesirable to change the cell design of all the memory bit cell circuits 608(0)(0) to 608(X)(Y) to accommodate the connection of the first bit lines BL(3)(0) to BL(3)(Y) to the first metal layer and provide an additional metal wire routing path for the second bit lines BL(4)(0) to BL(4)(Y) alongside the first bit lines BL(3)(0) to BL(3)(Y).

[0047] In this regard, as shown in FIG. 6, in order to avoid the need to extend the first bit lines BL(3)(0) to BL(3)(Y) of the inner memory sub-bank 604(1) long enough to reach the outer memory sub-bank 604(2), jumper cell circuits 632(0) to 632(Y) which may be similar to the jumper cell circuits 332(0) to 332(Y) of the memory array 302 in FIG. 3 are provided. In this example, as the jumper cell circuits 632(0) to 632(Y), the outermost memory bit cell circuits 608(X)(0) to 608(X)(Y) adjacent to the outer memory sub-bank 604(2) are provided. The jumper cell circuits 632(0) to 632(Y) are each coupled to the second bit lines BL(4)(0) to BL(4)(Y) for the outer memory sub-bank 604(2) and are also each coupled to the first bit lines BL(3)(0) to BL(3)(Y) for the inner memory sub-bank 604(1). The jumper cell circuits 632(0) to 632(Y) each include respective metal interconnections 634(0) to 634(Y) that couple the respective second bit lines BL(4)(0) to BL(4)(Y) for the outer memory sub-bank 604(2) to the respective second flying bit lines SFBL(0) to SFBL(Y). In this example, the metal interconnections 634(0) to 634(Y) of the respective jumper bit cell circuits 632(0) to 632(2) couple the respective second bit lines BL(4)(0) to BL(4)(Y) of the first metal layer for the outer memory sub-bank 604(2) to the respective flying bit lines SFBL(0) to SFBL(Y) of the second metal layer ML2 (e.g., ML4). For example, the second metal layer ML2 may be disposed in a metal layer higher than the first metal layer ML1 in which the first bit lines BL(3)(0) to BL(3)(Y) for the inner memory sub-bank 304(1) are disposed. In this way, the second flying bit lines SFBL(0) to SFBL(Y) can be coupled to the respective column multiplexer circuits 612(1) to 612(3) by "jumping over" the first metal layer ML1 in which the first bit lines BL(3)(0) to BL(3)(Y) for the inner memory sub-bank 604(1) are disposed vertically.

[0048] The examples of the metal layer layouts in FIGS. 4A to 5 can also be applied to the first bit lines BL(3)(0) to BL(3)(Y), the second bit lines BL(4)(0) to BL(4)(Y), and the second flying bit lines SFBL(0) to SFBL(Y) in the inner and outer memory sub-banks 604(1), 604(2) of the memory array 602 in FIG. 6.

[0049] A memory array including first and second memory sub-banks to increase memory density, as described herein including the memory arrays 302 and 602 in FIGS. 3 and 6, which increases the effective bit line length to support higher performance without extending the length of the first bit lines in the first memory sub-array, and further includes flying bit lines that couple access circuits to the second bit lines in the second memory sub-bank, may be provided as other column multiplexing arrangements including, but not limited to, CM16, CM32, etc.

[0050] FIG. 7 is a block diagram of an exemplary processor-based system 700 including a processor 702 configured to execute computer instructions for execution. Note that the processor-based system also includes a memory system 704 including one or more memory arrays including first and second memory sub-banks to increase memory density, and the memory arrays further include flying bit lines that couple access circuits to the second bit lines in the second memory sub-bank to increase the effective bit line length to support higher performance without extending the length of the first bit lines in the first memory sub-array. The memory system 704 includes, in this example, an instruction cache 706, a data cache 708, and a system memory 710. Any memory in the memory system 704 in FIG. 7 may include, by way of non-limiting example, the memory arrays 302, 602 in FIGS. 3 and 6.

[0051] Continuing to refer to FIG. 7, the processor-based system 700 may be one or more circuits included in an electronic substrate card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or other device, and may represent, for example, a server or a user's computer. The processor 702 represents one or more general-purpose processing circuits such as a microprocessor, a central processing unit. The processor 702 includes an instruction processing circuit 709 configured to execute processing logic in computer instructions for performing the operations and steps discussed herein. The processor 702 also includes an instruction cache 706 for temporary high-speed access memory storage of instructions. Instructions fetched or prefetched from memory such as system memory 710 via the system bus 712 are stored in the instruction cache 706. The processor 702 also includes a data cache 708 for temporary high-speed access memory storage of data from system memory 710 via the system bus 712.

[0052] The processor 702 and the system memory 710 are coupled to a system bus 712 and can interconnect the peripheral devices included in the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information via the system bus 712. For example, the processor 702 can communicate a bus transaction request to a memory controller 714 within the system memory 710 as an example of a slave device. Although not shown in FIG. 7, a plurality of system buses 712 may be provided where each system bus constitutes a different fabric. In this example, the memory controller 714 is configured to provide a memory access request to a memory array 716 within the system memory 710. The memory array 716 is composed of an array of memory bit cells for storing data. The system memory 710 may be, by way of non-limiting example, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0053] Other devices may be connected to the system bus 712. As shown in FIG. 7, these devices may include, by way of example, a system memory 710, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input device 718 can include any type of input device including, but not limited to, input keys, switches, voice processors, and the like. The output device 720 can include any type of output device including, but not limited to, voice, video, other visual indicators, and the like. The modem 722 can be any device configured to enable data exchange with a network 726. The network 726 can be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH (trademark) network, and the Internet. The modem 722 can be configured to support any desired type of communication protocol. The processor 702 can also be configured to access the display controller 724 via the system bus 712 and control the information transmitted to one or more displays 728. The display 728 can include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, and the like.

[0054] When executed by a processor such as processor 702 in the processor-based system 700 of FIG. 7, a set of instructions 730 may be included that locally generate, within the memory bank, a GBL clock signal and a local WL clock signal that control the timing of respective GBL control paths and WL paths within a selected memory row circuit in the memory bank. The instructions 730 may be stored in the system memory 710, the processor 702, and / or the instruction cache 706 as an example of a non-transitory computer-readable medium 732. The instructions 730 may also exist, in whole or at least in part, within the system memory 710 and / or within the processor 702 during their execution. The instructions 730 may further be transmitted or received via the network 726 via the modem 722 such that the network 726 includes the non-transitory computer-readable medium 732, or as another example, the input device 718.

[0055] Although the non-transitory computer-readable medium 732 is shown as being a single medium in the exemplary embodiment, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processing device and that causes a processing device to execute any one or more of the methodologies of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be taken to include, without limitation, solid-state memory, optical media, and magnetic media.

[0056] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied as machine-executable instructions, such instructions being used to cause a general-purpose processor or a special-purpose processor programmed with the instructions to execute the steps. Alternatively, the steps may be executed by a combination of hardware and software.

[0057] The embodiments disclosed herein may include a computer program product, or software, that includes a machine-readable medium (or computer-readable medium) storing instructions that can be used to program a computer system (or other electronic device) to execute a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0058] Unless stated otherwise specifically, and as will be apparent from the foregoing discussion, throughout this specification, discussions using terms such as "processing," "computing," "determining," "displaying," etc., refer to actions and processes of a computer system, or similar electronic computing device, that manipulate and transform data represented as physical (electronic) quantities within the registers of the computer system into other data similarly represented as physical quantities within the memory, registers, or other such information storage devices, transmission devices, or display devices of the computer system.

[0059] The algorithms and displays presented in this specification are not inherently related to any particular computer or other device. A variety of systems may be used with programs in accordance with the teachings of this specification, or it may prove convenient to construct more specialized devices to perform the required method steps. The structures required for these various systems will be apparent from the above description. Additionally, the embodiments described in this specification are not described with reference to any particular programming language. It should be appreciated that various programming languages may be used to implement the teachings of the embodiments as described herein.

[0060] Those skilled in the art will further understand that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or another computer-readable medium, executed by a processor or other processing device, or any combination thereof. The components of the distributed antenna system described herein may, by way of example, be implemented in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any desired type of information. For purposes of clearly explaining this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above from the perspective of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present embodiments.

[0061] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. The processor may be a microprocessor, but in the alternative, may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0062] The embodiments disclosed herein may be embodied as hardware and instructions stored on hardware, for example, in RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An illustrative memory medium is coupled to the processor such that the processor can read information from, and write information to, the memory medium. In the alternative, the memory medium may be integral to the processor. The processor and the memory medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the memory medium may reside as discrete components in a remote station, base station, or server.

[0063] Note that the operation steps described in any of the exemplary embodiments herein are described for purposes of providing examples and discussion. The operations described can be performed in many different orders other than the order shown. Further, operations described as a single operation step may actually be executed in a plurality of different steps. Additionally, one or more operation steps discussed in the exemplary embodiments may be combined. Also, those skilled in the art will understand that information and signals can be represented using any of a variety of techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

[0064] Unless explicitly stated otherwise, it is never intended that any method described herein be construed as requiring that its steps be performed in a particular order. Thus, when a method claim does not actually recite an order to be followed by its steps, or when the steps are not specifically stated in the claim or the specification as being limited to a particular order, it is never intended that a particular order be inferred.

[0065] It will be apparent to those skilled in the art that various modifications and variations can be made to the invention without departing from the spirit and scope of the invention. Since modifications, combinations, sub - combinations, and variations of the disclosed embodiments incorporating the spirit and substance of the invention may occur to those skilled in the art, the invention should be construed to include all within the scope of the appended claims and their equivalents.

Claims

1. Memory column access circuit, Memory array and A memory system including, the memory array is The first metal layer, A second metal layer, different from the first metal layer, comprising a plurality of flying bit lines each coupled to the memory column access circuit, The first memory subbank, A plurality of first memory row circuits, each of which is arranged in each of the plurality of first memory column circuits, each containing a plurality of first memory bit cell circuits, A plurality of first bit lines are arranged in the first metal layer and are coupled to the first memory column circuit and the memory column access circuit, respectively, among the plurality of first memory column circuits. The first memory subbank includes, The second memory subbank, Multiple second memory row circuits, each containing multiple second memory bit cell circuits, are arranged in each of the multiple second memory column circuits. A plurality of second bit lines are arranged in the first metal layer and coupled to the second memory array circuit among the plurality of second memory array circuits. A second memory subbank including, A first jumper row circuit including a plurality of first jumper cell circuits, each coupled to a second bit line among a plurality of second bit lines in a second memory row circuit among a plurality of second memory row circuits in the first metal layer, and to a first flying bit line among a plurality of first flying bit lines in the second metal layer. A memory system that includes this.

2. A memory system according to claim 1, wherein each of the plurality of first jumper cell circuits includes a metal interconnect that connects the second bit line of the first metal layer to the first flying bit line of the second metal layer.

3. A memory system according to claim 1, The first metal layer includes a plurality of first metal tracks, each containing a first bit line from the plurality of first bit lines, The second metal layer includes a first flying bit line among the plurality of first flying bit lines and a plurality of second metal tracks that each overlap at least partially perpendicular to the first metal tracks among the plurality of first metal tracks. Memory system.

4. A memory system according to claim 1, wherein the first memory row circuit among the plurality of first memory row circuits includes the plurality of first jumper cell circuits.

5. A memory system according to claim 1, wherein the first memory row circuit includes the plurality of first jumper cell circuits and is adjacent to the second memory subbank.

6. A memory system according to claim 1, wherein the plurality of first flying bit lines extend vertically over each of the plurality of first memory row circuits and each of the plurality of second memory row circuits.

7. A memory system according to claim 1, The plurality of first memory row circuits include at least 256 memory row circuits, The plurality of second memory row circuits include at least 256 memory row circuits. Memory system.

8. A memory system according to claim 1, A plurality of first word lines (WLs) connected to each of the first memory row circuits among the plurality of first memory row circuits, A plurality of second WLs, each coupled to a second memory row circuit among the plurality of second memory row circuits, Memory driver circuits coupled to the plurality of first WLs and the plurality of second WLs The memory driver circuit further includes, Receiving a memory access request that includes a memory address, In response to the memory access request, the memory address is The first memory row circuit among the plurality of first memory row circuits coupled to the first WL to be activated, The second memory row circuit among the plurality of second memory row circuits coupled to the second WL that is activated and In response to each of the above, the first WL of the plurality of first WLs and the second WL of the plurality of second WLs are activated. Configured to perform, Memory system.

9. The memory system according to claim 8, The aforementioned memory column access circuit is A plurality of column multiplexer circuits, each coupled to a unique set of a plurality of first bit lines and each coupled to X unique sets of a plurality of first flying bit lines, wherein X is a positive integer of 2 or more, and each of the plurality of column multiplexer circuits is configured to multiplex the bit lines from the coupled sets of first bit lines and the coupled sets of first flying bit lines to the corresponding multiplexed outputs. Includes, The memory driver circuit responds to the memory access request, Each of the aforementioned column multiplexer circuits is further configured to multiplex the bit lines among its combined X first bit lines and its combined X first flying bit lines to its corresponding multiplexed output. Memory system.

10. A memory system according to claim 9, further comprising a plurality of sense amplifiers each coupled to the multiplexed output of a column multiplexer circuit among the plurality of column multiplexer circuits.

11. A memory system according to claim 9, wherein X is equal to 4.

12. A memory system according to claim 9, wherein X is equal to 8.

13. A memory system according to claim 1, wherein the memory array is A third metal layer, A fourth metal layer distinct from the third metal layer, the fourth metal layer including a plurality of second flying bit lines each coupled to the memory column access circuit, It is the third memory subbank, Multiple third memory row circuits, each containing multiple third memory bit cell circuits, are arranged in each of the multiple third memory column circuits. A plurality of third bit lines are arranged in the third metal layer and are coupled to the third memory column circuit and the memory column access circuit, respectively, among the plurality of third memory column circuits. A third memory subbank including, It is the fourth memory subbank, Multiple fourth memory row circuits, each containing multiple fourth memory bit cell circuits, are arranged in each of the multiple fourth memory column circuits. A plurality of fourth bit lines are arranged in the fourth metal layer and coupled to each of the fourth memory array circuits among the plurality of fourth memory array circuits. A fourth memory subbank including, The third memory row circuit among the plurality of third memory row circuits, The third metal layer includes a plurality of second jumper cell circuits, each coupled to a fourth bit line among a plurality of fourth memory array circuits in the fourth memory array circuit and a first flying bit line among a plurality of first flying bit lines in the fourth metal layer. The third memory row circuit and A memory system that further includes this.

14. A memory system according to claim 13, The first metal layer includes the third metal layer, The second metal layer includes the fourth metal layer. Memory system.

15. A memory system according to claim 13, The third metal layer includes a plurality of third metal tracks, each containing a third bit line from the plurality of third bit lines, The fourth metal layer includes a second flying bit line among the plurality of second flying bit lines and a plurality of fourth metal tracks that each at least partially overlap the third metal track among the plurality of third metal tracks in a perpendicular direction. Memory system.

16. A memory system according to claim 13, A plurality of first word lines (WLs) connected to each of the first memory row circuits among the plurality of first memory row circuits, A plurality of second WLs, each coupled to a second memory row circuit among the plurality of second memory row circuits, A plurality of third WLs, each coupled to a third memory row circuit among the plurality of third memory row circuits, A plurality of fourth WLs, each coupled to a fourth memory row circuit among the plurality of fourth memory row circuits, Memory driver circuits coupled to the plurality of first WLs, the plurality of second WLs, the plurality of third WLs, and the plurality of fourth WLs The memory driver circuit further includes, Receiving a memory access request that includes a memory address corresponding to one of the first memory subbank and the second memory subbank, In response to the memory access request to the first memory subbank, The aforementioned memory address is The first memory row circuit among the plurality of first memory row circuits coupled to the first WL to be activated, The second memory row circuit among the plurality of second memory row circuits coupled to the second WL that is activated and In response to each of the following, activate one of the first WLs among the plurality of first WLs and the second WL among the plurality of second WLs, In response to the memory access request to the second memory subbank, The aforementioned memory address is The third memory row circuit among the plurality of third memory row circuits coupled to the third WL to be activated, The fourth memory row circuit among the plurality of fourth memory row circuits coupled to the fourth WL to be activated In response to each of the above, the third WL of the plurality of third WLs and the fourth WL of the plurality of fourth WLs are activated. Configured to perform, Memory system.

17. A memory system according to claim 16, The aforementioned memory column access circuit is A plurality of first column multiplexer circuits, each coupled to a unique set of a plurality of first bit lines and each coupled to X unique sets of a plurality of first flying bit lines, wherein X is a positive integer of 2 or more, and each of the plurality of first column multiplexer circuits is configured to multiplex the first bit lines from the coupled sets of first bit lines and the coupled sets of first flying bit lines to the corresponding first multiplexed outputs, A plurality of second column multiplexer circuits, each coupled to a unique set of a plurality of third bit lines and each coupled to X unique sets of a plurality of second flying bit lines, wherein X is a positive integer of 2 or more, and each of the plurality of second column multiplexer circuits is configured to multiplex the second bit lines from the coupled sets of third bit lines and the coupled sets of second flying bit lines to the corresponding second multiplexed outputs. Includes, The aforementioned memory driver circuit is In response to the memory access request to the first memory subbank, Each of the plurality of first column multiplexer circuits is configured to multiplex the first bit lines of the X coupled first flying bit lines into its corresponding first multiplexed output. In response to the memory access request to the second memory subbank, Each of the plurality of second column multiplexer circuits is configured to multiplex the second bit line of the X coupled third bit lines and the X coupled second flying bit lines into its corresponding second multiplexed output. Further configured to perform, Memory system.

18. A memory system according to claim 17, further comprising a plurality of sense amplifiers coupled to a first multiplexed output of a first column multiplexer circuit among a plurality of first column multiplexer circuits and a second multiplexed output of a second column multiplexer circuit among a plurality of second column multiplexer circuits.

19. A memory system according to claim 17, wherein X is equal to 8.

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