Circuit board and semiconductor package including the same

Abstract

The circuit board according to the embodiment includes an insulating layer, a first circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer and including a first open portion that overlaps the first circuit pattern perpendicularly. The first protective layer includes a first region that includes the first open portion and has a first thickness, and a second region that does not include the first open portion and has a second thickness greater than the first thickness. The first thickness of the first region is smaller than a third thickness of the first circuit pattern. The inner surface of the first region that constitutes the first open portion includes a first inner surface that is in direct contact with the outer surface of the first circuit pattern and a second inner surface that is separated from the outer surface of the first circuit pattern.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the same.

Background Art

[0002] As miniaturization, weight reduction, and integration of electronic components are accelerating, the circuit line width is being miniaturized. In particular, as the design rules of semiconductor chips are integrated on a nanometer scale, the circuit line width of the package substrate or circuit board on which the semiconductor chips are mounted is being miniaturized to several micrometers or less.

[0003] Various methods have been proposed to increase the circuit integration density of circuit boards (i.e., to miniaturize the circuit line width). For example, for the purpose of preventing loss of the circuit line width in the etching step for forming a pattern after copper plating, the semi-additive process (SAP) method, the modified semi-additive process (MSAP), etc. have been proposed.

[0004] Subsequently, an embeded trace substrate (ETS) method of embedding a copper foil in an insulating layer has been used in the industry to realize a finer circuit pattern. The ETS method is a type of manufacturing in which the copper foil circuit is embedded in the insulating layer instead of being formed to protrude from the surface of the insulating layer, so there is no circuit loss due to etching, which is advantageous for miniaturizing the circuit pitch.

[0005] On the other hand, on the circuit board as described above, a chip is mounted or coupled to the main board of an external device to form a package substrate.

[0006] For this purpose, a groove is formed in the protective layer disposed on the outermost periphery of the circuit board, and solder balls for mounting the chip and connecting the main board are disposed in the groove. Further, the package substrate can be manufactured by forming a molding layer that mounts a chip on the solder ball or molds the main board after connecting it.

[0007] However, according to the prior art, by disposing solder balls on the circuit board, an intermetallic contact (IMC) layer is formed between the solder balls and the metal layer to which the solder balls are connected. At this time, in the manufacturing process of the package substrate, when injecting the molding liquid for forming the molding layer, the damage caused by the injection pressure of the molding liquid is transmitted to the IMC layer, resulting in cracks in the IMC layer. When cracks occur in the IMC layer, a reliability problem occurs in that the chip and the main board are separated from the circuit board due to the separation of the IMC layer.

[0008] Therefore, there is a need for a structure that can minimize the damage transmitted to the IMC layer by the injection pressure of the molding liquid.

Summary of the Invention

Problems to be Solved by the Invention

[0009] Embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0010] Also, embodiments provide a circuit board that can improve the reliability of the IMC layer and a semiconductor package including the same.

[0011] Also, embodiments provide a circuit board that can increase the contact area between the connection part and the pad and a semiconductor package including the same.

[0012] In the proposed embodiment, the technical problem to be solved is not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those with ordinary knowledge in the technical field to which the proposed embodiment belongs from the following description.

Means for Solving the Problem

[0013] The circuit board according to the embodiment includes an insulating layer, a first circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer and including a first open portion overlapping perpendicularly with the first circuit pattern. The first protective layer includes a first region including the first open portion and having a first thickness, and a second region not including the first open portion and having a second thickness greater than the first thickness. The first thickness of the first region is smaller than a third thickness of the first circuit pattern. The inner surface of the first region constituting the first open portion includes a first inner surface in direct contact with the outer surface of the first circuit pattern and a second inner surface spaced apart from the outer surface of the first circuit pattern.

[0014] In addition, the second inner surface of the first region is connected to the first inner surface of the first region and has an inclination corresponding to the inclination of the first inner surface.

[0015] In addition, the second thickness of the second region is greater than the third thickness of the first circuit pattern.

[0016] In addition, the first circuit pattern includes a region where the width decreases toward the upper surface of the first circuit pattern, and the second inner surface of the first region is spaced apart from the outer surface of the region where the width of the first circuit pattern decreases.

[0017] In addition, the first thickness of the first region satisfies the range of 20% to 90% of the third thickness of the first circuit pattern.

[0018] Further, the first circuit pattern is disposed on the upper surface of the insulating layer and includes a first part whose outer surface contacts the first inner surface of the first region, and a second part disposed on the first part and whose outer surface does not contact the first protective layer. The second part includes a region having a width smaller than the width of the first part.

[0019] Also, the width of the first open portion corresponds to the width of the first part.

[0020] Also, the first part has a fourth thickness in the range of 20% to 90% of the first thickness of the first region.

[0021] Also, the outer surface of the second part has a linear inclination in which the width gradually decreases toward the upper surface of the second part.

[0022] Also, the outer surface of the second part has a curved inclination with a specific curvature in which the width decreases toward the upper surface of the second part.

[0023] Also, the width of the portion of the second part closest to the first part is smaller than the width of the portion of the first part closest to the second part, and the first circuit pattern includes a stepped portion provided between the first part and the second part.

[0024] Also, the outer surface of the second part has an inclination in which the width decreases toward the upper surface of the second part or an inclination in which there is no change in width toward the upper surface of the second part.

[0025] Also, the second part includes a first sub-part having an outer surface with a first inclination and a second sub-part having an outer surface with a second inclination different from the first inclination.

[0026] Also, the first protective layer is provided at the boundary between the first region and the second region and includes a recess recessed in the inner direction of the first protective layer.

[0027] Further, the circuit board further includes a surface treatment layer disposed on the first circuit board, and the lowermost end of the surface treatment layer is located lower than the upper surface of the first region.

[0028] Further, at least a part of the surface treatment layer contacts the second inner surface of the first region.

[0029] Further, the surface roughness of the outer surface of the first part is different from the surface roughness of the outer surface of the second part.

[0030] On the other hand, the semiconductor package according to the embodiment includes an insulating layer, a first circuit pattern disposed on the insulating layer, a first protective layer disposed on the insulating layer and including a first open portion overlapping the first circuit pattern perpendicularly, a first connection portion disposed on the first circuit pattern overlapping the first open portion of the first protective layer perpendicularly, and a semiconductor element mounted on the first connection portion. The first protective layer includes a first region including the first open portion and having a first thickness, and a second region not including the first open portion and having a second thickness greater than the first thickness. The first thickness of the first region is smaller than the third thickness of the first circuit pattern. A clevis is formed between the inner surface of the first region constituting the first open portion and the outer surface of the first circuit pattern, and at least a part of the first connection portion is disposed in the clevis.

[0031] Further, the first protective layer is provided at the boundary between the first region and the second region, includes a recess recessed in the inner direction of the first protective layer, and at least a part of the first connection portion is disposed in the recess.

Advantages of the Invention

[0032] The embodiment includes an insulating layer, a first circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer and including a first open portion overlapping the first circuit pattern perpendicularly.

[0033] That is, the first protective layer includes the first open portion and a first region adjacent to the first open portion. The first protective layer also includes a second region adjacent to the first region. At this time, the height of the upper surface of the first region is lower than the height of the upper surface of the second region. Preferably, the height of the upper surface of the first region is lower than the height of the upper surface of the first circuit pattern. Through this, the embodiment arranges a first protective layer including a first region having the first open portion in a region where the protective layer is not arranged due to the exposure resolution of the protective layer and a second region. And the first region is arranged surrounding the first circuit pattern while including a first open portion having substantially the same width as the first circuit pattern.

[0034] Therefore, the embodiment can stably protect the first circuit pattern from damage caused by various stresses. Through this, the embodiment can improve the physical reliability and / or electrical reliability of the first circuit pattern.

[0035] At this time, a clevis may be formed between the inner surface of the first region of the first protective layer and the outer surface of the first circuit pattern.

[0036] Specifically, the inner surface of the first region includes a first inner surface that contacts the outer surface of the first circuit pattern and a second inner surface that is separated from the outer surface of the first circuit pattern through the clevis without contacting the outer surface of the first circuit pattern.

[0037] And the embodiment enables a surface treatment layer and / or solder to be arranged in the clevis. Through this, the embodiment can increase the distance between the metal bonding layer formed by the arrangement of the solder and the uppermost surface of the first protective layer. Therefore, the embodiment can dramatically reduce the possibility of crack generation in the metal bonding layer, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package.

[0038] Furthermore, the embodiments can increase the distance using the clevis without increasing the thickness of the first protective layer. Therefore, the embodiments can achieve slimming of the circuit board and the semiconductor package.

[0039] In addition, the outer surface of the first circuit pattern includes a first outer surface that contacts the outer surface of the first region of the first protective layer and a second outer surface that does not contact the first protective layer. And the surface roughness of the second outer surface may be greater than the surface roughness of the first outer surface. Through this, the embodiments can ensure the adhesion between the surface treatment layer disposed on the second outer surface and the first circuit pattern, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0040] Also, the embodiments adjust the thickness of the first region so that a recess recessed inward is formed at the boundary between the first region and the second region. And the recess can be filled with a connection part such as solder in the solder bonding process. And the connection part disposed in the recess can perform an anchor function, thereby improving the bonding force between the connection part and the first circuit pattern.

Brief Description of the Drawings

[0041]

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[0042] Hereinafter, with reference to the attached drawings, the embodiments disclosed in this specification will be described in detail. However, components that are the same or similar regardless of the reference numerals will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes "module" and "section" for the components used in the following description are given or mixed for the purpose of facilitating the preparation of the specification and do not have meanings or roles that distinguish them from each other. Also, in the description of the embodiments disclosed in this specification, if it is determined that a specific description of such known technology obstructs the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted. Also, the attached drawings are for the purpose of facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and it should be understood to include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0043] Terms including ordinal numbers such as first and second can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

[0044] When a component is referred to as being "connected" or "coupled" to another component, it should be understood that it may be directly "connected" or "coupled" to the other component, or there may be other components in between. On the other hand, when a component is referred to as being "directly connected" or "directly coupled" to another component, it should be understood that there are no other components in between.

[0045] Singular expressions include plural expressions unless the context clearly has a different meaning.

[0046] In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof in advance.

[0047] Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail as follows.

[0048] - Comparative Example -

[0049] Prior to the description of the embodiments, a comparative example compared with the circuit board of the embodiments of the present application will be described.

[0050] FIG. 1 is a diagram showing a circuit board according to a comparative example, and FIG. 2 is a diagram for explaining the reliability problem of the metal bonding layer IMC in the comparative example of FIG. 1.

[0051] Referring to FIG. 1, the circuit board according to the comparative example includes an insulating layer 10, a circuit pattern layer 20, a protective layer 30, a surface treatment layer 40, and solder 50.

[0052] The circuit board in the comparative example has a structure in which solder 50 is disposed on the circuit pattern layer 20 for attaching a chip (not shown) or an external board (not shown).

[0053] The circuit board of the comparative example includes an insulating layer 10. Further, the circuit board of the comparative example includes a circuit pattern layer 20 disposed on the insulating layer 10. The circuit pattern layer 20 includes pads and traces. The pads mean electrode patterns on which solder 50 is disposed for bonding with the chip or the external board among the circuit pattern layer. The traces can mean thin signal lines connecting a plurality of pads.

[0054] Also, the circuit board of the comparative example includes a protective layer 30 disposed on the insulating layer 10.

[0055] The protective layer 30 includes an opening. Specifically, the protective layer 30 partially exposes the upper surface of the pad where the solder 50 is disposed in the circuit pattern layer 20. For example, the opening of the protective layer 30 provides a space where the solder 50 is disposed.

[0056] A surface treatment layer 40 is disposed within the opening of the protective layer 30. The surface treatment layer 40 is disposed on the circuit pattern layer 20 that vertically overlaps the opening of the protective layer 30.

[0057] The surface treatment layer 40 can have a certain thickness.

[0058] On the other hand, the solder 50 is disposed while filling the opening of the protective layer 30 on the surface treatment layer 40. At this time, the surface treatment layer 40 and the solder 50 are made of different substances, and a metal bonding layer IMC is formed at the interface between the surface treatment layer 40 and the solder 50.

[0059] At this time, the upper surface of the protective layer 30 in the comparative example is located adjacent to the metal bonding layer IMC. At this time, the protective layer 30 contracts and expands due to thermal stress in the usage environment of the circuit board. Then, the contraction and expansion are transmitted to the metal bonding layer IMC along the upper surface of the protective layer 30 and the inner wall of the opening.

[0060] In addition, the circuit board performs a step of forming a molding layer (not shown) that bonds a chip or the main board of an external device onto the solder 50 and thereby molds the chip or the main board. At this time, the step of forming the molding layer is performed by injecting a molding liquid onto the protective layer 30. At this time, a certain pressure is applied to inject the molding liquid during the step of forming the molding layer, and the applied pressure is transmitted to the metal bonding layer IMC along the inner wall of the opening of the protective layer 30.

[0061] At this time, in the comparative example as described above, the upper surface of the protective layer 30 and the metal bonding layer IMC are adjacent to each other, and thus the generated stress and pressure are directly transmitted to the metal bonding layer IMC.

[0062] As shown in FIG. 2, when the stress or pressure is transmitted to the metal bonding layer IMC, cracks may occur in the metal bonding layer IMC due to the transmitted pressure. Further, when cracks occur in the metal bonding layer IMC, a problem of physical reliability occurs in that the solder 50 is separated from the surface treatment layer 40.

[0063] Also, when the solder 50 is separated from the surface treatment layer 40, the chips and the main board connected to the solder 50 are also separated from the circuit board, resulting in a problem with the reliability of the product.

[0064] Furthermore, the functions provided by the semiconductor elements arranged on the circuit board are increasing, and as a result, the number of semiconductor elements arranged on the circuit board or the number of terminals provided in the semiconductor elements is increasing.

[0065] Therefore, the circuit pattern layer is required to be miniaturized for mounting the semiconductor elements. However, even if the circuit pattern layer is miniaturized, there is a limit to the size of the openings that can be formed in the protective layer 30. Therefore, the size of the openings is determined by the exposure resolution of the protective layer 30. At this time, the minimum size of the openings that can generally be formed is at the 50 μm level.

[0066] As a result, there is a problem that it is difficult to miniaturize the pads connected to the semiconductor elements due to the limit of the minimum size of the openings.

[0067] Recently, the protective layer is not disposed on the pad connected to the semiconductor element, and through this, miniaturization of the pad is realized. However, traces disposed in regions where the protective layer is not disposed are not protected by the protective layer, thereby causing physical reliability and / or electrical reliability problems.

[0068] Accordingly, the embodiment is configured to solve the physical reliability problem of the circuit board of the comparative example. Specifically, the embodiment is configured to increase the distance between the upper surface of the protective layer and the metal bonding layer IMC without increasing the thickness of the circuit board. Specifically, in the embodiment, the distance between the inner walls of the opening of the protective layer connecting between the upper surface of the protective layer and the metal bonding layer IMC can be increased.

[0069] Through this, the embodiment can stably protect the metal bonding layer IMC from the generated stress and pressure, thereby improving the physical reliability of the metal bonding layer IMC. Through this, the embodiment is configured to improve the physical reliability of the metal bonding layer.

[0070] Furthermore, the embodiment forms a protective layer including an opening overlapping perpendicularly to the pad while miniaturizing the pad connected to the semiconductor element. Through this, the embodiment can stably protect the pads and traces disposed in the mounting region of the semiconductor element.

[0071] - Electronic Device -

[0072] Prior to the description of the embodiment, the electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a main board (not shown). The main board can be physically and / or electrically connected to various components. For example, the main board can be connected to the semiconductor package of the embodiment. Various semiconductor elements can be mounted on the semiconductor package.

[0073] The semiconductor device can include active devices and / or passive devices. The active device can be an integrated circuit (IC)-type semiconductor chip in which hundreds to millions or more devices are integrated in one chip. The semiconductor chip can be a logic chip, a memory chip, or the like. The logic chip can be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an AP chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of those listed above.

[0074] The memory chip can be a stacked memory such as HBM. Further, the memory chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0075] On the other hand, the product group to which the semiconductor package of the embodiment is applied can be, but is not limited to, any one of a Chip Scale Package (CSP), a Flip Chip-Chip Scale Package (FC-CSP), a Flip Chip Ball Grid Array (FC-BGA), a Package On Package (POP), and a System In Package (SIP).

[0076] In addition, the electronic device can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, Automotive, etc. However, it is not limited thereto, and it goes without saying that it can be any other electronic device that processes data in addition to these.

[0077] - Circuit board -

[0078] Hereinafter, the circuit board of the embodiment will be described.

[0079] A circuit board means a board before a semiconductor element or chip is mounted.

[0080] FIG. 3 is a cross-sectional view showing a circuit board according to an embodiment, FIG. 4 is a plan view showing a first circuit pattern provided on the circuit board of FIG. 3, FIG. 5 is a cross-sectional view showing a first open portion and a first circuit pattern of a first protective layer according to a first embodiment, FIG. 6 is a cross-sectional view showing a state in which a surface treatment layer is disposed on the first circuit pattern of FIG. 5, and FIG. 7 is a cross-sectional view showing a second open portion and a second circuit pattern of a first protective layer according to an embodiment.

[0081] Hereinafter, with reference to FIGS. 3 to 7, the circuit board according to the embodiment will be described.

[0082] The circuit board of the embodiment provides a mounting space capable of mounting at least one semiconductor element.

[0083] For example, the circuit board of the first embodiment can provide a mounting space for mounting one semiconductor element, and in contrast, can provide a plurality of mounting spaces for mounting two or more semiconductor elements.

[0084] Also, one logic chip can be mounted on the circuit board of the first embodiment. Also, at least two logic chips of different types can be mounted on the circuit board of the first embodiment. Also, at least one logic chip and at least one memory chip can be mounted on the circuit board of the first embodiment.

[0085] Referring to FIG. 3, the circuit board 100 of the first embodiment includes an insulating layer 110. The insulating layer 110 can have one or more layers. Preferably, the insulating layer 110 can have a multilayer structure. At this time, although the insulating layer 110 is shown as being composed of one layer in the drawing, it is not limited thereto. For example, the insulating layer 110 can include a plurality of insulating layers having a stacked structure in the vertical direction.

[0086] Hereinafter, the insulating layer 110 will be described by showing it as one layer.

[0087] The insulating layer 110 can be rigid or flexible.

[0088] As an example, the insulating layer 110 can include a prepreg. For example, the insulating layer 110 can be a prepreg in which glass fibers are impregnated with a resin. The resin can be an epoxy resin, but is not limited thereto.

[0089] Also, the insulating layer 110 can include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer 110 can include reinforced or ductile plastics such as polyimide PI (Polyimide), polyethylene terephthalate PET (polyethylene terephthalate), propylene glycol PPG (propylene glycol), polycarbonate (PC), etc. For example, the insulating layer 110 can include an optically isotropic film. For example, the insulating layer 110 can include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate PC (polycarbonate), or optically isotropic polymethyl methacrylate (PMMA), etc. For example, the insulating layer 110 can be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 can have a structure in which inorganic fillers such as silica or alumina are disposed in a thermosetting resin or a thermoplastic resin. For example, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc. can be used for the insulating layer 110. For example, the insulating layer 110 can include RCC (Resin coated copper).

[0090] The insulating layer 110 can have a thickness in the range of 10 μm to 60 μm. For example, when the insulating layer 110 includes a plurality of layers, the thickness of each of the plurality of layers can satisfy the range of 10 μm to 60 μm. Preferably, the insulating layer 110 can satisfy a thickness in the range of 15 μm to 55 μm. More preferably, the insulating layer 110 can satisfy a thickness in the range of 18 μm to 52 μm.

[0091] The thickness of the insulating layer 110 can mean the vertical distance between a plurality of circuit pattern layers arranged adjacent to each other in the thickness direction. For example, the thickness of the insulating layer 110 can mean the vertical distance between the first circuit pattern layer 120 and the second circuit pattern layer 130. For example, the thickness of the insulating layer 110 can mean the vertical distance between the lower surface of the first circuit pattern layer 120 and the upper surface of the second circuit pattern layer 130.

[0092] If the thickness of the insulating layer 110 is less than 10 μm, the warping characteristics of the circuit board 100 may deteriorate. For example, if the thickness of the insulating layer 110 is less than 10 μm, the first circuit pattern layer 120 and the second circuit pattern layer 130 disposed on the surface of the insulating layer 110 may not be stably protected, and problems with electrical reliability and / or physical reliability may occur thereby. Also, if the thickness of the insulating layer 110 is less than 10 μm, the processability in the process of forming the first circuit pattern layer 120 or the second circuit pattern layer 130 on the insulating layer 110 may deteriorate.

[0093] Also, if the thickness of the insulating layer 110 exceeds 60 μm, the overall thickness of the circuit board 100 increases, and the thickness of the semiconductor package can increase accordingly. Also, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to miniaturize the first circuit pattern layer 120 and / or the second circuit pattern layer 130. For example, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to form the width of the first circuit pattern layer 120 and / or the second circuit pattern layer 130 and the interval between adjacent patterns to be 12 μm or less, 10 μm or less, 8 μm or less, or 6 μm or less. And if it is difficult to miniaturize the first circuit pattern layer 120 and / or the second circuit pattern layer 130, the integration degree of the circuit decreases, and thereby the signal transmission distance increases and the signal transmission loss can increase.

[0094] The circuit board 100 of the first embodiment includes a circuit pattern layer disposed on the insulating layer 110.

[0095] For example, the circuit board 100 of the first embodiment includes a first circuit pattern layer 120 disposed on the upper surface of the insulating layer 110. Further, the circuit board 100 includes a second circuit pattern layer 130 disposed on the lower surface of the insulating layer 110.

[0096] The first circuit pattern layer 120 can be divided into a plurality of circuit patterns according to position or function.

[0097] For example, the first circuit pattern layer 120 can include a first circuit pattern 120-1 and a second circuit pattern 120-2. At least one of the first circuit pattern 120-1 and the second circuit pattern 120-2 can be disposed in the semiconductor element mounting region of the circuit board 100.

[0098] For example, at least one of the first circuit pattern 120-1 and the second circuit pattern 120-2 can include a mounting pad connected to a terminal of a semiconductor element.

[0099] Also, at least one of the first circuit pattern 120-1 and the second circuit pattern 120-2 can include a terminal pad coupled to an external substrate.

[0100] Also, at least one of the first circuit pattern 120-1 and the second circuit pattern 120-2 can include a terminal pad coupled to an interposer or a main board of an electronic device. At this time, the interposer can be an active interposer including semiconductor element functions. In contrast, the interposer can be a passive interposer that performs a signal relay function between a plurality of components.

[0101] On the other hand, the first circuit pattern 120-1 and the second circuit pattern 120-2 can be distinguished from each other by their widths. For example, the first circuit pattern 120-1 can have a width that is relatively smaller than the width of the second circuit pattern 120-2.

[0102] Preferably, the first circuit pattern 120-1 can include mounting pads connected to the terminals of the semiconductor element. Also, the second circuit pattern 120-2 can include terminal pads connected to an external substrate or the like. Therefore, the first circuit pattern 120-1 can be a fine pattern corresponding to the terminals of the semiconductor element.

[0103] At this time, recently, due to the increase in the functions provided by semiconductor elements, the number of terminals provided in the semiconductor element and the number of semiconductor elements mounted on the circuit board have been increasing.

[0104] Therefore, miniaturization of the first circuit pattern 120-1 of the first circuit pattern layer 120 is required. However, in the comparative example, due to the size limit of the open portion of the protective layer, undercut, and reliability problems of the metal bonding layer, there was a limit to miniaturizing the first circuit pattern 120-1 of the first circuit pattern layer 120. That is, when the first circuit pattern 120-1 is miniaturized, an open portion having a size corresponding to the width of the first circuit pattern 120-1 cannot be formed, or adjacent patterns may be connected to each other by solder due to the undercut, or the reliability of the metal bonding layer may further decrease.

[0105] That is, when the interval between a plurality of patterns of the first circuit pattern 120-1 decreases, the circuit integration density can be improved. However, when the interval between the plurality of patterns decreases, a problem may occur in that an open portion corresponding to the plurality of patterns cannot be formed in the first protective layer 150.

[0106] Also, when the width of the first circuit pattern 120-1 decreases or the interval between a plurality of patterns decreases, the bonding area of the metal bonding layer decreases, and thereby the physical reliability of the metal bonding layer may further decrease.

[0107] Therefore, in the embodiment, the first protective layer 150 includes an open portion, and the upper surface of the first protective layer 150 has a stepped structure. Through this, the embodiment maximally increases the distance between the uppermost surface of the first protective layer 150 and the first circuit pattern 120-1. Specifically, in order to improve the physical reliability of the metal bonding layer, the distance between the uppermost surface of the first protective layer 150 and the first circuit pattern 120-1 must be increased. For this purpose, the thickness of the first protective layer 150 can also be increased. However, when the thickness of the first protective layer 150 increases, it may be difficult to form an open portion having a size corresponding to the first circuit pattern 120-1 in the first protective layer 150. Furthermore, when the thickness of the first protective layer 150 increases, the thickness of the circuit board thereby increases, and the overall thickness of the semiconductor package thereby increases.

[0108] Accordingly, in the embodiment, without increasing the thickness of the first protective layer 150, the length of the inner wall of the open portion of the first protective layer 150 provided between the first protective layer 150 and the first circuit pattern 120-1 is increased.

[0109] This can be achieved by the shape of the open portion of the first protective layer 150 described below and the shape of the first circuit pattern 120-1 that vertically overlaps the open portion. This will be described in more detail below.

[0110] On the other hand, when the insulating layer 110 of the circuit board 100 includes a plurality of layers, the first circuit pattern layer 120 may be disposed on the upper surface of the insulating layer disposed on the uppermost side among the plurality of layers of the insulating layer 110, and the second circuit pattern layer 130 may be disposed on the lower surface of the insulating layer disposed on the lowermost side among the plurality of layers of the insulating layer 110. For example, the first circuit pattern layer 120 and the second circuit pattern layer 130 may indicate outer layer circuit pattern layers, but are not limited thereto.

[0111] On the other hand, when the insulating layer 110 includes a plurality of layers, additional inner layer circuit pattern layers may be disposed between the plurality of layers.

[0112] Referring to FIG. 4, the first circuit pattern 120-1 is disposed in a region where semiconductor elements such as logic chips are mounted. Accordingly, the first circuit pattern 120-1 can include a fine pattern. FIG. 4(a) is a plan view showing the first circuit pattern 120-1 in a state where the first protective layer 150 of the embodiment is removed, and FIG. 4(b) is a cross-sectional view taken along the A-A' direction of FIG. 4(a).

[0113] The first circuit pattern 120-1 includes pads 120-11 corresponding to terminals of semiconductor elements or pads of an interposer, and traces 120-12 connected to the pads 120-11.

[0114] The first circuit pattern 120-1 is required to be miniaturized. For example, the first circuit pattern 120-1 is connected to all terminals of semiconductor elements or all pads of an interposer within a limited space, and traces for connecting between them must be arranged. Accordingly, the first circuit pattern 120-1 can include a fine pattern.

[0115] Also, due to reasons such as 5G, the Internet of Things (IOT), increased image quality, and increased communication speed, the number of terminals in the first processor chip and the second processor chip is gradually increasing. Accordingly, although all functions cannot be provided by one semiconductor element, the number of terminals provided in one semiconductor element is increasing.

[0116] Accordingly, the first circuit pattern 120-1 may be required to be ultra-miniaturized.

[0117] The pads 120-11 of the first circuit pattern 120-1 correspond to terminals of semiconductor elements mounted on the circuit board. Accordingly, the number of the pads 120-11 corresponds to the number of terminals of semiconductor elements.

[0118] The pad 120-11 may have a width in a first horizontal direction and a width in a second horizontal direction perpendicular to the first horizontal direction that are different from each other. At this time, the width of the pad 120-11 in the separation direction from adjacent pads or traces may be smaller than the width in a direction perpendicular to the separation direction. And among the widths of the pad 120-11, the width in the separation direction has a great influence on the circuit integration density. The separation direction may mean the first horizontal direction.

[0119] That is, the pad 120-11 may have an elliptical shape in which the width in the first horizontal direction is smaller than the width in the second horizontal direction. However, the embodiments are not limited thereto. For example, the pad 120-11 may have a circular shape having the width in the first horizontal direction as a whole.

[0120] The width W1 of the pad 120-11 may be 3 μm to 30 μm. For example, the width W1 of the pad 120-11 may be 4 μm to 28 μm. For example, the width W1 of the pad 120-11 may be 5 μm to 25 μm.

[0121] If the width W1 of the pad 120-11 is smaller than 3 μm, it may be difficult to arrange the connection portion connected to the terminal of the semiconductor element. If the width W1 of the pad 120-11 is smaller than 3 μm, the connection reliability between the pad 120-11 and the semiconductor element may decrease. If the width W1 of the pad 120-11 is larger than 30 μm, it may be difficult to arrange all the pads connected to the semiconductor element within a limited space. If the width W1 of the pad 120-11 is larger than 30 μm, the size of the circuit board can increase. If the width W1 of the pad 120-11 is larger than 30 μm, the interval between adjacent patterns becomes narrow, and this may cause reliability problems such as circuit short circuits.

[0122] Further, the first circuit pattern 120-1 includes a trace 120-12 connected to the pad 120-11. The trace 120-12 can mean an elongated signal line connected to the pad 120-11. Also, when two semiconductor elements are mounted on the first circuit pattern 120-1, the trace 120-12 can include a signal line connecting between the two semiconductors.

[0123] Accordingly, the trace 120-12 can include a superfine pattern. For example, the line width W2 of the trace 120-12 can satisfy the range of 1 μm to 10 μm. For example, the line width W2 of the trace 120-12 can satisfy the range of 1.2 μm to 8 μm. For example, the line width W2 of the trace 120-12 can satisfy the range of 1.5 μm to 7 μm. When the line width W2 of the trace 120-12 is smaller than 1 μm, the resistance of the trace 120-12 increases, and it may be difficult to communicate normally with the semiconductor element. Also, when the line width W2 of the trace 120-12 is smaller than 1 μm, it may be difficult to apply a general circuit pattern manufacturing process. When the line width W2 of the trace 120-12 is smaller than 1 μm, a physical reliability problem may occur in which the trace 120-12 collapses due to stress generated by various factors. When the line width W2 of the trace 120-12 is larger than 10 μm, it may be difficult to arrange all signal lines connected to the terminals of the semiconductor element within a limited space. For example, when the line width W2 of the trace 120-12 is larger than 10 μm, it may be difficult to arrange all traces for connecting between a plurality of processor chips within a limited space. For example, when the line width W2 of the trace 120-12 is larger than 10 μm, the circuit integration degree may decrease.

[0124] On the one hand, the first circuit pattern 120-1 can be separated at a mutual fixed interval W3. The interval W3 can mean the separation interval between the pads 120-11 of the first circuit pattern 120-1. Also, the interval W3 can mean the separation interval between the traces of the first circuit pattern 120-1. Also, the interval W3 can mean the separation interval between the pads 120-11 and the traces 120-12 adjacent to each other of the first circuit pattern 120-1.

[0125] The interval W3 can have a range of 1 μm to 10 μm. The interval W3 can have a range of 1.2 μm to 8 μm. The interval W3 can have a range of 1.5 μm to 7 μm. If the interval W3 is smaller than 1 μm, there is a problem that the second traces and the second pads adjacent to each other are connected to each other and an electrical short circuit occurs. For example, if the interval W3 is larger than 10 μm, it may be difficult to arrange all the traces for connecting between a plurality of processor chips within a limited space.

[0126] The circuit board 100 of the first embodiment can include a through electrode 140. The through electrode 140 can penetrate the insulating layer 110. Preferably, the through electrode 140 can penetrate the insulating layer 110 so as to electrically connect between the first circuit pattern layer 120 and the second circuit pattern layer 130. At this time, when the circuit board 100 has a multi-layer structure, the through electrode 140 can electrically connect between the circuit pattern layers adjacent to each other and separated in the vertical direction.

[0127] On the one hand, the first circuit pattern layer 120 and the second circuit pattern layer 130 are wirings for transmitting electrical signals and can be formed of a metallic substance with high electrical conductivity. For this purpose, the first circuit pattern layer 120 and the second circuit pattern layer 130 can be formed of at least one metallic substance selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Also, the first circuit pattern layer 120 and the second circuit pattern layer 130 can be formed of a paste or a solder paste containing at least one metallic substance selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) which have excellent bonding force. Preferably, the first circuit pattern layer 120 and the second circuit pattern layer 130 can be formed of copper (Cu) which has high electrical conductivity and is relatively inexpensive.

[0128] The first circuit pattern layer 120 and the second circuit pattern layer 130 can be formed by an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), an SAP (Semi Additive Process), etc., which are normal circuit board manufacturing processes. Here, detailed descriptions are omitted.

[0129] The thickness T1 of the first circuit pattern layer 120 (see FIG. 5) can satisfy the range of 5 μm to 30 μm. Preferably, the thickness T1 of the first circuit pattern layer 120 can satisfy the range of 6 μm to 25 μm. More preferably, the thickness T1 of the first circuit pattern layer 120 can have a thickness in the range of 7 μm to 20 μm. The thickness T1 of the first circuit pattern layer 120 can mean the vertical distance from the lower surface to the upper surface of the first circuit pattern layer 120. At this time, when the upper surface or the lower surface of the first circuit pattern layer 120 has a step, the thickness T1 of the first circuit pattern layer 120 can mean the vertical distance from the lowermost end to the uppermost end of the first circuit pattern layer 120. However, the embodiments are not limited thereto. For example, the thickness T1 of the first circuit pattern layer 120 can also mean the average thickness in the entire region.

[0130] When the thickness T1 of the first circuit pattern layer 120 is less than 5 μm, the resistance of the circuit pattern may increase, and the signal transmission efficiency may decrease accordingly. For example, when the thickness T1 of the first circuit pattern layer 120 is less than 5 μm, the signal transmission loss can increase. For example, when the thickness T1 of the first circuit pattern layer 120 exceeds 30 μm, the line width of the first circuit pattern layer 120 may increase, and the circuit integration degree may decrease accordingly.

[0131] On the other hand, the thickness of the second circuit pattern layer 130 can correspond to the thickness T1 of the first circuit pattern layer 120.

[0132] The through electrode 140 can be formed by filling the inside of a through hole penetrating the insulating layer 110 with a conductive material.

[0133] The through-hole can be formed by any one of machining methods including mechanical, laser, and chemical machining. When the through-hole is formed by machining, methods such as milling, drill, and routing can be used. When the through-hole is formed by laser machining, UV or CO2 laser methods can be used. When the through-hole is formed by chemical machining, chemicals including minosilane and ketones can be used.

[0134] On the other hand, the circuit board 100 of the first embodiment can include a protective layer.

[0135] For example, the circuit board 100 can include the first protective layer 150 disposed on the insulating layer 110. For example, the circuit board 100 can include a second protective layer 160 disposed under the insulating layer 110.

[0136] The first protective layer 150 and the second protective layer 160 can be resist layers. Preferably, the first protective layer 150 and the second protective layer 160 can be solder resist layers containing organic polymer substances. As an example, the first protective layer 150 and the second protective layer 160 can contain epoxy acrylate-based resins. Specifically, the first protective layer 150 and the second protective layer 160 can contain resins, curing agents, pigments, solvents, fillers, additives, acrylic monomers, and the like.

[0137] The thickness of each of the first protective layer 150 and the second protective layer 160 may be greater than the thickness of each of the first circuit pattern layer 120 and the second circuit pattern layer 130.

[0138] In other words, the thickness of the first protective layer 150 may be greater than the thickness of the first circuit pattern layer. It may be greater than the thickness. Also, the thickness of the second protective layer 160 may be greater than the thickness of the second circuit pattern layer 130.

[0139] The thickness of the first protective layer 150 means the vertical distance from the lower surface to the upper surface of the first protective layer 150 in a region that does not include the open portion of the first protective layer 150. For example, the thickness of the first protective layer 150 can mean the thickness T4 (see FIG. 5) in the second region R2 (see FIG. 5) of the first protective layer 150.

[0140] The thickness T4 of the protective layer 150 can satisfy the range of 6.7 μm to 35.0 μm. Preferably, the thickness T1 of the first protective layer 150 can satisfy the range of 7.3 μm to 32 μm. More preferably, the thickness T1 of the first protective layer 150 can satisfy the range of 8.0 μm to 30 μm.

[0141] When the thickness of the first protective layer 150 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package can increase. Also, when the thickness of the first protective layer 150 is less than 6.7 μm, the first circuit pattern layer may not be stably protected, which may result in a decrease in electrical reliability or physical reliability.

[0142] Also, the second protective layer 160 can have a thickness corresponding to the thickness of the first protective layer 150, but is not limited thereto.

[0143] On the other hand, the first protective layer 150 includes at least one open portion. Also, the second protective layer 160 includes at least one open portion.

[0144] The first protective layer 150 can include a first open portion OP1. For example, the first protective layer 150 can include the first open portion OP1 that vertically overlaps the first circuit pattern 120-1.

[0145] Also, the first protective layer 150 can include a second open portion OP2. For example, the first protective layer 150 can include the second open portion OP2 that vertically overlaps the second circuit pattern 120-2.

[0146] Further, the second protective layer 160 may include at least one third open portion overlapping perpendicularly with the second circuit pattern layer 130.

[0147] And the first protective layer 150 may be divided into a plurality of regions.

[0148] The first protective layer 150 may include a first region R1 including the first open portion OP1. Further, the first protective layer 150 may include a second region R2 adjacent to the first region R1 and not including the first open portion OP1.

[0149] Also, the first protective layer 150 may include a third region R3 including the second open portion OP2. Further, the first protective layer 150 may include a fourth region R4 adjacent to the third region R3 and not including the second open portion OP2.

[0150] At this time, the second region R2 and the fourth region R4 are regions not including the first open portion OP1 and the second open portion OP2. And the second region R2 and the fourth region R4 of the first protective layer 150 may constitute one region connected to each other. Therefore, a part of the region of the first protective layer 150 may mean any one of the second region R2 and the fourth region R4, and differently, may also mean both the second region R2 and the fourth region R4.

[0151] Hereinafter, together with the first open portion OP1 and the second open portion OP2 formed in the first protective layer 150, the shapes of the first circuit pattern 120-1 and the second circuit pattern 120-2 will be specifically described.

[0152] Referring to FIG. 5, the first protective layer 150 includes the first open portion OP1.

[0153] The first open portion OP1 can correspond to the first circuit pattern 120-1. Specifically, the first protective layer 150 can include the first open portion OP1 that overlaps perpendicularly with the first circuit pattern 120-1.

[0154] The first open portion OP1 can mean an area that exposes the upper surface of the first circuit pattern 120-1 in the first region R1 of the first protective layer 150. For example, the first open portion OP1 can mean an area that overlaps perpendicularly with the first circuit pattern 1201 in the first region R1 of the first protective layer 150.

[0155] At this time, the thickness T3 of the first region R1 of the first protective layer 150 is smaller than the thickness T1 of the first circuit pattern 120-1. Thereby, the first open portion OP1 can mean an area where the first protective layer 150 is not disposed by the first circuit pattern 120-1 in the area where the first circuit pattern 120-1 is disposed.

[0156] Therefore, the width of the first open portion OP1 of the first protective layer 150 can correspond to the width of the first circuit pattern 120-1. Here, corresponding means that the difference between the width of the first open portion OP1 of the first protective layer 150 and the width of the first circuit pattern 120-1 is 2 μm or less, 1.5 μm or less, 1.0 μm or less, 0.8 μm or less, or 0.5 μm or less.

[0157] Preferably, the first protective layer 150 is formed by thinning the first protective layer 150 to less than the thickness of the first circuit pattern 120-1 while covering the upper surface of the first circuit pattern 120-1. At this time, the thinned region can be referred to as a first region R1 of the first protective layer 150. And, among the first region R1 of the thinned first protective layer 150, the region where the circuit pattern 120-1 is disposed (or, the region overlapping perpendicularly with the first circuit pattern) can be referred to as the first open portion OP1. Thereby, the width of the first open portion OP1 of the first protective layer 150 may be the same as the width of the first circuit pattern 120-1. Preferably, the width of the first open portion OP1 of the first protective layer 150 may be the same as the width of the lower surface of the first circuit pattern 120-1. Thereby, the first protective layer 150 can be disposed to cover a part of the side surface of the first circuit pattern 120-1 while including the first open portion OP1.

[0158] Specifically, the first protective layer 150 can be divided into a plurality of regions based on the position where the first open portion OP1 is formed.

[0159] For example, the first protective layer 150 includes the first open portion OP1 and includes a first region R1 adjacent to the first open portion OP1. Also, the first protective layer 150 can include a second region R2 having a step with the first region R1 adjacent to the first region R1.

[0160] The first region R1 of the first protective layer 150 includes a first open portion OP1 that overlaps perpendicularly with the first circuit pattern 120-1. Preferably, the first region R1 of the first protective layer 150 includes the first open portion OP1 having the same width as the lower surface of the first circuit pattern 120-1.

[0161] The height of the upper surface of the first region R1 of the first protective layer 150 is different from the height of the upper surface of the second region R2. Preferably, the thickness T3 of the first region R1 of the first protective layer 150 is smaller than the thickness T4 of the second region R2 of the first protective layer 150.

[0162] The thickness T3 of the first region R1 of the first protective layer 150 can be determined based on the thickness T1 of the first circuit pattern 120-1. Preferably, the thickness T3 of the first region R1 of the first protective layer 150 is smaller than the thickness T1 of the first circuit pattern 120-1.

[0163] For example, the thickness T3 of the first region R1 of the first protective layer 150 can satisfy the range of 20% to 90% of the thickness T1 of the first circuit pattern 120-1. Preferably, the thickness T3 of the first region R1 of the first protective layer 150 can satisfy the range of 25% to 85% of the thickness T1 of the first circuit pattern 120-1. More preferably, the thickness T3 of the first region R1 of the first protective layer 150 can satisfy the range of 27% to 83% of the thickness T1 of the first circuit pattern 120-1.

[0164] When the thickness T3 of the first region R1 of the first protective layer 150 is less than 20% of the thickness T1 of the first circuit pattern 120-1, the physical and / or electrical reliability of the first circuit pattern 120-1 may decrease. Specifically, the first region R1 of the first protective layer 150 can function to support the pad 120-11 and / or the trace 120-12 of the first circuit pattern 120-1, which is a fine pattern. And when the thickness T3 of the first region R1 of the first protective layer 150 is less than 20% of the thickness T1 of the first circuit pattern 120-1, the effect of the support function may be insufficient.

[0165] Also, when the thickness T3 of the first region R1 of the first protective layer 150 exceeds 90% of the thickness T1 of the first circuit pattern 120-1, residual resin of the first protective layer 150 can be present on a part of the upper surface of the first circuit pattern 120-1. And when the residual resin of the first protective layer 150 is present on the upper surface of the first circuit pattern 120-1, the electrical reliability of the first circuit pattern 120-1 may decrease.

[0166] At this time, the first region R1 of the first protective layer 150 is disposed to cover a part of the side surface of the first circuit pattern 120-1.

[0167] At this time, the first circuit pattern 120-1 can include a region where the width changes toward the upper surface. Preferably, the first circuit pattern 120-1 can include a region where the width decreases toward the upper surface of the first circuit pattern 120-1. At this time, in the first circuit pattern 120-1, the position where the width starts to decrease can be lower than the upper surface of the first region R1 of the first protective layer 150.

[0168] As a result, at least a part of the inner surface of the first region R1 of the first protective layer 150 (preferably, the side wall of the first open portion OP1 formed in the first region R1) may not contact the side surface of the first circuit pattern 120-1. For example, a crevice may be formed between the inner surface of the first region R1 of the first protective layer 150 and the outer surface of the first circuit pattern 120-1. Specifically, the inner surface of the first region R1 of the first protective layer 150 may be adjacent to the lower surface of the first region R1 of the first protective layer 150 and may include a first inner surface that contacts the outer surface of the first circuit pattern 120-1. In addition, the inner surface of the first region R1 of the first protective layer 150 may be adjacent to the upper surface of the first region R1 of the first protective layer 150 and may include a second inner surface that does not contact or is separated from the outer surface of the first circuit pattern 120-1. And the crevice may be provided between the outer surface of the first circuit pattern 120-1 and the second inner surface of the first region R1 of the first protective layer 150.

[0169] At this time, the crevice is not formed by the second inner surface of the first region R1 of the first protective layer 150, but may be formed by the outer surface of the first circuit pattern 120-1. For example, the crevice may be provided by at least a part of the outer surface of the first circuit pattern 120-1 being shaved inward. However, the embodiments are not limited thereto. For example, the crevice may be formed by the second inner surface of the first region R1 of the first protective layer 150 being shaved inward, and may be formed by a combination thereof.

[0170] However, hereinafter, the crevice will be described as being formed by a part of the outer surface of the first circuit pattern 120-1 being shaved inward.

[0171] The first inner surface and the second inner surface of the first region R1 of the first protective layer 150 are connected to each other. At this time, the inclination of the first inner surface of the first region R1 of the first protective layer 150 can correspond to the inclination of the second inner surface. For example, the first and second inner surfaces of the first region R1 of the first protective layer 150 can have an inclination perpendicular to the lower surface of the first region R1 of the first protective layer 150.

[0172] The first circuit pattern 120-1 can be divided into a plurality of parts in the thickness direction. For example, the pads 120-11 and / or traces 120-12 of the first circuit pattern 120-1 can be divided into a plurality of parts in the thickness direction.

[0173] The first circuit pattern 120-1 can include a first part 120-1a adjacent to the upper surface of the insulating layer 110. The width of the upper surface of the first part 120-1a of the first circuit pattern 120-1 can correspond to the width of the lower surface of the first part 120-1a. Here, corresponding means that the width difference between the upper surface and the lower surface of the first part 120-1a of the first circuit pattern 120-1 is 2 μm or less, 1.5 μm or less, 1.0 μm or less, 0.8 μm or less, or 0.5 μm or less.

[0174] The width of the first part 120-1a of the first circuit pattern 120-1 can correspond to the width of the first open part OP1 formed in the first region R1 of the first protective layer 150. Preferably, the width of the first part 120-1a of the first circuit pattern 120-1 may be the same as the width of the first open part OP1.

[0175] Therefore, the outer surface 120-1as of the first part 120-1a of the first circuit pattern 120-1 can be in direct contact with the first protective layer 150. Preferably, the outer surface 120-1as of the first part 120-1a of the first circuit pattern 120-1 can be in direct contact with the first inner surface of the first region R1 of the first protective layer 150.

[0176] The outer surface 120-1as of the first part 120-1a of the first circuit pattern 120-1 can have an inclination corresponding to the inclination of the first inner surface of the first region R1 of the first protective layer 150. For example, the outer surface of the first part 120-1a of the first circuit pattern 120-1 may be perpendicular to the lower surface of the first circuit pattern 120-1, but is not limited thereto.

[0177] At this time, the uppermost end of the first part 120-1a of the first circuit pattern 120-1 can be positioned lower than the upper surface of the first region R1 of the first protective layer 150. For example, the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 may be smaller than the thickness T3 of the first region R1 of the first protective layer 150.

[0178] At this time, the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 can be determined by the thickness T3 of the first region R1 of the first protective layer 150.

[0179] Specifically, the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 can satisfy the range of 20% to 90% of the thickness T3 of the first region R1 of the first protective layer 150. Preferably, the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 can satisfy the range of 25% to 85% of the thickness T3 of the first region R1 of the first protective layer 150. More preferably, the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 can satisfy the range of 27% to 83% of the thickness T3 of the first region R1 of the first protective layer 150.

[0180] When the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 is less than 20% of the thickness T3 of the first region R1 of the first protective layer 150, the contact area between the outer surface of the first circuit pattern 120-1 and the inner surface of the first region R1 of the first protective layer 150 decreases, and the physical reliability and / or electrical reliability of the first circuit pattern 120-1 may be reduced thereby. Also, when the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 is less than 20% of the thickness T3 of the first region R1 of the first protective layer 150, the depth of the crevice increases, and the physical reliability of the connection part disposed on the first circuit pattern 120-1 may be reduced thereby. For example, when the depth of the crevice increases, the deviation in the thickness of the connection part increases, and the mounting processability of the semiconductor element may be reduced thereby. Also, when the depth of the crevice increases, the coating amount of the connection part increases, and the rigidity of the connection part may be reduced thereby.

[0181] Also, when the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 exceeds 90% of the thickness T3 of the first region R1 of the first protective layer 150, the depth of the crevice decreases, and the effect exhibited by the crevice may be insufficient thereby. For example, the crevice is formed to increase the distance between the lowermost end of the surface treatment layer 170 (see FIG. 6) disposed on the first circuit pattern 120-1 and the upper surface of the second region R2 of the first protective layer 150. At this time, when the thickness T2 of the first part 120-1a of the first circuit pattern 120-1 exceeds 90% of the thickness T3 of the first region R1 of the first protective layer 150, the distance increasing effect becomes insufficient, and physical reliability problems such as cracks occurring in the metal bonding layer formed by disposing the connection part may occur thereby.

[0182] On the one hand, the first circuit pattern 120-1 includes a second part 120-1b disposed on the first part 120-1a. The upper surface of the second part 120-1b is located higher than the upper surface of the first region R1 of the first protective layer 150. Also, the lower surface of the second part 120-1b is located lower than the upper surface of the first region R1 of the first protective layer 150.

[0183] The second part 120-1b of the first circuit pattern 120-1 includes a region where the width changes.

[0184] Specifically, the width of the second part 120-1b of the first circuit pattern 120-1 may decrease as it moves away from the first part 120-1a.

[0185] For example, the second part 120-1b of the first circuit pattern 120-1 includes an outer surface 120-1bs that is connected to the outer surface 120-1as of the first part 120-1a.

[0186] The outer surface 120-1bs of the second part 120-1b has a slope different from the slope of the outer surface 120-1as of the first part 120-1a. For example, the outer surface 120-1as of the first part 120-1a can have a slope without a change in width.

[0187] And the outer surface 120-1bs of the second part 120-1b can have a slope where the width gradually decreases as it moves away from the first part 120-1a.

[0188] For example, the outer surface 120-1bs of the second part 120-1b can be a straight line having a specific slope with a gradually decreasing width. At this time, in FIG. 5, the outer surface 120-1bs of the second part 120-1b is shown as a straight line having a specific slope, but it is not limited thereto. For example, the outer surface 120-1bs of the second part 120-1b can have a specific curvature such that the width decreases toward the upper surface. And the outer surface 120-1bs of the second part 120-1b having the curvature can have a convex shape toward the first region R1 of the first protective layer 150, and differently, it can have a concave shape toward the inside of the second pad 120-1b away from the first region R1 of the first protective layer 150.

[0189] The outer surface 120-1b of the second part 120-1b does not contact the first protective layer 150. For example, the outer surface 120-1bs of the second part 120-1b does not contact the inner surface of the first region R1 of the first protective layer 150. For example, the outer surface 120-1bs of the second part 120-1b is separated from the inner surface of the first region R1 of the first protective layer 150. For example, a clevis is formed between the outer surface 120-1b of the second part 120-1b and the inner surface of the first region R1 of the first protective layer 150.

[0190] And the embodiment can improve the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same by using the clevis formed between the first circuit pattern 120-1 and the first protective layer 150.

[0191] For example, referring to FIG. 6, a surface treatment layer 170 is disposed on the first circuit pattern 120-1. The surface treatment layer 170 can be an organic solderability preservative (OSP).

[0192] At this time, the surface treatment layer 170 is disposed on the surface of the first circuit pattern 120-1. For example, the surface treatment layer 170 is disposed on the surface of the circuit pattern 120-1 exposed through the first open portion OP1 of the first protective layer 150. For example, the surface treatment layer 170 is disposed on the upper surface and the outer side surface 120-1bs of the second part 120-1b of the first circuit pattern 120-1. Thereby, the lowermost end of the surface treatment layer 170 is located within a clevis formed between the first circuit pattern 120-1 and the first region R1 of the first protective layer 150. Through this, the embodiment can increase the distance or length of the side wall of the first protective layer 150 between the upper surface of the second region R2 of the first protective layer 150 and the lowermost end of the surface treatment layer 170. Therefore, the embodiment can improve the physical reliability and / or electrical reliability of a metal bonding layer formed by disposing a connection portion such as solder on the surface treatment layer 170.

[0193] On the other hand, the clevis can be formed by pre-treating a part of the upper surface and the outer side surface of the first circuit pattern 120-1 in the process of forming the surface treatment layer 170. For example, in the pre-treatment process, etching of the upper surface and the outer side surface 120-1bs of the second part 120-1b of the first circuit pattern 120-1 can be performed. Therefore, an etching-based clevis can be formed between the outer side surface 120-1b of the second part 120-1b and the inner side surface of the first region R1 of the first protective layer 150.

[0194] Therefore, the outer side surfaces of the first circuit pattern 120-1 can have different roughnesses depending on the region.

[0195] For example, the outer side surface 120-1as of the first part 120-1a of the first circuit pattern 120-1 can have a first surface roughness. At this time, the first surface roughness of the outer side surface 120-1as of the first part 120-1a can correspond to the surface roughness of the inner side surface of the first region R1 of the first protective layer 150 in contact therewith.

[0196] On the one hand, the outer surface 120-1bs of the second part 120-1b of the first circuit pattern 120-1 can have a second surface roughness different from the first surface roughness. Preferably, the outer surface 120-1bs of the second part 120-1b of the first circuit pattern 120-1 can have a second surface roughness greater than the first surface roughness of the outer surface 120-1as of the first part 120-1a.

[0197] Through this, the embodiment can ensure the adhesion between the surface treatment layer 170 and the first circuit pattern 120-1, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0198] On the one hand, the first protective layer 150 can include a recess 153. The recess 153 can be formed at the boundary between the first region R1 and the second region R2 of the first protective layer 150. The recess 153 can be formed at the boundary when the thickness T3 of the first region R1 of the first protective layer 150 decreases. For example, the recess 153 can be formed at the boundary between the first region R1 and the second region R2 due to incomplete curing of the first protective layer 150. And the embodiment can minimize the horizontal length of the recess 153 by adjusting the thickness T3 of the first region R1.

[0199] However, the embodiment adjusts the thickness T3 of the first region R1 so that the recess 153 is provided at the boundary with a certain level of horizontal length. And the recess 153 can be filled with solder at the same connection part in a later solder bonding process. And the connection part arranged in the recess 153 can perform an anchor function, through which the bonding force between the connection part and the first circuit pattern 120-1 can be improved.

[0200] On the one hand, referring to FIG. 7, the first protective layer 150 includes a second open portion OP2. At this time, the second open portion OP2 can have a shape different from that of the first open portion OP1. For example, the second open portion OP2 can be an SMD type open portion.

[0201] For example, the second open portion OP2 overlaps perpendicularly with the second circuit pattern 120-2. At this time, the second open portion OP2 partially overlaps perpendicularly with the upper surface of the second circuit pattern 120-2. For example, a part of the upper surface of the second circuit pattern 120-2 can be covered by the first protective layer 150, and the remaining part can be exposed through the second open portion OP2.

[0202] At this time, the first protective layer 150 can include the second open portion OP2 and a third region R3 adjacent to the second open portion OP2. The third region R3 can mean a region that overlaps perpendicularly with the second circuit pattern 120-2 while including the second open portion OP2. Also, the first protective layer 150 can include a fourth region R4 adjacent to the third region R3. At this time, the upper surface of the third region R3 of the first protective layer 150 can have the same height as the upper surface of the fourth region R4. For example, the upper surface of the third region R3 of the first protective layer 150 may not have a step with the upper surface of the fourth region R4. For example, the upper surface of the third region R3 of the first protective layer 150 can be located on the same plane as the upper surface of the fourth region R4. That is, the second circuit pattern 120-2 is a large area pattern compared to the first circuit pattern 120-1. Therefore, even if the second open portion OP2 that overlaps perpendicularly with the second circuit pattern 120-2 does not have the same structure as the first open portion OP1, the reliability of the metal bonding layer can be maintained.

[0203] Therefore, in the pre-treatment process for forming a surface treatment layer (not shown) on the second circuit pattern 120-2, the second circuit pattern 120-2 may include a recess 120-2R formed by etching a part of the upper surface of the second circuit pattern 120-2. And the horizontal width of the recess 120-2R may be larger than the width of the second open portion OP2. For example, a part of the recess 120-2R overlaps the second open portion OP2 vertically, and the remaining part overlaps the third region R3 of the first protective layer 150 vertically. Thereby, a connection part such as a surface treatment layer or solder can penetrate into the recess 120-2R. Through this, the embodiment can enable the surface treatment layer or the connection part penetrating into the recess 120-2R to perform an anchor function, and thereby further improve the bonding force between the second circuit pattern 120-2 and the surface treatment layer or solder.

[0204] The embodiment includes an insulating layer, a first circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer and including a first open portion overlapping the first circuit pattern vertically.

[0205] That is, the first protective layer includes the first open portion and a first region adjacent to the first open portion. The first protective layer also includes a second region adjacent to the first region. At this time, the height of the upper surface of the first region is lower than the height of the upper surface of the second region. Preferably, the height of the upper surface of the first region is lower than the height of the upper surface of the first circuit pattern. Through this, the embodiment arranges a first protective layer including a first region and a second region having the first open portion in a region where the protective layer is not arranged due to the exposure resolution of the protective layer. And the first region is arranged surrounding the periphery of the first circuit pattern while including a first open portion having substantially the same width as the first circuit pattern.

[0206] Therefore, the embodiments can stably protect the first circuit pattern from damages caused by various stresses. Through this, the embodiments can improve the physical reliability and / or electrical reliability of the first circuit pattern.

[0207] At this time, a clevis may be formed between the inner surface of the first region of the first protective layer and the outer surface of the first circuit pattern.

[0208] Specifically, the inner surface of the first region includes a first inner surface that contacts the outer surface of the first circuit pattern and a second inner surface that is separated from the outer surface of the first circuit pattern through the clevis without contacting the outer surface of the first circuit pattern.

[0209] And the embodiments enable the surface treatment layer and / or solder to be disposed in the clevis. Through this, the embodiments can increase the distance between the metal bonding layer formed by the disposition of the solder and the uppermost surface of the first protective layer. Therefore, the embodiments can dramatically reduce the possibility of crack generation in the metal bonding layer, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package.

[0210] Furthermore, the embodiments can increase the distance using the clevis without increasing the thickness of the first protective layer. Therefore, the embodiments can achieve slimming of the circuit board and the semiconductor package.

[0211] Also, the outer surface of the first circuit pattern includes a first outer surface that contacts the outer surface of the first region of the first protective layer and a second outer surface that does not contact the first protective layer. And the surface roughness of the second outer surface may be greater than the surface roughness of the first outer surface. Through this, the embodiments can ensure the adhesion between the surface treatment layer disposed on the second outer surface and the first circuit pattern, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0212] Also, in the embodiment, the thickness of the first region is adjusted so that a recess recessed inward is formed at the boundary between the first region and the second region. Then, the recess can be filled with a connection part such as solder in the solder bonding process. And the connection part disposed in the recess can perform an anchor function, through which the bonding force between the connection part and the first circuit pattern can be improved.

[0213] Hereinafter, a circuit board according to another embodiment will be described.

[0214] The circuit board described below is similar to the embodiment of the first circuit board shown in FIG. 5 and may be different from each other in the shape of the first circuit pattern. Therefore, in the description of the circuit board of the following other embodiments, the description will be centered on the shape of the first circuit pattern.

[0215] FIG. 8 is a diagram showing a circuit board according to a second embodiment.

[0216] Referring to FIG. 8, the circuit board of the second embodiment includes an insulating layer 210, a first circuit pattern 220-1, and a first protective layer 250.

[0217] The first protective layer 250 includes a first open portion OP1. For example, the first protective layer 250 includes the first open portion OP1 and includes a first region R1 adjacent to the first open portion OP1. Also, the first protective layer 250 can include a second region R2 that has a step with the first region R1 while being adjacent to the first region R1.

[0218] Also, the first circuit pattern 220-1 includes a first part 220-1a and a second part 220-1b.

[0219] Here, the insulating layer 210 and the first protective layer 250 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Thus, the description thereof is omitted.

[0220] The first part 220-1a of the first circuit pattern 220-1 has the same structure as the first part 120-1a of the first circuit pattern 110-1 in the first embodiment. Thus, its description is also omitted.

[0221] On the other hand, the second part 220-1b of the first circuit pattern 220-1 is disposed on the first part 220-1a. At this time, the second part 220-1b can have a step with the first part 220-1a.

[0222] Specifically, the first part 120-1a in the first embodiment did not have a step with the second part 120-1b. That is, the width of the portion of the first part 120-1a in the first embodiment that is closest to the second part 120-1b was the same as the width of the portion of the second part 120-1b that is closest to the first part 120-1a.

[0223] In contrast, the second part 220-1b in the second embodiment can have a step with the first part 220-1a. Specifically, the width of the portion of the second part 220-1b that is closest to the first part 220-1a can be different from the width of the portion of the first part 220-1a that is closest to the second part 220-1b. More specifically, the width of the portion of the second part 220-1b that is closest to the first part 220-1a is smaller than the width of the portion of the first part 220-1a that is closest to the second part 220-1b.

[0224] As a result, a step portion 220-1ST may be provided between the first part 220-1a and the second part 220-1b of the first circuit pattern 220-1. The step portion 220-1ST may mean a portion where a part of the upper surface of the first part 220-1a is exposed due to the difference in width between the first part 220-1a and the second part 220-1a of the first circuit pattern 220-1. That is, the upper surface of the first part 220-1a does not contact the second part 220-1b and the first protective layer 250.

[0225] And, the outer surface 220-1bs of the second part 220-1b may have an inclination in which the width gradually decreases as it moves away from the first part 220-1a.

[0226] For example, the outer surface 220-1b of the second part 220-1b may be a straight line having a specific inclination in which the width gradually decreases, but is not limited thereto.

[0227] For example, the outer surface 220-1bs of the second part 220-1b may have a specific curvature in which the width decreases toward the upper surface. And, the outer surface 220-1bs of the second part 220-1b having the curvature may have a convex shape on the outside, and differently, may have a concave shape on the inside.

[0228] FIG. 9 is a diagram showing a circuit board according to a third embodiment.

[0229] Referring to FIG. 9, the circuit board of the third embodiment includes an insulating layer 310, a first circuit pattern 320-1, and a first protective layer 350.

[0230] The first protective layer 350 includes the first open portion OP1. For example, the first protective layer 350 includes the first open portion OP1 and includes a first region R1 adjacent to the first open portion OP1. Further, the first protective layer 350 may include a second region R2 that has a step with the first region R1 while being adjacent to the first region R1.

[0231] Further, the first circuit pattern 320-1 includes a first part 320-1a and a second part 320-1b.

[0232] Here, the insulating layer 310 and the first protective layer 350 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Therefore, the description thereof is omitted.

[0233] The first part 320-1a of the first circuit pattern 320-1 has the same structure as the first part 120-1a of the first circuit pattern 110-1 of the first embodiment. Therefore, the description thereof is also omitted.

[0234] On the other hand, the second part 320-1b of the first circuit pattern 320-1 is disposed on the first part 320-1a. At this time, the second part 320-1b can have a step with the first part 120-1a.

[0235] That is, the width of the portion of the second part 320-1b that is closest to the first part 320-1a is the closest to the first part 320-1a among the first part 320-1a. It can be different from the width of the adjacent portion. Specifically, the width of the portion of the second part 320-1b that is closest to the first part 320-1a is smaller than the width of the portion of the first part 320-1a that is closest to the second part 320-1b.

[0236] Thereby, a stepped portion 320-1ST may be provided between the first part 320-1a and the second part 320-1b of the first circuit pattern 320-1. The stepped portion 320-1ST can mean a portion where a part of the upper surface of the first part 320-1a is exposed due to the difference in width between the first part 320-1a and the second part 320-1a of the first circuit pattern 320-1. That is, the upper surface of the first part 320-1a does not contact the second part 320-1b and the first protective layer 350.

[0237] And the second part 320-1b may not change in width as it moves away from the first part 320-1a. For example, the outer surface 320-1bs of the second part 320-1b may have no change in width and may be a straight line perpendicular to the lower surface of the first circuit pattern 320-1.

[0238] FIG. 10 is a diagram showing a circuit board according to a fourth embodiment.

[0239] Referring to FIG. 10, the circuit board of the fourth embodiment includes an insulating layer 410, a first circuit pattern 420-1, and a first protective layer 450.

[0240] The first protective layer 450 includes a first open portion OP1. For example, the first protective layer 450 includes the first open portion OP1 and a first region R1 adjacent to the first open portion OP1. Further, the first protective layer 450 may include a second region R2 that is adjacent to the first region R1 and has a step with the first region R1.

[0241] The first circuit pattern 420-1 includes a first part 420-1a and a second part 420-1b.

[0242] Here, the insulating layer 410 and the first protective layer 450 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Therefore, the description thereof is omitted.

[0243] The first part 420-1a of the first circuit pattern 420-1 has the same structure as the first part 120-1a of the first circuit pattern 110-1 of the first embodiment. Therefore, the description thereof is also omitted.

[0244] On the other hand, the second part 420-1b of the first circuit pattern 420-1 is disposed on the first part 420-1a.

[0245] At this time, the second part 420-1b may be divided into a plurality of sub-parts.

[0246] For example, the second part 420-1b can be divided into a plurality of sub-parts based on the shape or inclination of the outer surface.

[0247] The second part 420-1b includes a first sub-part 420-1b1 disposed on the first part 420-1a. Further, the second part 420-1b can include a second sub-part 420-1b2 disposed on the first sub-part 420-1b1.

[0248] At this time, the vertical cross-sections of the first sub-part 420-1b1 and the second sub-part 420-1b2 can have different shapes from each other. For example, the outer surfaces of the first sub-part 420-1b1 and the second sub-part 420-1b2 can have different inclinations from each other.

[0249] The outer surface 420-1b1s of the first sub-part 420-1b1 can be a curve having a specific curvature. Therefore, the first sub-part 420-1b1 may decrease in width as it moves away from the first sub-part 420-1a based on the curvature of the curve. And the outer surface 420-1b1s of the first sub-part 420-1b1 having the curvature can have a convex shape outward, and in contrast, can have a concave shape inward.

[0250] The outer surface 420-1b2s of the second sub-part 420-1b2 can have an inclination such that the width gradually decreases as it moves away from the first sub-part 420-1b1.

[0251] For example, the outer surface 420-1b2s of the second sub-part 420-1b2 can be a straight line having a specific inclination with a gradually decreasing width, but is not limited thereto. For example, the outer surface 420-1b2s of the second sub-part 420-1b2 can have a specific curvature. And the outer surface 420-1b2s of the second sub-part 420-1b2 having the curvature can have a convex shape outward, and in contrast, can have a concave shape inward.

[0252] FIG. 11 is a diagram showing a circuit board according to the fifth embodiment.

[0253] Referring to FIG. 15, the circuit board of the fifth embodiment includes an insulating layer 510, a first circuit pattern 520-1, and a first protective layer 550.

[0254] The first protective layer 550 includes the first open portion OP1. For example, the first protective layer 550 includes the first open portion OP1 and a first region R1 adjacent to the first open portion OP1. Further, the first protective layer 550 may include a second region R2 that is adjacent to the first region R1 and has a step with the first region R1.

[0255] Also, the first circuit pattern 520-1 includes a first part 520-1a and a second part 520-1b.

[0256] Here, the insulating layer 510 and the first protective layer 550 have the same structure as the insulating layer 110 and the first protective layer 150 of the first embodiment. Accordingly, the description thereof is omitted.

[0257] The first part 520-1a of the first circuit pattern 520-1 has the same structure as the first part 120-1a of the first circuit pattern 110-1 of the first embodiment. Accordingly, the description thereof is also omitted.

[0258] On the other hand, the second part 520-1b of the first circuit pattern 520-1 is disposed on the first part 520-1a.

[0259] At this time, the second part 520-1b may be divided into a plurality of sub-parts.

[0260] For example, the second part 520-1b may be divided into a plurality of sub-parts based on the shape or inclination of the outer surface.

[0261] The second part 520-1b includes a first sub-part 520-1b1 disposed on the first part 520-1a. Further, the second part 520-1b can include a second sub-part 520-1b2 disposed on the first sub-part 520-1b1.

[0262] At this time, the vertical cross-sections of the first sub-part 520-1b1 and the second sub-part 520-1b2 can have different shapes from each other. For example, the outer surfaces of the first sub-part 520-1b1 and the second sub-part 520-1b2 can have different inclinations from each other.

[0263] The outer surface 520-1b1s of the first sub-part 520-1b1 can be a curve having a specific curvature. Accordingly, the first sub-part 520-1b1 may decrease in width as it moves away from the first part 520-1a based on the curvature of the curve. And the outer surface 520-1b1s of the first sub-part 520-1b1 having the curvature can have a convex shape outward, and in contrast, can have a concave shape inward.

[0264] The second sub-part 520-1b2 may not change in width as it moves away from the first sub-part 520-1b1.

[0265] For example, the outer surface 520-1b2s of the second sub-part 520-1b2 may be perpendicular to the lower surface of the first circuit pattern 520-1.

[0266] -Semiconductor Package-

[0267] FIG. 12 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0268] Referring to FIG. 12, the semiconductor package of the embodiment can include any one of the circuit boards shown in FIGS. 5, 8, 9, 10, and 11. Further, the circuit board can have a multilayer structure.

[0269] The semiconductor package of the embodiment includes a first connection part 610. That is, the circuit pattern layer of the circuit pattern includes pads arranged corresponding to the mounting region of the semiconductor element 620. The pads can mean the pads 120-11 of the first circuit pattern 120-1 of the first circuit pattern layer.

[0270] The first connection part 610 can have a hexahedron shape. The cross section of the first connection part 610 can include a quadrangular shape. The cross section of the first connection part 610 can include a rectangular shape or a square shape. For example, the first connection part 610 can include a spherical shape. For example, the cross section of the first connection part 610 can include a circular shape or a semi-circular shape. For example, the cross section of the first connection part 610 can include a partially or entirely rounded shape. The cross-sectional shape of the first connection part 610 may be a plane on one side and a curved surface on the other side. The first connection part 610 can be a solder ball, but is not limited thereto. On the other hand, at least a part of the first connection part 610 can be arranged in the clevis.

[0271] The semiconductor package of the embodiment includes a configuration arranged on the first connection part 610. The configuration arranged on the first connection part 610 may be a semiconductor element or, alternatively, an interposer. Hereinafter, it will be described assuming that the configuration arranged on the first connection part 610 is a semiconductor element 620.

[0272] The semiconductor element 620 can be a logic chip, but is not limited thereto. For example, the semiconductor element 620 can be an application processor (AP) chip among a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The semiconductor element 620 includes terminals 625 on the lower surface. Then, the terminals 625 of the semiconductor element 620 are connected to the circuit pattern layer of the circuit board via the first connection part 610.

[0273] Also, the semiconductor package can include an underfill 630. The underfill 630 can be disposed to cover the periphery of the semiconductor element 620 on the circuit board. However, the underfill 630 can be selectively omitted. For example, in the semiconductor package, the underfill 630 can be omitted, and the function of the underfill 630 can be fulfilled by the molding layer 650.

[0274] The semiconductor package can include a second connection portion 640. The second connection portion 640 is disposed on the first circuit pattern layer of the circuit board. For example, the second connection portion 640 can be disposed on the second circuit pattern 120-2 of the first circuit pattern layer 120.

[0275] The second connection portion 640 can be a bump. As an example, the second connection portion 640 can be a solder bump, but is not limited thereto. For example, the second connection portion 640 can be a post bump. For example, the second connection portion 640 can include a copper post and a solder bump disposed on the copper post. The upper surface of the second connection portion 640 can be positioned higher than the upper surface of the semiconductor element 620. Through this, it is possible to prevent the semiconductor element 620 from being damaged in the bonding process of the external substrate 600 disposed on the second connection portion 640.

[0276] The semiconductor package can include a molding layer 650. The molding layer 650 can mold the configuration disposed on the circuit board.

[0277] The molding layer 650 can be, but is not limited to, EMC (Epoxy Mold Compound). The molding layer 650 can have a low dielectric constant. For example, the dielectric constant (Dk) of the molding layer 650 can be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 650 can be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 650 can be 0.8 to 5. Thereby, in the embodiment, the heat dissipation characteristics of the heat generated by the semiconductor element 620 can be enhanced by making the molding layer 650 have a low dielectric constant. The molding layer 650 can include an opening. For example, the molding layer 650 can include an opening that overlaps the upper surface of the second connection portion 640 in the vertical direction.

[0278] The semiconductor package includes a third connection portion 660.

[0279] The third connection portion 660 can be disposed under the circuit pattern layer disposed on the lowermost side of the circuit board. The third connection portion 660 can be, but is not limited to, solder for connecting the semiconductor package of the embodiment to another external substrate (for example, the main board of an electronic device).

[0280] The semiconductor package includes an external substrate 700. The external substrate 700 can mean another substrate coupled to the circuit board of the embodiment. For example, the semiconductor element 620 disposed on the circuit board may be a logic chip such as a CPU or a GPU, and the external substrate 700 can mean a memory substrate on which a memory chip coupled to the logic chip is disposed. The external substrate 700 can be an interposer that connects between the memory substrate on which the semiconductor element 780 corresponding to the memory chip is disposed and the circuit board.

[0281] The external substrate 700 may include an insulating layer 710, a circuit layer 720, a through electrode 730, an upper protective layer 740, and a lower protective layer 750. And the external substrate 700 may include a fourth connection portion 760. The fourth connection portion 760 may be disposed between the external substrate 700 and the third connection portion 740.

[0282] Also, the semiconductor package may include a fifth connection portion 770. The fifth connection portion 770 may be disposed on the external substrate 700.

[0283] The semiconductor package may include a semiconductor element 780. The semiconductor element 780 may be mounted on the external substrate 700 via the fifth connection portion 770. The semiconductor element 780 may be a memory chip, but is not limited thereto. Terminals 785 of the semiconductor element 780 may be electrically connected to the external substrate 700 via the fifth connection portion 770. At this time, although the semiconductor element 780 is shown as being mounted in a flip chip manner, it is not limited thereto. The semiconductor element 780 may be a stacked memory chip, and thus may be electrically connected to the external substrate 700 via a connection member such as another wire.

[0284] -Manufacturing Method-

[0285] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described.

[0286] FIGS. 13 to 18 are cross-sectional views showing a method for manufacturing a circuit board according to an embodiment in the order of manufacturing steps.

[0287] Referring to FIG. 13, in the embodiment, an insulating layer 110 is prepared.

[0288] Thereafter, in the embodiment, a through hole VH penetrating the upper and lower surfaces of the insulating layer 110 is formed.

[0289] Next, referring to FIG. 14, the embodiment can form a through electrode 140 that fills the through hole VH on the insulating layer 110. Also, the embodiment can form a first circuit pattern layer 120 including a first circuit pattern 120-1 and a second circuit pattern 120-2 on the upper surface of the insulating layer 110. Further, the embodiment can form a second circuit pattern layer 130 on the lower surface of the insulating layer 120.

[0290] Next, referring to FIG. 15, the embodiment forms a first resist layer R1 on the insulating layer 120. At this time, the first resist layer R1 can mean a protective layer before an open portion is formed in the first protective layer 150. The first resist layer R1 can be, but is not limited to, a solder resist layer.

[0291] Also, the embodiment forms a second resist layer R2 under the insulating layer 120. At this time, the second resist layer R2 can mean a protective layer before an open portion is formed in the second protective layer 160. The second resist layer R2 can be, but is not limited to, a solder resist layer.

[0292] Next, referring to FIG. 16, the embodiment can perform a process of exposing the first resist layer R1 to form a first exposure pattern ER1 and a second exposure pattern ER2. The first exposure pattern ER1 and the second exposure pattern ER2 can be formed corresponding to regions where open portions are formed in the first resist layer R1.

[0293] Also, the embodiment can perform a process of exposing the second resist layer R2 to form a third exposure pattern ER3.

[0294] Next, referring to FIG. 17, in the embodiment, by forming the first to third exposure patterns ER1, ER2, and ER3, a step of curing the remaining regions of the first resist layer R1 and the second resist layer R2 excluding the first to third exposure patterns ER1, ER2, and ER3 can be performed. Thereafter, the embodiment can perform a thinning step of reducing the thickness of the regions corresponding to the first to third exposure patterns ER1, ER2, and ER3 to a target thickness.

[0295] The thinning step can be performed using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0296] Through this, in the embodiment, a first open portion OP1 and a second open portion OP2 can be respectively formed in the first protective layer 150.

[0297] Thereafter, the embodiment can perform OSP pretreatment. And by performing the OSP pretreatment, a part of the outer surface of the first circuit pattern 120-1 not covered by the first protective layer 150 can be removed by etching. Through this, a clevis can be formed between the first protective layer 150 and the first circuit pattern 120-1. Also, the OSP pretreatment can be performed on the upper surface of the second circuit pattern 120-2 that vertically overlaps the second open portion OP2. As a result, a recess 120-2R can be formed on the upper surface of the second circuit pattern 120-2 by the OSP pretreatment.

[0298] On the one hand, when a circuit board having the features of the above-described invention is used in IT devices such as smartphones, servers, TVs, and home appliances, functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor package function, it can perform a function of safely protecting a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical short circuit between terminals, or electrical open of terminals supplied to the semiconductor chip. Also, when performing the function of signal transmission, the noise problem can be solved. Through this, the circuit board having the features of the above-described invention can maintain the stable functions of IT devices and home appliances, so that the overall product and the circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0299] When a circuit board having the features of the above-described invention is used in a transport device such as a vehicle, the problem of signal distortion transmitted to the transport device can be solved, or a semiconductor chip that controls the transport device can be safely protected from the outside, and leakage current, electrical short circuit between terminals, or, different from this, the problem of electrical open of terminals supplied to the semiconductor chip can be solved, and the stability of the transport device can be further improved. Therefore, the transport device and the circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0300] As described above, the features, structures, effects, etc. described in the embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified and implemented for other embodiments by those having ordinary knowledge in the field to which the embodiment belongs. Therefore, the content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0301] Although the above has been described mainly with reference to the embodiments, this is merely an illustration and does not limit the embodiments. Those with ordinary knowledge in the field to which the embodiments belong will understand that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be implemented with modifications. And the differences related to such modifications and applications should be construed as being included in the scope of the embodiments set forth in the appended claims.

Claims

1. An insulating layer, a first circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer and including a first open portion that overlaps the first circuit pattern perpendicularly, wherein the first protective layer includes a first region that includes the first open portion and has a first thickness, and a second region that does not include the first open portion and has a second thickness greater than the first thickness, wherein the first thickness of the first region is smaller than a third thickness of the first circuit pattern, wherein an inner surface of the first region that constitutes the first open portion includes a first inner surface that is in direct contact with an outer surface of the first circuit pattern, and a second inner surface that is separated from the outer surface of the first circuit pattern, a circuit board

2. The second inner surface of the first region is connected to the first inner surface of the first region and has an inclination corresponding to the inclination of the first inner surface, the circuit board according to claim 1.

3. The second thickness of the second region is greater than the third thickness of the first circuit pattern, the circuit board according to claim 1.

4. The first circuit pattern includes a region where the width decreases toward the upper surface of the first circuit pattern, wherein the second inner surface of the first region is separated from an outer surface of the region where the width of the first circuit pattern decreases, the circuit board according to claim 1.

5. The first thickness of the first region satisfies the range of 20% to 90% of the third thickness of the first circuit pattern, the circuit board according to any one of claims 1 to 4.

6. The first circuit pattern includes a first part disposed on the upper surface of the insulating layer and having an outer surface in contact with the first inner surface of the first region, and a second part disposed on the first part and having an outer surface not in contact with the first protective layer, wherein the second part includes a region having a width smaller than the width of the first part, the circuit board according to claim 5.

7. The width of the first open portion corresponds to the width of the first part, the circuit board according to claim 6.

8. The first part has a fourth thickness in the range of 20% to 90% of the first thickness of the first region, the circuit board according to claim 6.

9. The outer surface of the second part has a linear inclination in which the width gradually decreases toward the upper surface of the second part, the circuit board according to claim 6.

10. The outer surface of the second part The circuit board according to claim 6, having an inclination of a curve with a specific curvature that decreases in width toward the upper surface of the second part.

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