Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel includes an output terminal group, a multiplexer, a test terminal group, an input terminal group, and an organic layer arranged in a chip bonding region. A first boundary of the organic layer is located between the multiplexer and the output terminal group, and a distance between the first boundary and the output terminal group is 30 μm or more. A second boundary of the organic layer is located between the test terminal group and the input terminal group, and a distance between the second boundary and the input terminal group is 30 μm or more.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to display panels and display devices.

Background Art

[0002] Organic Light-Emitting Diode (abbreviated as OLED) display panels have advantages such as being thinner, having better display effects, higher resolutions, wider color gamuts, being able to achieve low power consumption and flexible display compared to liquid crystal displays. Therefore, in recent years, they have developed rapidly and have become the top-ranked type of display panel for mobile terminals.

[0003] With the development of OLED display technology, users' requirements for each performance of the display panel are gradually increasing. Usually, OLED display panels are tested using the double 85 test / HAST test (also known as the RA test) for their limits in harsh environments of high temperature and high humidity. A common defect that often appears in OLED display panels during the double 85 test / HAST test is the problem of film layer peeling in the Chip On Panel (COP) area. The film layer peeling in the COP area causes abnormal chip output signals, generates vertical bright lines on the OLED display panel, and affects the display quality of the display panel. This problem must be solved urgently.

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to this application, a display panel and a display device are provided, which can effectively solve the problems of display anomalies and reduced display image quality in conventional OLED display panels.

[0005] On the one hand, the present application provides a display panel, the display panel has a chip bonding region, the display panel includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group sequentially arranged in the chip bonding region, the display panel further includes an organic layer disposed in the chip bonding region, the organic layer includes a first boundary and a second boundary, where the first boundary is located between the multiplexer and the output terminal group, the distance between the first boundary and the output terminal group is a, a≧30μm, the second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, b≧30μm.

[0006] Preferably, an electrostatic prevention circuit is not arranged between the output terminal group and the input terminal group.

[0007] Preferably, the organic layer located between the first boundary and the second boundary is arranged continuously.

[0008] Preferably, the organic layer located between the first boundary and the second boundary is arranged discontinuously. Here, the display panel further includes a dummy terminal group disposed in the chip bonding region. The dummy terminal group is located between the multiplexer and the test terminal group. The organic layer includes a third boundary and a fourth boundary. The third boundary is located between the multiplexer and the dummy terminal group. The distance between the third boundary and the dummy terminal group is c, c>m / 6, where m is the distance between the third boundary and the first boundary. The fourth boundary is located between the test terminal group and the dummy terminal group. The distance between the fourth boundary and the test terminal group is d, d>n / 6, where n is the distance between the fourth boundary and the second boundary.

[0009] Preferably, the dummy terminal group includes a plurality of dummy terminals, and the plurality of dummy terminals form a plurality of dummy terminal rows. Here, c = d≧50μm.

[0010] Preferably, the organic layer is not disposed between any two adjacent dummy terminal rows.

[0011] Preferably, the dummy terminal group includes a plurality of dummy terminals, and the plurality of dummy terminals form one dummy terminal row, where c = d ≥ 80 μm.

[0012] Preferably, a = b = c = d.

[0013] Preferably, the organic layer is integrally formed.

[0014] On the other hand, the present application provides a display device, which includes a housing and the display panel described in any of the above, where the housing has an accommodation space, and the display panel is disposed in the accommodation space.

Advantages of the Invention

[0015] The present application provides a display panel and a display device. The display panel has a chip bonding region, and the display panel includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group sequentially arranged in the chip bonding region. The display panel further includes an organic layer disposed in the chip bonding region. The organic layer includes a first boundary and a second boundary. Here, the first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, where a ≥ 30 μm. The second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, where b ≥ 30 μm. The display panel and the display device provided by the present application can improve the problem of film layer peeling in the chip bonding region, and thus improve the problem of abnormal chip output signals caused by film layer peeling, and can improve the display quality.

Brief Description of the Drawings

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Figure 1

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Embodiments for Carrying Out the Invention

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is obvious that the described embodiments are only a part of the embodiments of the present application and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without inventive efforts belong to the protection scope of the present application. It should be understood that the embodiments for carrying out the invention described in this specification are only for the purpose of explaining and interpreting the present application and are not intended to be limiting. In the present application, unless otherwise stated, orientation terms such as "upper" and "lower" usually refer to the upper and lower in the state where the device is actually used or the operating state, especially the direction of the drawings in the accompanying drawings. On the other hand, "inner" and "outer" refer to the outline of the device.

[0018] Numerous different embodiments or examples are provided for implementing various configurations of the present application by the following disclosure. To simplify the disclosure of the present application, specific exemplary components and configurations are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may refer to reference numerals and / or letters repeatedly in various examples, and such repetition is for the purpose of simplification and clarification and does not itself indicate the relationship between the various embodiments and / or configurations discussed. Additionally, examples of various specific processes and materials are provided herein, but those skilled in the art can understand the use of other processes and / or other materials. Each will be described in detail below. Note that the order of description of the following examples does not limit the preferred order of the examples.

[0019] FIG. 1 is a top schematic view showing a display area and a chip bonding area of a display panel provided by Embodiment 1 of the present application. Referring to FIG. 1, Embodiment 1 of the present application provides a display panel 01, and the display panel 01 has a display area 10 and a chip bonding area 20. Here, the display area 10 includes a plurality of data lines and a plurality of scanning lines, and the data lines and the scanning lines are arranged such that the orthographic projections in the display area 10 intersect. The chip bonding area 20, also called a bonding area, is provided with a plurality of electrical elements such as bonding terminals, test terminals, and multiplexers. The number of the same type of electrical elements may be plural, and a plurality of the same type of electrical elements may form an electrical element group. Here, the bonding terminal is electrically connected to a chip, a data line, and / or a scanning line of the display panel 01 through a bonding process. For example, the type of the bonding terminal may be an input terminal electrically connected to the chip, or an output terminal electrically connected to the data line and / or the scanning line. The input terminal and the output terminal belong to different types of electrical components. The test terminal is electrically connected to a test circuit in the manufacturing process of the display panel 01 and is used to detect the display performance of the display panel 01. In order to simplify the circuit configuration of the display panel 01, the multiplexer is used to realize a multiplexing function.

[0020] FIG. 2 is a top schematic view showing electrical elements and organic layers in a chip bonding region provided by Example 1 of the present application. FIG. 3 is a schematic view showing a film layer structure of a display panel provided by Example 1 of the present application. When combined with what is shown in FIGS. 1-3, in some embodiments of the present application, the display panel 01 has a chip bonding region 20, and the display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23, and an input terminal group 24 that are sequentially arranged in the chip bonding region 20. The display panel 01 further includes an organic layer 140 disposed in the chip bonding region 20. The organic layer 140 includes a first boundary 141 and a second boundary 142. Here, the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, and the distance between the first boundary 141 and the output terminal group 21 is a, where a ≥ 30 μm. The second boundary 142 is located between the test terminal group 23 and the input terminal group 24, and the distance between the second boundary 142 and the input terminal group 24 is b, where b ≥ 30 μm.

[0021] In the related art, when performing a bonding process, it is necessary to crimp bonding terminals and / or other terminals. Usually, since the terminals have a certain thickness, during the crimping process, the terminals are deformed under pressure, and this deformation pulls the film layers near the terminals, which in turn causes a peeling phenomenon or a peeling tendency between the film layers. Since the test environment of the double 85 test / HAST test is a high-temperature and high-humidity environment, the degree of peeling between the film layers is further intensified, resulting in abnormal chip output signals, generating vertical bright lines on the OLED display panel, and affecting the display quality of the display panel 01.

[0022] The researchers of the present application have found through many experiments that the organic layer 140 is an important film layer that is most likely to cause peeling problems among many film layers. On the other hand, in the display panel 01 of the present application, since the distance between the first boundary 141 and the output terminal group 21 is 30 μm or more, the distance between the first boundary 141 and the output terminals of the output terminal group 21 can be maintained at or above the minimum safety distance. Therefore, when bonding the output terminal group 21, it is possible to improve the problem that the output terminals of the output terminal group 21 are deformed under pressure and pull the first boundary 141 to cause a peeling problem. As a result, the possibility of abnormality of the chip output signal can be reduced, and the display quality of the display panel 01 can be improved. On the other hand, since the distance between the second boundary 142 and the input terminal group 24 is 30 μm or more, the distance between the second boundary 142 and the input terminals of the input terminal group 24 can be maintained at or above the minimum safety distance. Therefore, when bonding the input terminal group 24, it is possible to improve the problem that the input terminals of the input terminal group 24 are deformed under pressure and pull the second boundary 142 to cause a peeling problem. As a result, the possibility of abnormality of the chip output signal can be reduced, and the display quality of the display panel 01 can be improved.

[0023] As an example, the arrangement directions of the output terminal group 21, the multiplexer 22, the test terminal group 23, and the input terminal group 24 are the first direction, and the first direction is parallel to the data line. Here, the output terminal group 21 includes a plurality of output terminals, and the plurality of output terminals are sequentially arranged along the second direction. The test terminal group 23 includes a plurality of test terminals, and the plurality of test terminals are sequentially arranged along the second direction. The first direction and the second direction are arranged such that the orthographic projections in the chip bonding region 20 intersect.

[0024] In some embodiments of the present application, no electrostatic prevention circuit is arranged between the output terminal group 21 and the input terminal group 24.

[0025] In related technologies, the chip bonding region 20 usually has a larger layout area and is often equipped with an electrostatic prevention circuit that reduces the distance between the terminals and the organic layer 140. In the display panel 01 provided by the present application, since the electrostatic protection circuit is not arranged between the output terminal group 21 and the input terminal group 24, the layout area of other electrical elements between the output terminal group 21 and the input terminal group 24 can be increased, the degree of freedom in layout design is greatly improved, and the distance between the first boundary 141 and the output terminal group 21 can be 30 μm or more, and the distance between the second boundary 142 and the input terminal group 24 can be 30 μm or more.

[0026] In some embodiments of the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is continuously arranged.

[0027] In the display panel provided by the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is continuously arranged, whereby the integrity and stability of the organic layer 140 can be improved.

[0028] In some embodiments of the present application, a = b.

[0029] In the display panel 01 provided by the present application, a = b, that is, the distance between the first boundary 141 and the output terminal group 21 is equal to the distance between the second boundary 142 and the input terminal group 24. Thereby, the uniformity of the film layer design of the display panel 01 can be improved, which is beneficial to the improvement of production efficiency, and ultimately the manufacturing cost of the display panel 01 is reduced.

[0030] In some embodiments of the present application, the display panel 01 includes a substrate 100, a first conductive layer 110, an interlayer insulating film layer 120, a second conductive layer 130, an organic layer 140, a third conductive layer 150, a passivation layer 160, and a fourth conductive layer 170 that are sequentially stacked and arranged in the chip bonding region 20.

[0031] Preferably, the substrate 100 may be a flexible substrate or a rigid substrate. In the present application, the material of the substrate 100 is not limited, and the material may be an organic material or an inorganic material. The first conductive layer 110 is, for example, arranged in the same layer as the gate layer of the display region 10. The gate layer includes a gate. The second conductive layer 130 is, for example, arranged in the same layer as the first source-drain layer of the display region 10. The first source-drain layer includes a first source electrode and a first drain electrode. The third conductive layer 150 is, for example, arranged in the same layer as the second source-drain layer of the display region 10. The second source-drain layer includes a second source electrode and a second drain electrode.

[0032] In some embodiments of the present application, the organic layer 140 covers the multiplexer 22 and protects the components of the multiplexer 22. The organic layer 140 does not cover the test terminal in order to facilitate an operator to test the display panel 01 by the test terminal during the manufacturing process of the display panel 01.

[0033] In some embodiments of the present application, the organic layer 140 is integrally formed.

[0034] In the related art, the organic layer 140 in the chip bonding region 20 has a double film layer structure. The double film layer structure increases the thickness of the organic layer 140, the structure is more complex, and the organic layer 140 increases the peeling risk in the bonding process and the upper limit of expansion in the high temperature and high humidity environment created by the double 85 test / HAST test. In the display panel 01 provided by the present application, since the organic layer 140 is integrally formed, the organic layer 140 has a single film layer structure, thereby reducing the strain difference value between the organic layer 140 and other film layers during the bonding process and the double 85 test / HAST test process.

[0035] Figure 4 is a simulation data diagram showing the strain difference value between the organic layer and the interlayer dielectric layer in the pressure-receiving and thermal expansion states provided by Example 1 of the present application. As shown in Figure 4, in the pressure-receiving state during bonding, the strain difference value between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 of the double organic layer 140 reaches 6.872E-04. On the other hand, the strain difference value between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 of the single organic layer 140 is only 4.771E-04, and the strain difference value has decreased significantly. In the thermal expansion state of the double 85 test / HAST test, the strain difference value between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 of the double organic layer 140 reaches 7.149E-04. On the other hand, the strain difference value between the organic layer 140 and the interlayer dielectric layer 120 in the display panel 01 of the single organic layer 140 is only 3.408E-04, and the strain difference value has decreased significantly.

[0036] In some embodiments of the present application, the thickness of the organic layer 140 is 4 μm or less.

[0037] Specifically, in the prior art, since the thickness of each sub-film layer in the organic layer 140 in the chip bonding region 20 is 2 μm or more, the thickness of the organic layer 140 having a double film layer structure is 4 μm or more. By reducing the thickness of the organic layer 140, the present application can further reduce the strain difference value between the organic layer 140 and other film layers during the bonding process and the double 85 test / HAST test process.

[0038] On the other hand, the present application provides a display device, which includes a housing and the display panel 01 described in any of the above. Here, the housing has an accommodation space, and the display panel 01 is disposed in the accommodation space.

[0039] Example 2

[0040] FIG. 5 is a top schematic view showing an electrical element and an organic layer in a chip bonding region provided by Example 2 of the present application. FIG. 6 is a schematic view showing a film layer structure of a display panel provided by Example 2 of the present application. When combined with what is shown in FIGS. 1, 5, and 6, Example 2 of the present application provides a display panel 01 and a display device, the display panel 01 has a chip bonding region 20, the display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23, and an input terminal group 24 sequentially arranged in the chip bonding region 20, the display panel 01 further includes an organic layer 140 arranged in the chip bonding region 20, the organic layer 140 includes a first boundary 141 and a second boundary 142, here, the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, the distance between the first boundary 141 and the output terminal group 21 is a, and a≥30 μm, the second boundary 142 is located between the test terminal group 23 and the input terminal group 24, the distance between the second boundary 142 and the input terminal group 24 is b, and b≥30 μm, the display panel 01 includes a housing and the display panel 01, here, the housing has an accommodation space, and the display panel 01 is arranged in the accommodation space.

[0041] Note that the configurations of the display panel 01 and the display device provided by Example 2 of the present application are similar to the configurations of the display panel 01 and the display device provided by Example 1 of the present application, and descriptions of the same parts for Example 2 of the present application are omitted.

[0042] What is different is that in some embodiments of the present application, the organic layer 140 located between the first boundary 141 and the second boundary 142 is discontinuously arranged. Here, the display panel 01 further includes a dummy terminal group 25 arranged in the chip bonding region 20. The dummy terminal group 25 is located between the multiplexer 22 and the test terminal group 23. The organic layer 140 includes a third boundary 143 and a fourth boundary 144. Here, the third boundary 143 is located between the multiplexer 22 and the dummy terminal group 25, and the distance between the third boundary 143 and the dummy terminal group 25 is c, where c > m / 6, and m is the distance between the third boundary 143 and the first boundary 141. The fourth boundary 144 is located between the test terminal group 23 and the dummy terminal group 25, and the distance between the fourth boundary 144 and the test terminal group 23 is d, where d > n / 6, and n is the distance between the fourth boundary 144 and the second boundary 142.

[0043] In the prior art, the dummy terminal group 25 serves as an auxiliary support during the bonding process. Since the dummy terminal group 25 is located between the multiplexer 22 and the test terminal group 23, the organic layer 140 located near the dummy terminal group 25 is more easily pulled during the bonding pressure application, and it has been found that the organic layer 140 has a peeling problem at the third boundary 143 and the fourth boundary 144.

[0044] This application is designed based on the specific position of the dummy terminal group 25 such that the distance between the third boundary 143 and the dummy terminal group 25 is at least one-sixth of the distance between the third boundary 143 and the first boundary 141, and the distance between the fourth boundary 144 and the dummy terminal group 25 is at least one-sixth of the distance between the fourth boundary 144 and the second boundary 142. Thereby, the distances between the dummy terminals 251 in the third boundary 143, the fourth boundary 144, and the dummy terminal group 25 can all be maintained at a safe distance or more. Therefore, in the bonding process between the output terminal group 21 and the input terminal group 24, it is possible to improve the problem of pulling and peeling the third boundary 143 and the fourth boundary 144 due to the pressure-induced deformation of the dummy terminals 251 in the dummy terminal group 25, and thus reduce the possibility of abnormal chip output signals and improve the display quality of the display panel 01.

[0045] In some embodiments of this application, the dummy terminal group 25 includes a plurality of dummy terminals 251, and the plurality of dummy terminals 251 form a plurality of dummy terminal rows. Here, let c = d ≧ 50 μm, and both m / 6 and n / 6 are less than 50 μm.

[0046] In the display panel 01 provided by this application, the plurality of dummy terminals 251 form a plurality of dummy terminal rows. In the bonding process of the output terminals, the dummy terminal row closest to the output terminal group 21 can play a role in auxiliary support. In the bonding process of the input terminals, the dummy terminal row closest to the input terminal group 24 can play a role in auxiliary support.

[0047] In the display panel 01 provided by this application, since c = d ≧ 50 μm, the distance between the third boundary and the dummy terminal group and the distance between the fourth boundary and the test terminal group are both d, far exceeding the 30 μm as the safe distance in Embodiment 1. Thereby, the problem of peeling caused by the dummy terminal group being more pressured and having a large deformation amount can be improved, and the stability of the display panel can be improved.

[0048] Also, since c = d, that is, the distance between the third boundary 143 and the output terminal group 21 is equal to the distance between the fourth boundary 144 and the input terminal group 24, the uniformity of the film layer design of the display panel 01 can be improved, which is advantageous for improving production efficiency, and ultimately realizes the effect of reducing the manufacturing cost of the display panel 01.

[0049] In some embodiments of the present application, the organic layer 140 is not disposed between any two adjacent dummy terminal rows.

[0050] In the display panel 01 provided by the present application, since the organic layer 140 is not disposed between any two adjacent dummy terminal rows, the probability of film layer peeling during pressure and thermal expansion can be significantly reduced in the region between two adjacent dummy terminal rows.

[0051] Furthermore, a = b = c = d.

[0052] In the display panel 01 provided by the present application, a = b = c = d, that is, the distance between the first boundary 141 and the output terminal group 21, the distance between the second boundary 142 and the input terminal group 24, the distance between the third boundary 143 and the dummy terminal group 25, and the distance between the fourth boundary 144 and the test terminal group 23 are all equal. Therefore, the uniformity of the film layer design of the display panel 01 can be improved, which is advantageous for improving production efficiency, and ultimately realizes the effect of reducing the manufacturing cost of the display panel 01.

[0053] Example 3

[0054] FIG. 7 is a top schematic view showing an electrical element and an organic layer in a chip bonding region provided by Embodiment 3 of the present application. FIG. 8 is a schematic view showing a film layer structure of a display panel provided by Embodiment 3 of the present application. In combination with what is shown in FIGS. 1, 7 and 8, Embodiment 3 of the present application provides a display panel 01 and a display device. The display panel 01 has a chip bonding region 20. The display panel 01 includes an output terminal group 21, a multiplexer 22, a test terminal group 23 and an input terminal group 24 sequentially arranged in the chip bonding region 20. The display panel 01 further includes an organic layer 140 arranged in the chip bonding region 20. The organic layer 140 includes a first boundary 141 and a second boundary 142. Here, the first boundary 141 is located between the multiplexer 22 and the output terminal group 21, and the distance between the first boundary 141 and the output terminal group 21 is a, where a≧30 μm. The second boundary 142 is located between the test terminal group 23 and the input terminal group 24, and the distance between the second boundary 142 and the input terminal group 24 is b, where b≧30 μm. The display panel 01 includes a housing and the display panel 01. Here, the housing has an accommodation space, and the display panel 01 is arranged in the accommodation space.

[0055] It should be noted that the configurations of the display panel 01 and the display device provided by Embodiment 3 of the present application are similar to those of the display panel 01 and the display device provided by Embodiment 2 of the present application. For the same parts in Embodiment 3 of the present application, the description will be omitted.

[0056] The difference is that in some embodiments of the present application, the dummy terminal group 25 includes a plurality of dummy terminals 251, and the plurality of dummy terminals 251 form one dummy terminal row. Here, c = d≧80 μm.

[0057] In the display panel 01 provided by the present application, since a plurality of the dummy terminals 251 form one dummy terminal row, the dummy terminal row needs to be pressed to play a role of auxiliary support in the bonding process between the output terminal and the input terminal. The present application further increases the distance between the third boundary 143 and the dummy terminal group 25, and further increases the distance between the fourth boundary 144 and the dummy terminal group 25, thereby improving the problem that the risk of film layer peeling increases due to the increase in the deformation amount of the dummy terminal row caused by repeated pressure.

[0058] Moreover, since a plurality of the dummy terminals 251 form one dummy terminal row, the layout area of the dummy terminal group 25 can be reduced, and thus the distance between the third boundary 143 and the dummy terminal group 25 can be made larger, and the distance between the fourth boundary 144 and the dummy terminal group 25 can be made larger, so as to reduce the possibility of pulling the first boundary 141 due to the pressure deformation of the dummy terminal 251 in the dummy terminal group 25 and causing a peeling problem, and thus the possibility of abnormality of the chip output signal can be reduced, and the display quality of the display panel 01 can be improved.

[0059] In addition, in order to make c = d, that is, since the distance between the third boundary 143 and the output terminal group 21 is equal to the distance between the fourth boundary 144 and the input terminal group 24, the uniformity of the film layer design of the display panel 01 can be improved, which is advantageous for improving the production efficiency, and thus the effect of reducing the manufacturing cost of the display panel 01 is realized.

[0060] Furthermore, let a = b = c = d.

[0061] In the display panel 01 provided by the present application, a = b = c = d, that is, the distance between the first boundary 141 and the output terminal group 21, the distance between the second boundary 142 and the input terminal group 24, the distance between the third boundary 143 and the dummy terminal group 25, and the distance between the fourth boundary 144 and the test terminal group 23 are all equal. Therefore, the uniformity of the film layer design of the display panel 01 can be improved, which is beneficial to the improvement of production efficiency, and ultimately realizes the effect of reducing the manufacturing cost of the display panel 01.

[0062] As described above, the present application provides a display panel and a display device. The display panel has a chip bonding area. The display panel includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group sequentially arranged in the chip bonding area. The display panel further includes an organic layer disposed in the chip bonding area. The organic layer includes a first boundary and a second boundary. Here, the first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, where a ≥ 30 μm. The second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, where b ≥ 30 μm. The display panel and the display device provided by the present application can improve the problem of film layer peeling in the chip bonding area, and ultimately improve the problem of abnormal chip output signals caused by film layer peeling, and can improve the display quality.

[0063] As described above, the display panel and the display device provided by the embodiments of the present application have been described in detail. In this specification, specific examples are used to describe the principle and embodiments of the present application. The description of the above embodiments is for the purpose of helping to understand the method and its core idea of the present application. In addition, those skilled in the art can make changes in specific embodiments and application scopes based on the idea of the present application, and the disclosure of this specification should not be construed as limiting the present application.

Explanation of Reference Numerals

[0064] 01 Display panel 10 Indication area 20 Chip bonding area 21 Output terminal group 22 Multiplexer 23 Test terminal group 24 Input terminal group 25Dummy terminal group 251Dummy terminal 100 Substrate 110 First conductive layer 120 Interlayer dielectric layer 130 Second conductive layer 140 Organic layer 141 First boundary 142 Second boundary 143 Third boundary 144 Fourth boundary 150 Third conductive layer 160 Passivation layer 170 Fourth conductive layer

Claims

1. A display panel, wherein the display panel has a chip bonding region, and includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group that are sequentially arranged in the chip bonding region, and the display panel further includes an organic layer disposed in the chip bonding region, and the organic layer includes a first boundary and a second boundary, wherein the first boundary is located between the multiplexer and the output terminal group, and a distance between the first boundary and the output terminal group is a, and a≧30μm, wherein the second boundary is located between the test terminal group and the input terminal group, and a distance between the second boundary and the input terminal group is b, and b≧30μm, A display panel.

2. An electrostatic prevention circuit is not disposed between the output terminal group and the input terminal group, The display panel according to Claim 1.

3. The organic layer located between the first boundary and the second boundary is continuously arranged, The display panel according to Claim 2.

4. The organic layer located between the first boundary and the second boundary is discontinuously arranged, wherein the display panel further includes a dummy terminal group disposed in the chip bonding region, the dummy terminal group is located between the multiplexer and the test terminal group, and the organic layer includes a third boundary and a fourth boundary, wherein the third boundary is located between the multiplexer and the dummy terminal group, and a distance between the third boundary and the dummy terminal group is c, and c>m / 6, where m is a distance between the third boundary and the first boundary, wherein the fourth boundary is located between the test terminal group and the dummy terminal group, and a distance between the fourth boundary and the test terminal group is d, and d>n / 6, where n is a distance between the fourth boundary and the second boundary, The display panel according to Claim 3.

5. The dummy terminal group includes a plurality of dummy terminals, the plurality of dummy terminals form a plurality of dummy terminal rows, and c = d≧50μm, The display panel according to Claim 4.

6. The organic layer is not disposed between any two adjacent dummy terminal rows, The display panel according to Claim 5.

7. The dummy terminal group includes a plurality of dummy terminals, the plurality of dummy terminals form one dummy terminal row, and c = d≧80μm, The display panel according to Claim 4.

8. Let a = b = c = d, The display panel according to Claim 4.

9. The organic layer is integrally formed. The display panel according to claim 1.

10. The thickness of the organic layer is 4 μm or less. The display panel according to claim 1.

11. A display device, The display device includes a housing and a display panel. The housing has an accommodation space, the display panel is disposed in the accommodation space, the display panel has a chip bonding region, and the chip bonding region includes an output terminal group, a multiplexer, a test terminal group, and an input terminal group arranged in sequence. The display panel further includes an organic layer disposed in the chip bonding region. The organic layer includes a first boundary and a second boundary. The first boundary is located between the multiplexer and the output terminal group, and the distance between the first boundary and the output terminal group is a, where a ≥ 30 μm. The second boundary is located between the test terminal group and the input terminal group, and the distance between the second boundary and the input terminal group is b, where b ≥ 30 μm. Display device.

12. An electrostatic prevention circuit is not disposed between the output terminal group and the input terminal group. The display device according to claim 11.

13. The organic layer located between the first boundary and the second boundary is continuously disposed. The display device according to claim 12.

14. The organic layer located between the first boundary and the second boundary is discontinuously disposed. The display panel further includes a dummy terminal group disposed in the chip bonding region. The dummy terminal group is located between the multiplexer and the test terminal group. The organic layer includes a third boundary and a fourth boundary. The third boundary is located between the multiplexer and the dummy terminal group, and the distance between the third boundary and the dummy terminal group is c, where c > m / 6, and m is the distance between the third boundary and the first boundary. The fourth boundary is located between the test terminal group and the dummy terminal group, and the distance between the fourth boundary and the test terminal group is d, where d > n / 6, and n is the distance between the fourth boundary and the second boundary. The display device according to claim 13.

15. The dummy terminal group includes a plurality of dummy terminals. The plurality of dummy terminals form a plurality of dummy terminal rows, and c = d ≥ 50 μm. The display device according to claim 14.

16. No organic layer is disposed between any two adjacent dummy terminal rows. ​ The display device according to claim 15.

17. The dummy terminal group includes a plurality of dummy terminals, the plurality of dummy terminals form one dummy terminal row, and c = d ≧ 80 μm. The display device according to claim 14.

18. Let a = b = c = d. The display device according to claim 14.

19. The organic layer is integrally formed. The display device according to claim 11.

20. The thickness of the organic layer is 4 μm or less. The display device according to claim 11.

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