Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate (100 / 600) includes a base substrate (101 / 601) and a pixel circuit (110 / 610) located on the base substrate (101 / 601) and including a storage capacitor (C), and the storage capacitor (C) includes opposing first and second electrodes (Cst1, Cst2); the display substrate (100 / 600) further includes a conductive film layer (107 / 607), the conductive film layer (107 / 607) includes a first conductive portion (1074 / 6072), the first conductive portion (1074 / 6072) includes a main body portion (1074a / 6072a) corresponding to two of the second electrodes (Cst2) and a bridge portion (1074b / 6072b) connecting the two second electrodes (Cst2), and the first conductive portion (1074 / 6072) includes a gap (1074c / 6072c) between the two second electrodes (Cst2), and the provision of the gap (1074c / 6072c) can improve the pixel transmittance.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device.

Background Art

[0002] Organic Light Emitting Diode (abbreviated as OLED) and Quantum-dot Light Emitting Diodes (abbreviated as QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light and thin, foldable, and low cost, etc., so they have high development potential. With the continuous development of display technology, flexible display devices that use OLED or QLED as light-emitting devices and perform signal control by Thin Film Transistor (abbreviated as TFT) have already become the mainstream products in the conventional display field. With the continuous development of display technology, the optimization of display effects has already tended to be inevitable.

Summary of the Invention

Means for Solving the Problems

[0003] At least one embodiment of the present disclosure provides a display substrate and a display device. The conductive film layer on the display substrate includes a first conductive part, and the first conductive part includes a gap between two second plates. By setting the gap, the pixel transmittance can be improved, and the display substrate shields the N1 node with a first electrode transfer line or a first power signal line located in the second conductive layer (SD2). The second conductive layer (SD2) is connected to a stable signal, and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1). Therefore, the influence of the nearby data signal on the N1 node can be reduced, that is, the influence of the data signal on the N1 node is shielded, and further, the problem that the display panel cannot be normally displayed caused by the jump of the data signal affecting the voltage of the N1 node can be improved.

[0004] At least one embodiment of the present disclosure provides a display substrate, the display substrate includes a base substrate, and a pixel circuit located on the base substrate and including a storage capacitor, the storage capacitor includes opposing first and second electrodes, and a pixel circuit, the display substrate further includes a conductive film layer, the conductive film layer includes a first conductive portion, the first conductive portion includes a main body portion corresponding to the two second electrodes and a bridge portion connecting the two second electrodes, and the first conductive portion includes a gap between the two second electrodes.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further includes a driving transistor, the display substrate further includes a first conductive layer, a second conductive layer, and a first semiconductor layer, the first conductive layer includes a first connection structure, the first connection structure includes opposing first and second ends, the first end is connected to the first semiconductor layer, the second end is electrically connected to the gate electrode of the driving transistor and the first electrode of the storage capacitor, the first conductive layer is located on a side of the first semiconductor layer away from the base substrate, the second conductive layer is located on a side of the first conductive layer away from the base substrate, and a positive projection of the second conductive layer on the base substrate overlaps at least partially with a positive projection of at least a part of the first connection structure on the base substrate.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, a positive projection of the first conductive layer on the base substrate and a positive projection of the gap on the base substrate do not have an overlapping portion, and a positive projection of the second conductive layer on the base substrate and a positive projection of the gap on the base substrate do not have an overlapping portion.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, a positive projection of the second electrode on the base substrate and a positive projection of the first electrode on the base substrate at least partially overlap.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, an opening is formed in the second electrode plate, and a positive projection of the via hole connected between the gate electrode of the driving transistor and the first connection structure on the base substrate is located within a positive projection of the opening on the base substrate, whereby the conductive structure in the via hole and the second electrode plate are insulated from each other.

[0009] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of sub-pixels, each of the sub-pixels includes the pixel circuit and the light-emitting element, the first conductive layer is located between the first electrode of the light-emitting element and the first semiconductor layer, and the second conductive layer is located between the first conductive layer and the first electrode of the light-emitting element.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive layer includes data lines spaced apart from each other, a first electrode transfer line, and a first power signal line, the first electrode transfer line is connected to the first electrode of the light-emitting element, and a positive projection of the first electrode transfer line on the base substrate overlaps a positive projection of a part of the first connection structure on the base substrate.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first electrode transfer line is elongate and extends entirely along an extending direction of the data line closest to it, the first connection structure is in a folded line shape extending toward a side away from the data line closest to it, includes a portion overlapping the first electrode transfer line and a portion not overlapping the first electrode transfer line, and the non-overlapping portion is farther away from the data line closest to it than the overlapping portion.

[0012] For example, in a display substrate provided by at least one embodiment of the present disclosure, the extending direction of the data line is the first direction, the direction orthogonal or substantially orthogonal to the extending direction of the data line is the second direction, the first conductive layer further includes a power signal connection line, the power signal connection line includes a main body portion and a branch portion, the overall extending direction of the power signal connection line is parallel to the second direction, the extending direction of the branch portion is parallel to the first direction, the first power signal line includes a block portion and a strip portion that extends entirely along the first direction and connects the adjacent block portions, and the main body portion of the power signal connection line is connected to the first power signal line to form a grid shape.

[0013] For example, in a display substrate provided by at least one embodiment of the present disclosure, the strip portion includes a first strip portion and a second strip portion that are oppositely installed, and a third strip portion that connects the first strip portion and the second strip portion, the extending directions of the first strip portion and the second strip portion are parallel to the first direction, and the third strip portion connects an intermediate region between the first strip portion and the second strip portion.

[0014] For example, in a display substrate provided by at least one embodiment of the present disclosure, the strip portion includes a hollow structure.

[0015] For example, in a display substrate provided by at least one embodiment of the present disclosure, the width of the block portion in the second direction is larger than the overall width of the strip portion in the second direction.

[0016] For example, in a display substrate provided by at least one embodiment of the present disclosure, the second polar plate is electrically connected to the first power signal line.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further includes a first transistor, a second transistor, a sixth transistor, and a seventh transistor. A first pole of the first transistor is connected to a gate electrode of the driving transistor. A second pole of the first transistor is connected to a first initial signal line. A first pole of the second transistor is connected to the gate electrode of the driving transistor. A second pole of the second transistor is connected to a second pole of the driving transistor. A first pole of the sixth transistor is connected to the second pole of the driving transistor. A first pole of the seventh transistor is connected to a second pole of the sixth transistor. A second pole of the seventh transistor is connected to a second initial signal line. The display substrate is located between the base substrate and the second conductive layer and is a first active layer including a third active part, a sixth active part, and a seventh active part. The third active part is configured to form a channel region of the driving transistor. The sixth active part is configured to form a channel region of the sixth transistor. The seventh active part is configured to form a channel region of the seventh transistor. The display substrate further includes a second active layer located between the first active layer and the second conductive layer and including a first active part and a second active part. The first active part is configured to form a channel region of the first transistor. The second active part is connected to the first active part and is configured to form a channel region of the second transistor.

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, the display substrate includes a plurality of repeating units distributed along the first direction and the second direction. Each repeating unit includes two of the pixel circuits. The two pixel circuits include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are installed in mirror symmetry. Each pixel circuit further includes a fourth transistor and a fifth transistor. A first pole of the fourth transistor is connected to the data line. A second pole of the fourth transistor is connected to a first pole of the driving transistor. A first pole of the fifth transistor is connected to the first power signal line. A second pole of the fifth transistor is connected to a first pole of the driving transistor. The first active layer further includes a fourth active part connected to one side of the third active part and configured to form a channel region of the fourth transistor, and a fifth active part configured to form a channel region of the fifth transistor.

[0019] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a third conductive layer. The orthographic projection of the third conductive layer on the base substrate extends along the second direction and overlaps with the orthographic projection of the fourth active portion on the base substrate. A part of the structure thereof is a second gate line for forming the gate electrode of the fourth transistor. The orthographic projection of the third conductive layer on the base substrate extends along the second direction and overlaps with the orthographic projection of the sixth active portion on the base substrate. A part of the structure thereof is a light emission control signal line for forming the gate electrode of the sixth transistor. The orthographic projection of the third conductive layer on the base substrate extends along the second direction and overlaps with the orthographic projection of the seventh active portion on the base substrate. The third conductive layer is a second reset signal line, and a part of the structure of the second reset signal line is used to form the gate electrode of the seventh transistor. The second gate line in the pixel circuit of this row is multiplexed with the second reset signal line in the pixel circuit of the adjacent row. The orthographic projection of the third conductive layer on the base substrate overlaps with the orthographic projection of the third active portion on the base substrate, and includes a second conductive portion configured to form the gate electrode of the driving transistor and the first electrode plate of the storage capacitor. In the same pixel circuit, the orthographic projection of the second conductive portion on the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the light emission control signal line on the base substrate. The orthographic projection of the second reset signal line on the base substrate is located on the side away from the orthographic projection of the second conductive portion of the orthographic projection of the light emission control signal line on the base substrate.

[0020] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a fourth conductive layer, the fourth conductive layer is located between the second active layer and the second conductive layer, the orthographic projection on the base substrate overlaps with the orthographic projection of the first active part on the base substrate, and a first reset signal line configured such that a part of its structure forms the top gate of the first transistor; and a first gate line, the orthographic projection on the base substrate overlaps with the orthographic projection of the second active part on the base substrate, and a part of its structure is configured to form the top gate of the second transistor. In the same pixel driving circuit, the orthographic projection of the first gate line on the base substrate is located between the orthographic projection of the second conductive part on the base substrate and the orthographic projection of the second gate line on the base substrate, and the orthographic projection of the first reset signal line on the base substrate is located on the side away from the orthographic projection of the second conductive part on the base substrate of the orthographic projection of the second gate line on the base substrate.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the conductive film layer further includes a first initial signal line, the orthographic projection on the base substrate is located on the side away from the orthographic projection of the second conductive part on the base substrate of the orthographic projection of the first reset signal line on the base substrate; a third reset signal line connected to the first reset signal line through a via hole, the orthographic projection on the base substrate overlaps with the orthographic projection of the first active part on the base substrate, and a part of its structure is configured to form the bottom gate of the first transistor; and a third gate line, the orthographic projection on the base substrate overlaps with the orthographic projection of the second active part on the base substrate, and a part of its structure is configured to form the bottom gate of the second transistor.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. Two of the second sub-pixels constitute a second sub-pixel pair. The two second sub-pixels in one second sub-pixel pair are a first pixel block and a second pixel block respectively, and the first pixel block and the second pixel block are alternately arranged along the first direction or the second direction. The plurality of sub-pixels include a plurality of minimum repeating units. One minimum repeating unit includes one first sub-pixel, one first pixel block, one second pixel block, and one third sub-pixel.

[0023] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a first electrode layer. The first electrode layer is located on the side of the second conductive layer away from the base substrate. The first electrode layer includes a plurality of electrode portions. Each electrode portion includes a main body portion and an additional portion that are connected. The orthographic projection of the additional portion on the base substrate at least partially overlaps with the orthographic projection of the first electrode transfer line on the base substrate. Each electrode portion corresponds to one of the first sub-pixel, the first pixel block, the second pixel block, and the third sub-pixel.

[0024] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of electrode portions include first electrode portions, second electrode portions, and third electrode portions of three different colors. The first electrode portion corresponds to the first sub-pixel, the second electrode portion corresponds to any one of the first pixel block and the second pixel block, the third electrode portion corresponds to the third sub-pixel, and the overlapping area of the orthographic projection of the first electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate is larger than the overlapping area of the orthographic projection of the second electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate, and is also larger than the overlapping area of the orthographic projection of the third electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate. The overlapping area of the orthographic projection of the third electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate is larger than the overlapping area of the orthographic projection of the second electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first electrode portion corresponds to a blue sub-pixel that emits blue light, the second electrode portion corresponds to a green sub-pixel that emits green light, and the third electrode portion corresponds to a red sub-pixel that emits red light.

[0026] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive layer further includes a plurality of second connection structures. The plurality of second connection structures are installed in one-to-one correspondence with the plurality of electrode portions, and the electrode portion is connected to the corresponding second connection structure through a via hole.

[0027] For example, in the display substrate provided by at least one embodiment of the present disclosure, the sub-pixel further includes a shielding portion located on the side away from the base substrate of the active semiconductor pattern of the driving transistor, and the orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active semiconductor pattern of the driving transistor on the base substrate.

[0028] For example, at least one embodiment of the present disclosure further provides a display device including the display substrate described in any one of the above items.

[0029] To more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description relate only to some embodiments of the present disclosure and do not limit the present disclosure.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and fully described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments that can be obtained by those skilled in the art without creative labor shall fall within the protection scope of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meanings that can be understood by those skilled in the art of the present disclosure. The "first", "second", and similar terms used in the present disclosure do not indicate any order, quantity, or importance, and are only used to distinguish different components. Terms such as "comprising" or "including" mean that the elements or components indicated before such terms cover the elements or components listed after such terms and their equivalents, but do not exclude other elements or components.

[0033] Features such as "orthogonal" and "the same" used in the embodiments of the present disclosure include not only the features of "orthogonal", "the same", etc. in a strict sense, but also situations with a predetermined error such as "substantially orthogonal", "substantially the same", etc. Considering the errors related to measurement and the measurement of specific quantities (i.e., the limitations of the measurement system), it is shown within an acceptable deviation range to a specific value determined by those skilled in the art. The "center" in the embodiments of the present disclosure may include a position strictly located at the geometric center and a position approximately located at the center within a small area around the geometric center. For example, "substantially" can mean within one or more standard deviations, or within 10% or 5% of the said value.

[0034] Low Temperature Polycrystalline Oxide (LTPO) technology can be applied to organic light-emitting diode displays, thereby reducing the power consumption of the display panel. The power consumption of the display panel includes driving power and light-emitting power. A display panel based on LTPO technology has lower driving power than a display panel based on LTPS technology. When a display panel based on LTPS technology displays a still image, it requires 60 Hertz (Hz), but when a display panel based on LTPO technology displays a still image, it can be reduced to 1 Hz, thereby significantly reducing the driving power.

[0035] Based on LTPO technology, some of the transistors in the display panel are oxide transistors (for example, N-type oxide transistors). Since the leakage current of the oxide transistors is small, the voltage (charge) of the capacitor can be maintained for 1 second, thereby realizing a refresh rate of 1 Hz. The leakage current of LTPS transistors is large, so even when driving a still pixel, 60 Hz is required; otherwise, the brightness will decrease significantly. Therefore, LTPO technology is widely applied in display substrates.

[0036] For example, FIG. 1 shows a layout for reducing the influence on the N1 node due to data signal jumps by forming a 3D capacitor within the LTPS pixel circuit. For example, the position of the N1 node is the connection position between the lower electrode plate of the storage capacitor and the gate electrode of the driving transistor. As shown in FIG. 1, in the LTPS pixel circuit design, in order to avoid the N1 node being affected by the data signal, a second gate electrode layer 02 connected to the power signal is added to the right side of the N1 node. The power signal is generated by the power signal line 04, that is, the second gate electrode layer 02 is electrically connected to the power signal line 04. A capacitor can be formed between the second gate electrode layer 02 and the N1 node, thereby preventing the influence on the N1 node when the data signal jumps due to the data line 03. However, since this structural design does not directly overlap the second gate electrode layer 02 and the N1 node, the capacitor formed in this way does not overlap on the plane, forming a spatial 3D capacitor. Since the spatial 3D capacitor is too small, the shielding of the N1 node becomes insufficient. As a result, the influence of the data signal on the N1 node cannot be effectively avoided.

[0037] For example, FIG. 2 shows a layout in which the positive electrode shields the N1 node. As shown in FIG. 2, the positive electrode 05 covers the N1 node. Specifically, as shown in FIG. 2, the positive electrode 05R of the red sub-pixel covers the N1 node, and the additional portion of the positive electrode 05R of the red sub-pixel extends across the data line 03 on the right side of the positive electrode 05R. The positive electrode 05B of the blue sub-pixel covers the N1 node. In order to avoid differences in pixel luminance and ensure the uniformity of display luminance, only the positive electrode 05R of the red sub-pixel and the positive electrode 05B of the blue sub-pixel are made to cover the N1 node, and the positive electrode 05G of the green sub-pixel is not made to shield the N1 node at all.

[0038] Due to the advantages of LTPO technology such as high charge mobility, high pixel reaction speed, and low power consumption, there are many performance specification requirements for LTPO display products. The inventors of the present disclosure note that these performance specifications of LTPO display products are closely related to the circuit design of the product backsheet. For example, the positive transfer line located in the second conductive layer (SD2) can shield the N1 node. The second conductive layer (SD2) is connected to a stable signal, and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1). Therefore, the influence of the nearby data signal on the N1 node can be reduced, that is, the influence of the data signal on the N1 node can be shielded, and further, the problem that the display panel cannot be normally displayed due to the influence of the data signal jump on the voltage of the N1 node can be improved. Moreover, for the red sub-pixel, green sub-pixel, and blue sub-pixel, the N1 node can be shielded by this design, thereby improving the problem of the decrease in the light emission uniformity of the display panel due to the process variation of the transistor.

[0039] The inventors of the present disclosure further note that a horizontal power signal line (horizontal VDD) can be designed in the first conductive layer (SD1), and a vertical power signal line (vertical VDD) can also be designed in the second conductive layer (SD2). The horizontal power signal line and the vertical power signal line intersect to form a mesh-like power signal line, thereby making the signal on the power signal line more stable and also saving the design space.

[0040] For example, at least one embodiment of the present disclosure provides a display substrate, the display substrate including a base substrate and a pixel circuit disposed on the base substrate and including a driving transistor and a storage capacitor, the display substrate further including a first conductive layer, a second conductive layer, and a first semiconductor layer, the first conductive layer including a first connection structure, the first connection structure including an opposing first end and a second end, the first end being connected to the first semiconductor layer, the second end being electrically connected to a gate electrode of the driving transistor and a first electrode plate of the storage capacitor, the first conductive layer being located on a side of the first semiconductor layer away from the base substrate, the second conductive layer being located on a side of the first conductive layer away from the base substrate, and a positive projection of the second conductive layer on the base substrate overlapping at least a part of a positive projection of the first connection structure on the base substrate, the display substrate overlapping a positive projection of the second conductive layer on the base substrate and at least a part of a positive projection of the first connection structure on the base substrate, that is, by shielding at least a part of the N1 node by the first electrode transfer line in the second conductive layer (SD2), the second conductive layer (SD2) is connected to a stable signal, and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1), so that a capacitor is formed between the N1 node and the nearest data line, and the influence of the data signal on the capacitor is small, thereby reducing the influence of the nearby data signal on the N1 node, that is, shielding the influence of the data signal on the N1 node, and further improving the problem that the display panel cannot be normally displayed due to the influence of the data signal jump on the voltage of the N1 node.

[0041] For example, FIG. 3 is a circuit structure schematic diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 3, the pixel circuit 110 includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C.

[0042] For example, as shown in FIG. 3, the first transistor T1 is a first reset transistor T1, the second transistor T2 is a threshold compensation transistor T2, the fourth transistor T4 is a data writing transistor T4, the fifth transistor T5 is a second light emission control transistor T5, the sixth transistor T6 is a first light emission control transistor T6, and the seventh transistor T7 is a second reset control transistor T7.

[0043] For example, the first pole of the first transistor T1 is connected to the N1 node, that is, electrically connected to the gate electrode of the driving transistor T3. The second pole of the first transistor T1 is connected to the first initial signal terminal Vinit1, that is, electrically connected to the first reset signal line to receive a reset signal. The gate electrode of the first transistor T1 is connected to the first reset signal terminal Re1, that is, electrically connected to the reset control signal line to receive a reset control signal. The first pole of the threshold compensation transistor, which is the second transistor T2, is connected to the N1 node, that is, electrically connected to the gate electrode of the driving transistor T3. The second pole of the second transistor T2 is connected to the second pole of the driving transistor T3. The gate electrode of the second transistor T2 is connected to the first gate electrode drive signal terminal G1 to receive a compensation control signal. The gate electrode of the driving transistor T3 is connected to the N1 node, thereby being connected to the first electrode plate of the storage capacitor C, the first pole of the first transistor T1, and the first pole of the second transistor T2. The first pole of the data writing transistor, which is the fourth transistor T4, is connected to the data signal terminal Data to receive a data signal. The second pole of the fourth transistor T4 is connected to the first pole of the driving transistor T3. The gate electrode of the fourth transistor T4 is connected to the second gate electrode drive signal terminal G2 to receive a scanning signal. The first pole of the second light emission control transistor, which is the fifth transistor T5, is connected to the first power supply terminal VDD to receive a first power supply signal. The second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T3. The gate electrode of the fifth transistor T5 is connected to the light emission control signal terminal EM to receive a light emission control signal. The first pole of the first light emission control transistor, which is the sixth transistor T6, is connected to the second pole of the driving transistor T3. The second pole of the sixth transistor T6 is connected to the first pole of the seventh transistor T7. The gate electrode of the sixth transistor T6 is connected to the light emission control signal terminal EM to receive a light emission control signal. The second pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, that is, electrically connected to the second reset power supply signal line to receive a reset signal Vinit. The gate electrode of the seventh transistor T7 is connected to the second reset signal terminal Re2, that is,By being electrically connected to the reset control signal line, it receives the reset control signal. The first plate of the storage capacitor C is connected to the N1 node and electrically connected to the gate electrode of the driving transistor T3. The second plate of the storage capacitor C is connected to the first power supply terminal VDD, that is, connected to the first power supply signal line. The pixel circuit may be connected to the light-emitting element 120. The light-emitting element 120 may be an organic light-emitting diode (OLED). The pixel circuit is used to drive the light-emitting element 120 to emit light. The light-emitting element 120 may be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS, that is, connected to the second power supply signal line.

[0044] For example, the first power supply signal line is a signal line that outputs the voltage signal VDD and can be connected to a voltage source to output a constant voltage signal such as a positive voltage signal. The second power supply signal line is a signal line that outputs the voltage signal VSS and can be connected to a voltage source to output a constant voltage signal such as a negative voltage signal.

[0045] For example, the scan signal and the compensation control signal may be the same. That is, the gate electrode of the data writing transistor T4 and the gate electrode of the threshold compensation transistor T2 are electrically connected to the same signal line to receive the same signal, and the number of signal lines may be reduced. For example, the gate electrode of the data writing transistor T4 and the gate electrode of the threshold compensation transistor T2 may be electrically connected to different signal lines respectively. That is, the gate electrode of the data writing transistor T4 is electrically connected to the second scan signal line (the second gate line), while the gate electrode of the threshold compensation transistor T2 is electrically connected to the first scan signal line (the first gate line). The signals transmitted by the first scan signal line and the second scan signal line may be the same or different. Thereby, the gate electrode of the data writing transistor T4 and the gate electrode of the threshold compensation transistor T2 are individually and independently controlled, and thereby, the flexibility of the control of the pixel circuit is improved.

[0046] For example, even if the light emission control signals input to the first light emission control transistor T6 and the second light emission control transistor T5 are the same, that is, the gate electrode of the first light emission control transistor T6 and the gate electrode of the second light emission control transistor T5 are electrically connected to the same signal line to receive the same signal, the number of signal lines may be reduced. For example, the gate electrode of the first light emission control transistor T6 and the gate electrode of the second light emission control transistor T5 may be electrically connected to different light emission control signal lines respectively. At this time, the signals transmitted by the different light emission control signal lines may be the same or different.

[0047] For example, even if the reset control signals input to the second reset transistor T7 and the first reset transistor T1 are the same, that is, the gate electrode of the second reset transistor T7 and the gate electrode of the first reset transistor T1 are electrically connected to the same signal line to receive the same signal, the number of signal lines may be reduced. For example, the gate electrode of the second reset transistor T7 and the gate electrode of the first reset transistor T1 may be electrically connected to different reset control signal lines respectively. At this time, the signals on the different reset control signal lines may be the same or different.

[0048] For example, the first transistor T1 and the second transistor T2 may be N-type transistors. For example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors. Since the N-type metal oxide transistor has a small leakage current, thereby, in the light-emitting stage, leakage of the N1 node through the first transistor T1 and the second transistor T2 can be avoided. At the same time, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors. For example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon transistors. Since the P-type low-temperature polycrystalline silicon transistor has a high carrier mobility, thereby, it is advantageous for realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals according to the actual situation.

[0049] For example, FIG. 4 is a timing diagram of each node in the driving method of the pixel circuit of FIG. 3. G1 represents the timing of the first gate electrode driving signal terminal G1, G2 represents the timing of the second gate electrode driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the emission control signal terminal EM, and Data represents the timing of the data signal terminal Data. The driving method of the pixel circuit can include a first reset stage t1, a compensation stage t2, a second reset stage t3, and an emission stage t4. In the first reset stage t1, the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N1. In the compensation stage t2, the first gate electrode driving signal terminal G1 outputs a high-level signal, the second gate electrode driving signal terminal G2 outputs a low-level signal. At the same time that the fourth transistor T4 and the second transistor T2 are turned on, the data signal terminal Data outputs a driving signal to write a voltage Vdata + Vth (that is, the sum of the voltages Vdata and Vth) to the node N1. Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6. In the emission stage t4, the emission control signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata + Vth stored in the storage capacitor C.

[0050] In addition, in the embodiments of the present disclosure, each pixel circuit may have a 7T1C (that is, 7 transistors and 1 capacitor) structure shown in FIG. 3, or may have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, an 8T1C structure, or a 9T2C structure. The embodiments of the present disclosure do not limit this.

[0051] For example, the display substrate includes a plurality of repeating units distributed along a first direction and a second direction that intersect each other. Each repeating unit includes two pixel circuits. The two pixel circuits include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are arranged in a substantially mirror-symmetric manner. The pixel circuit described below is described for one of the first pixel circuit and the second pixel circuit.

[0052] For example, the embodiments of the present disclosure provide a display substrate. FIG. 5A is a structural layout of a display substrate according to at least one embodiment of the present disclosure. FIG. 5B is a structural layout of another display substrate according to at least one embodiment of the present disclosure. FIG. 6 is a structural layout of the second conductive layer in FIG. 5B. FIG. 7 is a structural layout of the first conductive layer in FIG. 5B. FIG. 8 is a structural layout when the first conductive layer and the second conductive layer in FIG. 5B are stacked. FIGS. 5A to 7 only exemplarily show a stacked structure schematic diagram or a single-layer structure schematic diagram of some film layers in the display substrate. Other film layers can also include film layers such as the film layer where the gate line is located and the film layer where the light-shielding layer is located. FIG. 5B has an additional light-shielding layer compared to FIG. 5A, and other structural settings are the same.

[0053] For example, as shown in FIGS. 3 and 5B, the display substrate 100 includes a base substrate 101 and a pixel circuit 110 disposed on the base substrate 101 and including a driving transistor T3 and a storage capacitor C. The display substrate 100 further includes a first conductive layer 102, a second conductive layer 103, and a first semiconductor layer 104. The first conductive layer 102 includes a first connection structure 1021, and the first connection structure 1021 includes an opposing first end 1021a and a second end 1021b. The first end 1021a is connected to the first semiconductor layer 104, and the second end 1021b is electrically connected to the gate electrode of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor C. The first conductive layer 102 is located on the side of the first semiconductor layer 104 away from the base substrate 101. The second conductive layer 103 is located on the side of the first conductive layer 102 away from the base substrate 101, and at least a part of the orthographic projection of the second conductive layer 103 on the base substrate 101 overlaps with at least a part of the orthographic projection of the first connection structure 1021 on the base substrate 101. By overlapping at least a part of the orthographic projection of the second conductive layer 103 on the base substrate 101 with at least a part of the orthographic projection of the first connection structure 1021 on the base substrate 101, that is, by shielding at least a part of the first connection structure 1021 (also called the N1 node) with the second conductive layer 103 (also called SD2), a capacitor is directly formed between the second conductive layer 103 and the first connection structure 1021 located in the first conductive layer 102, that is, a capacitor is directly formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also called SD1), thereby forming a capacitor between the N1 node and the data line data closest to it. The light emission control signal line EM and the second initial signal line Vinit2 both transmit stable DC signals. The second conductive layer 103 (SD2) is connected to a stable signal, and within the time of one frame, the signal changes only once. With such a design, when the N1 node is operating normally, the second conductive layer 103 (SD2) directly forms a capacitor with the first conductive layer 102 (also called SD1) at the N1 node location. The second conductive layer 103 (SD2, upper electrode plate) is connected to a stable signal. Due to the characteristics of the capacitor itself, the voltage across both ends of the capacitor does not change suddenly. After the upper electrode plate is connected to a stable DC signal,The signal of the first conductive layer 102 (SD1) at the N1 node, which is the lower electrode plate, can also maintain a stable state, thereby reducing the influence on the N1 node by a data signal in which jumps frequently occur within one frame time. The influence of the data signal on the capacitor is small, thereby reducing the influence on the N1 node by the nearby data signal, that is, shielding the influence of the data signal on the N1 node, and further improving the problem that the display panel caused by the influence of the data signal jump on the voltage of the N1 node cannot be normally displayed.

[0054] For example, as shown in FIG. 5B, the first semiconductor layer 104 includes the active semiconductor patterns of the first transistor T1 and the second transistor T2 described later, and the material of the first semiconductor layer 104 is a metal oxide semiconductor such as indium gallium zinc oxide (IGZO). The first electrode plate Cst1 of the storage capacitor C can be used as the gate electrode of the driving transistor T3.

[0055] For example, as shown in FIGS. 3 and 5B, the first end 1021a of the first connection structure 1021 is also electrically connected to the first electrode of the first transistor T1 (the first reset transistor) and the first electrode of the second transistor T2 (the threshold compensation transistor).

[0056] For example, as shown in FIGS. 5A, 5B, 6, and 8, the second conductive layer 103 includes spaced-apart data lines 1031, a first electrode transfer line 1032, and a first power signal line 1033. The first electrode transfer line 1032 is elongate and extends entirely along the extending direction of the data line 1031 closest to it. The extending direction of the data line 1031 is the first direction Y, and the direction orthogonal or substantially orthogonal to the extending direction of the data line 1031 is the second direction X. As shown in FIGS. 3, 5B, 6, and 8, the first electrode transfer line 1032 is connected to a first electrode of a light-emitting element 120 described below through a via hole. For example, as shown in FIGS. 5B, 6, and 8, the orthographic projection of the entire data line 1031 on the base substrate 101 extends linearly along the first direction Y. In the same repeating unit, the orthographic projections of two data lines 1031 on the base substrate 101 are located between the orthographic projections of two first power signal lines 1033 on the base substrate 101.

[0057] For example, in the structural layout of the first conductive layer 102 shown in FIG. 7, the first conductive layer 102 further includes a second initial signal line 1022. As shown in FIGS. 3 and 7, the second initial signal line 1022 provides a reset signal by being electrically connected to a first pole of a seventh transistor T7 (a first reset transistor). For example, the second initial signal line 1022 may be a first reset signal line electrically connected to the first pole of the seventh transistor T7. The display substrate 110 further includes a second reset power signal line (not shown). A first portion of the second reset power signal line is located between the first conductive layer 102 and a film layer where the gate electrode of the seventh transistor T7 is located, and is configured to provide a reset signal by being electrically connected to the first pole of the first transistor T1.

[0058] For example, as shown in FIGS. 7 and 8, the first conductive layer 102 further includes a power signal connection line 1023 extending along the second direction X, and the second conductive layer 103 includes a data line data and a first power signal line 1033 extending along the first direction Y. Each power signal connection line 1023 is electrically connected to a plurality of first power signal lines 1033 arranged along the second direction X to form a grid pattern. The first power signal line 1033 can be used to provide the first power terminal in FIG. 3, and the data line 1031 can be used to provide the data signal terminal in FIG. 3. For example, as shown in FIGS. 7 and 8, the main body portion 1023a of the power signal connection line 1023 is in a folded line shape with a protruding portion, and there is a connection block 1023b in the middle portion of the protruding portion. The overall extending direction of the power signal connection line 1023 is parallel to the second direction X, and the extending direction of the connection block 1023b is parallel to the first direction Y. The number of connection blocks 1023b on the power signal connection line 1023 is plural, and the power signal connection line 1023 is connected to a plurality of first power signal lines 1033 on the second conductive layer 103 by a plurality of connection blocks 1023b.

[0059] For example, as shown in FIGS. 3, 5, and 7, the first conductive layer 102 further includes a first connection portion 1024 electrically connected to the first portion of the second reset power signal line.

[0060] For example, as shown in FIGS. 3, 5, and 7, the first conductive layer 102 further includes a second connection portion 1025, and the first pole of the data writing transistor T4 receives a data signal by being electrically connected to the data line 1031 by the second connection portion 1025.

[0061] For example, as shown in FIGS. 3, 5, 7, and 8, the first conductive layer 102 further includes a third connection structure 1027, and the first pole of the sixth transistor T6 (the first light emission control transistor) is electrically connected to the second pole of the second transistor T2 (the threshold compensation transistor) by the third connection structure 1027. For example, the third connection structure 1027 is a branched portion included in the power signal connection line 1023.

[0062] For example, as shown in FIGS. 5B, 6, 7, and 8, the orthographic projection of the first electrode transfer line 1032 on the base substrate 101 overlaps with the orthographic projection of a part of the first connection structure 1021 on the base substrate 101. The first connection structure 1021 is in a folded line shape extending in a direction away from the nearest data line 1031 as a whole, and the first connection structure 1021 includes a portion overlapping with the first electrode transfer line 1032 and a portion not overlapping with the first electrode transfer line 1032, and the non-overlapping portion is farther away from the nearest data line 1031 than the overlapping portion.

[0063] For example, as shown in FIGS. 5B, 6, 7, and 8, the first power signal line 1033 includes a block portion 1033a and a strip portion 1033b that extends entirely along the first direction Y and connects the adjacent block portions 1033a along the first direction Y. The main body portion 1023a of the power signal connection line 1023 is connected to the first power signal line 1033 to form a grid shape. For example, the main body portion 1023a of the power signal connection line 1023 is connected to the strip portion 1033b of the first power signal line 1033 to form a grid shape. With this grid-shaped setting form, the first power signal lines 1033 of each pixel can be electrically connected, which is advantageous for reducing the voltage drop of the first power signal line 1033. Thereby, when the display substrate is applied to the display panel, the display uniformity of the display panel can be improved.

[0064] For example, as shown in FIGS. 5B, 6, and 7, the block portion 1033a overlaps with at least one of the light-emitting regions of the first sub-pixel and the third sub-pixel described later.

[0065] For example, as shown in FIGS. 5B, 6, and 7, the second conductive layer 103 further includes a portion (for example, a part of the data line 1031) that overlaps with the light-emitting region of the second sub-pixel described later.

[0066] For example, as shown in FIG. 6, the width W1 of the block portion 1033a in the second direction X is larger than the width W2 of the entire strip portion 1033b in the second direction X, whereby the area of the second conductive layer 103 can be further reduced and space can be saved.

[0067] For example, as shown in FIGS. 5B, 6, 7, and 8, the first electrode transfer line 1032 extends along the first direction Y, and the first electrode transfer line 1032 shields a part of the first connection structure 1021 at an end position close to the first connection structure 1021, that is, the orthographic projection of the end of the first electrode transfer line 1032 close to the first connection structure 1021 on the base substrate 101 overlaps with the orthographic projection of a part of the first connection structure 1021 on the base substrate 101.

[0068] For example, as shown in FIGS. 6 and 8, the strip portion 1033b includes a first strip portion 1033b1 and a second strip portion 1033b2 that are oppositely arranged, and a third strip portion 1033b3 that connects the first strip portion 1033b1 and the second strip portion 1033b2. The extending directions of the first strip portion 1033b1 and the second strip portion 1033b2 are parallel to the first direction Y, and the third strip portion 1033b3 connects the intermediate regions of the first strip portion 1033b1 and the second strip portion 1033b2. For example, the extending direction of the third strip portion 1033b3 may be parallel to the second direction X, or may not be parallel to the second direction X and intersect the second direction X.

[0069] For example, in one example, the planar shapes of the first strip portion 1033b1, the second strip portion 1033b2, and the third strip portion 1033b3 may be in an H shape.

[0070] For example, in one example, the strip portion 1033b includes a hollow structure, and with this structure design, the area of the second conductive layer 103 can be reduced, whereby space can be saved.

[0071] For example, as shown in FIGS. 3, 5B, 6, 7, and 8, the first conductive layer 102 further includes a third connection portion 1026, and the second electrode of the sixth transistor T6 (the first light emission control transistor) is electrically connected to the first electrode of the light emitting element by the third connection portion 1026 and the first electrode transfer line 1032.

[0072] For example, FIG. 9 is a schematic diagram of the local structure of the first active layer in the display substrate shown in FIG. 5B. For example, as shown in FIGS. 5B to 9, the pixel circuit 110 includes a first active layer 105 including a channel region 1051 and a source-drain region 1052 of each transistor. For example, the source-drain region 1052 may include a source electrode region 1052a and a drain electrode region 1052b.

[0073] For example, FIG. 9 exemplarily shows that the first active layer 105 is formed by patterning a semiconductor material. The first active layer 105 can be used to manufacture the active layers of the above driving transistor T3, fourth transistor T4 (data writing transistor), fifth transistor T5 (second light emission control transistor), sixth transistor T6 (first light emission control transistor), and seventh transistor T7 (second reset control transistor) to form the channel regions of the above transistors. The first active layer 105 includes the active layer patterns (channel regions) and doping region patterns (source-drain regions) of the transistors of each sub-pixel, and the active layer patterns and doping region patterns of the transistors in the same pixel circuit are integrally formed.

[0074] For example, each dashed rectangular frame in FIG. 9 shows the portions overlapping with the first active layer 105 of the metal layer as the channel regions of the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, respectively. A part of the first active layer on both sides of each channel region 1051 is made conductive as the first and second electrodes of each transistor, i.e., the source-drain region 1052, by a process such as ion doping. The source electrodes and drain electrodes of the above transistors may be symmetric in structure. Therefore, there may be no difference in their physical structures between the source electrode and the drain electrode. In the embodiments of the present disclosure, in order to distinguish the transistors, in addition to the gate electrode serving as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, the first and second electrodes of all or some of the transistors in the embodiments of the present disclosure are interchangeable as required.

[0075] For example, as shown in FIG. 9, the first active layer 105 includes a third active portion 23, a fourth active portion 24, a fifth active portion 25, a sixth active portion 26, a seventh active portion 27, an eighth active portion 28, a ninth active portion 29, a tenth active portion 210, and an eleventh active portion 211. The third active portion 23 is used to form the channel region of the driving transistor T3, the fourth active portion 24 is used to form the channel region of the fourth transistor T4, the fifth active portion 25 is used to form the channel region of the fifth transistor T5, the sixth active portion 26 is used to form the channel region of the sixth transistor T6, the seventh active portion 27 is used to form the channel region of the seventh transistor T7, the eighth active portion 28 is connected to the side of the fifth active portion 25 away from the third active portion 23, and the ninth active portion 29 is connected between the eighth active portion 28 in the first pixel circuit P1 and the eighth active portion 28 in the second pixel circuit P2. The tenth active portion 210 is connected between the sixth active portion 26 and the seventh active portion 27, and the eleventh active portion 211 is connected between the sixth active portion 26 and the third active portion 23. The eighth active portion 28 can be used to form the first pole of the fifth transistor T5. For example, in the embodiment of the present disclosure, by connecting the eighth active portions 28 in two adjacent pixel circuits by the ninth active portion 29, the voltage difference between the first power terminals in the adjacent pixel circuits can be reduced.

[0076] For example, as shown in FIG. 9, the first active layer 105 may be manufactured with amorphous silicon, polycrystalline silicon, or the like. It should be noted that the source electrode region and the drain electrode region may be regions doped with n-type impurities or p-type impurities. For example, in one example, the first active layer may be formed of a polycrystalline silicon material, and correspondingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon thin-film transistors.

[0077] For example, a metal layer is provided on the side of the first active layer 105 away from the base substrate 101, and the metal layer includes the gate electrodes of the scanning signal line, the reset control signal line, the light emission control signal line, and the drive transistors T3, T4, T5, T6, and T7.

[0078] For example, the display substrate further includes a third conductive layer. For example, FIG. 10 is a partial structural schematic diagram of the third conductive layer in the display substrate shown in FIG. 5B. As shown in FIGS. 5B and 10, the third conductive layer 106 includes a second gate line 1061, a light emission control signal line 1062, a second reset signal line 1063, and a second conductive portion 1064.

[0079] For example, as shown in FIGS. 5B, 9, and 10, the orthographic projection of the second gate line 1061 on the base substrate 101 extends along the second direction X and overlaps the orthographic projection of the fourth active portion 24 on the base substrate 101, and a part of the structure of the second gate line 1061 is used to form the gate electrode of the fourth transistor T4. The second gate line 1061 can be used to provide the second gate electrode drive signal terminal G2 in FIG. 3.

[0080] For example, as shown in FIGS. 5B, 9, and 10, the orthographic projection of the light emission control signal line 1062 on the base substrate 101 extends along the second direction X and overlaps the orthographic projection of the sixth active portion 26 on the base substrate 101, and a part of the structure of the light emission control signal line 1062 is used to form the gate electrode of the sixth transistor T6. The light emission control signal line 1062 can be used to provide the light emission control signal terminal EM in FIG. 3. For example, the orthographic projection of the light emission control signal line 1062 on the base substrate 101 may further overlap the orthographic projection of the fifth active portion 25 on the base substrate 101, and a part of the structure of the light emission control signal line 1062 is used to form the gate electrode of the fifth transistor T5.

[0081] For example, as shown in FIGS. 5B, 9, and 10, the orthographic projection of the second reset signal line 1063 on the base substrate 101 extends along the second direction X and overlaps with the orthographic projection of the seventh active portion 27 on the base substrate 101. A part of the structure of the second reset signal line 1063 is used to form the gate electrode of the seventh transistor T7. Moreover, the second gate line 1061 in the pixel circuit 110 of this row is multiplexed with the second reset signal line 1063 in the pixel circuit 110 of the adjacent row. The second reset signal line 1063 can be used to provide the second reset signal terminal Re2 in FIG. 3. For example, by this arrangement, the integration degree of the pixel circuit can be improved, and the layout area of the pixel circuit can be reduced.

[0082] For example, as shown in FIGS. 5B and 10, the orthographic projections of the second gate line 1061, the emission control signal line 1062, and the second reset signal line 1063 on the base substrate 101 all extend along the second direction X and are substantially parallel to each other. It should be noted that the orthographic projection of a certain structure on the base substrate extending along a certain direction can be understood as the orthographic projection of the structure on the base substrate extending linearly or bendingly along the direction, and the embodiments of the present disclosure do not limit this.

[0083] For example, as shown in FIGS. 5B, 9, and 10, the orthographic projection of the second conductive portion 1064 on the base substrate 101 overlaps with the orthographic projection of the third active portion 23 on the base substrate 101. The second conductive portion 1064 forms the gate electrode of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor C. For example, in the same pixel circuit 110, the orthographic projection of the second conductive portion 1064 on the base substrate 101 is located between the orthographic projection of the second gate line 1061 on the base substrate 101 and the orthographic projection of the emission control signal line 1062 on the base substrate 101. The orthographic projection of the second reset signal line 1063 on the base substrate 101 is located on the side away from the orthographic projection of the second conductive portion 1064 of the orthographic projection of the emission control signal line 1062 on the base substrate 101.

[0084] For example, the display substrate can perform a conductor conversion process on the first active layer 105 using the third conductive layer 106 as a mask. That is, in the first active layer 105, the region covered by the third conductive layer 106 can form the channel region of each transistor, and the region in the first active layer 105 that is not covered by the third conductive layer 106 forms a conductor structure.

[0085] For example, the display substrate further includes a conductive film layer. For example, FIG. 11 is a schematic diagram of the local structure of the conductive film layer in the display substrate shown in FIG. 5B. As shown in FIGS. 5B and 11, the conductive film layer 107 is located between the third conductive layer 106 and the second conductive layer 103, and the conductive film layer 107 includes a first initial signal line 1071, a third reset signal line 1072, a third gate line 1073, and a first conductive portion 1074.

[0086] For example, as shown in FIG. 11, the first initial signal line 1071 is used to provide the first initial signal terminal in FIG. 3, the third reset signal line 1072 is used to provide the first reset signal terminal in FIG. 3, and the third gate line 1073 is used to provide the first gate electrode drive signal terminal G1 in FIG. 3. The orthographic projection of the first initial signal line 1071 on the base substrate 101, the orthographic projection of the third reset signal line 1072 on the base substrate 101, and the orthographic projection of the third gate line 1073 on the base substrate 101 can all extend along the second direction X.

[0087] For example, as shown in FIGS. 3 and 11, the orthographic projection of the first initial signal line 1071 on the base substrate 101 is located on the side away from the orthographic projection of the second conductive portion 1064 of the orthographic projection of the first reset signal line (mentioned when explaining FIG. 3) on the base substrate 101.

[0088] For example, as shown in FIGS. 3, 5B, and 11, the third reset signal line 1072 is connected to the first reset signal line through a via hole, and the orthographic projection of the third reset signal line 1072 on the base substrate 101 overlaps with the orthographic projection of the first active portion (subsequently included in the fourth conductive layer) on the base substrate 101. A part of the structure of the third reset signal line 1072 is used to form the bottom gate of the first transistor T1. The orthographic projection of the third gate line 1073 on the base substrate 101 overlaps with the orthographic projection of the second active portion (subsequently included in the fourth conductive layer) on the base substrate 101. A part of the structure of the third gate line 1073 is used to form the bottom gate of the second transistor T2.

[0089] For example, as shown in FIGS. 3, 5B, and 11, the first conductive portion 1074 includes a main body portion 1074a. The storage capacitor C further includes a second electrode plate Cst2 facing the first electrode plate Cst1. The main body portion 1074a corresponds to two second electrode plates Cst2. For example, the first conductive portion 1074 further includes a bridge portion 1074b. The bridge portion 1074b is connected to two main body portions 1074a adjacent in the second direction X, that is, connects two adjacent second electrode plates Cst2. The first conductive portion 1074 further includes a gap 1074c between the two second electrode plates Cst2.

[0090] For example, as shown in FIGS. 3, 5B, and 11, there is no overlapping portion between the orthographic projection of the first conductive layer 102 on the base substrate 101 and the orthographic projection of the gap 1074c on the base substrate 101, and there is no overlapping portion between the orthographic projection of the second conductive layer 103 on the base substrate 101 and the orthographic projection of the gap 1074c on the base substrate 101. Thus, the gap 1074c is not shielded by the first conductive layer 102 and the second conductive layer 103, thereby improving the pixel transmittance. Note that the gap 1074c is not shielded by any other film layer with a light-shielding effect.

[0091] For example, as shown in FIGS. 3, 5B, and 11, an opening 1074d is further formed in the first conductive portion 1074, and the orthographic projection on the base substrate 101 of the via hole connected between the gate electrode of the driving transistor T3 and the first connection structure 1021 is located within the orthographic projection on the base substrate 101 of the opening 1074d, whereby the conductive structure in the via hole and the first conductive portion 1074 are insulated from each other.

[0092] For example, the display substrate further includes a second active layer. For example, FIG. 12 is a schematic diagram of the local structure of the second active layer in the display substrate shown in FIG. 5B. As shown in FIGS. 5B and 12, the second active layer 108 is located between the first active layer 105 and the second conductive layer 103. The second active layer 108 may include a first active portion 311, a second active portion 312, and a twelfth active portion 313 that are connected to each other. The first active portion 311 forms the channel region of the first transistor T1, the second active portion 312 forms the channel region of the second transistor T2, the twelfth active portion 313 is connected to the end of the second active portion 312 that is away from the first active portion 311, and the first semiconductor layer includes the second active layer 108.

[0093] For example, in one example, as shown in FIG. 12, the second active layer 108 may be formed of indium gallium zinc oxide. Correspondingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.

[0094] For example, the first semiconductor layer that forms the channel regions of the first transistor T1 and the second transistor T2 in the pixel circuit 110 may be located on the side away from the base substrate 101 of the layer where the active semiconductor pattern of the driving transistor T3 is located, and the first semiconductor layer may contain an oxide semiconductor material. For example, when the active layers in the first transistor T1 and the second transistor T2 of the pixel circuit employ an oxide semiconductor, since the transistor using the oxide semiconductor has excellent hysteresis characteristics, low leakage current, and at the same time low mobility, the low-temperature polycrystalline silicon material in the transistor can be replaced with a transistor using an oxide semiconductor to form a low-temperature polycrystalline silicon-oxide (LTPO) pixel circuit, which can achieve low leakage and is advantageous for improving the stability of the gate electrode voltage of the transistor.

[0095] Of course, in the embodiments of the present disclosure, the second active layer of the pixel circuit is not limited to the structure shown in FIG. 12. In other examples, the first semiconductor layer of the channel regions of the first transistor T1 and the second transistor T2 may be located in the same layer as the semiconductor layers of the channel regions of other transistors, that is, the first active layer may include the channel regions of the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0096] For example, as shown in FIGS. 5B, 11, and 12, the orthographic projection of the third gate line 1073 on the base substrate 101 can cover the orthographic projection of the second active portion 312 on the base substrate 101, and a part of the structure of the third gate line 1073 can be used to form the bottom gate of the second transistor T2. The orthographic projection of the third reset signal line 1072 on the base substrate 101 can cover the orthographic projection of the first active portion 311 on the base substrate 101, and a part of the structure of the third reset signal line 1072 can be used to form the bottom gate of the first transistor T1.

[0097] For example, the display substrate further includes a fourth conductive layer. For example, FIG. 13 is a schematic diagram of the local structure of the fourth conductive layer in the display substrate shown in FIG. 5B. As shown in FIGS. 5B and 13, the fourth conductive layer 109 is located between the second active layer 108 and the second conductive layer 103, and the fourth conductive layer 109 includes a first reset signal line 1091 and a first gate line 1092.

[0098] For example, as shown in FIGS. 3, 5B, 12, and 13, the orthographic projection of the first reset signal line 1091 on the base substrate 101 and the orthographic projection of the first gate line 1092 on the base substrate 101 can both extend along the second direction X. The first reset signal line 1091 can be used to provide the first reset signal terminal in FIG. 3. The orthographic projection of the first reset signal line 1091 on the base substrate 101 overlaps with the orthographic projection of the first active part 311 on the base substrate 101, and a part of the structure of the first reset signal line 1091 is configured to form the top gate of the first transistor T1. At the same time, the first reset signal line 1091 can be connected to the third reset signal 1072 through a via hole located in the edge wiring area of the display substrate.

[0099] For example, as shown in FIGS. 3, 5B, 11, 12, and 13, the first gate line 1092 can be used to provide the first gate electrode drive signal terminal in FIG. 3. The orthographic projection of the first gate line 1092 on the base substrate 101 can cover the orthographic projection of the second active part 312 on the base substrate 101. A part of the structure of the first gate line 1092 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 1092 can be connected to the third gate line 1073 through a via hole located in the edge wiring area of the display substrate.

[0100] For example, as shown in FIGS. 5B, 10, and 13, in the same pixel circuit, the orthographic projection of the first gate line 1092 on the base substrate 101 is located between the orthographic projection of the second conductive portion 1064 on the base substrate 101 and the orthographic projection of the second gate line 1061 on the base substrate 101, and the orthographic projection of the first reset signal line 1091 on the base substrate 101 is located on the side away from the orthographic projection of the second conductive portion 1064 on the base substrate 101 of the orthographic projection of the second gate line 1061 on the base substrate 101.

[0101] For example, as shown in FIGS. 5B, 10, and 13, in the same pixel circuit, the orthographic projection of the second conductive portion 1064 on the base substrate 101 can be located between the orthographic projection of the first gate line 1092 on the base substrate 101 and the orthographic projection of the emission control signal line 1062 on the base substrate 101. The orthographic projection of the first reset signal line 1091 on the base substrate 101 can be located on the side away from the orthographic projection of the second conductive portion 1064 on the base substrate 101 of the orthographic projection of the first gate line 1092 on the base substrate 101.

[0102] For example, as shown in FIGS. 5B, 10, and 13, in the same pixel circuit, the orthographic projection of the second gate line 1061 on the base substrate 101 can be located between the orthographic projection of the first gate line 1092 on the base substrate 101 and the orthographic projection of the first reset signal line 1091 on the base substrate 101. The orthographic projection of the second reset signal line 1063 on the base substrate 101 can be located on the side away from the orthographic projection of the second conductive portion 1064 on the base substrate 101 of the orthographic projection of the emission control signal line 1062 on the base substrate 101.

[0103] For example, as shown in FIGS. 3, 5B, 7, and 11, a plurality of third connection structures 1027 included in the first conductive layer 102 are installed in one-to-one correspondence with the plurality of repeating units. The third connection structure 1027 is connected to a ninth active part 29 included in the first active layer 105 through a first via hole connection part H1, and is connected to a bridge part 1074b (a part of the first conductive part 1074) included in the conductive film layer 107 through a second via hole connection part H2. Thereby, a first pole of the fifth transistor T5 and a second electrode plate Cst2 of the capacitor C can be connected. That is, the third connection structure 1027 includes the first via hole connection part H1 for connecting to the ninth active part 29. Note that in the embodiments of the present disclosure, only some of the via holes are marked.

[0104] For example, as shown in FIGS. 5B, 7, and 8, a sixth connection structure 1028 included in the first conductive layer 102 and a first electrode transfer line 1032 included in the second conductive layer 103 are connected through a third via hole connection part H3.

[0105] For example, as shown in FIGS. 3, 5B, 7, 8, 9, and 12, the third connection part 1026 is connected to an eleventh active part 211 through a fourth via hole connection part H4, and the third connection part 1026 is connected to a twelfth active part 313 through a fifth via hole connection part H5. Thereby, a second pole of the second transistor T2, a first pole of the sixth transistor T6, and a second pole of the driving transistor T3 can be connected.

[0106] For example, as shown in FIGS. 3, 5B, 7, 8, and 12, the first connection structure 1021 is connected to a portion located between a first active part 311 and a second active part 312 of the second active layer 108 through a sixth via hole connection part H6, and the first connection structure 1021 is connected to a second conductive part 1064 through a seventh via hole connection part H7. Thereby, a first pole of the second transistor T2 and a gate electrode of the driving transistor T3 can be connected.

[0107] For example, as shown in FIGS. 5B, 10, and 11, an opening 1074d is formed in the first conductive portion 1074, and the orthographic projection of the seventh via hole connection portion H7 connected between the second conductive portion 1064 and the first connection structure 1021 on the base substrate 101 is located within the orthographic projection of the opening 1074d on the base substrate 101, whereby the conductive structure within the seventh via hole connection portion H7 and the first conductive portion 1074 are insulated from each other.

[0108] For example, as shown in FIGS. 3, 5B, 7, 8, 11, and 12, the first connection portion 1024 can be connected by an eighth via hole connection portion H8 to a portion away from the second active layer on one side of the second active portion 312 of the first active portion 311. The first connection portion 1024 is connected to the first initial signal line 1071 by a ninth via hole connection portion H9, thereby connecting the second electrode of the first transistor T1 and the first initial signal terminal. For example, in two adjacent repeating units in the second direction X, two adjacent pixel circuits can share the same first connection portion 1024.

[0109] For example, as shown in FIGS. 3, 5B, 7, and 9, the second connection portion 1025 can be connected by a tenth via hole connection portion H10 to a portion located on the side away from the third active portion 23 of the fourth active portion 24 of the first active layer 105, thereby being able to connect to the first electrode of the fourth transistor T4.

[0110] For example, as shown in FIGS. 3, 5B, 7, 8, and 9, the second initial signal line 1022 can be used to provide the second initial signal terminal in FIG. 3. The second initial signal line 1022 can be connected by an eleventh via hole connection portion H11 to a portion located on the side away from the sixth active portion 26 of the seventh active portion 27 of the first active layer 105, thereby being able to connect the second electrode of the seventh transistor T7 and the second initial signal terminal Vinit2.

[0111] For example, the display substrate further includes a plurality of sub-pixels, each sub-pixel includes the pixel circuit 110 and the light-emitting element described in any of the above examples. FIG. 14 is a schematic diagram showing a local pixel array structure on the display substrate according to an embodiment of the present disclosure. FIG. 15A is a layout showing the stack of the pixel circuit and the first electrode of the light-emitting element in FIG. 5B, and FIG. 15B is another layout showing the stack of the pixel circuit and the first electrode of the light-emitting element in FIG. 5B. In FIG. 15B, a light-shielding layer is added compared to FIG. 15A, and other structure settings are the same. For example, as shown in FIGS. 14 and 15B, the plurality of sub-pixels 40 include a plurality of first sub-pixels 401, a plurality of second sub-pixels 402, and a plurality of third sub-pixels 403. For example, one of the first sub-pixel 401 and the third sub-pixel 403 is a red sub-pixel that emits red light, the other of the first sub-pixel 401 and the third sub-pixel 403 is a blue sub-pixel that emits blue light, and the second sub-pixel 402 is a green sub-pixel that emits green light.

[0112] For example, in one example, the first sub-pixel 401 is a red sub-pixel, the third sub-pixel 403 is a blue sub-pixel, the second sub-pixel 402 is a green sub-pixel, the area of the light-emitting region of the blue sub-pixel is larger than the area of the light-emitting region of the red sub-pixel, and the area of the light-emitting region of the red sub-pixel is larger than the area of the light-emitting region of the green sub-pixel.

[0113] For example, the names of the first sub-pixel, the second sub-pixel, and the third sub-pixel are interchangeable. For example, the first sub-pixel may be a green sub-pixel, the second sub-pixel may be a blue sub-pixel, the third sub-pixel may be a red sub-pixel, or the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a red sub-pixel, the third sub-pixel may be a green sub-pixel, etc. The embodiments of the present disclosure do not limit this.

[0114] For example, as shown in FIG. 14, a plurality of first sub-pixels 401 and a plurality of third sub-pixels 403 are alternately arranged along a second direction X and a first direction Y to form a plurality of first pixel rows R1 and a plurality of first pixel columns C1. A plurality of second sub-pixels 402 are arranged in an array along the second direction X and the first direction Y to form a plurality of second pixel rows R2 and a plurality of second pixel columns C2. The plurality of first pixel rows R1 and the plurality of second pixel rows R2 are alternately arranged along the first direction Y and are offset from each other in the second direction X. The plurality of first pixel columns C1 and the plurality of second pixel columns C2 are alternately arranged along the second direction X and are offset from each other in the first direction Y. The second direction X and the first direction Y intersect. For example, the second direction X and the first direction Y may be orthogonal. For example, the second direction X and the first direction Y are interchangeable.

[0115] For example, as shown in FIG. 14, one second pixel row R2 includes a plurality of second sub-pixel pairs 4020 arranged along the second direction X. The two second sub-pixels 402 within one second sub-pixel pair 4020 are a first pixel block 4020a and a second pixel block 4020b, respectively, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, the first pixel block 4020a and the second pixel block 4020b in one second pixel column C2 are alternately arranged along the first direction Y.

[0116] For example, as shown in FIG. 14, at least two second pixel rows R2 include a plurality of second sub-pixel pairs 4020 arranged along the second direction X. The two second sub-pixels 402 within at least two second sub-pixel pairs 4020 are a first pixel block 4020a and a second pixel block 4020b, respectively, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, the first pixel block 4020a and the second pixel block 4020b in at least two second pixel columns C2 are alternately arranged along the first direction Y.

[0117] For example, as shown in FIG. 14, each second pixel row R2 includes a plurality of second sub-pixel pairs 4020 arranged along the second direction X. The two second sub-pixels 402 within each second sub-pixel pair 4020 are the first pixel block 4020a and the second pixel block 4020b respectively, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, the first pixel block 4020a and the second pixel block 4020b in each second pixel column C2 are alternately arranged along the first direction Y.

[0118] For example, as shown in FIG. 14, the plurality of sub-pixels 40 include a plurality of minimum repeating units A. One minimum repeating unit A includes one first sub-pixel 401, one first pixel block 4020a, one second pixel block 4020b, and one third sub-pixel 403. For example, at least two minimum repeating units A include one first sub-pixel 401, one first pixel block 4020a, one second pixel block 4020b, and one third sub-pixel 403. For example, each minimum repeating unit A includes one first sub-pixel 401, one first pixel block 4020a, one second pixel block 4020b, and one third sub-pixel 403. For example, each minimum repeating unit A includes sub-pixels 40 arranged in 2 rows and 4 columns.

[0119] For example, as shown in FIG. 14, in one minimum repeating unit A, the first pixel block 4020a and the first sub-pixel 401 constitute the first pixel unit A1, and the second pixel block 4020b and the third sub-pixel 403 constitute the second pixel unit A2. For example, in at least two minimum repeating units A, the first pixel block 4020a and the first sub-pixel 401 constitute the first pixel unit A1, and the second pixel block 4020b and the third sub-pixel 403 constitute the second pixel unit A2. For example, in each minimum repeating unit A, the first pixel block 4020a and the first sub-pixel 401 constitute the first pixel unit A1, and the second pixel block 4020b and the third sub-pixel 403 constitute the second pixel unit A2.

[0120] The above-described first pixel unit A1 and second pixel unit A2 are not pixels in the strict sense, that is, not a single pixel defined by a complete one first sub-pixel, one second sub-pixel, and one third sub-pixel. The minimum repeating unit here means that the pixel array structure can include such minimum repeating units that are repeatedly arranged in a plurality.

[0121] For example, FIG. 16 is a schematic cross-sectional structure diagram of a display substrate according to an embodiment of the present disclosure. As shown in FIGS. 14 to 16, the display substrate 100 includes a base substrate 101 and a plurality of sub-pixels 40 located on the base substrate 101. At least some of the sub-pixels 40 include a light-emitting element 120 and a pixel circuit 110. The light-emitting element 120 includes a light-emitting functional layer 122, and a first electrode 121 and a second electrode 123 located on both sides of the light-emitting functional layer 122 along a direction orthogonal to the base substrate 101. The first electrode 121 is located between the light-emitting functional layer 122 and the base substrate 101.

[0122] For example, as shown in FIG. 16, the display substrate 100 further includes a pixel defining pattern 50. The direction orthogonal to the main surface of the base substrate 101 is the third direction Z, and the third direction Z is a direction orthogonal to the plane in which the first direction Y and the second direction X are located. The pixel defining pattern 50 is located on the side of the first electrode 121 of the light-emitting element 120 away from the base substrate 101, and the pixel defining pattern 50 includes a plurality of pixel openings 51 and a limiting portion 52 surrounding the plurality of pixel openings 51. A plurality of light-emitting elements 120 are at least partially located in the plurality of pixel openings 51. FIG. 16 exemplarily shows that a structural layer 011 is installed on the side of the first electrode 121 of the light-emitting element 120 away from the second electrode 123. The structural layer 011 may include film layers such as the base substrate 101, the layer where the active semiconductor pattern is located, the film layer where the gate line is located, the film layer where the data line is located, and a plurality of insulating layers.

[0123] For example, the limiting portion 52 is a structure that limits the pixel opening 51. For example, the material of the limiting portion 52 may include polyimide, acrylic, polyethylene terephthalate, etc.

[0124] For example, the pixel opening 51 of the pixel defining pattern 50 is configured to define the light emitting region 124 of the light emitting element 120. For example, the light emitting elements 120 of the plurality of sub-pixels 40 can be installed in one-to-one correspondence with the plurality of pixel openings 51. For example, the light emitting element 120 may include a portion located in the pixel opening 51 and a portion overlapping with the limiting portion 52 in a direction orthogonal to the base substrate 101.

[0125] For example, the opening 51 of the pixel defining pattern 50 is configured to expose the first electrode 121 of the light emitting element 120, and the exposed first electrode 121 is at least partially in contact with the light emitting functional layer 122 in the light emitting element 120. For example, at least a part of the first electrode 121 is located between the limiting portion 52 and the base substrate 101. For example, when the light emitting functional layer 122 is located in the pixel opening 51 of the pixel defining pattern 50, the first electrode 121 and the second electrode 123 located on both sides of the light emitting functional layer 122 can drive the light emitting functional layer 122 in the pixel opening 51 of the pixel defining pattern 50 to emit light. For example, the above-mentioned light emitting region 124 may refer to the effective light emitting region of the light emitting element 120, the shape of the light emitting region 124 refers to a two-dimensional shape, and for example, the shape of the light emitting region 124 may be the same as the shape of the pixel opening 51 of the pixel defining pattern 50. For example, the pixel opening 51 of the pixel defining pattern 50 may have a shape such that the size on the side closer to the base substrate 101 is small, but the size on the side away from the base substrate 101 is large. For example, the shape of the light emitting region 124 may be substantially the same as the size and shape of the pixel opening 51 of the pixel defining pattern 50 on the side closer to the base substrate 101.

[0126] For example, the first electrode 121 may be a positive electrode, and the second electrode 123 may be a negative electrode. For example, the negative electrode may be formed of a material with high conductivity and low work function. For example, the negative electrode may be manufactured from a metal material. For example, the positive electrode may be formed of a conductive material with high work function.

[0127] For example, assuming the direction indicated by the arrow in the first direction Y is upward and the direction indicated by the arrow in the second direction X is rightward, in the first pixel unit A1, the first pixel block 4020a is located at the lower right of the first sub-pixel 401, and in the second pixel unit A2, the second pixel block 4020b is located at the lower right of the third sub-pixel 403. In the first pixel unit and the second pixel unit of the display substrate provided by the embodiments of the present disclosure, by changing the first sub-pixel and the third sub-pixel to the second sub-pixels at different positions, the pixel space and the design are optimized. As a result, the flatness of the first electrode of the light-emitting element is improved, the pixel space structure is optimized, and the purpose of further reducing the lower edge is achieved.

[0128] For example, as shown in FIGS. 14 to 16, the first sub-pixel 401 can form a first pixel unit with the second sub-pixel 402 located at its upper right or the second sub-pixel 402 located at its lower right. Similarly, the third sub-pixel 403 can form a second pixel unit with the second sub-pixel 402 located at its upper right or the second sub-pixel 402 located at its lower right. In the embodiments of the present disclosure, in the first sub-pixel 401, the fifth transistor T5 is located in the light-emitting region. By forming the first pixel unit with the second sub-pixel 402 located at its upper right, the design of the pixel circuit is facilitated. By changing the shape of the pad that plays a role in planarization in the second conductive layer, the possibility of affecting the flatness of the pixel is reduced. In addition to preventing the occurrence of color shift, the influence on the capacitor of the node corresponding to the first electrode of the light-emitting element can be reduced. For example, the influence on the image quality of low gray scales can be prevented. Here, the larger the capacitor, the more necessary it is to fully fill the capacitor of the node corresponding to the first electrode of the light-emitting element first at low gray scales. As a result, the charging voltage to the node decreases under low gray scales, and in this way, the pixel lighting time (response time) becomes longer, further affecting the image quality. Similarly, in the third sub-pixel 403, the fifth transistor T5 is located in the light-emitting region, and the design of the pixel circuit can be facilitated by forming the second pixel unit with the second sub-pixel 402 located at its upper right.

[0129] For example, as shown in FIGS. 5A, 5B, and 15, two data lines 1031 are respectively installed on both sides of the first sub-pixel 401 along the second direction X. For example, two data lines 1031 are installed between the adjacent first sub-pixel 401 and the third sub-pixel 403 arranged in the second direction X.

[0130] For example, the layer structure shown in FIG. 14 may be the first electrode layer 501 included in the display substrate. The first electrode layer 501 is located on the side away from the base substrate 101 of the second conductive layer 103. The first electrode layer 501 includes a plurality of electrode portions 502. Each electrode portion 502 includes a main body portion 5021 and an additional portion 5022 that are connected. The orthographic projection of the additional portion 5022 on the base substrate 101 at least partially overlaps with the orthographic projection of the first electrode transfer line 1032 on the base substrate 101. Each electrode portion 502 corresponds to one of the first sub-pixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third sub-pixel 403. By providing the additional portion 5022 in the electrode portion 502, the overlapping area between the electrode portion 502 and the second conductive layer 103 is increased. Thereby, the self-capacitance of the light-emitting unit electrode portion is increased, and further, the charging time length before the light emission of the light-emitting unit is extended. And in the embodiments of the present disclosure, the period when the current output of the driving transistor T3 is unstable is completely or at least partially within the charging period of the light-emitting unit. That is, by this installation, the light emission time length of the light-emitting unit during the period when the current output of the driving transistor T3 is unstable can be shortened. Thereby, by this installation, the flicker problem during the operation of the display substrate can be improved.

[0131] For example, as shown in FIG. 14, the plurality of electrode portions 502 include first electrode portions 502a, second electrode portions 502b, and third electrode portions 502c of three different colors. The first electrode portion 502a corresponds to the first sub-pixel 401. The second electrode portion 502b corresponds to either the first pixel block 4020a or the second pixel block 4020b. The third electrode portion 502c corresponds to the third sub-pixel 403.

[0132] For example, as shown in FIGS. 14 and 15B, in the first direction Y, the first electrode portion 502a and the third electrode portion 502c are covered by the block portion 1033a included in the first power supply signal line 1033, the second electrode portion 502b is covered by a part of the data lines 1031 and a part of the first electrode transfer lines 1032, and the orthographic projection of the second electrode portion 502b on the base substrate 101 is limited to be between the orthographic projections of two adjacent first electrode transfer lines 1032 on the base substrate 101. Therefore, there is no overlapping portion between the orthographic projection of the second electrode portion 502b on the base substrate 101 and the orthographic projection of the first power supply signal line 1033 on the base substrate 101. The overlapping area between the orthographic projection of the first electrode portion 502a on the base substrate 101 and the orthographic projection of the first power supply signal line 1033 on the base substrate 101 is larger than the overlapping area between the orthographic projection of the second electrode portion 502b on the base substrate 101 and the orthographic projection of the first power supply signal line 1033 on the base substrate 101, and is also larger than the overlapping area between the orthographic projection of the third electrode portion 502c on the base substrate 101 and the orthographic projection of the first power supply signal line 1033 on the base substrate 101.

[0133] For example, as shown in FIGS. 14 and 15B, the overlapping area between the orthographic projection of the third electrode portion 502c on the base substrate 101 and the orthographic projection of the first power supply signal line 1033 on the base substrate 101 is also larger than the overlapping area between the orthographic projection of the second electrode portion 502b on the base substrate 101 and the orthographic projection of the first power supply signal line 1033 on the base substrate 101.

[0134] For example, as shown in FIGS. 14 and 15B, the orthographic projection of the additional portion 5022 of each electrode portion 502 on the base substrate 101 overlaps at least partially with the orthographic projection of the second conductive layer 103 on the base substrate 101 and is electrically connected to the second conductive layer 103 through corresponding via holes. For example, the additional portion 5022a of the first electrode portion 502a is connected to the first electrode transfer line 1032 through the first via hole V1, the additional portion 5022b of the second electrode portion 502b is connected to the first electrode transfer line 1032 through the second via hole V2, and the additional portion 5022c of the third electrode portion 502c is connected to the first electrode transfer line 1032 through the third via hole V3.

[0135] For example, as shown in FIGS. 14 and 15B, the first electrode portion 502a corresponds to a blue sub-pixel that emits blue light, the second electrode portion 502b corresponds to a green sub-pixel that emits green light, and the third electrode portion 502c corresponds to a red sub-pixel that emits red light.

[0136] For example, the display substrate further includes a light-shielding layer. For example, FIG. 17 is a schematic diagram of a local structure of the light-shielding layer in the display substrate shown in FIGS. 5B and 15B. As shown in FIG. 17, the light-shielding layer 111 may include a plurality of light-shielding portions 111a distributed in the second direction X and the first direction Y. The light-shielding portions 111a adjacent to each other in the second direction X are connected to each other, and the connection lines connecting the adjacent light-shielding portions 111a are located on the same straight line. The extending direction of the connection line is parallel or substantially parallel to the second direction X. Two light-shielding portions 111a adjacent to each other in the first direction Y are also connected to each other. The light-shielding layer 111 may be a conductor structure. For example, the light-shielding layer 111 may be a light-shielding metal layer.

[0137] For example, as shown in FIGS. 3, 5B, 15B, and 17, the light-shielding layer 111 can be connected to a stable power supply terminal. For example, the light-shielding layer 111 can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in FIG. 3. The light-shielding layer 111 can stabilize the pressure of the second conductive portion 1064, thereby reducing the voltage fluctuation at the gate electrode of the driving transistor T3 during the light-emitting stage.

[0138] For example, FIG. 18 is a layout showing the lamination of the light-shielding layer and the first active layer according to an embodiment of the present disclosure. As shown in FIG. 18, the orthographic projection of the light-shielding layer 111 on the base substrate 101 can cover the orthographic projection of the third active portion 23 on the base substrate 101. The light-shielding layer 111 can reduce the influence of light on the characteristics of the driving transistor T3.

[0139] For example, FIG. 19 is a schematic circuit diagram of another pixel circuit according to an embodiment of the present disclosure. As shown in FIG. 19, the pixel circuit 610 includes a first transistor T1, a second transistor T2, a third transistor (driving transistor) T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor C. That is, the pixel circuit 610 may include eight transistors (the first transistor T1 to the eighth transistor T8), one storage capacitor C, and a plurality of signal lines (data signal line Data, first scan signal line Gate, second scan signal line GateN, reset control signal line Reset, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, second power supply line VSS, and emission control signal line EM).

[0140] For example, as shown in FIG. 19, the gate electrode of the first transistor T1 is connected to the reset control signal line Reset, the first pole of the first transistor T1 is connected to the first initial signal line Vinit1, and the second pole of the first transistor T1 is connected to the N5 node. The gate electrode of the second transistor T2 is connected to the first scan signal line Gate, the first pole of the second transistor T2 is connected to the N5 node, and the second pole of the second transistor T2 is connected to the N3 node. The gate electrode of the driving transistor T3 is connected to the N1 node, the first pole of the driving transistor T3 is connected to the N2 node, and the second pole of the driving transistor T3 is connected to the N3 node. The gate electrode of the fourth transistor T4 is connected to the first scan signal line Gate, the first pole of the fourth transistor T4 is connected to the data signal line Data, and the second pole of the fourth transistor T4 is connected to the N2 node. The gate electrode of the fifth transistor T5 is connected to the emission control signal line EM, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the N2 node. The gate electrode of the sixth transistor T6 is connected to the emission control signal line EM, the first pole of the sixth transistor T6 is connected to the N3 node, and the second pole of the sixth transistor T6 is connected to the N4 node (i.e., the first pole of the light-emitting element). The gate electrode of the seventh transistor T7 is connected to the first scan signal line Gate or the reset control signal line Reset, the first pole of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second pole of the seventh transistor T7 is connected to the N4 node. The gate electrode of the eighth transistor T8 is connected to the second scan signal line GateN, the first pole of the eighth transistor T8 is connected to the N5 node, and the second pole of the eighth transistor T8 is connected to the N1 node. The first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the N1 node.

[0141] Specifically, the gate electrode of the first transistor T1 is connected to the reset control signal line, the first pole of the first transistor T1 is connected to the first initial signal line, the second pole of the first transistor T1 is connected to the first pole of the eighth transistor T8 and the first pole of the second transistor T2, the gate electrode of the second transistor T2 is connected to the first scanning signal line, the second pole of the second transistor T2 is connected to the second pole of the driving transistor T3 and the first pole of the sixth transistor T6, the gate electrode of the driving transistor T3 is connected to the second pole of the eighth transistor T8 and the first electrode plate Cst1 of the storage capacitor C, the first pole of the driving transistor T3 is connected to the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, the second pole of the driving transistor T3 is connected to the second pole of the second transistor T2 and the first pole of the sixth transistor T6, the gate electrode of the fourth transistor T4 is connected to the first scanning signal line, the first pole of the fourth transistor T4 is connected to the data line Data, the second pole of the fourth transistor T4 is connected to the first pole of the driving transistor T3 and the second pole of the fifth transistor T5, the gate electrode of the fifth transistor T5 is connected to the first light emission control signal line, the first pole of the fifth transistor is connected to the first power supply signal line and the second electrode plate Cst2 of the storage capacitor C, the second pole of the fifth transistor T5 is connected to the second pole of the fourth transistor T4 and the first pole of the driving transistor T3, the gate electrode of the sixth transistor T6 is connected to the first light emission control signal line, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3 and the second pole of the second transistor T2, the second pole of the sixth transistor T6 is connected to the first pole of the light emitting element and the second pole of the seventh transistor T7, the gate electrode of the seventh transistor T7 is connected to the first scanning signal line or the reset control signal line, the first pole of the seventh transistor T7 is connected to the first initial signal line, the second pole of the seventh transistor T7 is connected to the second pole of the sixth transistor T6 and the first pole of the light emitting element, the gate electrode of the eighth transistor T8 is connected to the second scanning signal line, the first pole of the eighth transistor T8 is connected to the second pole of the first transistor T1 and the first pole of the second transistor T2, the second pole of the eighth transistor T8 is connected to the gate electrode of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor C,The first electrode Cst1 of the storage capacitor C is connected to the gate electrode of the driving transistor T3 and the second electrode of the eighth transistor T8, and the second electrode Cst2 of the storage capacitor C is connected to the first power signal line.

[0142] For example, in some exemplary embodiments, the first transistor T1 to the seventh transistor T7 may be N-type thin film transistors, and the eighth transistor T8 may be a P-type thin film transistor, or the first transistor T1 to the seventh transistor T7 may be P-type thin film transistors, and the eighth transistor T8 may be an N-type thin film transistor.

[0143] For example, in some exemplary embodiments, the first transistor T1 to the seventh transistor T7 may be low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs), and the eighth transistor T8 may be an indium gallium zinc oxide (IGZO) thin film transistor.

[0144] For example, compared with low temperature polycrystalline silicon thin film transistors, the leakage current generated by indium gallium zinc oxide thin film transistors is small. Therefore, if the eighth transistor T8 is set as an indium gallium zinc oxide thin film transistor, the generation of leakage current can be significantly reduced, thereby improving the problem of low-frequency and low-brightness flicker of the display substrate. The first transistor T1 and the second transistor T2 do not need to be set as indium gallium zinc oxide thin film transistors because the size of low temperature polycrystalline silicon thin film transistors is generally smaller than that of indium gallium zinc oxide thin film transistors. Therefore, the occupied space of the pixel circuit of the present disclosure embodiment is small, which is beneficial to the improvement of the resolution of the subsequently formed display panel.

[0145] For example, the pixel circuit shown in FIG. 19 has both the excellent switching characteristics of LTPS-TFT and the low leakage characteristics of Oxide-TFT, so that low-frequency driving (1 Hz to 60 Hz) can be realized, and the power consumption of the display substrate can be significantly reduced.

[0146] For example, the display substrate further includes a light-emitting element EL. The second electrode of the light-emitting element EL is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal provided continuously, and the signal of the first power supply line VDD is a high-level signal provided continuously. The signal of the first scanning signal line Gate is the scanning signal in the pixel circuit of the current display row, and the signal of the reset control signal line Reset is the scanning signal in the pixel circuit of the previous display row. That is, for the nth display row, the first scanning signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n - 1). The signal of the reset control signal line Reset of the current display row and the signal of the first scanning signal line Gate in the pixel circuit of the previous display row may be the same signal, thereby reducing the signal lines on the display substrate and realizing a narrow border of the display substrate.

[0147] For example, in some exemplary embodiments, the first scanning signal line Gate, the second scanning signal line GateN, the reset control signal line Reset, the light-emitting control signal line EM, the first initial signal line Vinit1, and the second initial signal line Vinit2 all extend along the horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line Data all extend along the orthogonal direction.

[0148] For example, in some exemplary embodiments, the light-emitting element 620 may be an organic light-emitting diode (OLED) including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0149] For example, FIG. 20 is a timing diagram of each node in the driving method of the pixel circuit of FIG. 19. Hereinafter, an exemplary embodiment of the present disclosure will be described based on the operation process of the pixel circuit shown in FIG. 20. The pixel circuit in FIG. 19 includes eight transistors (a first transistor T1 to an eighth transistor T8) and one storage capacitor C. The first transistor T1 to the seventh transistor T7 are P-type transistors, and the eighth transistor T8 is an N-type transistor. An example will be described in which the gate electrode of the seventh transistor T7 is connected to the first scanning signal line Gate.

[0150] For example, as shown in FIGS. 19 and 20, the operation process of the pixel circuit includes a first stage t1 to a third stage t3.

[0151] The first stage t1 is called a reset stage. The signals of the first scanning signal line Gate, the reset control signal line Reset, the second scanning signal line GateN, and the light emission control signal line EM are all high-level signals, and the signal of the reset control signal line Reset is a low-level signal. Due to the high-level signal of the light emission control signal line EM, the fifth transistor T5 and the sixth transistor T6 are turned off. Due to the high-level signal of the second scanning signal line GateN, the eighth transistor T8 is turned on. Due to the low-level signal of the reset control signal line Reset, the first transistor T1 is turned on. Therefore, the voltage of the N1 node is reset to the first initial voltage Vinit1 provided by the first initial signal line Vinit1. Next, the potential of the reset control signal line Reset becomes high, and the first transistor T1 is turned off. Since the fifth transistor T5 and the sixth transistor T6 are turned off, the light-emitting element EL does not emit light at this stage.

[0152] The second stage t2 is called the data writing stage. The signal on the first scanning signal line Gate is a low-level signal. The fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on. The data signal line Data outputs a data voltage. The voltage of the N4 node is reset to the second initial voltage Vinit2 provided by the second initial signal line Vinit2, and the initialization is completed. At this stage, since the N1 node is at a low level, the third transistor T3 is turned on. Because the fourth transistor T4 and the second transistor T2 are turned on, the data voltage output by the data signal line DataS passes through the turned-on fourth transistor T4, the N2 node, the turned-on third transistor T3, the N3 node, the turned-on second transistor T2, the N5 node, and the eighth transistor T8 and is provided to the N1 node, and the sum of the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is stored in the storage capacitor C. The voltage of the second terminal (N1 node) of the storage capacitor C is Vdata+Vth, where Vdata is the data voltage output by the data signal line Data and Vth is the threshold voltage of the driving transistor T3. The signal on the emission control signal line EM is a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off, thereby ensuring that the light-emitting element EL does not emit light.

[0153] The third stage t3 is called the light emission stage. The signals on the first scanning signal line Gate and the reset control signal line Reset are high-level signals, and the signals on the emission control signal line EM and the second scanning signal line GateN are both low-level signals. Due to the high-level signal on the reset control signal line Reset, the seventh transistor T7 is turned off. Due to the low-level signal on the emission control signal line EM, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 and provides a driving voltage to the first pole (i.e., the N4 node) of the light-emitting element EL to drive the light-emitting element EL to emit light.

[0154] For example, in the pixel circuit shown in FIG. 19, by initializing the N4 node with the signal of the second initial signal line Vinit2 and initializing the N5 node with the signal of the first initial signal line Vinit1, the reset voltage of the light-emitting element EL and the reset voltage of the N1 node can be adjusted respectively, thereby realizing a better display effect and improving problems such as low-frequency blinking.

[0155] It should be noted that in the embodiments of the present disclosure, each pixel circuit may have an 8T1C (i.e., eight transistors and one capacitor) structure shown in FIG. 19, or may have other structures including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, a 7T1C structure, or a 9T2C structure, etc. The embodiments of the present disclosure do not limit this.

[0156] For example, the display substrate includes a plurality of repeating units distributed along a first direction and a second direction intersecting each other. Each repeating unit includes two pixel circuits. The two pixel circuits include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are arranged in a substantially mirror symmetry. The pixel circuit described below will describe one of the first pixel circuit and the second pixel circuit.

[0157] For example, the embodiments of the present disclosure provide a display substrate. FIG. 21A is a structural layout of another display substrate according to an embodiment of the present disclosure, FIG. 21B is a structural layout of another display substrate according to an embodiment of the present disclosure, FIG. 22 is a structural layout of the second conductive layer in FIG. 21B, FIG. 23 is a structural layout of the first conductive layer in FIG. 21B, and FIG. 24 is a structural layout when the first conductive layer and the second conductive layer in FIG. 21B are laminated. FIGS. 21A to 24 only exemplarily show the laminated structure schematic diagrams or single-layer structure schematic diagrams of some film layers on the display substrate. Other film layers may further include film layers such as the film layer where the gate line is located and the film layer where the light-shielding layer is located. FIG. 21B has an additional light-shielding layer compared to FIG. 21A, and other structural settings are the same.

[0158] For example, as shown in FIGS. 19 and 21B, the display substrate 600 includes a base substrate 601 and a pixel circuit 610 installed on the base substrate 101 and including a driving transistor T3 and a storage capacitor C. The display substrate 600 further includes a first conductive layer 602, a second conductive layer 603, and a first semiconductor layer 604. The first conductive layer 602 includes a first connection structure 6021. The first connection structure 6021 includes an opposing first end 6021a and a second end 6021b. The first end 6021a is connected to the first semiconductor layer 604. The second end 6021b is electrically connected to the gate electrode of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor C. The first conductive layer 602 is located on the side of the first semiconductor layer 604 away from the base substrate 601. The second conductive layer 603 is located on the side of the first conductive layer 602 away from the base substrate 601. And the orthographic projection of the first power signal line 6033 on the base substrate 601 of the second conductive layer 603 overlaps with the orthographic projection of the entire first connection structure 6021 on the base substrate 601. The display substrate 600 overlaps the orthographic projection of the second conductive layer 603 on the base substrate 601 with the orthographic projection of the entire first connection structure 6021 on the base substrate 601. That is, by completely covering the first connection structure 6021 (also called the N1 node) with the first power signal line 6033 in the second conductive layer 603 (also called SD2), the second conductive layer 603 (SD2) is connected to a stable signal. And a capacitor is formed between the second conductive layer 603 (SD2) and the first conductive layer 602 (also called SD1), and a capacitor is formed between the N1 node and the nearest data line data. Therefore, the influence of the data signal on the capacitor is small, thereby reducing the influence of the nearby data signal on the N1 node. That is, shielding the influence of the data signal on the N1 node, and further improving the problem that the display panel cannot be normally displayed due to the influence of the data signal jump on the voltage of the N1 node.

[0159] For example, as shown in FIGS. 19 and 21, the first semiconductor layer 604 includes a semiconductor pattern of an eighth transistor T8 described later, and the material of the first semiconductor layer 604 is a metal oxide semiconductor such as indium gallium zinc oxide (IGZO). The first electrode plate Cst1 of the storage capacitor C can be used as the gate electrode of the driving transistor T3.

[0160] For example, as shown in FIGS. 21B and 22, the second conductive layer 603 includes a data line 6031 and a first power supply signal line 6033. The second conductive layer 603 may be a second source-drain metal layer (SD2). The orthographic projection of the first power supply signal line 6033 on the base substrate 601 covers 50% or more of the orthographic projection of the first connection structure 6021 on the base substrate 601. That is, the first power supply signal line 6033 may completely cover the first connection structure 6021 or may cover a part of the first connection structure 6021. When the first power supply signal line 6033 completely covers the first connection structure 6021, the orthographic projection of the first power supply signal line 6033 on the base substrate 601 covers the entire orthographic projection of the first connection structure on the base substrate 601.

[0161] For example, as shown in FIGS. 21B and 22, the second conductive layer 603 further includes a first electrode transfer line 6032. For example, the planar shape of the first electrode transfer line 6032 may be rectangular. The plurality of first electrode transfer lines 6032 are installed in one-to-one correspondence with a plurality of electrode portions (not shown), and the electrode portions are connected to the first electrode transfer lines 6032 installed in correspondence therewith through via holes.

[0162] For example, as shown in FIGS. 21B and 22, the first power supply signal line 6033 includes a block-shaped portion 6033a and a strip portion 6033b connecting two adjacent block-shaped portions 6033a in the first direction Y. The strip portion 6033b connects the block-shaped portion 6033a adjacent to the edge of the block-shaped portion 6033a, and forms a storage space between the strip portion 6033b and the block-shaped portion 6033a. The first electrode transfer line 6032 is formed in the storage space.

[0163] For example, as shown in FIGS. 21B and 22, the orthographic projection of the entire data line 6031 on the base substrate 601 extends linearly along the first direction Y. In the same repeating unit, the orthographic projections of two data lines 6031 on the base substrate 601 are located between the orthographic projections of two first power signal lines 6033 on the base substrate 601.

[0164] For example, in the first direction Y, the second conductive layers 603 of any two adjacent columns of sub-pixels have a mirror-symmetric structure. In some other exemplary embodiments, in the first direction Y, the second conductive layers 603 of any two adjacent columns of sub-pixels may not have a mirror-symmetric structure.

[0165] For example, as shown in FIG. 23, the first conductive layer 602 includes at least a second initial signal line Vinit2, a first connection electrode 6021, a second connection electrode 6022, a third connection electrode 6023, a fourth connection electrode 6024, a fifth connection electrode 6025, and a sixth connection electrode 6026, as shown in FIG. 23. In some exemplary embodiments, the first conductive layer 602 may be referred to as a first source-drain metal (SD1) layer.

[0166] For example, as shown in FIGS. 21B, 22, and 23, the extending direction of the data line 6031 is the first direction Y, the direction orthogonal or substantially orthogonal to the extending direction of the data line 6031 is the second direction X, the first connection structure 6021 is in an inverted "L" shape, and the portion of the inverted "L" shape along the second direction X extends toward the side away from the data line 6031 closest to it. The end M1 of the portion of the inverted "L" shape along the second direction X away from the data line 6031 closest to it is connected to the second pole of the eighth transistor T8.

[0167] For example, as shown in FIG. 24, the orthographic projection of the block-shaped portion 6033a of the first power supply signal line 6033 on the base substrate 601 completely covers the orthographic projection of the first connection structure 6021 on the base substrate 601 and the orthographic projection of the third connection electrode 6023 on the base substrate 601. The orthographic projection of the first electrode transfer line 6032 on the base substrate 601 overlaps at least partially with the orthographic projection of at least some of the fourth connection electrodes 6024 on the base substrate 601. The orthographic projection of the strip portion 6033b of the first power supply signal line 6033 on the base substrate 601 overlaps at least partially with the orthographic projection of at least some of the fifth connection electrodes 6025 on the base substrate 601 and the orthographic projection of the sixth connection electrode 6026 on the base substrate 601. The orthographic projection of the data line 6031 on the base substrate 601 at least partially overlaps with the orthographic projection of the second connection electrode 6022 on the base substrate 601.

[0168] For example, FIG. 25 is a schematic diagram of the local structure of the first active layer in the display substrate shown in FIG. 19. For example, as shown in FIG. 25, the pixel circuit 610 includes a first active layer 605, and the first active layer 605 includes the channel regions and source-drain regions of the respective transistors. For example, the source-drain region may include a source electrode region and a drain electrode region.

[0169] For example, FIG. 25 exemplarily shows that the first active layer 605 is formed by patterning a semiconductor material. The first active layer 605 can be used to manufacture the active layers of the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to form the channel regions of the transistors. The first active layer 605 includes the active layer patterns (channel regions) and doping region patterns (source-drain regions) of the transistors of each sub-pixel, and the active layer patterns and doping region patterns of the transistors in the same pixel circuit are integrally formed.

[0170] For example, each dashed rectangular frame in FIG. 25 indicates each portion of the metal layer that overlaps with the first active layer 605, that is, the first active portion 21, the second active portion 22, the third active portion 23, the fourth active portion 24, the fifth active portion 25, the sixth active portion 26, and the seventh active portion 27, as the channel regions of the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, respectively. The portions of the first active layer 605 located on both sides of each channel region are made conductive as the first and second electrodes of each transistor, that is, the source-drain regions, by a process such as ion doping. The first active layer 605 may have an integral structure. The source and drain electrodes of each transistor may be symmetric in structure, and thus, there may be no difference in their physical structures. In the embodiments of the present disclosure, in order to distinguish the transistors, in addition to the gate electrode as the control electrode, one electrode is referred to as the first electrode and the other electrode is directly described as the second electrode. Therefore, the first and second electrodes of all or some of the transistors in the embodiments of the present disclosure can be converted as needed.

[0171] For example, as shown in FIG. 25, the shape of the channel region 23 of the driving transistor T3 may be in the shape of a "ji" character, and the shapes of the channel regions 21 of the first transistor T1, 22 of the second transistor T2, 24 of the fourth transistor T4, 25 of the fifth transistor T5, 26 of the sixth transistor T6, and 27 of the seventh transistor T7 are all in the shape of a "1" character.

[0172] For example, in some exemplary embodiments, the active structure of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0173] For example, in some exemplary embodiments, the first active layer 605 may employ polycrystalline silicon (p-Si), that is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be LTPS thin film transistors.

[0174] For example, FIG. 26 is a schematic diagram of the local structure of the third conductive layer in the display substrate shown in FIG. 19. For example, as shown in FIG. 26, the pixel circuit 610 includes a third conductive layer 606, and the third conductive layer 606 includes at least a first scanning signal line 6061 (Gate_P), a reset control signal line 6062 (Reset_P), an emission control signal line 6063 (EM_P), and a first electrode plate Cst1 of the storage capacitor C, as shown in FIG. 26. In some exemplary embodiments, the third conductive layer 606 may be referred to as a first gate metal (Gate 1) layer. The first scanning signal line 6061 can be further used as the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4. The reset control signal line 6062 can be further used as the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7. The reset control signal line 6062 can be used as the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6. The first electrode plate Cst1 of the storage capacitor C can be used as the gate electrode of the driving transistor T3.

[0175] For example, as shown in FIG. 26, in the first direction Y, the third conductive layers 606 of any two adjacent columns of sub-pixels have a mirror-symmetric structure.

[0176] For example, as shown in FIG. 26, the first scanning signal line 6061, the reset control signal line 6062, and the emission control signal line 6063 all extend along the second direction X. Within each sub-pixel, the reset control signal line 6062 is located on the side away from the emission control signal line 6063 of the first scanning signal line 6061, and the first electrode plate Cst1 of the storage capacitor is installed between the first scanning signal line 6061 and the emission control signal line 6063.

[0177] For example, as shown in FIGS. 25 and 26, the planar shape of the first electrode plate Cst1 is rectangular, and at least one corner of the rectangle may be chamfered. There is an overlapping area between the orthographic projection of the first electrode plate Cst1 on the base substrate 601 and the orthographic projection of the channel region 23 of the third transistor T3 on the base substrate 601. The region of the first active layer 605 that overlaps with the first electrode plate Cst1 is used as the channel region 23 of the third transistor T3. One end of the channel region 23 of the third transistor T3 is connected to the first region of the active region of the third transistor T3, and the other end is connected to the second region of the active region of the third transistor T3.

[0178] For example, in some exemplary embodiments, the region of the reset control signal line 6062 (Reset_P) that overlaps with the first active region of the first transistor T1 serves as the gate electrode of the first transistor T1, the region of the first scan signal line 6061 (Gate_P) that overlaps with the second active region of the second transistor T2 serves as the gate electrode of the second transistor T2, the region of the first scan signal line 6061 (Gate_P) that overlaps with the fourth active region of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4, the region of the emission control signal line 6063 (EM_P) that overlaps with the fifth active region of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5, and the region of the emission control signal line 6063 (EM_P) that overlaps with the sixth active region of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. The region of the reset control signal line Reset_P (which is the same as the signal of the first scan signal line Gate_P in the sub-pixels of this row) in the sub-pixels of the next row of each row of sub-pixels that overlaps with the seventh active region of the seventh transistor T7 in the sub-pixels of this row serves as the gate electrode of the seventh transistor T7.

[0179] For example, FIG. 27 is a schematic diagram of the local structure of the conductive film layer in the display substrate shown in FIG. 19. For example, as shown in FIG. 27, the pixel circuit 610 includes a conductive film layer 607, and the conductive film layer 607 is located between the third conductive layer 606 and the second conductive layer 603. The conductive film layer 607 includes a second scanning signal line 6071, a first conductive portion 6072, and a fifth conductive portion 6073. A part of the structure of the second scanning signal line 6071 is used to form the bottom gate of the eighth transistor T8. The first conductive portion 6072 includes the second plates Cst2 of two storage capacitors C adjacent in the first direction Y, and the fifth conductive portion 6073 is electrically connected to the first conductive layer 602. The conductive film layer 607 may be called the second gate metal (Gate 2) layer.

[0180] For example, as shown in FIG. 27, the first conductive portion 6072 includes a main body portion 6072a, the storage capacitor C further includes a second plate Cst2 facing the first plate Cst1, and the main body portion 6072a corresponds to the two second plates Cst2. For example, the first conductive portion 6072 further includes a bridge portion 6072b, and the bridge portion 6072b is connected to two main body portions 6072a adjacent in the second direction X, that is, two adjacent second plates Cst2. The first conductive portion 6072 further includes a gap 6072c between the two second plates Cst2.

[0181] For example, as shown in FIGS. 19, 23, and 27, there is no overlapping portion between the orthographic projection of the first conductive layer 602 on the base substrate 601 and the orthographic projection of the gap 6072c on the base substrate 601, and there is no overlapping portion between the orthographic projection of the second conductive layer 603 on the base substrate 601 and the orthographic projection of the gap 6072c on the base substrate 601. Thus, the gap 6072c is not shielded by the first conductive layer 602 and the second conductive layer 603, thereby improving the pixel transmittance. Note that the gap 6072c is not shielded by any other film layer with an arbitrary light-shielding effect.

[0182] For example, as shown in FIGS. 19, 23, and 27, an opening 6072d is further formed in the first conductive portion 6072, and the orthographic projection on the base substrate 601 of the via hole connected between the gate electrode of the driving transistor T3 and the first connection structure 6021 is located within the orthographic projection on the base substrate 601 of the opening 6072d, whereby the conductive structure in the via hole and the first conductive portion 6072 are insulated from each other.

[0183] For example, the display substrate further includes a second active layer. For example, FIG. 28 is a schematic diagram of a local structure of the second active layer in the display substrate shown in FIG. 19. As shown in FIGS. 19 and 28, the second active layer 608 is located between the first active layer 605 and the second conductive layer 603. The second active layer 608 may include an eighth active portion 38. The eighth active portion 38 forms the channel region of the eighth transistor T8. At both ends of the eighth active portion 38, a first region 381 and a second region 382 of the eighth transistor T8 are formed. The first region 381 of the eighth transistor T8 is adjacent to the channel region of the first transistor T1, and the second region 382 of the eighth transistor T8 is adjacent to the storage capacitor C. Moreover, the first semiconductor layer 604 includes the second active layer 608.

[0184] For example, as shown in FIGS. 19 and 28, the second active layer 608 may be formed of indium gallium zinc oxide. Correspondingly, the eighth transistor T8 may be an N-type metal oxide thin film transistor. The eighth active portion 38, the first region 381, and the second region 382 of the eighth transistor T8 all extend along the first direction Y, and the overall shape of the eighth active portion 38, the first region 381, and the second region 382 of the eighth transistor T8 may be dumbbell-shaped.

[0185] For example, the first semiconductor layer that forms the channel region of the eighth transistor T8 in the pixel circuit can be located on the side away from the base substrate 601 of the layer where the active semiconductor pattern of the driving transistor T3 is located, and the first semiconductor layer may include an oxide semiconductor material. For example, when the active layer in the eighth transistor T8 of the pixel circuit employs an oxide semiconductor, since the transistor using the oxide semiconductor has excellent hysteresis characteristics, low leakage current, and at the same time low mobility, the low-temperature polycrystalline silicon material in the transistor can be replaced with a transistor using an oxide semiconductor to form a low-temperature polycrystalline silicon-oxide (LTPO) pixel circuit, which can achieve low leakage and is advantageous for improving the stability of the gate electrode voltage of the transistor.

[0186] Of course, in the embodiments of the present disclosure, the second active layer of the pixel circuit is not limited to the structure shown in FIG. 28. In other examples, the first semiconductor layer including the channel region of the eighth transistor T8 may be located in the same layer as the semiconductor layers of the channel regions of other transistors, that is, the first active layer may include the channel regions of the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0187] For example, FIG. 29 is a partial structural schematic diagram of the fourth conductive layer in the display substrate shown in FIG. 19. For example, as shown in FIG. 29, the pixel circuit 610 further includes a fourth conductive layer 609. The fourth conductive layer 609 is located between the conductive film layer 607 and the second conductive layer 603. The fourth conductive layer 609 includes a first initial signal line Vinit1 and a fourth scanning signal line 6091, and a part of the structure of the fourth scanning signal line 6091 is configured to form the top gate of the eighth transistor T8.

[0188] For example, as shown in FIGS. 21A to 29, the second initial signal line Vinit2 included in the first conductive layer 602 extends along the second direction X, and the second initial signal line Vinit2 is connected to the first region of the seventh transistor T7 through the third via hole V3, whereby the first pole of the seventh transistor T7 and the second initial signal line Vinit2 have the same potential.

[0189] For example, as shown in FIGS. 21A to 29, the first scanning signal line 6061 includes a protruding portion 6061a extending along the first direction Y and a portion extending along the second direction X. The first end 6021a of the first connection structure 6021 is connected to the first region of the eighth transistor T8 through the fourth via hole V4, and the second end 6021b of the first connection structure 6021 is electrically connected to the gate electrode of the driving transistor T3 and the first electrode plate Cst1 of the storage capacitor C through the fifth via hole V5. The orthographic projection of the third end 6021c of the first connection structure 6021 on the base substrate 601 overlaps with the orthographic projection of the protruding portion 6061a of the first scanning signal line 6061 on the base substrate 601, whereby a coupling capacitor can be formed between the third end 6021c of the first connection structure 6021 and the protruding portion 6061a of the first scanning signal line 6061. For example, the first end 6021a of the first connection structure 6021 can be used as the second pole of the eighth transistor T8.

[0190] For example, the reverse "L" - shaped portion of the first connection structure 6021 along the first direction Y is electrically connected to the fifth conductive portion 6073 of the conductive film layer 607, and the fifth conductive portion 6073 overlaps with the protruding portion 6061a extending along the first direction Y of the first scanning signal line.

[0191] For example, as shown in FIGS. 21A to 29, the second connection electrode 6022 is connected to the first region of the fourth transistor T4 through the sixth via hole V6. In some exemplary embodiments, the second connection electrode 6022 can be used as the first pole of the fourth transistor T4.

[0192] For example, as shown in FIGS. 21A to 29, one end of the third connection electrode 6023 is connected to the first region of the second transistor T2 (i.e., the second region of the first transistor T1) through the seventh via hole V7, and the other end is connected to the first region of the eighth transistor T8 through the eighth via hole V8. In some exemplary embodiments, the third connection electrode 6023 can be used as the first pole of the eighth transistor T8, the first pole of the second transistor T2, and the second pole of the first transistor T1.

[0193] For example, as shown in FIGS. 21A to 29, on the one hand, the fourth connection electrode 6024 is connected to the second region of the sixth transistor T6 (i.e., the second region of the seventh transistor T7) through the ninth via hole V9. In some exemplary embodiments, the fourth connection electrode 6024 can be used as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 at the same time.

[0194] For example, as shown in FIGS. 21A to 29, on the one hand, the fifth connection electrode 6025 is connected to the second electrode plate Cst2 through the tenth via hole V10, and on the other hand, it is connected to the first region of the fifth transistor T5 through the eleventh via hole V11. The fifth connection electrode 6025 is further configured to be connected to a subsequently formed first power signal line.

[0195] For example, as shown in FIGS. 21A to 29, one end of the sixth connection electrode 6026 is connected to the first region of the first transistor T1 through the twelfth via hole V12, and the other end is connected to the first initial signal line. Thereby, the first pole of the first transistor T1 and the first initial signal line have the same potential.

[0196] For example, in the first direction Y, the first conductive layers 602 of any two adjacent columns of sub-pixels have a mirror-symmetric structure.

[0197] For example, the display substrate 100 further includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit 610 and a light-emitting element described in any of the above examples. FIG. 30 is a schematic diagram showing a local pixel array structure on the display substrate according to an embodiment of the present disclosure. FIG. 31A is a layout showing the stack of the pixel circuit and the first electrode of the light-emitting element in FIG. 19, and FIG. 31B is another layout showing the stack of the pixel circuit and the first electrode of the light-emitting element in FIG. 19. In FIG. 31B, a light-shielding layer is added compared to FIG. 31A, and other structure settings are the same.

[0198] For example, for the design of the local pixel array structure and each electrode portion 502 on the first electrode layer 501, reference may be made to the above related descriptions about FIGS. 14, 15A, and 15B, and detailed descriptions are omitted here.

[0199] For example, as shown in FIGS. 30, 31A, and 31B, each electrode portion 502 on the first electrode layer 501 is connected to a first electrode transfer line 6032.

[0200] For example, the display substrate 610 may include a light-shielding layer. For the related description of the light-shielding layer, reference may be made to the related description about FIG. 17, and detailed descriptions are omitted here.

[0201] For example, in some exemplary embodiments, the display substrate may further include a package layer. The package layer may include a stacked first package layer, a second package layer, and a third package layer. The first package layer and the third package layer may employ inorganic materials, and the second package layer may employ organic materials. The second package layer is disposed between the first package layer and the third package layer, thereby ensuring that external water vapor cannot penetrate into the light-emitting structure layer.

[0202] For example, FIG. 32 is a schematic cross-sectional structure diagram of a display substrate according to at least one embodiment of the present disclosure, and is described based on the 7T1C structure of the pixel circuit. For example, a first buffer layer 125 is provided on the base substrate 101, a first active layer 105 is provided on the first buffer layer 125, a first insulating layer 126 is provided on the first active layer 105, a third conductive layer 106 is provided on the first insulating layer 126, a second insulating layer 127 is provided on the third conductive layer 106, a conductive film layer 107 is provided on the second insulating layer 127, a third insulating layer 128 is provided on the conductive film layer 107, a fourth insulating layer 129 is provided on the third insulating layer 128, a second active layer 108 is provided on the fourth insulating layer 129, a fifth insulating layer 130 is provided on the second active layer 108, a fourth conductive layer 109 is provided on the fifth insulating layer 130, a sixth insulating layer 131 is provided on the fourth conductive layer 109, a first conductive layer 102 is provided on the sixth insulating layer 131. The first conductive layer 102 is electrically connected to the first active layer 105, the third conductive layer 106, and the conductive film layer 107 respectively through each via hole. A seventh insulating layer 132 is provided on the first conductive layer 102, and a second conductive layer 103 is provided on the seventh insulating layer 132. The second conductive layer 103 penetrates the via hole of the seventh insulating layer 132 and is electrically connected to the first conductive layer 102. A second planarization layer 133 is provided on the second conductive layer 103, and a first electrode layer 501 is provided on the second planarization layer 133. The first electrode layer 501 penetrates the via hole of the second planarization layer 133 and is electrically connected to the second conductive layer 103.

[0203] For example, the first buffer layer (BUF1) 125, the first insulating layer 126, the second insulating layer 127, the third insulating layer 128, the fourth insulating layer 129, the fifth insulating layer 130, and the sixth insulating layer 131 may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first buffer (BUF1) layer can be used to improve the water resistance and oxygen resistance of the base substrate 101. The first insulating layer 126 is called the first gate insulating (GI1) layer, the second insulating layer 127 is called the second gate insulating (GI2) layer, the third insulating layer 128 is called the first interlayer insulating (ILD1) layer, the fourth insulating layer 129 is called the second buffer (BUF2) layer, and the fifth insulating layer 130 is called the third gate insulating (GI3) layer.

[0204] For example, the first planarization layer 132 and the second planarization layer 133 can adopt an organic material, and the transparent conductive thin film can adopt indium tin oxide ITO or indium zinc oxide IZO. The first active layer can adopt polycrystalline silicon (p-Si), and the second active layer can adopt a metal oxide.

[0205] For example, in some exemplary embodiments, the base substrate 101 / 601 may be a flexible base or a rigid base. The rigid base may be, but is not limited to, one or more of glass and quartz. The flexible base may be, but is not limited to, one or more of polyethylene terephthalate, diethylene glycol terephthalate ester, polyether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and woven fibers. In some exemplary embodiments, the flexible base may include a laminated first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may employ materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may employ silicon nitride (SiNx) or silicon oxide (SiOx), etc., which are used to improve the water resistance and oxygen resistance of the base. The material of the semiconductor layer may employ amorphous silicon (a-si).

[0206] For example, in some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the conductive film layer, and the light-shielding layer may employ a metal material that is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or may employ an alloy material of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may have a single-layer structure or a multilayer composite structure, for example, Mo / Cu / Mo, etc.

[0207] The structure of the display substrate shown in FIG. 32 is merely exemplary. In some exemplary embodiments, the corresponding structure can be changed according to actual requirements, and the embodiments of the present disclosure are not limited thereto. The structure of the above display substrate is described by taking the 7T1C pixel circuit shown in FIG. 3 as an example. In other exemplary embodiments, the pixel circuit may have a structure such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 8T1C, etc., and the embodiments of the present disclosure are not limited thereto.

[0208] For example, FIG. 33 is a structural layout of another display substrate according to at least one embodiment of the present disclosure. In FIG. 33, the pixel circuit is taken as an example of a 7T1C pixel circuit. As shown in FIG. 33, for the structure of the first conductive layer 102, reference may be made to the above related description about FIG. 6, and for the structure of the second conductive layer 103, reference may be made to the above related description about FIG. 7, and detailed description is omitted here. As shown in FIGS. 3 and 33, the first conductive layer 102 includes a first connection structure 1021, and the orthographic projection of the first electrode transfer line 1032 on the second conductive layer 103 on the base substrate 101 overlaps at least partially with the orthographic projection of the first connection structure 1021 on the base substrate 101, that is, at least a part of the first connection structure 1021 (also called the N1 node) is shielded by the second conductive layer 103 (also called SD2), whereby a capacitor is directly formed between the second conductive layer 103 and the first connection structure 1021 located in the first conductive layer 102, that is, a capacitor is formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also called SD1), whereby a capacitor is formed between the N1 node and the data line data closest to it. The light emission control signal line EM and the second initial signal line Vinit2 both transmit stable DC signals. The second conductive layer 103 (SD2) is connected to a stable signal, and within the time of one frame, the signal changes only once. With this design, when the N1 node is operating normally, the second conductive layer 103 (SD2) can directly form a capacitor with the first conductive layer 102 (also called SD1) at the N1 node location, and the second conductive layer 103 (SD2, upper electrode plate) can be connected to a stable signal. Due to the characteristics of the capacitor itself, the voltage across both ends of the capacitor cannot change rapidly. After the upper electrode plate is connected to a stable DC signal, the signal of the first conductive layer 102 (SD1) at the N1 node location, which is the lower electrode plate, can also maintain a stable state, thereby reducing the influence of the data signal that frequently jumps within one frame time on the N1 node.The influence on the capacitor by the data signal is small, thereby reducing the influence on the N1 node by the nearby data signal, that is, shielding the influence on the N1 node by the data signal, and further improving the problem that the display panel caused by the influence of the data signal jump on the voltage of the N1 node cannot be displayed normally.

[0209] For example, in the structure shown in FIG. 33, exemplarily, each first conductive part 1074 includes only two main body parts 1074a, the storage capacitor C includes a second electrode plate Cst2, and the main body part 1074a corresponds to the two second electrode plates Cst2. For example, the first conductive part 1074 does not include other structures.

[0210] For example, other structure settings in FIG. 33 may refer to the description of the corresponding parts, and detailed descriptions are omitted here.

[0211] For example, FIG. 34 shows the structural layout of another display substrate according to at least one embodiment of the present disclosure. In FIG. 34, the pixel circuit is taken as an example of an 8T1C pixel circuit. As shown in FIG. 34, for the structure of the first conductive layer 602, reference may be made to the above-related description about FIG. 23. For the structure of the second conductive layer 603, reference may be made to the above-related description about FIG. 22, and detailed description is omitted here. As shown in FIGS. 19 and 34, the first conductive layer 602 includes a first connection structure 6021, and the orthographic projection of the first power signal line 6033 on the second conductive layer 603 on the base substrate 601 overlaps with the orthographic projection of the entire first connection structure 6021 on the base substrate 601. That is, the first connection structure 6021 (also called the N1 node) completely covers the second conductive layer 603 (also called SD2), whereby a capacitor is directly formed between the second conductive layer 603 and the first power signal line 6033 located in the first conductive layer 602. That is, a capacitor is formed between the second conductive layer 603 (SD2) and the first conductive layer 602 (also called SD1), whereby a capacitor is formed between the N1 node and the data line data closest to it. The light emission control signal line EM and the second initial signal line Vinit2 both transmit stable DC signals. The second conductive layer 603 (SD2) is connected to a stable signal, and within the time of one frame, the signal changes only once. With this design, when the N1 node is operating normally, the second conductive layer 603 (SD2) directly forms a capacitor with the first conductive layer 602 (also called SD1) at the N1 node location. The second conductive layer 603 (SD2, upper electrode plate) can be connected to a stable signal. Due to the characteristics of the capacitor itself, the voltage across the capacitor cannot change rapidly. After the upper electrode plate is connected to a stable DC signal, the signal of the first conductive layer 602 (SD1) at the N1 node location, which is the lower electrode plate, can also maintain a stable state, thereby reducing the influence of the data signal that frequently jumps within one frame time on the N1 node.The influence of the data signal on the capacitor is small, thereby reducing the influence of the nearby data signal on the N1 node, that is, shielding the influence of the data signal on the N1 node, and further improving the problem that the display panel caused by the influence of the data signal jump on the voltage of the N1 node cannot be displayed normally.

[0212] For example, in the structure shown in FIG. 34, exemplarily, each first conductive part 6074 includes only two main body parts 6074a, the storage capacitor C includes a second electrode plate Cst2, and the main body part 6074a corresponds to the two second electrode plates Cst2. For example, the first conductive part 6074 does not include other structures.

[0213] For example, other structure settings in FIG. 34 may be referred to the description of the corresponding part, and detailed description is omitted here.

[0214] For example, FIG. 35 shows the structural layout of another display substrate according to at least one embodiment of the present disclosure. In FIG. 35, the pixel circuit is taken as an example of a 7T1C pixel circuit. As shown in FIG. 35, for the structure of the first conductive layer 102, reference may be made to the above related description about FIG. 6, and for the structure of the second conductive layer 103, reference may be made to the above related description about FIG. 22, and detailed description is omitted here. As shown in FIGS. 3 and 35, the first conductive layer 102 includes a first connection structure 1021, and the orthographic projection of the first power signal line 1033 on the second conductive layer 103 on the base substrate 101 overlaps with the orthographic projection of more than 50% of the area of the first connection structure 1021 on the base substrate 101. That is, the first connection structure 1021 (also called the N1 node) completely covers the second conductive layer 103 (also called SD2), so that a capacitor is directly formed between the second conductive layer 103 and the first power signal line 1033 located in the first conductive layer 102, that is, a capacitor is formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also called SD1), so that a capacitor is formed between the N1 node and the data line data closest to it. Both the emission control signal line EM and the second initial signal line Vinit2 transmit stable DC signals. The second conductive layer 103 (SD2) is connected to a stable signal, and within the time of one frame, the signal changes only once. With this design, when the N1 node is operating normally, the second conductive layer 103 (SD2) directly forms a capacitor with the first conductive layer 102 (also called SD1) at the N1 node location. The second conductive layer 103 (SD2, upper electrode plate) can be connected to a stable signal. Due to the characteristics of the capacitor itself, the voltage across the capacitor cannot change rapidly. After the upper electrode plate is connected to a stable DC signal, the signal of the first conductive layer 102 (SD1) at the N1 node location, which is the lower electrode plate, can also maintain a stable state, thereby reducing the influence of the data signal that frequently jumps within one frame time on the N1 node.The influence on the capacitor by the data signal is small, thereby reducing the influence on the N1 node by the nearby data signal. That is, the influence on the N1 node by the data signal can be shielded, and further, the problem that the display panel cannot be normally displayed due to the influence of the data signal jump on the voltage of the N1 node can be improved.

[0215] For example, in the structure shown in FIG. 35, illustratively, each first conductive part 6074 includes only two main body parts 6074a, the storage capacitor C includes a second electrode plate Cst2, and the main body part 6074a corresponds to the two second electrode plates Cst2. For example, the first conductive part 6074 does not include other structures.

[0216] For example, as shown in FIG. 35, there is no overlapping part between the first electrode transfer line 1032 and the first connection structure 1021.

[0217] For example, for other structure settings in FIG. 35, reference may be made to the description of the corresponding parts, and detailed description is omitted here.

[0218] For example, FIG. 36 is a structural layout of another display substrate according to at least one embodiment of the present disclosure. For the layer structure shown in FIG. 36, the display substrate may include a first electrode layer 501 located on the side away from the base substrate 101 of the second conductive layer 103. By this installation, the lower part of the first electrode (positive electrode) in the pixel unit is flattened, and further, the balance of the capacitor can be maintained. As shown in FIG. 36, the first electrode layer 501 includes a plurality of electrode parts 502, and each electrode part 502 includes a connected main body part 5021 and an additional part 5022. Each electrode part 502 corresponds to one of the first sub-pixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third sub-pixel 403. For example, the first electrodes (positive electrodes) corresponding to the first sub-pixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third sub-pixel 403 are all installed as high as possible above the first power signal line 1033 of the second conductive layer 103.

[0219] For example, if an additional part 5022 is installed on the electrode part 502, the overlapping area between the electrode part 502 and the second conductive layer 103 can be increased. For example, the additional part 5022 corresponding to the electrode parts 502 of the first pixel block 4020a and the second pixel block 4020b can cover the long-shaped position of the edge of the first power signal line 1033, and the additional part 5022 corresponding to the electrode parts 502 of the first sub-pixel 401 and the third sub-pixel 403 is covered by the block part of the first power signal line 1033, thereby further increasing the overlapping area between the electrode part 502 and the second conductive layer 103.

[0220] At least one embodiment of the present disclosure further provides a display device including any one of the above display substrates. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., but is not limited thereto in the embodiments of the present invention. The following points need to be explained.

[0221] (1) The drawings of the embodiments of the present disclosure relate only to the structures according to the embodiments of the present disclosure, and other structures can refer to the normal design.

[0222] (2) Unless there is a conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0223] The above are only exemplary embodiments of the present disclosure and do not limit the protection scope of the present disclosure. The patent scope of the present disclosure should conform to the appended claims.

Description of Reference Numerals

[0224] 100 Display substrate 101 Base substrate 102 First conductive layer 103 Second conductive layer 104 First semiconductor layer 107 Conductive film layer 110 Pixel circuit 120 Light-emitting element 1021 First connection structure 1074 First conductive part C Storage capacitor Cst1 First electrode plate Cst2 Second electrode plate T3 Drive transistor

Claims

1. A display substrate, comprising: a base substrate; and a pixel circuit located on the base substrate and including a storage capacitor, the storage capacitor including opposing first and second electrodes, wherein the display substrate further includes a conductive film layer including a first conductive portion, the first conductive portion including a main body portion corresponding to the two second electrodes and a bridge portion connecting the two second electrodes, and the first conductive portion including a gap between the two second electrodes.

2. wherein the pixel circuit further includes a driving transistor, the display substrate further includes a first conductive layer, a second conductive layer, and a first semiconductor layer, the first conductive layer including a first connection structure including opposing first and second ends, the first end being connected to the first semiconductor layer, and the second end being electrically connected to a gate electrode of the driving transistor and the first electrode of the storage capacitor, the first conductive layer being located on a side of the first semiconductor layer away from the base substrate, the second conductive layer being located on a side of the first conductive layer away from the base substrate, and a projection of the second conductive layer on the base substrate overlapping at least a portion of a projection of the first connection structure on the base substrate. The display substrate according to claim 1.

3. wherein a projection of the first conductive layer on the base substrate and a projection of the gap on the base substrate do not have an overlapping portion, and a projection of the second conductive layer on the base substrate and a projection of the gap on the base substrate do not have an overlapping portion. The display substrate according to claim 2.

4. wherein a projection of the second electrode on the base substrate and a projection of the first electrode on the base substrate at least partially overlap. The display substrate according to claim 2.

5. wherein an opening is formed in the second electrode, a projection of a via hole connected between a gate electrode of the driving transistor and the first connection structure on the base substrate overlaps a projection of the opening on the base substrate, and a conductive structure in the via hole and the second electrode are insulated from each other. The display substrate according to claim 4.

6. It further includes a plurality of sub-pixels, each of the sub-pixels includes the pixel circuit and a light-emitting element, the first conductive layer is located between the first electrode of the light-emitting element and the first semiconductor layer, and the second conductive layer is located between the first conductive layer and the first electrode of the light-emitting element. The display substrate according to any one of claims 2 to 5.

7. The second conductive layer includes data lines spaced apart from each other, a first electrode transfer line, and a first power signal line. The first electrode transfer line is connected to the first electrode of the light-emitting element, and a positive projection of the first electrode transfer line on the base substrate overlaps a positive projection of a part of the first connection structure on the base substrate. The display substrate according to claim 6.

8. The first electrode transfer line is elongated and extends along the extending direction of the data line closest to it as a whole. The first connection structure is in a folded line shape extending toward the side away from the data line closest to it as a whole, and includes a part overlapping the first electrode transfer line and a part not overlapping the first electrode transfer line. The part not overlapping is farther from the data line closest to it than the overlapping part. The display substrate according to claim 6.

9. The extending direction of the data line is the first direction, and the direction perpendicular or substantially perpendicular to the extending direction of the data line is the second direction. The first conductive layer further includes a power signal connection line. The power signal connection line includes a main body part and a branch part. The overall extending direction of the power signal connection line is parallel to the second direction, and the extending direction of the branch part is parallel to the first direction. The first power signal line includes a block part and a strip part that extends along the first direction as a whole and connects adjacent block parts. The main body part of the power signal connection line is connected to the first power signal line to form a grid shape. The display substrate according to claim 7 or 8.

10. The strip part includes a first strip part and a second strip part installed opposite to each other, and a third strip part connecting the first strip part and the second strip part. The extending directions of the first strip part and the second strip part are parallel to the first direction, and the third strip part is connected to the intermediate region between the first strip part and the second strip part. The display substrate according to claim 9.

11. The strip part includes a hollow structure. The display substrate according to claim 10.

12. The display substrate according to any one of claims 8 to 11, wherein the width of the block portion in the second direction is larger than the width of the entire strip portion in the second direction.

13. The display substrate according to any one of claims 7 to 12, wherein the second electrode plate is electrically connected to the first power signal line.

14. The pixel circuit further includes a first transistor, a second transistor, a sixth transistor, and a seventh transistor. A first pole of the first transistor is connected to a gate electrode of the driving transistor, a second pole of the first transistor is connected to a first initial signal line, a first pole of the second transistor is connected to the gate electrode of the driving transistor, a second pole of the second transistor is connected to a second pole of the driving transistor, a first pole of the sixth transistor is connected to the second pole of the driving transistor, a first pole of the seventh transistor is connected to a second pole of the sixth transistor, and a second pole of the seventh transistor is connected to a second initial signal line. The display substrate is A first active layer located between the base substrate and the second conductive layer and including a third active portion, a sixth active portion, and a seventh active portion, wherein the third active portion is configured to form a channel region of the driving transistor, the sixth active portion is configured to form a channel region of the sixth transistor, and the seventh active portion is configured to form a channel region of the seventh transistor; and the first active layer A second active layer located between the first active layer and the second conductive layer and including a first active portion and a second active portion, wherein the first active portion is configured to form a channel region of the first transistor, the second active portion is connected to the first active portion, and the second active portion is configured to form a channel region of the second transistor. The display substrate according to any one of claims 7 to 13 further includes the second active layer.

15. The display substrate includes a plurality of repeating units distributed along the first direction and the second direction. Each repeating unit includes two of the pixel circuits. The two pixel circuits include a first pixel circuit and a second pixel circuit distributed along the second direction. The first pixel circuit and the second pixel circuit are installed in mirror symmetry. Each of the pixel circuits further includes a fourth transistor and a fifth transistor. A first pole of the fourth transistor is connected to the data line, a second pole of the fourth transistor is connected to a first pole of the driving transistor, a first pole of the fifth transistor is connected to the first power supply signal line, and a second pole of the fifth transistor is connected to the first pole of the driving transistor. The first active layer is a fourth active part connected to one side of the third active part and configured to form a channel region of the fourth transistor, and a fifth active part configured to form a channel region of the fifth transistor, The display substrate according to claim 14, further comprising.

16. Further including a third conductive layer, the third conductive layer a second gate line whose orthographic projection on the base substrate extends along the second direction and overlaps with the orthographic projection of the fourth active part on the base substrate, and a part of the structure forms a gate electrode of the fourth transistor, a light emission control signal line whose orthographic projection on the base substrate extends along the second direction and overlaps with the orthographic projection of the sixth active part on the base substrate, and a part of the structure forms a gate electrode of the sixth transistor, a second reset signal line whose orthographic projection on the base substrate extends along the second direction and overlaps with the orthographic projection of the seventh active part on the base substrate. A part of the structure of the second reset signal line is used to form a gate electrode of the seventh transistor, and the second gate line in the pixel circuit of this row is multiplexed with the second reset signal line in the pixel circuit of the adjacent row. a second conductive part whose orthographic projection on the base substrate overlaps with the orthographic projection of the third active part on the base substrate and is configured to form a gate electrode of the driving transistor and a first electrode plate of the storage capacitor. In the same pixel circuit, the orthographic projection of the second conductive part on the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the light emission control signal line on the base substrate. The display substrate according to claim 15, wherein the orthographic projection of the second reset signal line on the base substrate is located on a side away from the orthographic projection of the second conductive part of the orthographic projection of the light emission control signal line on the base substrate.

17. Further comprising a fourth conductive layer, the fourth conductive layer being located between the second active layer and the second conductive layer, A first reset signal line whose orthographic projection on the base substrate overlaps with the orthographic projection of the first active portion on the base substrate and a part of whose structure is configured to form the top gate of the first transistor, A first gate line whose orthographic projection on the base substrate overlaps with the orthographic projection of the second active portion on the base substrate and a part of whose structure is configured to form the top gate of the second transistor, In the same pixel driving circuit, the orthographic projection of the first gate line on the base substrate is located between the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the second gate line on the base substrate, and the orthographic projection of the first reset signal line on the base substrate is located on the side away from the orthographic projection of the second conductive portion on the base substrate of the orthographic projection of the second gate line on the base substrate. The display substrate according to claim 16.

18. The conductive film layer, A first initial signal line whose orthographic projection on the base substrate is located on the side away from the orthographic projection of the second conductive portion on the base substrate of the orthographic projection of the first reset signal line on the base substrate, Connected to the first reset signal line through a via hole, the orthographic projection of which on the base substrate overlaps with the orthographic projection of the first active portion on the base substrate, and a part of whose structure is a third reset signal line for forming the bottom gate of the first transistor, The orthographic projection of which on the base substrate overlaps with the orthographic projection of the second active portion on the base substrate, and a part of whose structure is a third gate line for forming the bottom gate of the second transistor. The display substrate according to claim 17, further comprising:

19. The plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, Two of the second sub-pixels constitute a second sub-pixel pair, and the two second sub-pixels in one second sub-pixel pair are a first pixel block and a second pixel block respectively, and the first pixel block and the second pixel block are alternately arranged along the first direction or the second direction. The plurality of sub-pixels includes a plurality of minimum repeating units, and one of the minimum repeating units includes one of the first sub-pixels, one of the first pixel blocks, one of the second pixel blocks, and one of the third sub-pixels. The display substrate according to any one of claims 7 to 18.

20. Further including a first electrode layer, the first electrode layer is located on the side of the second conductive layer away from the base substrate, the first electrode layer includes a plurality of electrode portions, and each of the electrode portions includes a main body portion and an additional portion that are connected. The orthographic projection of the additional portion on the base substrate at least partially overlaps the orthographic projection of the first electrode transfer line on the base substrate. Each of the electrode portions corresponds to one of the first sub-pixel, the first pixel block, the second pixel block, and the third sub-pixel. The display substrate according to claim 19.

21. The plurality of electrode portions includes first, second, and third electrode portions of different three colors. The first electrode portion corresponds to the first sub-pixel, the second electrode portion corresponds to one of the first pixel block and the second pixel block, and the third electrode portion corresponds to the third sub-pixel. The overlapping area between the orthographic projection of the first electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate is larger than the overlapping area between the orthographic projection of the second electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate, and is also larger than the overlapping area between the orthographic projection of the third electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate. The overlapping area between the orthographic projection of the third electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate is larger than the overlapping area between the orthographic projection of the second electrode portion on the base substrate and the orthographic projection of the first power signal line on the base substrate. The display substrate according to claim 20.

22. The first electrode portion corresponds to a blue sub-pixel that emits blue light, the second electrode portion corresponds to a green sub-pixel that emits green light, and the third electrode portion corresponds to a red sub-pixel that emits red light. The display substrate according to claim 21.

23. The second conductive layer further includes a plurality of second connection structures, and the plurality of second connection structures are installed in one-to-one correspondence with the plurality of electrode portions. The electrode portion is connected to the second connection structure installed corresponding thereto through a via hole. The display substrate according to any one of claims 20 to 22.

24. The sub-pixel further includes a shielding portion located on a side of the active semiconductor pattern of the driving transistor away from the base substrate, and a front projection of the shielding portion on the base substrate at least partially overlaps a front projection of the active semiconductor pattern of the driving transistor on the base substrate. The display substrate according to any one of claims 2 to 23.

25. A display device including the display substrate according to any one of claims 1 to 24.

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