Capacitive sensor with an irregular shape and the position of a touch event thereon

Abstract

The method includes changing the geometry of a capacitive sensor structure from a first geometry to a second geometry different from the first geometry, and obtaining executable instructions for converting a position identifier of a touch event from a first position identifier associated with the first geometry to a second position identifier associated with the second geometry.

Description

Technical Field

[0001] (Claims of Priority) This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 366,682, filed Jun. 20, 2022, entitled “CAPACITIVE SENSOR GEOMETRY DISTORTION TO DESIGN A CAPACITIVE SENSOR HAVING AN IRREGULAR GEOMETRY, AND CAPACITIVE SENSORS HAVING IRREGULAR GEOMETRIES,” the entire contents and disclosure of which are incorporated herein by reference.

[0002] (Field of the Invention) Embodiments relate to capacitive sensors, capacitive sensors having irregular geometries, and reporting the location of touch events therein.

Background Art

[0003] Capacitive sensors are used in a variety of operating situations, including but not limited to touchscreens, touch pads, and capacitive buttons.

Brief Description of the Drawings

[0004] To easily identify any particular element or action, the leading digit of the reference number refers to the figure number in which the element was first introduced.

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DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized and structural, material, and process changes may be made without departing from the scope of the present disclosure.

[0006] The figures presented in this specification are not intended to be actual figures of any specific method, system, device, or structure, but are merely idealized representations used to illustrate embodiments of the present disclosure. The drawings presented in this specification are not necessarily drawn to scale. Similar structures or components in the various drawings may retain the same or similar reference numerals for the convenience of the reader. However, similarity in reference numerals does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to assist those skilled in the art in implementing the disclosed embodiments. The use of the terms "exemplary," "as an example," "for example" means that the associated description is illustrative, and the scope of the present disclosure is intended to include the examples and legal equivalents, and the use of such terms is not intended to limit the embodiments or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0008] It will be readily understood that the components of the embodiments generally described herein and illustrated in the drawings can be arranged and designed in a wide variety of different configurations. Accordingly, the following description of the various embodiments is not intended to limit the scope of the present disclosure, but merely represents the various embodiments. Although various aspects of the embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementation manners illustrated and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in the form of block diagrams so as not to obscure the present disclosure with unnecessary details. Conversely, the specific implementation manners illustrated and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Additionally, the logical block definitions and partitioning among various blocks are examples of specific implementation manners. It will be readily apparent to those skilled in the art that the present disclosure may be implemented by many other partitioning solutions. For the most part, details regarding timing considerations and the like are omitted as such details are not necessary to obtain a full understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. In some of the drawings, a signal may be illustrated as a single signal for clarity of presentation and description. Those skilled in the art will understand that a signal may represent a signal bus, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals including a single data signal.

[0011] The various exemplary logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed using any combination of a general-purpose processor, a dedicated processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any design to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) can be a microprocessor, but instead, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such combination of computing devices. A general-purpose computer including a processor is regarded as a dedicated computer, and the general-purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0012] Embodiments can be described with respect to a process depicted as a flowchart, a flow diagram, a structural diagram, or a block diagram. A flowchart can illustrate operational acts as a sequential process, although many of these acts can be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of the acts can be rearranged. A process can correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, but is not limited thereto. Further, the methods disclosed herein can be implemented in hardware, software, or both. When implemented in software, the functionality can be stored or transmitted as one or more instructions or code on a computer-readable medium. A computer-readable medium includes both a computer storage medium and a communication medium including any medium that facilitates transfer of a computer program from one place to another.

[0013] Any reference in this specification to an element using the notations "first", "second", etc. does not limit the quantity or order of those elements unless such a limitation is explicitly stated. Rather, these notations can be used herein as a convenient way to distinguish between two or more elements or instances of an element. Thus, a reference to a first element and a second element does not mean that only two elements can be used or that the first element must precede the second element in any manner. Additionally, unless otherwise specified, a set of elements can include one or more elements.

[0014] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes that the given parameter, characteristic, or condition meets the degree of small variations that one of ordinary skill in the art would understand, for example, within the range of acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition being substantially met, the parameter, characteristic, or condition can be met at least 90%, at least 95%, or even at least 99%.

[0015] In this description, the term "coupled" and its derivatives can be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements can be in direct physical or electrical contact, or there can be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, there are no intervening elements or layers. The terms "on" and "connected" can be used interchangeably with the term "coupled" in this specification and have the same meaning unless explicitly indicated otherwise or unless the context indicates otherwise to one of ordinary skill in the art.

[0016] As used herein, the term "geometry" means the shape and relative arrangement of some part. As used herein, the term "irregular geometry" means a geometry that is not rectangular. Non-limiting examples include geometries that include non-uniform sides, non-uniform angles, or non-uniform curves. As used herein, the term "irregularly shaped" means "having an irregular geometry" unless explicitly defined otherwise or unless the particular context in which this term is used indicates otherwise to one of ordinary skill in the art.

[0017] In a typical capacitance sensor configuration for capacitance detection, electrodes are respectively arranged in rows and columns of a grid (sometimes called "X electrodes" and "Y electrodes"), and the intersections of the X electrodes and the Y electrodes are called "sensor nodes". When an alternating current stimulus is applied to the capacitance sensor, the electrodes measure the capacitance. When a conductive object such as a finger or a stylus is suitably close to a sensor node (e.g., but not limited to, nearby or in contact), at least some of the electrodes measure different capacitances, i.e., the measured capacitances of those electrodes change. Capacitance detection involves detecting such changes in the measured capacitance.

[0018] In a typical two - dimensional (2D) arrangement of a capacitance sensor ("sensor"), the grid has a rectangular shape, and each sensor node of the sensor has a uniform rectangular shape. A typical touch controller is pre - configured to detect changes in capacitance in a sensor having a rectangular shape. Symmetry is advantageous for capacitance detection (especially mutual capacitance detection) because the balance of the influence of capacitive loads (e.g., a conductive object suitably close to a sensor node) is achieved.

[0019] Sometimes, it may be desirable to have a sensor with a non - rectangular shape (e.g., but not limited to, trapezoidal or elliptical, and regular or irregular). As a non - limiting example, a non - rectangular sensor may be paired with a non - rectangular display, touch pad, button, or slider.

[0020] A touch controller pre - configured to detect changes in capacitance in a sensor having a rectangular shape may produce incorrect or inaccurate results when paired with a sensor having a non - rectangular shape. For example, a touch controller that creates orthogonal coordinates ("coordinates") associated with the position of a touch event in a sensor may create coordinates different from the actual coordinates of the position of the touch event in a non - rectangular sensor.

[0021] One or more embodiments generally relate to distorting the geometry of a capacitive sensor structure from a first regular geometry to a second irregular geometry, and methods, apparatuses, and systems for doing so. The distorted capacitive sensor structure can determine the dimensions of a physical capacitive sensor fabricated based on the structure.

[0022] One or more embodiments generally relate to creating a position identifier (e.g., but not limited to, Cartesian coordinates) of a touch event in a capacitive sensor having an irregular geometry, configuring a controller to create a position identifier of a touch event in a capacitive sensor having an irregular geometry, and methods, apparatuses, and systems for doing so. The controller can be preconfigured to create a position identifier of a capacitive sensor having a regular geometry, and one or more embodiments can relate to changing a position identifier of a capacitive sensor having a regular geometry to a position identifier of a capacitive sensor having an irregular geometry.

[0023] One or more embodiments generally relate to a controller configured to create a position identifier of a touch event in a capacitive sensor having an irregular geometry, and a capacitive sensing system including the same.

[0024] Figures 1A and 1B are graphical representations of a capacitive sensor structure before (the "capacitive sensor structure to be distorted") and after (the "distorted capacitive sensor structure") distortion, according to one or more embodiments.

[0025] In each of FIGS. 1A and 1B, an X-axis and a Y-axis defining an XY plane are depicted. The numbers on the X-axis and Y-axis increase in a linear scale from the origin. Using the XY pairs of these numbers, the position of a specific point on the XY plane can be represented as unique coordinates according to the coordinate system. These numbers can be used to represent the distance from the origin. In a Cartesian coordinate system, the intervals between the numbers are uniform. The coordinate system defined by the X-axis and Y-axis depicted by FIGS. 1A and 1B is a Cartesian coordinate system. By convention, height is the distance on the Y-axis and width is the distance on the X-axis, but the use of this convention in this specification is merely for convenience and is in no way intended to limit the scope of the present disclosure in any way.

[0026] FIG. 1A is a graphical representation of a capacitive sensor structure 100a to be distorted, which may also be referred to herein as the capacitive sensor structure 100a to be distorted. The capacitive sensor structure to be distorted may also be referred to herein as the "reference capacitive sensor structure" or simply the "reference structure".

[0027] The capacitive sensor structure 100a to be distorted includes a sensor 102. The sensor 102 includes X electrodes and Y electrodes arranged in a grid pattern. The X electrodes and Y electrodes may be in the same layer, or may be different layers where one overlaps the other, or they may form them. Each intersection 104 of the X electrodes and Y electrodes forms a respective sensor node 106 of the sensor 102.

[0028] Sensor 102 has a regular geometric shape. Specifically, sensor 102 has uniform dimensions, the height of sensor 102 is 25, the width of sensor 102 is 25, the length of each column of electrodes is 25, and the length of each row of electrodes is 25. Further, each row and column of sensor 102 has the same number of sensor nodes, and each sensor node has the same area (the area of each node of the node, "node area"). The capacitance type sensor structure 100a to be distorted and the coordinate plane of its geometry are the XY plane defined by the contour of sensor 102.

[0029] Since the node area of sensor node 106 and the number of sensor nodes are uniform, when there is no touch event (that is, when there is no object suitably close to one or more sensor nodes that affect capacitance measurement), the capacitance and capacitance value of each node of sensor 102 (for example, but not limited to, the value generated by receiving capacitance measurement) can be represented by the formula of a uniform parallel plate capacitor

[0030]

Number

[0031] FIG. 1B is a graphical representation of a distorted capacitive sensor structure 100b according to one or more embodiments, and is also referred to herein as the distorted capacitive sensor structure 100b. The distorted capacitive sensor structure 100b was created by distorting the geometry of sensor 102 of the capacitive sensor structure 100a to be distorted, as will be described below. In one or more embodiments, the distorted capacitive sensor structure may correspond to a target capacitive sensor structure. The target capacitive sensor structure may also be referred to herein as the "target structure".

[0032] The distorted capacitive sensor structure 100b includes a distorted sensor 108 that includes X and Y electrodes arranged in a grid pattern. The X and Y electrodes may be in the same layer, may be different layers with one overlapping the other, or may form them. Each intersection of the X and Y electrodes of the distorted sensor 108 forms a respective sensor node of the distorted sensor 108.

[0033] The distorted sensor 108 has an irregular geometry. More specifically, the distorted sensor 108 does not have uniform dimensions. The width at the top is about 20, the width at the bottom is about 25, and the length of each row of the sensor 102 increases from the bottom row with a width of about 25 to the top row with a width of about 20. The lengths of the left and right sides of the distorted sensor 108 are different, and the formula

[0034]

Number

[0035] The position of a point on the region defined by the distorted sensor 108 may be represented according to the Cartesian coordinate system of the capacitive sensor structure 100a to be distorted, or according to another coordinate system which is a distorted version of the coordinate system of the capacitive sensor structure 100a to be distorted. In the distorted coordinate system, the intervals on the X-axis and Y-axis are not uniform. The intervals of the distorted coordinate system are defined by the intervals in the X-direction and Y-direction between the intersections of the X-electrodes and Y-electrodes of the distorted capacitive sensor structure 100b, which does not match either the interval between the intersections of the X-electrodes and Y-electrodes of the capacitive sensor structure 100a to be distorted or the interval of the numbers on the X-axis and Y-axis.

[0036] The distorted capacitive sensor structure 100b is associated with the Cartesian coordinate system of FIG. 1A and is also associated with a coordinate system different from that of the capacitive sensor structure 100a to be distorted.

[0037] The area of each sensor node of the distorted sensor 108 is substantially uniform (i.e., here, the node area is substantially uniform if the difference from the minimum area to the maximum area is <25%), and the geometric shape of each sensor node is different in at least some cases (e.g., without limitation, the height or width of each sensor node is different), and thus may not be substantially uniform. In the specific non-limiting example depicted by FIG. 1B, the geometric shape of the sensor node 110 is different from that of the sensor node 112. The widths of the sensor node 110 and the sensor node 112 are different, and the heights of the sensor node 110 and the sensor node 112 are different. In particular, the node areas of the sensor node 110 and the sensor node 112 are substantially the same (i.e., uniform as will be described below).

[0038] The number of sensor nodes in each row of the distorted sensor 108 is uniform, the respective node areas of the sensor nodes of the distorted sensor 108 are substantially uniform, and the respective capacitances and capacitance values of the X electrode and the Y electrode of the distorted sensor 108 in the absence of touch are substantially uniform (the capacitance is substantially uniform when the difference from the minimum capacitance to the maximum capacitance is ≦ 20%, but some higher or lower variations may be tolerated based on specific operating conditions), and are based on the formula of a parallel plate capacitor (described above). Since the capacitance is substantially uniform, the capacitance response to touch is substantially uniform (that is, here, when the difference from the response of the minimum capacitance to the response of the maximum capacitance is <XYZ%, the capacitance response to touch is substantially uniform). Since the capacitance response to touch is substantially uniform, a touch controller configured to detect touch events on a sensor having a regular geometry can reliably detect touch events on the distorted sensor 108.

[0039] The above-described visual difference between the capacitance type sensor structure 100a to be distorted and the distorted capacitance type sensor structure 100b represents the distortion applied to the capacitance type sensor structure 100a to be distorted, as described below.

[0040] When a touch controller configured to detect touch in the sensor 102 is used to detect touch in the distorted sensor 108, the coordinates used to represent the position of the touch event detected by the touch controller are associated with the coordinate plane of the capacitance type sensor structure 100a to be distorted. For example, in the case of a touch event at the upper right corner of the distorted sensor 108, such a touch controller outputs XY coordinates (25, 25), but the actual XY coordinates are (24, 25).

[0041] The coordinate plane is known for both the capacitive sensor structure 100a to be distorted and the distorted capacitive sensor structure 100b. Thus, the transformation for changing the coordinates associated with the coordinate plane of the capacitive sensor structure 100a to be distorted to the coordinates associated with the coordinate plane of the distorted capacitive sensor structure 100b can be determined as described below.

[0042] FIG. 2 is a flow diagram depicting a process 200 for distorting the geometry of a capacitive sensor structure from a first regular geometry to a second irregular geometry according to one or more embodiments. Process 200 is a non-limiting example of a process for distorting a capacitive sensor structure 100a to be distorted into a distorted capacitive sensor structure 100b.

[0043] The exemplary process 200 depicts a particular sequence of operations, but that sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the function of process 200. In other embodiments, the various components of an exemplary device or system implementing process 200 may function substantially simultaneously or in a particular order.

[0044] According to one or more embodiments, process 200 includes, in operation 202, changing the geometry of the capacitive sensor structure from a first geometry to a second geometry, where the second geometry is different from the first geometry. In one or more embodiments, the first geometry may be a regular geometry and the second geometry may be an irregular geometry.

[0045] According to one or more embodiments, in operation 204, process 200 includes obtaining executable instructions (e.g., but not limited to, software, firmware, machine-executable instructions) for converting a position identifier of a touch event from a first position identifier associated with a first geometry to a second position identifier associated with a second geometry. Obtaining executable instructions includes, but is not limited to, generating executable instructions. In one or more embodiments, each position identifier is XY coordinates in a Cartesian coordinate system. In one or more embodiments, the first position identifier is associated with the coordinate plane of the first geometry and thus is associated with the first geometry. In one or more embodiments, the second position identifier is associated with the coordinate plane of the second geometry based on the applied transformation and thus is associated with the second geometry.

[0046] FIG. 3 is a flowchart depicting a process 300 for distorting the geometry of a capacitive sensor structure according to one or more embodiments.

[0047] Exemplary process 300 depicts a particular sequence of operations, but the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the functionality of process 300. In other embodiments, the various components of an exemplary device or system implementing process 300 may function substantially simultaneously or in a particular order.

[0048] According to one or more embodiments, process 300 includes, in operation 302, stretching, narrowing, or deforming the geometry of the capacitive sensor structure or the respective geometries of one or more of its sensor nodes. In one or more embodiments, stretching, narrowing, or deforming the geometry of the capacitive sensor structure may include increasing or decreasing the height, width, or both of the capacitive sensor structure or the region corresponding to its sensor nodes, increasing or decreasing the length of each row or column of the capacitive sensor structure or its sensor nodes, rotating the region corresponding to the capacitive sensor structure or its sensor nodes about an axis perpendicular thereto, or combinations and partial combinations thereof.

[0049] According to one or more embodiments, process 300 includes, in operation 304, keeping the number of sensor nodes of the capacitive sensor structure the same between a first geometry and a second geometry.

[0050] According to one or more embodiments, process 300 includes, in operation 306, keeping the respective node areas of one or more sensor nodes of the capacitive sensor structure substantially uniform.

[0051] FIG. 4 is a flow diagram depicting a process 400 for changing the geometry of a capacitive sensor structure from a first geometry to a second geometry according to one or more embodiments.

[0052] Exemplary process 400 depicts a particular sequence of operations, but the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the functionality of process 400. In other embodiments, the various components of an exemplary device or system implementing process 400 may perform functions substantially simultaneously or in a particular order.

[0053] According to one or more embodiments, process 400 includes, in operation 402, obtaining a reference capacitance type sensor structure and a target capacitance type sensor structure. The geometry of the reference capacitance type sensor structure is a first geometry, and the geometry of the target capacitance type sensor structure is a second geometry. The first and second geometries are different and, as non-limiting examples, may be a regular geometry and an irregular geometry, respectively. The reference capacitance type sensor structure is the capacitance type sensor structure to be distorted. The target capacitance type sensor structure represents the requirements of the distorted capacitance type sensor structure. Theoretically, the distorted capacitance type sensor structure should match the target capacitance type sensor structure. The degree to which the distorted capacitance type sensor structure matches the target capacitance type sensor structure is a matter of design choice and may depend, as a non-limiting example, on a particular use or particular operating conditions of a system including the capacitance type sensor by the distorted capacitance type sensor structure.

[0054] According to one or more embodiments, process 400 includes, in operation 404, mapping the geometry of the reference capacitance type sensor structure to the geometry of the target capacitance type sensor structure.

[0055] According to one or more embodiments, process 400 includes, in operation 406, setting each node area of the mapped reference capacitance type sensor structure to be substantially uniform.

[0056] According to one or more embodiments, process 400 includes, in operation 408, finishing each sensor node geometry of the mapped reference capacitance type sensor structure. Here, "finishing" refers to an act performed, if any, to refine and complete the outer shape, fitting, or function of the sensor node geometry.

[0057] FIG. 5 is a flow diagram depicting a process 500 for mapping the geometry of a reference structure to the geometry of a target structure, according to one or more embodiments.

[0058] Exemplary process 500 depicts a particular sequence of operations, but the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the functionality of process 500. In other embodiments, the various components of an exemplary device or system implementing process 500 may function substantially simultaneously or in a particular order.

[0059] According to one or more embodiments, process 500 includes, in operation 502, obtaining a reference capacitance-based sensor structure and a target capacitance-based sensor structure. The geometry of the reference capacitance-based sensor structure is a first geometry, and the geometry of the target capacitance-based sensor structure is a second geometry. The first and second geometries are different and, as non-limiting examples, may be a regular geometry and an irregular geometry, respectively.

[0060] According to one or more embodiments, process 500 includes, in operation 504, identifying a constituent geometry that matches a predetermined geometry in the geometry of the target capacitance-based sensor structure.

[0061] According to one or more embodiments, the method includes, in operation 506, dividing the geometry of the reference capacitance-based sensor structure into rectangular sub-geometries. Each rectangular sub-geometry includes each of the identified constituent geometries of the target capacitance-based sensor structure.

[0062] According to one or more embodiments, process 500 includes, in operation 508, calculating, for each Y coordinate, each X coordinate of the constituent geometries.

[0063] According to one or more embodiments, process 500 includes, in operation 510, determining a function that describes the relationship between the X coordinates of the configured geometry and the Y coordinates of the rectangular sub-geometry.

[0064] According to one or more embodiments, process 500 includes, in operation 512, returning the XY coordinates for the geometry of the target capacitance-type sensor structure and the function for determining them. The function for determining the X and Y coordinates is a coordinate transformation.

[0065] FIG. 6 is a flowchart depicting a process 600 for setting the respective node areas of a mapped reference structure to be substantially uniform according to one or more embodiments.

[0066] Exemplary process 600 depicts a particular sequence of operations, but the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the function of process 600. In other embodiments, the various components of an exemplary device or system implementing process 600 may perform functions substantially simultaneously or in a particular order.

[0067] According to one or more embodiments, the method includes obtaining a scaling factor in operation 602.

[0068] According to one or more embodiments, the method includes, in operation 604, scaling the dimensions of each node area of the mapped reference structure according to the scaling factor.

[0069] FIG. 7 is a flowchart depicting a process 700 for scaling the dimensions of each node area of a mapped reference structure according to a scaling factor according to one or more embodiments.

[0070] Exemplary process 700 depicts a particular sequence of operations, but the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the functionality of process 700. In other embodiments, the various components of the exemplary device or system implementing process 700 may function substantially simultaneously or in a particular order.

[0071] According to one or more embodiments, process 700 includes receiving a ratio value and an increment value in operation 702.

[0072] According to one or more embodiments, process 700 includes applying the ratio value to the height of the bottom row of the reference structure in operation 704.

[0073] According to one or more embodiments, process 700 includes incrementing the ratio value by the increment value in operation 706.

[0074] According to one or more embodiments, process 700 includes applying the incremented ratio value to the height of the next row of the reference structure in operation 708.

[0075] According to one or more embodiments, process 700 includes determining in decision block 710 whether all rows have been allocated. If process 700 receives a "no" determination at decision block 710, the process returns to operation 706 to increment the ratio value by the increment value and continue in the same manner. If process 700 receives a "yes" determination at decision block 710, process 700 proceeds to decision block 712.

[0076] According to one or more embodiments, process 700 includes, at decision block 712, calculating a maximum sensor node area, a minimum sensor node area, and a maximum area difference. The maximum area difference is calculated as the difference between the calculated maximum sensor node area and the calculated minimum sensor node area. The maximum sensor node area is the area of each sensor node having the maximum area calculated by process 700, and the minimum sensor node area is the area of each further sensor node having the minimum area calculated by process 700.

[0077] According to one or more embodiments, process 700 includes, at decision block 714, determining whether the maximum area difference is acceptable. In one or more embodiments, determining whether the maximum area difference is acceptable includes comparing the maximum area difference to a predetermined threshold, and determining "yes" if the maximum area difference is greater than the predetermined threshold and determining "no" if the maximum area difference is less than the predetermined threshold.

[0078] In some embodiments, the result of the iteration repeated in process 700 may not be an acceptable (e.g., but not limited to, below a predetermined threshold) maximum area difference, so the loop of process 700 may appear to be infinite. Thus, in one or more embodiments, process 700 includes a counter and can proceed to return an error state if decision block 712 does not return "yes" within a predetermined number of counts (i.e., current counter > predetermined count threshold).

[0079] If process 700 determines "no" at decision block 714, process 700 proceeds to operation 716.

[0080] According to one or more embodiments, process 700 includes obtaining a new ratio value in operation 716 and then returning to operation 704. The new ratio value can be calculated using any suitable technique. As a non-limiting example, the new ratio value can be calculated by increasing or decreasing the current ratio value according to a function or a predetermined step size. As a further non-limiting example, the new ratio value can be obtained from a look-up table (LUT) that associates ratio values with the current ratio value.

[0081] If process 700 determines "yes" in decision block 714, process 700 proceeds to operation 718.

[0082] According to one or more embodiments, process 700 includes, in operation 718, returning a scaled and remapped reference capacitance type sensor structure.

[0083] FIG. 8 is a flowchart depicting a process 800 for finishing the sensor node geometry of each of the mapped reference capacitance type sensor structures according to one or more embodiments.

[0084] Exemplary process 800 depicts a particular sequence of operations, but the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the function of process 800. In other embodiments, the various components of an exemplary device or system implementing process 800 may function substantially simultaneously or in a particular order.

[0085] According to one or more embodiments, the method includes constructing a rough sensor node geometry for the distorted sensor node in operation 802.

[0086] According to one or more embodiments, the method includes smoothing the curve of the cutting line of the rough node geometry in operation 804.

[0087] According to one or more embodiments, the method includes, at operation 806, aligning respective intersection elements of respective sensor node geometries. At the intersection of an X electrode and a Y electrode, typically, one or both of the electrodes include being discontinuous at the intersection. An intersection element is a mass of conductive material arranged to provide a physical and electrical connection across a space created by a discontinuity between portions of an electrode having a discontinuity.

[0088] According to one or more embodiments, the method includes, at operation 808, trimming a gap within a cut line.

[0089] According to one or more embodiments, the method includes, at operation 810, returning a finished sensor node geometry. The sensor node geometry has been smoothed, aligned, and trimmed to refine and complete the outer shape, fit, or function of the sensor node geometry. The amount of action taken to refine and complete the outer shape, fit, or function of the sensor node geometry, and the quality of the result, depends on specific operating conditions.

[0090] Figures 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 13A, and 13B together depict certain non - limiting examples of intermediate graphical representations of a strained capacitive sensor structure according to one or more embodiments.

[0091] Figures 9A and 9B are graphical representations of the constituent geometry of a target capacitive sensor structure identified when mapping the geometry of a reference capacitive sensor structure to the geometry of the target capacitive sensor structure, as described with respect to FIGS. 5 and process 500.

[0092] The contour line is set along the XY axes according to the Cartesian coordinate system (via the line from point (15, 25) to point (25, 0)), and the Cartesian coordinates (0, 0), (0, 25), (15, 25), (25, 0), and (25, 25) are depicted. The height of the target capacitance type sensor structure is the length from (0, 0) to (0, 25). The bottom length (bot_length) is the length from (0, 0) to (25, 0). The X - direction difference between the upper - right corner (coordinate (25, 25)) and point 902 is "X_diff". Since the coordinate of point 902 is (15, 25), X_diff = 10.

[0093] Figures 9A and 9B depict a manner of determining a function that defines the relationship between the respective X - coordinates of the constituent geometries and the X - coordinates of the regular rectangular sub - geometries of the reference capacitance type sensor structure.

[0094] In this example, new coordinates are calculated for the XY coordinate (10, 12.5).

[0095] The parameter "x_diff_over" is calculated using the formula x_diff_over=(x_diff / (y_height / y)). Here, "y_height" is the Y - coordinate of the point using the original XY coordinates, "y" is the height of the point using the constituent geometry, and "x_diff" is the difference between the X - coordinate of the upper - right corner of the constituent geometry and the X - coordinate of the regular rectangular sub - geometry of the reference capacitance type sensor structure that is distorted to reach the constituent geometry of the target capacitance type sensor structure. Substituting the values of these parameters into the formula x_diff_over=(10 / (25 / 12.5)) = 5.

[0096] The coefficient is calculated using the formula coefficient=bot_length / (bot_length - x_diff_over), where "bot_length" is the length of the lower - end side of the constituent geometry of the target capacitance type sensor structure.

[0097] The "coefficient" is a function (also referred to herein as the "transformation function") that defines the relationship between the respective X coordinates of the constituent geometric shapes and the X coordinates of the rectangular sub - geometric shapes. In one or more embodiments, the coefficient is stored (e.g., but not limited to, within a look - up table), and the coefficient is utilized in coordinate transformation to change the coordinates associated with a first geometric shape (a regular geometric shape) to coordinates associated with a second geometric shape (an irregular geometric shape).

[0098] When substituting the values of bot_length and x_diff_over into the formula, the coefficient = 25 / (25 - 5)=1.25.

[0099] The new X coordinate is calculated using the formula: X / coefficient, where "X" is the original X coordinate. Substituting the values of these terms, the new X coordinate=(10 / 1.666)=8. The new XY coordinate is (8,12.5).

[0100] As described herein, when a touch event occurs at sensor point 902 of a sensor generated from a distorted capacitive sensor structure, the sensor nodes of the reference capacitive sensor structure were pushed together in the x - direction to generate the distorted capacitive sensor structure. Thus, a touch controller configured to detect touches with a sensor having a regular geometric shape would output the XY coordinates (25,25). The distorted capacitive sensor structure has the same number of sensor nodes as the reference capacitive sensor structure and is just arranged more compactly.

[0101] By applying the transformation function to the output coordinates, the coordinates are changed to a non - uniform orthogonal coordinate plane. Additionally or alternatively, the XY coordinates associated with the irregular shape may be stored in a look - up table (LUT) and retrieved using the XY coordinates associated with the irregular shape.

[0102] FIG. 10A is a graphical representation of a basic grid according to one or more embodiments. FIG. 10B is a graphical representation of the basic grid of FIG. 10A remapped as described above.

[0103] The remapped basic grid of FIG. 10B depicts the outline of a target capacitance type sensor structure having an irregular geometry. The center point of each cell of the grid corresponds to a sensor node, i.e., the center point of the cell of the grid corresponds to the intersection of the X electrode and the Y electrode. The basic grid and the remapped basic grid include the same number of cells, but the cells of the remapped basic grid are not regular, but rather irregular (e.g., parallelograms and trapezoids).

[0104] In particular, on the remapped grid, there is an area difference of 104% between the minimum area and the maximum area of the cells of the remapped grid. As described above, it is desirable to reduce or eliminate the difference in the area of each sensor node represented by the grid cells.

[0105] FIG. 10C is a graphical representation of a basic touch sensor panel (TSP) pattern. FIG. 10D is a graphical representation of the TSP pattern of FIG. 10C remapped as described above.

[0106] The basic TSP pattern of FIG. 10C corresponds to the basic grid depicted in FIG. 10A, and the remapped TSP pattern of FIG. 10D corresponds to the remapped basic grid of FIG. 10B.

[0107] The positions of the intersections of the X electrodes and the Y electrodes depicted in FIGS. 10C and 10D respectively correspond to the center points of the cells of the grid and the remapped grid depicted in FIGS. 10A and 10B.

[0108] In particular, the number of sensor nodes and intersections in the remapped TSP pattern is the same as the number of sensor nodes and intersections in the basic TSP pattern.

[0109] As described above, it is desirable to reduce or eliminate the difference in the area of each sensor node.

[0110] FIG. 11A is a graphical representation of an exemplary basic grid having a horizontal aspect ratio of 0.7. FIG. 11B is a graphical representation of the remapped FIG. 11A basic grid having a horizontal aspect ratio of 0.7. The basic grid and the remapped basic grid having a horizontal aspect ratio of 0.7, depicted by FIGS. 11A and 11B respectively, can be obtained, as non-limiting examples, by applying a scaling process such as process 700, without limitation, to FIGS. 10A and 10B.

[0111] The vertical aspect ratio is the ratio of the height of the row at the lower end of the cell in FIG. 11A to the height of the row at the lower end of the cell before scaling (i.e., in FIG. 10A). Here, the ratio is 0.7 and the height of the row at the lower end of the cell is equal to 0.7H1. Although the adjustment of the vertical aspect ratio is used in this embodiment, the adjustment of the horizontal aspect ratio can be performed in the same manner. Further, adjustments of both the vertical aspect ratio and the horizontal aspect ratio may be performed.

[0112] FIG. 11C is a graphical representation of an exemplary basic TSP pattern having a horizontal aspect ratio of 0.7. FIG. 11D is a graphical representation of the remapped FIG. 11C exemplary basic TSP pattern having a horizontal aspect ratio of 0.7. The basic TSP pattern and the remapped basic TSP pattern having a horizontal aspect ratio of 0.7, depicted by FIGS. 11C and 11D respectively, can be obtained, as non-limiting examples, by applying a scaling process such as process 700, whiteout restriction, to FIGS. 10C and 10D.

[0113] In the case of the sensor node of the example depicted in FIG. 11D, although the gap is maintained, the node area and geometry of the cross elements are not uniform among the various sensor nodes, which can cause a significant difference in the capacitance values of the respective sensor nodes. Setting the node area and geometry of the sensor nodes of the mapped capacitive sensor structure to be substantially uniform generally reduces the difference in the capacitance values of the respective sensor nodes.

[0114] FIGS. 12A, 12B, and 12C are graphical representations depicting a rough sensor node geometry for a two-layer sensor node structure according to one or more embodiments.

[0115] The geometries depicted by FIGS. 12A, 12B, and 12C can be obtained, by way of non-limiting example, by performing some or all of the operations of process 800.

[0116] FIG. 12A depicts an exemplary basic sensor node geometry for a basic sensor node structure.

[0117] FIG. 12B depicts an exemplary rough sensor node geometry for a first exemplary distorted sensor node structure.

[0118] FIG. 12C depicts an exemplary rough sensor node geometry for a second exemplary distorted sensor node structure different from the first one.

[0119] The exemplary rough sensor node geometry depicted in FIG. 12A was constructed using a four-corner point construction method utilized in computer-aided layout design, but the present disclosure is not limited thereto, and any suitable method, including an edge-centered based construction method utilized in computer-aided layout design, can be utilized without limitation.

[0120] Other rough sensor node geometries may be made, and they are merely specific and non-limiting examples that fit some of the sensor nodes within the remapped TSP pattern depicted in Figure 11B.

[0121] Figures 13A and 13B are graphical representations depicting a strained capacitance sensor structure including sensor nodes having geometries configured as described herein. The sensor nodes of the strained capacitance sensor structure depicted in Figure 13A are constructed using an edge-center construction method, and the sensor nodes of the strained capacitance sensor structure depicted in Figure 13B are constructed using a 4-examiner point construction method.

[0122] The geometries of the intersection elements are not consistently aligned in the strained capacitance sensor structures depicted in Figures 13A and 13B, which can cause significant differences in the capacitance values of the sensor nodes.

[0123] Figures 14A, 14B, and 14C are schematic structures depicting portions of sensor nodes including intersections of electrodes and intersection elements. Figure 14A illustrates a case where the intersection elements of a sensor node are not evenly aligned with respect to the vertices of a segment, as described below.

[0124] As depicted in Figure 14A, the intersection element 1404 is arranged in the direction represented by an arrow 1406 that extends from the center point 1410 of the intersection element 1404 through the midpoint of a line segment that defines a side of the box representing the intersection element 1404. The desired alignment is represented by an alignment line 1402 that extends from the center point 1410 to the vertex 1408 of the segment, representing the direction in which the intersection element 1404 should be aligned. As long as the intersection elements have the same geometry, any similar side of the box representing the intersection element can be selected for orientation.

[0125] As depicted in FIG. 14B, the intersection element 1404 is rotated about an axis (the axis passes through the center point 1410 and is perpendicular to the page) in the direction indicated by arrow 1414 until it is oriented in the direction indicated by arrow 1412, which is a straight line from the center point 1410 passing through the midline of the edge of 1404 to the vertex 1408 of the segment. When the intersection element 1404 is thus oriented, it is oriented to be aligned with the vertex 1408 of the segment. Generally speaking, it is desirable to exhibit a uniform direction with respect to the vertex of the segment or with respect to another similar criterion.

[0126] FIG. 14C depicts several sensor node portions including intersection elements uniformly aligned with the vertices of the segments as described above.

[0127] FIG. 15 is a graphical representation depicting an exemplary distorted capacitive sensor structure pattern finished as described above.

[0128] FIG. 16 is a block diagram depicting a system 1600 that distorts the geometry of a capacitive sensor structure from a first regular geometry to a second irregular geometry according to one or more embodiments.

[0129] System 1600 includes a sensor design application 1602. The sensor design application 1602 includes a geometry distorter 1604, a transducer calculator 1606, a distorted reference structure 1612, and a coordinate converter 1614.

[0130] The sensor design application 1602 may be, by way of non-limiting example, a software application executed on a local computer or a remote computer, or a service provided in a server computer or a cloud computing environment.

[0131] The geometric distorter 1604 may be, by way of non-limiting example, a software module, routine, subroutine, or package of the sensor design application 1602. The geometric distorter 1604 receives a reference structure 1608 and a target structure 1610 that are a capacitive sensor structure, and generates a distorted reference structure 1612 at least in part in response to the reference structure 1608 and the target structure 1610. By way of non-limiting example, the geometric distorter 1604 may generate the distorted reference structure 1612 in response to having performed some or all of the operations described with respect to process 200, process 300, process 400, process 500, process 600, process 700, or process 800, or any combination or sub-combination thereof.

[0132] The transducer calculator 1606 may be, by way of non-limiting example, a software module, routine, subroutine, or package of the sensor design application 1602 or the geometric distorter 1604. The transducer calculator 1606 receives the distorted reference structure 1612 and generates a coordinate transformer 1614. By way of non-limiting example, the transducer calculator 1606 may be the generated coordinate transformer 1614 in response to having performed some or all of the operations described with respect to process 500, or any combination or sub-combination thereof.

[0133] The coordinate transformer 1614 is a set of executable instructions for changing a set of coordinates generated by a touch controller configured to be used with a regularly shaped sensor into coordinates associated with an irregularly shaped sensor. In one or more embodiments, the coordinate transformer 1614 generated by the transducer calculator 1606 may be executable software, firmware, or microcode at least in part by a processing core of a microcontroller or more generally an integrated circuit (IC).

[0134] FIG. 17 is a block diagram depicting a system 1700 for detecting a touch in a capacitively based sensor of irregular shape, according to one or more embodiments.

[0135] System 1700 includes a touch controller 1702 and a capacitively based sensor 1704 of irregular shape. Touch controller 1702 includes firmware 1710 that includes a regularly shaped sensor detector 1706 and a sensor coordinate converter 1708. Regularly shaped sensor detector 1706 is firmware for performing touch measurements and detections in touch controller 1702. Generally speaking, regularly shaped sensor detector 1706 detects a touch in a regularly shaped capacitively based sensor and generates coordinates in a Cartesian coordinate system. Coordinate converter 1708 is firmware for converting coordinates generated by a touch controller (e.g., without limitation, touch controller 1702) configured to generate coordinates in a Cartesian coordinate system, such as regularly shaped sensor detector 1706, into coordinates associated with an irregular geometry, specifically the irregular geometry of irregularly shaped capacitively based sensor 1704. Coordinate converter 1708 may be coordinate converter 1614 generated by calculator 1606 of the converter. As a non-limiting example, coordinate converter 1708 may be a non-limiting example of coordinate converter 1614 generated by calculator 1606 of the converter or generated via process 500.

[0136] FIG. 18 is a flow diagram depicting a process 1800 for detecting a touch event and reporting its location in an irregularly shaped capacitively based sensor, according to one or more embodiments. Some or all of the operations of process 1800 may be performed, by way of non-limiting example, in system 1700.

[0137] Exemplary process 1800 depicts a particular sequence of operations, but the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not significantly affect the function of process 1800. In other embodiments, the various components of the exemplary device or system implementing process 1800 may function substantially simultaneously or in a particular order.

[0138] According to some embodiments, the method includes, in operation 1802, receiving a measurement signal from a capacitive sensor of irregular shape during a capacitance measurement process.

[0139] According to some embodiments, the method includes, in operation 1804, detecting a capacitance change indicative of a touch event in a capacitive sensor of irregular shape.

[0140] According to some embodiments, the method includes, in operation 1806, generating a location identifier associated with the location of the touch event.

[0141] According to some embodiments, the method includes, in operation 1808, changing the location identifier from a first location identifier value associated with a regular geometry to a second location identifier value associated with an irregular geometry. In one or more embodiments, changing the location identifier from the first location identifier value to the second location identifier value may include assigning new coordinate values or generating a further location identifier having the second location identifier value. In one or more embodiments, optionally, the changed location identifier or the further location identifier may be utilized to report the touch event.

[0142] It will be understood by those skilled in the art that the functional elements (e.g., functions, operations, acts, processes, and / or methods) of the embodiments disclosed herein can be implemented in any suitable hardware, software, firmware, or combination thereof. FIG. 19 illustrates a non-limiting example of an implementation manner of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein can be performed by hardware capable of executing the functional elements.

[0143] FIG. 19 is a block diagram of a circuit that can be used to implement various functions, operations, acts, processes, and / or methods disclosed herein in some embodiments. The circuit includes one or more processors 1902 (which may be referred to herein as "processor 1902") operably coupled to one or more data storage devices 1904 (which may be referred to herein as "storage device 1904"). The storage device 1904 includes machine-executable code 1906 stored therein, and the processor 1902 includes logic circuitry 1908. The machine-executable code 1906 includes information describing functional elements that can be implemented (e.g., performed) by the logic circuitry 1908. The logic circuitry 1908 is adapted to implement (e.g., perform) the functional elements described by the machine-executable code 1906. The circuit should be regarded as dedicated hardware for executing the functional elements disclosed herein when executing the functional elements described by the machine-executable code 1906. In some embodiments, the processor 1902 can perform the functional elements described by the machine-executable code 1906 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0144] When implemented by the logic circuitry 1908 of the processor 1902, the machine-executable code 1906 configures the processor 1902 to perform the operations of the embodiments disclosed herein. By way of non-limiting example, the machine-executable code 1906 can configure the processor 1902 to perform some or all of the operations of one or more of processes 200, 300, 400, 500, 600, 700, 800, or 1800.

[0145] Also, by way of non-limiting example, the machine-executable code 1906 can configure the processor 1902 to perform some or all of the features, functions, or operations disclosed herein for one or more of the capacitively coupled sensor structures 100a to be distorted, the capacitively coupled sensor structures 100b that have been distorted, the system 1600, and the system 1700. More specifically, for one or more of the sensor design application 1602, the geometry distorter 1604, the transducer calculator 1606, the touch controller 1702, the firmware 1710, the irregular-shaped capacitive sensor 1704, the regular-shaped sensor detector 1706, and the coordinate converter 1708, the features, functions, or operations disclosed herein.

[0146] Processor 1902 may include a general-purpose processor, a dedicated processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a dedicated computer, but a general-purpose computer executes functional elements corresponding to machine-executable code 1906 (e.g., software code, firmware code, hardware description) related to embodiments of the present disclosure. The general-purpose processor (also sometimes referred to herein as the host processor or simply the host) may be a microprocessor, but alternatively, it should be noted that processor 1902 may include any conventional processor, controller, microcontroller, or state machine. Processor 1902 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other configuration combination.

[0147] In some embodiments, the memory device 1904 may include a volatile data storage device (e.g., but not limited to, random-access memory (RAM)), a non-volatile data storage device (e.g., but not limited to, flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM)). In some embodiments, the processor 1902 and the memory device 1904 may be implemented on a single device (e.g., but not limited to, a semiconductor device product, a system on chip (SOC)). In some embodiments, the processor 1902 and the memory device 1904 may be implemented on separate devices.

[0148] In some embodiments, the machine-executable code 1906 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by the memory device 1904, accessed directly from the processor 1902, and executed by the processor 1902 using at least the logic circuit 1908. Also, as a non-limiting example, the computer-readable instructions may be stored in the memory device 1904, transferred to a memory device (not shown) for execution, and executed by the processor 1902 using at least the logic circuit 1908. As a result, in some embodiments, the logic circuit 1908 includes an electrically configurable logic circuit 1908.

[0149] In some embodiments, the machine-executable code 1906 may describe hardware (e.g., circuitry) implemented in the logic circuit 1908 to perform functional elements. This hardware may be described at any of various levels of abstraction, from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL), such as the IEEE Standard Hardware Description Language, may be used. By way of non-limiting example, Verilog, SystemVerilog (trademark), or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL) may be used.

[0150] HDL descriptions can be converted, as desired, into descriptions at any of a number of other levels of abstraction. By way of non-limiting example, a high-level description can be converted into a logic-level description, such as a Register-Transfer Language (RTL), gate-level (GL) description, layout-level description, or mask-level description. By way of non-limiting example, the micro-operations performed by the hardware logic circuitry of the logic circuit 1908 (e.g., but not limited to, gates, flip-flops, registers) can be described in RTL and then converted by a synthesis tool into a GL description, which can be converted by placement and routing tools into a layout-level description that corresponds to the physical layout of an integrated circuit of programmable logic devices, individual gates or transistor logic, individual hardware components, or combinations thereof. As a result, in some embodiments, the machine-executable code 1906 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0151] In an embodiment where the machine-executable code 1906 includes a hardware description (at any level of abstraction), a system (not shown but including the storage device 1904) may implement the hardware description described by the machine-executable code 1906. As a non-limiting example, the processor 1902 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1908 may be electrically controlled to implement a circuit corresponding to the hardware description in the logic circuit 1908. Also, as a non-limiting example, the logic circuit 1908 may include hardwired logic manufactured by a manufacturing system (not shown but including the storage device 1904) according to the hardware description of the machine-executable code 1906.

[0152] Regardless of whether the machine-executable code 1906 includes computer-readable instructions or a hardware description, the logic circuit 1908 is adapted to perform the functional elements described by the machine-executable code 1906 when implementing the functional elements of the machine-executable code 1906. Note that the hardware description need not directly describe the functional elements, but the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description can perform.

[0153] The terms used in this disclosure, and in particular the terms used in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be construed as "including, but not limited to", the term "having" should be construed as "having at least", the term "includes" should be construed as "includes, but is not limited to", etc.).

[0154] In addition, if a specific number of introduced claim listings are intended, such intention shall be explicitly listed in the claims, and if there is no such listing, then such intention does not exist. For example, for the purpose of illustration, the following appended claims may include the use of introductory phrases "at least one" and "one or more" to introduce claim listings. However, the use of such phrases should not be construed to limit any particular claim that includes an introduced claim listing by an indefinite article such as "one or more" or "at least one" and "a" or "an" in the introductory phrase, even if the same claim includes both (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"), and the same applies to the use of definite articles used to introduce claim listings.

[0155] In addition, even if a specific number of introduced claim listings are explicitly listed, one of ordinary skill in the art will recognize that such listings should be construed to mean at least the number listed (e.g., an explicit listing of "two listings" without other modifiers means at least two listings or two or more listings). Further, when conventions similar to "at least one of A, B, and C" or "one or more of A, B, and C" are used, generally such constructions are intended to include only A, only B, only C, A and B together, A and C together, B and C together, or A, B, and C together. As used herein, "each" means part or whole, and "each and every" means whole.

[0156] Furthermore, any disjunctive word or phrase that presents two or more alternative terms should be understood to contemplate the possibility of including one of the terms, any of the terms, or both terms, regardless of whether in the specification, the claims, or the drawings. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0157] Further non-limiting examples include the following.

[0158] Example 1: A method comprising changing the geometry of a capacitive sensor structure from a first geometry to a second geometry different from the first geometry, and obtaining executable instructions for converting a touch event position identifier from a first position identifier associated with the first geometry to a second position identifier associated with the second geometry.

[0159] Example 2: The method according to Example 1, wherein the first geometry is a regular geometry and the second geometry is an irregular geometry.

[0160] Example 3: The step of changing the geometry of the capacitive sensor structure from the first geometry to the second geometry comprises obtaining a reference capacitive sensor structure and a target capacitive sensor structure, wherein the geometry of the reference capacitive sensor structure is the first geometry and the geometry of the target capacitive sensor structure is the second geometry; mapping the geometry of the reference capacitive sensor structure to the geometry of the target capacitive sensor structure; and setting the respective node areas of the mapped reference capacitive sensor structure to be uniform, the method according to Example 1 or 2.

[0161] Example 4: The step of mapping the geometry of the reference structure to the geometry of the target structure is In the geometry of the target capacitance type sensor structure, a step of identifying a constituent geometry that matches a predetermined geometry, a step of dividing the geometry of the reference capacitance type sensor structure into rectangular sub-geometries, each of the rectangular sub-geometries including each of the identified ones of the constituent geometries of the target capacitance type sensor structure, a step of calculating, for each Y coordinate, each X coordinate of the identified constituent geometry, a step of determining a function that describes the relationship between the X coordinate of the constituent geometry and the X coordinate of the rectangular sub-geometry, A step of returning the X coordinate and Y coordinate of the second geometry and the function, the method according to any one of Examples 1 to 3.

[0162] Example 5: The step of setting each node area of the mapped reference structure to be uniform includes a step of obtaining a scaling factor and a step of scaling the dimensions of each node area of the mapped reference capacitance type sensor structure according to the scaling factor, the method according to any one of Examples 1 to 4.

[0163] Example 6: The method according to any one of Examples 1 to 5, including a step of finishing each sensor node geometry of the mapped reference capacitance type sensor structure.

[0164] Example 7: The finishing step includes a step of constructing a rough sensor node geometry, a step of smoothing the curve of the cutting line of the rough node geometry, a step of aligning the details of each intersection of each sensor node geometry, a step of trimming the gap within the cutting line, and a step of returning the finished sensor node geometry, the method according to any one of Examples 1 to 6.

[0165] Example 8: The scale of the reference coordinate line of the first geometry is different from the scale of the reference coordinate line of the second geometry, the method according to any one of Examples 1 to 7.

[0166] Example 9: A method according to any one of Examples 1 to 8, comprising: keeping the number of sensor nodes of the capacitive sensor structure the same between the first geometric shape and the second geometric shape; and keeping the respective node areas of one or more sensor nodes of the capacitive sensor structure substantially uniform.

[0167] Example 10: A method according to any one of Examples 1 to 9, wherein the step of changing the geometry of the capacitive sensor structure includes one or more of the steps of stretching, narrowing, or deforming the geometry of the capacitive sensor structure or the respective geometries of one or more of its sensor nodes.

[0168] Example 11: A method according to any one of Examples 1 to 10, comprising defining a second geometry according to the geometry of the target touch surface.

[0169] Example 12: An apparatus comprising a memory device and at least one processor for executing machine-executable instructions stored in the memory device, the machine-executable instructions causing the at least one processor to change the geometry of a capacitive sensor structure from a first geometry to a second geometry different from the first geometry and to convert a position identifier of a touch event from a first position identifier associated with the first geometry to a second position identifier associated with the second geometry.

[0170] Example 13: A method comprising receiving a measurement signal from a capacitive sensor of irregular shape during a capacitance measurement process, detecting a capacitance change indicative of a touch event in the capacitive sensor of irregular shape, generating a position identifier associated with the position of the touch event, and changing the position identifier from a first position identifier value to a second position identifier value, wherein the first position identifier value is associated with a regular geometry and the second position identifier value is associated with an irregular geometry.

[0171] Example 14: The method according to Example 13, wherein the step of changing the position identifier from the first position identifier value to the second position identifier value includes generating a further position identifier having a second position identifier value associated with an irregular geometric shape.

[0172] Example 15: The method according to Example 13 or 14, including the step of calculating a second position identifier value by applying a conversion function to the first position identifier value.

[0173] Example 16: The method according to any one of Examples 13 to 15, wherein the first position identifier value and the second position identifier value are XY coordinates.

[0174] Example 17: The method according to any one of Examples 13 to 16, wherein the capacitive sensor having an irregular shape is a non-rectangular capacitive sensor.

[0175] Example 18: The method according to any one of Examples 13 to 17, wherein the sensor nodes of the capacitive sensor having an irregular shape exhibit a substantially uniform sensor area.

[0176] Example 19: The method according to any one of Examples 13 to 18, wherein the sensor nodes of the capacitive sensor having an irregular shape exhibit a substantially non-uniform geometry.

[0177] Example 20: The method according to any one of Examples 13 to 19, wherein the spacing between the sensor nodes of the capacitive sensor having an irregular shape is non-uniform.

[0178] Example 21: The method according to any one of Examples 13 to 20, wherein the number of sensor nodes in each row of the capacitive sensor having an irregular shape is uniform.

[0179] Example 22: The sensor nodes of a capacitive sensor with an irregular shape exhibit a substantially uniform sensor area, the sensor nodes of a capacitive sensor with an irregular shape exhibit a substantially non-uniform geometric shape, the spacing between the sensor nodes of a capacitive sensor with an irregular shape is non-uniform, and the number of sensor nodes in each row of a capacitive sensor with an irregular shape is uniform. The method according to any one of Examples 13 to 21.

[0180] Example 23: An apparatus comprising a memory and at least one processor for executing instructions stored in the memory, the instructions causing the at least one processor to receive a measurement signal from a capacitive sensor with an irregular shape during a capacitance measurement process, detect a capacitance change indicating a touch event in the capacitive sensor with an irregular shape, generate a position identifier associated with the position of the touch event, and change the position identifier from a first position identifier value associated with a regular geometry to a second position identifier value associated with an irregular geometry.

[0181] Example 24: The apparatus according to Example 23, wherein the instructions for causing the at least one processor to change the position identifier from the first position identifier value to the second position identifier value include instructions for generating a further position identifier having the second position identifier value associated with the irregular geometry.

[0182] Example 25: The apparatus according to Example 23 or 24, wherein the instructions for causing the at least one processor to change the position identifier from the first position identifier value to the second position identifier value include instructions for calculating the second position identifier value by applying a conversion function to the first position identifier value.

[0183] Example 26: A system comprising an irregularly shaped capacitance-type sensor and a touch controller associated with the irregularly shaped capacitance-type sensor, the touch controller including first firmware that enables the touch controller to generate a first position identifier for a touch event associated with a regularly shaped capacitance-type sensor, and second firmware that enables the touch controller to generate a second position identifier for a touch event associated with the irregularly shaped capacitance-type sensor based at least in part on the first position identifier.

[0184] Example 27: The system according to Example 26, wherein the surface of the irregularly shaped capacitance-type sensor has an irregular geometry.

[0185] Example 28: The system according to Example 26 or 27, wherein the irregular geometry of the irregularly shaped capacitance-type sensor is a non-rectangular geometry.

[0186] Example 29: The system according to any one of Examples 26 to 28, wherein the first position identifier value and the second position identifier value are XY coordinates.

[0187] Example 30: The system according to any one of Examples 26 to 29, wherein the irregularly shaped capacitance-type sensor is a non-rectangular capacitance-type sensor.

[0188] Example 31: The system according to any one of Examples 26 to 30, wherein the sensor nodes of the irregularly shaped capacitance-type sensor exhibit a substantially uniform sensor area.

[0189] Example 32: The system according to any one of Examples 26 to 31, wherein the sensor nodes of the irregularly shaped capacitance-type sensor exhibit a substantially non-uniform geometry.

[0190] Example 33: The system according to any one of Examples 26 to 32, wherein the spacing between the sensor nodes of the irregularly shaped capacitance-type sensor is non-uniform.

[0191] Example 34: A system according to any of Examples 26 - 33, wherein the number of sensor nodes in each row of the irregularly shaped capacitance type sensor is uniform.

[0192] Example 35: A method according to any of Examples 26 - 34, wherein the sensor nodes of the irregularly shaped capacitance type sensor exhibit a substantially uniform sensor area, the sensor nodes of the irregularly shaped capacitance type sensor exhibit a substantially non-uniform geometry, the spacing between the sensor nodes of the irregularly shaped capacitance type sensor is non-uniform, and the number of sensor nodes in each row of the irregularly shaped capacitance type sensor is uniform.

[0193] Although the present disclosure has been described herein with respect to certain exemplary embodiments, those skilled in the art will recognize and understand that the invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed hereinafter together with their legal equivalents. Additionally, the features of one embodiment can be combined with the features of another disclosed embodiment as contemplated by the inventors, and still be encompassed within the scope of the present disclosure.

Claims

1. A method comprising: changing a geometry of a capacitive sensor structure from a first geometry to a second geometry different from the first geometry; and obtaining executable instructions for converting a touch event position identifier from a first position identifier associated with the first geometry to a second position identifier associated with the second geometry.

2. The method of claim 1, wherein the first geometry is a regular geometry and the second geometry is an irregular geometry.

3. The step of changing the geometry of the capacitive sensor structure from the first geometry to the second geometry comprises: obtaining a reference capacitive sensor structure and a target capacitive sensor structure, wherein the geometry of the reference capacitive sensor structure is the first geometry and the geometry of the target capacitive sensor structure is the second geometry; mapping the geometry of the reference capacitive sensor structure to the geometry of the target capacitive sensor structure; and setting respective node areas of the mapped reference capacitive sensor structure to be uniform.

4. The step of mapping the geometry of the reference structure to the geometry of the target structure comprises: identifying a constituent geometry that matches a predetermined geometry in the geometry of the target capacitive sensor structure; dividing the geometry of the reference capacitive sensor structure into sub-geometries that are rectangular, each of the rectangular sub-geometries including a respective one of the identified constituent geometries of the target capacitive sensor structure; calculating respective X coordinates of the identified constituent geometries for respective Y coordinates; determining a function that describes a relationship between the X coordinates of the constituent geometries and the X coordinates of the rectangular sub-geometries; and returning the X and Y coordinates of the second geometry and the function.

5. The step of setting each node area of the mapped reference structure to be uniform includes: obtaining a scaling factor; and scaling the dimensions of each node area of the mapped reference capacitance type sensor structure according to the scaling factor. The method according to claim 3 includes these steps. **Claim 6** The method according to claim 3 includes the step of finishing the geometric shape of each sensor node of the mapped reference capacitance type sensor structure. **Claim 7** The step of finishing includes: constructing a rough sensor node geometry; smoothing the curve of the cutting line of the rough node geometry; aligning the details of each intersection of each sensor node geometry; trimming the gaps within the cutting line; and returning the finished sensor node geometry. The method according to claim 6 includes these steps. **Claim 8** The scale of the reference coordinate line of the first geometry is different from the scale of the reference coordinate line of the second geometry. The method according to claim 1. **Claim 9** The method according to claim 1 includes the steps of keeping the number of sensor nodes of the capacitance type sensor structure the same between the first geometry and the second geometry, and substantially keeping the node area of each of the one or more sensor nodes of the capacitance type sensor structure uniform. **Claim 10** The step of changing the geometry of the capacitance type sensor structure includes one or more of the steps of stretching, narrowing, or distorting the geometry of the capacitance type sensor structure or the geometry of each of one or more of its sensor nodes. The method according to claim 1. **Claim 11** The method according to claim 1 includes the step of defining the second geometry according to the geometry of the target touch surface. **Claim 12** An apparatus comprising: a memory device; and at least one processor for executing machine-executable instructions stored in the memory device, the machine-executable instructions causing the at least one processor to change the geometry of a capacitance type sensor structure from a first geometry to a second geometry different from the first geometry, and An apparatus for obtaining executable instructions for converting a touch event position identifier from a first position identifier associated with the first geometric shape to a second position identifier associated with the second geometric shape. **Claim 13** A method comprising: receiving a measurement signal from a capacitive sensor of an irregular shape during a capacitance measurement process; detecting a capacitance change indicating a touch event in the capacitive sensor of the irregular shape; generating a position identifier associated with the position of the touch event; changing the position identifier from a first position identifier value associated with a regular geometric shape to a second position identifier value associated with an irregular geometric shape. **Claim 14** The step of changing the position identifier from the first position identifier value to the second position identifier value includes generating a further position identifier having the second position identifier value associated with the irregular geometric shape, according to the method of claim 13. **Claim 15** The method of claim 13, including calculating the second position identifier value by applying a conversion function to the first position identifier value. **Claim 16** The method of claim 13, wherein the first position identifier value and the second position identifier value are XY coordinates. **Claim 17** The method of claim 13, wherein the capacitive sensor of the irregular shape is a non-rectangular capacitive sensor. **Claim 18** The method of claim 13, wherein the sensor nodes of the capacitive sensor of the irregular shape exhibit a substantially uniform sensor area. **Claim 19** The method of claim 13, wherein the sensor nodes of the capacitive sensor of the irregular shape exhibit a substantially non-uniform geometry. **Claim 20** The method of claim 13, wherein the spacing between the sensor nodes of the capacitive sensor of the irregular shape is non-uniform. **Claim 21** The method of claim 13, wherein the number of sensor nodes in each row of the capacitive sensor of the irregular shape is uniform. **Claim 22** The sensor nodes of the capacitive sensor of the irregular shape exhibit a substantially uniform sensor area, The sensor nodes of the capacitive sensor of the irregular shape exhibit a substantially non-uniform geometry, The spacing between sensor nodes of the capacitive sensor with an irregular shape is non-uniform, The method according to claim 13, wherein the number of sensor nodes in each row of the capacitive sensor with an irregular shape is uniform.

23. An apparatus, a memory, at least one processor for executing instructions stored in the memory, the instructions causing the at least one processor to, receive a measurement signal from a capacitive sensor with an irregular shape during a capacitance measurement process, detect a capacitance change indicating a touch event in the capacitive sensor with an irregular shape, generate a position identifier associated with the position of the touch event, change the position identifier from a first position identifier value associated with a regular geometric shape to a second position identifier value associated with an irregular geometric shape, the apparatus.

24. The instructions for causing the at least one processor to change the position identifier from a first position identifier value to a second position identifier value, The apparatus according to claim 23, comprising instructions for generating a further position identifier having the second position identifier value associated with the irregular geometric shape.

25. The instructions for causing the at least one processor to change the position identifier from a first position identifier value to a second position identifier value, The apparatus according to claim 23, comprising instructions for calculating the second position identifier value by applying a conversion function to the first position identifier value.

26. A system, a capacitive sensor with an irregular shape, a touch controller associated with the capacitive sensor with an irregular shape, the touch controller comprising a first firmware that enables the touch controller to generate a first position identifier of a touch event associated with a capacitive sensor with a regular shape, a second firmware that enables the touch controller to generate a second position identifier of the touch event associated with the capacitive sensor with an irregular shape based at least in part on the first position identifier, the system.

27. The surface of the capacitive sensor with an irregular shape has an irregular geometric shape, the system according to claim 26.

28. The system according to claim 26, wherein the irregular geometric shape of the capacitive sensor with an irregular shape is a non-rectangular geometric shape.

29. The system according to claim 26, wherein the first position identifier value and the second position identifier value are XY coordinates.

30. The system according to claim 26, wherein the capacitive sensor with an irregular shape is a non-rectangular capacitive sensor.

31. The system according to claim 26, wherein the sensor nodes of the capacitive sensor with an irregular shape exhibit a substantially uniform sensor area.

32. The system according to claim 26, wherein the sensor nodes of the capacitive sensor with an irregular shape exhibit a substantially non-uniform geometric shape.

33. The system according to claim 26, wherein the spacing between the sensor nodes of the capacitive sensor with an irregular shape is non-uniform.

34. The system according to claim 26, wherein the number of sensor nodes in each row of the capacitive sensor with an irregular shape is uniform.

35. The sensor nodes of the capacitive sensor with an irregular shape exhibit a substantially uniform sensor area, the sensor nodes of the capacitive sensor with an irregular shape exhibit a substantially non-uniform geometric shape, the spacing between the sensor nodes of the capacitive sensor with an irregular shape is non-uniform, and the number of sensor nodes in each row of the capacitive sensor with an irregular shape is uniform, the method according to claim 26.

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