Wiring Substrate, Manufacturing Method, Backplane, and Display Device

Abstract

A wiring board (100), the wiring board (100) includes a base (120), a conductive layer (130), and a protective layer (140). The conductive layer (130) is located on one side of the base (120), the conductive layer (130) includes a plurality of pad groups (1300), and one pad group (1300) includes a plurality of conductive pads (131). The protective layer (140) is located on the side of the conductive layer (130) away from the base (120), the protective layer (140) includes a plurality of openings, and the portion of the conductive layer (130) exposed in the opening (141) is the conductive pad (131). The maximum size of the conductive pad (131) in the direction parallel to the base (120) is 30 times or less of the minimum distance between the edge of the conductive pad (131) and the edge of the conductive layer (130).

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a wiring substrate, a manufacturing method, a backplane, and a display device.

Background Art

[0002] Mini LED (Mini Organic Light-Emitting Diode) / Micro LED (Micro Organic Light-Emitting Diode) display devices have advantages such as high brightness, a clear display screen, and low power consumption, and have good application prospects.

Summary of the Invention

Means for Solving the Problems

[0003] In one aspect, a wiring substrate is provided. The wiring substrate includes a base, at least one a conductive layer, and a protective layer. The at least one conductive layer is located on one side of the base, one the conductive layer includes a plurality of pad groups, and one pad group includes a plurality of conductive pads. The protective layer is located on the side of the conductive layer away from the base, the protective layer includes a plurality of openings, and the portion of the conductive layer exposed through the openings is the conductive pad. The maximum size of the conductive pad in the direction parallel to the base is 1.5 times or more the minimum distance between the edge of the conductive pad and the edge of the conductive layer, and 30 times or less the minimum distance between the edge of the conductive pad and the edge of the conductive layer. at least one In some embodiments, the maximum size of the conductive pad in the direction parallel to the base is 0.5 to 5 times the distance between the conductive pad and an adjacent conductive pad.

[0004] In some embodiments, the maximum size of the conductive pad in the direction parallel to the base is 105 μm or more and 350 μm or less.

[0005] ​

[0006] In some embodiments, the area of the conductive pad is 5000 μm 2 or more and 55000 μm 2 or less.

[0007] In some embodiments, in the same group of pads, the distance between two adjacent conductive pads is 70 μm or more and 214 μm or less.

[0008] In some embodiments, the above at least one conductive layer includes a plurality of conductive lines, the portion of the conductive line exposed at the opening is the conductive pad, the conductive line includes a main surface and side surfaces connected to the main surface, the main surface is a surface away from the base of the conductive line, and the included angle between the main surface and the side surfaces is 105° or more and 145° or less.

[0009] In some embodiments, the above at least one conductive layer includes a plurality of conductive lines, the portion of the conductive line exposed at the opening is the conductive pad, the conductive line includes a main surface and a plurality of side surfaces connected to the main surface, the main surface is a surface away from the base of the conductive line, at least two of the plurality of side surfaces with a relatively short distance from the conductive pad of the conductive line are the first side surfaces, and the two first side surfaces are connected by a curved surface.

[0010] In some embodiments, the orthographic projection of the curved surface on the base is a first fillet, and the radius of the first fillet is 20 μm or more and 30 μm or less.

[0011] In some embodiments, the wiring substrate includes a plurality of device regions. The plurality of groups of pads includes a plurality of first groups of pads and one second group of pads located in any one of the device regions. The first group of pads includes a first-pole pad and a second-pole pad arranged at intervals. The second group of pads includes at least a power supply pad, a ground pad, an address pad, and an output pad arranged at intervals. The wiring substrate includes a source voltage line and a drive voltage linecomprising No. In the same device region, the power pad is electrically connected to the source voltage line, the address pad is electrically connected to an output pad in another device region, and in the plurality of first pad groups, the first pole pad in the first first pad group is electrically connected to the drive voltage line, the second pole pad in the previous first pad group is electrically connected to the first pole pad in the next first pad group, and the second pole pad in the last first pad group is electrically connected to the output pad. At least one of the maximum sizes in the direction parallel to the base of at least the first pole pad in the first first pad group, the power pad, and the ground pad is 30 times or less the minimum distance between the edge of the pad and the edge of the conductive layer.

[0012] In some embodiments, the wiring substrate includes a plurality of sub device regions and one control region. The plurality of pad groups includes a plurality of first pad groups located in any one sub device region, and the first pad groups include first pole pads and second pole pads arranged at intervals. The plurality of pad groups further includes a second pad group located in the control region, and the second pad group includes a power pad, a ground pad, an address pad, and an output pad. The wiring substrate includes a source voltage line and a drive voltage line comprising See, the power pad is electrically connected to the source voltage line. In the same sub device region, among the plurality of first pad groups, the first pole pad in the first first pad group is electrically connected to the drive voltage line, the second pole pad in the previous first pad group is electrically connected to the first pole pad in the next first pad group, and the second pole pad in the last first pad group is electrically connected to the output pad. The maximum size in the direction parallel to the base of at least the first pole pad in the first first pad group is 30 times or less the minimum distance between the edge of the first pole pad and the edge of the conductive layer.

[0013] In some embodiments, the above at least oneThe number of conductive layers is two. The first conductive layer is located on one side of the base, a part of the conductive line is located in the first conductive layer, the second conductive layer is located on the side away from the base of the first conductive layer, and the other part of the conductive line is located in the second conductive layer. One conductive line in the first conductive layer and at least one conductive line located in the second conductive layer are connected via a via hole, and the portion of the conductive line located in the second conductive layer and exposed at the opening is the conductive pad.

[0014] In some embodiments, the wiring substrate further includes an oxidation protection layer and a conductive functional layer. The oxidation protection layer covers the side of the conductive pad away from the base. The conductive functional layer covers the side of the oxidation protection layer away from the base.

[0015] In another aspect, a backplane is provided. The backplane includes a plurality of functional elements, at least one driving chip, and the wiring substrate described in any of the above embodiments. The plurality of pad groups in the wiring substrate include a first pad group and a second pad group. The first pad group is connected to the functional element, and the second pad group is connected to the driving chip.

[0016] In yet another aspect, a display device is provided. The display device includes a backlight module and a liquid crystal display panel. The backlight module is the backplane provided according to some of the above embodiments, and the functional element includes a light emitting diode. The liquid crystal display panel is located on the light emitting side of the backlight module.

[0017] In yet another aspect, a display device is provided. The display device includes a display panel, and the display panel includes the backplane provided according to some of the above embodiments.

[0018] In yet another aspect, a method for manufacturing a wiring board is provided. The method for manufacturing the wiring board includes a step of forming a conductive layer on a base, wherein the conductive layer includes a plurality of pad groups, and one pad group includes a plurality of conductive pads; and a step of forming a protective layer on a side of the conductive layer away from the base and forming an opening in the protective layer, wherein a portion of the conductive layer exposed in the opening is the conductive pad, and a maximum size of the conductive pad in a direction parallel to the base is not more than 30 times a minimum distance between an edge of the conductive pad and an edge of the conductive layer.

[0019] In some embodiments, the step of forming a conductive layer on the base includes depositing a conductive material on the base to form an initial conductive layer; forming a photoresist layer on a side of the initial conductive layer away from the base; baking the photoresist layer at a predetermined temperature, wherein the predetermined temperature is 125 °C or higher and 135 °C or lower; exposing and developing the photoresist layer to pattern the photoresist layer; and etching the initial conductive layer based on the patterned photoresist layer to form the conductive layer.

Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the present disclosure, the following briefly describes the drawings necessary for describing some embodiments of the present disclosure. The drawings in the following description are only the drawings of some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings. Furthermore, the drawings in the following description can be regarded as schematic drawings and do not limit the actual dimensions of the products according to the embodiments of the present disclosure, the actual processes of the methods, the actual sequences of the signals, etc.

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Embodiments for Carrying Out the Invention

[0052] The following will clearly and completely describe the technical solutions of some embodiments of the present disclosure with reference to the drawings. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art shall fall within the protection scope of the present disclosure.

[0053] In this specification and the claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", should be construed in an open, inclusive sense, i.e., "including but not limited to", unless the context requires otherwise. In the description of this specification, terms such as "some embodiments", "example", or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic related to the embodiment or the example is included in at least one embodiment or example of the present disclosure. The schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0054] Hereinafter, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features shown. Therefore, the features defined by "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the embodiments of the present disclosure, unless otherwise specified, "a plurality" means two or more.

[0055] When describing some embodiments, the terms "connection" and its derived expressions may be used. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0056] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include combinations of A only, B only, C only, A and B, A and C, B and C, and A, B, and C.

[0057] "A and / or B" includes three combinations: only A, only B, and the combination of A and B.

[0058] As used herein, the use of "arranged as" means open and inclusive language and does not exclude an apparatus that is applied or arranged to perform additional tasks or steps.

[0059] Also, the use of "based on" means open and inclusive in that a process, step, calculation, or other operation performed "based on" one or more recited conditions or values may actually be based on additional conditions or may exceed the recited values.

[0060] As used herein, "about" or "approximately" includes the recited value and the average value within an acceptable deviation range of the recited value, where the acceptable deviation range is determined considering the errors associated with the measurements being considered by one of ordinary skill in the art and the measurements of the particular quantity (i.e., the limitations of the measurement system).

[0061] As used herein, "parallel", "equal" include the recited situation and situations approximating the recited situation, where the range of the approximating situation is within an acceptable deviation range, and where the acceptable deviation range is determined considering the errors associated with the measurements being considered by one of ordinary skill in the art and the measurements of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes being absolutely parallel and approximately parallel, where the acceptable deviation range for being approximately parallel is, for example, a deviation within 5°, and "equal" includes being absolutely equal and approximately equal, where the acceptable deviation range for being approximately equal is, for example, a difference between the two equal ones that can be 5% or less of either.

[0062] When a layer or element is referred to as being on another layer or substrate, it is understood that the layer or element may be directly located on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0063] In this specification, exemplary embodiments are described with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are enlarged for clarity. Thus, variations in shape with respect to the drawings, for example due to manufacturing techniques and / or tolerances, can be assumed. Accordingly, exemplary embodiments should not be construed as being limited to the shapes of the regions illustrated herein, but should be interpreted as including shape deviations resulting from manufacturing and the like. For example, an etching region shown as rectangular typically has curved features. Thus, the regions shown in the drawings are essentially exemplary, and their shapes are not intended to represent the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0064] FIG. 1A is a structural diagram of backplane 1000 according to some embodiments.

[0065] As shown in FIG. 1A, some embodiments of the present disclosure provide a backplane 1000 including a wiring substrate 100, a plurality of functional elements 200, and at least one driving chip 300. All of the plurality of functional elements 200 and at least one driving chip 300 are electrically connected to the wiring substrate 100, and a plurality of conductive lines 110 are disposed on the wiring substrate 100, and between the plurality of functional elements 200 and between the functional components 200 and the driving chip 300 can all be electrically connected via the conductive lines 110.

[0066] In addition to the functional elements 200 and the driving chip 300, the backplane 1000 can further include other electronic elements (not shown) such as sensor chips, capacitors, resistors, inductors, etc.

[0067] As shown in FIG. 1A, in some examples, the plurality of conductive lines 110 in the wiring substrate 100 include a source address line 111, a source voltage line 112, a driving voltage line 113, and a common voltage line 114.

[0068] FIG. 1B is a structural diagram of a driving chip 300 according to some embodiments.

[0069] As shown in FIG. 1B, in some examples, the driving chip 300 includes a power pin Pwr, a ground pin Gnd, an address pin Di, and an output pin Ot.

[0070] As further shown in FIG. 1A, the source address line 111 is connected to the address pin Di of the driving chip 300. The source address line 111 is configured to transmit a first input signal, and the first input signal includes an address signal for gating the driving chip 300 of the corresponding address. For example, the addresses of different driving chips 300 may be the same or different. The first input signal may be a digital signal including address information with a bit width of 8 bits, and by analyzing the first input signal, the address of the transmission target can be obtained.

[0071] The source voltage line 112 is connected to the power pin Pwr of the driving chip 300. The source voltage line 112 is configured to transmit a second input signal, and the second input signal includes a power signal and / or a carrier communication signal for supplying power to the driving chip 300 and / or transmitting communication data. For example, the second input signal is a power signal and a carrier communication signal. The second input signal not only supplies power to the driving chip 300 but also transmits communication data to the driving chip 300, and the communication data can be used to control the operating state of the corresponding functional element 200.

[0072] The driving voltage line 113 is connected to the output pin Ot of the driving chip 300. A plurality of functional elements 200 are arranged in a circuit where the driving voltage line 113 is connected to the output pin Ot of the driving chip 300. The driving voltage line 113 is configured to transmit a driving voltage and provide an operating voltage to the functional element 200. The output pin Ot of the driving chip 300 can provide a driving signal and / or a relay signal. For example, the driving signal is used to control the operating state of the functional element 200, and the relay signal is used to provide the first input signal to another driving chip 300.

[0073] The common voltage line 114 is connected to the ground pin Gnd of the drive chip 300. The common voltage line 114 is configured to receive and transmit a common voltage signal including a ground signal.

[0074] As shown in FIG. 1A, in some examples, backplane 1000 includes a plurality of device regions AA, and the device region AA includes a control region A2 and at least one sub-device region A1 connected to the control region A2. The functional elements are arranged in the sub-device region A1, the drive chip 300 is arranged in the control region A2, a plurality of functional elements 200 and one drive chip 300 are arranged in one device region AA, and one drive chip 300 is used to control the operating states of the plurality of functional elements 200.

[0075] FIG. 1C is a structural diagram of another backplane 1000 according to some embodiments.

[0076] As shown in FIG. 1C, in some examples, the plurality of device regions AA in the backplane 1000 are arranged in a plurality of rows and columns. Among two device regions AA adjacent in the column direction X, the address pin Di of the drive chip 300 in one device region AA is electrically connected to the output pin Ot of the drive chip 300 in the other device region AA. As shown in FIG. 1C, the direction indicated by the arrow X is the column direction X.

[0077] In some examples, a plurality of functional branches are arranged in one device area AA, each functional branch includes a plurality of functionally-elements 200 connected in series, and the plurality of functional branches are arranged in parallel. In some other examples, one functional branch is arranged in one device area AA, that is, at this time, all the functionally-elements 200 in one device area AA are arranged in series. Exemplarily, the number of functionally-elements 200 in one functional branch may be 4, 6, 9, etc., or may be more than that, and is not particularly limited herein. The plurality of functionally-elements 200 arranged in series in one device area AA, or the plurality of functionally-elements 200 arranged in series in one functional branch are electrically connected between the drive voltage line 113 and the output pin Ot.

[0078] In some other examples, a plurality of functional branches connected in parallel with each other may be arranged in one device area AA. Each functional branch includes at least one functionally-element 200. When a plurality of functionally-elements 200 are included in the functional branch, the functionally-elements 200 belonging to the same functional branch are connected in series. There is no limit to the number of functionally-elements in each functional branch, and both ends of each functional branch are electrically connected to the drive voltage line 113 and the output pin Ot, respectively.

[0079] FIG. 1D is a bottom view of the functionally-element 200 according to some embodiments.

[0080] As shown in FIG. 1D, in some examples, the functionally-element 200 has two pins, which are the first pin P and the second pin N, respectively.

[0081] Furthermore, as shown in FIG. 1C, in one functional branch, the first pin P in the first functional element 200A is electrically connected to the drive voltage line 113, the second pin N in the previous functional element 200 is electrically connected to the first pin P in the next functional element 200, and the second pin N in the last functional element 200 is electrically connected to the output pin Ot. The previous functional element 200 and the next functional element 200 are two adjacent functional elements 200, and the length of the conductive line 110 between the previous functional element 200 and the drive voltage line 113 is greater than the length of the conductive line 110 between the next functional element 200 and the drive voltage line 113.

[0082] Exemplarily, as shown in FIG. 1C, the same device area AA includes nine functional elements 200, and the nine functional elements 200 are, in sequence, the first functional element 200A, …, the eighth functional element 200H, and the ninth functional element 200I.

[0083] It is understood that among the eighth functional element 200H and the ninth functional element 200I, the eighth functional element 200H is the previous functional element 200 and the ninth functional element 200I is the next functional element 200. The second pin N in the eighth functional element 200H is electrically connected to the first pin P in the ninth functional element 200I, and the second pin N in the ninth functional element 200I is electrically connected to the output pin Ot in the drive chip 300.

[0084] Hereinafter, the wiring board 100 will be described.

[0085] FIG. 2A is a cross-sectional view of a wiring board 100 according to some embodiments.

[0086] As shown in FIG. 2A, some embodiments of the present disclosure provide a wiring board 100 including a base 120, a conductive layer 130, and a protective layer 140. The conductive layer 130 is located on one side of the base 120, and the protective layer 140 is located on the side of the conductive layer 130 away from the base 120. The protective layer 140 includes a plurality of openings 141, and the portion of the conductive layer 130 exposed in the openings 141 is the conductive pad 131.

[0087] Exemplarily, the base 120 is a flexible base, that is, the wiring board 100 and the backplane 1000 can be bent. Of course, the base 120 may also be a rigid base. Exemplarily, the material of the base 120 can include any one of plastic, FR-4 grade material, resin, glass, quartz, polyimide, or polymethyl methacrylate (English full name: Polymethyl Methacrylate, English abbreviation PMMA).

[0088] Exemplarily, the protective layer 140 may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The protective layer 140 can protect the conductive layer 130.

[0089] Exemplarily, one conductive layer 130 can include a plurality of material layers. For example, the conductive layer 130 includes a copper (Cu) layer and two molybdenum niobium (MoNb) layers, and the two molybdenum niobium layers are respectively arranged on two opposite surfaces of the copper layer. It is understood that one surface of the copper layer faces the base 120 and the other surface is away from the base 120. Also, the conductive layer 130 may be composed of only copper.

[0090] The conductive layer 130 includes a plurality of conductive lines 110, and the portion exposed at the opening 141 of the conductive line 110 is the conductive pad 131. It should be noted that the opening 141 can be formed by etching the protective layer. In some cases, when the surface layer of the region exposed by the opening 141 of the conductive layer 130 is a molybdenum niobium layer, in order to expose the copper layer and ensure the solderability of the subsequent conductive pad 131, it is necessary to further etch the molybdenum niobium layer.

[0091] As shown in FIG. 2A, in some embodiments, the wiring substrate includes two conductive layers 130. The first conductive layer 130A is located on one side of the base 120, and a part of the conductive line 110 is located within the first conductive layer 130A. For convenience of description, the conductive line 110 located in the first conductive layer 130A can be referred to as a signal line. Exemplarily, the signal lines located in the first conductive layer 130A include the source address line 111, the source voltage line 112, the driving voltage line 113, and the common voltage line 114 described above.

[0092] The second conductive layer 130B is located on the side of the base 120 away from the first conductive layer 130A, and the other part of the conductive line 110 is located within the second conductive layer 130B. For convenience of description, the other part of the conductive line 110 located in the second conductive layer 130B is defined as a transfer line 115.

[0093] One conductive line 110 in the first conductive layer 130A and at least one conductive line 110 located in the second conductive layer 130B are V1 connected via a via hole. Exemplarily, each signal line among the source address line 111, the source voltage line 112, the driving voltage line 113, and the common voltage line 114 is connected to at least one transfer line 115 via a via hole.

[0094] The portion of the conductive line 110 located in the second conductive layer 130B that is exposed at the opening 141 is a conductive pad 131, that is, the portion of the transfer line 115 that is exposed at the opening 141 is a conductive pad 131.

[0095] In addition to the above-described conductive layer 130 and protective layer 140, the wiring substrate 100 further includes other film layers. Hereinafter, based on an embodiment in which the wiring substrate 100 includes two conductive layers 130, other film layers in the wiring substrate 100 will be described.

[0096] As shown in FIG. 2A, in some examples, a buffer layer (English name: Buffer) 150 is disposed on one side of the base 120, and the buffer layer 150 is located between the base 120 and the first conductive layer 130A.

[0097] An insulating layer 160 is formed on the side of the first conductive layer 130A away from the base 120, and the insulating layer 160 is located between the second conductive layer 130B and the first conductive layer 130A. Exemplarily, the insulating layer 160 includes a first passivation layer PVX1, a first resin layer OC1, and a second passivation layer PVX2 that are sequentially disposed on the first conductive layer 130A.

[0098] A via hole is formed in the insulating layer 160, and the second conductive layer 130B can be connected to the first conductive layer 130A through the via hole in the insulating layer 160.

[0099] Exemplarily, the first passivation layer PVX1 can be formed of an inorganic insulating material such as SiN.

[0100] Exemplarily, the materials of the first passivation layer PVX1, the second passivation layer PVX2, and the protective layer 140 are the same.

[0101] Exemplarily, the first resin layer OC1 can be formed of a resin material.

[0102] In several of the above-described embodiments, an embodiment in which the wiring substrate 100 includes two conductive layers 130 has been described. However, in some other embodiments, the wiring substrate 100 may include one conductive layer 130.

[0103] FIG. 2B is a cross-sectional view of a wiring substrate 100 according to some other embodiments.

[0104] As shown in FIG. 2B, the wiring substrate 100 includes a buffer layer 150, a conductive layer 130, and a protective layer 140 that are sequentially stacked on the base 120. The protective layer 140 includes a third passivation layer PVX3 and a second resin layer OC2.

[0105] As shown in FIG. 2B, in some examples, the conductive layer 130 may have a two-layer structure. At this time, the conductive layer 130 may include two sub-conductive layers 130C. To avoid the conductive layer 130 formed in one process from being too thick, the two sub-conductive layers 130C can be formed in two processes.

[0106] FIG. 2C is a cross-sectional view of a wiring substrate 100 according to some other embodiments.

[0107] As shown in FIG. 2C, in some other examples, when the wiring substrate 100 further includes one conductive layer 130, the conductive layer 130 may have a single-layer structure.

[0108] In addition, as further shown in FIG. 2A, when the wiring substrate 100 includes two conductive layers 130, the conductive layer 130 may have a single-layer structure. Alternatively, the first conductive layer 130A and / or the second conductive layer 130B includes two sub-conductive layers 130C.

[0109] As shown in FIGS. 2A and 2B, the conductive layer 130 includes a plurality of pad groups 1300, and one pad group 1300 includes a plurality of conductive pads 131. The plurality of conductive pads 131 are arranged at intervals.

[0110] One pad group 1300 can be electrically connected to one electronic element. The plurality of pad groups 1300 are divided into a plurality of types. Each type of pad group 1300 is electrically connected to one type of electronic element, and different types of pad groups 1300 can be electrically connected to different types of electronic elements. The number of each type of pad group 1300 may be one or more.

[0111] Exemplarily, the electronic element may include the functional element 200 and the driving chip 300 described above. Specifically, the functional element may be an inorganic light-emitting diode, and the light-emitting area of the inorganic light-emitting diode does not exceed 300000 μm 2 and specifically does not exceed 40000 μm 2may not exceed, and the area of the orthographic projection on the base 120 of the drive chip 300 is 300000 μm 2 The following is. FIG. 2D relates to some embodiments backplane It is a structural diagram of 1000.

[0112] As shown in FIG. 2D, the backplane 1000 may further include other types of elements such as a circuit board 400. The circuit board 400 is located on one side of the wiring board 100.

[0113] The wiring board 100 includes a functional region BB and a coupling region CC. In FIG. 2D, the dashed frames indicated by BB and CC are for indicating the positions of the functional region BB and the coupling region CC, and do not further limit the functional region BB and the coupling region CC.

[0114] The plurality of device regions AA (as shown in FIG. 1C) described above are located in the functional region BB, and thus the plurality of pad groups 1300 (as shown in FIGS. 2A and 2B) are located in the functional region BB.

[0115] As shown in FIGS. 2A and 2B, the plurality of conductive pads 131 further include circuit board pads 1310. The circuit board pads 1310 are located in the coupling region CC, and the circuit board pads 1310 can be coupled to the pins of the circuit board 400.

[0116] Exemplarily, electronic elements such as the functional element 200, the drive chip 300, and the circuit board 400 can be fixedly connected to the conductive pads 131 by surface mounting technology (or surface mounting technology, English full name: Surface Mounted Technology, English abbreviation SMT). Exemplarily, the pins of the functional element 200 and the pins of the drive chip 300 are connected to the conductive pads 131 by a soldering process.

[0117] Exemplarily, the pins of the functional component 200 and the pins of the drive chip 300 are soldered using tin-based solder. After the reflow soldering process, the tin-based solder and the Cu layer in the pad easily form an intermetallic compound (IMC layer) such as Cu6Sn5. The IMC layer is a symbol that the pad and the device form a good connection. However, the IMC is a brittle substance. If its thickness is too large, the reliability of the soldered part will be significantly reduced. To prevent the generation of an IMC layer that is too thick at the soldered part, an electroless nickel-gold plating process is introduced as a barrier layer in the pad structure to prevent the rapid generation of the Cu-Sn compound.

[0118] As shown in FIG. 2A, in some embodiments, the barrier layer in the wiring substrate 100 further includes an oxidation protection layer 170 and a conductive functional layer 180. The oxidation protection layer 170 covers the side away from the base 120 of the conductive pad 131, and the conductive functional layer 180 covers the side away from the base 120 of the oxidation protection layer 170.

[0119] By disposing the oxidation protection layer 170 on the side away from the base 120 of the conductive pad 131, it can play a role in protecting the conductive pad 131 and can reduce the degree of oxidation of the conductive pad 131. By disposing the conductive functional layer 180 on the side away from the conductive pad 131 of the oxidation protection layer 170, it can play a role in protecting the oxidation protection layer 170, that is, it can further play a role in protecting the conductive pad 131. By reducing the degree of oxidation of the conductive pad 131 and the oxidation protection layer 170, the soldering difficulty between the functional element 200, the drive chip 300, and the wiring substrate 100 can be reduced, and the connection reliability between the functional element 200, the drive chip 300, and the wiring substrate 100 can be further improved.

[0120] Exemplarily, the material of the oxidation protection layer 170 contains nickel (Ni). Nickel is a conductive material. Nickel can chemically react with the material of the solder (for example, tin), and can improve the wettability of the solder during soldering, thereby improving the robustness of the soldering between the functional component 200, the driving chip 300, and the conductive pad 131, and further improving the connection reliability between the functional component 200, the driving chip 300, the conductive pad 131, and the wiring board 100.

[0121] Exemplarily, the conductive functional layer 180 contains a conductive material such as gold (Au).

[0122] Hereinafter, based on the fact that the material of the oxidation protection layer 170 contains nickel and the material of the conductive functional layer 180 contains gold, the formation process of the oxidation protection layer 170 and the conductive functional layer 180 in some embodiments of the present disclosure will be described.

[0123] In some examples, an electroless nickel-gold plating process can be used to form the oxidation protection layer 170 and the conductive functional layer 180.

[0124] In the electroless nickel-gold plating process, first, after pickling the wiring board 100, then the wiring board 100 is placed in an activation solution containing Pd 2+ At this time, a substitution reaction occurs between Cu in the conductive pad 131 and Pd 2+ in the activation solution, and Cu 2+ and Pd (palladium) are generated, and Pd adheres to the surface away from the base 120 of the Cu layer to form a palladium layer. Then, when the wiring board 100 is placed in a solution mainly composed of nickel sulfate, sodium hypophosphite (a reducing agent that reduces nickel ions to nickel metal), and a complexing agent, a phosphorus - nickel alloy layer (that is, the oxidation protection layer 170) is generated on the pad surface, and the phosphorus - nickel alloy layer is still easily oxidized, and it is difficult to solder to the oxidized phosphorus - nickel alloy layer and the reliability is low. Finally, the wiring board 100 is immersed in a solution containing gold ions, and phosphorus -A gold-impregnated layer (i.e., the conductive functional layer 180) is formed on the surface of the nickel alloy layer, and the gold particles in the gold-impregnated layer fill the voids in the electroless nickel-gold plating layer, thereby reducing the phosphorus - oxidation probability of the nickel alloy layer and reducing the degree of oxidation of the conductive pad 131. Then, the electronic component is soldered to the conductive pad 131 having an electroless nickel-gold plating layer (including the oxidation protection layer 170 and the conductive functional layer 180 described above) on its surface by a reflow soldering process.

[0125] FIG. 3 is a structural diagram of a wiring board 100 according to some embodiments.

[0126] As shown in FIG. 3, after the electroless nickel-gold plating process, not only the oxidation protection layer 170 (as shown in FIG. 2A) and the conductive functional layer 180 (as shown in FIG. 2A) are formed on the conductive pad 131, but also the oxidation protection layer 170 and the conductive functional layer 180 are formed on the edge of the conductive line 110 near the conductive pad 131. embodiment Here, for convenience of explanation, the phenomenon that the oxidation protection layer 170 and the conductive functional layer 180 are formed on the edge of the conductive line 110 is called an abnormal growth phenomenon. The region where the oxidation protection layer 170 and / or the conductive functional layer 180 is formed on the edge of the conductive line 110 is called an abnormal region. As shown in FIG. 3, the region surrounded by the broken line frame is the abnormal region.

[0127] As a result of research, the inventors of the present disclosure have found that the abnormal growth phenomenon occurs for the following reasons.

[0128] FIG. 4A is a cross-sectional view of a wiring board 100 according to some embodiments. FIG. 4B is a cross-sectional view of a wiring board 100 according to some embodiments.

[0129] As shown in FIG. 4A, the edge of the conductive line 110 has a step structure 1101, and the step structure 1101 needs to be covered by the protective layer 140. Usually, the step structure 1101 generates a roof structure (Tip) in the protective layer 140 that covers it here, and as a result, breakage occurs. Thereby, the protective layer 140 lacks protection at the step structure 1101, and as a result, a partial region of the step structure 1101 is exposed. Therefore, in the electroless nickel-gold plating process, the exposed region of the step structure 1101 is immersed in the activation solution, and as a result, abnormal growth of the oxidation protective layer 170 and / or the conductive functional layer 180 occurs at the step structure 1101.

[0130] As shown in FIG. 4B, the oxidation protective layer 170 and the conductive functional layer 180 in the step structure 1101 (as shown in FIG. 4A) expand spherically in the step structure 1101. In some cases, the oxidation protective layer 170 is not in complete contact with the step structure 1101, that is, there is a gap between the two. The existence of the gap provides a path for water and oxygen to erode the conductive line 110.

[0131] As further shown in FIG. 3, a part of the abnormally grown oxidation protective layer 170 and / or conductive functional layer 180 is connected in a strip shape along the edge of the conductive line 110.

[0132] In particular, the oxidation protective layer 170 and / or the conductive functional layer 180 are prone to peeling at the part that grows abnormally along the edge of the conductive line 110 and is connected in a strip shape. When peeling occurs, a tensile force is generated at other positions of the conductive line 110. As a result, the part located near the abnormal region in the conductive line 110 peels off due to the action of the tensile force, and the conductive line 110 breaks. Thereby, the functional element 200 connected to the conductive line 110 fails. In addition to this, when the peeled abnormal growth accumulates on the conductive pad 131, a short circuit occurs in the region where the conductive pad 131 is located, and finally, the functional element 200 electrically connected to the conductive pad 131 does not operate normally.

[0133] As further shown in FIG. 3, in one embodiment, the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 is much larger than the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130.

[0134] Note that the orthographic projection of the base 120 of the conductive pad 131 may be a rectangle, a square, a pentagon, or other polygons. In some examples, the orthographic projection of the base 120 of the conductive pad 131 may be circular. When the conductive pad 131 is circular, the maximum size in the direction parallel to the base 120 of the conductive pad 131 is the diameter of the circle. When the conductive pad 131 is a convex polygon, as shown in FIG. 4B, the maximum size in the direction parallel to the base 120 of the conductive pad 131 is the length of the diagonal of the conductive pad 131.

[0135] Furthermore, as shown in FIG. 3, the conductive layer 130 includes a conductive line 110, the conductive pad 131 is located in the end region of the conductive line 110, and except for the surface where the conductive pad 131 is located being exposed, the surfaces of other regions of the conductive line 110 are all covered by other film layers (for example, a protective layer). The edge of the conductive layer 130 refers to the end of the conductive line 110 including the conductive pad 131. The minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130 refers to the minimum distance between the edge of the conductive pad 131 and the edge of the conductive line 110 where it is located. The conductive line 110 has a plurality of edges, and the distance between one or more of these edges and the edge of the conductive pad 131 is the minimum.

[0136] FIG. 4C is a schematic diagram of the principle of the activation reaction according to some embodiments. Note that the arrows in FIG. 4C indicate the moving direction of ions.

[0137] As shown in FIG. 4C, in the activation reaction, Pd 2+ is an important catalyst for nickel precipitation, and Pd in the reaction region in the activation solution 2+ is rapidly consumed and deposited, but Pd in other regions 2+ diffuses and gathers in the reaction region, and Pd in the reaction region2+ is replenished. The reaction region is an area near the conductive pad 131. The larger the area of the conductive pad 131 and the larger the possible value of L1, the faster the consumption of Pd in the reaction region, the greater the diffusion rate of Pd, and the easier it is for the palladium layer to deposit on the exposed step structure 1101 (as shown in FIG. 4A). This facilitates the subsequent growth of the oxidation protection layer 170 and the conductive functional layer 180. 2+ 2+

[0138] In the above-described embodiment, L1 is much larger than L2, and the area of the conductive pad 131 is too large. As a result, Pd in the reaction region in the activation solution is rapidly consumed, the diffusion rate of Pd in the solution is too large, the palladium layer is rapidly deposited on the exposed step structure 1101, and the subsequent growth of the oxidation protection layer 170 and the conductive functional layer 180 is promoted, resulting in an abnormal growth phenomenon. 2+ 2+

[0139] Based on this, as shown in FIG. 5, FIG. 5 is a structural diagram of a wiring board 100 according to some embodiments. In the wiring board 100 according to some embodiments of the present invention, the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 is 1.5 times or more the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130, and is 30 times or less the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130, that is, 1.5×L2≦L1≦30×L2.

[0140] Exemplarily, 2×L2≦L1≦28×L2.

[0141] Exemplarily, 1.5×L2≦L1≦7.5×L2.

[0142] Exemplarily, 8×L2≦L1≦28×L2.

[0143] Exemplarily, 2.5×L2≦L1≦11×L2.

[0144] ​​​​Exemplarily, 10×L2 ≦ L1 ≦ 27×L2. Since L1 ≦ 30×L2, the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 is relatively small. As a result, the consumption rate of Pd in the reaction region in the activation solution is relatively small, and the diffusion rate of Pd in the solution can be made relatively small. Consequently, the rate of depositing a palladium layer on the exposed step structure 1101 can be reduced, and the rate of promoting the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be decreased. Thereby, the occurrence of abnormal growth phenomena can even be reduced or avoided. 2+ of which can be made relatively small, and the diffusion rate of Pd 2+ in the solution can be made relatively small.

[0145] In addition, since L1 ≧ 1.5×L2, it is possible to avoid the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 being too small (for example, less than 1.5×L2). Thereby, the reliability of the connection between the conductive pad 131 and the pins of the electronic element is ensured.

[0146] FIG. 6 is a structural diagram of a wiring board 100 according to some embodiments.

[0147] As shown in FIG. 6, in some embodiments, the wiring board 100 includes a plurality of device regions AA. The plurality of pad groups 1300 include a plurality of first pad groups 1301 located in any one of the device regions AA and one second pad group 1302.

[0148] Note that the backplane 1000 includes the wiring board 100, and the device region AA in the wiring board 100 and the device region AA in the backplane 1000 are the same region.

[0149] FIG. 7 is a structural diagram of a wiring board 100 according to some embodiments. In FIG. 7, one first pad group 1301 and one second pad group 1302 are shown.

[0150] As shown in FIG. 7, the first pad group 1301 includes first pole pads 131P and second pole pads 131N arranged at intervals. It is understood that the number of conductive pads 131 in the first pad group 1301 is not limited to two. That is, in some examples, the first pad group 1301 may include only the first pole pads 131P and the second pole pads 131N, but in some other examples, the first pad group 1301 may further include other conductive pads 131.

[0151] In some examples, the orthographic projections of the first pole pads 131P and the second pole pads 131N on the base 120 may be circular or polygonal such as square, rectangular, and pentagonal.

[0152] The first pole pad 131P may be connected to the first pin P of the functional element 200, and the second pole pad 131N may be connected to the second pin N of the functional element 200. In FIG. 7, the functional element 200 and the first pin P and the second pin N of the functional element 200 are not shown, and reference may be made to FIG. 1D.

[0153] The area of the first pole pad 131P is larger than the area of the first pin P, and the area of the second pole pad 131N is larger than the area of the second pin N. Thereby, the reliability of the connection between the functional element 200 and the wiring board 100 can be ensured.

[0154] As shown in FIG. 7, the second pad group 1302 includes at least a power supply pad Pwr’, a ground pad Gnd’, an address pad Di’, and an output pad Ot’ arranged at intervals. The second pad group 1302 is connected to the driving chip 300. The power supply pad Pwr’ is connected to the power supply pin Pwr of the driving chip 300, the ground pad Gnd’ is connected to the ground pin Gnd of the driving chip 300, the address pad Di’ is connected to the address pin Di of the driving chip 300, and the output pad Ot’ is connected to the output pin Ot of the driving chip 300.

[0155] In some examples, the orthographic projections of the power pad Pwr’, the ground pad Gnd’, the address pad Di’, and the output pad Ot’ on the base 120 may be polygons such as circles, squares, rectangles, and pentagons.

[0156] In some examples, the address pad Di’ and the output pad Ot’ are arranged opposite to two adjacent edges of the power pad Pwr’ respectively, and the address pad Di’ and the output pad Ot’ are further arranged opposite to two adjacent edges of the ground pad Gnd’ respectively.

[0157] As further shown in FIG. 6, the wiring substrate 100 further includes a source address line 111, a source voltage line 112, a drive voltage line 113, and a common voltage line 114.

[0158] In the same device region AA, the power pad Pwr’ is electrically connected to the source voltage line 112, and the address pad Di’ is electrically connected to the output pad Ot’ within another device region AA. The power pad Pwr’ is electrically connected to the source voltage line 112, the ground pad Gnd’ is electrically connected to the common voltage line 114, the address pad Di’ is electrically connected to the source address line 111, and the output pad Ot’ is electrically connected to the drive voltage line 113.

[0159] When the wiring substrate 100 includes two conductive layers 130, the conductive pad 131 is located in the second conductive layer 130B. At this time, the power pad Pwr’ is electrically connected to the source voltage line 112 through the transfer line 115 (as shown in FIG. 7), the ground pad Gnd’ is electrically connected to the common voltage line 114 through the transfer line 115, the address pad Di’ is electrically connected to the source address line 111 through the transfer line 115, and the output pad Ot’ is electrically connected to the drive voltage line 113 through the transfer line 115.

[0160] As shown in FIG. 6, in the same device region AA, among a plurality of first pad groups 1301, the first pole pad 131P in the first first pad group 1301A is electrically connected to the drive voltage line 113, and the first pole pad 131P in the first first pad group 1301A is connected to the first pin P of the first functional element 200A (as shown in FIG. 1C). Thereby, the first pin P of the first functional element 200A is electrically connected to the drive voltage line 113.

[0161] In some examples, the plurality of device regions AA are arranged in a plurality of rows and a plurality of columns. The first pole pads 131P in the plurality of first first pad groups 1301A within one column of device regions AA are connected to the same drive voltage line 113. Therefore, the first pole pads 131P in the plurality of first first pad groups 1301A are arranged in parallel.

[0162] As shown in FIG. 6, in the same device region AA, the second pole pad 131N in the previous first pad group 1301 is electrically connected to the first pole pad 131P in the next first pad group 1301, and the second pole pad 131N in the last first pad group 1301 is electrically connected to the output pad Ot'. Here, the previous first pad group 1301 and the next first pad group 1301 refer to two adjacent first pad groups 1301.

[0163] One or more functional branches may be arranged within the same device region AA. One functional branch has one first functional element 200A (as shown in FIG. 1C), and it is understood that one or more first first pad groups 1301A may be included within the same device region AA.

[0164] When the wiring substrate 100 includes two conductive layers 130, the second pole pad 131N in the previous first pad group 1301 and the first pole pad 131P in the next first pad group 1301 are arranged at both ends of one transfer line 115, respectively.

[0165] Exemplarily, as shown in FIG. 6, the same device region AA includes nine first pad groups 1301, and the nine first pad groups 1301 are, in sequence, the first first pad group 1301A, …, the eighth first pad group 1301H, and the ninth first pad group 1301I. The ninth first pad group 1301I is the last first pad group 1301.

[0166] Among the eighth first pad group 1301H and the ninth first pad group 1301I, it is understood that the eighth first pad group 1301H is the previous first pad group 1301, and the ninth first pad group 1301I is the next first pad group 1301. The second pole pad 131N of the eighth first pad group 1301H is electrically connected to the first pole pad 131P of the ninth first pad group 1301I.

[0167] The first pole pad 131P and the second pole pad 131N in the first pad group 1301 are arranged adjacent to each other, the first pole pad 131P and the second pole pad 131N are insulated from each other, and the two need to be electrically connected via the functional element 200.

[0168] In some embodiments, at least one of the maximum size L1 in the direction parallel to the base 120 of at least the first pole pad 131P, the power supply pad Pwr’, and the ground pad Gnd’ in the first first pad group 1301A is 30 times or less the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130. Here, the “said pad” is understood to refer to any one of the first pole pad 131P, the power supply pad Pwr’, and the ground pad Gnd’ in at least the first first pad group 1301A described above.

[0169] In the activation reaction, the activation solution can be the cathode, and the conductive layer 130 can be the anode. Cu in the conductive layer 130 loses electrons to form Cu 2+To form this, the electrons lost by Cu can flow into the conductive line 110. At this time, the first pole pads 131P in the plurality of first first pad groups 1301A connected to the same drive voltage line 113 undergo an electrochemical parallel reaction, that is, the first pole pads 131P in the plurality of first first pad groups 1301A are arranged in parallel. Therefore, the electrons lost by the first pole pads 131P in the plurality of first first pad groups 1301A flow into the drive voltage line 113. When the wiring substrate 100 includes two conductive layers 130, it is understood that the electrons lost by the first pole pads 131P in the plurality of first first pad groups 1301A also flow into the transfer line 115 connected to the drive voltage line 113.

[0170] According to the principle of a parallel circuit, it is known that the total current of a parallel circuit is equal to the sum of the currents of each branch. Therefore, the more conductive pads 131 electrically connected to the conductive line 110, the greater the current flowing in the conductive line 110. The number of conductive pads 131 electrically connected to the drive voltage line 113 is relatively large and more than the number of conductive pads 131 electrically connected to some other conductive lines 110. Therefore, the current flowing in the drive voltage line 113 is relatively large, and thus the current flowing through the first pole pads 131P in the first first pad group 1301A electrically connected to the drive voltage line 113 is relatively large. On the other hand, the higher the current, the faster the substitution reaction rate, that is, the faster the formation rate of the palladium layer, and thus the easier the subsequent formation of the oxidation protection layer 170 and the conductive functional layer 180. Therefore, in the protection layer lacking region around the first pole pads 131P in the first first pad group 1301A (that is, the region where the step structure 1101 is exposed), an abnormal growth phenomenon is likely to occur.

[0171] Similarly, all the power pads Pwr' in the plurality of second pad groups 1302 are electrically connected to the source voltage line 112. Therefore, the plurality of power pads Pwr' are arranged in parallel. Thus, the greater the current flowing through the source voltage line 112, the faster the replacement reaction rate of the plurality of power pads Pwr' electrically connected to the source voltage line 112, that is, the faster the formation rate of the palladium layer, and thus the easier the subsequent formation of the oxidation protection layer 170 and the conductive functional layer 180. Therefore, in the protection layer lack region around the power pad Pwr' (i.e., the region where the step structure 1101 is exposed), an abnormal growth phenomenon is likely to occur.

[0172] Similarly, all the ground pads Gnd' in the plurality of second pad groups 1302 are electrically connected to the common voltage line 114. Therefore, the plurality of ground pads Gnd' are arranged in parallel. Thus, the greater the current flowing through the common voltage line 114, the faster the replacement reaction rate of the plurality of ground pads Gnd' electrically connected to the common voltage line 114, that is, the faster the formation rate of the palladium layer, and thus the easier the subsequent formation of the oxidation protection layer 170 and the conductive functional layer 180. Therefore, in the protection layer lack region around the ground pad Gnd' (i.e., the region where the step structure 1101 is exposed), an abnormal growth phenomenon is likely to occur.

[0173] Therefore, in some embodiments of the present invention, at least one of the first pole pad 131P, the power pad Pwr', and the ground pad Gnd' in the at least first first pad group 1301A is such that the maximum size L1 in the direction parallel to the base 120 is 30 times or less the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130. The abnormal growth phenomenon in the protection layer lack region near at least one of the first pole pad 131P, the power pad Pwr', and the ground pad Gnd' in the first first pad group 1301A can be reduced.

[0174] In some examples, it is possible to ensure that the maximum size L1 in the direction parallel to the base 120 of only the first pole pad 131P, the power pad Pwr’, and the ground pad Gnd’ in the first first pad group 1301A is not more than 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130.

[0175] In some other examples, it is possible to ensure that the maximum size L1 in the direction parallel to the base 120 of some of the first pole pad 131P, the power pad Pwr’, and the ground pad Gnd’ in the first first pad group 1301A is not more than 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130.

[0176] In some other examples, it is possible to ensure that the maximum dimension L1 in the direction parallel to the base 120 of all the conductive pads 131 in the wiring board 100 is not more than 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130.

[0177] Above, the embodiment in which the device region AA in the wiring board 100 includes one sub-device region A1 and one control region A2 has been described. Hereinafter, the case where the device region AA includes at least two sub-device regions A1 and one control region A2 will be described.

[0178] FIG. 8 is a structural diagram of a wiring board 100 according to some embodiments.

[0179] As shown in FIG. 8, in some other examples, the device region AA includes at least two sub-device regions A1 and one control region A2.

[0180] The plurality of pad groups 1300 includes a plurality of first pad groups 1301 located in any one of the sub-device regions A1, and the first pad group 1301 includes a first pole pad 131P and a second pole pad 131N arranged at intervals. The first pad group 1301 is used to be connected to the functional element 200.

[0181] The plurality of pad groups 1300 further includes a second pad group 1302 located in the control region A2. The second pad group 1302 includes a power pad Pwr’, a ground pad Gnd’, an address input pad Din’, an address output pad Dio’, and at least two output pads (such as Ot1’ and Ot2’). The power pad Pwr’ is electrically connected to the power supply voltage line 112. The address output pad Dio’ in the control region A2 in one of the two different device regions AA is connected to the address input pad Din’ in the control region A2 in the other device region AA.

[0182] In the same sub-device region A1, among the plurality of first pad groups 1301, the first pole pad 131P in the first first pad group 1301A is electrically connected to the drive voltage line 113, the second pole pad 131N in the previous first pad group 1301 is electrically connected to the first pole pad 131P in the next first pad group 1301, and the second pole pad 131N in the last first pad group 1301I is electrically connected to one output pad Otx’, where x is a positive integer of 2 or more. The second pole pads 131N in the last first pad group 1301I of each sub-device region A1 among the plurality of sub-device regions A1 are respectively connected to one output pad Otx’ in the control region A2. Exemplarily, when the device region AA includes two sub-device regions A1, at this time, the output pad Ot2’ is the output pad Otx’, the second pole pad 131N in the last first pad group 1301I in one sub-device region A1 is connected to the output pad Ot1’, and the second pole pad 131N in the last first pad group 1301I in the other sub-device region A1 is connected to the output pad Ot2’.

[0183] The maximum size in the direction parallel to the base 120 of the first pole pad 131P in at least the first first pad group 1301A is 30 times or less the minimum distance between the edge of the first pole pad 131P and the edge of the conductive layer 130.

[0184] Among a plurality of sub-device regions A1 belonging to the same device region AA, the first pole pads 131P in the first first pad group 1301A of each sub-device region A1 are arranged in parallel. As can be seen from the above, the larger the number of conductive pads 131 arranged in parallel on one conductive line 110, the faster the replacement reaction rate of the conductive pads 131 on the conductive line 110, that is, the faster the formation rate of the palladium layer, and thus the subsequent formation of the oxidation protection layer 170 and the conductive functional layer 180 becomes easier. Therefore, in the protection layer lacking region near the first pole pad 131P in the first first pad group 1301A (that is, the region where the step structure 1101 is exposed), an abnormal growth phenomenon is likely to occur.

[0185] By making the maximum size L1 in the direction parallel to the base 120 of the first pole pad 131P in the first first pad group 1301A be 30 times or less the minimum distance between the edge of the first pole pad 131P and the edge of the conductive layer 130, the abnormal growth phenomenon in the protection layer lacking region near the first pole pad 131P in the first first pad group 1301A can be reduced.

[0186] In some other embodiments, the wiring substrate 100 may include one device region AA, and the device region AA includes a plurality of sub-device regions A1 and one control region A2.

[0187] The plurality of pad groups 1300 include a plurality of first pad groups 1301 located in any sub-device region A1. Exemplarily, one light-emitting branch is arranged in one sub-device region A1.

[0188] The plurality of pad groups 1300 further include a second pad group 1302 located in the control region A2. The second pad group 1302 includes a power supply pad Pwr’, a ground pad Gnd’, an address pad Di’ and a plurality of output pads Ot’. The number of output pads Ot’ is the same as the number of light-emitting branches.

[0189] In the same sub-device region A1, among a plurality of first pad groups 1301, the first pole pad 131P in the first first pad group 1301A is electrically connected to the drive voltage line 113, and the second pole pad 131N in the previous first pad group 1301 is electrically connected to the first pole pad 131P in the next first pad group 1301. The second pole pad 131N in the last first pad group 1301I is electrically connected to one output pad Ot'. Note that the second pole pads 131N in the last first pad groups 1301I in all sub-device regions A1 are connected to different output pads Ot', respectively.

[0190] In addition to the embodiment in which the second pole pads 131N in the last first pad groups 1301I in each of the above-described sub-device regions A1 are connected to different output pads Ot', respectively, it is also possible to provide only one output pad Ot' in the control region A2. At this time, the second pole pads 131N in the last first pad groups 1301I in each sub-device region A1 are connected to the same output pad Ot'. At this time, since the second pole pads 131N in the last first pad groups 1301I in a plurality of sub-device regions A1 are arranged in parallel, an abnormal growth phenomenon is likely to occur in the protective layer lacking region near the second pole pads 131N in the last first pad group 1301I.

[0191] In some examples, the maximum size L1 in the direction parallel to the base 120 of the first pole pad 131N in the last first pad group 1301 can be made 30 times or less the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130.

[0192] In some examples, the maximum size L1 in the direction parallel to the base 120 of the first pole pad 131P in the first first pad group 1301A and / or the second pole pad 131N in the last first pad group 1301 can be made 30 times or less the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130. FIG. 9A is a partially enlarged view of D in FIG. 7, and FIG. 9A shows one first pad group 1301.

[0193] In some examples, the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 in the first pad group 1301 is not less than 1.5 times the minimum distance L21 between the edge of the conductive pad 131 and the edge of the conductive layer 130, and is not more than 28 times the minimum distance L21 between the edge of the conductive pad 131 and the edge of the conductive layer 130, that is, 1.5×L21≦L11≦28×L21. In some examples, it is understood that the conductive pad 131 in the first pad group 1301 refers to the first pole pad 131P and the second pole pad 131N.

[0194] Since L11≦28×L21, the maximum size L11 in the direction parallel to the base 120 of the conductive pad 131 in the first pad group 1301 is relatively small. Thereby, the consumption rate of Pd in the reaction region corresponding to the conductive pad 131 in the first pad group 1301 in the activation solution is reduced, and the diffusion rate of Pd 2+ can be reduced. As a result, the rate of depositing the palladium layer on the exposed step structure 1101 near the conductive pad 131 in the first pad group 1301 can be reduced, the rate of promoting the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided. 2+ Moreover, since L11≧1.5×L21, it is possible to avoid the maximum size L11 in the direction parallel to the base 120 of the conductive pad 131 in the first pad group 1301 being too small (for example, less than 1.5×L21). Thereby, the reliability of the connection between the conductive pad 131 and the pin of the functional element 200 is ensured.

[0195]

[0196] Exemplarily, 2.3×L21≦L11≦28×L21.

[0197] Exemplarily, 3×L21≦L11≦10×L21.

[0198] Exemplarily, 2.3×L21≦L11≦7×L21.

[0199] Exemplarily, 9×L21 ≦ L11 ≦ 28×L21.

[0200] Exemplarily, 2×L21 ≦ L11 ≦ 15×L21.

[0201] Exemplarily, 12 μm ≦ L21 ≦ 50 μm.

[0202] FIG. 9B is a partially enlarged view at E in FIG. 7.

[0203] As shown in FIG. 9B, in some examples, the maximum size L12 in the direction parallel to the base 120 of the conductive pad 131 in the second pad group 1302 is 1.5 times or more the minimum distance L22 between the edge of the conductive pad 131 and the edge of the conductive layer 130, and is 26 times or less the minimum distance L22 between the edge of the conductive pad 131 and the edge of the conductive layer 130, that is, 1.5×L22 ≦ L12 ≦ 26×L22. In some examples, it is understood that the conductive pads 131 in the second pad group 1302 refer to the power supply pad Pwr’, the ground pad Gnd’, the address pad Di’ and the output pad Ot’.

[0204] Since L12 ≦ 26×L22, the maximum size L12 in the direction parallel to the base 120 of the conductive pad 131 in the second pad group 1302 is relatively small. Thereby, the consumption rate of Pd in the reaction region corresponding to the conductive pad 131 in the second pad group 1302 in the activation solution is reduced, and thus the diffusion rate of Pd 2+ can be reduced, and thus the deposition rate of the palladium layer on the exposed step structure 1101 near the conductive pad 131 in the second pad group 1302 can be reduced, and the growth promotion rate of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided. 2+

[0205] ​Also, since L12 ≧ 1.5 × L22, it is possible to avoid the situation where the maximum size L12 in the direction parallel to the base 120 of the conductive pad 131 in the second pad group 1302 is too small (for example, less than 1.5 × L22). Thereby, the reliability of the connection between the conductive pad 131 and the pin of the drive chip 300 is ensured.

[0206] Exemplarily, 1.5 × L22 ≦ L12 ≦ 5 × L22.

[0207] Exemplarily, 5 × L22 ≦ L12 ≦ 11 × L22.

[0208] Exemplarily, 2.5 × L22 ≦ L12 ≦ 5.5 × L22.

[0209] Exemplarily, 2.5 × L22 ≦ L12 ≦ 7 × L22.

[0210] Exemplarily, 2.5 × L22 ≦ L12 ≦ 15 × L22.

[0211] Exemplarily, 15 × L22 ≦ L12 ≦ 25 × L22.

[0212] Exemplarily, 7 μm ≦ L22 ≦ 50 μm.

[0213] As further shown in FIGS. 9A and 9B, in some embodiments, in the same pad group 1300, the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 is 0.5 to 5 times the distance between the conductive pad 131 and the adjacent conductive pad, that is, 0.5 × L3 ≦ L1 ≦ 5 × L3. Two adjacent conductive pads 131 are located in the same pad group 1300. The distance L3 between one conductive pad 131 and the adjacent conductive pad 131 is the minimum distance between the two.

[0214] In some embodiments, two adjacent conductive pads 131 in the same pad group 1300 may be respectively disposed on two conductive lines 110. At this time, the distance between two adjacent conductive pads 131 is affected by the distance between the two conductive lines 110 where the two adjacent conductive pads 131 are located. At this time, the greater the distance between the two conductive lines 110 where the two adjacent conductive pads 131 are located, the greater the distance between the two adjacent conductive pads 131 can be set.

[0215] In some other examples, two adjacent conductive pads 131 in the same conductive pad 1300 may be located on the same conductive line 110. For example, the driving chip 300 includes two ground pins Gnd. Correspondingly, the second conductive pad 1302 connected to the driving chip 300 includes two ground pads Gnd'. The ground pins Gnd in the driving chip 300 are separated from each other. Therefore, the two ground pads Gnd' are arranged at intervals from each other. At this time, the two ground pads Gnd' may be arranged on the same conductive line 110. At this time, the two ground pads Gnd' are arranged adjacent to each other, and the shape of the two ground pads Gnd' and the distance between the two may be limited by the line width and / or line length of the conductive line 110 where the two ground pads Gnd' are located. At this time, the smaller the line width and / or line length of the conductive line 110 where the two ground pads Gnd' are located, the relatively smaller the distance between the two ground pads Gnd'.

[0216] It is understood that the relative positional relationship of each conductive pad in any first pad group is substantially the same as the relative positional relationship of each pin of an electronic element to be connected to the first pad group, and the relative positional relationship of each conductive pad in any second pad group is substantially the same as the relative positional relationship of each pin of an electronic element to be connected to the second pad group.

[0217] By setting 0.5×L3≦L1≦5×L3, it is possible to avoid L1 being too large (for example, larger than 5×L3). Thereby, Pd in the reaction region in the activation solution 2+Reduce the consumption rate and reduce the diffusion rate of Pd in the solution, thereby reducing the deposition rate of the palladium layer on the exposed step structure 1101, and then reducing the promotion rate of the growth of the oxidation protection layer 170 and the conductive functional layer 180, and reducing or avoiding the occurrence of abnormal growth phenomena. Also, it is possible to avoid L1 being too small (for example, less than 0.5×L3). Thereby, the reliability of the connection between the conductive pad 131 and the pin of the electronic element is ensured. 2+ It is possible to reduce the diffusion rate of Pd, and thus reduce the deposition rate of the palladium layer on the exposed step structure 1101, and then reduce the promotion rate of the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180, and reduce or avoid the occurrence of abnormal growth phenomena. Also, it is possible to avoid L1 being too small (for example, less than 0.5×L3). Thereby, the reliability of the connection between the conductive pad 131 and the pin of the electronic element is ensured.

[0218] As shown in FIGS. 9A and 9B, in some embodiments, the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 is 105 μm or more and 350 μm or less.

[0219] Since 105 μm ≤ L1 ≤ 350 μm, it is possible to avoid L1 having a value that is too large (for example, greater than 350 μm). As can be seen from the above, the larger L1 is, the faster the consumption rate of Pd in the reaction region in the activation solution. Therefore, in some embodiments of the present disclosure, by setting L1 ≤ 2+ μm, the consumption rate of Pd in the reaction region in the activation solution can be reduced, the diffusion rate of Pd can be reduced, and thus the deposition rate of the palladium layer on the exposed step structure 1101 can be reduced, and the promotion rate of the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided. 350 μm, the consumption rate of Pd in the reaction region in the activation solution can be reduced, and the diffusion rate of Pd can be reduced, and thus the deposition rate of the palladium layer on the exposed step structure 1101 can be reduced, and the promotion rate of the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided. 2+ of the consumption rate of Pd in the reaction region in the activation solution, and reduce the diffusion rate of Pd, and thus reduce the deposition rate of the palladium layer on the exposed step structure 1101, and then reduce the promotion rate of the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180, and reduce or avoid the occurrence of abnormal growth phenomena. 2+ It is also possible to reduce or avoid the occurrence of abnormal growth phenomena.

[0220] Also, it is possible to avoid the reliability of the connection between the conductive pad 131 and the pin of the electronic element from decreasing when L1 is too small (for example, less than 105 μm). Here, it is understood that the "electronic element" includes the above-described functional component 200 and the drive chip 300. In some embodiments of the present disclosure, by setting L1 to 105 μm or more, the reliability of the connection between the conductive pad 131 and the pin of the electronic element can be ensured.

[0221] As shown in FIG. 9A, in some examples, the maximum size L11 in the direction parallel to the base 120 of the conductive pad 131 in the first pad group 1301 is 105 μm or more and 350 μm or less.

[0222] In some examples, the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130 is 7 μm or more and 50 μm or less.

[0223] Exemplarily, the conductive pad 131 in the first pad group 1301 is rectangular.

[0224] In some examples, the length L4 of the conductive pad 131 in the first pad group 1301 is 2 × L21 or more and 25 × L21 or less.

[0225] In some examples, the length L4 of the conductive pad 131 in the first pad group 1301 is 80 μm or more and 280 μm or less.

[0226] Exemplarily, the possible values of L4 may be 102 μm, 162 μm, 264 μm, etc.

[0227] In some examples, the width L5 of the conductive pad 131 in the first pad group 1301 is L21 or more and 20 × L21 or less.

[0228] In some examples, the width L5 of the conductive pad 131 in the first pad group 1301 is 45 μm or more and 220 μm or less.

[0229] Exemplarily, the possible values of L5 may be 62 μm, 122 μm, 205 μm, etc.

[0230] Exemplarily, 12 μm ≤ L21 ≤ 50 μm.

[0231] As shown in FIG. 9B, in some examples, the maximum size L12 in the direction parallel to the base 120 of the conductive pad 131 in the second pad group 1302 is 105 μm or more and 190 μm or less.

[0232] In some examples, the conductive pad 131 in the second pad group 1302 is square. At this time, the side length L6 of the conductive pad 131 in the second pad group 1302 is not less than 1.5×L22 and not more than 20×L22.

[0233] In some examples, L6 is not less than 70 μm and not more than 140 μm.

[0234] Exemplarily, the possible values of L6 may be 82 μm, 92 μm, 122 μm, etc.

[0235] Exemplarily, 7 μm ≤ L22 ≤ 50 μm.

[0236] In some embodiments, the size of the area of the conductive pads 131 in at least two pad groups 1300 has a positive correlation with the distance L3 between two adjacent conductive pads 131.

[0237] It is understood that the larger the area of the conductive pad 131, the larger the distance L3 between the conductive pad 131 and the adjacent conductive pad 131.

[0238] The larger the distance L3 between two adjacent conductive pads 131, the larger the reaction area corresponding to the pad group 1300 where the two adjacent conductive pads 131 are located. At this time, the consumption rate of Pd 2+ in the reaction region corresponding to the pad group 1300 becomes slower. The larger the area of the conductive pad 131, the faster the consumption of Pd 2+ in the reaction region corresponding to the conductive pad 131, and thus the consumption rate of Pd 2+ in the reaction region corresponding to the pad group 1300 where the conductive pad 131 is located becomes faster.

[0239] Therefore, in some embodiments of the present disclosure, when the area of the conductive pad 131 is relatively large, by increasing the distance L3 between the conductive pad 131 and the adjacent conductive pad 131, the Pd in the reaction region corresponding to the pad group 1300 where the conductive pad 131 is located 2+ consumption rate can be reduced, and thus the diffusion rate of Pd in the solution 2+ can be reduced. Thereby, the deposition rate of the palladium layer on the exposed step structure 1101 can be reduced, the growth promotion rate of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided.

[0240] In some examples, among the two specified pad groups 1300, the area of the conductive pad 131 in one pad group 1300 is larger than the area of the conductive pad 131 in the other pad group 1300, and the distance L3 between the conductive pad 131 with the larger area and the adjacent conductive pad 131 is larger than the distance L3 between two adjacent conductive pads 131 in the other pad group 1300.

[0241] On the contrary, in some other examples, among the two other specified pad groups 1300, the area of the conductive pad 131 in one pad group 1300 is larger than the area of the conductive pad 131 in the other pad group 1300, and the distance L3 between the conductive pad 131 with the larger area and the adjacent conductive pad 131 is smaller than the distance L3 between two adjacent conductive pads 131 in the other pad group 1300.

[0242] In some embodiments, the area of the conductive pad 131 is 5000 μm 2 or more and 55000 μm 2 or less.

[0243] By setting the area of the conductive pad 131 to 55000 μm 2 or less, it is possible to avoid the area of the conductive pad 131 becoming too large. Thereby, the consumption rate of Pd in the reaction region in the activation solution is slowed down, and the Pd in the solution 2+ ​2+ The diffusion rate can be slowed down, and consequently, the deposition rate of the palladium layer on the exposed stepped structure 1101 can be decreased, the promotion rate of the subsequent growth of the oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided.

[0244] Also, by setting the area of the conductive pad 131 to 5000 μm 2 or more, it is possible to avoid the area of the conductive pad 131 from becoming too small, and consequently, the reliability of the connection between the conductive pad 131 and the pin of the electronic element can be ensured.

[0245] In some examples, the area of the conductive pad 131 in the first pad group 1301 is 5000 μm 2 or more and 55000 μm 2 or less. Exemplarily, the area of the conductive pad 131 in the first pad group 1301 is 6200 μm 2 or more and 54700 μm 2 or less.

[0246] In some examples, the area of the conductive pad 131 in the second pad group 1302 is 5500 μm 2 or more and 15500 μm 2 or less.

[0247] Exemplarily, the area of the conductive pad 131 in the second pad group 1302 is 6600 μm 2 or more and 15000 μm 2 or less.

[0248] In some embodiments, in the same pad group 1300, the distance L3 between two adjacent conductive pads 131 is 70 μm or more and 214 μm or less, that is, 70 μm ≤ L3 ≤ 214 μm.

[0249] As can be seen from the above, the larger the possible value of L3, the more Pd in the reaction region in the activation solution 2+The consumption rate becomes slower. In contrast, in some embodiments of the present disclosure, by setting L3≥70 μm, it is possible to avoid the situation where L3 is too small (for example, less than 70 μm). As a result, 2+ the consumption rate of Pd in the reaction region in the activation solution is slowed down, and the diffusion rate of Pd 2+ in the solution can be slowed down. Consequently, the consumption rate of Pd 2+ in the reaction region in the activation solution becomes slower, and the rate of depositing the palladium layer on the exposed step structure 1101 can be reduced. Subsequently, the rate of promoting the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be decreased, and the occurrence of abnormal growth phenomena can also be reduced or avoided.

[0250] Also, by setting L3≤214 μm, it is possible to avoid the situation where L3 is too large (for example, larger than 214 μm), which would cause the distance between two adjacent conductive pads 131 to become too large, and the area occupied by the pad group 1300 where the two conductive pads are located to become too large, resulting in the area of the wiring substrate 100 becoming too large.

[0251] In some of the above embodiments, it has been explained that by reducing the area of the conductive pad 131 and / or increasing the distance between two adjacent conductive pads 131, the occurrence of the phenomenon of poor growth can be reduced. However, there are also other methods to reduce the occurrence of the phenomenon of poor growth.

[0252] Hereinafter, the relationship between the area of the conductive pad 131 and the size of the pins of the electronic element connected to the conductive pad 131 will be described.

[0253] FIG. 10 is a structural diagram of a wiring substrate 100 according to some embodiments. The dashed frame indicated by P is the region covered by the orthographic projection of the first pin P of the functional element 200 on the conductive layer 130. The dashed frame indicated by N is the region covered by the orthographic projection of the second pin N of the functional element 200 on the conductive layer 130.

[0254] In some examples, the pattern formed by the orthographic projection of the conductive pad 131 on the base 120 and the pattern formed by the orthographic projection of the pin of the electronic element connected to the conductive pad 131 on the base 120 are substantially the same in shape. For the convenience of explanation, the pattern formed by the orthographic projection of the conductive pad 131 on the base 120 is defined as the first pattern J, and the pattern formed by the orthographic projection of the pin of the electronic element on the base 120 is defined as the second pattern K. Also, it is understood that the above-described conductive pad 131 may be the first pole pad 131P or the second pole pad 131N in the first pad group 1301, or any one of the power supply pad Pwr’, the ground pad Gnd’, the address pad Di’, and the output pad Ot’ in the second pad group 1302. The pin of the electronic element may be the first pin P or the second pin N of the functional element 200, or any one of the power supply pin Pwr, the ground pin Gnd, the address pin Di, and the output pin Ot in the driving chip 300.

[0255] The second pattern K is located within the first pattern J. Exemplarily, both the first pattern J and the second pattern K are rectangles.

[0256] In some examples, the first pattern J includes at least one first edge J1. When the first pattern J includes one first edge J1, it is understood that the first pattern J is circular. Also, when the first pattern J is rectangular, the lengths of some of the first edges J1 of the first pattern J are different. When the first pattern J is square, the lengths of the plurality of first edges J1 of the first pattern J are the same.

[0257] The second pattern K includes at least one second edge K2. One first edge J1 and one second edge K2 are arranged opposite to each other. When the second pattern K includes one second edge K2 it is understood that the second pattern K is circular. When the second pattern K is rectangular, the lengths of some of the second edges K2 of the second pattern K are different. When the second pattern K is square, the lengths of the plurality of second edges K2 of the second pattern K are the same.

[0258] Of the first edge J1 and the second edge K2 that are arranged opposite to each other, the difference between the length Lj of the first edge J1 and the length Lk of the second edge K2 is 2 μm or more and 4 μm or less, that is, 2 μm ≤ Lj - Lk ≤ 4 μm. The length Lj of the first edge J1 is longer than the length Lk of the second edge K2.

[0259] Hereinafter, taking the case where the conductive pad 131 is the first pole pad 131P or the second pole pad 131N in the first pad group 1301 as an example, the first edge J1 and the second edge K2 will be exemplarily described.

[0260] In the same first pad group 1301, the pattern formed by the orthographic projection on the base 120 of the first pole pad 131P and the pattern formed by the orthographic projection on the base 120 of the second pole pad 131N have the same shape and the same size. "Having the same shape and the same size" means that the pattern formed by the orthographic projection on the base 120 of the first pole pad 131P can completely overlap with the pattern formed by the orthographic projection on the base 120 of the second pole pad 131N after being translated parallel by a predetermined distance on the base 120.

[0261] As shown in FIG. 10, the first pattern J includes two first first edges J11 and two second first edges J12, and the length of the first first edge J11 is longer than the length of the second first edge J12. The second pattern K includes two first second edges K21 and two second second edges K22, and the length of the first second edge K21 is longer than the length of the second second edge K22. One first first edge J11 is arranged opposite to one first second edge K21, and one second first edge J12 is arranged opposite to one second second edge K22.

[0262] The difference between the length Lj1 of the first first edge J11 and the length Lk1 of the first second edge K21 is 2 μm or more and 4 μm or less, that is, 2 μm ≤ Lj1 - Lk1 ≤ 4 μm. The length Lj2 of the second first edge J12 and the length Lk2 of the second second edge K22 are 2 μm or more and 4 μm or less, that is, 2 μm ≤ Lj2 - Lk2 ≤ 4 μm.

[0263] In the first edge J1 and the second edge K2 arranged opposite to each other, by making the difference between the length Lj of the first edge J1 and the length Lk of the second edge K2 4 μm or less, it is possible to avoid the situation where the length of the first edge J1 is too large and the area of the conductive pad 131 in the first pad group 1301 becomes too large. As a result, the consumption rate of Pd in the reaction region in the activation solution 2+ can be slowed down, and the diffusion rate of Pd 2+ in the solution can be slowed down. Consequently, the rate of depositing the palladium layer on the exposed step structure 1101 can be reduced, and the rate of promoting the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided. Also, in the first edge J1 and the second edge K2 arranged opposite to each other, by making the difference between the length Lj of the first edge J1 and the length Lk of the second edge K2 2 μm or more, it is possible to avoid the situation where the length Lj of the first edge J1 becomes too small, the area of the conductive pad 131 becomes too small, and the reliability of the connection between the conductive pad 131 in the first pad group 1301 and the pin of the functional element 200 cannot be ensured.

[0264] As can be seen from the above, the wiring board 100 may include two conductive layers 130 or may include one conductive layer 130. Hereinafter, based on an embodiment in which the wiring board 100 includes one conductive layer 130, the conductive pad 131 in the wiring board 100 will be described.

[0265] FIG. 11 is a structural diagram of a wiring board 100 according to some embodiments. FIG. 12 is a partial enlarged view of F in FIG. 11.

[0266] As shown in FIGS. 11 and 12, the second pad group 1302 is located on the source voltage line 112, and the source voltage line 112 passes through the gap between the ground pad Gnd’ and the output pad Ot’.

[0267] In some examples, the ground pad Gnd’ and the address pad Di’ are arranged to face two adjacent edges of the output pad Ot’, respectively. Also, the ground pad Gnd’ and the address pad Di’ are arranged to face two adjacent edges of the power supply pad Pwr’, respectively.

[0268] FIG. 13 is a partially enlarged view at G in FIG. 2A.

[0269] In some embodiments, the conductive layer 130 includes a plurality of conductive lines 110, the region exposed by the opening 141 of the conductive line 110 is the conductive pad 131, and in a cross-section perpendicular to the base and perpendicular to the extending direction of the conductive line 110, the main surface 1102 of the conductive line 110 and the side surface 1103 connected to the main surface 1102 can be seen. The main surface 1102 is the surface away from the base 102 of the conductive line 110, and the included angle H1 between the main surface 1102 and the side surface 1103 is 105° or more and 145° or less.

[0270] The larger the included angle H1 between the main surface 1102 and the side surface 1103, the easier it is to generate the step structure 1101, and thus the edge of the conductive line 110 is more likely to be exposed.

[0271] In some embodiments of the present disclosure, by setting the included angle H1 between the main surface 1102 and the side surface 1103 to 105° or more, it is possible to avoid the situation where H1 is too small (for example, less than 105°), and H1 can be made relatively small, so that the probability of generating the step structure 1101 is relatively small. Thereby, the probability that the edge of the conductive line 1100 is exposed can be made relatively small, and the abnormal growth phenomenon can be reduced.

[0272] Furthermore, the included angle H2 between the side surface 1103 and the base 120 is complementary to the included angle H1 between the main surface 1102 and the side surface 1103, that is, H1 + H2 = 180°, where H2 refers to the acute angle sandwiched between the side surface 1103 and the base 120. Therefore, the larger H2 is, the smaller H1 becomes, and the smaller the included angle H2 between the side surface 1103 and the base 120 is, the higher the covering effect of the side surface 1103 by the protective layer 140 is, and the less likely the conductive line 110 is to be exposed. In some embodiments of the present disclosure, by setting the included angle H1 between the main surface 1102 and the side surface 1103 to be 105° or more, the included angle H 2 between the side surface 1103 and the base 120 can be 75° or less, and it is possible to avoid the included angle between the side surface 1103 and the base 120 becoming too large (for example, larger than 75°). Thereby, the covering effect of the side surface 1103 by the protective layer 140 can be ensured, the occurrence rate of the exposure of the conductive line 110 can be reduced, and the abnormal growth phenomenon can be reduced.

[0273] In some embodiments of the present disclosure, by setting the included angle H1 between the main surface 1102 and the side surface 1103 to be 145° or less, it is possible to avoid the process difficulty being relatively large due to H1 becoming too large (for example, larger than 145°).

[0274] In some examples, the included angle H1 between the main surface 1102 and the side surface 1103 is 115° or more and 140° or less.

[0275] As further shown in FIG. 9A, in some embodiments, among the plurality of side surfaces 1103, at least two side surfaces 1103 with a relatively short distance from the conductive pad 131 of the conductive line 110 are the first side surfaces 1103A, and the two first side surfaces 1103A are connected by a curved surface in between.

[0276] In some examples, one conductive line 110has two first side surfaces 1103A that are relatively close to the conductive pad 131. The distance between the two first side surfaces 1103A and the edge of the conductive pad 131 is smaller than the distance between the other side surfaces 1103 and the edge of the conductive pad 131. Note that the distances between the two first side surfaces 1103A and the edge of the conductive pad 131 may or may not be equal.

[0277] As shown in FIG. 9A, all of the first side surfaces 1103A in the conductive line 110 where the first pole pad 131P is located and the first side surfaces 1103A in the conductive line 110 where the second pole pad 131N is located are positioned between the first pole pad 131P and the second pole pad 131N.

[0278] In some examples, all of the side surfaces 1103 to which both ends of the first side surface 1103A positioned between the first pole pad 131P and the second pole pad 131N are connected are the first side surfaces 1103A.

[0279] As shown in FIG. 9B, the two first side surfaces 1103A in the conductive line 110 where the power supply pad Pwr’ is located are respectively positioned between the power supply pad Pwr’ and the output pad Ot’, and between the power supply pad Pwr’ and the address pad Di’.

[0280] The two first side surfaces 1103A in the conductive line 110 where the output pad Ot’ is located are respectively positioned between the output pad Ot’ and the power supply pad Pwr’, and between the output pad Ot’ and the ground pad Gnd’.

[0281] The two first side surfaces 1103A in the conductive line 110 where the ground pad Gnd’ is located are respectively positioned between the ground pad Gnd’ and the output pad Ot’, and between the ground pad Gnd’ and the address pad Di’.

[0282] The two first side surfaces 1103A in the conductive line 110 where the address pad Di’ is located are respectively positioned between the address pad Di’ and the ground pad Gnd’, and between the address pad Di’ and the power supply pad Pwr’.

[0283] As shown in FIG. 12, when the source voltage line 112 passes through the gap between the ground pad Gnd’ and the output pad Ot’, the two first side surfaces 1103A on the conductive line 110 where the output pad Ot’ is located are respectively located between the output pad Ot’ and the ground pad Gnd’, and between the output pad Ot’ and the address pad Di’. The two first side surfaces 1103A on the conductive line 110 where the address pad Di’ is located are respectively located between the address pad Di’ and the output pad Ot’, and between the address pad Di’ and the power supply pad Pwr’. The two first side surfaces 1103A of the ground pad Gnd’ are respectively located between the ground pad Gnd’ and the power supply pad Pwr’, and between the ground pad Gnd’ and the output pad Ot’.

[0284] The two first side surfaces 1103A are connected by a curved surface, that is, the orthographic projection at the base 120 of the intersection of the two first side surfaces 1103A is the first fillet 1104 (as shown in FIGS. 9A and 9B) and the sharp edge of the conductive line 110 can be reduced. During the use of the backplane 1000, static electricity is likely to accumulate at the sharp edge. In some embodiments of the present disclosure, the two first side surfaces 1103A are connected by a curved surface. Thereby, the accumulation of static electricity in the conductive line 110 can be reduced.

[0285] In some embodiments As shown in FIGS. 9A and 9B, The radius R of the first fillet 1104 is 20 μm or more and 30 μm or less.

[0286] In some embodiments of the present disclosure, by setting the radius R of the first fillet 1104 to be 20 μm or more, it is possible to avoid the occurrence of a situation where the radius R of the first fillet 1104 is too small (for example, less than 20 μm) and the accumulation of static electricity cannot be effectively prevented. Thereby, the conductive line 110 can have a better effect of preventing static electricity accumulation.

[0287] Furthermore, the larger the radius R of the first fillet 1104 is, the closer the edge of the conductive pad 131 is to the edge of the first fillet 1104. In some embodiments of the present disclosure, by setting the radius R of the curved surface or the first fillet 1104 to 30 μm or less, it is possible to avoid the radius R of the first fillet 1104 being too large (for example, larger than 30 μm), and it is possible to avoid the distance between the edge of the conductive pad 131 and the edge of the first fillet 1104 from being too small.

[0288] The backplane 1000 provided by some embodiments of the present disclosure includes the wiring board 100 provided by some of the above embodiments. Therefore, the backplane 1000 provided by some embodiments of the present disclosure includes all the beneficial effects of the wiring board 100 provided by some of the above embodiments, and will not be repeatedly described here.

[0289] FIG. 14 is a structural diagram of a display device 2000 according to some embodiments.

[0290] As shown in FIG. 14, some embodiments of the present disclosure further provide a display device 2000. The display device 2000 includes a backlight module 500 and a liquid crystal display panel 600. The backlight module 500 is the backplane 1000 provided by some embodiments. The functional element 200 includes light-emitting diodes. The liquid crystal display panel 600 is located on the light-emitting side of the backlight module 500. The display device 2000 provided by some embodiments of the present disclosure includes all the beneficial effects of the backplane 1000 provided by some of the above embodiments, and will not be repeatedly described here.

[0291] It is understood that the display device 2000 may display moving image information such as videos and game screens, or may display still image information such as images and photos.

[0292] As shown in FIG. 14, in some embodiments, the main structure of the liquid crystal display panel 600 includes an array substrate 61, a counter substrate 62, and a liquid crystal layer 63 disposed between the array substrate 61 and the counter substrate 62.

[0293] Each sub-pixel of the array substrate 61 includes a thin film transistor 611 and a pixel electrode 612, both of which are located on the first base 610. The thin film transistor 611 includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulating layer. The source electrode and the drain electrode are each in contact with the active layer, and the pixel electrode 612 is electrically connected to the drain electrode of the thin film transistor 611. In some embodiments, the array substrate 61 further includes a common electrode 613 disposed on the first base 610. The pixel electrode 612 and the common electrode 613 may be disposed in the same layer. In this case, both the pixel electrode 612 and the common electrode 613 have a comb structure including a plurality of strip-shaped sub-electrodes. The pixel electrode 612 and the common electrode 613 may be disposed in different layers. In this case, as shown in FIG. 14, a first interlayer insulating layer 614 is disposed between the pixel electrode 612 and the common electrode 613. When the common electrode 613 is disposed between the thin film transistor 611 and the pixel electrode 612, as shown in FIG. 14, a second interlayer insulating layer 615 is further disposed between the common electrode 613 and the thin film transistor 611. In some other embodiments, the array substrate 61 does not include the common electrode 613. At this time, the common electrode 613 may be located in the counter substrate 62.

[0294] As shown in FIG. 14, the array substrate 61 further includes a planarization layer 616 disposed on a side away from the first base 610 of the thin film transistor 611 and the pixel electrode 612 electrode.

[0295] As shown in FIG. 14, the counter substrate 62 includes a color filter layer 621 disposed on the second substrate 620. In this case, the counter substrate 62 may also be referred to as a color filter substrate (abbreviation: CF). The color filter layer 621 includes at least a red photoresist unit, a green photoresist unit, and a blue photoresist unit, and the red photoresist unit, the green photoresist unit, and the blue photoresist unit are respectively aligned one-to-one with the sub-pixels on the array substrate 61. The counter substrate 62 further includes a black matrix pattern 622 disposed on the second base 620, and the black matrix pattern 622 is used to separate the red photoresist unit, the green photoresist unit, and the blue photoresist unit.

[0296] It is understood that light is emitted from the light-emitting side of the backlight module 500 and irradiated onto the liquid crystal layer 63. By adjusting the arrangement mode of the liquid crystal molecules in the liquid crystal layer 63, the intensity of the light transmitted through the liquid crystal layer 63 can be adjusted, and thus it plays a role in adjusting the intensity of the light irradiated onto the counter substrate 62. The counter substrate 62 includes a color filter layer 621. In this way, by adjusting the intensity of the light irradiated onto different color photoresist units, the display device 2000 can realize the display function of a color image.

[0297] As shown in FIG. 14, the liquid crystal display panel 600 further includes an upper polarizing plate 64 disposed on the side away from the liquid crystal layer 63 of the counter substrate 62, and a lower polarizing plate 65 disposed on the side away from the liquid crystal layer 63 of the array substrate 61.

[0298] FIG. 15 is a structural diagram of a display device 3000 according to some embodiments.

[0299] As shown in FIG. 15, some embodiments of the present disclosure further provide a display device 3000, which includes a display panel 700, and the display panel 700 includes the backplane 1000 provided by the above-mentioned some embodiments. The display device 3000 provided by some embodiments of the present disclosure includes all beneficial effects of the backplane 1000 provided by the above-mentioned some embodiments, and will not be repeatedly described herein.

[0300] It is understood that the display device 3000 may display moving image information such as videos and game screens, or may display still image information such as images and photos.

[0301] In some embodiments, the display device 3000 may be an LED display, a mini-LED display, a micro-LED display, etc. It is understood that the plurality of LED chips in the backplane 1000 are used to emit red light, green light, and blue light, so that the display device 3000 can realize color display.

[0302] FIG. 16 is a flowchart of a method for manufacturing a display substrate according to some embodiments of the present disclosure.

[0303] As shown in FIG. 16, some embodiments of the present invention further provide a method for manufacturing a wiring substrate used to form the wiring substrate 100 provided by the above-mentioned some embodiments. The method for manufacturing the wiring substrate includes the following steps S1 to S2.

[0304] S1, as shown in FIGS. 2A and 2B, form a conductive layer 130 on a base 120, the conductive layer 130 includes a plurality of pad groups 1300, and one pad group 1300 includes a plurality of conductive pads 131.

[0305] As shown in S2, FIGS. 2A and 2B, a protective layer 140 is formed on the side of the conductive layer 130 away from the base 120, an opening 141 is formed in the protective layer 140, and the portion of the conductive layer 130 exposed in the opening 141 is the conductive pad 131. The maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 is 30 times or less the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130.

[0306] Since L1≤30×L2, the maximum size L1 in the direction parallel to the base 120 of the conductive pad 131 is relatively small. Thereby, the consumption rate of Pd in the reaction region in the activation solution 2+ is made relatively small, and the diffusion rate of Pd 2+ in the solution can be made relatively small. The rate of depositing the palladium layer on the exposed step structure 1101 can be reduced, the rate of promoting the growth of the subsequent oxidation protection layer 170 and the conductive functional layer 180 can be reduced, and the occurrence of abnormal growth phenomena can also be reduced or avoided.

[0307] FIG. 17 is a flowchart of a method for manufacturing a display substrate according to some embodiments of the present disclosure. FIGS. 18 to 22 are process diagrams of a method for manufacturing a wiring substrate according to some embodiments.

[0308] As shown in FIG. 17, in some embodiments, the step of forming the conductive layer 130 on the base 120 in S1 includes the following steps S11 to S15.

[0309] S11, as shown in FIG. 18, deposit a conductive material on the base 120 to form an initial conductive layer 130'.

[0310] In step S11, the initial conductive layer 130' can be formed using a deposition process.

[0311] As shown in FIG. 18, before forming the initial conductive layer 130', a buffer layer 150 may be formed on one side of the base 120, and the initial conductive layer 130' is formed on the side of the buffer layer 150 away from the base 120.

[0312] S12. As shown in FIG. 19, a photoresist layer 190 is formed on the side of the base 120 of the initial conductive layer 130' away from the base 120.

[0313] S13. Bake the photoresist layer 190 at a predetermined temperature, where the predetermined temperature is 125°C or higher and 135°C or lower.

[0314] S14. As shown in FIG. 20, expose and develop the photoresist layer 190 to pattern the photoresist layer 190.

[0315] S15. As shown in FIG. 21, etch the initial conductive layer 130' based on the patterned photoresist layer 190 to form the conductive layer 130.

[0316] In some examples, the photoresist layer 190 includes a positive photoresist. As shown in FIG. 20, in step S14, after the photoresist layer 190 is exposed, the photoresist layer 190 irradiated with light (as shown in FIG. 19) is removed, whereby the photoresist layer 190 can be patterned to form a plurality of photoresist lines 190'.

[0317] After exposure and development, the cross-section of the photoresist line 190' is a frustum of a pyramid, that is, the line width of the photoresist line 190' gradually decreases along the first direction I1. As shown in FIG. 13, the direction indicated by the arrow I1 is the first direction. The direction indicated by the arrow I2 is the direction of the line width of the photoresist line 190'. The direction from the base 120 towards the initial conductive layer 130' is the first direction I1. The conductive layer 130 formed in step S15 includes a plurality of conductive lines 110, and the cross-section of the conductive line 110 presents a frustum of a pyramid.

[0318] In step S13, the higher the predetermined temperature, the higher the fluidity of the photoresist layer 190. After exposure and development, as shown in FIG. 20, the included angle H3 between the side surface 1901 and the bottom surface 1902 of the photoresist line 190' becomes smaller. Here, the bottom surface 1902 of the photoresist line 190' refers to the surface of the photoresist line 190' facing the base 120 of the photoresist line 190'. The side surface 1901 is connected to the bottom surface 1902.

[0319] In step S15, the initial conductive layer 130' is etched along the side surface 1901 of the photoresist line 190'. Therefore, as shown in FIG. 21, the included angles H2 and H3 between the side surface 1103 of the conductive line 110 formed in step S15 and the base 120 are substantially equal.

[0320] In some embodiments of the present disclosure, the predetermined temperature is 125°C or higher and 135°C or lower, and thus it is possible to avoid the predetermined temperature being too high (for example, exceeding 135°C). Thereby, the fluidity of the photoresist layer 190 can be increased, and as a result, after exposure and development, the included angle H3 between the side surface 1901 and the bottom surface 1902 of the photoresist line 190' can be reduced, and the included angle H2 between the conductive line 110 and the base 120 can be reduced. Thereby, the covering property of the conductive line 110 by the protective layer 140 can be made relatively good, so that the conductive line 110 is less likely to be exposed, and the abnormal growth phenomenon can be reduced.

[0321] Furthermore, the included angle H2 between the side surface 1103 of the conductive line 110 and the base 120 is complementary to the included angle H1 between the main surface 1102 and the side surface 1103, that is, H1 + H2 = 180°. Therefore, the smaller H2 is, the larger H1 is. Therefore, by setting the predetermined temperature to 135°C or lower, H1 can be made a larger value, and the edge of the conductive line 110 is less likely to form a stepped structure. Therefore, the covering property of the edge of the conductive line 110 by the protective layer 140 is relatively good, the edge of the conductive line 110 is less likely to be exposed, and thus the abnormal growth phenomenon can be reduced.

[0322] Otherwise, if the predetermined temperature is too low (e.g., less than 125°C), the fluidity of the photoresist layer 190 becomes excessive, and it is possible to avoid a relatively high process difficulty.

[0323] In some examples, the predetermined temperature is equal to 130°C.

[0324] In some examples, the included angle H1 between the main surface 1102 and the side surface 1103 of the conductive line 110 formed in step S15 is 105° or more and 145° or less.

[0325] Furthermore, the greater the thickness of the photoresist layer 190, the greater the included angle H2 between the side surface 1103 and the base 120. Exemplarily, when the thickness of the photoresist layer 190 is 7 μm, H2 is about 70°; when the thickness of the photoresist layer 190 is 3 - 4 μm, H2 is about 55°; and when the thickness of the photoresist layer 190 is 2 μm, H2 is about 40°.

[0326] Furthermore, after step S15, it further includes step S16 of removing the photoresist layer 190.

[0327] After step S16, step S2 can be executed.

[0328] In some embodiments, in the step of forming the protective layer 140 on the side of the conductive layer 130 away from the base 120, the protective layer 140 is formed through Chemical Vapor Deposition (CVD).

[0329] Since the protective layer 140 formed by Chemical Vapor Deposition has relatively high density, the coverage of the conductive layer 130 by the protective layer 140 can be improved, and thus the exposure of the conductive layer 130 can be reduced. Thereby, the abnormal growth phenomenon can be reduced.

[0330] In some other embodiments, the protective layer 140 can also be formed by physical vapor deposition (PVD).

[0331] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope of the present disclosure are all included within the technical scope of the present disclosure. Therefore, the protection scope of the present disclosure should follow the protection scope of the claims.

Claims

1. A base, A conductive layer located on one side of the base, the conductive layer includes a plurality of pad groups, and one pad group includes a plurality of conductive pads, A protective layer located on the side of the conductive layer away from the base, the protective layer includes a plurality of openings, and the part of the conductive layer exposed through the openings is the conductive pad, The maximum size of the conductive pad in the direction parallel to the base is 1.5 times or more and 30 times or less of the minimum distance between the edge of the conductive pad and the edge of the conductive layer, A wiring board.

2. The maximum size of the conductive pad in the direction parallel to the base is 0.5 to 5 times the distance between the conductive pad and the adjacent conductive pad, The wiring board according to Claim 1.

3. The maximum size of the conductive pad in the direction parallel to the base is 105 μm or more and 350 μm or less, The wiring board according to Claim 1 or 2.

4. The area of the conductive pad is 5000 μm ２ or more and 55000 μm ２ or less The wiring board according to any one of Claims 1 to 3.

5. In the same pad group, the distance between two adjacent conductive pads is 70 μm or more and 214 μm or less, The wiring board according to any one of Claims 1 to 4.

6. The conductive layer includes a plurality of conductive lines, and the part of the conductive line exposed through the opening is the conductive pad, The conductive line includes a main surface and a side surface connected to the main surface, and the main surface is the surface of the conductive line away from the base, The included angle between the main surface and the side surface is 105° or more and 145° or less, The wiring board according to any one of Claims 1 to 5.

7. The conductive layer includes a plurality of conductive lines, and the part of the conductive line exposed through the opening is the conductive pad, The conductive line includes a main surface and a plurality of side surfaces connected to the main surface, and the main surface is the surface of the conductive line away from the base, At least two of the plurality of side surfaces with a relatively short distance from the conductive pad of the conductive line are the first side surfaces, and the two first side surfaces are connected by a curved surface, The wiring board according to any one of Claims 1 to 6.

8. The orthographic projection of the curved surface on the base is a first fillet, and the radius of the first fillet is 20 μm or more and 30 μm or less, The wiring board according to Claim 7.

9. The wiring board includes a plurality of device regions, The plurality of pad groups include a plurality of first pad groups and one second pad group located in any one of the device regions. The first pad groups include first pole pads and second pole pads arranged at intervals. The second pad group includes at least a power supply pad, a ground pad, an address pad, and an output pad arranged at intervals, The wiring board further includes a source voltage line and a drive voltage line, In the same device region, the power supply pad is electrically connected to the source voltage line, the address pad is electrically connected to an output pad in another device region, and in the plurality of first pad groups, the first pole pad in the first first pad group is electrically connected to the drive voltage line, the second pole pad in the previous first pad group is electrically connected to the first pole pad in the next first pad group, and the second pole pad in the last first pad group is electrically connected to the output pad, The maximum size in the direction parallel to the base of at least one of the first pole pads, the power supply pad, and the ground pad in at least the first first pad group is 30 times or less the minimum distance between the edge of the pad and the edge of the conductive layer, The wiring board according to any one of claims 1 to 8.

10. The wiring board includes a plurality of sub-device regions and one control region, The plurality of pad groups include a plurality of first pad groups located in any one of the sub-device regions. The first pad groups include first pole pads and second pole pads arranged at intervals, The plurality of pad groups further include a second pad group located in the control region. The second pad group includes a power supply pad, a ground pad, an address pad, and an output pad, The wiring board further includes a source voltage line and a drive voltage line, The power supply pad is electrically connected to the source voltage line, In the same sub-device region, among the plurality of first pad groups, the first pole pad in the first first pad group is electrically connected to the drive voltage line, the second pole pad in the previous first pad group is electrically connected to the first pole pad in the next first pad group, and the second pole pad in the last first pad group is electrically connected to the output pad, The maximum size of the first electrode pad in at least the first pad group in a direction parallel to the base is 30 times or less the minimum distance between the edge of the first electrode pad and the edge of the conductive layer. The wiring board according to any one of claims 1 to 8.

11. The number of the conductive layers is two, The first conductive layer is located on one side of the base, and a part of the conductive line is located in the first conductive layer, The second conductive layer is located on the side away from the base of the first conductive layer, and the other part of the conductive line is located in the second conductive layer, One conductive line in the first conductive layer and at least one conductive line located in the second conductive layer are connected via a via hole, and the portion of the conductive line located in the second conductive layer and exposed at the opening is the conductive pad. The wiring board according to any one of claims 7 to 10.

12. An oxidation protection layer covering the side of the conductive pad away from the base, And a conductive functional part covering the side of the oxidation protection layer away from the base. The wiring board according to any one of claims 1 to 11.

13. A plurality of functional elements, At least one driving chip, A wiring board according to any one of claims 1 to 12, wherein the plurality of pad groups in the wiring board include a first pad group and a second pad group, the first pad group is connected to the functional element, and the second pad group is connected to the driving chip. Backplane.

14. A backlight module, wherein the backlight module is the backplane according to claim 13, and the functional element includes a light emitting diode. And a liquid crystal display panel located on the light emitting side of the backlight module. Display device.

15. Including a display panel, the display panel including the backplane according to claim 13. Display device.

16. A step of forming a conductive layer on a base, the conductive layer including a plurality of pad groups, and one pad group including a plurality of conductive pads. Forming a protective layer on the side of the conductive layer away from the base, and forming an opening in the protective layer, wherein the portion of the conductive layer exposed in the opening is the conductive pad, and the maximum size of the conductive pad in the direction parallel to the base is 30 times or less the minimum distance between the edge of the conductive pad and the edge of the conductive layer, and A method for manufacturing a wiring substrate. **Claim 17** The step of forming a conductive layer on the base includes Depositing a conductive material on the base to form an initial conductive layer, Forming a photoresist layer on the side of the initial conductive layer away from the base, Baking the photoresist layer at a predetermined temperature, where the predetermined temperature is 125°C or higher and 135°C or lower, Exposing and developing the photoresist layer to pattern the photoresist layer, Etching the initial conductive layer based on the patterned photoresist layer to form the conductive layer, and The method for manufacturing a wiring substrate according to claim 16. **Claim 18** In the step of forming a protective layer on the side of the conductive layer away from the base, the protective layer is formed through chemical vapor deposition. The method for manufacturing a wiring substrate according to claim 16 or 17.

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