Data processing method and data processing apparatus

Abstract

The data processing method includes the steps of separately performing inner code encoding on n first data streams to obtain n second data streams, where the n second data streams include n inner code codewords from the n second data streams, the n inner code codewords include n / m codeword sets, each of the codeword sets includes m inner code codewords, and each of the inner code codewords includes N bits; separately performing bit interleaving on the n / m codeword sets to obtain n / m target bit sets; separately mapping m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, and obtaining a total of n×N / L modulation symbols, where each L bits are mapped to one modulation symbol, the L bits in the modulation symbol are from L inner code codewords, and when the L bits in the modulation symbol are all from the information bits in the inner code codewords.

Description

Technical Field

[0001] This application claims priority to Chinese Patent Application No. 202210727137.1, titled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the China National Intellectual Property Administration on June 24, 2022, Chinese Patent Application No. 202210867882.6, titled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the China National Intellectual Property Administration on June 22, 2022, and Chinese Patent Application No. 202310382561.1, titled "DATA PROCESSING METHOD AND DATA PROCESSING APPARATUS", filed with the China National Intellectual Property Administration on April 4, 2023, and the entire contents of all of these are incorporated herein by reference.

[0002] This application relates to the field of communications, and more particularly, to a data processing method and a data processing apparatus.

Background Art

[0003] Continuously promoted by 5G, cloud computing, big data, artificial intelligence, etc., high-speed optical transmission networks are developing towards large capacity, packetization, and intelligence. Implementing forward error correction (FEC) encoding on the data transmitted for error correction can solve the problem of transmission bit errors in order to restore the original data transmitted by the transmitter from the received data.

[0004] Currently, a concatenated FEC transmission strategy has been proposed. The transmitter device and the transmitter processing module are connected through an attachment unit interface (AUI). The transmitter device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitter processing module. The transmitter processing module then performs a second FEC encoding on the first FEC-encoded data, performs modulation and mapping on the second FEC-encoded bit sequence to generate a corresponding modulation symbol sequence, and finally sends the generated symbol sequence to the receiver through an optical transmission network. The receiver may obtain the information transmitted by the transmitter by demodulating and decoding the received modulation symbol sequence.

[0005] Generally, in order to improve the error correction performance of the entire FEC strategy, concatenated encoding and interleaving are performed before the second FEC encoding, and the order of the first FEC-encoded data is scrambled. In addition, in the actual transmission process of the modulation symbol sequence, the transmission link is affected by the burst factor. As a result, errors occur in some consecutive symbols in the modulation symbol sequence, and the receiver receives the modulation symbol sequence affected by the burst factor. Because there are a large number of consecutive errors, it is difficult to accurately perform error correction through FEC encoding. As a result, the bit error rate of information transmission is high.

Summary of the Invention

Means for Solving the Problems

[0006] Embodiments of this application provide a data processing method and a data processing device so that the concatenated FEC transmission strategy has a strong burst tolerance ability and can be applied to a large number of transmission scenarios, especially actual coherent transmission scenarios where there is colored noise on the channel.

[0007] According to a first aspect, the present application provides a data processing method. This method includes the following steps. First, inner coding is separately performed on n first data streams to obtain n second data streams, outer coding is performed on all of the n first data streams, both inner coding and outer coding are FEC coding, the n second data streams include at least n inner codewords, the n inner codewords are from the n second data streams, the n inner codewords include n / m codeword sets, each codeword set includes m inner codewords, each of the inner codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. Then, bit interleaving is separately performed on the n / m codeword sets to obtain n / m target bit sets, each of the target bit sets includes m×N bits. Further, the m×N bits in each of the target bit sets are separately mapped to obtain m×N / L modulation symbols, and a total of n×N / L modulation symbols are obtained, with each L bits mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are from the L inner codewords. When all of the L bits mapped to the modulation symbol are from the information bits in the inner codewords, any two of the L bits mapped to the modulation symbol are from two different positions in two different inner codewords.

[0008] In this implementation form, a concatenated FEC transmission strategy is used. That is, outer coding and inner coding are sequentially performed on the data stream. Based on this, the present application designs a bit interleaving and mapping method such that both the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to modulation symbols. In this way, this concatenated FEC transmission strategy has a strong burst tolerance ability. In particular, short burst errors can be directly corrected through inner decoding. This concatenated FEC transmission strategy is widely applicable to transmission scenarios, especially actual coherent transmission scenarios where there is colored noise on the channel.

[0009] In some possible implementation forms, N is divisible by L, N bits in each inner codeword are mapped to N modulation symbols, N bits in the inner codeword include L first bit subsets, bits in the same first bit subset are separately mapped to the same bit in different modulation symbols, and bits in different first bit subsets are separately mapped to different bits in different modulation symbols. For example, one modulation symbol includes bits b0, b1, …, and bit b L-1 which are among the N bits in the inner codeword, and the amount of bits mapped to bits b0, b1, …, and bit b L-1 is all N / L. It should be understood that the probability of an error occurring in L bits during transmission is not necessarily equal. Since the bits in one inner codeword are more evenly mapped to modulation symbols, the burst tolerance ability of the concatenated FEC strategy in actual transmission can be improved.

[0010] In some possible implementations, obtaining a target bit set by performing bit interleaving on a codeword set includes the following. A first position transformation is performed on K information bits in each inner codeword in the codeword set to obtain a first bit set. A second position transformation is performed on the bits at the same positions in the first bit set to obtain the target bit set. For example, the codeword set is represented as a bit matrix. The first position transformation may be understood as performing a position transformation on the bits in each row, and the second position transformation may be understood as performing a position transformation on the bits in each column. This implementation provides a specific implementation of bit interleaving such that this approach has strong burst resistance capabilities.

[0011] In some possible implementations, performing a first position transformation on K information bits in each inner codeword in the codeword set includes performing a left circular shift or a right circular shift on K information bits in each inner codeword in the codeword set. This implementation provides a specific implementation of the first position transformation and has good practical effects.

[0012] In some possible implementations, both the codeword set and the first bit set are represented as bit matrices, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, the one-dimensional array includes m×N bits, and the bits at the same positions in the first bit set are the entire m bits in one column in the bit matrix corresponding to the first bit set.

[0013] In some possible implementations, the first position transformation satisfies a first condition, and the first condition is

[0014]

Number

[0015] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the first position transformation has not been performed, H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the first position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0 ≤ i < m.

[0016] In some possible implementations, each same position in the first bit set includes m / L second bit subsets, each second bit subset includes L bits, and the fact that the second position transformation is performed on the bits at the same position in the first bit set includes that an upward cyclic shift or a downward cyclic shift is performed on the m / L second bit subsets at each same position in the first bit set. This implementation provides a specific implementation form of the second position transformation and has good practical effects.

[0017] In some possible implementations, the second position transformation satisfies a second condition, and the second condition

[0018]

Number

[0019] including, where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation,

[0020]

Number

[0021] represents truncation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, θ is a non-zero integer greater than -L and less than L, 0 ≤ i < m, and 0 ≤ j < N.

[0022] In some possible implementations, the second position transformation satisfies a third condition, and the third condition is

[0023]

Number

[0024] where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, and H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation,

[0025]

Number

[0026] represents truncation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≦ i < m, and 0 ≦ j < N.

[0027] In some possible implementations, the second position transformation satisfies a fourth condition, and the fourth condition is H3[i][j]=H2[i^(j%L)][j] where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, and H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≦ i < m, and 0 ≦ j < N.

[0028] In some possible implementations, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes bits of m rows and N columns, and the one-dimensional array includes m×N bits.

[0029] In some possible implementations, the target bit set is a bit matrix, the bit interleaving satisfies a fifth condition, and the fifth condition is

[0030]

Number

[0031] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where bit interleaving is not performed, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through bit interleaving, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K,

[0032]

Number

[0033] represents floor, θ is a non-zero integer greater than -L and less than L, and 0≦i<m.

[0034] In some possible implementations, the target bit set is a one-dimensional array, the bit interleaving satisfies a sixth condition, and the sixth condition is

[0035]

Number

[0036] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix without bit interleaving, A[t] represents the t-th bit in the one-dimensional array obtained through bit interleaving, 0 ≦ t < m×N, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K,

[0037] [Number]

[0038] represents truncation, θ is a non-zero integer greater than -L and less than L, and 0 ≦ i < m.

[0039] In some possible implementations, the target bit set is a bit matrix, and the bit interleaving satisfies the seventh condition, and the seventh condition is

[0040] [Number]

[0041] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix without bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through bit interleaving, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, and 0 ≦ i < m.

[0042] In some possible implementations, the target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, and the eighth condition is

[0043] [Number]

[0044] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where bit interleaving is not performed, A[t] represents the t-th bit in the one-dimensional array obtained through bit interleaving, 0 ≦ t < m×N, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, and 0 ≦ i < m.

[0045] In some possible implementations, mapping the m×N bits in each target bit set to obtain m×N / L modulation symbols includes mapping each L consecutive bits at the same position in each target bit set to one modulation symbol to obtain m×N / L modulation symbols.

[0046] In some possible implementations, the modulation symbol stream includes the m×N / L modulation symbols obtained through mapping. The m / L modulation symbols obtained through mapping of m bits at the same position in each target bit set are consecutive in the modulation symbol stream. When the target bit set is represented as a bit matrix, the m bits at the same position in the target bit set are the m bits in one column in the bit matrix. Or when the target bit set is represented as a one-dimensional array, the m bits at the same position in the target bit set are m consecutive bits in the one-dimensional array.

[0047] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained through mapping, each target bit set is represented as a bit matrix including m rows and N columns of bits, m bits in one column among each target bit set are mapped to obtain m / L first modulation symbols, and each T consecutive first modulation symbols among the m / L first modulation symbols are consecutive in the modulation symbol stream; m bits in another column among each target bit set are mapped to obtain m / L second modulation symbols, and each T consecutive second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream, and that column is adjacent to another column; T consecutive first modulation symbols among the m / L first modulation symbols and T consecutive second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T.

[0048] In some possible implementations, for all of the n first data streams, alignment marker lock and lane deskew processing are performed for all of the n first data streams, and when all of the W×L bits among W consecutive modulation symbols are information bits in the inner codeword, the W×L bits are from more than two outer codewords obtained through outer coding, and W≧2.

[0049] In some possible implementations, each modulation symbol is a differential phase shift keying quadrature amplitude modulation (DP-16QAM) modulation symbol, and each modulation symbol includes 8 bits, or each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, and each modulation symbol includes 2 bits.

[0050] According to a second aspect, the present application provides a data processing method. The method includes the following steps. First, inner coding is separately performed on n first data streams to obtain n second data streams, outer coding is performed on all of the n first data streams, both the inner coding and the outer coding are FEC coding, the n second data streams include at least n inner codewords, the n inner codewords are from the n second data streams, the n inner codewords include n / m codeword sets, each codeword set includes m inner codewords, each of the inner codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. Next, bit interleaving is separately performed on the n / m codeword sets to obtain n / m target bit sets, each of the target bit sets includes m×N bits, and the bit interleaving includes performing a position transformation on the K information bits in each of the inner codewords in the codeword sets. Further, the m×N bits in each of the target bit sets are separately mapped to obtain m×N / L modulation symbols, and a total of n×N / L modulation symbols are obtained, with each L bits being mapped to one modulation symbol, m is divisible by L, the L bits mapped to the modulation symbol are from L r inner codewords, and the L r bits in each of the L c inner codewords are mapped to the modulation symbol, and the 2L bits mapped to two consecutive modulation symbols are from 2L r inner codewords, where L = L r ×L c and L c > 1.

[0051] In some possible implementations, performing the position transformation on the K information bits in each of the inner codewords in the codeword sets includes performing a left cyclic shift or a right cyclic shift on the K information bits in each of the inner codewords in the codeword sets.

[0052] In some possible implementations, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes bits of m rows and N columns, and the one-dimensional array includes m×N bits.

[0053] In some possible implementations, the position transformation satisfies a target condition, and the target condition

[0054]

Number

[0055] includes, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the position transformation has not been performed, H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≦i<m.

[0056] In some possible implementations, each target bit set includes bits of m rows and N columns, and a total of L bits in each L r rows and L c columns are mapped to one modulation symbol.

[0057] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained through mapping, and m / L c modulation symbols obtained through the mapping of each L r columns in the target bit set are consecutive in the modulation symbol stream, and m×N / L modulation symbols obtained through the mapping of each N columns of bits in the target bit set are consecutive in the modulation symbol stream.

[0058] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained through mapping, and L bits in each of the L columns in each target bit set are mapped to obtain m / L first modulation symbols, and each of the T consecutive first modulation symbols in the m / L first modulation symbols is consecutive in the modulation symbol stream. L bits in each of the other L columns in each target bit set are mapped to obtain m / L second modulation symbols, and each of the T consecutive second modulation symbols in the m / L second modulation symbols is consecutive in the modulation symbol stream. The L columns are adjacent to the other L columns, and the T consecutive first modulation symbols in the m / L first modulation symbols and the T consecutive second modulation symbols in the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T. c bits in each of the L columns are mapped to obtain m / L r first modulation symbols, and m / L r each of the T consecutive first modulation symbols in the m / L first modulation symbols is consecutive in the modulation symbol stream. L bits in each of the other L columns in each target bit set are mapped to obtain m / L c second modulation symbols, and m / L r each of the T consecutive second modulation symbols in the m / L second modulation symbols is consecutive in the modulation symbol stream. L r columns are adjacent to the other L c columns, and m / L c each of the T consecutive first modulation symbols in the m / L first modulation symbols and each of the T consecutive second modulation symbols in the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L r is divisible by T. r is divisible by T. r is divisible by T.

[0059] In some possible implementations, each modulation symbol is a dual-polarization quadrature amplitude modulation (DP-16QAM) modulation symbol, and each modulation symbol includes 8 bits, or each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, and each modulation symbol includes 2 bits.

[0060] According to a third aspect, the present application provides a data processing apparatus. The data processing apparatus includes an encoding module, a bit interleaving module, and a bit mapping module. The encoding module is configured to separately perform inner code codewords on n first data streams to obtain n second data streams, outer code encoding is performed on all of the n first data streams, both inner code encoding and outer code encoding are forward error correction (FEC) encoding, the n second data streams include at least n inner code codewords, the n inner code codewords are from the n second data streams, the n inner code codewords include n / m codeword sets, each codeword set includes m inner code codewords, each of the inner code codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. The bit interleaving module is configured to separately perform bit interleaving on the n / m codeword sets to obtain n / m target bit sets, each of the target bit sets includes m×N bits. The bit mapping module is configured to map the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, and to obtain a total of n×N / L modulation symbols, with each L bits mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are from L inner code codewords. When all of the L bits mapped to the modulation symbol are from the information bits in the inner code codewords, any two of the L bits mapped to the modulation symbol are from two different positions in two different inner code codewords.

[0061] In some possible implementations, N is divisible by L, the N bits in each inner codeword are mapped to N modulation symbols, the N bits in the inner codeword include L first-bit subsets, the bits in the same first-bit subset are separately mapped to the same bits in different modulation symbols, and the bits in different first-bit subsets are separately mapped to different bits in different modulation symbols.

[0062] In some possible implementations, the bit mapping module is specifically configured to perform a first position transformation on the K information bits in each inner codeword in the codeword set to obtain a first bit set, and perform a second position transformation on the bits at the same position in the first bit set to obtain a target bit set.

[0063] In some possible implementations, the bit mapping module is specifically configured to perform a left circular shift or a right circular shift on the K information bits in each inner codeword in the codeword set.

[0064] In some possible implementations, both the codeword set and the first bit set are represented as bit matrices, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, the one-dimensional array includes m×N bits, and the bits at the same position in the first bit set are m bits in an entire column in the bit matrix corresponding to the first bit set.

[0065] In some possible implementations, the first position information meets a first condition, and the first condition is

[0066]

Number

[0067] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the first position transformation has not been performed, H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the first position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0 ≤ i < m.

[0068] In some possible implementations, each same position in the first bit set includes m / L second bit subsets, each second bit subset includes L bits, and the bit mapping module is configured to perform a cyclic shift up or a cyclic shift down on the m / L second bit subsets at each same position in the first bit set.

[0069] In some possible implementations, the second position information satisfies a second condition, and the second condition is

[0070]

Number

[0071] including, where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation,

[0072]

Number

[0073] represents truncation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, θ represents a non-zero integer greater than -L and less than L, 0 ≤ i < m, and 0 ≤ j < N.

[0074] In some possible implementations, the second position transformation satisfies a third condition, and the third condition is

[0075] [Number]

[0076] including, where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, and H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation.

[0077] [Number]

[0078] represents truncation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≤ i < m, and 0 ≤ j < N.

[0079] In some possible implementations, the second position transformation satisfies the fourth condition, and the fourth condition is H3[i][j]=H2[i^(j%L)][j] including, where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, and H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≤ i < m, and 0 ≤ j < N.

[0080] In some possible implementations, the symbol word set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes bits of m rows and N columns, and the one-dimensional array includes m×N bits.

[0081] In some possible implementations, the target bit set is a bit matrix, and the bit interleaving satisfies a fifth condition, and the fifth condition is

[0082]

Number

[0083] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where bit interleaving is not performed, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through bit interleaving, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K,

[0084]

Number

[0085] represents truncation, θ is a non-zero integer greater than -L and less than L, and 0≦i<m.

[0086] In some possible implementations, the target bit set is a one-dimensional array, and the bit interleaving satisfies a sixth condition, and the sixth condition is

[0087]

Number

[0088] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix without bit interleaving, A[t] represents the t-th bit in the one-dimensional array obtained through bit interleaving, 0 ≦ t < m×N, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K,

[0089]

Number

[0090] represents truncation, θ is a non-zero integer greater than -L and less than L, 0 ≦ i < m.

[0091] In some possible implementations, the target bit set is a bit matrix, and the bit interleaving satisfies the seventh condition, where the seventh condition

[0092]

Number

[0093] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix without bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through bit interleaving, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0 ≦ i < m.

[0094] In some possible implementations, the target bit set is a one-dimensional array, and the bit interleaving satisfies the eighth condition, where the eighth condition

[0095] [Number]

[0096] including, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where bit interleaving is not performed, A[t] represents the t-th bit in the one-dimensional array obtained through bit interleaving, 0 ≦ t < m × N, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, and 0 ≦ i < m.

[0097] In some possible implementations, the bit mapping module is specifically configured to map each L consecutive bits at the same position in each target bit set to one modulation symbol, thereby obtaining m × N / L modulation symbols.

[0098] In some possible implementations, the modulation symbol stream includes the m × N / L modulation symbols obtained through mapping. The m / L modulation symbols obtained through the mapping of m bits at the same position in each target bit set are consecutive in the modulation symbol stream. When the target bit set is represented as a bit matrix, the m bits at the same position in the target bit set are the m bits in one column of the bit matrix. Or when the target bit set is represented as a one-dimensional array, the m bits at the same position in the target bit set are m consecutive bits in the one-dimensional array.

[0099] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained through mapping, each target bit set is represented as a bit matrix including m rows and N columns of bits, m bits in one column of each target bit set are mapped to obtain m / L first modulation symbols, and T consecutive first modulation symbols among the m / L first modulation symbols are consecutive in the modulation symbol stream. m bits in another column of each target bit set are mapped to obtain m / L second modulation symbols, and T consecutive second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream, and that column is adjacent to another column. T consecutive first modulation symbols among the m / L first modulation symbols and T consecutive second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T.

[0100] In some possible implementations, for all of the n first data streams, alignment marker locking and lane deskewing processing are performed. When all of the W×L bits in W consecutive modulation symbols are information bits in the inner codeword, those W×L bits are from more than two outer codewords obtained through outer coding, and W≥2.

[0101] In some possible implementations, each modulation symbol is a DP-16QAM modulation symbol, and each modulation symbol includes 8 bits, or each modulation symbol is a PAM4 modulation symbol, and each modulation symbol includes 2 bits.

[0102] According to a fourth aspect, the present application provides a data processing apparatus. The data processing apparatus includes an encoding module, a bit interleaving module, and a bit mapping module. The encoding module is configured to separately perform inner code encoding on n first data streams to obtain n second data streams, outer code encoding is performed on all of the n first data streams, both the inner code encoding and the outer code encoding are forward error correction (FEC) encoding, the n second data streams include at least n inner code codewords, the n inner code codewords are from the n second data streams, the n inner code codewords include n / m codeword sets, each codeword set includes m inner code codewords, each of the inner code codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. The bit interleaving module is configured to separately perform bit interleaving on the n / m codeword sets to obtain n / m target bit sets, each of the target bit sets includes m×N bits, and the bit interleaving includes performing a position transformation on the K information bits in each of the inner code codewords in the codeword set. The bit mapping module is configured to map the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, and to obtain a total of n×N / L modulation symbols, with each L bits being mapped to one modulation symbol, m is divisible by L, the L bits mapped to the modulation symbol are from L r inner code codewords, and the L r bits in each of the L c inner code codewords are mapped to the modulation symbol, and the 2L bits mapped to two consecutive modulation symbols are from 2L r inner code codewords, where L = L r ×L c and L c > 1.

[0103] In some possible implementations, the bit interleaving module is configured to perform a left circular shift or a right circular shift on K information bits in each inner codeword in the codeword set.

[0104] In some possible implementations, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes m×N bits.

[0105] In some possible implementations, the position transformation satisfies a target condition, and the target condition

[0106]

Number

[0107] includes, where H1[i][j] represents the bit in the i-th row and the j-th column in the bit matrix where the position transformation has not been performed, H2[i][j] represents the bit in the i-th row and the j-th column in the bit matrix obtained through the position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≦i<m.

[0108] In some possible implementations, each target bit set includes m rows and N columns of bits, and all L bits in each L r rows and L c columns in the target bit set are mapped to one modulation symbol.

[0109] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained through mapping, and m / L c obtained through the mapping of each L rIndividual modulation symbols are consecutive in the modulation symbol stream, and m×N / L modulation symbols obtained through the mapping of each N columns of bits in the target bit set are consecutive in the modulation symbol stream.

[0110] In some possible implementations, the modulation symbol stream includes m×N / L modulation symbols obtained through mapping, and L c bits in each column of each target bit set are mapped to obtain m / L r first modulation symbols, and each T consecutive first modulation symbols among the m / L r first modulation symbols are consecutive in the modulation symbol stream, and L c bits in each other column of each target bit set are mapped to obtain m / L r second modulation symbols, and each T consecutive second modulation symbols among the m / L r second modulation symbols are consecutive in the modulation symbol stream, and L c columns are adjacent to the other L c columns, and T consecutive first modulation symbols among the m / L r first modulation symbols and T consecutive second modulation symbols among the m / L r second modulation symbols are consecutive in the modulation symbol stream, and m / L r is divisible by T.

[0111] In some possible implementations, each modulation symbol is a DP-16QAM modulation symbol, each modulation symbol includes 8 bits, or each modulation symbol is a PAM4 modulation symbol, and each modulation symbol includes 2 bits.

[0112] According to a fifth aspect, the present application provides a data processing method. This method includes the following steps. First, for each of n1 first data streams among n0 first data streams, interleaving and encoding processes are separately performed to obtain one second data stream, and a total of n2 second data streams are obtained, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Next, each 2 bits among the n2 second data streams are separately mapped to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding processes include the following steps. a0 first bit sets are obtained from each of the n1 first data streams, and a total of m = n1 × a0 first bit sets are obtained. Outer encoding is performed on all of the n1 first data streams. Each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1. Inner encoding is separately performed on the m first bit sets to obtain m inner encoded codewords. Both the inner encoding and the outer encoding are forward error correction (FEC) encodings. Each of the inner encoded codewords includes one first bit set that participates in the inner encoding and has a total of N bits and one parity bit set. N = K + P, each parity bit set includes P bits, and P is an integer greater than or equal to 1. Cyclic shifts are separately performed on the m inner encoded codewords to obtain m third bit sets. Each of the third bit sets includes one parity bit set and one second bit set obtained by performing a cyclic shift on the first bit set. 2 bits are obtained from each of the third bit sets through round-robin to obtain a fourth bit set. The fourth bit set includes m × N bits. A total of m × K bits from the m second bit sets that are in the fourth bit set are consecutive, and a total of m × P bits from the m parity bit sets that are in the fourth bit set are consecutive.Each of the second data streams includes a plurality of fourth bit sets, and a total of m×N / 2 PAM4 symbols are obtained through the mapping of each of the fourth bit sets. It should be understood that the m×2 bits mapped to m consecutive PAM4 symbols among the m×N / 2 PAM4 symbols are from m inner code codewords.

[0113] In some possible implementations, outer coding is performed for each of the first data streams, and at least 10 PAM4 symbols are obtained through interleaving and coding processing and the mapping of 20 consecutive bits in the first data stream. Those 20 consecutive bits are from 2 outer code symbols in one outer code codeword, and any two of at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0114] In some possible implementations, the amount of bits of the cyclic shift performed for any two of the m first bit sets is different.

[0115] In some possible implementations, both the m inner code codewords and the m third bit sets are represented as bit matrices, and the bit matrices include m rows and N columns of bits.

[0116] In some possible implementations, the second bit set is obtained by performing a left cyclic shift of bits on the first bit set, and the left cyclic shift satisfies a first condition, and the first condition is

[0117]

Number

[0118] obtained by performing a left cyclic shift of bits, and the left cyclic shift satisfies a first condition, and the first condition is

[0119]

Number

[0120] including M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m inner code codewords for which no left circular shift has been performed, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m third bit sets obtained through a left circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ i < m, and

[0121]

Number

[0122] is satisfied.

[0123] In some possible implementations, the second bit set is obtained by performing a right circular shift of δ i bits with respect to the first bit set, and the right circular shift satisfies a second condition, where the second condition

[0124]

Number

[0125] including M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m inner code codewords for which no right circular shift has been performed, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m third bit sets obtained through a right circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ i < m, and 0 ≤ δ i < K is satisfied.

[0126] In some possible implementations, the m third bit sets and the fourth bit set satisfy a third condition, where the third condition

[0127]

Number

[0128] including, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m third bit sets,

[0129]

Number

[0130] is the

[0131]

Number

[0132] bit in the fourth bit set, where 0 ≦ 1 < m and 0 ≦ j < N,

[0133]

Number

[0134] represents the floor operation.

[0135] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a left circular shift of

[0136]

Number

[0137] the bits of the i-th first bit set, where 0 ≦ i < 8,

[0138]

Number

[0139] The value of

[0140]

Number

[0141] satisfies any one of the items of the first value, and the item of the first value

[0142]

Number

[0143] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} is included.

[0144] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ i bits on the i-th first bit, where 0 ≤ i < 8, and δ i The value of satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the item of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} is {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} including

[0145] According to the sixth aspect, the present application provides a data processing method. This method includes the following steps. First, for each of the n1 first data streams among the n0 first data streams, interleaving and encoding processes are separately performed to obtain one second data stream, and a total of n2 second data streams are obtained, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Next, each 2 bits among the n2 second data streams are separately mapped to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding processes include the following steps. a0 first bit sets are obtained from each of the n1 first data streams, and a total of m = n1 × a0 first bit sets are obtained. Outer encoding is performed on all of the n1 first data streams. Each of the first bit sets contains K bits, and n1, a0, and K are all integers greater than 1. Circular shifts are separately performed on the m first bit sets to obtain m second bit sets, and inner encoding is separately performed on the m first bit sets to obtain m parity bit sets. Both the inner encoding and the outer encoding are forward error correction (FEC) encoding. Each of the second bit sets contains K bits, and each of the parity bit sets contains P bits, where P is an integer greater than or equal to 1. 2 bits are obtained from each of the second bit sets through round robin to obtain a total of m × K consecutive bits, 2 bits are obtained from each parity bit set through round robin to obtain a total of m × P consecutive bits, and a third bit set containing m × N bits is obtained, where N = K + P.Each second data stream includes a plurality of third bit sets, each of the third bit sets including m×K bits in the second bit set and m×P bits in the parity bit set, with a total of m×K / 2 PAM4 symbols obtained through the mapping of the m×K bits in each of the third bit sets from the second bit set, and a total of m×P / 2 PAM4 symbols obtained through the mapping of the m×P bits in each of the third bit sets from the parity bit set, and it should be understood that the m×2 bits mapped to m consecutive PAM4 symbols out of a total of m×N / 2 PAM4 symbols are from m second bit sets and / or m parity bit sets.

[0146] In some possible implementations, outer coding is performed for each of the first data streams, with at least 10 PAM4 symbols obtained through interleaving and coding processes and the mapping of 20 consecutive bits in the first data stream, where the 20 consecutive bits are from 2 outer code symbols in one outer codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0147] In some possible implementations, the amount of bits of the cyclic shift performed for any two of the m first bit sets is different.

[0148] In some possible implementations, both the m first bit sets and the m second bit sets are represented as bit matrices, and the bit matrices include m rows and K columns of bits.

[0149] In some possible implementations, the second bit set is relative to the first bit set

[0150]

Number

[0151] Obtained by performing a left circular shift of bits, the left circular shift satisfies a first condition, and the first condition is

[0152] [Number]

[0153] including, where M1[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m first bit sets where no left circular shift is performed, M2[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m second bit sets obtained through the left circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ j < K, 0 ≤ i < m,

[0154] [Number]

[0155] and

[0156] In some possible implementations, the second bit set is δ i Obtained by performing a right circular shift of bits, the right circular shift satisfies a second condition, and the second condition is M2[i][j]=M1[i][(j - δ i )%K] including, where M1[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m first bit sets where no right circular shift is performed, M2[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m second bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ j < K, 0 ≤ i < m, 0 ≤ δ i < K

[0157] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a left circular shift of bits on the i-th first bit set, where 0 ≤ i < 8,

[0158]

Number

[0159] and the value of

[0160]

Number

[0161] satisfies any one of the items of the first value, and the item of the first value

[0162]

Number

[0163] satisfies any one of the following, and the item of the first value

[0164]

Number

[0165] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} and includes.

[0166] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8, and the value of δ satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} are i obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8, and i the value of δ satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} are {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} and include.

[0167] According to a seventh aspect, the present application provides a data processing method. This method includes the following steps. First, for each of n1 first data streams among n0 first data streams, interleaving and encoding processes are separately performed to obtain one second data stream, and a total of n2 second data streams are obtained, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Next, each 2 bits among the n2 second data streams are separately mapped to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding processes include the following steps. a0 first bit sets are obtained from each of the n1 first data streams, and a total of m = n1 × a0 first bit sets are obtained. Outer encoding is performed on all of the n1 first data streams. Each of the first bit sets contains K bits, and n1, a0, and K are all integers greater than 1. Circular shifts are separately performed on the m first bit sets to obtain m second bit sets, and each of the second bit sets contains K bits. Inner encoding is separately performed on the m second bit sets to obtain m inner encoded words. Both the inner encoding and the outer encoding are forward error correction (FEC) encodings. Each of the inner encoded words contains one second bit set that participates in the inner encoding and has a total of N bits and one parity bit set, where N = K + P. Each parity bit set contains P bits, and P is an integer greater than or equal to 1. 2 bits are obtained from each inner encoded word through round-robin to obtain a third bit set. The third bit set contains m × N bits. A total of m × K bits in the third bit set from the m second bit sets are consecutive, and a total of m × P bits in the third bit set from the m parity bit sets are consecutive.Each second data stream includes a plurality of third bit sets, and a total of m×N / 2 PAM4 symbols are obtained through the mapping of each of the third bit sets. It should be understood that m×2 bits mapped to m consecutive PAM4 symbols among the m×N / 2 PAM4 symbols are from m inner code codewords.

[0168] In some possible implementations, outer coding is performed for each of the first data streams, and at least 10 PAM4 symbols are obtained through interleaving and coding processing and the mapping of 20 consecutive bits in the first data stream. The 20 consecutive bits are from 2 outer code symbols in one outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0169] In some possible implementations, the amount of bits of the cyclic shift performed for any two of the m first bit sets is different.

[0170] In some possible implementations, both the m first bit sets and the m second bit sets are represented as bit matrices, and the bit matrices include bits in m rows and K columns.

[0171] In some possible implementations, the second bit set is obtained by performing a left cyclic shift of bits on the first bit set, and the left cyclic shift satisfies a first condition, and the first condition is

[0172]

Number

[0173] obtained by performing a left cyclic shift of bits, and the left cyclic shift satisfies a first condition, and the first condition is

[0174]

Number

[0175] including, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m first bit sets where no left circular shift is performed, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m second bit sets obtained through left circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≦ i < m, 0 ≦ j < K,

[0176]

Number

[0177] and it is.

[0178] In some possible implementations, the second bit set is obtained by performing a right circular shift of δ i bits on the first bit set, and the right circular shift satisfies the second condition, where the second condition is M2[i][j] = M1[i][(j - δ i )%K] including, M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m first bit sets where no right circular shift is performed, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m second bit sets obtained through right circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≦ i < m, 0 ≦ j < K, 0 ≦ δ i < K.

[0179] In some possible implementations, the m inner code codewords are represented as a bit matrix including m rows and N columns, and the m inner code codewords and the third bit set satisfy the third condition, where the third condition is

[0180]

Number

[0181] including M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner codewords,

[0182]

Number

[0183] is the

[0184]

Number

[0185] bit in the third bit set, where 0 ≤ i < m and 0 ≤ j < N,

[0186]

Number

[0187] represents the floor operation.

[0188] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a left circular shift of

[0189]

Number

[0190] bits with respect to the i-th first bit set, where 0 ≤ i < 8,

[0191]

Number

[0192] the value of is the item of the first value

[0193]

Number

[0194] satisfies any one of them, and the item of the first value

[0195]

Number

[0196] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} includes.

[0197] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits with respect to the i-th first bit, where 0 ≤ i < 8, and δ i is obtained by performing a right circular shift of δ bits, where 0 ≤ i < 8, and δ i satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the item of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} is {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} includes

[0198] According to an eighth aspect, the present application provides a data processing method. This method includes the following steps. First, interleaving and encoding processes are separately performed on each of n1 first data streams among n0 first data streams to obtain one second data stream, and a total of n2 second data streams are obtained, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Next, each 2 bits among the n2 second data streams are separately mapped to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding processes include the following steps. a0 first bit sets are obtained from each of the n1 first data streams, and a total of m = n1 × a0 first bit sets are obtained. Outer code encoding is performed on all of the n1 first data streams. Each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1. Inner code encoding is separately performed on the m first bit sets to obtain m inner code codewords. Both the inner code encoding and the outer code encoding are forward error correction (FEC) encodings. Each of the inner code codewords includes one first bit set that participates in the inner code encoding and has a total of N bits and one parity bit set, where N = K + P. Each parity bit set includes P bits, and P is an integer greater than or equal to 1. The m inner code codewords are separately interleaved to obtain one second bit set. The second bit set includes m × N bits. The

[0199]

Number

[0200] bits satisfy the first condition or the second condition, where 0 ≤ i < m and 0 ≤ j < N.

[0201] The first condition is

[0202] [Number]

[0203] including

[0204] [Number]

[0205] is the

[0206] [Number]

[0207] bit in the second bit set,

[0208] [Number]

[0209] is the

[0210] [Number]

[0211] bit in the ith inner codeword, and C i [j] represents the jth bit in the ith inner codeword.

[0212] The second condition is

[0213] [Number]

[0214] including

[0215]

Number

[0216] represents the bit in the second bit set, where the

[0217]

Number

[0218] bit, and C i [(j - δ i ) % K] represents the bit at position ((j - δ i ) % K) in the i-th inner codeword, and C i [j] represents the bit at position j in the i-th inner codeword.

[0219] Each second data stream includes a plurality of second bit sets. In total, m × N / 2 PAM4 symbols are obtained through the mapping of each second bit set. It should be understood that the m × 2 bits mapped to m consecutive PAM4 symbols among the m × N / 2 PAM4 symbols are from m inner codewords.

[0220] In some possible implementations, K = 120 and m = 8,

[0221]

Number

[0222] the value satisfies any one of the items of the first value

[0223]

Number

[0224] and the items of the first value

[0225]

Number

[0226] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} and includes δ i where the value of δ satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} are {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} and includes

[0227] According to a ninth aspect, the present application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bitmapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processing on each of n1 first data streams in n0 first data streams to obtain one second data stream, and to obtain a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bitmapping module is configured to separately map each 2 bits in the n2 second data streams to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams.The interleaving and encoding module, in particular, obtains a0 first bit sets from each of n1 first data streams, obtaining a total of m = n1 × a0 first bit sets in total, and the outer coding is performed on all of the n1 first data streams. Each of the first bit sets contains K bits, where n1, a0, and K are all integers greater than 1. Inner coding is performed separately on the m first bit sets to obtain m inner coded words. Both the inner coding and the outer coding are forward error correction (FEC) coding. Each of the inner coded words contains one first bit set that participates in the inner coding and has a total of N bits and one parity bit set, where N = K + P. Each parity bit set contains P bits, and P is an integer greater than or equal to 1. A cyclic shift is performed separately on the m inner coded words to obtain m third bit sets. Each of the third bit sets contains one parity bit set and one second bit set obtained by performing a cyclic shift on the first bit set. A fourth bit set is obtained through a 2-bit round robin in each of the third bit sets. The fourth bit set contains m × N bits. A total of m × K bits from the m second bit sets that are in the fourth bit set are consecutive, and a total of m × P bits from the m parity bit sets that are in the fourth bit set are consecutive. The second data stream is configured to contain a plurality of fourth bit sets, and a total of m × N / 2 PAM4 symbols are obtained through the mapping of each of the fourth bit sets. It should be understood that m × 2 bits mapped to m consecutive PAM4 symbols among the m × N / 2 PAM4 symbols are from the m inner coded words.

[0228] In some possible implementations, outer coding is performed for each of the first data streams, and at least 10 PAM4 symbols are obtained through interleaving and coding processes and mapping of 20 consecutive bits in the first data stream, where the 20 consecutive bits are from two outer code symbols in one outer codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0229] In some possible implementations, the amount of bits of the cyclic shift performed for any two of the m first bit sets is different.

[0230] In some possible implementations, both the m inner codewords and the m third bit sets are represented as bit matrices, and the bit matrices include bits of m rows and N columns.

[0231] In some possible implementations, the second bit set is obtained by performing a left cyclic shift of bits on the first bit set, and the left cyclic shift satisfies a first condition, where the first condition

[0232]

Number

[0233] includes M,

[0234]

Number

[0235] and M C[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m inner code codewords for which no left circular shift has been performed, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m third bit sets obtained through a left circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ i < m,

[0236] [Number]

[0237] and

[0238] In some possible implementations, the second bit set is obtained by performing a right circular shift of δ i bits on the first bit set, the right circular shift satisfies a second condition, and the second condition

[0239] [Number]

[0240] includes, M C [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m inner code codewords for which no right circular shift has been performed, M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m third bit sets obtained through a right circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ i < m, and 0 ≤ δ i < K.

[0241] In some possible implementations, the m third bit sets and the fourth bit set satisfy a third condition, and the third condition

[0242] [Number]

[0243] including, where M3[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m third bit sets,

[0244] [Number]

[0245] is the

[0246] [Number]

[0247] bit in the fourth bit set, where 0 ≤ i < m and 0 ≤ j < N,

[0248] [Number]

[0249] represents the floor operation.

[0250] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a left circular shift of

[0251] [Number]

[0252] bits with respect to the i-th first bit set, where 0 ≤ i < 8,

[0253] [Number]

[0254] the value of is the item of the first value

[0255] [Number]

[0256] satisfies any one of them, and the item of the first value

[0257] [Number]

[0258] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} includes.

[0259] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ i bits on the i-th first bit, where 0 ≤ i < 8, and the value of δ i satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the item of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} is {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} includes.

[0260] According to the 10th aspect, the present application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bitmapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processes on each of n1 first data streams out of n0 first data streams to obtain one second data stream, and to obtain a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bitmapping module is configured to separately map each of 2 bits in the n2 second data streams to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. The interleaving and encoding module specifically obtains a0 first bit sets from each of the n1 first data streams, obtaining a total of m = n1 × a0 first bit sets, performing outer code encoding on all of the n1 first data streams, each of the first bit sets containing K bits, where n1, a0, and K are all integers greater than 1, separately performing a cyclic shift on the m first bit sets to obtain m second bit sets, separately performing inner code encoding on the m first bit sets to obtain m parity bit sets, both the inner code encoding and the outer code encoding being forward error correction (FEC) encoding, each of the second bit sets containing K bits, each of the parity bit sets containing P bits, where P is an integer greater than or equal to 1, obtaining 2 bits from each of the second bit sets through round-robin to obtain a total of m × K consecutive bits, obtaining 2 bits from each parity bit set through round-robin to obtain a total of m × P consecutive bits, and obtaining a third bit set containing m × N bits, where N = K + P, as described above.Each second data stream includes a plurality of third bit sets, each of the third bit sets including m×K bits in the second bit set and m×P bits in the parity bit set, with a total of m×K / 2 PAM4 symbols obtained through mapping of the m×K bits in each of the third bit sets from the second bit set, and a total of m×P / 2 PAM4 symbols obtained through mapping of the m×P bits in each of the third bit sets from the parity bit set, and it should be understood that the m×2 bits mapped to m consecutive PAM4 symbols out of the total m×N / 2 PAM4 symbols are from m second bit sets and / or m parity bit sets.

[0261] In some possible implementations, outer coding is performed for each of the first data streams, with at least 10 PAM4 symbols obtained through interleaving and coding processing and mapping of 20 consecutive bits in the first data stream, where the 20 consecutive bits are from 2 outer code symbols in one outer codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0262] In some possible implementations, the amount of bits of the cyclic shift performed for any two of the m first bit sets is different.

[0263] In some possible implementations, both the m first bit sets and the m second bit sets are represented as bit matrices, and the bit matrices include m rows and K columns of bits.

[0264] In some possible implementations, the second bit set is relative to the first bit set

[0265]

Number

[0266] Obtained by performing a left circular shift of bits, the left circular shift satisfies a first condition, and the first condition is

[0267] [Number]

[0268] which includes, M1[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m first bit sets where no left circular shift has been performed, M2[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m second bit sets obtained through the left circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ j < K, 0 ≤ i < m,

[0269] [Number]

[0270] and

[0271] In some possible implementations, the second bit set is obtained by performing a right circular shift of δ i bits on the first bit set, the right circular shift satisfies a second condition, and the second condition is M2[i][j]=M1[i][(j - δ i )%K] which includes, M1[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m first bit sets where no right circular shift has been performed, M2[i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to m second bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ j < K, 0 ≤ i < m, 0 ≤ δ i < K

[0272] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a left circular shift of the bits of the i-th first bit set, where 0 ≤ i < 8, and

[0273] [Number]

[0274] the value of which satisfies any one of the items of the first value

[0275] [Number]

[0276] and the item of the first value

[0277] [Number]

[0278] satisfies any one of the following, and the item of the first value

[0279] [Number]

[0280] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} and includes.

[0281] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8, and the value of δ satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} are i {0, 30, 60, 90, 10, 40, 70, 100}, i {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} including.

[0282] ​​According to the 11th aspect, the present application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bitmapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processes on each of n1 first data streams among n0 first data streams to obtain one second data stream, and to obtain a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bitmapping module is configured to separately map each of 2 bits in the n2 second data streams to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. Specifically, the interleaving and encoding module obtains a0 first bit sets from each of the n1 first data streams, obtaining a total of m = n1×a0 first bit sets, performing outer code encoding on all of the n1 first data streams, each of the first bit sets including K bits, where n1, a0, and K are all integers greater than 1, separately performing a cyclic shift on the m first bit sets to obtain m second bit sets, each of the second bit sets including K bits, separately performing inner code encoding on the m second bit sets to obtain m inner code codewords, both the inner code encoding and the outer code encoding being forward error correction (FEC) encoding, each of the inner code codewords including one second bit set and one parity bit set that participates in the inner code encoding and has a total of N bits, where N = K + P, each parity bit set including P bits, and P being an integer greater than or equal to 1, obtaining 2 bits from each of the inner code codewords through round-robin to obtain a third bit set, the third bit set including m×N bits, a total of m×K bits in the third bit set from the m second bit sets being consecutive, and a total of m×P bits in the third bit set from the m parity bit sets being consecutive.Each second data stream includes a plurality of third bit sets, and through the mapping of each of the third bit sets, a total of m×N / 2 PAM4 symbols are obtained. It should be understood that the m×2 bits mapped to m consecutive PAM4 symbols among the m×N / 2 PAM4 symbols are from m inner code codewords.

[0283] In some possible implementations, outer coding is performed for each of the first data streams, and at least 10 PAM4 symbols are obtained through interleaving and encoding processing and the mapping of 20 consecutive bits in the first data stream. The 20 consecutive bits are from 2 outer code symbols in one outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

[0284] In some possible implementations, the amount of bits of the cyclic shift performed for any two of the m first bit sets is different.

[0285] In some possible implementations, both the m first bit sets and the m second bit sets are represented as bit matrices, and the bit matrices include bits in m rows and K columns.

[0286] In some possible implementations, the second bit set is obtained by performing a left cyclic shift of bits on the first bit set, and the left cyclic shift satisfies a first condition, and the first condition is

[0287]

Number

[0288] obtained by performing a left cyclic shift of bits, and the left cyclic shift satisfies a first condition, and the first condition is

[0289]

Number

[0290] including, where M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m first bit sets where no left circular shift is performed, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m second bit sets obtained through a left circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ i < m, 0 ≤ j < K,

[0291]

Number

[0292] and

[0293] In some possible implementations, the second bit set is obtained by performing a right circular shift of δ i bits on the first bit set, and the right circular shift satisfies a second condition, where the second condition is M2[i][j]=M1[i][(j - δ i )%K] including, where M1[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m first bit sets where no right circular shift is performed, M2[i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to m second bit sets obtained through a right circular shift, Y%Z represents the remainder obtained by dividing integer Y by integer Z, 0 ≤ i < m, 0 ≤ j < K, and 0 ≤ δ i < K.

[0294] In some possible implementations, the m inner codewords are represented as a bit matrix including m rows and N columns, and the m inner codewords and the third bit set satisfy a third condition, where the third condition is

[0295]

Number

[0296] including M C [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m inner code codewords,

[0297]

Number

[0298] is the

[0299]

Number

[0300] representing the bit, where 0 ≤ i < m and 0 ≤ j < N,

[0301]

Number

[0302] represents the floor operation.

[0303] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a

[0304]

Number

[0305] left cyclic shift of the bits with respect to the i-th first bit set, where 0 ≤ i < 8,

[0306]

Number

[0307] value is the item of the first value

[0308]

Number

[0309] Satisfies any one of them, and the item of the first value

[0310]

Number

[0311] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} includes.

[0312] In some possible implementations, K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ i bits on the i-th first bit, where 0 ≤ i < 8, and δ i satisfies any one of the items of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the item of the second value {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} is {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} includes

[0313] According to a twelfth aspect, the present application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bitmapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processing on each of n1 first data streams among n0 first data streams to obtain one second data stream, and to obtain a total of n2 second data streams, where n2 = n0 / n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bitmapping module is configured to separately map each 2 bits among the n2 second data streams to one PAM4 symbol to obtain a total of n2 PAM4 symbol data streams. In particular, the interleaving and encoding module obtains a0 first bit sets from each of the n1 first data streams, obtains a total of m = n1 × a0 first bit sets, performs outer code encoding on all of the n1 first data streams, each of the first bit sets includes K bits, n1, a0, and K are all integers greater than 1, separately performs inner code encoding on the m first bit sets to obtain m inner code codewords, both the inner code encoding and the outer code encoding are forward error correction (FEC) encoding, each of the inner code codewords includes one first bit set that participates in the inner code encoding and has a total of N bits and one parity bit set, N = K + P, each parity bit set includes P bits, P is an integer greater than or equal to 1, separately interleaves the m inner code codewords to obtain one second bit set, the second bit set includes m × N bits, and the

[0314]

Number

[0315] The bits are configured such that they satisfy the first condition or the second condition, 0 ≤ i < m, and 0 ≤ j < N.

[0316] The first condition is

[0317]

Number

[0318] includes

[0319]

Number

[0320] is the

[0321]

Number

[0322] bit in the second bit set,

[0323]

Number

[0324] is the

[0325]

Number

[0326] bit in the i-th inner codeword, and C i [j] represents the j-th bit in the i-th inner codeword.

[0327] The second condition is

[0328]

Number

[0329] includes

[0330] [Number]

[0331] is the

[0332] [Number]

[0333] bit in the second bit set, and C i [(j - δ i ) % K] represents the ((j - δ i ) % K) - th bit in the i - th inner - code codeword, and C i [j] represents the j - th bit in the i - th inner - code codeword.

[0334] Each second data stream includes a plurality of second bit sets, and a total of m×N / 2 PAM4 symbols are obtained through each mapping of the second bit sets. It should be understood that the m×2 bits mapped to m consecutive PAM4 symbols among the m×N / 2 PAM4 symbols are from m inner - code codewords.

[0335] In some possible implementations, K = 120 and m = 8,

[0336] [Number]

[0337] value satisfies any one of the items of the first value

[0338] [Number]

[0339] and satisfies any one of the items of the first value

[0340]

Number

[0341] is {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} includes δ i The value of satisfies any one of the items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the second value, and the items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the second value are {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} includes.

[0342] In an embodiment of the present application, a concatenated FEC transmission strategy is used. That is, outer coding and inner coding are sequentially performed on the data stream. Based on this, the present application designs an interleaving and mapping method such that both the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to modulation symbols. In this way, the concatenated FEC transmission strategy has a strong burst tolerance ability. In particular, short burst errors can be directly corrected through inner decoding. The concatenated FEC transmission strategy is widely applicable to transmission scenarios, especially the transmission scenario of actual coherent transmission with colored noise on the channel.

Brief Description of the Drawings

[0343]

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Figure 12(b)

Figure 12(c)

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Figure 34

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Figure 36

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Figure 38

Figure 39

Figure 40

Embodiments for Carrying Out the Invention

[0344] Embodiments of the present application provide a data processing method and a data processing apparatus that have a strong burst tolerance ability with a concatenated FEC transmission strategy and can be applied in a large number of transmission scenarios, particularly in actual coherent transmission scenarios where there is colored noise on the channel. In the specification, claims, and the above-mentioned accompanying drawings of the present application, it should be noted that the terms "first" and "second" are intended to distinguish similar objects and do not limit a specific order or permutation. It should be understood that in appropriate cases, the above terms may be interchangeable so that the embodiments described in the present application can be implemented in an order other than that described in the present application. In addition, the terms "including", "having", or any variation thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or units is not limited to the steps or units explicitly listed, and may include other steps and units not explicitly listed or inherent to those processes, methods, products, or devices.

[0345] FIG. 1 is a diagram of a communication system to which an embodiment of the present application is applicable. As shown in FIG. 1, the communication system includes a transmitter device 01, a transmitter processing module 02, a channel transmission medium 03, a receiver processing module 04, and a receiver device 05. For example, the communication system is a data center network. The transmitter device 01 and the receiver device 05 can be devices such as switches or routers. In addition, the transmitter device 01 is also called a host chip located in the transmitter, the receiver device 05 is also called a host chip located in the receiver, and the channel transmission medium 03 can be an optical fiber. The host chip may sometimes be called a host device. The transmitter device 01 and the transmitter processing module 02 may be connected to each other through an attachment unit interface (AUI), and the receiver device 05 and the receiver processing module 04 may be connected to each other through the AUI. The transmitter processing module 02 and the receiver processing module 04 can be an optical module, an electrical module, a connector, or other modules that process data in the data transmission process. For example, the processing module can be an 800LR module (800LR module, which is a coherent optical module). In addition, all of the transmitter device 01, the transmitter processing module 02, the channel transmission medium 03, the receiver processing module 04, and the receiver device 05 in the communication system can support bidirectional transmission or unidirectional transmission. This is not particularly limited in this specification.

[0346] Figure 2 is a diagram of the data transmission process in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from the transmitter device 01 to the receiver device 05, the transmitter device 01 is configured to perform outer coding on the data and then transmit the outer-coded data to the transmitter processing module 02. The transmitter processing module 02 is configured to perform inner coding on the outer-coded data to obtain outer-coded and inner-coded data, and transmit the outer-coded and inner-coded data to the channel transmission medium 03. The channel transmission medium 03 is configured to transmit the outer-coded and inner-coded data to the receiver processing module 04. The receiver processing module 04 is configured to perform inner decoding on the outer-coded and inner-coded data and transmit the inner-decoded data to the receiver device 05. The receiver device 05 is configured to perform outer decoding on the inner-decoded data.

[0347] It should be understood that the "inner" in the inner code and the "outer" in the outer code are distinguished only based on the distance between the execution entity that performs operations on the data and the channel transmission medium 03. The execution entity that performs operations on the inner code is closer to the channel transmission medium, and the execution entity that performs operations on the outer code is farther from the channel transmission medium. In the embodiments of the present application, after being transmitted from the transmitter device 01, the data is transmitted to the channel transmission medium 03 via the transmitter processing module 02, and then transmitted from the channel transmission medium 03 to the receiver device 05 via the receiver processing module 04. The data obtained through the encoding performed by the transmitter device 01 is farther from the channel transmission medium 03 than the data obtained through the encoding performed by the transmitter processing module 02, and the data obtained through the decoding performed by the receiver device 05 is farther from the channel transmission medium 03 than the data obtained through the decoding performed by the receiver processing module 04. Therefore, the data obtained through the encoding performed by the transmitter device 01 is called outer-code-encoded data, the data obtained through the encoding performed by the transmitter processing module 02 is called inner-code-encoded data, the data obtained through the decoding performed by the receiver device 05 is called outer-code-decoded data, and the data obtained through the decoding performed by the receiver processing module 04 is called inner-code-decoded data. In a possible implementation, both the inner-code encoding and the outer-code encoding use the FEC encoding method to form a concatenated FEC transmission strategy. For example, the transmitter device 01 may perform outer-code encoding by using the RS code, and the transmitter processing module 02 may perform inner-code encoding by using the Hamming code. As another example, the transmitter device 01 may perform outer-code encoding by using the RS code, and the transmitter processing module 02 may perform inner-code encoding by using the Bose-Chaudhuri-Hocquenghem (BCH) code.

[0348] The above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of the present application. It should be noted that it does not impose any restrictions on the application scenarios of the data processing method. Those skilled in the art may know that as the service requirements change, the application scenarios of the data processing method can be adjusted based on the application requirements. The application scenarios are not enumerated in the embodiments of the present application.

[0349] FIG. 3 is a schematic flowchart of a data processing method according to an embodiment of the present application. This method is for data processing performed on an outer-coded data stream, and specifically, it should be understood that it can be performed by the above-mentioned transmitter processing module 02.

[0350] 301: Separately perform inner coding on n first data streams to obtain n second data streams.

[0351] In this embodiment, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n first data streams, where n is an integer greater than 1. The first data processing may include alignment lock, lane de-skew processing, lane reorder processing, concatenated interleaving processing, etc. All of the above-mentioned n first data streams are outer-coded data streams. For example, an RS code may be used for outer coding, and the n outer-coded data streams may include a plurality of RS codewords. In actual application examples, alternatively, another coding method may be used for performing outer coding. For the sake of simplicity of description, hereinafter, uniformly, an RS codeword is used to represent a codeword generated through outer coding. It should be noted that in this application, the code length of the outer code is measured in outer code symbol units, and a symbol may include one or more bits. For example, the outer code is the KP4 RS(544,514) code in use, the code length is 544 symbols, and one outer code symbol includes 10 bits.

[0352] The inner code encoder performs inner coding on each K bits in each of the first data streams, and then adds P parity bits to obtain an inner codeword including a total of N bits. In this specification, these K bits may sometimes be referred to as the inner code information sequence, and K + P = N. Generally, K is a multiple of 10, and the K bits correspond to K / 10 outer code symbols. In some scenarios, the K / 10 outer code symbols corresponding to the K information bits are from K / 10 different outer codewords.

[0353] It should be understood that each second data stream obtained through inner code symbolization includes at least one inner code symbol word. One inner code symbol word is obtained separately from each second data stream, and a total of n inner code symbol words are obtained. The n inner code symbol words include n / m symbol word sets, namely symbol word set 0, symbol word set 1, …, and symbol word set n / m−1. Each symbol word set includes m inner code symbol words. The symbol word set h (0 ≦ h < n / m) includes symbol words m×h, m×h + 1, …, and m×h + m−1. n is divisible by m.

[0354] Note that the above symbol word sets are just concepts introduced to simplify the explanation. In actual application examples, the second data stream is an integral part without division. Each symbol word set can be regarded as a plurality of bits in the second data stream.

[0355] 302: Bit interleaving is separately performed on the n / m symbol word sets to obtain n / m target bit sets.

[0356] It should be understood that both the amount of bits in the symbol word set and the amount of bits in the target bit set are m×N. This step is to perform a position transformation on the bits in the symbol word set to obtain the target bit set. In one example, the target bit set can be represented as a bit matrix having m rows and N columns. In another example, the target bit set can alternatively be represented as a one-dimensional array containing m×N bits. In one example where the symbol word set is represented as a bit matrix, the bit interleaving provided in this application performs a position transformation (briefly referred to as row transformation) on the bits in each row of the symbol word set, performs a position transformation (briefly referred to as column transformation) on the bits in each column of the symbol word set, and performs a position transformation (briefly referred to as row-column transformation) on the bits in each row and each column of the symbol word set, it should be noted. The row-column transformation includes first row transformation then column transformation, first column transformation then row transformation, and simultaneous row transformation and column transformation. The following describes the bit interleaving in detail for some specific implementations.

[0357] For simplicity of explanation, the m×N symbol word bits in the symbol word set h (0≤h<n / m) are represented by using a first matrix H1 having m rows and N columns, and each row in the first matrix H1 contains N bits in one inner code symbol word. The bit in the i-th (0≤i<m) row and the j-th (0≤j<N) column in the first matrix H1 is denoted as H1[i][j]. More specifically, H1[i][j] represents the j-th bit in the i-th inner code symbol word in the symbol word set h, and also represents the j-th bit in the symbol word m×h+i from the second data stream m×h+i. It should be noted that the n / m symbol word sets correspond to n / m first matrices H1. That is, the symbol word set h (0≤h<n / m) corresponds to the h-th first matrix H1. For simplicity of explanation, hereinafter, the h-th first matrix H1 is briefly described as the first matrix H1.

[0358] Among the first \(K\) bits in each row of the first matrix \(H1\), from the 0th column to the \((K - 1)\)th column, they correspond to the information bits of length \(K\) in one inner codeword. Among the first \(m\times K\) bits in each row of the first matrix \(H1\), from the 0th column to the \((K - 1)\)th column, they correspond to the \(m\times K\) information bits in the inner codewords. Similarly, among the first \(P\) bits in each row of the first matrix \(H1\), from the \(K\)th column to the \((N - 1)\)th column, they correspond to the parity bits of length \(P\) in one inner codeword. Among the first \(m\times P\) bits in each row of the first matrix \(H1\), from the \(K\)th column to the \((N - 1)\)th column, they correspond to the \(m\times P\) parity bits in \(m\) inner codewords.

[0359] The following describes a specific method in which row transformation and column transformation are performed separately.

[0360] Implementation form 1 of bit interleaving: row transformation (which can also be called the first position transformation).

[0361] Specifically, the first position transformation is performed on the \(K\) information bits in each inner codeword in the codeword set. Alternatively, this can be described as "the first position transformation is performed on the \(K\) information bits in each row of the first matrix \(H1\)". In a possible implementation form, specifically, the first position transformation is to perform a left circular shift or a right circular shift on the \(K\) information bits in each row of the first matrix \(H1\). For example, a left circular shift is used. For the \(K\) information bits in the \(i\)th (\(0\leq i\lt m\)) row of the first matrix \(H1\), a left circular shift of \(i\times\Delta\) bits is performed, and the non-zero integer \(\Delta\) is the row offset constraint factor. Note that for the \(K\) information bits \((u0, u1, u2, u3, \ldots, u K-2 , u K-1 ), a left circular shift of \(i\times\Delta\) bits is performed to obtain the \(K\) bits \((u (i×Δ)%K , u (1+i×Δ)%K , u (2+i×Δ)%K , \ldots, u (K-2+i×Δ)%K , u (K-1+i×Δ)%K ) obtained through the shift.

[0362] Figure 4 is a diagram of performing a left circular shift on the information bits in each row according to an embodiment of the present application. As shown in the example of (a) in Figure 4, K = 8, and a 2-bit left circular shift is performed. For the eight information bits (u i,0 , u i,1 , u i,2 , u i,3 , u i,4 , u i,5 , u i,6 , u i,7 ) in the i-th row, a 2-bit left circular shift is performed to obtain (u i,2 , u i,3 , u i,4 , u i,5 , u i,6 , u i,7 , u i,0 , u i,1 ). As shown in the example of (b) in Figure 4, Δ = 2, and an i×2-bit left circular shift is performed on the eight information bits in the i-th row. For example, a 0-bit left circular shift is performed on the eight information bits in the 0-th row, a 2-bit left circular shift is performed on the eight information bits in the 1-st row, and a 4-bit left circular shift is performed on the eight information bits in the 2-nd row. The circular shift is performed in this way to perform the first position transformation on the K information bits in each row in the first matrix H1.

[0363] More specifically, the circular shift method used for the first position transformation is described by using the following formula.

[0364] In an example, a left circular shift is used for the first position transformation, and the first position transformation is Equation (1.1)

[0365]

Equation

[0366] Satisfy, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the first position transformation has not been performed, H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the first position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ i < m, generally, the row offset constraint factor Δ is a multiple of 10, and 0 < Δ < K.

[0367] It should be noted that performing an i×Δ-bit left circular shift on K information bits is equivalent to performing an (i×Δ)%K-bit left circular shift on K information bits. That is, the above formula (1.1) is the following formula (1.2)

[0368]

Number

[0369] Can be written as.

[0370] An i×Δ-bit left circular shift is performed on the K information bits in the i-th row in the first matrix H1 to obtain K bits from the 0-th column to the (K - 1)-th column in the i-th row in the second matrix H2. Equivalently, an i×(K - Δ)-bit right circular shift is performed on the K information bits from the 0-th column to the (K - 1)-th column in the i-th row in the first matrix H1 to obtain K bits from the 0-th column to the (K - 1)-th column in the i-th row in the second matrix H2. As shown in the example of (a) in Figure 4, when K = 8, performing a 2-bit left circular shift on the information bits is equivalent to performing a 6-bit right circular shift.

[0371] In another example, a right circular shift is used for the first position transformation, and the first position transformation is formula (1.3)

[0372]

Number

[0373] satisfies, the integer α is a multiple of K, and when 0 ≦ i < m and 0 ≦ j < K,

[0374]

Number

[0375] is a non - negative integer, and the integer

[0376]

Number

[0377] and generally, the row offset constraint factor

[0378]

Number

[0379] is a multiple of 10,

[0380]

Number

[0381] and other parameters that are the same as those in the above formula (1.1) will not be explained one by one here again.

[0382] In the expressions of some specific formulas, for the sake of simplicity, formula (1.3) is expressed as formula (1.4)

[0383]

Number

[0384] and is concisely expressed as.

[0385] It should be further noted that performing a cyclic shift on the K information bits in the 0th to (K-1)th columns in each row of the first matrix H1 is to perform an operation only on the information bits in the first matrix H1. Therefore, it can also be described as performing a cyclic shift on the K information bits in the 0th to (K-1)th columns in each row of the first matrix H1 to obtain a fourth matrix H4 having m rows and K columns. Specifically, the left cyclic shift is used for the first position transformation, and the first position transformation is given by Equation (3.1) H4 = H1[i][(j + i×Δ)%K] is satisfied.

[0386] The meanings of the parameters in Equation (3.1) are similar to those in Equation (1.1). Details will not be described again here.

[0387] Implementation form 2 of bit interleaving: column transformation (which can also be called the second position transformation).

[0388] It should be noted that the column transformation described in this implementation form is described based on performing a row transformation on the first matrix H1 to obtain a second matrix H2. In some possible scenarios, in this implementation form, alternatively, the column transformation may be first performed on the first matrix H1. Details will not be described again here.

[0389] Specifically, a second position transformation is performed on the bits at the same position in the second matrix H2 to obtain a third matrix H3. It should be understood that the bits at the same position in the second matrix H2 can be understood as m bits in the same column in the second matrix H2. In other words, a position transformation is performed on m bits in the same column. Alternatively, the bits at the same position in the second matrix H2 may be understood as G×m bits in G same columns in the second matrix H2, where G is an integer greater than 1. In other words, for every G bits in G same columns in each row, an up-down position transformation is performed. For the sake of simplicity of explanation, the following provides an explanation by using an example where the same position is the same column.

[0390] In a possible implementation, the second matrix H2 is divided into m / L first sub-matrices, and each first sub-matrix includes L rows and N columns. An upper cyclic shift or a lower cyclic shift is performed on the L bits in each column in each first sub-matrix to perform a position transformation of the bits in each first sub-matrix. An upper cyclic shift is used as an example. An upper cyclic shift of θ×(j%L) bits is performed on the L bits in the j-th (0≤j<N) column in each first sub-matrix, and the non-zero integer θ is a column offset constraint factor. Here, performing an upper cyclic shift of θ×(j%L) bits on the L bits in the j-th (0≤j<N) column in each first sub-matrix is equivalent to, alternatively, performing an upper cyclic shift of θ×j bits. This may be known to those skilled in the art. Details are not explained again here. The L bits

[0391]

Number

[0392] An upper cyclic shift of θ×(j%L) bits is performed on them, and the L bits obtained through the shift

[0393]

Number

[0394] to obtain.

[0395] FIG. 5 is a diagram of performing a circular shift upward on each L bits in each column in each of the first partial matrices according to an embodiment of the present application. As shown in the example of FIG. 5(a), L = 8 and a circular shift upward of 2 bits is performed. The 8 bits in the j-th column

[0396]

Number

[0397] is subjected to a circular shift upward of 2 bits, and the 8 bits obtained through the shift

[0398]

Number

[0399] is obtained. As shown in the example of FIG. 5(b), θ = 2, and a circular shift upward of 2×(j%8) bits is performed on the 8 bits in the j-th column. For example, a circular shift upward of 0 bits is performed on the 8 bits in the 0-th column, a circular shift upward of 2 bits is performed on the 8 bits in the 1-st column, and a circular shift upward of 4 bits is performed on the 8 information bits in the 2-nd column. The circular shift is performed in this manner to perform a second position transformation on the bits at the same position in the second matrix H2.

[0400] More specifically, the circular shift method used for the second position transformation is described by using the following formula.

[0401] In an example, a circular shift upward is used for the second position transformation, and the second position transformation is given by Equation (2.1)

[0402]

Number

[0403] satisfies, where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, and H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation.

[0404]

Number

[0405] represents truncation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≤ i < m, and 0 ≤ j < N. The non-zero integer θ is a column offset constraint factor, and generally, the column offset constraint factor satisfies 0 < θ < L.

[0406] The above formula (2.1) can alternatively be

[0407]

Number

[0408] understood to be written as.

[0409] Performing a θ×(j%L)-bit upward circular shift on the L bits in the j-th column of the first submatrix in the second matrix H2 is equivalent to performing an (L - θ)×(j%L)-bit downward circular shift. As shown in the example of (a) in Figure 5, when L = 8, performing a 2-bit upward circular shift is equivalent to performing a 6-bit downward circular shift.

[0410] In another example, a downward circular shift is used for the second position transformation, and the second position transformation is formula (2.2)

[0411]

Number

[0412] satisfies, and the integer β is a multiple of L,

[0413]

Number

[0414] is a non - negative integer when 0 ≦ i < m and 0 ≦ j < N, and the integer

[0415]

Number

[0416] is. Generally, the column offset constraint factor

[0417]

Number

[0418] satisfies, and the other parameters same as those in the above formula (2.1) are not explained one by one here again.

[0419] In some specific formula expressions, for the sake of simplicity, formula (2.2) is formula (2.3)

[0420]

Number

[0421] and is concisely expressed as.

[0422] In another possible implementation, different from the second position transformation where the above - mentioned upper - cyclic shift or lower - cyclic shift method is used, the second position transformation is formula (2.4)

[0423]

Number

[0424] satisfies, where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, and H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation.

[0425]

Number

[0426] represents truncation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≤ i < m, and 0 ≤ j < N.

[0427] Figure 6 is a diagram of performing position transformation on the bits in each column according to an embodiment of the present application. As shown in Figure 6, when m = 8 and L = 8, the method of the second position transformation that satisfies the above formula (2.4) is shown. U i,j represents the bit in the i-th row and j-th column in the second symbol matrix H2. In the manner shown in the figure, each 8 consecutive columns in the second matrix H2, that is, the columns from the (8*k)-th column to the (8*k + 7)-th column, are interleaved and mapped to 8 consecutive columns in the third symbol matrix, that is, the columns from the (8*k)-th column to the (8*k + 7)-th column.

[0428] When the integer L is a power of 2, the second position transformation further satisfies the formula (2.5) H3[i][j]=H2[i^(j%L)][j] may be satisfied, where H2[i][j] represents the bit in the i-th row and j-th column in the bit matrix where the second position transformation has not been performed, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, and it should be noted that 0≦i<m and 0≦j<N.

[0429] It should be further noted that the above-mentioned first position transformation is a position transformation performed only on information bits, while the second position transformation is a position transformation performed on both information bits and parity bits. The above description is only for the fourth matrix H4 having only information bits of m rows and K columns, and the second position transformation is further expressed in the following different manner.

[0430] Specifically, the m rows and K columns in the first matrix H1 and the columns from the K-th column to the (N - 1)-th column, that is, the fourth matrix H4 having m rows and N columns in total, are divided into a plurality of second sub-matrices, and each second sub-matrix includes L rows and N columns. This position transformation is performed on the L bits in each column in each second sub-matrix to obtain a third matrix H3 having m rows and N columns.

[0431] In a specific implementation form, for the L bits in the j-th (0≦j<N) column in each second sub-matrix, a circular shift of θ×(j%L) bits is performed. More specifically, for 0≦i<m, the second position transformation further satisfies the formula (4.1)

[0432]

Equation

[0433] may be satisfied.

[0434] The integer θ is a column offset constraint factor. Equation (4.1) can alternatively be

[0435]

Number

[0436] concisely expressed as.

[0437] In another specific implementation form, for 0 ≦ i < m, the second position transformation further satisfies Equation (4.2)

[0438]

Number

[0439] and may be satisfied.

[0440] When L is a power of 2, for 0 ≦ i < m, the second position transformation further satisfies Equation (4.3)

[0441]

Number

[0442] and may be satisfied.

[0443] It should be understood that the above describes a specific method in which the row transformation and the column transformation are performed separately. That is, bit interleaving includes a two-stage operation. In some possible scenarios, alternatively, the row transformation and the column transformation may be performed using a one-stage operation. The following details this implementation form.

[0444] Implementation form 3 of bit interleaving: The row transformation and the column transformation are performed using a one-stage operation.

[0445] In a certain specific implementation form, for 0 ≦ i < m, bit interleaving is Equation (5)

[0446] [Number]

[0447] satisfies, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix without bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through bit interleaving, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K,

[0448] [Number]

[0449] represents truncation, and θ is a non-zero integer greater than -L and less than L.

[0450] Equation (5) can alternatively be

[0451] [Number]

[0452] concisely expressed as.

[0453] In another specific implementation, for 0 ≦ i < m, the bit interleaving is given by Equation (6)

[0454] [Number]

[0455] satisfies, where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix without bit interleaving, H3[i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through bit interleaving, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K,

[0456]

Number

[0457] represents truncation, θ is a non-zero integer greater than -L and less than L, and Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z.

[0458] When L is a power of 2, for 0 ≦ i < m, the bit interleaving satisfies equation (7)

[0459]

Number

[0460] is satisfied.

[0461] Note that when the integer Δ is a multiple of 10 and one outer code symbol in the outer codeword contains 10 bits, the K information bits may be regarded as K / 10 symbols, and each symbol corresponds to 10 information bits. Performing a cyclic shift of i×Δ bits on the K information bits in the i-th (0 ≦ i < m) row in the first matrix H1 is equivalent to performing

[0462]

Number

[0463] It can be regarded as performing a cyclic shift of symbols. Its specific implementation form is known to those skilled in the art. Details are not described again here.

[0464] When specific values of parameters such as Δ, θ, m, and L are given, the correspondence of interleaving for performing bit interleaving on the first matrix H1 to obtain the third matrix H3 can be described by using a table. Its specific implementation form is known to those skilled in the art. Details are not described again here.

[0465] When specific values of parameters such as Δ, θ, m, and L are given, the above formula (5) or (6) can be easily converted into another formula. For example, when m = L, formula (5) can be simplified as follows.

[0466] [Number]

[0467] Formula (6) can be converted as follows.

[0468] [Number]

[0469] [Number]

[0470] It should be understood that specific implementation forms of other simple conversions are known to those skilled in the art. Details are not described again here.

[0471] It should be noted that the above symbol word sets, bit matrices, and submatrices are only concepts introduced to simplify the description. In actual application examples, the data stream is an integral part without division. Each symbol word set, bit matrix, and submatrix can be regarded as one or more bits in the data stream. In addition, in actual application examples, the first matrix, the second matrix, the third matrix, the fourth matrix, etc. may not be presented in the form of a matrix as an alternative. For example, the first matrix H1 is presented as the first bit set, the first bit set includes m first bit subsets, and each first bit subset includes the bit elements in one row and N columns in the corresponding first matrix H1.

[0472] It should be noted that in the above implementation form, the target bit set obtained through bit interleaving of m symbol words is represented by using a third matrix H3 with m rows and N columns. In addition, the target bit set can alternatively be represented by using a one-dimensional array (array) denoted as array A and including m×N bits. The t-th (0≦t<m×N) bit in array A is denoted as A[t]. Performing bit interleaving on the first matrix H1 to obtain an array A including m×N bit elements can alternatively be represented in the following manner.

[0473] In an example, for 0≦i<m, the bit interleaving satisfies Equation (8)

[0474]

Equation

[0475] where H1[i][j] represents the bit in the i-th row and j-th column in the bit matrix where bit interleaving has not been performed, A[t] represents the t-th bit in the one-dimensional array obtained through bit interleaving, 0≦t<m×N, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, and Δ is a non-zero integer greater than -K and less than K.

[0476] [Number]

[0477] represents truncation, and θ is a non - zero integer greater than -L and less than L.

[0478] In another example, for 0 ≦ i < m, bit interleaving is given by Equation (9)

[0479] [Number]

[0480] satisfies, where H1[i][j] represents the bit in the i - th row and j - th column of the bit matrix where no bit interleaving is performed, A[t] represents the t - th bit in the one - dimensional array obtained through bit interleaving, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non - zero integer greater than -K and less than K,

[0481] [Number]

[0482] represents truncation, θ is a non - zero integer greater than -L and less than L, and Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive - OR operation performed on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z.

[0483] When L is a power of 2, for 0 ≦ i < m, bit interleaving is given by Equation (10)

[0484] [Number]

[0485] is satisfied.

[0486] 303: Map each m×N bits in the target bit set separately to obtain m×N / L modulation symbols, and obtain n×N / L modulation symbols in total.

[0487] In this embodiment, m is divisible by L. Each L bits in the target bit set are mapped to one modulation symbol. That is, the modulation symbol contains L bits. The L bits in each modulation symbol are from L inner code codewords. In addition, when all the L bits mapped to the modulation symbol are from the information bits in the inner code codewords, any two of the L bits mapped to the modulation symbol are from two different positions in two different inner code codewords.

[0488] It should be understood that the n×N / L modulation symbols obtained through the mapping of all target bit sets can be represented as one modulation symbol stream. Alternatively, the m×N / L modulation symbols obtained through the mapping of each target bit set are represented as one modulation symbol stream, and a total of n / m modulation symbol streams can be obtained. Then, the modulation symbol stream can further undergo other data processing and then be transmitted to the channel transmission medium for transmission. Other data processing may include polarization distribution, DSP framing processing, etc.

[0489] In a possible implementation, when N is divisible by L, the N bits in each inner code codeword are mapped to N modulation symbols. The N bits in the inner code codeword include L first bit subsets. The bits in the same first bit subset are separately mapped to the same bits in different modulation symbols, and the bits in different first bit subsets are separately mapped to different bits in different modulation symbols. For example, one modulation symbol is bit b0, bit b1, …, and bit b L-1including, among the N bits in the inner code codeword, bit b0, bit b1, …, and bit b L-1 The amounts of bits mapped to bits b L-1 are all N / L. It should be understood that the probabilities of errors occurring in the L bits in transmission are not necessarily the same. Since the bits in one inner code codeword are more evenly mapped to modulation symbols, the burst tolerance ability of the concatenated FEC scheme in actual transmission can be improved.

[0490] In some possible scenarios, alignment marker locking and lane deskewing processing are performed for all of the n first data streams, and when all of the W×L bits in the W consecutive modulation symbols are information bits in the inner code codeword, note that those W×L bits are from more than two outer code codewords obtained through outer coding, with W≧2.

[0491] In some implementations applied to coherent optical communication, the modulation method described above is dual-polarization quadrature amplitude modulation (DP-QAM), for example, DP-QPSK or DP-16QAM. For DP-QPSK modulation, one DP-QPSK modulation symbol corresponds to L = 4 bits. For DP-16QAM modulation, one DP-16QAM modulation symbol corresponds to L = 8 bits.

[0492] In some implementations applied to direct detection optical communication, the modulation method described above is pulse amplitude modulation (PAM), for example PAM4. In PAM4 modulation, one PAM4 modulation symbol corresponds to L = 2 bits.

[0493] The following describes a specific implementation of mapping by using an example where the target bit set is represented as the third matrix H3.

[0494] Implementation form 1 of mapping:

[0495] Each of the L consecutive bits among the m bits in each column in the third matrix H3 is mapped to one modulation symbol. Each third matrix H3 is mapped to m×N / L modulation symbols.

[0496] In a possible implementation, the m / L modulation symbols obtained through the mapping of the m bits in each column in the third matrix H3 are consecutive in the modulation symbol stream. In other words, the m / L modulation symbols obtained through the mapping of each column in the third matrix H3 are used as m / L consecutive modulation symbols in the modulation symbol stream, and the m×N / L modulation symbols obtained through the mapping of the N columns in the third matrix H3 are used as m×N / L consecutive modulation symbols in the modulation symbol stream.

[0497] FIG. 7 is a first diagram of bit mapping according to an embodiment of the present application. As shown in FIG. 7, when m / L = 2, each column in the third matrix H3 is mapped to two modulation symbols, and the two modulation symbols are represented by using S(0,k) and S(1,j), where 0≦j<N.

[0498] In another possible implementation, the m bits in column B in the third matrix H3 are mapped to obtain m / L first modulation symbols, and each of the T consecutive first modulation symbols among the m / L first modulation symbols is consecutive in the modulation symbol stream. The m bits in column C in the third matrix H3 are mapped to obtain m / L second modulation symbols, and each of the T consecutive second modulation symbols among the m / L second modulation symbols is consecutive in the modulation symbol stream. Column B is adjacent to column C, and the T consecutive first modulation symbols among the m / L first modulation symbols and the T consecutive second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T.

[0499] Figure 8 is a second diagram of bitmapping according to an embodiment of the present application. As shown in Figure 8, when m / L = 4 and T = 2, each column in the third matrix H3 is mapped to four modulation symbols represented by using S(0,j), S(1,j), S(2,j), and S(3,j), where 0 ≦ j < N. It can be seen that the first T modulation symbols among the m / L modulation symbols obtained through the mapping of each column in the third matrix H3 are used as T consecutive modulation symbols in the modulation symbol stream. Correspondingly, a total of T×N modulation symbols among the N columns are used as T×N consecutive modulation symbols in the modulation symbol stream. The next T modulation symbols among the m / L modulation symbols obtained through the mapping of each column in the third matrix H3 are used as T consecutive modulation symbols in the modulation symbol stream. Correspondingly, a total of T×N modulation symbols among the N columns are used as the next T×N consecutive modulation symbols in the modulation symbol stream. By analogy, m×N / L consecutive modulation symbols in the modulation symbol stream can be obtained.

[0500] Implementation form 2 of mapping:

[0501] The L bits in each modulation symbol are from L r inner code codewords. Each of the L r inner code codewords has L c bits, that is, a total of L r ×L c bits are mapped to one modulation symbol. The 2L bits in two consecutive modulation symbols are from 2L r inner code codewords. The L r bits in each of the 2L c inner code codewords are mapped to two consecutive modulation symbols. L = L r ×L c and L c > 1. In other words, each of the L r rows in the third matrix H3 has Lc All L within the column r ×L c = L bits are mapped to one modulation symbol, where L c > 1. For example, the bits b0, b1, …, and bit b L-1 in one modulation symbol, respectively corresponding to L inner code bits are from L r different inner code codewords, and each inner code codeword provides L c bits. For the third matrix H3, in each of the L c columns, a total of m×L c bits are mapped to m / L r modulation symbols. Each third matrix H3 is mapped to m×N / L modulation symbols to obtain m×N / L consecutive modulation symbols in the modulation symbol data stream.

[0502] c In a possible implementation, the m / L r modulation symbols obtained through the mapping of each L r column in the third matrix H3 are used as m / L consecutive modulation symbols in the modulation symbol stream, and the m×N / L modulation symbols obtained through the mapping of N columns are used as m×N / L consecutive modulation symbols in the modulation symbol stream.

[0503] Figure 9 is a third diagram of bit mapping according to an embodiment of the present application. As shown in Figure 9,

[0504]

Number

[0505] When it is c the total m×L c bits in each L column in the third matrix H3 are respectively represented by using S(0,j) and S(i,j)

[0506]

Number

[0507] are mapped to N / L modulation symbols, where 0 ≦ j < N / L c is true.

[0508] In another possible implementation, the bits in column B of the third matrix H3 are mapped to m / L r first modulation symbols are obtained, and for each T consecutive first modulation symbols among the m / L r first modulation symbols, they are consecutive in the modulation symbol stream. The bits in column C of each target bit set are mapped to m / L r second modulation symbols are obtained, and for each T consecutive second modulation symbols among the m / L r second modulation symbols, they are consecutive in the modulation symbol stream. Column B contains L c columns, column C also contains L c columns, column B is adjacent to column C, and T consecutive first modulation symbols among the m / L r first modulation symbols and T consecutive second modulation symbols among the m / L r second modulation symbols are consecutive in the modulation symbol stream, and m / L r is divisible by T.

[0509] Figure 10 is a fourth diagram of bit mapping according to an embodiment of the present application. As shown in Figure 10,

[0510]

Number

[0511] and when T = 2, all m × L c bits in each L c column of the third matrix H3 are respectively represented by using S(0,j), S(1,j), S(2,j), and S(3,j)

[0512]

Number

[0513] are mapped to individual modulation symbols, where 0 ≤ j < N / L c is the case. For each L c the first T modulation symbols out of the m / L modulation symbols obtained through the mapping of each L r columns are used as T consecutive modulation symbols in the first modulation symbol stream. Correspondingly, a total of T × N / L c modulation symbols in N columns are used as T × N / L c consecutive modulation symbols in the modulation symbol stream. For each L c the next T modulation symbols out of the m / L modulation symbols obtained through the mapping of each L r columns are used as T consecutive modulation symbols in the first modulation symbol stream. Correspondingly, a total of T × N / L c modulation symbols in N columns are used as the next T × N / L c consecutive modulation symbols in the modulation symbol stream. By analogy, m × N / L consecutive modulation symbols in the modulation symbol stream can be obtained.

[0514] In this embodiment of the present application, a concatenated FEC transmission strategy is used. That is, outer coding and inner coding are sequentially performed on the data stream. Based on this, the present application designs a bit interleaving and mapping method such that both the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to the modulation symbols. In this way, the concatenated FEC transmission strategy has a strong burst tolerance ability. In particular, short burst errors can be directly corrected through inner decoding. The concatenated FEC transmission strategy is widely applicable to transmission scenarios, especially in the scenario of actual coherent transmission with colored noise on the channel.

[0515] Regarding some specific embodiments, the following describes the procedure of the data processing method further illustrated in FIG. 3.

[0516] Embodiment 1: The target bit set is represented as a bit matrix, where n = 32, m = 16, K = 160, and L = 8.

[0517] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 32 first data streams. The 32 first data streams are separately transmitted to an inner encoder for inner coding to obtain 32 second data streams. BCH(176, 160) is used for inner coding. That is, the codeword bit length N = 176, the information bit length K = 160, and the parity bit length P = 16. The 160 information bits in each inner codeword are from 16 symbols in 16 different outer code RS codewords.

[0518] The 32 codewords obtained through inner coding are grouped into h = 2 codeword sets, and each codeword set contains m = 16 BCH(176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to one DP-16QAM symbol. Through bit interleaving and mapping of the 16 BCH(176, 160) codewords in each codeword set, 352 DP-16QAM symbols can be obtained.

[0519] Among the above 16 BCH(176,160) codewords, the total of 2,816 bits are represented by using a first matrix H1 having 16 rows and 176 columns, and each row in the first matrix H1 includes 176 bits in one inner code BCH(176,160) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 having 16 rows and 176 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 16,

[0520] [Number]

[0521] where

[0522] [Number]

[0523] represents a floor operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -160 < Δ < 160, the non-zero integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, 110, 130, 140, and 150, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0524] In the above-described third matrix H3 having 16 rows and 176 columns, each column contains 16 bits. Each of the 8 bits out of the 16 bits is mapped to one DP-16QAM symbol. Each column is separately mapped to two modulation symbols. In a particular implementation, within each column, rows 0 to 7 are mapped to one DP-16QAM symbol, and rows 8 to 15 are mapped to another DP-16QAM symbol. Each third matrix H3 is mapped to 352 DP-16QAM symbols. The two DP-16QAM symbols obtained through the mapping of each column are used as two consecutive DP-16QAM symbols in the first modulation symbol stream, and the 352 DP-16QAM symbols obtained through the mapping of 176 columns are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0525] Each of the 16 codewords out of the 32 codewords undergoes bit interleaving and is then mapped to 352 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to a total of 704 DP-16QAM symbols, and those 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0526] In this embodiment, there is colored noise in actual transmission. When the colored noise has a width of four DP-16QAM symbols, 32 error bits may be scattered among a plurality of inner code BCH(176,160) codewords, and the amount of error bits corresponding to each inner code BCH(176,160) codeword is not more than 2. Since it is considered that the inner code BCH(176,160) can correct 2 bits, colored noise having a width of two or three DP-16QAM symbols can be effectively corrected by the inner code. In addition, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can withstand burst errors longer than 1500 bits. That is, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise having a width of up to four DP-16QAM symbols and can withstand burst errors longer than 1500 bits. According to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise having a width of up to four DP-16QAM symbols and can withstand burst errors longer than 1500 bits.

[0527] Embodiment 2: The target bit set is represented as an array, where n = 32, m = 16, K = 160, and L = 8.

[0528] Based on the scheme of Embodiment 1, a total of 2816 bits among 16 BCH(176,160) codewords are represented by using a first matrix H1 having 16 rows and 176 columns. The data obtained through the bit interleaving of the first matrix H1 is not represented by using a third matrix H3 having 16 rows and 176 columns shown in Embodiment 1, but is represented by using an array A having a length of 2816 bits. Bit interleaving is performed on the first matrix H1 to obtain an array A having a length of 2816 bits. The association of interleaving between the first matrix H1 and the array A is such that for 0 ≦ i < 16,

[0529]

Number

[0530] is,

[0531]

Number

[0532] represents a truncation operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -160 < Δ < 160, the non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, 110, 130, 140, and 150, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0533] Each of the eight consecutive bits in the first array A including 2816 bits is mapped to one DP-16QAM symbol to obtain 352 DP-16QAM symbols, and the 352 DP-16QAM symbols are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0534] Each of the 16 codewords out of 32 codewords undergoes bit interleaving and is then mapped to 352 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to 704 DP-16QAM symbols in total, and the 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0535] When the values of the row offset constraint factor Δ and the column offset constraint factor θ in Embodiment 1 are equal to the values of Δ and θ in Embodiment 2 respectively, it should be noted that the same 704 DP-16QAM symbols as those in Embodiment 2 can be obtained through bit interleaving and mapping of 32 codewords in Embodiment 2.

[0536] In this embodiment, according to the designed bit interleaving and mapping method, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to 4 DP-16QAM symbols and can withstand burst errors longer than 1500 bits.

[0537] Embodiment 3: The target bit set is represented as a bit matrix, where n = 32, m = 8, K = 160, and L = 8.

[0538] Based on the strategy in Embodiment 1, the 32 codewords obtained through inner code encoding are not grouped into the two codeword sets shown in Embodiment 1, but are grouped into 4 codeword sets, and each codeword set contains m = 8 BCH(176,160) codewords. Considering the DP-16QAM symbols, each L = 8 bits is mapped to 1 DP-16QAM symbol, and through bit interleaving and mapping of the 8 BCH(176,160) codewords in each codeword set, 176 DP-16QAM symbols can be obtained.

[0539] A total of 1408 bits in the above 8 BCH(176,160) codewords are represented by using a first matrix H1 with 8 rows and 176 columns. Each row in the first matrix H1 contains 176 bits in 1 inner code BCH(176,160) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 8 rows and 176 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is such that for 0 ≦ i < 8,

[0540]

Number

[0541] is.

[0542] The above formula is

[0543]

Number

[0544] can be simplified to

[0545]

Number

[0546] represents a truncation operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -160 < Δ < 160, the non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0547] In the above-mentioned third matrix H3 having 8 rows and 176 columns, each column contains 8 bits. These 8 bits are mapped to 1 DP-16QAM symbol. Each third matrix H3 is mapped to 176 DP-16QAM symbols. The 176 DP-16QAM symbols obtained through the mapping of 176 columns are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0548] Each of the 8 codewords out of the 32 codewords undergoes bit interleaving and is then mapped to 176 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to 704 DP-16QAM symbols in total, and these 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0549] In this embodiment, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise with a width of up to 2 DP-16QAM symbols and can withstand burst errors longer than 2000 bits.

[0550] Embodiment 4: The target bit set is represented as an array, where n = 32, m = 8, K = 160, and L = 8.

[0551] Based on the scheme in Embodiment 3, a total of 1408 bits among the 8 BCH(176,160) codewords are represented by using a first matrix H1 with 8 rows and 176 columns. The data obtained through the bit interleaving of the first matrix H1 is not represented by using a third matrix H3 with 8 rows and 176 columns shown in Embodiment 1, but is represented by using an array A with a length of 1408 bits. Bit interleaving is performed on the first matrix H1 to obtain an array A with a length of 1408 bits. The interleaving correspondence between the first matrix H1 and the array A is, for 0 ≦ i < 8,

[0552]

Number

[0553] is,

[0554]

Number

[0555] represents a truncation operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -160 < Δ < 160, a non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0556] Each of the 8 consecutive bits in the first array A containing 1408 bits is mapped to 1 DP-16QAM symbol, obtaining 176 DP-16QAM symbols, and the 176 DP-16QAM symbols are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0557] Each of the 8 codewords among the 32 codewords undergoes bit interleaving and is then mapped to 176 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to 704 DP-16QAM symbols in total.

[0558] It should be noted that when the values of the row offset constraint factor Δ and the column offset constraint factor θ in Embodiment 4 are equal to the values of Δ and θ in Embodiment 3 respectively, the same 704 DP-16QAM symbols as those in Embodiment 3 are obtained through the bit interleaving and mapping of the 32 codewords in Embodiment 4.

[0559] In this embodiment, due to the designed bit interleaving and mapping method, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to 2 DP-16QAM symbols and can withstand burst errors longer than 2000 bits.

[0560] Embodiment 5: The target bit set is represented as a bit matrix, where n = 32, m = 32, K = 160, and L = 8.

[0561] Based on the strategy of Embodiment 1, the 32 codewords obtained through inner code encoding are grouped into the two codeword sets shown in Embodiment 1, but are used as one codeword set containing m = 32 PCH(176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to one DP-16QAM symbol. Through bit interleaving and mapping of the 32 BCH(176, 160) codewords, 704 DP-16QAM symbols can be obtained.

[0562] A total of 5632 bits among the above-mentioned 32 BCH(176, 160) codewords are represented using a first matrix H1 having 32 rows and 176 columns, and each row in the first matrix H1 contains 176 bits in one inner code BCH(176, 160) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 having 32 rows and 176 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 32,

[0563]

Number

[0564] where

[0565]

Number

[0566] represents a truncation operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -160 < Δ < 160, the non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 20, 30, 50, 60, 70, 90, 100, 110, 130, and 140, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0567] In the above-mentioned third matrix H3 having 32 rows and 176 columns, each column contains 32 bits. The 32 bits in each column are mapped to 4 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped in total to 704 DP-16QAM symbols. The 704 consecutive DP-16QAM symbols in the first modulation symbol stream consist of those 704 DP-16QAM symbols.

[0568] In a particular implementation, regarding the first T = 1 DP-16QAM symbol among the 4 DP-16QAM symbols obtained through the mapping of each column (i.e., the 0th DP-16QAM symbol obtained through the mapping of each column), a total of 176 DP-16QAM symbols among the 176 columns are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream. Regarding the next T = 1 DP-16QAM symbol among the 4 DP-16QAM symbols obtained through the mapping of each column (i.e., the 1st DP-16QAM symbol obtained through the mapping of each column), a total of 176 DP-16QAM symbols among the 176 columns are used as the next 176 consecutive DP-16QAM symbols in the first modulation symbol stream. By analogy, 704 consecutive DP-16QAM symbols in the first modulation symbol stream can be obtained.

[0569] According to the bit interleaving and mapping method designed in this embodiment, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to two DP-16QAM symbols and can withstand burst errors longer than 2000 bits.

[0570] Embodiment 6: The target bit set is represented as a bit matrix, two symbols in each column are output continuously, and n = 32, m = 32, K = 160, and L = 8.

[0571] Based on the strategy in Embodiment 5, 32 codewords undergo bit interleaving and then are mapped to a total of 704 DP-16QAM symbols. The 704 consecutive DP-16QAM symbols in the first modulation symbol stream consist of those 704 DP-16QAM symbols. This embodiment provides another specific implementation form. Regarding the first two DP-16QAM symbols (i.e., the 0th and 1st DP-16QAM symbols obtained through the mapping of each column) among the four DP-16QAM symbols obtained through the mapping of each column, a total of 352 DP-16QAM symbols among 176 columns are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream. Regarding the last two DP-16QAM symbols (i.e., the 2nd and 3rd DP-16QAM symbols obtained through the mapping of each column) among the four DP-16QAM symbols obtained through the mapping of each column, a total of 352 DP-16QAM symbols among 176 columns are used as the next 352 consecutive DP-16QAM symbols in the first modulation symbol stream. Finally, 704 consecutive DP-16QAM symbols in the first modulation symbol stream are obtained.

[0572] According to the bit interleaving and mapping method designed in this embodiment, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to four DP-16QAM symbols and can withstand burst errors longer than 1500 bits.

[0573] Embodiment 7: The target bit set is represented as a bit matrix, and two symbols in each column are output continuously, where n = 16, m = 16, K = 160, and L = 8.

[0574] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 16 first data streams. The 16 first data streams are separately transmitted to an inner code encoder for inner code encoding to obtain 16 second data streams. BCH(176, 160) is used for inner code encoding. That is, the codeword bit length N = 176, the information bit length K = 160, and the parity bit length P = 16. The 160 information bits in each inner codeword are from 16 symbols in 16 different outer code RS codewords.

[0575] The above-mentioned 16 inner codewords are used as a set of codewords and include m = 16 BCH(176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to one DP-16QAM symbol. 352 DP-16QAM symbols can be obtained through bit interleaving and mapping of 16 BCH(176, 160) codewords.

[0576] A total of 2816 bits in the above-mentioned 16 BCH(176, 160) codewords are represented by using a first matrix H1 with 16 rows and 176 columns. Each row in the first matrix H1 includes 176 bits in one inner code BCH(176, 160) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 176 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is for 0 ≦ i < 16,

[0577]

Number

[0578] wherein

[0579]

Number

[0580] represents a truncation operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -160 < Δ < 160, the integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 20, 30, 50, 60, 70, 90, 100, 110, 130, and 140, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0581] In the above-mentioned third matrix H3 having 16 rows and 176 columns, each column contains 16 bits. The 16 bits in each column are mapped to two DP-16QAM symbols. In a particular implementation, in each column, the 0th row to the 7th row are mapped to one DP-16QAM symbol, and the 8th row to the 15th row are mapped to the other DP-16QAM symbol. The 16 codewords undergo bit interleaving and are then mapped to a total of 352 DP-16QAM symbols, and the 352 consecutive DP-16QAM symbols in the first modulation symbol stream consist of those 352 DP-16QAM symbols. In a particular implementation, the two DP-16QAM symbols obtained through the mapping of each column are used as two consecutive DP-16QAM symbols in the first modulation symbol stream, and the 352 DP-16QAM symbols obtained through the mapping of 176 columns are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0582] The 2816-bit interleaved data obtained through bit interleaving of the first matrix H1 is represented by using a third matrix H3 having 16 rows and 176 columns, or can be represented by using an array having a length of 2816 bits as shown in Embodiment 2 and Embodiment 4. It should be noted that its specific implementation forms are known to those skilled in the art. Details are not described again here.

[0583] In this embodiment, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise with a width of up to 4 DP-16QAM symbols and can withstand burst errors longer than 1500 bits.

[0584] It should be noted that the operation procedure of the transmitter processing module can alternatively be as shown in FIG. 12(b). The lane data stream obtained through the alignment marker lock is directly transmitted to the lane rearrangement without lane dequeue processing. When the host interface is 2×400G, any one of the RS symbols in lane data stream 0 to 15 transmitted to the convolutional interleaving and any one of the RS symbols in lane data stream 16 to 31 transmitted to the convolutional interleaving are from two different outer RS codewords. In the scenario of a 2×400G interface, the transmitter processing module uses the operation procedure in FIG. 12(c) or FIG. 12(d), that is, does not perform the lane rearrangement operation. Nevertheless, it can be guaranteed that 160 information bits in the inner codeword correspond to 16 RS symbols and are from 16 different outer RS codewords. In this case, the delay of the overall concatenated FEC scheme can be reduced, but the ability to withstand burst errors by the concatenated FEC scheme is weakened. Whether to perform lane dequeue processing and lane rearrangement in the transmitter processing module can be determined based on the actual transmission scenario.

[0585] Embodiment 8: The target bit set is represented as a bit matrix, 4 symbols in each column are output continuously, n = 8, m = 8, K = 120, and L = 2.

[0586] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 8 first data streams. These 8 first data streams are separately sent to an inner encoder for inner coding to obtain 8 second data streams. The Hamming code Hamming(128, 120) is used for inner coding. That is, the codeword bit length N = 128, the information bit length K = 120, and the parity bit length P = 8. The 120 information bits in each inner codeword are from 12 symbols in 12 different outer code RS codewords.

[0587] The above 8 inner codewords are used as a set of codewords and include m = 8 Hamming(128, 120) codewords. Considering PAM4 modulation, each L = 2 bits are mapped to 1 PAM4 symbol. 512 PAM4 symbols can be obtained through bit interleaving and mapping of 8 Hamming(128, 120) codewords.

[0588] A total of 1024 bits in the above 8 Hamming(128, 120) codewords are represented by using a first matrix H1 with 8 rows and 128 columns. Each row in the first matrix H1 contains 128 bits in 1 inner code Hamming(128, 120) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 8 rows and 128 columns. The interleaving association between the first matrix H1 and the third matrix H3 is for 0 ≤ i < 8,

[0589]

Equation

[0590] is,

[0591]

Number

[0592] represents a truncation operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, 0 < Δ < 120, the non-zero integer θ is a column offset constraint factor, and the integer θ = 1. In this embodiment, typical values of the integer Δ are 20, 30, 50, 60, 70, 90, and 100.

[0593] In the above-described third matrix H3 having 8 rows and 176 columns, each column contains 8 bits. The 8 bits in each column are mapped to 4 PAM4 symbols. In a particular implementation, in each column, 2 bits in the 0th row and the 1st row are mapped to a certain PAM4 symbol, 2 bits in the 2nd row and the 3rd row are mapped to another PAM4 symbol, 2 bits in the 4th row and the 5th row are mapped to yet another PAM4 symbol, and 2 bits in the 6th row and the 7th row are mapped to yet another PAM4 symbol. The 8 codewords undergo bit interleaving and are then mapped in total to 512 PAM4 symbols, and the 512 consecutive PAM4 symbols in the first modulation symbol stream consist of those 512 PAM4 symbols. In a particular implementation, the 4 PAM4 symbols obtained through the mapping of each column are used as 4 consecutive PAM4 symbols in the first modulation symbol stream, and the 512 PAM4 symbols obtained through the mapping of 128 columns are used as 512 consecutive PAM4 symbols in the first modulation symbol stream.

[0594] In this embodiment, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise with a width of up to 4 PAM4 symbols and can withstand burst errors longer than 1200 bits.

[0595] Embodiment 9: The target bit set is represented as a bit matrix, and 4 symbols in each column are output continuously, where n = 32, m = 8, K = 120, and L = 2.

[0596] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 32 first data streams. FIG. 11 is a diagram of performing inner coding, interleaving, modulation, and mapping on a data stream according to an embodiment of the present application. As shown in FIG. 11, 32 first data streams are separately sent to an inner encoder for inner coding to obtain 32 second data streams. For inner coding, the Hamming code Hamming(128,120) is used. That is, the codeword bit length N = 128, the information bit length K = 120, and the parity bit length P = 8. The 120 information bits in each inner codeword are from 12 symbols in 12 different outer code RS codewords. The 32 second data streams are grouped into 4 second data stream groups. Each group contains 8 second data streams. Through the interleaving and modulation of each second data stream group, 1 modulation symbol stream is obtained. A total of 4 modulation and mapping streams are obtained. The 4 modulation and mapping data streams will be transmitted through 4 different channels. These 4 different channels may be 4 different wavelengths, 4 different optical fibers, etc.

[0597] One Hamming (128, 120) codeword is obtained from each of the above second data streams. A total of 1024 bits out of a total of 8 Hamming (128, 120) codewords are represented by using a first matrix H1 having 8 rows and 128 columns, and each row in the first matrix H1 contains 128 bits in one inner code Hamming (128, 120) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 having 8 rows and 128 columns. The interleaving association between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 8,

[0598] [Number]

[0599] where

[0600] [Number]

[0601] represents a floor operation, a non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, 0 < Δ < 120, a non-zero integer θ is a column offset constraint factor, and the integer θ = 1. In this embodiment, typical values of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, and 110.

[0602] Another interleaving mapping relationship is

[0603] [Number]

[0604] where

[0605] In the above-described third matrix H3 having 8 rows and 176 columns, each column contains 8 bits. The 8 bits in each column are mapped to 4 PAM4 symbols. In a particular implementation, in each column, 2 bits in the 0th row and the 1st row are mapped to a certain PAM4 symbol, 2 bits in the 2nd row and the 3rd row are mapped to another PAM4 symbol, 2 bits in the 4th row and the 5th row are mapped to yet another PAM4 symbol, and 2 bits in the 6th row and the 7th row are mapped to yet another PAM4 symbol. 8 codewords undergo bit interleaving and are then mapped to a total of 512 PAM4 symbols. The 512 consecutive PAM4 symbols in the first modulation symbol stream consist of those 512 PAM4 symbols.

[0606] In this embodiment, according to the designed bit interleaving and mapping method, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to 8 PAM4 symbols on each channel and can withstand burst errors longer than 1100 bits.

[0607] Note that the operation procedure of the transmitter processing module can alternatively be as shown in Fig. 12(b). The lane data stream obtained through the alignment marker lock is directly sent to lane rearrangement without lane dequeue processing. In this case, the delay of the overall concatenated FEC strategy can be reduced, but the ability to withstand burst errors by the concatenated FEC strategy becomes weaker. Whether to perform lane dequeue processing and lane rearrangement in the transmitter processing module can be determined based on the actual transmission scenario.

[0608] Embodiment 10: The target bit set is represented as a bit matrix, where n = 32, m = 8, K = 160, L = 8, L r = 4, and L c = 2.

[0609] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from multiple synchronized client lanes to obtain n = 32 first data streams. The 32 first data streams are separately transmitted to an inner encoder for inner encoding to obtain 32 second data streams. For inner encoding, BCH(176,160) is used. That is, the codeword bit length N = 176, the information bit length K = 160, and the parity bit length P = 16. The 160 information bits in each inner codeword are from 16 symbols in 16 different outer code RS codewords.

[0610] The 32 codewords obtained through inner encoding are grouped into 4 codeword sets, and each codeword set contains m = 8 BCH(176,160) codewords. Considering DP-16QAM modulation, each L = 8 bits are mapped to 1 DP-16QAM symbol. The 176 DP-16QAM symbols are obtained through bit interleaving and mapping of the 8 BCH(176,160) codewords in each codeword set.

[0611] A total of 1408 bits in the above 8 BCH(176,160) codewords are represented by using a first matrix H1 with 8 rows and 176 columns, and each row in the first matrix H1 contains 176 bits in 1 inner code BCH(176,160) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 8 rows and 176 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 8,

[0612]

Number

[0613] and

[0614]

Number

[0615] represents a truncation operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, 0 < Δ < 160, and the integer is a column offset constraint factor. In this embodiment, typical values of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150.

[0616] In the above-mentioned third matrix H3 having 8 rows and 176 columns, each column contains 8 bits. L r = 4 and L c = 2 are considered, and a total of 8 bits in 2 columns out of each 4 rows are mapped to 1 DP-16QAM symbol. In the third matrix H3, the 2 modulation symbols obtained through the mapping of each 2 columns are used as 2 consecutive modulation symbols in the first modulation symbol stream, and the 176 modulation symbols obtained through the mapping of 176 columns are used as 176 consecutive modulation symbols in the first modulation symbol stream and as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0617] Each of the 8 codewords out of 32 codewords undergoes bit interleaving and is then mapped to 176 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to a total of 704 DP-16QAM symbols, and those 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0618] Embodiment 11: The target bit set is represented as a bit matrix, where n = 32, m = 16, K = 160, L = 8, L r = 4, and L c = 2.

[0619] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 32 first data streams. The 32 first data streams are separately transmitted to an inner encoder for inner encoding to obtain 32 second data streams. For inner encoding, BCH(176,160) is used. That is, the codeword bit length N = 176, the information bit length K = 160, and the parity bit length P = 16. The 160 information bits in each inner codeword are from 16 symbols in 16 different outer code RS codewords.

[0620] The 32 codewords obtained through inner encoding are grouped into two codeword sets, and each codeword set contains m = 16 BCH(176,160) codewords. Considering DP-16QAM modulation, each L = 8 bits is mapped to one DP-16QAM symbol. Through bit interleaving and mapping of the 16 BCH(176,160) codewords in each codeword set, 352 DP-16QAM symbols can be obtained.

[0621] A total of 1408 bits in the above-mentioned 16 BCH(176,160) codewords are represented by using a first matrix H1 with 16 rows and 176 columns. Each row in the first matrix H1 contains 176 bits in one inner code BCH(176,160) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 176 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 16,

[0622]

Number

[0623] where

[0624]

Number

[0625] represents a truncation operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, 0 < Δ < 160, and this integer is a column offset constraint factor. In this embodiment, typical values of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150.

[0626] In the above-mentioned third matrix H3 having 16 rows and 176 columns, each column contains 16 bits. L r = 4 and L c = 2 are considered, and a total of 8 bits in 2 columns out of each 4 rows are mapped to 1 DP-16QAM symbol. Each 2 columns in the third matrix H3 are mapped to obtain 4 DP-16QAM symbols.

[0627] Regarding the first 2 DP-16QAM symbols (i.e., the 0th and 1st DP-16QAM symbols obtained through the mapping of each 2 columns) among the 4 DP-16QAM symbols obtained through the mapping of each 2 columns in the third matrix H3, a total of 176 DP-16QAM symbols among the 176 columns are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream. Regarding the last 2 DP-16QAM symbols (i.e., the 2nd and 3rd DP-16QAM symbols obtained through the mapping of each 2 columns) among the 4 DP-16QAM symbols obtained through the mapping of each 2 columns, a total of 176 DP-16QAM symbols among the 176 columns are used as the next 176 consecutive DP-16QAM symbols in the first modulation symbol stream. Finally, 352 consecutive DP-16QAM symbols in the first modulation symbol stream are obtained.

[0628] Each of the 16 codewords out of the 32 codewords undergoes bit interleaving and is then mapped to 352 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to a total of 704 DP-16QAM symbols, and those 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0629] Embodiment 12: The target bit set is represented as a bit matrix, where n = 32, m = 16, K = 110, and L = 8.

[0630] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 32 first data streams. The 32 first data streams are separately sent to an inner encoder for inner coding to obtain 32 second data streams. For inner coding, BCH(126, 110) is used. That is, the codeword bit length N = 126, the information bit length K = 160, and the parity bit length P = 16. The 110 information bits in each inner codeword are from 11 symbols in 11 different outer code RS codewords.

[0631] The 32 codewords obtained through inner coding are grouped into h = 2 codeword sets, and each codeword set contains m = 16 BCH(176, 160) codewords. Considering DP-16QAM modulation, each L = 8 bits is mapped to 1 DP-16QAM symbol. Through bit interleaving and mapping of the 16 BCH(126, 110) codewords in each codeword set, 252 DP-16QAM symbols can be obtained.

[0632] Among the above 16 BCH(126,110) codewords, a total of 2016 bits are represented by using a first matrix H1 having 16 rows and 126 columns. Each row in the first matrix H1 contains 126 bits of one inner code BCH(126,110) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 having 16 rows and 126 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 16,

[0633]

Number

[0634] where

[0635]

Number

[0636] represents a floor operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -110 < Δ < 110, the non-zero integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 50, 60, 70, 90, and 100, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0637] In the above-described third matrix H3 having 16 rows and 126 columns, each column contains 16 bits. Each of the 8 bits out of the 16 bits is mapped to 1 DP-16QAM symbol. Each column is separately mapped to 2 modulation symbols. In a particular implementation, in each column, rows 0 to 7 are mapped to one DP-16QAM symbol, and rows 8 to 15 are mapped to the other DP-16QAM symbol. Each third matrix H3 is mapped to 252 DP-16QAM symbols. The 2 DP-16QAM symbols obtained through the mapping of each column are used as 2 consecutive DP-16QAM symbols in the first modulation symbol stream, and the 252 DP-16QAM symbols obtained through the mapping of 126 columns are used as 252 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0638] Each of the 16 codewords out of the 32 codewords undergoes bit interleaving and is then mapped to 252 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to a total of 504 DP-16QAM symbols, and those 504 DP-16QAM symbols are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0639] In this embodiment, there is colored noise in the actual transmission. When the colored noise has a width of four DP-16QAM symbols, 32 error bits may be scattered among a plurality of inner code BCH(126,110), and the amount of error bits corresponding to each inner code is not more than 2. Since it is considered that the inner code BCH(126,110) can correct 2 bits, colored noise with a width of two or three DP-16QAM symbols can be effectively corrected by the inner code. In addition, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can withstand burst errors longer than 1200 bits. That is, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise with a width of up to four DP-16QAM symbols and can withstand burst errors longer than 1200 bits. According to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise with a width of up to four DP-16QAM symbols and can withstand burst errors longer than 1200 bits.

[0640] Embodiment 13: The target bit set is represented as an array, where n = 32, m = 16, K = 110, and L = 8.

[0641] Based on the scheme of Embodiment 12, a total of 2016 bits among 16 BCH(126,110) codewords are represented by using a first matrix H1 having 16 rows and 126 columns. The data obtained through the bit interleaving of the first matrix H1 is not represented by using a third matrix H3 having 16 rows and 126 columns shown in Embodiment 1, but is represented by using an array A having a length of 2016 bits. Bit interleaving is performed on the first matrix H1 to obtain an array A having a length of 2016 bits. The correspondence of the interleaving between the first matrix H1 and the array A is such that for 0 ≦ i < 16,

[0642]

Number

[0643] and

[0644] [Number]

[0645] represents a truncation operation, a non - zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, - 110 < Δ < 110, a non - zero integer θ is a column offset constraint factor, and the integer θ satisfies - 8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 50, 60, 70, 90, and 100, a typical value of the integer θ is θ = 7, and another typical value is θ = 1. In particular, for 0 ≦ i < 16,

[0646] [Number]

[0647] is

[0648] Each of the eight consecutive bits in the first array A containing 2016 bits is mapped to one DP - 16QAM symbol, obtaining 252 DP - 16QAM symbols, and these 252 DP - 16QAM symbols are used as 252 consecutive DP - 16QAM symbols in the first modulation symbol stream.

[0649] Each of the 16 codewords out of 32 codewords undergoes bit interleaving and is then mapped to 252 DP - 16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to a total of 504 DP - 16QAM symbols, and the 504 DP - 16QAM symbols are used as 504 consecutive DP - 16QAM symbols in the first modulation symbol stream.

[0650] When the values of the row offset constraint factor Δ and the column offset constraint factor θ in Embodiment 11 are equal to the values of Δ and θ in Embodiment 12 respectively, it should be noted that the same 504 DP-16QAM symbols as those in Embodiment 12 can be obtained in Embodiment 11 through bit interleaving and mapping of 32 codewords.

[0651] In this embodiment, according to the designed bit interleaving and mapping method, the overall concatenated FEC scheme can effectively withstand colored noise with a width of up to 4 DP-16QAM symbols and can withstand burst errors longer than 1200 bits.

[0652] Embodiment 14: The target bit set is represented as a bit matrix, where n = 32, m = 8, K = 110, L = 8, L r = 4, and L c = 2.

[0653] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 32 first data streams. The 32 first data streams are separately transmitted to an inner encoder for inner encoding to obtain 32 second data streams. For inner encoding, BCH(126,110) is used. That is, the codeword bit length N = 126, the information bit length K = 110, and the parity bit length P = 16. The 110 information bits in each inner codeword are from 11 symbols in 11 different outer code RS codewords.

[0654] The 32 coded words obtained through inner symbol coding are grouped into 4 coded word sets, and each coded word set contains m = 8 BCH(126, 110) coded words. Considering DP-16QAM modulation, each L = 8 bits is mapped to 1 DP-16QAM symbol. Through bit interleaving and mapping of the 8 BCH(126, 110) coded words in each coded word set, 126 DP-16QAM symbols can be obtained.

[0655] A total of 1008 bits in the above-mentioned 8 BCH(126, 110) coded words are represented by using a first matrix H1 with 8 rows and 126 columns. Each row in the first matrix H1 contains 126 bits in 1 inner code BCH(126, 110) coded word. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 8 rows and 126 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 8,

[0656]

Number

[0657] where

[0658]

Number

[0659] represents a floor operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -100 < Δ < 100, and the non-zero integer Δ is a column offset constraint factor. In this embodiment, typical values of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, and 100.

[0660] In the above-mentioned third matrix H3 with 8 rows and 126 columns, each column contains 8 bits. L r = 4 and L cConsidering =2, a total of 8 bits in 2 columns out of each 4 rows are mapped to 1 DP-16QAM symbol. In the third matrix H3, the 2 modulated symbols obtained through the mapping of each 2 columns are used as 2 consecutive modulated symbols in the first modulated symbol stream, and the 126 modulated symbols obtained through the mapping of 126 columns are used as 126 consecutive modulated symbols in the first modulated symbol stream, and are used as 126 consecutive DP-16QAM symbols in the first modulated symbol stream.

[0661] Each of the 8 codewords out of 32 codewords undergoes bit interleaving and is then mapped to 126 DP-16QAM symbols. The 32 codewords undergo bit interleaving and are then mapped to a total of 504 DP-16QAM symbols, and those 504 DP-16QAM symbols are used as 504 consecutive DP-16QAM symbols in the first modulated symbol stream.

[0662] Embodiment 15: The target bit set is represented as a bit matrix, where n = 16, m = 16, K = 120, and L = 8.

[0663] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 16 first data streams. The 16 first data streams are separately transmitted to an inner encoder for inner encoding to obtain 16 second data streams. For inner encoding, BCH(136,120) is used. That is, the codeword bit length N = 136, the information bit length K = 120, and the parity bit length P = 16. The 120 information bits in each inner codeword are from 12 symbols in 12 different outer code RS codewords.

[0664] The 16 coded words obtained through inner symbol coding are used as a set of h = 1 coded words, and this set of coded words contains m = 16 BCH(136, 120) coded words. Considering DP-16QAM modulation, each L = 8 bits is mapped to one DP-16QAM symbol. Through bit interleaving and mapping of the 16 BCH(136, 120) coded words in each set of coded words, 272 DP-16QAM symbols can be obtained.

[0665] A total of 2176 bits in the above-mentioned 16 BCH(136, 120) coded words are represented by using a first matrix H1 with 16 rows and 136 columns. Each row in the first matrix H1 contains 136 bits in one inner code BCH(136, 120) coded word. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 136 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 16,

[0666]

Number

[0667] where

[0668]

Number

[0669] represents a floor operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -120 < Δ < 120, the non-zero integer θ is a column offset constraint factor, and the non-zero integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, and 110, a typical value of the integer θ is θ = 7, and another typical value is θ = 1.

[0670] In the above-mentioned third matrix H3 having 16 rows and 136 columns, each column contains 16 bits. Each of the 8 bits within the 16 bits is mapped to one DP-16QAM symbol. Each column is separately mapped to two modulation symbols. In a specific implementation, in each column, the 0th row to the 7th row are mapped to one DP-16QAM symbol, and the 8th row to the 15th row are mapped to the other DP-16QAM symbol. Each of the third matrices H3 is mapped to 272 DP-16QAM symbols. The two DP-16QAM symbols obtained through the mapping of each column are used as two consecutive DP-16QAM symbols in the first modulation symbol stream, and the 272 DP-16QAM symbols obtained through the mapping of 136 columns are used as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0671] In this embodiment, there is colored noise in actual transmission. When the colored noise has a width of 4 DP-16QAM symbols, 32 error bits may be scattered among multiple inner codes BCH(136,120), and the amount of error bits corresponding to each inner code is not more than 2. Since the inner code BCH(136,120) can correct 2 bits, the colored noise with a width of 2 or 3 DP-16QAM symbols can be effectively corrected by that inner code. In addition, according to the designed bit interleaving and mapping method, the overall concatenated FEC strategy can withstand burst errors longer than 1200 bits. That is, according to the designed bit interleaving and mapping method, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to 4 DP-16QAM symbols and can withstand burst errors longer than 1200 bits. According to the designed bit interleaving and mapping method, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to 4 DP-16QAM symbols and can withstand burst errors longer than 1200 bits.

[0672] Embodiment 16: The target bit set is represented as an array, where n = 16, m = 16, K = 120, and L = 8.

[0673] Based on the strategy of Embodiment 15, a total of 2176 bits among the 16 BCH(136, 120) codewords are represented by using a first matrix H1 having 16 rows and 136 columns. The data obtained through the bit interleaving of the first matrix H1 is not represented by using a third matrix H3 having 16 rows and 136 columns shown in Embodiment 1, but is represented by using an array A having a length of 2176 bits. Bit interleaving is performed on the first matrix H1 to obtain an array A having a length of 2176 bits. The interleaving association between the first matrix H1 and the array A is, for 0 ≦ i < 16,

[0674]

Number

[0675] where

[0676]

Number

[0677] represents a floor operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, -120 < Δ < 120, the non-zero integer θ is a column offset constraint factor, and the integer θ satisfies -8 < θ < 8. In this embodiment, typical values of the integer Δ are 10, 20, 30, 50, 60, 70, 90, 100, and 110, a typical value of the integer θ is θ = 7, another typical value is θ = 1, and in particular, for 0 ≦ i < 16,

[0678]

Number

[0679] where

[0680] Each of eight consecutive bits in the first array A containing 2176 bits is mapped to one DP-16QAM symbol, obtaining 272 DP-16QAM symbols, and these 272 DP-16QAM symbols are used as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.

[0681] In this embodiment, according to the designed bit interleaving and mapping method, the overall concatenated FEC strategy can effectively withstand colored noise with a width of up to four DP-16QAM symbols and can withstand burst errors longer than 1200 bits.

[0682] Embodiment 17: The target bit set is represented as a bit matrix, where n = 16, m = 8, K = 120, L = 8, L r = 4, and L c = 2.

[0683] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 16 first data streams. The 16 first data streams are separately transmitted to an inner encoder for inner encoding to obtain 16 second data streams. For inner encoding, BCH(136, 120) is used. That is, the codeword bit length N = 136, the information bit length K = 120, and the parity bit length P = 16. The 120 information bits in each inner codeword are from 12 symbols in 12 different outer code RS codewords.

[0684] The 16 coded words obtained through inner symbol coding are grouped into two coded word sets, and each coded word set contains m = 8 BCH(136, 110) coded words. Considering DP-16QAM modulation, each L = 8 bits is mapped to one DP-16QAM symbol. Through bit interleaving and mapping of the 8 BCH(136, 120) coded words in each coded word set, 136 DP-16QAM symbols can be obtained.

[0685] A total of 1088 bits in the above-mentioned 8 BCH(136, 120) coded words are represented by using a first matrix H1 having 8 rows and 136 columns. Each row in the first matrix H1 contains 136 bits in one inner code BCH(136, 120) coded word. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 having 8 rows and 136 columns. The interleaving association between the first matrix H1 and the third matrix H3 is, for 0 ≦ i < 8,

[0686]

Number

[0687] where

[0688]

Number

[0689] represents a floor operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, 0 < Δ < 120, and this integer is a column offset constraint factor. In this embodiment, typical values of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, and 110.

[0690] In the above-mentioned third matrix H3 having 8 rows and 136 columns, each column contains 8 bits. L r = 4 and L cConsidering =2, a total of 8 bits in 2 columns out of each 4 rows are mapped to 1 DP-16QAM symbol. In the third matrix H3, the 2 modulated symbols obtained through the mapping of each 2 columns are used as 2 consecutive modulated symbols in the first modulated symbol stream, and the 136 modulated symbols obtained through the mapping of 136 columns are used as 136 consecutive modulated symbols in the first modulated symbol stream and used as 136 consecutive DP-16QAM symbols in the first modulated symbol stream.

[0691] Each of the 8 codewords out of 16 codewords undergoes bit interleaving and then is mapped to 136 DP-16QAM symbols. The 16 codewords undergo bit interleaving and then are mapped to a total of 272 DP-16QAM symbols, and those 272 DP-16QAM symbols are used as 272 consecutive DP-16QAM symbols in the first modulated symbol stream.

[0692] Embodiment 18: The target bit set is represented as a bit matrix, where n = 12, m = 12, K = 160, L = 8, L r = 4, and L c = 2.

[0693] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain n = 12 first data streams. The 12 first data streams are separately transmitted to an inner encoder for inner encoding to obtain 12 second data streams. For inner encoding, BCH(176, 160) is used. That is, the codeword bit length N = 176, the information bit length K = 160, and the parity bit length P = 16. The 160 information bits in each inner codeword are from 16 symbols in 16 different outer code RS codewords.

[0694] The 12 coded words obtained through inner symbol coding are used as one set of coded words, and this set of coded words contains m = 12 BCH(176, 160) coded words. Considering DP-16QAM modulation, each L = 8 bits is mapped to one DP-16QAM symbol. Through bit interleaving and mapping of the 12 BCH(176, 160) coded words in each set of coded words, 264 DP-16QAM symbols can be obtained.

[0695] Among the above-mentioned 12 BCH(176, 160) coded words, a total of 2112 bits are represented by using a first matrix H1 with 12 rows and 176 columns, and each row in the first matrix H1 contains 176 bits in one inner code BCH(176, 160) coded word. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 12 rows and 176 columns. The interleaving correspondence between the first matrix H1 and the third matrix H3 is, for 0 ≤ i < 12,

[0696]

Number

[0697] where

[0698]

Number

[0699] represents a floor operation, the non-zero integer Δ is a row offset constraint factor, Δ is a multiple of 10, 0 < Δ < 160, and this integer is a column offset constraint factor. In this embodiment, typical values of the integer Δ are 10, 20, 30, 40, 50, 60, 70, 90, 100, 110, 120, 130, 140, and 150.

[0700] In the above-mentioned third matrix H3 with 12 rows and 176 columns, each column contains 8 bits. L r=4 and L c Considering =2, a total of 8 bits in 2 columns out of 4 rows in each are mapped to 1 DP-16QAM symbol. In the third matrix H3, 3 modulation symbols obtained through the mapping of each 2 columns are used as 3 consecutive modulation symbols in the first modulation symbol stream, and 264 modulation symbols obtained through the mapping of 176 columns are used as 264 consecutive DP-16QAM modulation symbols in the first modulation symbol stream.

[0701] It should be noted that all of the above embodiments describe the operation steps in the data processing method shown in FIG. 3. In actual application examples, the operations implemented by the transmitter processing module 02 shown in FIG. 2 include, but are not limited to, the data processing method shown in FIG. 3. The following describes other operations implemented by the transmitter processing module 02 with reference to some specific implementation forms.

[0702] Implementation form 1: The operation procedure used by the transmitter processing module in a 1×800G interface scenario.

[0703] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n first data streams, where n is an integer greater than 1. The first data processing may include alignment lock, lane de-skew processing, lane reorder processing, concatenated interleaving processing, etc. This embodiment provides specific details of the first data processing.

[0704] Fig. 12(a) is a diagram of a first operation procedure of a transmitter processing module according to an embodiment of the present application. As shown in Fig. 12(a), the Physical Medium Attachment (PMA) sublayer of the transmitter processing module processes data from a plurality of synchronized client lanes to obtain a plurality of outer-coded lane data streams, and performs alignment lock and lane de-skew processing using an alignment marker to obtain a plurality of aligned lane data streams. Then, a lane reordering process is performed on the data on the plurality of lanes based on the alignment marker so that the data on the plurality of lanes can be arranged in a specified order. The lane data stream obtained through lane reordering is transmitted to a concatenated interleaver for data order scrambling processing to obtain n first data streams, and the n first data streams are separately transmitted to an inner encoder for inner coding. Designed bit interleaving and mapping are performed on the data stream obtained through inner coding to obtain modulation symbols, and then the modulation symbols are subjected to data processing and then transmitted to a channel transmission medium for transmission. The data processing may include polarization distribution, DSP framing processing, and the like. Here, n is a positive integer greater than 1.

[0705] Note that both the lane de-skew processing and lane reordering in Fig. 12(a) are optional. Fig. 12(b) is a diagram of a second operation procedure of the transmitter processing module according to an embodiment of the present application. As shown in Fig. 12(b), the lane data stream obtained through the alignment lock is directly transmitted to the lane reordering without lane de-skew processing. Fig. 12(c) is a diagram of a third operation procedure of the transmitter processing module according to an embodiment of the present application. As shown in Fig. 12(c), the lane data stream obtained through the alignment lock is directly transmitted to the concatenated interleaving without lane reordering after undergoing the lane de-skew processing. Fig. 12(d) is a diagram of a fourth operation procedure of the transmitter processing module according to an embodiment of the present application. As shown in Fig. 12(d), the lane data stream obtained through the alignment lock is directly transmitted to the concatenated interleaving without lane de-skew processing and lane reordering. Note that in the procedures of the transmitter processing module shown in Fig. 12(b) and Fig. 12(d), the lane de-skew processing is not performed on the lane data stream obtained through the alignment lock. In this case, the data in each lane data stream is required to be aligned based on the outer code symbols. More specifically, for example, KP4 is used for outer code encoding. The amount of skew bits of any two lane data streams is a multiple of 10. That is, the data in the lane data stream is aligned based on the KP4 RS symbols.

[0706] FIG. 13 is a diagram of a 1×800G interface scenario according to an embodiment of the present application. FIG. 13 is a diagram of 32 physical coding sublayer (PCS) lane data streams corresponding to a case where a transmitter device uses a 1×800G interface. The transmitter device performs outer coding on one lane of the 800-GbE service data stream to be transmitted by using a KP4 RS(544,514) code to obtain 32 PCS lane data streams. 68 consecutive symbols are obtained from each of PCS lane data streams 0 to 15, for a total of 1088 symbols. PCS lane data streams 0 to 15 contain two RS codewords. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from different RS codewords. Similarly, each of PCS lane data streams 16 to 31 is separated by only 68 symbols, for a total of 1088 symbols. PCS lane data streams 16 to 31 contain two RS codewords. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from different RS codewords. The 32 PCS lane data streams undergo PMA processing and are then transmitted to a transmitter processing module through a connection unit interface 800G AUI-8.

[0707] Based on the above figure of the data processing of the transmitter processing module shown in FIG. 12(a), the transmitter processing module performs an alignment lock on the lane data stream by using an alignment marker known to the PCS lane. Here, the alignment markers known to 32 channels are different (see Ethernet Technology Consortium 800G Specification). The transmitter processing module then performs a lane de-skew process on the 32 lane data streams to obtain 32 aligned lane data streams. Then, based on the alignment marker, a lane reorder process is performed on the data on the 32 lanes so that the data on the 32 lanes can be arranged in the specified order. One order is the same as the order in FIG. 13. That is, the lane data streams are arranged from top to bottom from 0 to 31. The 32 PCS lane data streams obtained through lane reordering are sent to a concatenated interleaver for data order scrambling processing to obtain n first data streams, and the n first data streams are separately sent to an inner encoder for inner encoding. After the designed bit interleaving and mapping are performed on the n second data streams obtained through inner encoding, the modulation symbols undergo data processing and are then sent to a channel transmission medium for transmission. Here, it should be noted that the value of n may be equal to 32 or 16.

[0708] Note that the operation procedure of the transmitter processing module can alternatively be as shown in FIG. 12(b). The lane data stream obtained through alignment lock is directly sent to lane reordering without lane de-skew processing. In this case, the delay of the overall concatenated FEC strategy can be reduced, but the ability to withstand burst errors by the concatenated FEC strategy is weakened. Whether to perform lane de-skew processing in the transmitter processing module can be determined based on the actual transmission scenario.

[0709] Implementation form 2: The operation procedure used in the scenario where the transmitter processing module has a 2×400G interface.

[0710] FIG. 14 is a diagram of a 2×400G interface scenario according to an embodiment of the present application. FIG. 14 is a diagram of 32 PCS lane data streams corresponding to a case where a transmitter device uses a 2×400G interface. The transmitter device performs outer coding on two lanes of a 400-GbE service data stream to be transmitted by using a KP4 RS(544,514) code, obtaining two lanes out of a total of 32 PCS lane data streams, with each lane containing 16 PCS lane data streams. Each of the PCS lane data streams from 0 to 15 or from 16 to 31 is separated by 68 symbols, and there are 1088 symbols in total. The PCS lane data streams from 0 to 15 or from 16 to 31 contain two RS codewords. Two adjacent symbols in each PCS lane data stream are from different RS codewords, and two symbols at the same position in two adjacent PCS lane data streams are from different RS codewords. The 32 PCS lane data streams undergo PMA processing and are then transmitted to the transmitter processing module through the connection unit interface 2×400G AUI-4.

[0711] Based on the above figure of the data processing of the transmitter processing module shown in FIG. 12(a), the transmitter processing module performs an alignment lock on 16 lane data streams by using the known alignment markers from PCS lane 0 to 15 or from PCS lane 16 to 31. Here, PCS lanes 0 to 15 may be regarded as PCS lanes 0 to 15 in the first 400G, and PCS lanes 16 to 31 may be regarded as PCS lanes 0 to 15 in the second 400G. The known alignment markers for the 16 lanes in the first 400G are the same as the known alignment markers for the 16 lanes in the second 400G. The transmitter processing module then performs a lane de-skew process on the 32 lane data streams to obtain 32 aligned lane data streams. Then, a lane reorder process is performed on the data on 16 lanes based on the alignment markers of PCS lanes 0 to 15 or PCS lanes 16 to 31 so that the data on the 16 lanes can be arranged in a specified order. Finally, the data on 32 lanes can be arranged in a specified order. One order is the same as the order in FIG. 14. That is, the lane data streams are arranged from top to bottom from 0 to 31. The 32 PCS lane data streams obtained through lane reordering are sent to a concatenated interleaver for data order scrambling processing to obtain n first data streams, and the n first data streams are separately sent to an inner code encoder for inner code encoding. After the designed bit interleaving and mapping are performed on the n second data streams obtained through inner code encoding, the modulation symbols undergo data processing and are then sent to a channel transmission medium for transmission. Here, note that the value of n may be equal to 32 or 16.

[0712] Note that the operation procedure of the transmitter processing module may alternatively be as shown in Fig. 12(b). The lane data stream obtained through the alignment marker lock is directly transmitted to lane rearrangement without lane dequeue processing. Further, considering that the host interface is 2×400G, the RS symbols in any one of lane data streams 0 to 15 transmitted to convolutional interleaving and the RS symbols in any one of lane data streams 16 to 31 transmitted to convolutional interleaving are from two different outer RS codewords. In the scenario of the 2×400G interface, the transmitter processing module may alternatively use the operation procedures of Fig. 12(c) or Fig. 12(d), that is, not perform the lane rearrangement operation. In this case, the delay of the overall concatenated FEC strategy can be reduced, but the ability to withstand burst errors by the concatenated FEC strategy is weakened. Whether to perform lane dequeue processing and lane rearrangement in the transmitter processing module can be determined based on the actual transmission scenario.

[0713] Embodiment 3: The operation procedure used in the scenario where the transmitter processing module is used with another 1×800G interface.

[0714] FIG. 15 is another view of a 1×800G interface scenario according to an embodiment of the present application. FIG. 15 is a view of eight lane data streams corresponding to a case where a transmitter device uses a 1×800G interface. The transmitter device performs outer coding on one lane of an 800-GbE service data stream to be transmitted by using a KP4 RS(544,514) code to obtain eight lane data streams. Each of lane data streams 0 to 7 is separated by 136 symbols, and there are 1088 symbols in total. Lane data streams 0 to 7 include two RS codewords. Two adjacent symbols in each lane data stream are from different RS codewords, and two symbols at the same position in two adjacent lane data streams are from different RS codewords. The eight lane data streams are subjected to PMA processing and then transmitted to a transmitter processing module through a connection unit interface 800G AUI-8. Note that in some specific implementations, the eight lane data streams described above are called eight PCS lane data streams. In other specific implementations, the eight lane data streams described above are called eight FEC lane data streams. This is not particularly limited in this specification.

[0715] Based on the above figure of the data processing of the transmitter processing module shown in FIG. 12(a), the transmitter processing module implements an alignment lock on the lane data stream by using alignment markers known to the lanes. Here, the eight alignment markers known to the lanes are different from each other. The transmitter processing module then performs lane de-skew processing on the eight lane data streams to obtain eight aligned lane data streams. Then, based on the alignment markers, a lane reorder processing is performed on the data on the eight lanes so that the data on the eight lanes can be arranged in a specified order. One order is the same as the order in FIG. 15. That is, the lane data streams are arranged from top to bottom from 0 to 7. The eight lane data streams obtained through lane reordering are sent to a concatenated interleaver for data order scrambling processing to obtain n first data streams, and the n first data streams are separately sent to an inner code encoder for inner code encoding. After the designed bit interleaving and mapping are performed on the n second data streams obtained through inner code encoding, the modulation symbols undergo data processing and are then sent to a channel transmission medium for transmission. Generally, the value of n here is 8.

[0716] Note that the operation procedure of the transmitter processing module can alternatively be as shown in FIG. 12(b). The lane data streams obtained through alignment lock are directly sent to lane reordering without lane de-skew processing. The transmitter processing module may alternatively use the operation procedures in FIG. 12(c) or FIG. 12(d), that is, not perform the lane reordering operation. In this case, the delay of the overall concatenated FEC strategy can be reduced, but the ability to withstand burst errors by the concatenated FEC strategy is weakened. Whether to perform lane de-skew processing and lane reordering in the transmitter processing module can be determined based on the actual transmission scenario.

[0717] Implementation form 4: The operation procedure used for concatenated interleaving in the scenario where the transmitter processing module is a 1×800G interface or a 2×400G interface.

[0718] Based on the above-mentioned implementation form 1 or implementation form 2, this embodiment provides a specific implementation form of the concatenated interleaver. The concatenated interleaver performs data order scrambling processing on 32 PCS lane data streams that receive lane rearrangement to obtain n = 32 first data streams. The following describes the specific structure of the concatenated interleaving.

[0719] FIG. 16 is a first diagram of the concatenated interleaving according to an embodiment of the present application. As shown in FIG. 16, 4 outer code RS symbols are obtained from each of the 32 PCS lane data streams, for a total of 128 symbols, and each symbol contains 10 bits. The 128 RS symbols without lane replacement may be represented by using a matrix of 32 rows and 4 columns, and the 4 symbols in the r-th row are from the PCS lane data stream r. The 128 RS symbols obtained through replacement may also be represented by using a matrix of 32 rows and 4 columns. In the 32 rows and 4 columns of the symbols obtained through lane replacement, the symbols in the 0-th column and the r-th row (0 ≦ r < 32) are from the symbols in the 0-th column and the r-th row without lane replacement, and the symbols in the 1-st column and the r-th row are from the symbols in the 1-st column and the r-th row without lane replacement, and the symbols in the 2-nd column and the

[0720]

Number

[0721] symbols in the r-th row are from the symbols in the 2-nd column and the

[0722]

Number

[0723] from the symbols in the rows of, the second column and the

[0724]

Number

[0725] symbols in the rows of are from the second column and the

[0726]

Number

[0727] from the symbols in the rows of, the third column and the

[0728]

Number

[0729] symbols in the rows of are from the third column and the

[0730]

Number

[0731] from the symbols in the rows of, the third column and the

[0732]

Number

[0733] symbols in the rows of are from the third column and the

[0734]

Number

[0735] It is from the symbols in the row of

[0736] As shown in FIG. 16, lane replacement is performed on a total of 128 RS symbols in 32 rows and 4 columns to obtain 128 replaced RS symbols in 32 rows and 4 columns, and the lane replacement relationship can be represented by using an equation. For the 128 replaced RS symbols in 32 rows and 4 columns, the symbol in the r0-th row and the c0-th column is among the 128 RS symbols in 32 rows and 4 columns where no replacement has been performed, and is from the symbol in the

[0737]

Number

[0738] row of and the symbol in the c0-th column. The 32 data streams obtained through lane replacement are sent to a convolutional interleaver for interleaving and data scrambling.

[0739] FIG. 17 is a diagram of a first structure of a convolutional interleaver according to an embodiment of the present application. As shown in FIG. 17, the convolutional interleaver used in this embodiment includes 4 delay lines. The 4 delay lines respectively include 3Q memory units, 2Q memory units, Q memory units, and 0 memory units. Each memory unit is configured to store 4 RS symbols, and each symbol is 10 bits. In other words, the delay value of delay line 0 is 12Q symbols, the delay value of delay line 1 is 8Q symbols, the delay value of delay line 2 is 4Q symbols, and the delay value of delay line 3 is 0 symbols, that is, there is no delay. The C shown in FIG. 17 r () represents the RS symbol in the data stream r (0 ≦ r < 32) obtained through lane replacement. For example, C r (16t), C r(16t + 1), C r (16t + 2), and C r (16t + 3) are four RS symbols that are in the lane data stream r and are currently input to delay line 0, C r (16t - 48Q), C r (16t - 48Q + 1), C r (16t - 48Q + 2), and C r (16t - 48Q + 3) are four RS symbols output by delay line 0, C r (16t + 4), C r (16t + 5), C r (16t + 6), and C r (16t + 7) are four RS symbols that are in the lane data stream and are next input to delay line 1, C r (16t - 32Q + 4), C r (16t - 32Q + 5), C r (16t - 32Q + 6), and C r (16t - 32Q + 7) are four RS symbols output by delay line 1, C r (16t + 8), C r (16t + 9), C r (16t + 10), and C r (16t + 11) are four RS symbols that are in the lane data stream and are subsequently input to delay line 2, C r (16t - 16Q + 8), C r (16t - 16Q + 9), C r (16t - 16Q + 10), and C r (16t - 16Q + 11) are four RS symbols output by delay line 2, C r (16t + 12), C r (16t + 13), C r (16t + 14), and C r (16t + 15) are four RS symbols that are in the lane data stream and are then input to delay line 3, C r (16t + 12), C r (16t + 13), C r (16t + 14), and C r(16t + 15) are the 4 RS symbols output by delay line 3. When 16Q + 4 ≥ 68, that is, Q ≥ 4, a total of 16 RS symbols C are output after convolutional interleaving. r (16t - 48Q), C r (16t - 48Q + 1), C r (16t - 48Q + 2), C r (16t - 48Q + 3), C r (16t - 32Q + 4), C r (16t - 32Q + 5), C r (16t - 32Q + 6), C r (16t - 32Q + 7), C r (16t - 16Q + 8), C r (16t - 16Q + 9), C r (16t - 16Q + 10), C r (16t - 16Q + 11), C r (16t + 12), C r (16t + 13), C r (16t + 14), and C r (16t + 15) are from 16 different RS codewords. In this embodiment, Q = 4 is used. The delay value of delay line 0 is 48 RS symbols (i.e., a delay of 480 bits), the delay value of delay line 1 is 32 RS symbols (i.e., a delay of 320 bits), the delay value of delay line 2 is 16 RS symbols (i.e., a delay of 160 bits), and the delay value of delay line 3 is 0, that is, there is no delay.

[0740] Implementation form 5: Another operation procedure used for concatenated interleaving in the scenario where the transmitter processing module has a 1×800G interface or a 2×400G interface.

[0741] Based on the above-mentioned implementation form 1 or implementation form 2, this embodiment provides another specific implementation form of the concatenated interleaver. The concatenated interleaver performs data order scrambling processing on 32 PCS lane data streams that receive lane rearrangement to obtain n = 16 first data streams. The following is an explanation of the specific structure of the concatenated interleaving.

[0742] Figure 18 is a second diagram of concatenated interleaving according to an embodiment of the present application. As shown in Figure 18, convolutional interleaving processing is separately performed on 32 PCS lane data streams to obtain 32 third data streams, and multiplexing processing is performed on every two of the 32 third data streams so that a total of 16 first data streams are obtained to obtain the first data stream.

[0743] Figure 19 is a diagram of a second structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 19, the convolutional interleaver used in this embodiment includes four delay lines. Each of the four delay lines includes 3Q storage units, 2Q storage units, Q storage units, and 0 storage units. Each storage unit is configured to store two RS symbols, and each symbol is 10 bits. In other words, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, that is, there is no delay. C shown in Figure 19 r () represents the RS symbols in the lane data stream r (0 ≦ r < 32). For example, C r (8t) and C r (8t + 1) represent two RS symbols that are in the lane data stream r and are currently input to delay line 0, and C r (8t - 24Q) and C r (8t - 24Q + 1) are two RS symbols output by delay line 0, and C r (8t + 2) and C r (8t + 3) represent two RS symbols that are in the lane data stream and are next input to delay line 1, and C r (8t - 16Q + 2) and C r (8t - 16Q + 3) are two RS symbols output by delay line 1, and C r (8t + 4) and C r(8t + 5) represents two RS symbols that are in the lane data stream and follow the delay line 2 and are input, C r (8t - 8Q + 4) and C r (8t - 8Q + 5) are two RS symbols output by the delay line 2, C r (8t + 6) and C r (8t + 7) represents two RS symbols that are in the lane data stream and are then input to the delay line 3, C r (8t + 6) and C r (8t + 7) are two RS symbols output by the delay line 3. When 8Q + 2 ≥ 68, that is, Q ≥ 9, a total of eight RS symbols C r (8t - 24Q), C r (8t - 24Q + 1), C r (8t - 16Q + 2), C r (8t - 16Q + 3), C r (8t - 8Q + 4), C r (8t - 8Q + 5), C r (8t + 6), and C r (8t + 7) are from eight different RS codewords. In this embodiment, Q = 9 is used. The delay value of the delay line 0 is 54 RS symbols (i.e., a delay of 540 bits), the delay value of the delay line 1 is 36 RS symbols (i.e., a delay of 360 bits), the delay value of the delay line 2 is 18 RS symbols (i.e., a delay of 180 bits), and the delay value of the delay line 3 is 0, that is, there is no delay.

[0744] For each pair of two out of the 32 third data streams obtained through the above-mentioned convolutional interleaving process, multiplexing is performed to obtain one first data stream, so a total of 16 first data streams are obtained. As shown in FIG. 18, multiplexing p (0 ≦ p < 16) means multiplexing eight consecutive RS symbols in the third data stream p and eight consecutive RS symbols in the third data stream p + 16 into 16 consecutive symbols in the first data stream p. The above-mentioned 16 consecutive symbols are from 16 RS symbols in 16 different outer code RS codewords. In a specific implementation, eight consecutive RS symbols C p (0), C p (1), C p (2), C p (3), C p (4), C p (5), C p (6), and C p (7) in the third data stream p and eight consecutive RS symbols C p+16 (0), C p+16 (1), C p+16 (2), C p+16 (3), C p+16 (4), C p+16 (5), C p+16 (6), and C p+16 (7) in the third data stream p + 16 become 16 consecutive symbols C p (0), C p (1), C p (2), C p (3), C p (4), C p (5), C p (6), C p (7), C p+16 (0), C p+16 (1), C p+16 (2), C p+16 (3), C p+16 (4), C p+16 (5), C p+16 (6), and C p+16(7) are multiplexed into. In another specific implementation, eight consecutive RS symbols C in the third data stream p p (0), C p (1), C p (2), C p (3), C p (4), C p (5), C p (6), and C p (7) and eight consecutive RS symbols C in the third data stream p + 16 p+16 (0), C p+16 (1), C p+16 (2), C p+16 (3), C p+16 (4), C p+16 (5), C p+16 (6), and C p+16 (7) are the sixteen consecutive symbols C in the first data stream p p (0), C p+16 (0), C p (1), C p+16 (1), C p (2), C p+16 (2), C p (3), C p+16 (3), C p (4), C p+16 (4), C p (5), C p+16 (5), C p (6), C p+16 (6), C p (7), and C p+16 (7) are multiplexed into. Here, the sixteen output symbols C p (0), C p (1), C p (2), C p (3), C p (4), C p (5), C p (6), C p (7), C p+16 (0), C p+16 (1), C p+16 (2), C p+16 (3), C p+16 (4), C p+16 (5), C p+16 (6), and Cp+16 The specific arrangement order of (7) is not limited.

[0745] Implementation form 6: Another operation procedure used for concatenated interleaving in the scenario where the transmitter processing module is a 1×800G interface.

[0746] Based on the above implementation form 3, this embodiment provides another specific implementation form of the concatenated interleaver. The concatenated interleaver performs data order scrambling processing on eight lane data streams that receive lane rearrangement to obtain n = 8 first data streams. The following describes the specific structure of the concatenated interleaving.

[0747] FIG. 20 is a third diagram of the concatenated interleaving according to an embodiment of the present application. As shown in FIG. 20, convolutional interleaving processing is performed on eight lane data streams to obtain eight first data streams.

[0748] FIG. 21 is a diagram of a third structure of the convolutional interleaver according to an embodiment of the present application. As shown in FIG. 21, the convolutional interleaver used in this embodiment includes six delay lines. The six delay lines respectively include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units. Each storage unit is configured to store two RS symbols, and each symbol is 10 bits. In other words, the delay value of delay line 0 is 10Q symbols, the delay value of delay line 1 is 8Q symbols, the delay value of delay line 2 is 6Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 2Q symbols, and the delay value of delay line 5 is 0 symbols, that is, there is no delay. The C shown in FIG. 21 r () represents the RS symbol in the data stream r (0 ≦ r < 8) obtained through lane replacement. For example, C r (12t) and C r(12t + 1) represents two RS symbols that are in the lane data stream r and are currently input to delay line 0, C r (12t - 60Q) and C r (12t - 60Q + 1) are two RS symbols output by delay line 0, C r (12t + 2) and C r (12t + 3) represents two RS symbols that are in the lane data stream and are next input to delay line 1, C r (12t - 48Q + 2) and C r (12t - 48Q + 3) are two RS symbols output by delay line 1, and by analogy, C r (12t + 10) and C r (12t + 11) represents two RS symbols that are in the lane data stream and are subsequently input to delay line 2, C r (12t + 10) and C r (12t + 11) are two RS symbols output by delay line 2. When 12Q + 2 ≥ 68, i.e., Q ≥ 6, the total 12 RS symbols output are C r (12t - 60Q), C r (12t - 60Q + 1), C r (12t - 48Q + 2), C r (12t - 48Q + 3), C r (12t - 36Q + 4), C r (12t - 36Q + 5), C r (12t - 24Q + 6), C r (12t - 24Q + 7), C r (12t - 12Q + 8), C r (12t - 12Q + 9), C r (12t + 10), and C r(12t + 11) is from 12 different RS codewords. In this embodiment, Q = 6 is used. The delay value of delay line 0 is 60 RS symbols (i.e., a delay of 600 bits), the delay value of delay line 1 is 48 RS symbols (i.e., a delay of 480 bits), the delay value of delay line 2 is 36 RS symbols (i.e., a delay of 360 bits), the delay value of delay line 3 is 24 RS symbols (i.e., a delay of 240 bits), the delay value of delay line 4 is 12 RS symbols (i.e., a delay of 120 bits), and the delay value of delay line 5 is 0, i.e., there is no delay.

[0749] Implementation Form 7: Another operation procedure used for concatenated interleaving in the scenario where the transmitter processing module is a 1×800G interface or a 2×400G interface.

[0750] Based on the above-mentioned Implementation Form 4, this embodiment provides a diagram of another structure of the convolutional interleaver. FIG. 22 is a diagram of the fourth structure of the convolutional interleaver according to an embodiment of the present application. As shown in FIG. 22, the convolutional interleaver used in this embodiment includes three delay lines. The three delay lines respectively include 2Q storage units, Q storage units, and 0 storage units. Each storage unit is configured to store 4 RS symbols, and each symbol is 10 bits. In other words, the delay value of delay line 0 is 8Q symbols, the delay value of delay line 1 is 4Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., there is no delay. C shown in FIG. 22 r () represents the RS symbols in the data stream r (0 ≦ r < 32) obtained through lane replacement. For example, C r (16t), C r (16t + 1), C r (16t + 2), and C r (16t + 3) represent the 4 RS symbols in the lane data stream r that are currently input to delay line 0, and C r (16t - 24Q), C r (16t - 24Q + 1), Cr (16t - 24Q + 2), and C r (16t - 24Q + 3) are four RS symbols output by delay line 0, and C r (16t + 4), C r (16t + 5), C r (16t + 6), and C r (16t + 7) represent four RS symbols that are in the lane data stream and are then input into delay line 1, and C r (16t - 12Q + 4), C r (16t - 12Q + 5), C r (16t - 12Q + 6), and C r (16t - 12Q + 7) are four RS symbols output by delay line 1, and C r (16t + 8), C r (16t + 9), C r (16t + 10), and C r (16t + 11) represent four RS symbols that are in the lane data stream and are subsequently input into delay line 2, and C r (16t + 8), C r (16t + 9), C r (16t + 10), and C r (16t + 11) are four RS symbols output by delay line 2. When 12Q + 4 ≥ 68, i.e., Q ≥ 6, a total of 12 RS symbols C are output after convolutional interleaving r (16t - 24Q), C r (16t - 24Q + 1), C r (16t - 24Q + 2), C r (16t - 24Q + 3), C r (16t - 12Q + 4), C r (16t - 12Q + 5), C r (16t - 12Q + 6), C r (16t - 12Q + 7), C r (16t + 8), C r (16t + 9), C r (16t + 10), and C r(16t + 11) is from 12 different RS codewords. In this embodiment, Q = 6 is used. The delay value of delay line 0 is 48 RS symbols (i.e., a delay of 480 bits), the delay value of delay line 1 is 24 RS symbols (i.e., a delay of 240 bits), and the delay value of delay line 2 is 0, i.e., there is no delay.

[0751] Implementation form 8: Another operation procedure used for concatenated interleaving in the scenario where the transmitter processing module has a 1×800G interface or a 2×400G interface.

[0752] Based on the above-mentioned implementation form 5, this embodiment provides a diagram of another structure of the convolutional interleaver. FIG. 23 is a diagram of the fifth structure of the convolutional interleaver according to an embodiment of the present application. As shown in FIG. 23, the convolutional interleaver used in this embodiment includes three delay lines. The three delay lines respectively include 2Q storage units, Q storage units, and 0 storage units. Each storage unit is configured to store 2 RS symbols, and each symbol is 10 bits. In other words, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., there is no delay. The C shown in FIG. 23 r () represents the RS symbols in the lane data stream r (0 ≦ r < 32). For example, C r (6t) and C r (6t + 1) represent the 2 RS symbols that are in the lane data stream r and are currently input to delay line 0, and C r (6t - 12Q) and C r (6t - 12Q + 1) are the 2 RS symbols output by delay line 0, and C r (6t + 2) and C r (6t + 3) represent the 2 RS symbols that are in the lane data stream and are next input to delay line 1, and C r (6t - 6Q + 2) and C r(6t - 6Q + 3) are two RS symbols output by delay line 1, C r (6t + 4) and C r (6t + 5) are two RS symbols that are in the lane data stream and are input following delay line 2, C r (6t + 4) and C r (6t + 5) are two RS symbols output by delay line 2. When 6Q + 2 ≥ 68, i.e., Q ≥ 11, a total of six RS symbols C r (6t - 12Q), C r (6t - 12Q + 1), C r (6t - 6Q + 2), C r (6t - 6Q + 3), C r (6t + 4), and C r (6t + 5) are from six different RS codewords. In this embodiment, Q = 11 is used. The delay value of delay line 0 is 44 RS symbols (i.e., a delay of 440 bits), the delay value of delay line 1 is 22 RS symbols (i.e., a delay of 220 bits), and the delay value of delay line 2 is 0, i.e., there is no delay.

[0753] For each two of the 32 third data streams obtained through the above convolutional interleaving process, multiplexing processing is performed to obtain one first data stream, so a total of 16 first data streams are obtained. As shown in FIG. 18, multiplexing p (0 ≤ p < 16) multiplexes six consecutive RS symbols in the third data stream p and six consecutive RS symbols in the third data stream p + 15 into 12 consecutive symbols in the first data stream p. The above 12 consecutive symbols are from 12 RS symbols in 12 different outer code RS codewords.

[0754] Note that in some actual application examples, different bit interleaving and mapping methods can be selected based on different transmission scenarios. FIG. 24 is a schematic flowchart of data processing according to an embodiment of the present application. As shown in FIG. 24, V bit interleaving and mapping processing modules are provided, where V is an integer greater than 1. The V bit interleaving and mapping processing modules have different burst tolerance capabilities. In a specific application example, inner coding is performed on n first data streams to obtain n second data streams, and one of the bit interleaving and mapping processing modules is selected based on the actual transmission scenario to perform bit interleaving and mapping on the data in the second data stream to obtain a plurality of modulation symbols. The inner coding module in FIG. 24 is configured to perform step 301 in the embodiment shown in FIG. 3, and it should be understood that each bit interleaving and mapping processing module in FIG. 24 is configured to perform steps 302 and 303 in the embodiment shown in FIG. 3. The specific implementation form will not be described again here. In one example, the above-described embodiments 1 to 11 provide a total of 11 different bit interleaving and mapping methods. In this case, 11 bit interleaving and mapping processing modules can be correspondingly provided in FIG. 24 to select the required bit interleaving and mapping processing module based on the actual transmission scenario and perform the bit interleaving and mapping method in the corresponding embodiment.

[0755] The above describes the data processing method provided in the embodiments of the present application. The following describes the data processing device provided in the embodiments of the present application.

[0756] FIG. 25 is a diagram of the structure of a data processing apparatus according to an embodiment of the present application. As shown in FIG. 25, the data processing apparatus includes an encoding module 101, a bit interleaving module 102, and a bit mapping module 103. The encoding module 101 is configured to perform the operation of step 301 in the data processing method shown in FIG. 3. The bit interleaving module 102 is configured to perform the operation of step 302 in the data processing method shown in FIG. 3. The bit mapping module 103 is configured to perform the operation of step 303 in the data processing method shown in FIG. 3. For details, refer to the relevant description of the above data processing method. Details will not be described again here.

[0757] It should be understood that the apparatus provided in the present application may be implemented in another way as an alternative. For example, the division of the units in the above apparatus is only a logical function division, and in an actual implementation form, it may be other divisions. For example, a plurality of units or components may be combined or integrated into another system. In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, each may be an independent physical unit, or two or more functional units may be integrated into one processing unit. The integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0758] In the data processing method of FIG. 3, note that the n inner code codewords are from n second data streams, one inner code codeword is obtained from each second data stream, and bit interleaving is performed on the n inner code codewords. In some specific application examples, the plurality of inner code codewords may alternatively be obtained from each data stream, and bit interleaving is performed on the plurality of inner code codewords. FIG. 26 is another schematic flowchart of a data processing method according to an embodiment of the present application. This method is for data processing performed on an outer code-encoded data stream, and it should be understood that it may specifically be implemented by the above-described transmitter processing module 02.

[0759] 401: Perform interleaving and encoding processes separately on each of the n1 first data streams among the n0 first data streams to obtain one second data stream, and obtain a total of n2 second data streams, where n2 = n0 / n1 and n1 is an integer greater than 0.

[0760] In this embodiment, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 first data streams, where n0 is an integer greater than 1. The first data processing may include alignment lock, lane de-skew processing or lane alignment processing, lane reorder processing, symbol mux processing, etc. All of the above-mentioned n0 first data streams are outer-coded data streams. For example, an RS code may be used for outer coding, and the n outer-coded data streams may include a plurality of RS codewords. For example, the outer code is a KP4 RS(544,514) code used, the code length is 544 symbols, and one outer code symbol includes 10 bits.

[0761] The following describes a specific operation of performing interleaving and coding processing on n1 first data streams to obtain one second data stream. The interleaving and coding processing includes inner coding, cyclic shift, round-robin reading, etc.

[0762] FIG. 27 is a diagram of a first implementation form of the interleaving and coding processing. As shown in FIG. 27(a), in the interleaving and coding processing, inner coding is first performed, then cyclic shift is performed, and then round-robin reading is performed. It should be understood that each of the first data streams includes at least a0 first bit sets, each of the first bit sets includes K bits, and the integer a0>1. For the n1 first data streams, a0 first bit sets are obtained from each of the first data streams, and a total of m = n1×a0 first bit sets are obtained, including a total of n1×a0×K bits.

[0763] As shown in Fig. 27(b), for each of the m first bit sets containing K bits, inner coding is performed, and P parity bits are added to obtain an inner codeword containing N bits. Thus, a total of m inner codewords are obtained. Here, the first bit set containing K bits may be called an inner code information sequence, and K + P = N. The P parity bits are also called a parity bit set. One inner codeword includes one first bit set and one parity bit set. In other words, the m inner codewords include m first bit sets and m parity bit sets. Generally, K is a multiple of 10. Note that in the materials of this application, the inner codeword is also abbreviated as a codeword.

[0764] Note that in order to enable K information bits to correspond to a large number of KP4 outer code symbols, for example, to correspond to K / 10 outer code symbols, and to enable those corresponding outer code symbols to be from a large number of outer codewords, so as to achieve good concatenated FEC performance as a whole, normally convolutional interleaving processing is further performed before inner coding. For example, when K = 120, the 120 information bits correspond to 12 KP4 outer code symbols, and the 12 KP4 outer code symbols are from 12 outer codewords.

[0765] Note that in some scenarios where low latency is required, normally convolutional interleaving processing is not performed before inner coding. The K information bits correspond to K / 10 outer code symbols, and the corresponding outer code symbols are from less than K / 10 outer codewords. For example, when K = 120, the 120 information bits correspond to 12 KP4 outer code symbols, and the 12 KP4 symbols are from 4 outer codewords.

[0766] As shown in Fig. 27(b), for the information bit sequences of m inner code codewords, i.e., m first bit sets, in a cyclic shift, for each first bit set

[0767]

Number

[0768] a left cyclic shift of bits is performed, or a right cyclic shift of δ bits is performed for each first bit set, to obtain one second bit set containing K bits. Each second bit set is combined with the parity bits of length P in the inner code codeword corresponding to the second bit set to obtain one third bit set containing N bits. It should be noted that the third bit set containing N bits is obtained by performing a cyclic shift on the information bit sequence (first bit set) containing K bits and in the inner code codeword, and combining the information bit sequence obtained through the cyclic shift with the parity bits of length P and in the inner code codeword. For the sake of simplicity of description, in the materials of this application, the third bit set containing N bits is simply described as being obtained by performing a cyclic shift process on the inner code codeword containing N bits.

[0769] A left cyclic shift is used as an example. For the first bit set (u0, u1, u2, u3, …, u K-2 , u K-1 ) containing K bits,

[0770]

Number

[0771] a left cyclic shift of bits is performed to obtain a second bit set containing K bits and obtained through this shift

[0772]

Number

[0773] is obtained, where Y%Z represents the remainder obtained by dividing the integer Y by the integer Z. Generally, the offset constraint factor

[0774]

Number

[0775] is a multiple of 10,

[0776]

Number

[0777] and is.

[0778] A right circular shift is used as an example. For a first bit set (u0, u1, u2, u3, …, u K-2 , u K-1 ) containing K bits, a right circular shift of δ bits is performed to obtain a second bit set (u (-δ)%K , u (1-δ)%K , u (2-δ)%K , …, u (K-2-δ)%K , u (K-1-δ)%K ) containing K bits obtained through the shift, where Y%Z represents the remainder obtained by dividing the integer Y by the integer Z. Generally, the offset constraint factor δ of the right circular shift is a multiple of 10 and 0 ≦ δ < K.

[0779]

Number

[0780] Obtaining the second bit set by performing a left circular shift of bits on the first bit set is

[0781]

Number

[0782] Note that obtaining the second bit set by performing a right circular shift of bits on the first bit set is equivalent.

[0783] Offset constraint factor of left circular shift

[0784]

Number

[0785] Note that the offset constraint factor δ of the right circular shift is not fixed and can change over time. Generally, the period of the circular shift is p c is. In the circular shift, for the i-th group of the first bit set containing K bits

[0786]

Number

[0787] a left circular shift of bits is performed, or, for the i-th group of the first bit set containing K bits, δ i a right circular shift of bits is performed, m is an integer multiple of p c and 0 ≦ i < p c is. Usually, m = p c is. Usually, m offset constraint factors

[0788]

Number

[0789] (i.e.,

[0790]

Number

[0791] ) of any two

[0792] [Number]

[0793] The values are not equal to each other, and for the m offset constraint factors δ i (i.e., δ0, δ1, …, δ m-1 ) any two δ values among them are not equal to each other.

[0794] As shown in FIG. 27(b), for the m third bit sets output through cyclic shift, in round-robin reading, 2 bits are obtained from each third bit through round-robin, and consecutive m×N / 2 operations are performed to obtain all of the m third bit sets and obtain a fourth bit set including m×N bits.

[0795] The second data stream includes a plurality of fourth bit sets. The fourth bit set including m×N bits is obtained by performing 2-bit round-robin reading on the m third bit sets. The m third bit sets each including N bits are obtained by performing information bit cyclic shift on the m inner code codewords. The m inner code codewords are obtained by performing inner code encoding on the m first bit sets. The m first bit sets are obtained by obtaining a0 first bit sets from each of the n1 first data streams, where m = n1×a0.

[0796] "Round-robin reading", specifically obtaining two bits from each of the third bit sets through round-robin to obtain a fourth bit set containing m×N bits, first obtains two bits from each of the m second bit sets through round-robin for the m second bit sets to obtain a total of m×K bits, and then for the parity bit sets in the m inner code codewords, two bits are obtained from each parity bit set through round-robin to obtain a total of m×P bits, and it should be noted that combining the m×K bits obtained from the m second bit sets and the m×P bits obtained from the m parity bit sets is equivalent to an operation of obtaining a fourth bit set containing m×N bits.

[0797] In some specific application examples, the cyclic shift and the round-robin reading operation may be combined, and it should be noted that through a one-step operation, bit interleaving is performed on the m inner code codewords containing m×N bits to obtain the fourth bit set.

[0798] Figure 28 is a diagram of a second implementation form of interleaving and encoding processing. As shown in Figure 28, the m first bit sets may be represented by using a first bit matrix M1 having m rows and K columns, and each row in the first bit matrix M1 contains K bits in one first bit set. The bit in the i-th (0≦i<m) row and the e-th (0≦e<K) column in the first bit matrix M1 is denoted as M1[i][e]. The m inner code codewords may be represented by using an inner code codeword matrix M c and each row in the inner code codeword matrix M c contains N bits in one inner code codeword. The bit in the i-th (0≦i<m) row and the j-th (0≦j<N) column in the inner code codeword matrix M c is denoted as M cIt is denoted as [i][j]. The m second bit sets may be represented by using a second bit matrix M2 having m rows and K columns, where each row in the second bit matrix M2 contains K bits in one second bit set. The bit in the i-th (0 ≤ i < m) row and the e-th (0 ≤ e < K) column in the second bit matrix M2 is denoted as M2[i][e]. The m parity bit sets may be represented by using a parity bit matrix M p and each row in the parity bit matrix M p contains P parity bits in one inner codeword. The bit in the i-th (0 ≤ i < m) row and the f-th (0 ≤ f < P) column in the parity bit matrix M p is denoted as M p [i][f]. The m third bit sets may be represented by using a third bit matrix M3 having m rows and N columns, where each row in the third bit matrix M3 contains N bits in one third bit set. The bit in the i-th (0 ≤ i < m) row and the j-th (0 ≤ j < N) column in the third bit matrix M3 is denoted as M3[i][j]. The fourth bit set containing m×N bits is represented by using an Array. The bit in the k-th (0 ≤ k < m×N) position in the Array A is denoted as A[k].

[0799] As shown in FIG. 28, inner coding is performed on the first bit matrix M1 to obtain an inner codeword matrix M c .

[0800] For the cyclic shift operation, a left cyclic shift is used as an example. For the K information bits in the i-th (0 ≤ i < m) row in the inner codeword matrix M c (i.e., the K bits in the i-th row in the first bit matrix M1),

[0801]

Number

[0802] A left circular shift of the bits is performed to obtain K bits in the i-th (0 ≤ i < m) row in the third bit matrix M3, where a non-zero integer

[0803]

Number

[0804] is the offset constraint factor of the circular shift in the i-th row. In this case, the third bit matrix M3 and the inner codeword matrix M c satisfy the equation (X - 1)

[0805]

Number

[0806] .

[0807] Y % Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≤ i < m. Generally, the offset constraint factor of the left circular shift

[0808]

Number

[0809] is a multiple of 10,

[0810]

Number

[0811] .

[0812] For the K information bits in the i-th row in the first matrix H1,

[0813]

Number

[0814] Note that a left circular shift of bits is performed to obtain K bits from the 0th column to the (K-1)th column in the ith row of the second matrix H2. Equivalently, for the K information bits from the 0th column to the (K-1)th column in the ith row of the first matrix H1,

[0815]

Number

[0816] A right circular shift of bits is performed to obtain K bits from the 0th column to the (K-1)th column in the ith row of the second matrix H2.

[0817] In another example, a right circular shift is used. The third bit matrix M3 and the inner codeword matrix M c satisfy the equation (M-2)

[0818]

Number

[0819] is satisfied.

[0820] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≤ i < m. Generally, the offset constraint factor δ i of the right circular shift is a multiple of 10, and 0 ≤ δ i < K.

[0821] For the K information bits in the ith row of the inner codeword matrix M c , note that a right circular shift of δ i bits is performed to obtain K bits from the 0th column to the (K-1)th column in the ith row of the third bit matrix M3. Equivalently, for the K information bits from the 0th column to the (K-1)th column in the ith row of the third bit matrix M3, a left circular shift of δ i bits is performed to obtain the inner codeword matrix M cObtain the K bits from the 0th column to the (K - 1)th column in the ith row within. In other words, equation (X - 2) can alternatively be equation (X - 3)

[0822]

Number

[0823] and can be written as

[0824] For the inner code symbol word matrix M c a cyclic shift of each row of the information bits is performed to obtain the third bit matrix M3

[0825] As shown in FIG. 28, "round robin reading" means reading 2 bits from each row in the third bit matrix M3 through round robin, and 2 columns in the third bit matrix M3 are obtained continuously for m times, and all m × N bits are read by using m × N / 2 operations in total to obtain an array A including m × N interleaved bits. The bit in the ith row and the jth column in the third bit matrix M3 is output to the bit of the

[0826]

Number

[0827] in the array A. This satisfies equation (X - 4)

[0828]

Number

[0829] where 0 ≤ i < m and 0 ≤ j < N,

[0830]

Number

[0831] represents a floor operation

[0832] Note that the operation of reading two bits from each row in the third bit matrix M3 through round robin is called m-way coded word interleaving.

[0833] Inner code coded word matrix M c For, a cyclic shift is performed on each row of the information bits to obtain the third bit matrix M3, and then two bits are read from each row through round robin. This can be done through a two-step operation or through a one-step operation. The following directly gives the direct mapping relationship between M c and A.

[0834] When a left cyclic shift is used, for equations (X-1) and (X-4), the following equation (X-5)

[0835]

Number

[0836] exists.

[0837] 0 ≦ i < m. Generally, the cyclic shift offset constraint factor

[0838]

Number

[0839] is a multiple of 10,

[0840]

Number

[0841] is. Usually, m offset constraint factors

[0842]

Number

[0843] (That is,

[0844] [Number]

[0845] ) any two of

[0846] [Number]

[0847] have unequal values.

[0848] When a right circular shift is used, for expressions (X - 2) and (X - 4), the following expression (X - 6)

[0849] [Number]

[0850] exists.

[0851] 0 ≤ i < m. Generally, the cyclic shift offset constraint factor δ i is a multiple of 10,

[0852] [Number]

[0853] is true. Usually, any two of the m cyclic shift offset constraint factors δ i (That is, δ0, δ1,..., δ m-1 ) have unequal values.

[0854] Note that the cyclic shift and round-robin reading are performed in one step, which has advantages such as simple implementation and low complexity.

[0855] Note that in the interleaving and encoding processes, the cyclic shift and inner encoding are performed in parallel, and then round-robin reading is performed. The following describes this implementation form.

[0856] Figure 29 is a diagram of a third implementation form of the interleaving and encoding processes. As shown in Figure 29, for n1 first data streams, a0 first bit sets are obtained from each of the first data streams, and a total of m = n1 × a0 first bit sets are obtained, which contain a total of n1 × a0 × K bits.

[0857] As shown in Figure 29(b), in the cyclic shift, for the i-th first bit set among the m first bit sets,

[0858]

Number

[0859] a left cyclic shift of the bits is performed, or δ i a right cyclic shift of the bits is performed to obtain the i-th second bit set containing K bits, and a total of m second bit sets are obtained, where 0 ≤ i < m. Generally, the offset constraint factor

[0860]

Number

[0861] is a multiple of 10,

[0862]

Number

[0863] and the offset constraint factor δ i is a multiple of 10, where 0 ≤ δ iIt is K. Usually, m offset constraint factors

[0864] [Number]

[0865] (That is,

[0866] [Number]

[0867] ) Any two among

[0868] [Number]

[0869] The values are not equal to each other, and for any two of the m offset constraint factors δ i (That is, δ0, δ1,..., δ m-1 ) The values of any two δs are not equal to each other.

[0870] For each of the first bit sets containing K bits and among m first bit sets, inner coding is performed to obtain a parity bit set containing P bits, so a total of m parity bit sets are obtained. In "round-robin reading", first, for m second bit sets, 2 bits are obtained from each second bit set through round-robin, obtaining a total of m×K bits. Then, for m parity bit sets, 2 bits are obtained from each parity bit set through round-robin, obtaining a total of m×P bits, and the m×K bits obtained from m second bit sets and the m×P bits obtained from m parity bit sets are combined to obtain a fourth bit set containing m×N bits.

[0871] FIG. 30 is a diagram of a fourth implementation form of interleaving and encoding processing. As shown in FIG. 30, m first bit sets may be represented by using a first bit matrix M1 having m rows and K columns, and m second bit sets may be represented by using a second bit matrix M2 having m rows and K columns. Specifically, the second bit matrix M2 is obtained by performing a cyclic shift on the first bit matrix M1.

[0872] A left cyclic shift is used as an example. The first bit matrix M1 and the second bit matrix M2 satisfy the formula (X-7)

[0873]

Number

[0874] which is satisfied.

[0875] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0≦i<m and 0≦j<K. Generally, the offset constraint factor of the left cyclic shift

[0876]

Number

[0877] is a multiple of 10,

[0878]

Number

[0879] and is as follows.

[0880] For the K bits in the i-th row in the first bit matrix M1,

[0881]

Number

[0882] Note that a left circular shift of the bits is performed to obtain K bits in the i-th row in the second bit matrix M2. Equivalently, for the K bits in the i-th row in the first bit matrix M1,

[0883]

Number

[0884] a right circular shift of the bits is performed to obtain K bits in the i-th row in the second bit matrix M2.

[0885] In another example, the position transformation is performed through a right circular shift. For the i-th first bit set among the m first bit sets, δ i a right circular shift of the bits is performed, and the non-zero integer δ i is the offset constraint factor of the circular shift corresponding to the i-th bit set. The right circular shift is given by equation (X-8): M2[i][j]=M1[i][(j-δ i )%K] is satisfied.

[0886] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≦ i < m and 0 ≦ j < K. Generally, the offset constraint factor δ i of the right circular shift is a multiple of 10, and 0 ≦ δ i < K.

[0887] For the K bits in the i-th row in the first bit matrix M1, δ i Note that a right circular shift of the bits is performed to obtain K bits in the i-th row in the second bit matrix M2. Equivalently, for the K bits in the i-th row in the second bit matrix M2, δ i a left circular shift of the bits is performed to obtain K bits in the i-th row in the first bit matrix M1. In other words, equation (X-8) can alternatively be equation (X-9): M1[i][j]=M2[i][(j+δi )%K] where 0 ≤ i < m and 0 ≤ j < K can be written as

[0888] As shown in FIG. 30, inner coding is performed on the first bit matrix M1 to obtain a parity bit matrix M p Two bits are read from each row in the second bit matrix M2 through round robin, and all m × K bits in the second bit matrix M2 are read through a total of m × K / 2 operations to obtain bits from the 0th bit to the (m × K - 1)th bit in the array A including m × N interleaved bits. Two bits are read from each row in the parity bit matrix M p through round robin, and all m × P bits in the parity bit matrix M p are read through a total of m × P / 2 operations to obtain bits from the (m × K)th bit to the (m × N - 1)th bit in the array A.

[0889] Note that the cyclic shift and the inner coding are performed in parallel, which has the advantage of low latency.

[0890] Note that in the interleaving and encoding process, the cyclic shift is first performed, then the inner coding is performed, and then the round robin reading is performed. The following describes this implementation form.

[0891] FIG. 31 is a diagram of a fifth implementation form of the interleaving and encoding process. As shown in FIG. 31, for n1 first data streams, a0 first bit sets are obtained from each first data stream, and a total of m = n1 × a0 first bit sets are obtained, including a total of n1 × a0 × K bits.

[0892] As shown in FIG. 31(b), in the cyclic shift, for the i-th first bit set among the m first bit sets,

[0893]

Number

[0894] A left cyclic shift of the bits is performed, or δ i A right cyclic shift of the bits is performed to obtain an i-th second bit set including K bits, and a total of m second bit sets are obtained, where 0 ≦ i < m. Generally, the offset constraint factor of the left cyclic shift

[0895]

Number

[0896] is a multiple of 10,

[0897]

Number

[0898] and the offset constraint factor δ of the right cyclic shift i is a multiple of 10, where 0 ≦ δ i < K. Usually, m offset constraint factors

[0899]

Number

[0900] (That is,

[0901]

Number

[0902] ) of any two

[0903]

Number

[0904] The values are not equal to each other, and there are m offset constraint factors δ i (i.e., δ0, δ1, …, δ m-1 ) and the values of any two δs among them are not equal to each other.

[0905] As shown in FIG. 31(b), for each of the m second bit sets containing K bits, inner coding is performed, and P parity bits are added to obtain an inner codeword containing N bits, so that a total of m inner codewords are obtained.

[0906] As shown in FIG. 31(b), for the m inner codewords, in round-robin reading, 2 bits are obtained from each inner codeword through round-robin, and a total of m×N / 2 consecutive operations are performed to obtain all the bits in the m inner codewords and obtain a fourth bit set containing m×N bits.

[0907] FIG. 32 is a diagram of a sixth implementation form of interleaving and encoding processing. As shown in FIG. 32, the m first bit sets may be represented by using a bit matrix M1 having m rows and K columns, the m second bit sets may be represented by using a bit matrix M2 having m rows and K columns, and the m inner codewords may be represented by using a bit matrix M c having m rows and N columns. The second bit matrix M2 is obtained by performing a cyclic shift on the first bit matrix M1.

[0908] A left cyclic shift is used as an example. The first bit matrix M1 and the second bit matrix M2 satisfy the formula (X - 10)

[0909] [Number]

[0910] .

[0911] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≦ i < m and 0 ≦ j < K. Generally, the offset constraint factor of the left circular shift

[0912]

Number

[0913] is a multiple of 10, and

[0914]

Number

[0915] it is.

[0916] For the K bits in the i-th row in the first bit matrix M1,

[0917]

Number

[0918] note that a left circular shift of the bits is performed to obtain the K bits in the i-th row in the second bit matrix M2. Equivalently, for the K bits in the i-th row in the first bit matrix M1,

[0919]

Number

[0920] a right circular shift of the bits is performed to obtain the K bits in the i-th row in the second bit matrix M2.

[0921] In another example, the position transformation is performed through a right circular shift. For the i-th first bit set among the m first bit sets, δ i a right circular shift of the bits is performed, where δ is a non-zero integer iis the offset constraint factor of the cyclic shift corresponding to the i-th bit set. The right cyclic shift is given by equation (X-11): M2[i][j]=M1[i][(j-δ i )%K] is satisfied.

[0922] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≦ i < m and 0 ≦ j < K. In general, the offset constraint factor δ i of the right cyclic shift is a multiple of 10, and 0 ≦ δ i < K.

[0923] Note that for the K bits in the i-th row of the first bit matrix M1, a right cyclic shift of δ i bits is performed to obtain the K bits in the i-th row of the second bit matrix M2. Equivalently, for the K bits in the i-th row of the second bit matrix M2, a left cyclic shift of δ i bits is performed to obtain the K bits in the i-th row of the first bit matrix M1. In other words, equation (X-11) can alternatively be written as equation (X-12): M1[i][j]=M2[i][(j+δ i )%K] where 0 ≦ i < m and 0 ≦ j < K can be written.

[0924] As shown in FIG. 32, inner code encoding is performed on the second bit matrix M2 to obtain the inner code codeword matrix M c . In "round-robin reading", it means reading 2 bits from each row in the inner code codeword matrix M c through the round-robin. In total, all m×N bits are read through m×N / 2 operations to obtain an array A containing m×N interleaved bits. The bit in the i-th row and j-th column of the inner code codeword matrix M c is the

[0925] [Number]

[0926] is output to the bits. This is the formula (X - 13)

[0927] [Number]

[0928] satisfies, where 0 ≤ i < m, 0 ≤ j < N, and

[0929] [Number]

[0930] represents a floor operation.

[0931] 402: Map each 2 bits in n2 second data streams to 1 PAM4 symbol separately to obtain an n2 PAM4 symbol data stream.

[0932] In PAM4 modulation, each 2 bits are mapped to 1 PAM4 modulation symbol. A fourth bit set or array A containing m × N bits is mapped to m × N / 2 PAM4 modulation symbols. The 2 bits mapped to 1 PAM4 modulation symbol are from 1 inner codeword, and the m × 2 bits mapped to m consecutive PAM4 modulation symbols are from m inner codewords.

[0933] Furthermore, 2 outer code symbols from the same RS outer codeword in 1 first data stream are mapped to multiple PAM4 symbols in the same PAM4 symbol data stream through the above data processing. Any 2 of the multiple PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream, with an appropriate offset constraint factor for left circular shift

[0934]

Number

[0935] or the constraint factor δ of the right cyclic shift offset i is selected. It should be noted that two adjacent PAM4 symbols in one PAM4 symbol data stream are considered to be only one PAM4 symbol apart.

[0936] In some specific application examples, padding bits are periodically inserted into the n2 second data streams before bitmapping is performed on the n2 second data streams, and the padding bits include alignment markers for receiver alignment and synchronization.

[0937] In this embodiment of the present application, a concatenated FEC transmission strategy is used. That is, outer coding and inner coding are sequentially performed on the data stream. Based on this, the present application designs an interleaving and coding processing method so that both the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to modulation symbols. In this way, this concatenated FEC transmission strategy has a strong burst tolerance ability. In particular, short burst errors can be directly corrected through inner code decoding. This concatenated FEC transmission strategy is widely applicable to transmission scenarios, especially actual coherent transmission scenarios where there is colored noise on the channel.

[0938] In the material of this application, it should be noted that in round-robin reading, 2 bits are obtained from each third bit set through the round-robin to obtain a fourth bit set containing m×N bits. That is, until all m×N bits are obtained, 2 bits are obtained from the 0th third bit set, 2 bits are obtained from the 1st third bit set,..., 2 bits are obtained from the m-1th third bit set, and then 2 bits are obtained from the 0th third bit set. In some specific implementations, the order of round-robin reading can be changed. Correspondingly, in the circular shift operation, the offset constraint factor

[0939]

Number

[0940] or the offset constraint factors δ0, δ1,..., δ m-1 of the left circular shift or right circular shift only need to have the corresponding order change implemented.

[0941] Regarding some specific implementations, the following describes the procedure of the data processing method further described in FIG. 26. The following Embodiments X-1 to X-6 describe the data processing procedures shown in FIGS. 27 and 28.

[0942] Embodiment X-1: n0 = 4, n1 = 1, and a0 = 8. The data processing procedure includes convolutional interleaving. For example, a bit set is used as a representative and a left circular shift is used.

[0943] The Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 4 first data streams. All of the above-mentioned n0 = 4 first data streams are outer-coded data streams. Interleaving and encoding processing is performed on each of the n1 = 1 first data streams among the n0 = 4 first data streams to obtain one second data stream, and a total of n2 = 4 second data streams are obtained.

[0944] Refer to FIG. 27. In the interleaving and encoding process, inner coding is first performed, then a cyclic shift is performed, and then a round-robin reading is performed. For the n1 = 1 first data stream, m = n1 × a0 = 8 first bit sets including K = 120 bits are obtained, so a total of m × K = 960 bits are included. Since convolutional interleaving processing is further performed on the first data stream before inner coding, the K = 120 bits are from 12 KP4 symbols among 12 different outer code KP4 RS codewords.

[0945] By using inner coding, inner coding is performed on each K = 120 bits, P = 8 parity bits are added, an inner codeword including N = 128 bits is obtained, and a total of m = 8 inner codewords are obtained. These K = 120 bits are also called an information bit sequence.

[0946] In this application, in the cyclic shift operation, for the K = 120 information bits in the i-th (0 ≦ i < 8) inner codeword, that is, the i-th first bit set,

[0947]

Equation

[0948] A left cyclic shift of the bits is performed to obtain the i-th second bit set, and eight offset constraint factors of the left cyclic shift

[0949]

Number

[0950] The specific values of are the items 1 of the following values: {0, 30, 60, 90, 110, 20, 50, 80}, {0, 30, 90, 60, 110, 20, 80, 50}, {0, 60, 30, 90, 110, 50, 20, 80}, {0, 60, 90, 30, 110, 50, 80, 20}, {0, 90, 30, 60, 110, 80, 20, 50}, or {0, 90, 60, 30, 110, 80, 50, 20} is one of them.

[0951] For any item, a fixed offset is added to each of the eight offset constraint factors of the left cyclic shift

[0952]

Number

[0953] It should be understood that is added to each value of. That is,

[0954]

Number

[0955] is also regarded as a valid parameter item, and Δ is an integer.

[0956] The i-th second bit set is combined with P = 8 parity bits in the i-th inner codeword to obtain the i-th third bit set including N = 128 bits.

[0957] Refer to FIG. 27. For the m = 8 third bit sets output after the cyclic shift, in the round-robin reading, 2 bits are obtained from each third bit set through the round-robin, and 512 consecutive operations are performed to obtain all the bits in the m = 8 third bit sets, and a fourth bit set containing m×N = 1024 bits is obtained.

[0958] Each 2 bits in the fourth bit set containing 1024 bits are mapped to 1 PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to 1 PAM4 modulation symbol are from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner codewords.

[0959] For n1 = 2 KP4 outer code symbols from the same RS outer codeword in 1 first data stream, there are a total of 20 bits. These 20 bits undergo the above interleaving and encoding processes and are mapped to 10 PAM4 symbols in 1 PAM4 symbol data stream. Any 2 of the 10 PAM4 symbols can be separated by at least 2 PAM4 symbols in the PAM4 symbol data stream, and the left cyclic shift offset constraint factor in item 1 of the value

[0960]

Number

[0961] is used. More specifically, when 2 of the 10 PAM4 symbols are from different KP4 outer codewords, 2 of the 10 PAM4 symbols are separated by at least 12 PAM4 symbols in the PAM4 symbol data stream.

[0962] According to the interleaving and encoding processing method designed in this embodiment, both the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to modulation symbols. In this way, the concatenated FEC transmission strategy has a strong burst tolerance ability.

[0963] In this embodiment, n0 = 4, n1 = 1, a0 = 8, and n2 = n0 / n1 = 4. It should be noted that this can be applied to an 800GE scenario where n2 = 4 second data streams have a rate of about 200G and are carried on 4-lane optical signals for transmission accordingly. The interleaving and encoding processing used in this embodiment can be applied to a 1.6TE scenario where n0 = 8, n1 = 1, a0 = 8, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from multiple synchronized client lanes to obtain n0 = 8 first data streams. All of the above-mentioned n0 = 8 first data streams are outer code-encoded data streams. Interleaving and encoding processing is performed on each of the n1 = 1 first data streams among the n0 = 8 first data streams to obtain 1 second data stream, and a total of n2 = 8 second data streams are obtained. Correspondingly, n2 = 8 second data streams (the rate is about 200G per second data stream) are carried on 8-lane optical signals for transmission.

[0964] Embodiment X-2: n0 = 4, n1 = 1, and a0 = 8. The data processing procedure includes convolutional interleaving. For example, a matrix is used as a representative and a left cyclic shift is used.

[0965] Based on the strategy of Embodiment X-1, the m = 8 first bit sets can be represented by using a first bit matrix M1 having 8 rows and 120 columns. Inner coding is performed on the K = 120 bits in each row of the first bit matrix M1 to obtain one inner code of N = 128 bits. The 8 inner code codewords can be represented by using an inner code codeword matrix M c and each row in the inner code codeword matrix M c contains the N = 128 bits in one inner code codeword. In the inner code codeword matrix M c , in total, the m×K = 960 bits from the 0th column to the (K - 1 = 119)th column correspond to the m×K = 960 information bits in the m = 8 inner code codewords. In the inner code codeword matrix, in total, the m×P = 64 bits from the (K = 120)th column to the (N - 1 = 127)th column in the inner code codeword matrix M c correspond to the m×P = 64 parity bits in the m = 8 inner code codewords.

[0966] For the 120 information bits in the i(0 ≤ i < 8)th row in the inner code codeword matrix M c (i.e., the 120 bits in the i-th row in the first bit matrix M1),

[0967]

Number

[0968] a left cyclic shift of the bits is performed to obtain 120 bits in the i-th row in the third bit matrix M3. The following equation is satisfied.

[0969]

Number

[0970] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≤ i < 8. The 8 offset constraint factors of the left cyclic shift

[0971] [Number]

[0972] The specific value of is one of the items of value 1.

[0973] Figure 33 is a diagram of the seventh implementation form of interleaving and encoding processing. As shown in Figure 33,

[0974] [Number]

[0975] are considered. The letters a, b, c, d, f, g, h, k, p, q, r, and s each represent one KP4 symbol, and the KP4 symbol contains 10 bits. In Figure 33, the KP4 symbols represented by the same letter are from the same KP4 outer code, and the KP4 symbols represented by different letters are from different KP4 outer codes. For example, the 8 KP4 symbols represented by the same letter a in Figure 33 are from the same KP4 outer code.

[0976] Two bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through a total of 512 operations to obtain an array A containing m×N = 1024 interleaved bits. The bit in the i-th row and j-th column in the third bit matrix M3 is output to the bit in the array A, and the following formula is satisfied,

[0977] [Number]

[0978] and the following formula is satisfied,

[0979] [Number]

[0980] where 0 ≤ i < 8 and 0 ≤ j < 128,

[0981]

Number

[0982] represents the floor operation.

[0983] To obtain the 1024-bit array A, the cyclic shift and round-robin read performed on the inner codeword matrix M c It should be noted that the cyclic shift and round-robin read performed on M can be implemented by using two operations or can be implemented by using one operation. The following is the direct association c between M

[0984]

Number

[0985] is directly provided, where 0 ≤ i < 8.

[0986] Each 2 bits in the array A containing 1024 bits are mapped to one PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The 2 bits mapped to one PAM4 modulation symbol are from one inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner codewords.

[0987] For two KP4 outer code symbols from the same RS outer code word in one first data stream, there are 20 bits in total. These 20 bits undergo the above-mentioned interleaving and encoding processes and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. Any two of the 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream so as to satisfy the offset constraint factor of the left circular shift in item 1 of the value.

[0988]

Number

[0989] is used. More specifically, when two of the 10 PAM4 symbols are from different RS outer code words, the two of the 10 PAM4 symbols are separated by at least 12 PAM4 symbols in the PAM4 symbol data stream.

[0990] According to the interleaving and encoding method designed in this embodiment, both the bits in the outer code word and the bits in the inner code word are individually and evenly mapped to modulation symbols. In this way, the concatenated FEC transmission strategy has a strong burst tolerance ability.

[0991] In this embodiment, n0 = 4, n1 = 1, a0 = 8, and n2 = n0 / n1 = 4, which is noted to be applicable to an 800GE scenario where n2 = 4 second data streams have a rate of approximately 200G and are carried on 4-lane optical signals for transmission accordingly. The interleaving and encoding processes used in this embodiment can be applied to a 1.6TE scenario where n0 = 8, n1 = 1, a0 = 8, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 8 first data streams. All of the above-mentioned n0 = 8 first data streams are outer-encoded data streams. Interleaving and encoding processes are performed on each of the n1 = 1 first data streams among the n0 = 8 first data streams to obtain 1 second data stream, and a total of n2 = 8 second data streams are obtained. Accordingly, n2 = 8 second data streams (the rate is approximately 200G per second data stream) are carried on 8-lane optical signals for transmission.

[0992] Embodiment X-3: n0 = 4, n1 = 1, and a0 = 8. The data processing procedure includes convolutional interleaving. For example, a matrix is used as a representative and a right circular shift is used.

[0993] Based on the strategy of Embodiment X-2, a right circular shift is used. For the 120 information bits in the i-th (0 ≦ i < 8) row in the inner-encoded codeword matrix M c (that is, the 120 bits in the i-th row in the first bit matrix M1), a right circular shift of δ i bits is performed to obtain 120 bits in the i-th row in the third bit matrix M3. The following equation is satisfied.

[0994]

Equation

[0995] Y%Z represents the remainder obtained by dividing integer Y by integer Z, where 0 ≦ i < m. The specific values of the eight offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the right circular shift are in item 2 of the following values: {0, 30, 60, 90, 10, 40, 70, 100}, {0, 30, 90, 60, 10, 40, 100, 70}, {0, 60, 30, 90, 10, 40, 40, 100}, {0, 60, 90, 30, 10, 70, 100, 40}, {0, 90, 30, 60, 10, 100, 40, 70}, or {0, 90, 60, 30, 10, 100, 70, 40} is one of them.

[0996] Note that the association between M3 and M2 can alternatively be written as the following formula.

[0997]

Number

[0998] Here, 0 ≦ i < 8.

[0999] Note that for any one of the values in item 2, a fixed offset is added to each value of the eight offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the right circular shift. That is, {(δ0 + Δ)%K, (δ1 + Δ)%K, (δ2 + Δ)%K, (δ3 + Δ)%K, (δ4 + Δ)%K, (δ5 + Δ)%K, (δ6 + Δ)%K, (δ7 + Δ)%K} is also regarded as a valid parameter item, where Δ is an integer.

[1000] FIG. 34 is a diagram of an eighth implementation form of interleaving and encoding processing. As shown in FIG. 34, {δ0 = 0, δ1 = 90, δ2 = 60, δ3 = 30, δ4 = 10, δ5 = 100, δ6 = 70, δ7 = 40} is considered. The characters a, b, c, d, f, g, h, k, p, q, r, and s each represent one KP4 symbol, and the KP4 symbol contains 10 bits. In FIG. 34, the KP4 symbols represented by the same character are from the same outer KP4 code, and the KP4 symbols represented by different characters are from different outer KP4 codes. For example, the eight KP4 symbols represented by the same character a in FIG. 34 are from the same outer KP4 code.

[1001] Two bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through a total of 512 operations to obtain an array A containing m×N = 1024 interleaved bits. The bit in the i-th row and j-th column in the third bit matrix M3 is output to the bit in the

[1002] [Number]

[1003] of the array A, and the following equation is satisfied,

[1004] [Number]

[1005] where 0 ≤ i < 8 and 0 ≤ j < 128,

[1006] [Number]

[1007] represents a floor operation.

[1008] The cyclic shift and round-robin reading performed on the inner code codeword matrix M to obtain the 1024-bit array A can be performed by using two operations or can be performed by using one operation. Note the following direct association between M c and A c provides directly, where 0 ≤ i < 8

[1009]

Number

[1010] Each 2 bits in the array A containing 1024 bits are mapped to one PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to one PAM4 modulation symbol are from one inner code codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner code codewords

[1011] For n1 = 2 KP4 outer code symbols from the same RS outer code codeword in one first data stream, there are a total of 20 bits. These 20 bits undergo the above interleaving and encoding processes and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. Any 2 of the 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream, and the offset constraint factor δ of the right cyclic shift in item 2 of the value

[1012] i is used. More specifically, when 2 of the 10 PAM4 symbols are from different KP4 outer code codewords, 2 of the 10 PAM4 symbols are separated by at least 12 PAM4 symbols in the PAM4 symbol data stream

[1013] ​According to the interleaving and encoding processing method designed in this embodiment, both the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to modulation symbols. In this way, the concatenated FEC transmission strategy has a strong burst tolerance ability.

[1014] In this embodiment, n0 = 4, n1 = 1, a0 = 8, and n2 = n0 / n1 = 4. It should be noted that this can be applied to an 800GE scenario where n2 = 4 second data streams have a rate of approximately 200G and are carried on 4-lane optical signals for transmission accordingly. The interleaving and encoding processing used in this embodiment can be applied to a 1.6TE scenario where n0 = 8, n1 = 1, a0 = 8, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 8 first data streams. All of the above-mentioned n0 = 8 first data streams are outer code-encoded data streams. Interleaving and encoding processing is performed on each of the n1 = 1 first data streams in the n0 = 8 first data streams to obtain 1 second data stream, and a total of n2 = 8 second data streams are obtained. Correspondingly, n2 = 8 second data streams (the rate is approximately 200G per second data stream) are carried on 8-lane optical signals for transmission.

[1015] Embodiment X - 4: n0 = 4, n1 = 1, and a0 = 8. The data processing procedure does not include convolutional interleaving. For example, a bit set is used as a representative and a left circular shift is used.

[1016] Based on Embodiment X-1, the convolutional interleaving operation is not performed (omitted), which has the advantage of low latency and satisfies application scenarios with high latency requirements. The Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 4 first data streams. All of the above-mentioned n0 = 4 first data streams are outer-coded data streams. Interleaving and encoding processing is performed on each n1 = 1 first data stream among the n0 = 4 first data streams to obtain one second data stream, and a total of n2 = 4 second data streams are obtained.

[1017] Refer to FIG. 27. In the interleaving and encoding process, inner coding is first performed, then a cyclic shift is performed, and then a round-robin read is performed. For an n1 = 1 first data stream, m = n1 × a0 = 8 first bit sets including K = 120 bits are obtained, so a total of m × K = 960 bits are included. The 120 information bits in each inner codeword are from 12 KP4 symbols in 4 different outer code KP4 RS codewords.

[1018] By using inner coding, inner coding is performed on each K = 120 bits, P = 8 parity bits are added, an inner codeword including N = 128 bits is obtained, and a total of m = 8 inner codewords are obtained. These K = 120 bits are also called an information bit sequence.

[1019] In this application, in the cyclic shift operation, for the K = 120 information bits in the i-th (0 ≦ i < 8) inner codeword, that is, the i-th first bit set,

[1020]

Equation

[1021] A left cyclic shift of the bits is performed to obtain the i-th second bit set, and eight offset constraint factors of the left cyclic shift

[1022]

Number

[1023] The specific values of are in item 3 of the following values: {0, 30, 60, 90, 110, 20, 50, 80}, or {0, 60, 30, 90, 110, 50, 20, 80} is one of them.

[1024] For any item, it should be understood that a fixed offset is added to each value of the eight offset constraint factors of the left cyclic shift

[1025]

Number

[1026] It should be understood that are added to each value. That is,

[1027]

Number

[1028] are also regarded as valid parameter items, and Δ is an integer.

[1029] The i-th second bit set is combined with P = 8 parity bits in the i-th inner codeword to obtain the i-th third bit set including N = 128 bits.

[1030] Refer to FIG. 27. For the m = 8 third bit sets output after the cyclic shift, in the round-robin reading, 2 bits are obtained from each third bit set through the round-robin, and continuous 512 operations are performed to obtain all the bits in the m = 8 third bit sets, and a fourth bit set containing m×N = 1024 bits is obtained.

[1031] Each 2 bits in the fourth bit set containing 1024 bits are mapped to 1 PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to 1 PAM4 modulation symbol are from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner codewords.

[1032] For n1 = 2 KP4 outer code symbols from the same RS outer codeword in 1 first data stream, there are a total of 20 bits. These 20 bits undergo the above interleaving and encoding processes and are mapped to 10 PAM4 symbols in 1 PAM4 symbol data stream. Any 2 of the 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream according to the left cyclic shift offset constraint factor in item 3 of the value

[1033]

Number

[1034] is used.

[1035] According to the interleaving and mapping method designed in this embodiment, when low latency is guaranteed, the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to the modulation symbols. In this way, the concatenated FEC transmission strategy has a strong burst tolerance ability.

[1036] In this embodiment, n0 = 4, n1 = 1, a0 = 8, and n2 = n0 / n1 = 4, which is noted to be applicable to an 800GE scenario where n2 = 4 second data streams have a rate of approximately 200G and are carried on a 4-lane optical signal for transmission accordingly. The interleaving and encoding processes used in this embodiment can be applied to a 1.6TE scenario where n0 = 8, n1 = 1, a0 = 8, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 8 first data streams. All of the above-mentioned n0 = 8 first data streams are outer-encoded data streams. Interleaving and encoding processes are performed on each of the n1 = 1 first data streams among the n0 = 8 first data streams to obtain one second data stream, and a total of n2 = 8 second data streams are obtained. Accordingly, n2 = 8 second data streams (the rate is approximately 200G per second data stream) are carried on an 8-lane optical signal for transmission.

[1037] Embodiment X-5: n0 = 4, n1 = 1, and a0 = 8. In a certain data processing procedure, convolutional interleaving is not performed. For example, a matrix is used as a representative and a left-circular shift is used.

[1038] Based on Embodiment X-4, m = 8 bit sets can be represented by using a matrix. Inner encoding is performed on K = 120 bits in each row of the first bit matrix M1 to obtain the inner-encoded word matrix M c to obtain. In the inner-encoded word matrix M c for the 120 information bits in the i-th (0 ≤ i < 8) row (that is, the 120 bits in the i-th row of the first bit matrix M1),

[1039]

Number

[1040] A left cyclic shift of bits is performed to obtain 120 bits in the i-th row in the third bit matrix M3. The following equation is satisfied.

[1041]

Number

[1042] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≦ i < 8. The eight offset constraint factors of the left cyclic shift

[1043]

Number

[1044] The specific value of is one of the values in item 3.

[1045] Figure 35 is a diagram of the ninth implementation form of the interleaving and encoding process. As shown in Figure 35,

[1046]

Number

[1047] are considered. The characters a, b, c, and d each represent one KP4 symbol, and the KP4 symbol contains 10 bits. In Figure 35, the KP4 symbols represented by the same character are from the same KP4 outer code, and the KP4 symbols represented by different characters are from different KP4 outer codes. For example, the 24 KP4 symbols represented by the same character a in Figure 35 are from the same KP4 outer code.

[1048] Through round robin, 2 bits are read from each row in the third bit matrix M3, and all 1024 bits are read through a total of 512 operations, obtaining an array A containing m×N = 1024 interleaved bits.

[1049] Each 2 bits in the array A containing 1024 bits are mapped to 1 PAM4 modulation symbol, obtaining a total of 512 PAM4 symbols. The 2 bits mapped to 1 PAM4 modulation symbol are from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner codewords.

[1050] For n1 = 2 KP4 outer code symbols from the same RS outer codeword in 1 first data stream, there are a total of 20 bits. These 20 bits undergo the above interleaving and encoding processes and are mapped to 10 PAM4 symbols in 1 PAM4 symbol data stream. Any 2 of the 10 PAM4 symbols are subject to the offset constraint factor of the left cyclic shift in item 3 of the value so that they can be separated by at least 2 PAM4 symbols in the PAM4 symbol data stream

[1051]

Number

[1052] is used.

[1053] According to the bit interleaving and mapping method designed in this embodiment, when low latency is guaranteed, the bits in the outer codeword and the bits in the inner codeword are mapped to the modulation symbols individually and evenly. In this way, the concatenated FEC transmission strategy has good burst tolerance ability.

[1054] In this embodiment, n0 = 4, n1 = 1, a0 = 8, and n2 = n0 / n1 = 4, which should be noted can be applied to an 800GE scenario where n2 = 4 second data streams have a rate of approximately 200G and are carried on a 4-lane optical signal for transmission accordingly. The interleaving and encoding processes used in this embodiment can be applied to a 1.6TE scenario where n0 = 8, n1 = 1, a0 = 8, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 8 first data streams. All of the above-mentioned n0 = 8 first data streams are outer-encoded data streams. Interleaving and encoding processes are performed on each of the n1 = 1 first data streams among the n0 = 8 first data streams to obtain 1 second data stream, and a total of n2 = 8 second data streams are obtained. Accordingly, n2 = 8 second data streams (the rate is approximately 200G per second data stream) are carried on an 8-lane optical signal for transmission.

[1055] Embodiment X-6: n0 = 4, n1 = 1, and a0 = 8. In a certain data processing procedure, convolutional interleaving is not performed. For example, a matrix is used as a representative and a right-circular shift is employed.

[1056] Based on Embodiment X-5, a right-circular shift is used. For the 120 information bits in the i-th (0 ≦ i < 8) row in the inner-code codeword matrix M c (i.e., the 120 bits in the i-th row in the first bit matrix M1), a right-circular shift of δ i bits is performed to obtain 120 bits in the i-th row in the third bit matrix M3. The following equations are satisfied.

[1057]

Equation

[1058] Y%Z represents the remainder obtained by dividing integer Y by integer Z, where 0 ≦ i < m. The specific values of the eight offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the right circular shift are item 4 of the following values: {0, 60, 90, 30, 10, 70, 100, 40}, or {0, 90, 60, 30, 10, 100, 70, 40} is one of them.

[1059] For any item, it should be understood that a fixed offset is added to each value of the eight offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the right circular shift. That is, {(δ0 + Δ)%K, (δ1 + Δ)%K, (δ2 + Δ)%K, (δ3 + Δ)%K, (δ4 + Δ)%K, (δ5 + Δ)%K, (δ6 + Δ)%K, (δ7 + Δ)%K} is also regarded as a valid parameter item, where Δ is an integer.

[1060] M3 and M c Note that the association between and can alternatively be written as follows.

[1061]

Number

[1062] Here, 0 ≦ i < 8.

[1063] FIG. 36 is a diagram of a tenth implementation form of interleaving and encoding processing. As shown in FIG. 36, {δ0 = 0, δ1 = 60, δ2 = 90, δ3 = 30, δ4 = 10, δ5 = 70, δ6 = 100, δ7 = 40} is considered. Characters a, b, c, and d each represent one KP4 symbol, and the KP4 symbol contains 10 bits. In FIG. 36, the KP4 symbols represented by the same character are from the same outer KP4 code, and the KP4 symbols represented by different characters are from different outer KP4 codes. For example, the 24 KP4 symbols represented by the same character a in FIG. 36 are from the same outer KP4 code.

[1064] Two bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through a total of 512 operations to obtain an array A containing m×N = 1024 interleaved bits.

[1065] Each 2 bits in the array A containing 1024 bits are mapped to one PAM4 modulation symbol, and a total of 512 PAM4 symbols are obtained. The 2 bits mapped to one PAM4 modulation symbol are from one inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner codewords.

[1066] For n1 = 2 outer KP4 code symbols from the same RS outer codeword in one first data stream, there are a total of 20 bits. These 20 bits undergo the above-described interleaving and encoding processing and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. Any two of the 10 PAM4 symbols can be at least 2 PAM4 symbols apart in the PAM4 symbol data stream, and the offset constraint factor δ in item 4 of the value i is used.

[1067] According to the bit interleaving and mapping method designed in this embodiment, when low latency is guaranteed, the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to modulation symbols. In this way, the concatenated FEC transmission strategy has good burst tolerance ability.

[1068] In this embodiment, n0 = 4, n1 = 1, a0 = 8, and n2 = n0 / n1 = 4. It should be noted that this can be applied to an 800GE scenario where n2 = 4 second data streams have a rate of about 200G and are carried on 4 lanes of optical signals for transmission accordingly. The interleaving and encoding processes used in this embodiment can be applied to a 1.6TE scenario where n0 = 8, n1 = 1, a0 = 8, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 8 first data streams. All of the above-mentioned n0 = 8 first data streams are outer code-encoded data streams. Interleaving and encoding processes are performed on each of the n1 = 1 first data streams in the n0 = 8 first data streams to obtain 1 second data stream, and a total of n2 = 8 second data streams are obtained. Correspondingly, n2 = 8 second data streams (the rate is about 200G per second data stream) are carried on 8 lanes of optical signals for transmission.

[1069] It should be noted that in Embodiments X-1 to X-6, inner code encoding is first performed, and then cyclic shift is performed. Alternatively, as shown in FIGS. 29 and 30, inner code encoding and cyclic shift may be performed in parallel. The following uses Embodiment X-7 as an example for explanation to provide an equivalent execution method of Embodiment X-3.

[1070] Embodiment X-7: n0 = 4, n1 = 1, and a0 = 8. The data processing procedure includes convolutional interleaving. For example, a matrix is used as a representative and a left circular shift is used. Inner coding and circular shift are performed in parallel.

[1071] Based on the method of Embodiment X-3, in this embodiment, inner coding and circular shift are performed in parallel.

[1072] FIG. 37 is a diagram of an eleventh implementation form of interleaving and encoding processing. As shown in FIG. 37, for the 120 information bits in the i-th (0 ≦ i < 8) in the first bit matrix M1 (that is, the 120 bits in the i-th row in the first bit matrix M1),

[1073]

Number

[1074] a left circular shift of bits is performed to obtain 120 bits in the i-th row in the second bit matrix M2. The following equation is satisfied.

[1075]

Number

[1076] Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, where 0 ≦ i < 8 and 0 ≦ j < 120. The eight offset constraint factors of the left circular shift

[1077]

Number

[1078] are one of the values in item 1 of the values. As shown in FIG. 37,

[1079]

Number

[1080] is considered.

[1081] For each of the K = 120 bits in each row of the first bit matrix M1, an inner codeword is performed to obtain one P = 8 parity bits, and a parity bit matrix M p is obtained.

[1082] Two bits are read from each row in the third bit matrix M3 through a round robin, and all 1024 bits are read through a total of 512 operations to obtain an array A containing m × N = 1024 interleaved bits. The bit in the i-th row and j-th column in the third bit matrix M3 is the bit in the

[1083]

Number

[1084] of the array A is output, and the following equation is satisfied.

[1085]

Number

[1086] Here, 0 ≤ i < 8 and 0 ≤ j < 128,

[1087]

Number

[1088] represents a floor operation.

[1089] The cyclic shift and round robin read performed on the inner codeword matrix M c to obtain the 1024-bit array A are performed by using two operations, or may be performed by using one operation. Note that the following is Mc directly provides a direct association between and A.

[1090]

Number

[1091] Here, 0 ≦ i < 8.

[1092] Each 2 bits in the array A containing 1024 bits are mapped to 1 PAM4 modulation symbol, resulting in a total of 512 PAM4 symbols. The 2 bits mapped to 1 PAM4 modulation symbol are from 1 inner codeword, and the 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner codewords.

[1093] For n1 = 2 KP4 outer code symbols from the same RS outer codeword in 1 first data stream, there are a total of 20 bits. These 20 bits undergo the above interleaving and encoding processes and are mapped to 10 PAM4 symbols in 1 PAM4 symbol data stream. Any 2 of the 10 PAM4 symbols are subject to a left - cyclic shift offset constraint factor

[1094]

Number

[1095] is used.

[1096] According to the interleaving and encoding method designed in this embodiment, both the bits in the outer codeword and the bits in the inner codeword are individually and evenly mapped to modulation symbols. In this way, the concatenated FEC transmission strategy has a strong burst tolerance ability.

[1097] In this embodiment, n0 = 4, n1 = 1, a0 = 8, and n2 = n0 / n1 = 4, which should be noted can be applied to an 800GE scenario where n2 = 4 second data streams have a rate of approximately 200G and are carried on a 4-lane optical signal for transmission accordingly. The interleaving and encoding processes used in this embodiment can be applied to a 1.6TE scenario where n0 = 8, n1 = 1, a0 = 8, and n2 = n0 / n1 = 8. In this case, the Physical Medium Attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronized client lanes to obtain n0 = 8 first data streams. All of the above-mentioned n0 = 8 first data streams are outer-encoded data streams. Interleaving and encoding processes are performed on each of the n1 = 1 first data streams among the n0 = 8 first data streams to obtain 1 second data stream, and a total of n2 = 8 second data streams are obtained. Corresponding...

Claims

1. A data processing method, comprising: separately performing inner coding on n first data streams to obtain n second data streams, wherein outer coding is performed on all of the n first data streams, both the inner coding and the outer coding are forward error correction (FEC) coding, the n second data streams include at least n inner coding codewords, the n inner coding codewords are respectively from the n second data streams, the n inner coding codewords include n / m codeword sets, each codeword set includes m inner coding codewords, each of the inner coding codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m; separately performing bit interleaving on the n / m codeword sets to obtain n / m target bit sets, each of the target bit sets including m×N bits; mapping the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, and obtaining a total of n×N / L modulation symbols, wherein each L bits are mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are respectively from L inner coding codewords; and when all of the L bits mapped to the modulation symbol are from information bits in the inner coding codewords, any two of the L bits mapped to the modulation symbol are from two different positions in two different inner coding codewords. A data processing method.

2. The method according to claim 1, wherein N is divisible by L, the N bits in each inner coding codeword are mapped to N modulation symbols, the N bits in the inner coding codeword include L first bit subsets, bits in the same first bit subset are separately mapped to the same bit in different modulation symbols, and bits in different first bit subsets are separately mapped to different bits in different modulation symbols.

3. The step of performing the bit interleaving on the codeword set to obtain the target bit set is Performing a first position transformation on the K information bits in each inner codeword symbol in the symbol set to obtain a first bit set; Performing a second position transformation on the bits at the same position in the first bit set to obtain the target bit set; The method according to claim 1 or 2, comprising:

4. The step of performing the first position transformation on the K information bits in each inner codeword symbol in the symbol set is: The method according to claim 3, comprising the step of performing a left circular shift or a right circular shift on the K information bits in each inner codeword symbol in the symbol set.

5. Both the symbol set and the first bit set are represented as bit matrices, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix has m rows and N columns of bits, the one-dimensional array has the m×N bits, and the bits at the same position in the first bit set are m bits in total in one column in the bit matrix corresponding to the first bit set. The method according to claim 3 or 4.

6. The first position transformation satisfies a first condition, and the first condition is: 【Number 1】 comprising H 1 [i][j] represents the bit in the i-th row and j-th column in the bit matrix where the first position conversion has not been performed, and H 2 [i][j] represents the bit in the i-th row and the j-th column in the bit matrix obtained through the first position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≦i<m. The method according to claim 5.

7. Each same position in the first bit set includes m / L second bit subsets, each second bit subset has L bits, and the step of performing the second position transformation on the bits at the same position in the first bit set is: The method according to any one of claims 3 to 6, comprising the step of performing an upward circular shift or a downward circular shift on the m / L second bit subsets at the same position in the first bit set.

8. The second position transformation satisfies a second condition, and the second condition is: 【Number 2】 equipped with, H 2 [i][j] represents the bit in the i-th row and j-th column of the bit matrix where the second position transformation has not been performed, and H 3 [i][j] represents the bit in the i-th row and the j-th column in the bit matrix obtained through the second position transformation. [Number 3] represents truncation, Y%Z represents the remainder obtained by dividing integer Y by integer Z, θ is a non-zero integer greater than -L and less than L, 0≦i<m, 0≦j<N, the method according to claim 5.

9. The second position transformation satisfies a third condition, and the third condition is 【Number 4】 comprising H 2 [i][j] represents a bit in the i-th row and j-th column of the bit matrix where the second position transformation has not been performed, and H 3 [i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation, 【Number 5】 represents truncation, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≦i<m, 0≦j<N, the method according to claim 5.

10. The second position transformation satisfies a fourth condition, and the fourth condition is H 3 [i][j]=H 2 [i^(j%L)][j] comprising H 2 [i][j] represents a bit in the i-th row and j-th column of the bit matrix before the second position transformation is performed, and H 3 [i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0≦i<m, 0≦j<N, the method according to claim 5.

11. The symbol word set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix has m rows and N columns of bits, and the one-dimensional array has the m×N bits, the method according to claim 1 or 2.

12. The target bit set is the bit matrix, the bit interleaving satisfies a fifth condition, and the fifth condition is 【Number 6】 comprising H 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix where the bit interleaving is not performed, and H 3 [i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the bit interleaving, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K, 【Number 7】 represents truncation, θ is a non-zero integer greater than -L and less than L, 0≦i<m, the method according to claim 11.

13. The target bit set is the one-dimensional array, the bit interleaving satisfies a sixth condition, and the sixth condition is 【Number 8】 comprising H 1 [i][j] represents the bit in the i-th row and j-th column in the bit matrix where the bit interleaving is not performed, A[t] represents the t-th bit in the one-dimensional array obtained through the bit interleaving, 0 ≦ t < m × N, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, 【Number 9】 represents truncation, θ is a non-zero integer greater than -L and less than L, 0 ≦ i < m, The method according to claim 11.

14. The target bit set is the bit matrix, the bit interleaving satisfies the seventh condition, and the seventh condition is 【Number 10】 comprising H 1 [i][j] represents the bit in the i-th row and j-th column in the bit matrix where the bit interleaving is not performed, and H 3 [i][j] represents the bit in the i-th row and j-th column in the bit matrix obtained through the bit interleaving, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≦ i < m, The method according to claim 11.

15. The target bit set is the one-dimensional array, the bit interleaving satisfies the eighth condition, and the eighth condition is 【Number 11】 comprising H 1 [i][j] represents the bit in the i-th row and j-th column in the bit matrix where the bit interleaving is not performed, A[t] represents the t-th bit in the one-dimensional array obtained through the bit interleaving, 0 ≦ t < m × N, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≦ i < m, The method according to claim 11.

16. The step of mapping the m × N bits in each target bit set to obtain m × N / L modulation symbols is The method according to any one of claims 1 to 15, comprising the step of mapping each of L consecutive bits at the same position in each target bit set to one modulation symbol to obtain the m×N / L modulation symbols.

17. The modulation symbol stream comprises the m×N / L modulation symbols obtained through the mapping, and m / L modulation symbols obtained through the mapping of m bits at the same position in each target bit set are consecutive in the modulation symbol stream, when the target bit set is represented as the bit matrix, the m bits at the same position in the target bit set are m bits in one column in the bit matrix, or when the target bit set is represented as the one-dimensional array, the m bits at the same position in the target bit set are m consecutive bits in the one-dimensional array. The method according to claim 16.

18. The modulation symbol stream comprises the m×N / L modulation symbols obtained through the mapping, each target bit set is represented as the bit matrix comprising the m rows and the N columns of bits, m bits in one column in each target bit set are mapped to obtain m / L first modulation symbols, and each of T consecutive first modulation symbols in the m / L first modulation symbols is consecutive in the modulation symbol stream, m bits in another column in each target bit set are mapped to obtain m / L second modulation symbols, and each of T consecutive second modulation symbols in the m / L second modulation symbols is consecutive in the modulation symbol stream, the column is adjacent to the another column, and the T consecutive first modulation symbols in the m / L first modulation symbols and the T consecutive second modulation symbols in the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T. The method according to claim 16.

19. Alignment marker locking and lane despooling processing are performed on all of the n first data streams, and when all of the W×L bits in W consecutive modulation symbols are information bits in an inner codeword, the W×L bits are from more than two outer codewords obtained through the outer coding, where W≥2. The method according to any one of claims 1 to 18.

20. Each modulation symbol is a dual-polarization 16-quadrature amplitude modulation (DP-16QAM) modulation symbol, each modulation symbol comprises 8 bits, or Each modulation symbol is a 4-level pulse amplitude modulation (PAM4) modulation symbol, each modulation symbol comprises 2 bits. The method according to any one of claims 1 to 19.

21. A data processing method, comprising: Separately performing inner coding on n first data streams to obtain n second data streams, wherein outer coding is performed on all of the n first data streams, both the inner coding and the outer coding are forward error correction (FEC) coding, the n second data streams comprise at least n inner codewords, the n inner codewords are respectively from the n second data streams, the n inner codewords comprise n / m codeword sets, each codeword set comprises m inner codewords, each of the inner codewords comprises N bits, the N bits comprise K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. Separately performing bit interleaving on the n / m codeword sets to obtain n / m target bit sets, wherein each of the target bit sets comprises m×N bits, and the bit interleaving comprises performing position transformation on the K information bits in each inner codeword in the codeword set. A step of separately mapping the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, and obtaining a total of n×N / L modulation symbols, wherein each L bits are mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are from L r inner code codewords, and the L r bits in each of the L c inner code codewords are mapped to the modulation symbol, and the 2L bits mapped to two consecutive modulation symbols are from 2L r inner code codewords, L = L r ×L c and L c > 1, the step and A data processing method.

22. The step of performing position transformation on the K information bits in each inner codeword in the codeword set Comprises the step of performing a left circular shift or a right circular shift on the K information bits in each inner codeword in the codeword set. The method according to claim 21.

23. The symbol word set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix has bits of m rows and N columns, and the one-dimensional array has the m×N bits. The method according to claim 21 or 22.

24. The position transformation satisfies a target condition, and the target condition is 【Number 12】 equipped with, H 1 [i][j] represents a bit in the i-th row and the j-th column in the bit matrix where the position conversion is not performed, and H 2 [i][j] represents the bit in the i-th row and the j-th column in the bit matrix obtained through the position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≦i<m. The method according to claim 23.

25. Each target bit set includes the bits of the m rows and the N columns, and in each of the L r rows and L c columns, a total of L bits are mapped to one modulation symbol, the method according to any one of claims 21 to 24.

26. The modulated symbol stream comprises the m×N / L modulated symbols obtained through the mapping, and each L c modulated symbols obtained through the mapping of the columns of bits in the target bit set are m / L r consecutive in the modulated symbol stream, and the m×N / L modulated symbols obtained through the mapping of each N columns of bits in the target bit set are consecutive in the modulated symbol stream, the method according to claim 25.

27. The modulated symbol stream comprises the m×N / L modulated symbols obtained through the mapping, and L bits in each of the L columns in each target bit set are mapped to obtain m / L first modulated symbols, and each of the T consecutive first modulated symbols among the m / L first modulated symbols is consecutive in the modulated symbol stream. L bits in each of the other L columns in each target bit set are mapped to obtain m / L second modulated symbols, and each of the T consecutive second modulated symbols among the m / L second modulated symbols is consecutive in the modulated symbol stream. The L columns are adjacent to the other L columns, and the T consecutive first modulated symbols among the m / L first modulated symbols and the T consecutive second modulated symbols among the m / L second modulated symbols are consecutive in the modulated symbol stream, and m / L is divisible by T. The method according to claim 25. c bits in the columns are mapped to obtain m / L r first modulated symbols, and the m / L r first modulated symbols, and each of the T consecutive first modulated symbols among the m / L c bits in the other L columns in each target bit set are mapped to obtain m / L r second modulated symbols, and the m / L r second modulated symbols, and each of the T consecutive second modulated symbols among the m / L c columns are adjacent to the other L c columns, and the m / L r first modulated symbols and the m / L r second modulated symbols are consecutive in the modulated symbol stream, and m / L r is divisible by T. The method according to claim 25.

28. Each modulation symbol is a dual-polarization 16-quadrature amplitude modulation (DP-16QAM) modulation symbol, each modulation symbol has 8 bits, or Each modulation symbol is a 4-level pulse amplitude modulation (PAM4) modulation symbol, each modulation symbol has 2 bits. The method according to any one of claims 21 to 27.

29. A data processing device comprising an encoding module, a bit interleaving module, and a bit mapping module, The encoding module is configured to separately perform inner code encoding on n first data streams to obtain n second data streams, outer code encoding is performed on all of the n first data streams, both the inner code encoding and the outer code encoding are forward error correction (FEC) encoding, the n second data streams include at least n inner code words, the n inner code words are from the n second data streams, the n inner code words include n / m code word sets, each code word set includes m inner code words, each of the inner code words has N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m, The bit interleaving module is configured to separately perform bit interleaving on the n / m code word sets to obtain n / m target bit sets, and each of the target bit sets has m×N bits. The bit mapping module is configured to map the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, and to obtain a total of n×N / L modulation symbols, where each L bits are mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are from L inner code codewords. A data processing apparatus, wherein when all of the L bits mapped to the modulation symbol are from information bits in the inner code codewords, any two of the L bits mapped to the modulation symbol are from two different positions in two different inner code codewords. Claim 30 The data processing apparatus according to claim 29, wherein N is divisible by L, the N bits in each inner code codeword are mapped to N modulation symbols, the N bits in the inner code codeword comprise L first bit subsets, bits in the same first bit subset are separately mapped to the same bit in different modulation symbols, and bits in different first bit subsets are separately mapped to different bits in different modulation symbols. Claim 31 In particular, the bit mapping module performs a first position transformation on the K information bits in each inner code codeword in the set of codewords to obtain a first bit set. The data processing apparatus according to claim 29 or 30, which is configured to perform a second position transformation on bits at the same position in the first bit set to obtain the target bit set. Claim 32 In particular, the bit mapping module is configured to perform a left cyclic shift or a right cyclic shift on the K information bits in each inner code codeword in the set of codewords, according to claim 31. Claim 33 In the data processing apparatus according to claim 31 or 32, both the set of codewords and the first bit set are represented as bit matrices, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix comprises m rows and N columns of bits, the one-dimensional array comprises the m×N bits, and the bits at the same position in the first bit set are a total of m bits in one column in the bit matrix corresponding to the first bit set.

34. the first position transformation satisfies a first condition, and the first condition is 【Number 13】 comprising H 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix before the first position transformation is performed, and H 2 [i][j] represents a bit in the i-th row and j-th column in the bit matrix obtained through the first position transformation, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Δ is a non-zero integer greater than -K and less than K, and 0 ≦ i < m. The data processing apparatus according to claim 33

35. each same position in the first bit set includes m / L second bit subsets, each second bit subset includes L bits, and the bit mapping module is particularly configured to perform a circulant shift up or a circulant shift down on the m / L second bit subsets at each same position in the first bit set. The data processing apparatus according to any one of claims 31 to 34

36. the second position transformation satisfies a second condition, and the second condition is 【Number 14】 comprising H 2 [i][j] represents a bit in the i-th row and the j-th column of the bit matrix before the second position transformation is performed, H 3 [i][j] represents a bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation 【Number 15】 represents truncation, Y%Z represents the remainder obtained by dividing integer Y by integer Z, θ is a non-zero integer greater than -L and less than L, 0 ≦ i < m, and 0 ≦ j < N. The data processing apparatus according to claim 33

37. the second position transformation satisfies a third condition, and the third condition is 【Number 16】 comprising H 2 [i][j] represents a bit in the i-th row and j-th column of the bit matrix where the second position transformation has not been performed, H 3 [i][j] represents a bit in the i-th row and j-th column in the bit matrix obtained through the second position transformation 【Number 17】 represents truncation, Y%Z represents the remainder obtained by dividing integer Y by integer Z, Y^Z represents an integer corresponding to a bit sequence obtained through an exclusive OR operation performed on the bit sequence corresponding to integer Y and the bit sequence corresponding to integer Z, 0 ≦ i < m, and 0 ≦ j < N. The data processing apparatus according to claim 33

38. the second position transformation satisfies a fourth condition, and the fourth condition is H 3 [i][j]=H 2 [i^(j%L)][j] comprising H 2 [i][j] represents a bit in the i-th row and j-th column of the bit matrix where the second position transformation has not been performed, and H 3 [i][j] represents the bit in the i-th row and j-th column of the bit matrix obtained through the second position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, 0 ≦ i < m, and 0 ≦ j < N. The data processing device according to claim 33.

39. The symbol word set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix has m rows and N columns of bits, and the one-dimensional array has the m×N bits. The data processing device according to claim 29 or 30.

40. The target bit set is the bit matrix, the bit interleaving satisfies a fifth condition, and the fifth condition is 【No. 18】 equipped with, H 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix where the bit interleaving is not performed, and H 3 [i][j] represents the bit in the i-th row and j-th column of the bit matrix obtained through the bit interleaving, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, 【Number 19】 represents truncation, θ is a non-zero integer greater than -L and less than L, and 0 ≦ i < m. The data processing device according to claim 39.

41. The target bit set is the one-dimensional array, the bit interleaving satisfies a sixth condition, and the sixth condition is 【Number 20】 comprising H 1 [i][j] represents the bit in the i-th row and j-th column of the bit matrix in which the bit interleaving is not performed, A[t] represents the t-th bit in the one-dimensional array obtained through the bit interleaving, 0 ≦ t < m×N, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, 【Number 21】 represents truncation, θ is a non-zero integer greater than -L and less than L, and 0 ≦ i < m. The data processing device according to claim 39.

42. The target bit set is the bit matrix, the bit interleaving satisfies a seventh condition, and the seventh condition is 【Number 22】 comprising H 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix where the bit interleaving is not performed, and H 3 [i][j] represents the bit in the i-th row and j-th column of the bit matrix obtained through the bit interleaving, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, and 0 ≦ i < m. The data processing device according to claim 39.

43. The target bit set is the one-dimensional array, the bit interleaving satisfies the eighth condition, and the eighth condition is 【Number 23】 comprising H 1 [i][j] represents the bit in the i-th row and j-th column of the bit matrix in which the bit interleaving is not performed, A[t] represents the t-th bit in the one-dimensional array obtained through the bit interleaving, 0 ≦ t < m×N, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, Y^Z represents the integer corresponding to the bit sequence obtained through the exclusive OR operation performed on the bit sequence corresponding to the integer Y and the bit sequence corresponding to the integer Z, and 0 ≦ i < m. The data processing device according to claim 39.

44. The bit mapping module is particularly configured to map each L consecutive bits at the same position in each target bit set to one modulation symbol to obtain the m×N / L modulation symbols. The data processing device according to any one of claims 29 to 43.

45. The modulation symbol stream includes the m×N / L modulation symbols obtained through the mapping, and the m / L modulation symbols obtained through the mapping of m bits at the same position in each target bit set are consecutive in the modulation symbol stream. When the target bit set is represented as the bit matrix, the m bits at the same position in the target bit set are m bits in one column in the bit matrix, or when the target bit set is represented as the one-dimensional array, the m bits at the same position in the target bit set are m consecutive bits in the one-dimensional array. The data processing apparatus according to claim 44.

46. The modulation symbol stream includes the m×N / L modulation symbols obtained through the mapping. Each target bit set is represented as the bit matrix including the bits of the m rows and the N columns. m bits in one column in each target bit set are mapped to obtain m / L first modulation symbols, and each T consecutive first modulation symbols among the m / L first modulation symbols are consecutive in the modulation symbol stream. m bits in another column in each target bit set are mapped to obtain m / L second modulation symbols, and each T consecutive second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream. The column is adjacent to the another column, and the T consecutive first modulation symbols among the m / L first modulation symbols and the T consecutive second modulation symbols among the m / L second modulation symbols are consecutive in the modulation symbol stream, and m / L is divisible by T. The data processing apparatus according to claim 44.

47. Marker lock and lane descrambling processing are performed for all of the n first data streams. When all of the W×L bits in W consecutive modulation symbols are information bits in the inner code codeword, the W×L bits are from more than two outer code codewords obtained through the outer coding, and W≧2. The data processing apparatus according to any one of claims 29 to 46.

48. Each modulation symbol is a dual-polarization 16-quadrature amplitude modulation (DP-16QAM) modulation symbol, and each modulation symbol includes 8 bits, or Each modulation symbol is a 4-level pulse amplitude modulation (PAM4) modulation symbol, and each modulation symbol includes 2 bits. The data processing apparatus according to any one of claims 29 to 47.

49. A data processing device, comprising an encoding module, a bit interleaving module, and a bit mapping module, wherein the encoding module is configured to separately perform inner code encoding on n first data streams to obtain n second data streams, outer code encoding is performed on all of the n first data streams, both the inner code encoding and the outer code encoding are forward error correction (FEC) encoding, the n second data streams include at least n inner code codewords, the n inner code codewords are from the n second data streams, the n inner code codewords include n / m codeword sets, each codeword set includes m inner code codewords, each of the inner code codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m, the bit interleaving module is configured to separately perform bit interleaving on the n / m codeword sets to obtain n / m target bit sets, each of the target bit sets includes m×N bits, and the bit interleaving includes performing a position transformation on the K information bits in each of the inner code codewords in the codeword sets, The bit mapping module is configured to map the m×N bits in each of the target bit sets to obtain m×N / L modulation symbols, and to obtain a total of n×N / L modulation symbols, where each L bits are mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are from L r inner code codewords, and L r bits in each of the L c inner code codewords are mapped to the modulation symbol, and the 2L bits mapped to two consecutive modulation symbols are from 2L r inner code codewords, where L = L r ×L c and L c > 1, a data processing device.

50. In particular, the bit interleaving module, The data processing device according to claim 49, wherein the bit interleaving module is configured to perform a left circular shift or a right circular shift on the K information bits in each of the inner code codewords in the codeword sets.

51. The data processing device according to claim 49 or 50, wherein the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes the m×N bits.

52. The position transformation satisfies a target condition, and the target condition is 【24 Points】 equipped with, H 1 [i][j] represents a bit in the i-th row and the j-th column in the bit matrix where the position conversion has not been performed, H 2 [i][j] represents the bit in the i-th row and the j-th column in the bit matrix obtained through the position transformation, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, Δ is a non-zero integer greater than -K and less than K, and 0≦i<m. The data processing device according to claim 51.

53. Each target bit set includes the bits of the m rows and the N columns, and in each of the L r rows and L c columns, a total of L bits among them are mapped to one modulation symbol. The data processing apparatus according to any one of claims 49 to 52.

54. The modulated symbol stream comprises the m×N / L modulated symbols obtained through the mapping, and L bits of each of the bits in the target bit set c The m / L modulated symbols obtained through the mapping of each column are consecutive in the modulated symbol stream, and the m×N / L modulated symbols obtained through the mapping of each N columns of the bits in the target bit set are consecutive in the modulated symbol stream. The data processing apparatus according to claim 53. r The m / L modulated symbols obtained through the mapping of each column are consecutive in the modulated symbol stream, and the m×N / L modulated symbols obtained through the mapping of each N columns of the bits in the target bit set are consecutive in the modulated symbol stream. The data processing apparatus according to claim 53.

55. The modulated symbol stream comprises the m×N / L modulated symbols obtained through the mapping, and L bits in each of the L columns in each target bit set are mapped to obtain m / L first modulated symbols, and each of the T consecutive first modulated symbols among the m / L first modulated symbols is continuous in the modulated symbol stream, and L bits in each of the other L columns in each target bit set are mapped to obtain m / L second modulated symbols, and each of the T consecutive second modulated symbols among the m / L second modulated symbols is continuous in the modulated symbol stream, and the L columns are adjacent to the other L columns, and the T consecutive first modulated symbols among the m / L first modulated symbols and the T consecutive second modulated symbols among the m / L second modulated symbols are continuous in the modulated symbol stream, and m / L is divisible by T. The data processing apparatus according to claim 53. c Among the columns, the bits are mapped to obtain m / L r first modulated symbols, and among the m / L r first modulated symbols, each of the T consecutive first modulated symbols is continuous in the modulated symbol stream, and among the other L columns in each target bit set, the bits are mapped to obtain m / L c second modulated symbols, and among the m / L r second modulated symbols, each of the T consecutive second modulated symbols is continuous in the modulated symbol stream, and the L r columns are adjacent to the other L c columns, and the T consecutive first modulated symbols among the m / L c first modulated symbols and the T consecutive second modulated symbols among the m / L r second modulated symbols are continuous in the modulated symbol stream, and m / L r is divisible by T. r The data processing apparatus according to claim 53.

56. Each modulation symbol is a dual-polarization 16-quadrature amplitude modulation (DP-16QAM) modulation symbol, each modulation symbol has 8 bits, or Each modulation symbol is a 4-level pulse amplitude modulation (PAM4) modulation symbol, each modulation symbol has 2 bits, the data processing device according to any one of claims 49 to 55.

57. A data processing method, comprising: n 0 each n in the n first data streams 1 perform interleaving and encoding processes separately on the n first data streams to obtain one second data stream, and obtain n second data streams in total, where 2 n 2 =n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0, the step of the foregoing n 2 separately mapping each 2 bits in each of the n second data streams to one PAM4 symbol, to obtain a total of n 2 steps of obtaining PAM4 symbol data streams; Comprising The interleaving and encoding process said n 1 from each of the n first data streams, obtain a 0 first bit sets, so that in total m = n 1 × a 0 first bit sets are obtained, where outer coding is performed on all of the n 1 first data streams, each of the first bit sets has K bits, n 1 , a 0 , and K are all integers greater than 1, and Performing inner code encoding separately on the m first bit sets to obtain m inner code codewords, both the inner code encoding and the outer code encoding being forward error correction (FEC) encoding, each of the inner code codewords participating in the inner code encoding and having a total of N bits, one first bit set and one parity bit set, N = K + P, each parity bit set having P bits, and P being an integer of 1 or more, Performing a cyclic shift separately on the m inner code codewords to obtain m third bit sets, each of the third bit sets having one parity bit set and one second bit set obtained by performing the cyclic shift on the first bit set, Obtaining 2 bits from each of the third bit sets through round robin to obtain a fourth bit set, the fourth bit having m×N bits, a total of m×K bits from the m second bit sets being consecutive in the fourth bit set, and a total of m×P bits from the m parity bit sets being consecutive in the fourth bit set, Comprising Each of the second data streams has a plurality of fourth bit sets, a total of m×N / 2 PAM4 symbols are obtained through the mapping of each of the fourth bit sets, and m×2 bits mapped to m consecutive PAM4 symbols among the m×N / 2 PAM4 symbols are from the m inner code codewords, the data processing method.

58. For each of the first data streams, the outer coding is performed, and at least 10 PAM4 symbols are obtained through the interleaving and coding process and the mapping of 20 consecutive bits in the first data stream, where the 20 consecutive bits are from two outer code symbols in one outer code word, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream. The method according to claim 57.

59. The amount of bits of the cyclic shift performed on any two of the m first bit sets is different. The method according to claim 57 or 58.

60. Both the m inner code words and the m third bit sets are represented as bit matrices, and the bit matrix comprises bits in m rows and N columns. The method according to any one of claims 57 to 59.

61. The second bit set is obtained by 【Number 25】 performing a left cyclic shift of bits on the first bit set, the left cyclic shift satisfies a first condition, and the first condition is 【Number 26】 comprising M c [i][j] represents a bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code codewords before the left circular shift is performed, M 3 [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m third bit sets obtained through the left cyclic shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0≦i<m, 【Number 27】 and. The method according to claim 60.

62. The second bit set is obtained by performing a right circular shift of δ i bits with respect to the first bit set, the right circular shift satisfies a second condition, and the second condition is 【Number 28】 comprising M c [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m inner code codewords before the right circular shift is performed, M 3 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ i < m, and 0 ≦ δ i <The method according to claim 60, wherein K is

63. The m third bit sets and the fourth bit set satisfy a third condition, and the third condition is [[Number 29]] equipped with, M 3 [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m third bit sets, 【Count 30】 represents the bit in the 【Number 31】 th of the fourth bit set, 0≦i<m, 0≦j<N, 【Number 32】 represents a floor operation. The method according to any one of claims 60 to 62.

64. K = 120, m = 8, and the i-th second bit set is obtained by 【Number 33】 performing the left cyclic shift of bits on the i-th first bit set, 0≦i<8, 【Number 34】 The value of satisfies any one of the items of the first value 【Number 35】 of the item of the first value 【Number 36】 is {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 {0, 90, 30, 60, 110, 80, 20, 50}, or {0,90,60,30,110,80,50,20} The method according to claim 57, 58, 59, 60, 61, or 63, comprising

65. K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8 and the value of δ satisfies any one of the items of the second value {δ i , δ i , δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7}, and the item of the second value {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 {0, 90, 30, 60, 10, 100, 40, 70}, or {0,90,60,30,10,100,70,40} The method according to claim 57, 58, 59, 60, 62, or 63, comprising

66. A data processing method, comprising n 0 each n in the 1 n first data streams, separately perform interleaving and encoding processes on each of the n first data streams to obtain one second data stream, and overall obtain n 2 second data streams, where n 2 = n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0, step the foregoing n 2 separately mapping each 2 bits among the foregoing n second data streams to one PAM4 symbol, to obtain a total of n 2 PAM4 symbol data streams; and and comprising wherein the interleaving and encoding processes said n 1 a number of first bit sets are obtained from each of the n 0 first data streams, and overall m = n 1 × a 0 first bit sets are obtained, where outer coding is performed on all of the n 1 first data streams, each of the first bit sets has K bits, and n 1 a 0 and K are all integers greater than 1 separately perform a cyclic shift on each of the m first bit sets to obtain m second bit sets, and separately perform inner encoding on each of the m first bit sets to obtain m parity bit sets, wherein both the inner encoding and the outer encoding are forward error correction (FEC) encodings, each of the second bit sets comprises K bits, each of the parity bit sets comprises P bits, and P is an integer greater than or equal to 1, obtaining, through round-robin, 2 bits from each of the second bit sets to obtain a total of m×K consecutive bits, and obtaining, through round-robin, 2 bits from each of the parity bit sets to obtain a total of m×P consecutive bits, and obtaining a third bit set comprising m×N bits and comprising N = K + P, each second data stream comprises a plurality of third bit sets, each of the third bit sets comprises the m×K bits in the second bit sets and the m×P bits in the parity bit sets, a total of m×K / 2 PAM4 symbols are obtained through the mapping of the m×K bits in each of the third bit sets from the second bit sets, a total of m×P / 2 PAM4 symbols are obtained through the mapping of the m×P bits in each of the third bit sets from the plurality of parity bit sets, and m×2 bits mapped to m consecutive PAM4 symbols among the total of m×N / 2 PAM4 symbols are from the m second bit sets and / or the m parity bit sets, the data processing method.

67. For each of the first data streams, the outer coding is performed, and at least 10 PAM4 symbols are obtained through the interleaving and coding process and the mapping of 20 consecutive bits in the first data stream, where the 20 consecutive bits are from two outer code symbols in one outer codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream. The method according to claim 66.

68. The method according to claim 66 or 67, wherein the amount of bits of the cyclic shift performed on any two of the m first bit sets is different.

69. The method according to any one of claims 66 to 68, wherein both the m first bit sets and the m second bit sets are represented as bit matrices, and the bit matrix comprises bits of m rows and K columns.

70. The second bit set is obtained by 【No. 37】 performing a left cyclic shift of bits on the first bit set, the left cyclic shift satisfying a first condition, and the first condition being 【Number 38】 comprising M 1 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets for which the left circular shift has not been performed, M 2 [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m second bit sets obtained through the left cyclic shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0≦j<K, 0≦i<m, 【Number 39】 The method according to claim 69.

71. The second bit set is obtained by performing a right circular shift of δ i bits with respect to the first bit set, the right circular shift satisfies a second condition, and the second condition is M 2 [i][j]=M 1 [i][(j - δ i ) % K] equipped with, M 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the right circular shift is performed, M 2 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ j < K, 0 ≦ i < m, 0 ≦ δ i <K, the method according to claim 69.

72. K = 120, m = 8, and the i-th second bit set is obtained by 【Number 40】 performing the left cyclic shift of bits on the i-th first bit set, 0≦i<8, 【Number 41】 the value of satisfies any one of the items of the first value 【Number 42】 the items of the first value 【Number 43】 is {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 {0, 90, 30, 60, 110, 80, 20, 50}, or {0,90,60,30,110,80,50,20} The method according to any one of claims 66 to 70, comprising.

73. K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8, and the value of δ satisfies any one of the items of the second value {δ i , δ i , δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7}, and the item of the second value {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 {0, 90, 30, 60, 10, 100, 40, 70}, or {0,90,60,30,10,100,70,40} The method according to claim 66, 67, 68, 69, or 71, comprising.

74. n 0 each n in each of the n first data streams 1 performing interleaving and encoding processes separately on each of the n first data streams to obtain one second data stream, and obtaining a total of n 2 second data streams, where n 2 = n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0, the step of the foregoing n 2 separately mapping each 2 bits among the n second data streams to one PAM4 symbol, to obtain a total of n 2 steps of obtaining PAM4 symbol data streams, and The interleaving and coding process is said n 1 each of the n first data streams to obtain a 0 number of first bit sets, and overall m = n 1 × a 0 number of first bit sets are obtained, where the outer coding is performed on all of the n 1 first data streams, each of the first bit sets comprises K bits, n 1 , a 0 , and K are all integers greater than 1, and Performing a separate cyclic shift on each of the m first bit sets to obtain m second bit sets, each of the second bit sets comprising K bits, Performing a separate inner coding on each of the m second bit sets to obtain m inner coded words, both the inner coding and the outer coding being forward error correction (FEC) coding, each of the inner coded words comprising one second bit set that participates in the inner coding and has a total of N bits and one parity bit set, N = K + P, each parity bit set comprising P bits, and P being an integer greater than or equal to 1, Obtaining a third bit set by obtaining 2 bits from each of the inner coded words through round robin, the third bit set comprising m × N bits, a total of m × K bits from the m second bit sets being consecutive in the third bit set, and a total of m × P bits from the m parity bit sets being consecutive in the third bit set, Each second data stream comprising a plurality of third bit sets, a total of m × N / 2 PAM4 symbols being obtained through the mapping of each of the third bit sets, and m × 2 bits mapped to m consecutive PAM4 symbols among the m × N / 2 PAM4 symbols being from the m inner coded words, a data processing method.

75. The method according to claim 74, wherein the outer coding is performed on each of the first data streams, and at least 10 PAM4 symbols are obtained through the interleaving and coding process and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits being from 2 outer code symbols in one outer coded word, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream.

76. The method according to claim 74 or 75, wherein the amount of bits of the cyclic shift performed on any two of the m first bit sets is different.

77. The method according to any one of claims 74 to 76, wherein both the m first bit sets and the m second bit sets are represented as bit matrices, and the bit matrix comprises bits of m rows and K columns.

78. wherein the second bit set is 【Number 44】 obtained by performing a left circular shift of bits with respect to the first bit set, the left circular shift satisfies a first condition, and the first condition is 【Number 45】 equipped with, M 1 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets where the left circular shift has not been performed, M 2 [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m second bit sets obtained through the left circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ i < m, 0 ≦ j < K, 【Number 46】 and the method according to claim 77.

79. the second bit set is obtained by performing a right circular shift of δ bits with respect to the first bit set i wherein the right circular shift satisfies a second condition, and the second condition is M 2 [i][j] = M 1 [i][(j - δ i ) % K] comprising M 1 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets where the right circular shift has not been performed, M 2 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ i < m, 0 ≦ j < K, 0 ≦ δ i <K, the method according to claim 77.

80. The m inner code codewords are represented as a bit matrix having m rows and N columns, the m inner code codewords and the third bit set satisfy a third condition, and the third condition is 【Number 47】 comprising M c [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m inner code codewords, 【Number 48】 represents the 【Number 49】 -th bit in the third bit set, 0 ≦ i < m, 0 ≦ j < N, 【Number 50】 and represents a floor operation, and the method according to any one of claims 77 to 79.

81. K = 120, m = 8, and the i-th second bit set is obtained by performing [Number 51] a left circular shift of bits with respect to the i-th first bit set, 0 ≦ i < 8, 【Number 52】 the value of 【Number 53】 satisfies any one of the items of the first value 【Number 54】 where the items of the first value {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 {0, 90, 30, 60, 110, 80, 20, 50}, or {0,90,60,30,110,80,50,20} and the method according to claim 74, 75, 76, 77, 78, or 80.

82. K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8, and the value of δ satisfies any one of the items of the second value {δ i , δ i , δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7}, and the item of the second value {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 {0, 90, 30, 60, 10, 100, 40, 70}, or {0,90,60,30,10,100,70,40} and the method according to claim 74, 75, 76, 77, 79, or 80.

83. A data processing method, n 0 each n in each of the n first data streams 1 perform interleaving and encoding processes separately on each of the n first data streams to obtain one second data stream, and obtain a total of n 2 second data streams, where n 2 = n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0, the step of said n 2 Separately mapping each 2 bits in said n 2 second data streams into one PAM4 symbol to obtain a total of n comprising wherein the interleaving and encoding processes said n 1 a number of first bit sets are obtained from each of the n 0 first data streams, and overall m = n 1 × a 0 first bit sets are obtained, where outer coding is performed on all of the n 1 first data streams, each of the first bit sets has K bits, and n 1 , a 0 , and K are all integers greater than 1 To separately perform inner coding on the m first bit sets to obtain m inner codewords, wherein both the inner coding and the outer coding are forward error correction (FEC) coding, each of the inner codewords includes one first bit set that participates in the inner coding and has a total of N bits and one parity bit set, N = K + P, each parity bit set includes P bits, and P is an integer greater than or equal to 1. The step of separately interleaving the m inner codewords to obtain one second bit set, wherein the second bit set includes m × N bits, and the 【Number 55】 bit in the second bit set satisfies a first condition or a second condition, 0 ≤ i < m, 0 ≤ j < N, The first condition is 【Number 56】 comprising 【Number 57】 represents the 【Number 58】 bit in the second bit set, 【Number 59】 is the 【Number 60】 represents a bit, and C i [j] represents the j-th bit in the i-th inner codeword, The second condition is 【Number 61】 comprising 【Number 62】 represents the 【Number 63】 represents the bit, and C i [(j - δ i ) % K] represents the bit at the ((j - δ i ) % K) - th position in the i - th inner codeword, and C i [j] represents the j - th bit in the i - th inner codeword. Each second data stream includes a plurality of second bit sets, and a total of m × N / 2 PAM4 symbols are obtained through the mapping of each of the second bit sets, and the m × 2 bits mapped to m consecutive PAM4 symbols among the m × N / 2 PAM4 symbols are from the m inner codewords. A data processing method. [

84. ] K = 120, m = 8, 【Number 64】 The value of satisfies any one of the items of the first value 【Number 65】 Among the items of the first value 【Number 66】 is {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 {0, 90, 30, 60, 110, 80, 20, 50}, or {0,90,60,30,110,80,50,20} comprising δ i where the value of 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} satisfies any one of, and the item of the second value {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 {0, 90, 30, 60, 10, 100, 40, 70}, or {0,90,60,30,10,100,70,40} comprising. The method according to claim 83. [

85. ] A data processing apparatus comprising an interleaving and encoding module and a bit mapping module, The interleaving and encoding module performs interleaving and encoding processes separately for each of the n 0 first data streams of the n 1 first data streams to obtain one second data stream, and is configured to obtain a total of n 2 second data streams, where n 2 = n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0 The bit mapping module maps each 2 bits in the n 2 second data streams to one PAM4 symbol separately, so as to obtain a total of n 2 PAM4 symbol data streams, The interleaving and encoding module, in particular, for each of the n 1 first data streams, obtains a 0 first bit sets, and in total obtains m = n 1 × a 0 first bit sets, and outer coding is performed on all of the n 1 first data streams, each of the first bit sets comprising K bits, where n 1 , a 0 , and K are all integers greater than 1, To separately perform inner coding on the m first bit sets to obtain m inner codewords, wherein both the inner coding and the outer coding are forward error correction (FEC) coding, each of the inner codewords includes one first bit set that participates in the inner coding and has a total of N bits and one parity bit set, N = K + P, each parity bit set includes P bits, and P is an integer greater than or equal to 1. For the m inner code codewords, perform cyclic shifts separately to obtain m third bit sets, each of the third bit sets comprising one parity bit set and one second bit set obtained by performing the cyclic shift on the first bit set. In each of the third bit sets, obtain a fourth bit set based on a 2-bit round robin, the fourth bit set comprising m×N bits, with a total of m×K bits from the m second bit sets being consecutive in the fourth bit set and a total of m×P bits from the m parity bit sets being consecutive in the fourth bit set. Each of the second data streams comprises a plurality of fourth bit sets, with a total of m×N / 2 PAM4 symbols obtained through the mapping of each of the fourth bit sets, and m×2 bits mapped to m consecutive PAM4 symbols among the m×N / 2 PAM4 symbols being from the m inner code codewords, a data processing apparatus.

86. The outer code encoding is performed on each of the first data streams, and at least 10 PAM4 symbols are obtained through the interleaving and encoding process and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits being from two outer code symbols in one outer code codeword, and any two of the at least 10 PAM4 symbols being separated by at least 2 PAM4 symbols in the PAM4 symbol data stream, the data processing apparatus according to Claim 85.

87. The amount of bits of the cyclic shift performed on any two of the m first bit sets is different, the data processing apparatus according to Claim 85 or 86.

88. Both the m inner code codewords and the m third bit sets are represented as bit matrices, the bit matrix comprising m rows and N columns of bits, the data processing apparatus according to any one of Claims 85 to 87.

89. The second bit set is obtained by 【Number 67】 performing a left cyclic shift of bits on the first bit set, the left cyclic shift satisfying a first condition, the first condition being 【Number 68】 comprising M c [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m inner code codewords before the left cyclic shift is performed, M 3 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets obtained through the left circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ i < m, 【Number 69】 The data processing apparatus according to claim 88, wherein Claim 90 the second bit set is obtained by performing a right circular shift of δ bits with respect to the first bit set, the right circular shift satisfies a second condition, and the second condition is i obtained by performing a right circular shift of the bits, the right circular shift satisfies a second condition, and the second condition is 【Number 70】 equipped with, M c [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m inner code codewords before the right circular shift is performed, M 3 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m third bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ i < m, and 0 ≦ δ i <The data processing apparatus according to claim 88, wherein <K>. Claim 91 the m third bit sets and the fourth bit set satisfy a third condition, and the third condition is 【Numerical value 71】 equipped with, M 3 [i][j] represents the bit in the i-th row and the j-th column of the bit matrix corresponding to the m third bit sets, 【Number 72】 represents the bit in the 【Number 73】 of the fourth bit set, 0 ≦ i < m, 0 ≦ j < N, 【Number 74】 The data processing apparatus according to any one of claims 88 to 90, wherein represents a floor operation. Claim 92 K = 120, m = 8, and the i-th second bit set is obtained by performing 【Number 75】 a left circular shift of bits on the i-th first bit set, 0 ≦ i < 8, 【Number 76】 the value of which satisfies any one of the items of the first value 【Number 77】 and the items of the first value 【Number 78】 are {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 {0, 90, 30, 60, 110, 80, 20, 50}, or {0,90,60,30,110,80,50,20} The data processing apparatus according to claim 85, 86, 87, 88, 89, or 91, comprising Claim 93 K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8, and the value of δ satisfies any one of the items of the second value {δ i , δ i , δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7}, and the item of the second value {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 {0, 90, 30, 60, 10, 100, 40, 70}, or {0,90,60,30,10,100,70,40} The data processing apparatus according to claim 85, 86, 87, 88, 90, or 91, comprising Claim 94 A data processing apparatus, comprising an interleaving and encoding module and a bit mapping module, The interleaving and encoding module performs interleaving and encoding processes separately for each of the n 0 first data streams of the first data streams to obtain one second data stream, and is configured to obtain a total of n 1 second data streams, where n 2 = n 2 = n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0. The bitmapping module maps each 2 bits in the n 2 second data streams to one PAM4 symbol separately, so as to obtain a total of n 2 PAM4 symbol data streams, and is configured as such. The interleaving and encoding module in particular, for each of the n 1 first data streams, obtains a 0 first bit sets, and in total obtains m = n 1 × a 0 first bit sets, and performs outer coding on all of the n 1 first data streams, each of the first bit sets comprising K bits, where n 1 , a 0 , and K are all integers greater than 1, performing a circular shift separately on the m first bit sets to obtain m second bit sets, performing inner code encoding separately on the m first bit sets to obtain m parity bit sets, both the inner code encoding and the outer code encoding being forward error correction (FEC) encoding, each of the second bit sets comprising K bits, each of the parity bit sets comprising P bits, and P being an integer greater than or equal to 1, Through round-robin, two bits are obtained from each of the second bit sets to obtain a total of m×K consecutive bits, and through round-robin, two bits are obtained from each parity bit set to obtain a total of m×P consecutive bits, and a third bit set with m×N bits is obtained, where N = K + P, and is configured as such. Each of the second data streams includes a plurality of third bit sets, each of the third bit sets includes the m×K bits in the second bit set and the m×P bits in the parity bits, and a total of m×K / 2 PAM4 symbols are obtained through the mapping of the m×K bits in each of the third bit sets from the second bit set, and a total of m×P / 2 PAM4 symbols are obtained through the mapping of the m×P bits in each of the third bit sets from the parity bit set, and m×2 bits mapped to m consecutive PAM4 symbols out of a total of m×N / 2 PAM4 symbols are from the m second bit sets and / or the m parity bit sets. A data processing device.

95. The outer code encoding is performed for each of the first data streams, and at least 10 PAM4 symbols are obtained through the interleaving and encoding process and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer code symbols in one outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream. The data processing device according to claim 94.

96. The amount of bits of the cyclic shift performed on any two of the m first bit sets is different. The data processing device according to claim 94 or 95.

97. Both the m first bit sets and the m second bit sets are represented as bit matrices, and the bit matrix includes m rows and K columns of bits. The data processing device according to any one of claims 94 to 96.

98. The second bit set is relative to the first bit set 【Number 79】 Obtained by performing a left circular shift of bits, wherein the left circular shift satisfies a first condition, and the first condition is 【Number 80】 comprising M 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets for which the left circular shift has not been performed, M 2 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets obtained through the left circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ j < K, 0 ≦ i < m, 【Number 81】 The data processing apparatus according to claim 97.

99. wherein the second bit set is obtained by performing a right circular shift of δ i bits with respect to the first bit set, the right circular shift satisfies a second condition, and the second condition is M 2 [i][j] = M 1 [i][(j - δ i ) % K] comprising M 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the right circular shift is performed, M 2 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ j < K, 0 ≦ i < m, 0 ≦ δ i <The data processing apparatus according to claim 97, wherein <K.

100. K = 120, m = 8, and the i-th second bit set is obtained by 【Number 82】 performing the left circular shift of bits with respect to the i-th first bit set, where 0 ≦ i < 8, 【Number 83】 of the item with the first value 【Number 84】 any one of which satisfies, and the item of the first value 【Number 85】 is {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 {0, 90, 30, 60, 110, 80, 20, 50}, or {0,90,60,30,110,80,50,20} The data processing apparatus according to any one of claims 94 to 98.

101. K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≦ i < 8, and the value of δ satisfies any one of the items of the second value {δ i , δ i , δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7}, and the item of the second value {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 {0, 90, 30, 60, 10, 100, 40, 70}, or {0,90,60,30,10,100,70,40} The data processing apparatus according to claim 94, 95, 96, 97, or 99.

102. A data processing apparatus, comprising an interleaving and encoding module and a bit mapping module, The interleaving and encoding module performs interleaving and encoding processes separately for each of the n 0 first data streams to obtain one second data stream, and is configured to obtain a total of n 1 second data streams, where n 2 = n 2 = n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0. The bit mapping module maps each 2 bits in the n 2 second data streams separately to one PAM4 symbol, so as to obtain a total of n 2 PAM4 symbol data streams, and is configured as such. The interleaving and encoding module, in particular, for each of the n 1 first data streams, obtains a 0 first bit sets, and in total obtains m = n 1 × a 0 first bit sets, and outer coding is performed on all of the n 1 first data streams, each of the first bit sets comprises K bits, and n 1 , a 0 , and K are all integers greater than 1. performing a circular shift separately on the m first bit sets to obtain m second bit sets, each of the second bit sets having K bits, performing inner code encoding separately on the m second bit sets to obtain m inner code codewords, both the inner code encoding and the outer code encoding being forward error correction (FEC) encoding, each of the inner code codewords participating in the inner code encoding and having a total of N bits including one second bit set and one parity bit set, N = K + P, each parity bit set having P bits, and P being an integer greater than or equal to 1, configured such that, through round robin, 2 bits are obtained from each inner code codeword to obtain a third bit set, the third bit set having m×N bits, a total of m×K bits from the m second bit sets being consecutive in the third bit set, and a total of m×P bits from the m parity bit sets being consecutive in the third bit set. Each second data stream comprises a plurality of third bit sets, and a total of m×N / 2 PAM4 symbols are obtained through each of the mappings of the third bit sets, and m×2 bits mapped to m consecutive PAM4 symbols among the m×N / 2 PAM4 symbols are from the m inner code codewords, a data processing apparatus.

103. The outer code encoding is performed for each of the first data streams, and at least 10 PAM4 symbols are obtained through the interleaving and encoding process and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer code symbols in one outer code codeword, and any two of the at least 10 PAM4 symbols are separated by at least 2 PAM4 symbols in the PAM4 symbol data stream, the data processing apparatus according to claim 102.

104. The amount of bits of the cyclic shift performed on any two of the m first bit sets is different, the data processing apparatus according to claim 102 or 103.

105. Both the m first bit sets and the m second bit sets are represented as bit matrices, the bit matrix comprising bits of m rows and K columns, the data processing apparatus according to any one of claims 102 to 104.

106. The second bit set is obtained by performing 【Number 86】 a left cyclic shift of bits on the first bit set, the left cyclic shift satisfies a first condition, and the first condition is 【Number 87】 comprising M 1 [i][j] represents a bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets before the left cyclic shift is performed, M 2 [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m second bit sets obtained through the left cyclic shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0≦i<m, 0≦j<K, 【Number 88】 and, the data processing apparatus according to claim 105.

107. the second bit set is obtained by performing a right circular shift of δ bits with respect to the first bit set, the right circular shift satisfies a second condition, and the second condition is i obtained by performing a right circular shift of δ bits with respect to the first bit set, the right circular shift satisfies a second condition, and the second condition is M 2 [i][j]=M 1 [i][(j - δ i ) % K] equipped with, M 1 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m first bit sets for which the right circular shift has not been performed, M 2 [i][j] represents the bit in the i-th row and j-th column of the bit matrix corresponding to the m second bit sets obtained through the right circular shift, Y%Z represents the remainder obtained by dividing the integer Y by the integer Z, 0 ≦ i < m, 0 ≦ j < K, 0 ≦ δ i <The data processing apparatus according to claim 105, wherein <K.

108. The m inner code codewords are represented as a bit matrix having m rows and N columns, the m inner code codewords and the third bit set satisfy a third condition, and the third condition is 【Number 89】 equipped with, M c [i][j] represents the bit in the i-th row and j-th column in the bit matrix corresponding to the m inner code codewords, 【Number 90】 represents the bit of the in the third bit set, where 0 ≤ i < m and 0 ≤ j < N, 【Number 91】 and represents the floor operation, a data processing apparatus according to any one of claims 105 to 107. 【Number 92】 **Claim 109** where K = 120, m = 8, and the i-th second bit set is obtained by performing a left circular shift of bits on the i-th first bit set, where 0 ≤ i < 8, and the value of satisfies any one of the items of the first value 【No. 93】 where the item of the first value 【Number 94】 is 【Number 95】 {0, 90, 30, 60, 110, 80, 20, 50}, or 【Number 96】 a data processing apparatus according to claim 102, 103, 104, 105, 106, or 108. {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 **Claim 110** {0,90,60,30,110,80,50,20} {0, 90, 30, 60, 10, 100, 40, 70}, or a data processing apparatus according to claim 102, 103, 104, 105, 107, or 108. K = 120, m = 8, and the i-th second bit set is obtained by performing a right circular shift of δ bits on the i-th first bit set, where 0 ≤ i < 8, and the value of δ satisfies any one of the items of the second value {δ i , δ i , δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7}, and the item of the second value {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 **Claim 111** {0,90,60,30,10,100,70,40} A data processing apparatus comprising: an interleaving and encoding module and a bit mapping module; performing inner code encoding separately on the m first bit sets to obtain m inner code codewords, where both the inner code encoding and the outer code encoding are forward error correction (FEC) encodings, and each of the inner code codewords comprises one first bit set and one parity bit set that participate in the inner code encoding and have N bits in total, where N = K + P, each parity bit set comprises P bits, and P is an integer greater than or equal to 1; interleaving the m inner code codewords separately to obtain one second bit set, where the second bit set comprises m × N bits, and the bit of the second bit set satisfies a first condition or a second condition, where 0 ≤ i < m and 0 ≤ j < N; The interleaving and encoding module performs interleaving and encoding processes separately for each of the n 0 first data streams to obtain one second data stream, and is configured to obtain a total of n 1 second data streams, where n 2 = n 2 = n 0 / n 1 and n 0 is an integer greater than 1, and n 1 is an integer greater than 0. The bit mapping module maps each 2 bits in the n 2 second data streams to one PAM4 symbol separately, so as to obtain a total of n 2 PAM4 symbol data streams, and is configured as such. The interleaving and encoding module, in particular, for each of the n 1 first data streams, obtains a 0 first bit sets, and in total m = n 1 × a 0 first bit sets are obtained, and outer coding is performed on all of the n 1 first data streams, each of the first bit sets comprising K bits, where n 1 , a 0 , and K are all integers greater than 1. where the first condition comprises and represents the bit of the in the second bit set, 【Number 97】 and represents the bit of the in the i-th inner code codeword, where the second condition comprises 【Number 98】 and represents the bit of the in the second bit set, 【Number 99】 each second data stream comprises a plurality of second bit sets, and a total of m × N / 2 PAM4 symbols are obtained through the mapping of each of the second bit sets, and the m × 2 bits mapped to m consecutive PAM4 symbols among the m × N / 2 PAM4 symbols are from the m inner code codewords. 【Number 100】 **Claim 112** 【Number 101】 ​ 【Number 102】 represents a bit, and C i [j] represents the j-th bit in the i-th inner codeword, ​ 【Number 103】 ​ 【Number 104】 ​ 【Number 105】 represents the bit, and C i [(j - δ i ) % K] represents the bit at the ((j - δ i ) % K) - th position in the i - th inner codeword, and C i [j] represents the j - th bit in the i - th inner codeword, ​ ​ K = 120, m = 8, 【Number 106】 the value of satisfies any one of the items of the first value 【Number 107】 and any one of the items of the first value 【Number 108】 is {0,30,60,90,110,20,50,80}、 {0,30,90,60,110,20,80,50}、 {0,60,30,90,110,50,20,80}、 {0,60,90,30,110,50,80,20}、 {0, 90, 30, 60, 110, 80, 20, 50}, or {0,90,60,30,110,80,50,20} comprising δ i where the value of 0 δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} satisfies any one of them, and the item {δ 0 , δ 1 , δ 2 , δ 3 , δ 4 , δ 5 , δ 6 , δ 7} of the second value is {0,30,60,90,10,40,70,100}、 {0,30,90,60,10,40,100,70}、 {0,60,30,90,10,40,70,100}、 {0,60,90,30,10,70,100,40}、 {0, 90, 30, 60, 10, 100, 40, 70}, or {0,90,60,30,10,100,70,40} The data processing apparatus according to claim 111, comprising.

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