Power switch with a small installation area

Abstract

The power switch includes a pair of substantially parallel half - bridges, a printed circuit board (PCB) controller operable to turn the half - bridges on and off, power terminals for coupling a high - energy power source to the half - bridges, and power phase output terminals for connecting a load to the half - bridges. The half - bridges, the PCB, the power terminals, and the power phase output terminals are enclosed within the same encapsulation envelope having a relatively large planar first face surface where the contact surfaces of the terminals are exposed.

Description

Technical Field

[0001] Related Applications This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63 / 358,886, filed on Jul. 7, 2022, the disclosure of which is incorporated herein by reference.

[0002] Technical Field Embodiments of the present invention relate to power switches.

Background Art

[0003] Almost all types of modern optical and electronic devices from computers to power trains include power switching circuits for generating timing pulses, data packets, and / or transmitting power. There is a need for a power switch that can conduct a large current and can be rapidly turned on and off to couple and decouple a high-voltage power source to a load in order to transmit power to an electric power train such as a power train used to transmit power to an electric vehicle. For example, a high-power inverter that operates to transmit AC power from a DC power source to an automotive traction motor may include a half-bridge having a high-side array of GaN dies connected to a low-side array of GaN dies, and a PCB control circuit that controls the array to convert DC power to AC power. The inverter advantageously has low inductance, a small footprint, and efficient heat dissipation and can be easily mounted and expanded to meet the electrical and mechanical constraints of various electric vehicle configurations.

Summary of the Invention

Means for Solving the Problems

[0004] One aspect of an embodiment of the present disclosure relates to providing a power switch, also referred to as a Power-Mite, having a low inductance, a small footprint, being easily extensible, being easily coupled to an external electrical circuit, and being attachable to a heat sink by soldering or sintering. In one embodiment, the Power-Mite includes a pair of half-bridges and a printed circuit board (PCB) controller operable to turn the half-bridges on and off to provide voltage and current pulses to a load connected to the Power-Mite. Each half-bridge optionally includes a high-side GaN die connected to a low-side GaN die. To provide a relatively low inductance to the Power-Mite, the half-bridges are configured such that current flows in a substantially same parallel direction when the half-bridge turns on to provide voltage and current pulses to the load. The total power loop inductance during the transition between the on-state and the off-state of the Power-Mite may be less than about 2.5 nanohenries (nH).

[0005] In one embodiment, the half-bridges, the PCB controller, and other electrical and mechanical components of the Power-Mite are encapsulated within a protective polymer envelope, which may be referred to as an envelope. The envelope has a substantially continuous and uniform geometric outer shape and includes a relatively large parallel planar face of the same shape and at least one relatively narrow end face. The envelope may be, for example, a substantially rectangular parallelepiped, a rectangular parallelepiped having rounded parallelogram faces, or a solid having quadrilateral faces. In one embodiment, terminals providing electrical contact to one or more components within the envelope are embedded within the envelope and have electrical contact surfaces for making electrical contact with terminals located on the surface of the envelope. In one embodiment, the contact surface of the terminal is substantially coplanar with the surface on which it is located. Optionally, the contact surface is recessed or raised with respect to the surface on which it is located. In one embodiment, the contact surface is located on a face of the envelope. Optionally, the contact surfaces of all terminals are located on the same face.

[0006] The PowerMite may include terminal pins that extend from an end face of the envelope and make electrical contact with one or more components within the envelope. In one embodiment, the terminal pins include terminal pins that are diagonally opposed to each other at opposite end faces of the envelope.

[0007] The summary of the invention is provided to introduce, in a simplified form, selected portions of concepts that are further described in the following brief description of the drawings. The summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Brief Description of the Drawings

[0008] Non-limiting examples of embodiments of the present invention are described below with reference to the accompanying drawings listed following this paragraph. Identical structures, elements, or parts that appear in multiple figures are usually labeled with the same reference numerals in all the figures in which they appear. The dimensions of the components and features shown in the figures are selected for the sake of convenience of display and clarity and are not necessarily shown to scale.

[0009]

Figure 1A

Figure 1B

Figure 1C

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

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Figure 2G

Figure 3A

Figure 3B

Figure 3C

Mode for Carrying Out the Invention

[0010] In this specification, unless otherwise specified, adjectives such as "substantially" and "about" that modify the conditions or relative characteristics of the features of the embodiments of the present disclosure are understood to mean that the conditions or characteristics are defined within an acceptable range that is acceptable for the operation for the intended use of the embodiments. When general terms in the present disclosure are explained by referring to exemplary examples or a list of exemplary examples, the examples referred to are always non-limiting examples of the general terms, and the general terms are not intended to be limited to the specific examples referred to. The expression "in one embodiment" is used to introduce a configuration that is an example, but not necessarily required, of a possible embodiment of the present disclosure for consideration, regardless of whether it is associated with permissive expressions such as "may", "optionally", or "as an example". The verbs "comprise", "include", and "have", and their respective conjugations, are used to indicate that the object of the verb is not necessarily a complete list of components, elements, or parts of the subject of the verb. Unless otherwise indicated, the word "or" in the specification and claims is considered an inclusive "or" rather than an exclusive disjunction, indicating at least one of the items it combines, or any combination of multiple items.

[0011] Figures 1A and 1B schematically show perspective views from the top and bottom, respectively, of a power module 20 optionally configured to supply power to the phases of a traction motor of an electric vehicle, according to one embodiment of the present disclosure. The power module 20 includes an optionally rectangular parallelepiped envelope 22 having a top face 23 shown in Figure 1A, a bottom face 24 shown in Figure 1B, and four relatively narrow end faces 25. The envelope 22 may be formed by dicing a plurality of power modules 20 from a common multi-unit encapsulation mold in which the power modules are encapsulated in a suitable polymer.

[0012] The terminals (not shown in FIGS. 1A and 1B) described below that contact components of the PowerMite 20 are enclosed within the envelope 22 and have contact surfaces 30-1, 30-2, 30-3, 30-4 that are exposed on the top surface 23 and are generally referred to as contact surface 30. Contact surfaces 30-1, 30-2 are the surfaces of power terminals 41, 42, respectively, described below, and power terminals 41, 42 can be used to couple power from a high energy power source (not shown) to a half-bridge enclosed within the envelope 22. Contact surface 30-3 is the surface of a power phase output terminal 43, described below, and power phase output terminal 43 can be used to couple voltage and current to the phases of an electric motor. Contact surface 30-4 is the surface of a control terminal 44, described below, and control terminal 44 can be used to couple a control circuit to a PCB controller, described below, enclosed within the envelope 22.

[0013] Optionally, as schematically shown in FIG. 1A, the contact surface 30 is in the same plane as the top surface 23 and is substantially flush. In one embodiment, the contact surface 30 may be raised or recessed to electrically insulate the contact surface and / or facilitate electrical contact with the contact surface. The contact surface 30 is formed from a material adapted to electrically and mechanically couple a conductor that is intended to provide electrical contact between an external circuit and the surface and each terminal of which the surface is a feature to the surface. In one embodiment, the contact surface 30 is configured to be electrically and mechanically coupled to a conductor by soldering, laser welding, or ultrasonic welding. Optionally, the surface 30 and its associated underlying terminals are configured such that a conductor can be screwed or press-fitted into holes formed within the terminals. The bottom surface 24 shown in FIG. 1B optionally has a conductive thermal interface 26 formed on the surface. This thermal interface may be formed from any of a variety of suitable high thermal conductivity materials such as, for example, thermally conductive solder or adhesive, sintered or cured silver paste.

[0014] In one embodiment, the power module 20 may include terminal pins in addition to, or instead of, the contact surface 30. FIG. 1C schematically shows a power module 21 according to an embodiment of the present disclosure. The power module 21 is similar to the power module 20, but includes a set 46 of terminal pins 47 and a set 48 of terminal pins 49 instead of the terminals having the contact surface 30 on the top face 23. In one embodiment, the set 46 of terminal pins 47 and the set 48 of terminal pins 49 are diagonally opposed to each other at the opposing (opposite) end faces 25 of the envelope 22. As will be described below with respect to FIGS. 3A and 3B, since the terminal pin sets 46 and 48 are diagonally opposed to each other, it becomes easy to densely arrange a plurality of power modules 20, and it becomes easy to connect the power modules in parallel to realize high-current switching.

[0015] Note that a dividing line 27 for arranging the terminal pins is shown in the envelope 22 of FIG. 1C. While it may be advantageous to enclose the terminals of a plurality of power modules 20 (for example, terminals 41 to 44 having the contact surface 30) in a common multi-unit encapsulation mold and then dice the circuits of the power modules 20 to separate the circuits of the individual power modules 20, it may be advantageous to individually enclose the power modules having terminal pins (for example, terminal pins 47 and 49) in a single-unit mold. In the process of dicing after multi-unit encapsulation, the dividing line disappears from the envelope 22, but a two-piece release mold is usually required for individual single-unit encapsulation, and as a result, typically, the dividing line 27 appears in the envelope 22 shown in FIG. 1C.

[0016] FIGS. 2A to 2G schematically show the stages of construction and assembly of a power module 20 according to an embodiment of the present disclosure.

[0017] Figure 2A schematically shows the first stage of the construction of the PowerMite 20. A pattern of conductive traces, generally referred to as traces 50, to which the components of the PowerMite are electrically connected, is formed on the upper surface 41 of an optional DBC (Direct Bonded Copper) substrate 40. In one embodiment, the traces 50 include a positive power terminal trace 51, a negative power terminal trace 52, a power output phase trace 53, a control trace 54, and die connection traces 55, 56, 57, 58. Connection pins 60 that can be used to electrically connect the circuit components of the PowerMite to a PCB controller 100 (not shown in Figure 2A) encapsulated within the PowerMite 20 are attached to the traces 50. In one embodiment, a conductive spacer 62 is electrically connected to the power trace 51 and facilitates the connection between the power trace and the metallized electrodes of the components of the PowerMite. As schematically shown in Figure 2C and described below, the spacer 62 uses planar interconnects to facilitate an electrical connection from the top surface of the trace 50 to the metallized electrodes of the components of the PowerMite that are raised by the thickness of the components.

[0018] Figure 2B schematically shows semiconductor dies directly connected to each of the plurality of traces 50 to form two half - bridges 70, 80 of the PowerMite 20. In one embodiment, the half - bridge 70 includes a high - side, optionally normally - on, lateral n - channel GaN (Gallium Nitride) die 72, a high - side, optionally p - channel MOSFET (Metal - Oxide - Semiconductor Field - Effect Transistor) die 74, a low - side, optionally normally - on, lateral n - channel GaN die 76, and a low - side, optionally p - channel MOSFET die 78. Similarly, the half - bridge 80 may include a high - side, optionally normally - on, lateral n - channel GaN die 82, a high - side, optionally p - channel MOSFET die 84, a low - side, optionally normally - on, lateral n - channel GaN die 86, and a low - side, optionally p - channel MOSFET die 88.

[0019] Each of the normally-on GaN dies 72, 76, 82, 86 optionally includes an array (not shown) of columns of normally-on lateral GaN transistors (not shown), the array being connected to a fishbone configuration 90 of a metallization layer, the metallization layer including a drain fishbone metallization layer 92-D having a spine 93 interleaved with a spine 94 of a source fishbone metallization layer 95-S. The drain (not shown) of the normally-on GaN transistor is in electrical contact with the spine 92-D of the drain fishbone 93, and the source of the transistor is in electrical contact with the spine 94 of the source fishbone 95-S. The gate of the GaN transistor is optionally electrically connected by wire bonding to a control trace 54 indicated by "54g". The gate of the MOSFET transistor is optionally electrically connected by wire bonding to the control trace 54 indicated by "54g * ". The substrates (not shown) of the GaN dies 72, 76, 82, 86 are electrically connected to respective die traces 55, 57, 56, 58 to which the dies are attached.

[0020] Each of the MOSFET dies 74, 84, 78, 88 includes an array of MOSFET transistors (not shown) in which the sources are electrically connected to source metallization layers 74-S, 84-S, 78-S, 88-S respectively and the drains are connected to drain metallization layers (not shown) respectively. The drain metallization layers of the high-side MOSFET dies 74, 84 are electrically connected to a power output phase output trace 53. Each drain metallization layer of the low-side MOSFET dies 78, 88 is electrically connected to a negative power trace 52.

[0021] In FIG. 2C, the GaN die and the MOSFET die shown in FIG. 2B are connected by planar interconnect conductors of relatively large area. The drain fishbone metallization layer 92-D (FIG. 2B) of the high-side GaN die 72 is electrically connected to the conductive spacer 62 (FIG. 2B) located on the positive power trace 51 by a conductive interconnect 73 that may be planar. The source metallization 95-S (FIG. 2B) of the high-side GaN die 72 is electrically connected to the source metallization 74-S of the high-side MOSFET 70 by a conductive interconnect 75 that may be planar. Similarly, the drain metallization 92-D (FIG. 2B) of the high-side GaN die 82 is electrically connected to the conductive spacer 62 located and connected on the positive power trace 51 by a conductive interconnect 83 that may be planar. The source metallization 95-S (FIG. 2B) of the high-side GaN die 82 is electrically connected to the source metallization 84-S of the high-side MOSFET 84 by a conductive interconnect 85 that may be planar. The source metallization layer 95-S of the low-side Gan die 76 is electrically connected to the source metallization layer 78-S of the MOSFET 78 by an interconnect 77 that may be planar, and the source metallization layer 95-S of the low-side GAN die 86 is electrically connected to the source metallization layer 88-S of the MOSFET die 88 by an interconnect 87 that may be planar. The drain metallization layers 92-D of the low-side GaN dies 76, 86 are interconnected by conductive interconnects 76-86 that may be planar. The interconnects 76-86 are in electrical contact with the conductive spacer 62 on the power output phase trace 53, thereby being in electrical contact with the power output phase trace.

[0022] Figure 2D schematically shows the direction of current in half - bridge 70 and half - bridge 80 when PowerMite 20 is on, energizing power trace 53 and supplying voltage and current from a power source connected to PowerMite 20, optionally, to a traction motor connected to PowerMite 20 via positive and negative power terminal traces 51, 52. In this figure, the band with an arrow labeled I - 70 schematically represents the flow of current through half - bridge 70. The solid - line portion of the band represents the flow of current of I - 70 on interconnects 73, 75 and conductive trace 53. The dashed - line region of band 1 - 70 represents the "hidden" portion of I - 70 that flows "downward" from interconnect 75 through MOSFET 74 (Figure 2B) and to a part of conductive trace 53 below interconnects 75, 85. Similarly, the band with an arrow labeled I - 80 schematically represents the flow of current through half - bridge 80. The solid - line portion of the band represents the flow of current of I - 80 on interconnects 83, 85 and conductive trace 53. The dashed - line region of band I - 80 represents the "hidden" portion of I - 80 that flows "downward" from interconnect 85 through MOSFET 84 (Figure 2B) and to conductive trace 53 below interconnects 75, 85. Note that currents I - 70, I - 80 flow parallel to each other on trace 53 and help reduce the inductance of PowerMite 20 when it is turned on and off.

[0023] Figure 2E schematically shows the direction of current in half - bridge 70 and half - bridge 80 when turning off PowerMite 20 by turning off high - side GaN transistors 72, 82 and MOSFETs 74, 84 and turning on low - side Gan transistors 76, 86 and low - side MOSFETs 78, 88. The current from negative power terminal trace 52 flows through current branches represented by bands I - 77, I - 87 through MOSFETs 78, 88 to conductive interconnects 76 - 86 and combines with the current represented by current band I - 53 and flows to PowerMite 20 along output phase trace 53. The dashed - line portions of the bands represent current portions hidden from the perspective of Figure 2E.

[0024] In one embodiment, the total power loop inductance of the power module 20 during the transition between the on state and the off state may be less than about 2.50 nH. Optionally, the total power loop inductance may be less than about 2.25 nH.

[0025] FIG. 2F schematically shows a power module 20 in which power terminals 41, 42 having contact surfaces 30-1, 30-2 (FIG. 1A) are respectively attached to positive and negative power terminal traces 51 and 52 (FIG. 2A), a power phase output terminal 43 having a contact surface 30-3 (FIG. 1A) is attached to a power output phase trace 53 (FIG. 2A), and a control PCB 100, which may be multilayered, is attached to the power module 20. The PCB 100 contacts components within the power module 20 via connection pins 60 (FIGS. 2A-2E) and contacts a circuit external to the power module 20 via a cylindrical control terminal 44, which may have a contact surface 30-4 (FIG. 1A). In one embodiment, the power module 20 as schematically shown in FIG. 2F is encapsulated to provide a completed power module 20 as shown in FIG. 1A.

[0026] FIG. 2G schematically shows a power module 21, which is a modification of the power module, in which the cylindrical control terminals 44 shown in FIG. 2F are replaced by sets 46, 48 that are diagonally opposed to terminal pins 47, 49, respectively, and the power module 21 has the configuration shown in FIG. 1C after encapsulation.

[0027] Power modules according to embodiments of the present disclosure, such as power modules 20, 21 designed as schematically shown in FIGS. 1A-2G, have a very beautiful configuration and a relatively small installation area. Since the installation area is small and the electrical terminals are embedded or diagonally opposed, the power modules according to embodiments of the present disclosure can be easily attached to a heat sink, optionally by soldering or sintering, and can be connected in parallel to form a compact and high-density "power pack" array.

[0028] As an example, FIGS. 3A and 3B schematically show the dimensions of the installation areas of the power pack arrays 201, 202 of six power miter saws 20, 21, respectively, according to an embodiment of the present disclosure. For comparison, FIG. 3C shows the installation area of a power pack 220 according to an embodiment, in which the terminal pin arrays are mounted directly facing each other, rather than diagonally facing each other as in the power miter saw 21. The installation areas of the power pack arrays 201, 202 are substantially smaller than the installation area of the power pack array 220.

[0029] The description of the embodiments of the invention in this application is provided as an example and is not intended to limit the scope of the invention. The described embodiments include different features, but not all of them are necessary for all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of features. Variations of the described embodiments of the invention and embodiments of the invention including different combinations of the features mentioned in the described embodiments will be variously contemplated by those skilled in the art. The scope of the invention is limited only by the claims.

Claims

1. A pair of substantially parallel half - bridges, Power terminals for coupling a power source to the half - bridges, Power phase output terminals for connecting a load to the half - bridges, A printed circuit board (PCB) controller having a control circuit operable to turn the half - bridges on and off to connect and disconnect the load to and from the power source Including, The half - bridges, the PCB, the power terminals, and the power phase output terminals are encapsulated within the same encapsulation envelope having a relatively large planar first face surface where the electrical contact surfaces of the terminals are exposed, a power switch.

2. The power switch according to claim 1, wherein the contact surfaces of the power terminals and the power phase output terminals are substantially flush with the first face surface.

3. The power switch according to claim 1, wherein the electrical contact surfaces of the power terminals and / or the power phase output terminals are raised or recessed with respect to the plane of the first face surface.

4. The power switch according to any one of claims 1 - 3, including control terminals that make electrical contact with the control circuit on the PCB controller.

5. The power switch according to claim 4, wherein the control terminals have electrical contact surfaces.

6. The power switch according to claim 5, wherein the contact surfaces of the control terminals are exposed on the first face surface.

7. The power switch according to claim 6, wherein the contact surfaces of the control terminals are substantially flush with the first face surface.

8. The power switch according to claim 7, wherein the electrical contact surface of one of the control terminals is raised or recessed with respect to the plane of the first face surface.

9. The contact surfaces and the control terminals to which the contact surfaces belong are configured to be coupled to electrical conductors, and the coupling is by soldering, ultrasonic welding or laser welding, or by pressing or screwing an electrical conductor into a hole of the control terminal, the power switch according to any one of claims 5 - 8.

10. The power switch according to any one of claims 1 - 9, wherein the encapsulation envelope is a rectangular parallelepiped that encapsulates all components of the switch.

11. The power switch according to any one of claims 1 - 3, including a plurality of control terminal pins that make electrical contact with the control circuit on the PCB controller.

12. The power switch according to claim 11, wherein the encapsulating envelope is a rectangular parallelepiped that encapsulates all components of the switch except the control terminal pins.

13. The power switch according to claim 12, wherein the rectangular parallelepiped has an end face through which a plurality of the terminal pins extend.

14. The power switch according to claim 13, wherein the plurality of terminal pins include terminal pins extending from opposite end faces.

15. The power switch according to claim 14, wherein the terminal pins extending from opposite end faces are diagonally opposed to each other.

16. The power switch according to any one of claims 1 to 15, including a second face surface on the opposite side of the first face surface, on which a conductive thermal interface is formed.

17. The power switch according to any one of claims 1 to 16, wherein when the switch is turned on, current flows in the same direction parallel to the power phase output terminals in each half bridge.

18. The power switch according to any one of claims 1 to 17, wherein when transitioning between the on state and the off state, the total power loop inductance is less than about 2.5 nH, less than 2.25 nH, or less than about 2.0 nH.

19. A power pack array including the power switch according to any one of claims 1 to 18, which are abutted against each other.

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