Voltage trimming for qubit control

Abstract

A quantum device includes a silicon layer in which a plurality of quantum dots 201 can be induced, a first gate of a first inductive quantum dot and a second gate of a second inductive quantum dot that control an electrical potential defining the induced quantum dots 201, and a first integrated circuit element and a second integrated circuit element 204 that control voltages of the first gate and the second gate. The integrated circuit element 204 has an adjustable non-volatile resistance value. The integrated circuit element 204 has an input voltage V in and first and second output voltages V out . The output voltages depend on the input voltage, the first non-volatile resistance value, and the second non-volatile resistance value. The integrated circuit element 204 is electrically connected to the gates such that the output voltages are applied to respective gates of the inductive quantum dots 201.

Description

Technical Field

[0001] The present invention relates to a quantum device suitable for quantum computing.

Background Art

[0002] Quantum bits are generally arranged in a high-density array as part of a quantum device. In order to perform quantum computing using the quantum bits in the array, each quantum bit must be addressable.

[0003] In the case of a small-scale quantum bit array, each quantum bit can be addressed using an individual control line. However, this method requires a large number of power supplies and is difficult to apply to larger quantum bit arrays.

[0004] It is desirable to reduce the number of control lines and devices required to address the quantum bits in the array. This generally requires uniformity across the entire array.

[0005] Generally, there are multiple input elements for addressing the quantum bits in the array. For example, electron spin resonance and tunnel junctions. It is desirable for each input element to be able to globally address the quantum bits in the array. However, each input may depend on the characteristics of the quantum bits that vary at the individual quantum bit level across the entire array. Therefore, it is necessary to appropriately adjust each of the multiple input elements according to each quantum bit in the array.

[0006] For example, in the case of electron spin qubits in silicon, it is desirable to be able to use a single frequency to drive multiple qubits. However, due to variations in the g-factor of electrons throughout the device, such global control of electron spins cannot be easily achieved. Although the g-factor can be adjusted using an external electric field, the adjustable range for each qubit is typically at least one order of magnitude smaller compared to the variations in the g-factor across the entire device. Therefore, even when applying a single frequency, only about 1 to 10% of the spin qubits within the device may be addressable.

[0007] This problem can be solved by using cavity amplitude modulation. With cavity amplitude modulation, a single-frequency input can be converted into multiple frequencies that cover the range of the electron g-factor. In this way, it is possible to globally control electron spins using a single frequency.

[0008] However, in the above-described method, it is necessary to adjust the voltage reference for each individual qubit, which is inefficient and difficult to scale.

[0009] It is desirable to globally operate an array of qubits. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0010] One aspect of the present invention provides a quantum device. This quantum device includes a silicon layer in which a plurality of quantum dots can be induced, a plunger gate or a barrier gate that is the first gate of a first inductive quantum dot for controlling the electrical potential defining the first inductive quantum dot, a plunger gate or a barrier gate that is the second gate of a second inductive quantum dot for controlling the electrical potential defining the second inductive quantum dot, a first integrated circuit element for controlling the voltage of the first gate, and a second integrated circuit element for controlling the voltage of the second gate. The first integrated circuit element has an adjustable first non-volatile resistance value R FIt has. The second integrated circuit element has an adjustable second non-volatile resistance value. The first integrated circuit element has an input voltage and a first output voltage, and the first output voltage depends on the input voltage and the first non-volatile resistance value. The second integrated circuit element has an input voltage and a second output voltage, and the second output voltage depends on the input voltage and the second non-volatile resistance value. The first and second integrated circuit elements are electrically connected to the first and second gates, respectively, such that the first and second output voltages are applied to the first gate of the first inductive quantum dot and the second gate of the second inductive quantum dot, respectively.

[0011] By adjusting the resistance value, the output voltage applied to the gate of the inductive quantum dot for a fixed input voltage is adjusted. This advantageously means that the output voltage can be adapted according to the physical and electronic characteristics of each inductive quantum dot.

[0012] The resistance value is non-volatile. This means that after the resistance value is adjusted, the resistance value remains stable and fixed. Those skilled in the art will understand the term "non-volatile" in this context to mean that the resistance value of the integrated circuit element, i.e., the encoded memory state, can be maintained without power input. Therefore, the memory state can be encoded and held.

[0013] The non-volatility of the resistance value has the advantage that it can be held for a long time after the resistance value is adjusted to a predetermined value. The resistance value can be maintained at a fixed value over the lifetime of the quantum circuit, at least during the quantum computation performed using the quantum device. The resistance value may be readjusted as needed, but advantageously there is no need for readjustment if a fixed resistance value is desired. That is, there is no need to refresh the resistance value. The integrated circuit element advantageously provides an addressable non-volatile analog memory capable of supplying a constant DC voltage offset to the quantum dots within the quantum device.

[0014] The gate of an inducible quantum dot is a gate for controlling the electric potential that defines the induced quantum dot. Preferably, the inducible quantum dot within the silicon layer is a quantum dot for which a gate is defined. Generally, a quantum dot for which a gate is defined has a plurality of gates for confining quantum charge carriers within the quantum dot. Typically, one or more gates that define the quantum dot are arranged such that the quantum dot can be induced when an appropriate bias potential is applied to the gate. The gate of the inducible quantum dot is selectively a plunger gate. The plunger gate can be used to raise or lower the electrical well-type potential of the quantum dot, thereby respectively decreasing or increasing the number of charge carriers confined in the quantum dot.

[0015] Advantageously, by applying an output voltage optimized for the plunger gate of the inducible quantum dot, the induced quantum dot can be configured such that only one electron is confined in the quantum dot during the operation of the device. To achieve this, the non-volatile resistance value of the integrated circuit element is preferably greater than the voltage V required for the output voltage applied to the plunger gate to capture or confine one electron 1e and less than the voltage V required for the output voltage applied to the plunger gate to capture or confine two electrons. 2e V 1e and V 2e may vary for each quantum dot, and this variation can be significant.

[0016] Alternatively, the gate of the inducible quantum dot is a barrier gate. The barrier gate can be used to raise or lower the electrostatic barrier that defines the edge of the electrical well-type potential of the quantum dot, thereby decreasing or increasing the coupling strength between the quantum dot and the adjacent confinement region. The adjacent confinement region may be a zero-dimensional confinement region, i.e., another quantum dot, a one-dimensional confinement region, e.g., an elongated quantum dot, or a two-dimensional confinement region, i.e., a charge carrier reservoir.

[0017] Advantageously, by applying a customized output voltage to the barrier gate of an inductive quantum dot, the coupling strength can be adapted according to the performance requirements. For example, by adjusting the output voltage applied to the barrier gate to lower the height of the electrostatic barrier between two adjacent quantum dots, a two-qubit interaction can be enabled. Since the required output voltage applied to the barrier gate varies across the entire quantum device, it is beneficial to be able to adjust the voltage applied to the barrier gate as needed.

[0018] Alternatively, one inductive quantum dot may have multiple barrier gates to define multiple edges of the electrical well-type potential of the quantum dot. For example, an inductive quantum dot may be defined by one plunger gate and two barrier gates. Each of the barrier gates and the plunger gate may have a corresponding integrated circuit element for controlling the voltage of the gate. Preferably, the non-volatile resistance value of each integrated circuit element is independently adjustable. Advantageously, the adjustment of each integrated circuit element provides a mechanism for addressing variations in the characteristics of the quantum dots across the device at the individual quantum dot level.

[0019] The characteristics of the inductive quantum dots can vary significantly across the entire quantum device depending on their position within the quantum device and differences introduced during manufacturing. For example, between the silicon layer and the silicon oxide layer (Si / SiO xDue to the surface roughness of the interface in [[ID=]], the g-factor of electrons can vary even on the scale of single-atom steps. A single-atom shift at the interface (i.e., a step of a single atom) causes a sign inversion of the Dresselhaus coefficient (β), while the Rashba coefficient (α) remains unchanged. The g-factor and Stark shift of electrons at symmetric points of the same dot also differ significantly. Similarly, due to changes in the physical properties underlying the device, the first electron energy can vary across the device. Furthermore, for the same reason, the second electron energy can also vary across the device. Additionally, the tunneling coupling characteristics between adjacent confinement regions (such as quantum dots or charge storage units) within the device can change due to changes in the surface roughness or other physical properties of the device. The output voltage applied to the tunnel barrier may need to be adjusted considering the variation in tunneling coupling strength.

[0020] The quantum device is a silicon-based quantum device having a silicon layer. The silicon layer may be, for example, intrinsic silicon, isotopically pure silicon Si 28 , or doped silicon. The quantum device typically comprises an additional layer for supporting the silicon layer and providing control circuitry.

[0021] The integrated circuit element has an adjustable non-volatile resistance value. This may be achieved by adjusting the threshold voltage of the integrated circuit element. A gate voltage may be applied to the integrated circuit element. When the gate voltage is greater than the threshold voltage of the n-type integrated circuit element, the integrated circuit element is "on". When the gate voltage is lower than the threshold voltage of the n-type integrated circuit element, the integrated circuit element is "off". In the range below the threshold voltage, i.e., below the threshold, the channel resistance of the circuit element is high and typically increases exponentially with a decrease in the gate voltage. The channel resistance of this circuit element is a non-volatile resistance value.

[0022] The integrated circuit element may be n-type, p-type, or ambipolar. When the gate voltage is lower (i.e., more negative) than the threshold voltage of the p-type integrated circuit element, the integrated circuit element is "on". When the gate voltage is higher than the threshold voltage of the p-type integrated circuit element, the integrated circuit element is "off". The ambipolar integrated circuit element has two threshold voltages. When it is lower than the first threshold voltage, the integrated circuit element is "on" and the transport is p-type, i.e., the charge carriers are holes. Between the first threshold voltage and the second threshold voltage, the integrated circuit is "off". When it is higher than the second threshold voltage, the integrated circuit element is "off" and the transport is n-type, i.e., the charge carriers are electrons.

[0023] The integrated circuit element is electrically connected to the gate such that the output voltage is applied to the gate of the induced quantum dot. When the quantum dot is induced in the silicon layer, the integrated circuit element is electrically connected to the induced quantum dot.

[0024] The output voltage controls the voltage of the gate that controls the electrical potential defining the quantum dot. In the example where the gate is a plunger gate, the output voltage is typically adjusted such that the quantum dot contains one electron (i.e., the dot is filled) or does not contain an electron (i.e., the dot is empty). This is usually achieved by adjusting the input voltage.

[0025] The quantum device is preferably manufactured using complementary metal oxide semiconductor (CMOS) manufacturing technology. This advantageously facilitates the manufacture of the device.

[0026] Optionally, the integrated circuit element includes a field effect transistor (FET). The FET typically includes three terminals: a gate, a source, and a drain. Optionally, the input voltage and the output voltage correspond to the source terminal and the drain terminal. Current flows between the source and the drain and is characterized by a channel resistance. The channel resistance is determined by the applied gate voltage (i.e., the gate voltage applied to the integrated circuit element) and the threshold voltage, and the channel resistance is non-volatile and adjustable. Various types of FETs may be suitable for use as integrated circuit elements. Preferably, the integrated circuit element is non-volatile and has long-term charge stability.

[0027] Preferably, the integrated circuit element includes a source-drain channel and an electrically isolated element capacitively coupled to the gate. The electrically isolated element can advantageously be charged and discharged to encode different non-volatile memory states. The encoded memory states advantageously do not require refreshing to be maintained.

[0028] For example, the first and / or second integrated circuit element may comprise a floating gate metal oxide semiconductor field effect transistor (FGMOS). The integrated circuit element may be an FGMOS. The FGMOS typically includes a control gate and a floating gate (also referred to as a floating island). The floating gate typically provides an electrically isolated element of the integrated circuit element. Advantageously, FGMOS devices are known to exhibit hysteresis characteristics that result in an adjustable and non-volatile resistance value.

[0029] Typically, to adjust the resistance value, an electrically insulated element can be charged or discharged. The charging and discharging of the electrically insulated, or "floating," element preferably adjusts the threshold voltage such that the resistance value is adjusted with respect to the fixed gate voltage applied to the integrated circuit element. The programmed charge state of the electrically insulated element is typically non-volatile and stable. This property allows the adjustable resistance value to be adjusted to a predetermined resistance value and maintained at that predetermined resistance value over time, thereby ensuring stable and reliable operation of the quantum device.

[0030] Alternatively, the first and / or second integrated circuit element may comprise a gate-defined multiple quantum dot device. Advantageously, these devices are also known to exhibit hysteresis characteristics. The resistance value of the multiple quantum dot device may be adjusted to a predetermined resistance value and maintained at that predetermined resistance value over a long period of time. The hysteresis characteristic is related to the ability to shift the threshold voltage to a more positive or more negative value to adjust the channel resistance value of the integrated circuit element. Optionally, the gate-defined multiple quantum dot device may comprise a silicon nanowire. Typically, the gate-defined multiple quantum dot device comprises a plurality of gates.

[0031] The quantum device is preferably arranged such that the inductive quantum dot has a fixed resistance (for a fixed temperature) and the integrated circuit element has an adjustable resistance. The inductive quantum dot and the integrated circuit element are preferably arranged such that the voltage applied to the inductive quantum dot is less than the voltage applied to the integrated circuit element. The reduction level may be controllable by adjusting the adjustable resistance value of the integrated circuit element to control the output voltage.

[0032] Preferably, the first inductive quantum dot has a first resistance value R D The resistance value R D of the inductive quantum dot typically depends on the temperature of the quantum device. As the temperature decreases, the first resistance value R Dmay increase. Since quantum computing is typically performed at extremely low temperatures, the first resistance value is usually large. For example, at 4 Kelvin, the first resistance value may be about 1×10 6 ~1×10 9 ohms. Advantageously, since the resistance value is non-volatile even at low temperatures, a predetermined resistance value can be maintained at the operating temperature of the device.

[0033] The non-volatile resistance value, i.e., the channel resistance R of the integrated circuit element F typically depends on the threshold voltage. In the case of a fixed input voltage and an n-type integrated circuit element, the non-volatile resistance value R F increases as the threshold voltage increases. The integrated circuit element preferably operates in a range below a low threshold. This means that during the operation of the quantum device, the gate voltage is preferably less than the threshold voltage. In the range below the threshold, the channel resistance of the integrated circuit element typically increases exponentially with a decrease in the gate voltage.

[0034] The integrated circuit element and the inductive quantum dot are preferably arranged such that the input voltage is divided among the components. This arrangement may be referred to as a resistive voltage divider, a voltage divider, or a potential divider. In this arrangement, the first output voltage V out is preferably proportional to the input voltage V D with a proportionality constant equal to R F / (R D +R in ).

[0035] Advantageously, when the integrated circuit element operates in a range below a low threshold, the non-volatile resistance R F is large and can be adjusted to be comparable to the large fixed resistance R D of the quantum dot. This allows the possible output voltage V outThis means that the range can be selected. Usually, "empty" means that there are no electrons in the quantum dot, and "filled" means that there is one electron in the quantum dot. Usually, it is possible to confine more than one electron in a quantum dot, but this is usually avoided when using the quantum dot as a qubit of a quantum device.

[0036] The quantum device may optionally further include an adjustment field effect transistor (FET). Here, the adjustment FET is electrically connected to the first or second integrated circuit element. The adjustment FET may be configured to enable or disable an adjustment voltage for the first or second integrated circuit element, respectively.

[0037] Advantageously, the adjustment FET can be used to enable or disable the adjustment voltage by charging and discharging the integrated circuit element. Specifically, the adjustment FET may be used to charge and discharge the floating element of the integrated circuit element. Usually, the output of the adjustment FET is connected to the gate of the integrated circuit element. For example, the adjustment FET may include a source, a drain, and a gate terminal, and the drain terminal of the adjustment FET may be connected to the control gate of the FGMOS. The adjustment FET preferably acts as a switch. When the adjustment FET is "off", the voltage applied to the source terminal of the adjustment FET is not transmitted, and the adjustment voltage or adjustment signal is disabled. When the adjustment FET is "on", the voltage applied to the source terminal can be transmitted to the drain terminal so that a current can flow between the source and drain terminals of the adjustment FET, and the drain terminal may be connected to the integrated circuit element. Therefore, when the adjustment FET is "on", the adjustment voltage or adjustment signal is enabled.

[0038] The adjustment FET may be used to adjust the non-volatile resistance value of the integrated circuit element in order to control the occupancy of the quantum dot by adjusting the voltage applied to the quantum dot gate. The first and second quantum dots of the quantum device can be induced in the silicon layer, and the first and / or second induced quantum dots are preferably suitable for use as qubits. The quantum dot is preferably a quantum dot with a defined gate, and the voltage of the gate of the induced quantum dot can be adjusted to add electrons to or remove electrons from the quantum dot. When electrons are confined in the quantum dot, the quantum dot may be suitable for use as a qubit. For example, the qubit may be an electron spin qubit. In this example, the two measurable states of the qubit are spin-up and spin-down. Therefore, the induced quantum dot may advantageously provide a carrier of quantum information in the quantum device.

[0039] To address and manipulate qubits for performing quantum operations, the quantum device may optionally include a qubit pulse control circuit configured to selectively adjust the state of the first and / or second qubit. The qubit pulse control circuit is preferably electrically connected between the first and / or second integrated circuit element and the first and / or second induced quantum dots, respectively. Preferably, the qubit pulse control circuit is electrically connected between the integrated circuit element and the gate of the inductive quantum dot. Incorporating the qubit pulse control circuit advantageously provides a mechanism for controlling the state of the qubit as part of quantum computing. The qubit pulse control circuit may be coupled, for example, using a bias tee configuration. For example, the qubit pulse control circuit may be electrically connected using a capacitor to provide AC coupling. The qubit pulse control circuit may include, for example, an arbitrary waveform generator (AWG). The AWG may be used to provide signals to the quantum device to control the state of one or more qubits.

[0040] Furthermore, to read out the state of the quantum bits, the quantum device may optionally include a quantum bit readout control circuit configured to selectively read out the state of the first and / or second quantum bits. The quantum bit readout control circuit is preferably connected between the first and / or second integrated circuit elements and the first and / or second inductive quantum dots, respectively. Preferably, the quantum bit readout control circuit is electrically connected between the integrated circuit element and the gate of the inductive quantum dot. Incorporating the quantum bit readout control circuit advantageously enables reading or inferring the state of the quantum bits as part of quantum computing. For example, after performing one or more quantum operations on the quantum bits, the state of the quantum bits can be read out. The quantum bit readout control circuit may include, for example, an inductor and a capacitor. The quantum bit readout control circuit may include an LC resonance circuit, also known as a tank circuit, an LC resonator, or a resonance circuit.

[0041] Multiple qubits are involved in quantum computing. Accordingly, the quantum device includes a plurality of quantum dots for use as qubits.

[0042] The first output voltage is applied to the first gate of the first inductive quantum dot. The second output voltage is applied to the second gate of the second inductive quantum dot. Alternatively, the first and second gates may both be used to control the electrical potential defining the same inductive quantum dot. For example, the first gate may be the plunger gate of the first inductive quantum dot, and the second gate may be the barrier gate of the first inductive quantum dot. In this alternative example, the first output voltage is applied to the plunger gate of the first inductive quantum dot, and the second output voltage is applied to the barrier gate of the first inductive quantum dot.

[0043] This advantageously enables global control of the quantum dots. Using the same input voltage, two output voltages can be applied. The first and second output voltages may be different. The first and second non-volatile resistance values can be adjusted to control the voltages of the first and second gates of the first and second inductive quantum dots respectively according to the respective characteristics of the first and second inductive quantum dots. Advantageously, this provides the ability to adapt the first and second output voltages according to the respective characteristics of the first and second inductive quantum dots. If the first and second inductive quantum dots have similar characteristics, the first and second output voltages may be similar.

[0044] More generally, any number of quantum dots can be induced within the silicon layer according to actual manufacturing constraints. For example, the device may be configured to be able to induce about 10 9 quantum dots within the silicon layer. For each gate of the inductive quantum dots, the quantum device preferably comprises a corresponding integrated circuit element for applying a voltage to the gate of the inductive quantum dot. Usually, there are multiple inductive quantum dots and multiple gates are used to define each quantum dot. Each integrated circuit element usually has an adjustable non-volatile resistance value. Each integrated circuit element preferably has the same input voltage. The output voltage of each integrated circuit element usually depends on the input voltage and the non-volatile resistance value of that integrated circuit element. Each integrated circuit element is preferably arranged such that the output voltage is applied to the corresponding gate of the inductive quantum dot. Advantageously, if the quantum device comprises an integrated circuit element for each gate of the inductive quantum dots, the voltages of each gate can be adjusted individually using a single input voltage.

[0045] In another example, the quantum device may have a unit cell structure. Here, each unit cell typically comprises two or more quantum dots, and the unit cells are repeated in a one-dimensional or two-dimensional array. The quantum device may optionally have two or more input voltages corresponding to each quantum dot within the unit cell. This configuration advantageously provides a mechanism for performing complex operations between multiple qubits while reducing the necessary control circuitry.

[0046] In another example, each quantum dot within the array may be defined by a plunger gate and two barrier gates. A first input voltage may be used to address the plunger gate of each quantum dot within the array. Second and third input voltages may be used to address the first and second barrier gates of each quantum dot within the array, respectively. Each gate preferably has a corresponding integrated circuit element for regulating the output voltage applied to the gate.

[0047] If the quantum device includes multiple gates and / or multiple addressable quantum dots, the quantum device may further comprise a crossbar array configured to be selectively electrically connected to the first and / or second integrated circuit elements. The selective electrical connection advantageously allows for individual tuning of the first and / or second integrated circuit elements to account for different characteristics.

[0048] Another aspect of the present invention provides a method of using a quantum device. The quantum device includes a silicon layer in which a plurality of quantum dots are addressable, a plunger gate or a barrier gate that controls the electrical potential defining a first addressable quantum dot, a first gate of the first addressable quantum dot, a plunger gate or a barrier gate that controls the electrical potential defining a second addressable quantum dot, a second gate of the second addressable quantum dot, and an adjustable first non-volatile resistance value R FIt has a first integrated circuit element that controls the voltage of a first gate, a second integrated circuit element that has an adjustable second non-volatile resistance value and controls the voltage of a second gate, and a crossbar array for selecting one or more integrated circuit elements. The method includes steps of inducing first and second quantum dots, selecting the first integrated circuit element, adjusting the first non-volatile resistance value of the first integrated circuit element to a first set non-volatile resistance value, selecting the second integrated circuit element, adjusting the second non-volatile resistance value of the second integrated circuit element to a second set non-volatile resistance value, applying an input voltage to the first and second integrated circuit elements, wherein the first output voltage of the first integrated circuit element and the second output voltage of the second integrated circuit element respectively depend on the input voltage and the first and second set non-volatile resistance values, applying the first output voltage of the first integrated circuit element to the first gate of the first induced quantum dot, and applying the second output voltage of the second integrated circuit element to the second gate of the second induced quantum dot.

[0049] Adjusting the resistance value of the integrated circuit element adjusts the respective output voltage. The advantage of this method is that by controlling the set non-volatile resistance value, the voltage applied to the gate of the induced quantum dot can be controlled according to the specific characteristics of the quantum dot.

[0050] The set point of the non-volatile resistance value may be selected to target the qubit resonance line. Although it is desirable to globally apply a drive frequency to the qubits, qubit resonance typically varies according to the electron g-factor, which varies significantly across the device. Advantageously, this method can be used to provide a voltage tailored to each quantum dot within the quantum device to control the occupancy of the quantum dots.

[0051] The set point of the non-volatile resistance value may be selected based on alternative requirements such as the target tunnel coupling strength. For example, for a specific electrical well-type potential, the barrier height required to provide a specific tunnel coupling strength may vary depending on the characteristics of the device in the region where the electrical well-type potential is formed. Therefore, different output voltages are required throughout the quantum device.

[0052] Generally, the non-volatile resistance value may be selected to generate different output voltages from the same input voltage for any selected output requirement. The output voltages usually need to be different due to variations in the electronic and / or physical characteristics throughout the quantum device. Generally, the quantum device may have multiple input voltages corresponding to different functions.

[0053] Optionally, when the quantum device further includes an adjustment field-effect transistor (FET) having a source, a drain, and a gate terminal, the step of adjusting the first or second non-volatile resistance value of the first or second integrated circuit element to the first or second set non-volatile resistance value respectively may include enabling the adjustment FET by applying a voltage to the gate terminal of the adjustment FET to allow current to flow between the source and drain terminals of the adjustment FET, and applying an adjustment voltage to the adjustment FET. The adjustment FET is preferably configured to enable or disable the adjustment voltage for the integrated circuit element. The adjustment FET is preferably electrically connected to the first or second integrated circuit element such that applying the adjustment voltage to the enabled adjustment FET adjusts the non-volatile resistance value of each of the first or second integrated circuit elements. Preferably, applying the adjustment voltage to the enabled adjustment FET adjusts the channel resistance of the integrated circuit element, and applying the adjustment voltage to the disabled adjustment FET does not adjust the channel resistance of the integrated circuit element. The first and second set non-volatile resistance values usually depend on the adjustment voltage.

[0054] The adjustment FET has a source, a drain, and a gate terminal. The adjustment FET may be n-type, p-type, or ambipolar. Enabling an n-type adjustment FET typically involves applying a voltage greater than the threshold voltage of the adjustment FET to the gate terminal. This causes the adjustment FET to turn "on". In this state, the channel resistance of the adjustment FET is low, and a conductive path exists between the source and drain terminals. When the adjustment FET is enabled, the adjustment voltage applied to the source terminal of the adjustment FET may be passed to the integrated circuit element. Preferably, the drain terminal of the adjustment FET is electrically connected to the gate terminal of the integrated circuit element. This may be, for example, a control gate or a top gate.

[0055] The enabled adjustment FET can advantageously be used to adjust the resistance value by charging and discharging the integrated circuit element. The enabled adjustment FET may be used to charge and discharge an electrically isolated element of the integrated circuit element. For example, if the integrated circuit element is an FGMOS device, charge may be accumulated on the floating gate, and the charge level affects the threshold voltage, which in turn affects the channel resistance of the device. The channel resistance is typically a non-volatile resistance value. The floating gate that holds the accumulated charge is capacitively coupled to the position of the quantum dot. As a result, based on the charge Q held by the floating gate and the capacitive coupling C, a voltage potential V FG = Q / C is used to add a direct voltage potential V FG to the quantum dot.

[0056] Optionally, the quantum device may be configured such that a plurality of inductive quantum dots are present within the silicon layer. For example, the gate may be a first gate of a first inductive quantum dot that controls the electrical potential defining the first inductive quantum dot, and the integrated circuit element may be a first integrated circuit element having an adjustable first non-volatile resistance value and controlling the voltage of the first gate. Optionally, a second quantum dot can be induced into the silicon layer, and the quantum device further comprises a second gate of a second inductive quantum dot that controls the electrical potential defining the second inductive quantum dot, and a second integrated circuit element that controls the voltage of the second gate. The second integrated circuit element preferably has an adjustable second non-volatile resistance value. The quantum device may also comprise a crossbar array for selecting one or more integrated circuit elements.

[0057] For a quantum device comprising first and second inductive quantum dots, the method typically comprises the step of selecting a first integrated circuit element, the step of adjusting the first non-volatile resistance value of the first integrated circuit element to a first set non-volatile resistance value, the step of selecting a second integrated circuit element, the step of adjusting the second non-volatile resistance value of the second integrated circuit element to a second set non-volatile resistance value, and the step of applying an input voltage to the first and second integrated circuit elements, wherein the first output voltage of the first integrated circuit element and the second output voltage of the second integrated circuit element depend on the input voltage and the first and second set non-volatile resistance values respectively, the step of applying the first output voltage of the first integrated circuit element to the first gate of the first inductive quantum dot, and the step of applying the second output voltage of the second integrated circuit element to the second gate of the second inductive quantum dot.

[0058] This method advantageously enables global control of the induced quantum dots. Using the same input voltage, two different output voltages can be applied. Advantageously, different g-factors, electron energies, and tunnel coupling strengths can be addressed with different output voltages using the same input voltage. Typically, different functions are addressed using different input voltages. For example, one input voltage may be used to apply multiple output voltages to address different tunnel coupling strengths, and another input voltage may be used to apply multiple output voltages to address different first electron energies. The first and second non-volatile resistance values can be adjusted to the first and second set non-volatile resistance values to control the voltages of the first and second gates of the respective induced quantum dots. Thus, the gates of the quantum dots can be individually addressed using a single input voltage.

[0059] Generally, a quantum device may comprise n inductive quantum dots, m gates per quantum dot, and m×n integrated circuit elements, with each gate of the quantum dots being electrically connected to a respective integrated circuit element. In another example, the number of gates per inductive quantum dot may vary across the quantum device. For example, a barrier gate may provide a barrier between two adjacent quantum dots. Generally, the method may comprise sequentially selecting each integrated circuit element and adjusting its non-volatile resistance value to its set value. Thereafter, the method may generally comprise applying an input voltage to the m×n integrated circuit elements. The output voltage applied to the gates of the quantum dots depends on the input voltage and the set non-volatile resistance value. This method advantageously provides global control of an array of quantum dots. Multiple output voltages can be applied to quantum dots with different characteristics using one input voltage. This advantageously reduces the complexity of the method and the required control circuitry.

[0060] Optionally, there may be m input voltages. Generally, each input voltage may be applied to n integrated circuit elements, and each of the n integrated circuit elements corresponds to an inductive quantum dot, and each of the m input voltages corresponds to a gate with a different function.

[0061] One aspect of the present invention provides a quantum device. This quantum device includes a silicon layer in which quantum dots are inductive, a gate of the inductive quantum dot that controls the electrical potential defining the inductive quantum dot, and an integrated circuit element that controls the voltage of the gate. The integrated circuit element has an adjustable non-volatile resistance value R F and has an input voltage and an output voltage, and the output voltage depends on the input voltage and the non-volatile resistance value. The integrated circuit element is electrically connected to the silicon layer such that the output voltage is applied to the gate of the inductive quantum dot.

[0062] Another aspect of the present invention provides a method of using a quantum device. This quantum device includes a silicon layer in which quantum dots are inductive, a gate of the inductive quantum dot that controls the electrical potential defining the inductive quantum dot, and an integrated circuit element that has an adjustable non-volatile resistance value and controls the voltage of the gate. The method includes the steps of adjusting the non-volatile resistance value of the integrated circuit element to a set non-volatile resistance value, applying an input voltage to the integrated circuit element, where the output voltage of the integrated circuit element depends on the input voltage and the set non-volatile resistance value, and applying the output voltage of the integrated circuit element to the gate of the inductive quantum dot.

Brief Description of the Drawings

[0063] Embodiments of the present invention will be described below with reference to the accompanying drawings.

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Figure 6

DETAILED DESCRIPTION OF THE INVENTION

[0064] Figure 1 is a circuit diagram of a quantum device according to the prior art. This device is described in "Silicon CMOS architecture for a spin-based quantum computer" by Veldhorst et al, DOI: 10.1038 / s41467-017-01905-6 (2017). Figure 1 shows four quantum dots QD1, QD2, QD3, QD4. Each quantum dot QD1, QD2, QD3, QD4 is a single quantum dot, and the resistance R D and capacitor C D are schematically shown. The resistance and capacitance of each quantum dot usually vary. The quantum dots QD1 to QD4 can be addressed using word lines and bit lines 101 to 105 connected to the quantum dots QD1 to QD4 via transistors 106 to 109. Each transistor 106 to 109 has a source terminal, a drain terminal, and a gate terminal.

[0065] Figure 1 shows a word line 101 electrically connected to the source terminals of four transistors 106, 107, 108, 109. Each bit line 102, 103, 104, 105 is electrically connected to the gate terminals of transistors 106, 107, 108, 109. Each quantum dot QD1, QD2, QD3, QD4 is electrically connected to the drain terminals of transistors 106, 107, 108, 109. For example, the gate terminal of the first transistor 106 is electrically connected to the first bit line 102, the source terminal of the first transistor 106 is electrically connected to the word line 101, and the drain terminal of the first transistor 106 is electrically connected to the first quantum dot QD1.

[0066] Bit lines 102 to 105 can be used to address each of the quantum dots QD1 to QD4. This can be achieved by applying bias potentials V B1 、V B2 、V B3 、V B4 to the relevant bit lines. When an appropriate bias potential is applied to the bit line, the electrically connected transistor is turned on. When the transistor is on, the channel resistance, that is, the resistance between the source and drain terminals of the transistor, is low. When the transistor is off, the channel resistance is high.

[0067] For example, to address the second quantum dot QD2, the bias potential V B2 can be applied to the second bit line 103. When a sufficiently large bias potential V B2 is applied to the second bit line 103, the second transistor 107 is turned on. When the second transistor 107 is on, since the channel resistance is low, current can flow between the word line 101 and the second quantum dot QD2. The current depends on the bias potential V W applied to the word line 101. A larger applied bias potential V W increases the current.

[0068] The quantum device shown in FIG. 1 includes charge storage electrodes 111, 112, 113, 114, or floating memory gate electrodes. When transistors 106 to 109 are on, the bias potential V W applied to the word line 101 can be controlled to charge or discharge the electrically connected charge storage electrodes 111 to 114. Charging or discharging the charge storage electrodes 111 to 114 can be used to adjust the electrical characteristics of the electrically connected quantum dots QD1 to QD4.

[0069] The charge storage electrodes 111 to 114 are adjusted so that the voltages applied to the quantum dots QD1 to QD4 are within an allowable range for quantum bit control. However, the voltages on the charge storage electrodes 111 to 114 decay according to the voltage decay time constant τ = RC. Here, R is the total resistance including the resistance R D of the quantum dot, and C is the total capacitance including the capacitance C D of the quantum dot and other parasitic capacitances within the quantum device. The total capacitance C usually includes the input capacitances on the source sides of the transistors 106 to 109. Due to the decay of the voltages on the charge storage electrodes 111 to 114, it is necessary to periodically refresh the applied voltages to keep the voltages within the allowable range. The decay may be due to leakage to neighboring structures or changes in capacitive coupling. This system is similar to a dynamic random access memory (DRAM) system.

[0070] To recondition the memory after decay, it is necessary to reactivate the transistors 106 to 109 using the bit lines and the word lines 101 to 105 to refresh the charge levels on the charge storage electrodes 111 to 114. The quantum device shown in FIG. 1 can be used to individually condition the quantum bits within a quantum bit array. However, this solution has several drawbacks. For example, the periodic refresh of the volatile memory elements (charge storage electrodes 111 to 114) requires an extensive control circuit to be periodically enabled during the operation of the device. This results in relatively high power consumption. Furthermore, it is difficult to initially write individual adjustment points to the charge storage electrodes 111 to 114 and to maintain them without damage when applying the desired control signals.

[0071] FIG. 2 is a circuit diagram of a part of a quantum device according to an embodiment of the present invention. The circuit includes a quantum dot 201 which is a single quantum dot. The quantum dot 201 is biased with a bias potential V outBy applying [voltage], it can be induced in a silicon layer (not shown). The induced quantum dot 201 is suitable for use as a qubit in a quantum device when the quantum dot 201 is occupied by a single electron. A voltage is applied to the plunger gate of the quantum dot to raise or lower the electrical well-type potential of the quantum dot, thereby decreasing or increasing the number of confined electrons respectively. The plunger gate voltage required to occupy the quantum dot 201 with a single electron depends on the characteristics of the quantum dot 201.

[0072] The quantum dot 201 is schematically shown as having a resistor 202 and a capacitor 203 arranged in parallel. The quantum dot 201 is electrically grounded. The resistor 202 has a resistance R D and the capacitor 203 has a capacitance C D The resistance R D and the capacitance C D depend on the characteristics of the quantum dot 201. Therefore, in a typical device including an array of quantum dots for use as qubits, the resistance and capacitance of each quantum dot vary across the entire array.

[0073] The circuit shown in FIG. 2 also includes an integrated circuit element 204. The integrated circuit element 204 has a source terminal, a drain terminal, and a gate terminal. In this example, the integrated circuit element 204 has two gate terminals, a control gate terminal and a floating gate terminal. The control gate is electrically connected to a voltage source (not shown). The floating gate is an electrically insulated element capacitively coupled close to the control gate and the source and drain terminals.

[0074] The integrated circuit element 204 can be used to encode a memory state in an almost analog manner with an adjustable non-volatile resistance value R FIt has a non-volatile resistance value that can be adjusted and maintained over a long period during the operation of the quantum device. Quantum devices typically operate at extremely low temperatures. The integrated circuit element 204 provides an element such as a FLASH memory that is stable for a long time at the operating temperature of the device. As a result, once the memory state is encoded, decay can be ignored, eliminating the need to refresh the memory state. The set memory state does not change significantly over time.

[0075] The non-volatile resistance value R F is the channel resistance of the integrated circuit element 204. The channel resistance R F depends on physical characteristics such as the dimensions and threshold voltage of the integrated circuit element 204. An input voltage V in can be applied to the source terminal of the integrated circuit element 204. The output voltage V out of the integrated circuit element 204 depends on the adjustable channel resistance R F , that is, the resistance between the source and drain terminals, and the resistance R D of the quantum dot 201.

[0076] In this example, the integrated circuit element 204 is an n-type field-effect transistor. The integrated circuit element 204 has a threshold voltage V th . When a bias potential below the threshold voltage is applied to the control gate, the integrated circuit element 204 is "off" and the channel resistance R F is very large. In the region below the threshold, the channel resistance R F continues to increase exponentially as the gate voltage decreases. When a bias potential above the threshold voltage is applied to the control gate, the integrated circuit element 204 is "on" and the channel resistance R F is very small. During the normal operation of the quantum device, that is, while quantum operations are being performed, the integrated circuit element is in the region below the threshold.

[0077] The non-volatile resistance value R Fcan be adjusted by regulating the charge of an electrically isolated element. The electrically isolated element can be charged and discharged by adjusting the bias potential applied to the control gate. For a specific control gate voltage applied to the integrated circuit element 204, in the case of an n-type integrated circuit element, a larger channel resistance R F corresponds to a positive threshold voltage V th . Therefore, the channel resistance R F can be adjusted by the shift of the threshold voltage achieved by changing the charge level of the electrically isolated element.

[0078] Therefore, the circuit shown in FIG. 2 provides a voltage divider. The input voltage V in is reduced according to the relative values of the resistance R D of the quantum dot 201 and the channel resistance R F of the integrated circuit element 204. The output voltage V out of the integrated circuit element 204 depends on the input voltage V in and the nonvolatile resistance value R F . The output voltage V out is applied to the gate of the inductive quantum dot 201 and can be calculated according to the following formula.

Equation

[0079] The resistance element R D of the quantum dot 201 is usually due to the cumulative leakage to the electrical ground existing in the complementary metal oxide semiconductor (CMOS) manufacturing technology. The resistance R D is temperature-dependent, and at extremely low temperatures, R D is usually very large. The channel resistance R F is preferably large to provide a range from a single input voltage V in to the output voltage V out . Therefore, the integrated circuit element 204 usually operates in a region below a low threshold.

[0080] In the example shown in FIG. 2, the gate of the quantum dot 201 is electrically connected to the drain terminal of the integrated circuit element 204. In another example, the gate of the quantum dot may be electrically connected to an electrically insulated element, and the drain terminal may be electrically grounded.

[0081] FIG. 3 is a circuit diagram of a part of a quantum device according to an embodiment of the present invention. The circuit includes four quantum dots 301, 302, 303, 304, each having a resistor with resistance R when n = 1, 2, 3, 4 n and a capacitor with capacitance C n are schematically shown as being arranged in parallel. The resistances R n and capacitances C n of each of the quantum dots 301 to 304 vary between the quantum dots due to manufacturing tolerances and potential material properties. Each of the quantum dots 301 to 304 is electrically grounded and can be induced in the silicon layer of the quantum device by applying an appropriate voltage to the gate used to define the quantum dot.

[0082] The quantum device shown in FIG. 3 includes an array of inductive quantum dots including a first quantum dot 301, a second quantum dot 302, a third quantum dot 303, and a fourth quantum dot 304. Each of the quantum dots 301 to 304 can be used as a qubit in the quantum device when occupied by a single electron. By controlling the voltage V supplied to the plunger gate of the quantum dot such that V 1e ≦ V < V 2e the occupancy is controlled, where V 1e is the minimum voltage required to occupy the quantum dot with one electron and V 2e is the minimum voltage required to occupy the quantum dot with two electrons.

[0083] In this example, the array is a one-dimensional array. However, in another example, the array is a two-dimensional array. A crossbar array including bit lines and word lines can be used to address individual quantum dots within the array. Optionally, two or more quantum dots can be grouped so that the bit lines and word lines can address multiple quantum dots simultaneously. This helps to reduce the necessary circuitry. FIG. 3 shows bit line 305 and word line 306. In this example, each of the first, second, third, and fourth quantum dots 301-304 is connected to the same bit line 305 and word line 306. In another example, each quantum dot may be connected to a separate bit line. The quantum dots may still be connected to the same word line.

[0084] The circuit shown in FIG. 3 includes first, second, third, and fourth integrated circuit elements 307, 308, 309, 310. In this example, each of the integrated circuit elements 307-310 comprises a floating gate metal oxide semiconductor field effect transistor (FGMOS). Each of the integrated circuit elements 307-310 includes a source, a drain, a control gate, and a floating gate. In this example, the drain terminals of each of the integrated circuit elements 307-310 are electrically connected to the respective quantum dots 301-304. Specifically, the drain terminals of each of the integrated circuit elements 307-310 are electrically connected to the gates of the respective quantum dots 301-304. Each of the first to fourth integrated circuit elements 307-310 is electrically connected to a silicon layer (not shown) of the quantum device such that first, second, third, and fourth output voltages V QD1 、V QD2 、V QD3 、V QD4 are applied to the gates of the first, second, third, and fourth induced quantum dots 301-304, respectively.

[0085] The source terminals of each of the integrated circuit elements 307-310 are electrically connected to a voltage source. In this example, since each of the integrated circuit elements 307-310 is connected to the same voltage source, the input voltage of each of the integrated circuit elements 307-310 is the same V setThat is. In another example, one or more additional voltage sources may be present, and the circuit may be configured such that each voltage source is electrically connected to one or more integrated circuit elements. Since the resistance value of each integrated circuit element is adjustable, the voltage of each gate of the inductive quantum dots can be controlled to result in different output voltages for the same input voltage V set with respect to. Adjusting the threshold voltage of any of the first to fourth integrated circuit elements 307 to 310 can be used to adjust the channel resistance R Fn (n = 1, 2, 3, 4).

[0086] The output voltage V applied to each quantum dot 301 to 304 QDn can be determined as follows. Here, n = 1, 2, 3, 4.

Equation

[0087] For example, the input voltage V set is divided according to the resistance R1 of the first quantum dot 301 and the channel resistance R F1 of the first integrated circuit element 307. Therefore, the output voltage V QD1 applied to the gate of the first quantum dot 301 is reduced according to the adjustable and non-volatile channel resistance R F1 of the first integrated circuit element 307. The channel resistance R F1 also depends on the adjustable threshold voltage V th .

[0088] In FIG. 3, the voltage source inputs the input voltage V to the source terminals of each integrated circuit element 307 to 310 setconfigured to supply. In this way, all four quantum dots 301 to 304 can be addressed using a single voltage source. This reduces the number of voltage sources and related control circuits required to address an array of qubits. Further, using one voltage source to address multiple qubits reduces the number of operations required to perform a quantum computing process and enables global operation of the qubits simultaneously across the entire quantum device, thereby speeding up the calculation. In a further example, the quantum device may have any number of quantum dots, typically arranged in a one- or two-dimensional array.

[0089] The circuit shown in FIG. 3 further includes four field effect transistors 311, 312, 313, 314. Each field effect transistor 311 to 314 includes a source, a drain, and a gate. The control gates of each integrated circuit element 307 to 310 are electrically connected to the drain terminals of the respective field effect transistors 311 to 314. The source terminals of each field effect transistor 311 to 314 are electrically connected to the word line 306. The gate terminals of each field effect transistor 311 to 314 are electrically connected to the bit line 305. In this example, each field effect transistor 311 to 314 is connected to the same word line 306 and bit line 305. In another example, each field effect transistor may be connected to different word lines and bit lines, or to the same word line and different bit lines, or to different word lines and the same bit line. The word lines and bit lines form a crossbar array across the array of qubits in the quantum device and can be used to selectively address specific qubits within the qubit array.

[0090] Each field effect transistor 311 to 314 applies an appropriate bias potential V to the bit line 305 FBIt can be turned "on" by applying. In the case of a p-type field-effect transistor, when the gate voltage (i.e., the bias potential applied to the bit line 305) is lower (i.e., more negative) than the threshold voltage, the field-effect transistor is "on" and the channel resistance is low. When the gate voltage is higher than the threshold voltage, the field-effect transistor is "off" and the channel resistance is high. When a bias potential is applied to the bit line 305 to turn on each of the field-effect transistors 311 to 314, due to the low channel resistance, current flows from the source to the drain terminals of each of the field-effect transistors 311 to 314. The bias potential V FW applied to the word line 306 can be adjusted to control the current. The current typically increases with an increase in the bias potential applied to the word line 306, and the current may be proportional to the bias potential.

[0091] Therefore, the field-effect transistors 311 to 314 can be used to adjust the resistance values of the respective integrated circuit elements 307 to 310. When a field-effect transistor is enabled using a bit line to which it is electrically connected, the electrically isolated gate of the integrated circuit element electrically connected to that field-effect transistor can be charged or discharged. The charging and discharging of the electrically isolated gate can be controlled by adjusting the bias potential applied to the word line electrically connected to the field-effect transistor. The individual integrated circuit elements 307 to 310, or a group of two or more integrated circuit elements 307 to 310, can be addressed using a crossbar array including the bit line 305 and the word line 306.

[0092] As described with respect to FIG. 2, the circuit provides a resistive voltage division to reduce the input voltage V set . For each of the quantum dots 301 to 304, the voltage division depends on the channel resistance of the respective connected integrated circuit elements 307 to 310, which depends on the adjusted resistance values. The resistance values of the respective integrated circuit elements 307 to 310 can be adjusted using the respective connected field-effect transistors 311 to 314.

[0093] Each of the integrated circuit elements 307 - 310 provides an addressable analog memory integrated within the quantum device and can supply a fixed DC voltage offset adjusted to maintain the voltage within an acceptable range for qubit control to each of the quantum dots 301 - 304. Specifically, for the plunger gate of the induced quantum dot, the acceptable range for qubit control is the voltage V corresponding to the quantum dot containing a single electron, i.e., V 1e ≦ V < V 2e where V 1e is the minimum voltage required for a single electron to occupy the quantum dot, and V 2e is the minimum voltage required for two electrons to occupy the quantum dot. Each of the integrated circuit elements 307 - 310 is used to control the voltage of the respective plunger gate of the induced quantum dots 301 - 304. Supplying a fixed DC voltage offset adjusted to each of the quantum dots 301 - 304 can be combined with the AC coupling of the control signal, as shown in FIGS. 4 and 5.

[0094] The input voltage V set can be selected such that the output voltage V QDn is adjustable within the acceptable range, i.e., V 1e ≦ V QDn < V 2e . The exact values of V 1e and V 2e for each quantum dot vary, but the nominal values of these voltages can be used to determine the appropriate input voltage V set . Typically, V 1e ≈ 0.4V and V 2e < 2V 1e . V QDn need not exceed V 2e . To occupy the quantum dot with a single quantum dot, the output voltage should be adjusted such that V 1e ≦ V QDn < V 2e . To empty the quantum dot, V QDn should be adjusted such that V < V 1e .

[0095] In one example, V set may be approximately equal to the nominal value of V 2e . In this example, the channel resistance R F1 of the first integrated circuit element 307 is much smaller than the resistance of the first quantum dot 301, that is, R F1 << R1. When this is the case, the output voltage V QD1 applied to the first quantum dot 301 is approximately equal to V 2e . When the channel resistance R F1 of the first integrated circuit element 307 is of the same order as that of the first quantum dot 301, that is, R F1 ≒ R1, the output voltage V QD1 is equal to approximately half of the input voltage V set , or V QD1 ≒ V 1e . Therefore, setting V set to be approximately V 2e provides a range of output voltage V QDn that is sufficient to cover the required operating range for each quantum dot.

[0096] The input voltage V set can be reduced to result in a smaller output voltage V Fn by increasing the channel resistance R QDn . However, since the resistance R n of the quantum dot is usually very large, especially at extremely low temperatures, it is difficult to achieve a very high channel resistance R Fn >> R n . Fn

[0097] Figure 4 is a circuit diagram of a part of a quantum device according to an embodiment of the present invention. The quantum device includes a qubit layer having quantum dots 401 that can be used as qubits. The circuit also includes a trimming layer having an integrated circuit element 404 used for voltage trimming as described herein. The circuit also includes an adjustment layer for adjusting a signal input including a first field effect transistor 405. The circuit further includes an adjustment selection layer including a second field effect transistor 406 electrically connected to word lines 409 and bit lines 410 in a crossbar configuration. In this example, the integrated circuit element 404 includes a silicon nanowire multiple quantum dot device as shown in FIG. 6. In another example, the integrated circuit element may include a multiple quantum dot device with any defined gates.

[0098] Each of the integrated circuit element 404 and the first and second field effect transistors (FETs) 405, 406 includes respective source, drain, and gate terminals. The integrated circuit element 404 further includes an electrically insulated element capacitively coupled to the gate terminal and capacitively coupled to the source-drain channel. The quantum device includes additional quantum dots not shown in this part for simplicity.

[0099] In this example, for each gate of each quantum dot, the device includes an integrated circuit element and two FETs electrically connected as shown for the quantum dot 401 in FIG. 4. This configuration provides control over each quantum dot's gate to account for variations in the characteristics of the quantum dots. The non-volatile resistance value of each integrated circuit element connected to the gate of the quantum dot can be adjusted to control the output voltage applied to the gate of the inductive quantum dot. In the example described below, the gate is a plunger gate. In another example, the gate is a barrier gate, and the output voltage applied by the integrated circuit element 404 can be used to adjust the height of the electrostatic barrier defining the edge of the inductive quantum dot.

[0100] The quantum dot 401 is electrically grounded and has a resistance R DResistor 402 having and capacitance C D It is schematically shown as capacitor 403 having. Quantum dot 401 is an electron spin quantum dot formed in the silicon layer of the quantum device. Quantum dot 401 can be induced by applying a voltage to the gate of quantum dot 401. The number of electrons in quantum dot 401 can be controlled by adjusting the voltage applied to the quantum dot plunger gate.

[0101] Integrated circuit element 404 is electrically connected to the silicon layer capable of inducing quantum dot 401. In this example, the drain terminal of integrated circuit element 404 is electrically connected to quantum dot 401, the source terminal of integrated circuit element 404 is connected to a voltage source configured to supply input voltage V DD and is electrically connected to the voltage source, and the gate terminal of integrated circuit element 404 is electrically connected to the drain terminal of the first FET 405.

[0102] This configuration is such that the output voltage of integrated circuit element 404 is applied to the gate of the induced quantum dot 401. The output voltage depends on the input voltage applied to the source terminal of integrated circuit element 404 and the non-volatile resistance value of integrated circuit element 404. The input voltage applied using the voltage source is typically applied to a plurality of quantum dots (not shown). This reduces the number of required voltage sources. The resistance values of each integrated circuit element connected to the gate of each quantum dot can be adjusted so that the same input voltage can provide different output voltages to the gates of different quantum dots as required according to the characteristics of each quantum dot.

[0103] In this example, the non-volatile resistance value is adjusted using the first FET 405, which may be referred to as the adjustment FET 405. The drain terminal of the first FET 405 is electrically connected to the gate terminal of integrated circuit element 404, and the source terminal of the first FET 405 is the adjustment signal V Pis electrically connected to a voltage source configured to supply, and the gate terminal of the first FET 405 is electrically connected to the drain terminal of the second FET 406. The first FET 405 can be turned on and off by applying a sufficiently large bias potential to the gate terminal using the second FET 406. When the first FET 405 is "on", the first FET 405 is enabled, and current can flow between the source and drain terminals of the first FET 405. When the first FET 405 is "off", the first FET 405 is disabled, and the source-drain current can be ignored. Therefore, when the first FET 405 is enabled, the adjustment signal V P is passed to the integrated circuit element 404, and when the first FET 405 is disabled, the adjustment signal V P is not passed to the integrated circuit element 404.

[0104] The current flowing through the first FET 405 can be controlled by adjusting the bias potential applied to the source terminal using the connected voltage source. The non-volatile resistance value of the integrated circuit element 404 can be adjusted by changing the charge level of its electrically isolated element. The electrically isolated element can be charged and discharged by controlling the current flowing through the first FET 405. For example, when the enabled first FET 405 is set up with a positive source-drain bias potential, that is, when the adjustment signal V P is positive, the charge on the electrically isolated element increases. Conversely, when the enabled first FET 405 is set up with a negative source-drain bias potential, that is, when the adjustment signal V P is negative, the charge on the electrically isolated element decreases (i.e., the electrically isolated element discharges). Therefore, the adjustment FET 405 acts as a switch and is configured to adjust the non-volatile resistance value of the integrated circuit element 404 only when the adjustment FET 405 is enabled.

[0105] In this example, the first FET 405 is selected using the second FET 406. The second FET 406 may be referred to as the selector FET 406. The drain terminal of the second FET 406 is electrically connected to the gate terminal of the first FET 405, the source terminal of the second FET 406 is electrically connected to the word line 409, and the gate terminal of the second FET 406 is electrically connected to the bit line 410. The bit line 410 and the word line 409 form part of a crossbar array. The second FET can be turned on and off by applying an appropriate bias potential to the bit line 410. The current flowing through the second FET 406 can be adjusted by adjusting the bias potential applied to the source terminal of the second FET 406.

[0106] The second FET 406 can be enabled by applying a bias potential to the electrically connected bit line 410 and word line 409. The crossbar array includes a plurality of bit lines and word lines (not shown) and is configured to be able to select each second FET corresponding to a quantum dot. When the first and second FETs 405, 406 are enabled, an electrical connection is provided between the crossbar array and the integrated circuit element 404. For a quantum device having a plurality of quantum dots and thus a plurality of integrated circuit elements, the crossbar array is configured to be selectively electrically connected to any of the integrated circuit elements. In this way, the non-volatile resistance value of each integrated circuit element can be individually adjusted.

[0107] The first and second FETs 405, 406 form an adjustment control circuit and are used to set up the quantum device during the setup stage. The integrated circuit element 404 forms a trimming layer and is used to trim, i.e., reduce, the input voltage. The integrated circuit element 404 is enabled and adjustable during the setup stage. Thereafter, during normal operation, the integrated circuit element 404 operates in a region below the threshold. Quantum operations can be executed during normal operation, and the quantum device further includes a parsing and readout layer including a qubit pulse control circuit 407 and a qubit readout control circuit 408 for controlling qubits during the operation of the device.

[0108] The qubit pulse control circuit 407 and the qubit readout control circuit 408 are electrically connected between the integrated circuit element and the induced quantum dot. In this example, the qubit pulse control circuit 407 includes a capacitor having a capacitance C C and a voltage source. The qubit pulse control circuit 407 is configured to adjust the state of the qubit by applying a bias potential using the voltage source. The output voltage V QD of the integrated circuit element 404 is configured to supply a constant DC offset voltage to induce the quantum dot, and the qubit pulse control circuit 407 is configured to supply an AC control signal to the electrons in the induced quantum dot, thereby adjusting the state of the electron spin qubit.

[0109] In this example, the qubit readout control circuit 408 includes a first capacitor having a capacitance C C , a second capacitor having a capacitance C G with respect to ground, and an inductor having an inductance L. The qubit readout control circuit 408 is configured to read out or infer the state of the qubit. Any suitable qubit readout control circuit can be used and may be referred to as a tank circuit, an LC resonator, an LC tank circuit, a resonant circuit, or a tuned circuit.

[0110] Since the qubit pulse control circuit and the qubit readout control circuit are electrically connected to a plurality of quantum dots in the array, the state of the qubits can be manipulated and read out for the plurality of quantum dots. Optionally, the qubit pulse control circuit and the qubit readout control circuit can be electrically connected to all the quantum dots in order to control each quantum dot in the same manner simultaneously throughout the quantum device. Alternatively, the quantum dots in the device can be divided into two or more subgroups of quantum dots, and each subgroup may be electrically connected to the qubit pulse control circuit and the qubit readout control circuit. Controlling the quantum dots globally in this way reduces the control circuitry required to perform quantum operations.

[0111] In FIG. 4, the integrated circuit element 404 provides an adjustable addressable analog memory using the first FET 405 and supplies a constant DC voltage offset V QD to the quantum dot 401. The qubit pulse control circuit 407 and the qubit readout control circuit 408 are electrically connected between the integrated circuit element 404 and the quantum dot 401 and provide an AC coupled control signal for conditioning and controlling the inductive quantum dot 401. A quantum device typically comprises a plurality of quantum dots. The addressable analog memory in the form of an integrated circuit element for each quantum dot can be used to individually adjust the DC voltage offset of each quantum dot. The AC coupled control signal is applied to a plurality of quantum dots having different DC voltage offsets to achieve global control of the scaled qubit array.

[0112] To perform a quantum operation using a quantum device, the quantum device is first set up in a setup phase. During the setup phase, the memory state is written by adjusting the charge of the floating element of the integrated circuit element 404. The memory state is stably retained during the operation of the device. The memory is non-volatile with respect to the operating conditions of the integrated circuit element 404.

[0113] During the setup phase, the non-volatile resistance value R of the integrated circuit element 404 F is adjusted to the set non-volatile resistance value R F,set In this example, the integrated circuit element 404 is for controlling the voltage of the plunger gate of the inductive quantum dot 401. The set non-volatile resistance value R F,set is such that when the input voltage V DD is applied to the integrated circuit element 404, i.e., when V 1e ≦V QD <V 2e , the inductive quantum dot 401 is set to be occupied by one electron. The voltages V 1e and V 2e depend on the characteristics of the quantum dot 401, and thus the set non-volatile resistance value R F,set required for the plunger gate of each quantum dot in the array varies accordingly.

[0114] The resistance value may be set using the adjustment FET 405. Since the resistance value is non-volatile, it can be set and maintained at a fixed value without power input. This eliminates the need to refresh the set point during the operation of the quantum device. To set the resistance value using the adjustment FET 405, the adjustment FET 405 is first enabled by applying bias potentials V BT , V WT to the word line 409 and the bit line 410 electrically connected to the second FET 406 such that the adjustment FET 405 is selected and turned "on". When the adjustment FET 405 is enabled, the resistance value of the integrated circuit element 404 can be adjusted by applying an adjustment voltage V P to the source terminal of the adjustment FET 405. The adjustment FET 405 is electrically connected to the integrated circuit element 404 such that by applying the adjustment voltage V P to the enabled adjustment FET 405, the resistance value R F of the integrated circuit element 404 can be adjusted. The set non-volatile resistance value R F,set depends on the adjustment voltage V P .

[0115] When the resistance value of the integrated circuit element 404 is adjusted to the set resistance value R F,set the control circuits used in the setup phase, i.e., the first and second FETs 405, 406, can be disabled and disconnected. Thereby, the power consumption is reduced. The electrostatic charge accumulated by the electrically insulated or floating elements of the integrated circuit element 404 is non-volatile, and thus the set resistance value can be maintained for a long time without requiring a refresh. The integrated circuit element 404 operates in a region below a low threshold value and does not require a power input.

[0116] During operation, the input voltage V DD can be applied to the integrated circuit element 404. The output voltage V QD of the integrated circuit element 404 depends on the input voltage V DD and the set resistance value R F,set The output voltage V QD of the integrated circuit element 404 is applied to the gate of the inductive quantum dot 401. In this example, the output voltage V QD of the integrated circuit element 404 is applied to the plunger gate of the inductive quantum dot 401 to control the electron occupancy of the quantum dot 401. In another example, the output voltage of the integrated circuit element is applied to the barrier gate of the inductive quantum dot to control the height of the tunnel barrier and / or the tunnel coupling strength between the inductive quantum dot and the adjacent confinement region.

[0117] For a quantum device including a plurality of quantum dots, the gates of each quantum dot are electrically connected to individual integrated circuit elements that can be adjusted according to the characteristics of that quantum dot. For example, the device has first and second resistance values R F1 R F2 and first and second threshold voltages V th1 V th2It may include first and second gates of first and second inductive quantum dots respectively connected to first and second integrated circuit elements. During the setup phase, a crossbar array for selecting one or more integrated circuit elements is used to apply appropriate bias potentials to the word lines and bit lines connected to the FETs electrically connected to the first integrated circuit element, thereby selecting the first integrated circuit element. Following the selection of the first integrated circuit element, as described above, the first non-volatile resistance value R F1 is adjusted to the first set non-volatile resistance value R F1,set .

[0118] Thereafter, the second integrated circuit element is selected by applying appropriate bias potentials to the word lines and bit lines connected to the FETs electrically connected to the first integrated circuit element. There may be one word line or bit line common to both FETs connected to each of the first and second integrated circuit elements. If both the word line and the bit line are common, the adjustment of the first and second resistance values R F1 , R F2 is performed simultaneously. However, usually, due to the nature of the variation in characteristics between quantum dots, individual control is desirable. Following the selection of the second integrated circuit element, as described above, the second non-volatile resistance value R F2 is adjusted to the second set non-volatile resistance value R F2,set .

[0119] Each nth integrated circuit element of the quantum device can be selected and adjusted during the setup phase. Any channel resistance can be set for each integrated circuit element to form an analog memory. The resistance value, and accordingly, the threshold voltage and output voltage of the integrated circuit element applied to the gates of the associated quantum dots, are kept constant during the lifetime of the device and do not require refreshing.

[0120] The setpoint of the resistance value of each quantum dot is usually selected such that the qubit resonance line is targeted. Although it is desirable to apply a global drive frequency to the qubits, qubit resonance varies according to the electron g-factor, which varies significantly across the device. The electron g-factor g e is nominally equal to 2, but the change in g e to -2 is about 10 -2 . The electron g-factor can be adjusted by inducing a Stark shift using an applied electric field, but since the Stark shift range is δg e = 10 -4 ~10 -3 , this is not sufficient to overcome the g-factor variation. Cavity amplitude modulation can be used to overcome this. A single drive frequency can be split into a 2N + 1 frequency band, thereby enabling most or all qubits to be addressed using a single drive frequency, regardless of the different g-factors. However, this requires a voltage adjusted for each quantum dot in the device such that each quantum dot is occupied by only one electron. The setpoint of the resistance value of each quantum dot can be selected to meet this requirement.

[0121] When the resistance value of each of the plurality of integrated circuit elements is adjusted to the set resistance value, the control circuit used in the setup stage can be disabled and put into an idle state. For non-volatile integrated circuit elements, the adjustment control circuit in the idle state can be disconnected to reduce potential power consumption or heat load. During operation, the same input voltage V DD can be applied to the first and second integrated circuit elements (and any further integrated circuit elements within the quantum device). The first and second output voltages of the integrated circuit elements are the input voltage V DD and the first and second set resistance values R F1,set , R F2,setIt depends. The first output voltage of the first integrated circuit element is applied to the plunger gate of the first inductive quantum dot to control that voltage for single electron occupancy. The second output voltage of the second integrated circuit element is applied to the plunger gate of the second inductive quantum dot to control that voltage for single electron occupancy. Similarly, the n-th output voltage of the n-th integrated circuit element is applied to the plunger gate of the n-th inductive quantum dot to control that voltage for single electron occupancy.

[0122] Typically, a quantum device may operate at extremely low temperatures. The characteristics of a quantum device, such as threshold voltage and channel resistance, typically change with temperature. Therefore, the setup phase is typically performed at the desired operating temperature before device operation. By following the procedure of the setup phase described above, the device can be reset. If readjustment or reconfiguration of the device is desired, the device may be reset.

[0123] FIG. 5 is a circuit diagram of a part of a quantum device according to an embodiment of the present invention. The circuit includes an adjustment layer 514 including an adjustment element and a crossbar array, a trimming layer 515 including an integrated circuit element configured to output a constant DC offset voltage, a parsing and readout layer 516 including an AC-coupled input configured to adjust the DC offset voltage to control a quantum bit, and a quantum bit layer 517 including an electron spin quantum bit formed from a single quantum dot induced by applying a voltage to the gate of an inductive quantum dot.

[0124] The circuit includes a first and a second quantum dot 501, 502 in the quantum bit layer 517, a first and a second integrated circuit element 503, 504 in the trimming layer 515, a first and a third field effect transistor (FET) 505, 506 in the adjustment layer 514, and a second and a fourth FET 507, 508 in the adjustment layer 514. The first and second quantum dots 501, 502 are electrically connected to the ground potential. The circuit also includes a quantum bit pulse input 509 that forms a quantum bit pulse control circuit and a tank circuit input 510 that forms a quantum bit readout control circuit. The quantum bit parsing and readout control circuits 509, 510 are disposed in the parsing and readout layer 516.

[0125] In FIG. 5, the circuit elements associated with the first quantum dot 501 are electrically connected according to the first configuration, and the circuit elements associated with the second quantum dot 502 are electrically connected according to the second configuration. Typically, the quantum dots in a quantum device are connected to the associated circuit elements according to either the first configuration or the second configuration. Optionally, some of the quantum dots in the device are connected according to the first configuration and other quantum dots in the device are connected according to the second configuration.

[0126] In the first configuration, the first quantum dot 501, the first integrated circuit element 503, the first FET 505, and the second FET 507 are electrically connected as described with respect to FIG. 4. The resistance value of the first integrated circuit element 503 can be adjusted with respect to an input voltage V DD connected to the drain terminal of the first integrated circuit element 503. The input voltage V DD is a global voltage reference. The non-volatile resistance value of the first integrated circuit element 503 is the channel resistance of the first integrated circuit element 503. When this channel resistance is arranged in series with a load resistance such as the resistance R D of the first quantum dot 501, it forms a common voltage divider configuration. Thus, the voltage seen at the load (i.e., the first quantum dot 501) is reduced with respect to the supply (i.e., the input voltage V DD ).

[0127] In the second configuration, the second quantum dot 502 is electrically connected to an electrically isolated element of the second integrated circuit device 504. The drain of the second integrated circuit device 504 is connected to ground. The electrical connections between the second integrated circuit device 504, the third FET 506, and the fourth FET 508 are configured in the same manner as the electrical connections between the first integrated circuit device 503, the first FET 505, and the second FET 507. Since the electrically isolated element is capacitively coupled to the source-drain channel and gate terminal of the second integrated circuit device 504, there is a DC voltage offset that can be applied to the gate of the second quantum dot 502. The electrically isolated element of the second integrated circuit device is directly connected to the gate of the second quantum dot 502.

[0128] The circuit shown in FIG. 5 includes a crossbar array having a first bit line 511, a second bit line 512, and a word line 513. In this example, the source terminals of both the second FET 507 and the fourth FET 508 are electrically connected to the word line 513. The gate terminals of the second and fourth FETs 507, 508 are electrically connected to separate bit lines. The first bit line 511 is electrically connected to the second FET 507, and the second bit line 512 is electrically connected to the fourth FET 508. In another example where both the first and second quantum dots are connected according to the same configuration, the arrangement of the second and fourth FETs 507, 508 with respect to the word line 513 and the bit lines 511, 512 can also be as shown in FIG. 5.

[0129] The crossbar array is configured to be selectively electrically connected to the first and / or second integrated circuit devices 503, 504. The selective electrical connection is achieved by adjusting the bias potentials applied to each of the first and second bit lines 511, 512 and the word line 513. Each of the first and second bit lines 511, 512 and the word line 513 is electrically connected to a voltage source configured to supply a controllable bias potential. A bias potential V greater than the threshold voltage of the second FET 507 BT(a)When a bias potential V is applied to the first bit line 511, the second FET 507 is enabled, i.e., the source-drain channel resistance becomes low, and the second FET 507 is in the "on" state. A bias potential V greater than the threshold voltage of the fourth FET 508 BT(b) When applied to the second bit line 512, the fourth FET 508 is enabled. The bias potentials V applied to the first or second bit lines 511, 512 BT(a) , V BT(b) If they are lower than the threshold voltages of the second or fourth FETs 507, 508 respectively, that FET is disabled, i.e., the source-drain channel resistance becomes high, and the second or fourth FETs 507, 508 are in the "off" state.

[0130] When the second and / or fourth FETs 507, 508 are enabled, the bias potential V applied to the word line 513 WT can be adjusted to control the source-drain current of the second and / or fourth FETs 507, 508. In one example, the bias potential V applied to the first bit line 511 BT(a) is greater than the threshold voltage of the second FET 507, and the bias potential V applied to the second bit line 512 BT(b) is lower than the threshold voltage of the fourth FET 508. In this example, when the bias potential V WT is applied to the word line 513, the signal is passed through the second FET 507 to enable the first FET 505, but not through the fourth FET 508 to the third FET 506. Therefore, the bias potential V applied to the source terminals of the first and third FETs 505, 506 P can be used to adjust the resistance value of the first integrated circuit element 503, but the signal is not passed to the second integrated circuit element 504.

[0131] FIG. 6 schematically shows a cross-sectional side view of an integrated circuit element 600. The integrated circuit element 600 shown in FIG. 6 is a silicon nanowire multiple quantum dot device manufactured by wiring silicon nanowires on a thin silicon-on-insulator substrate. The integrated circuit element 600 is known to exhibit hysteresis characteristics in the threshold voltage and the corresponding channel resistance.

[0132] The integrated circuit element 600 includes a silicon layer 601. A first dielectric layer 602 is disposed on the silicon layer 601. In this example, the first dielectric layer 602 includes thermally grown silicon oxide (SiO2). The integrated circuit element 600 includes five polycrystalline silicon (polysilicon) gates 603 to 607 deposited in two steps. In the first step, a first polysilicon gate 603 and a second polysilicon gate 604 are deposited. In this example, the first and second polysilicon gates 603, 604 have a thickness of about 50 nanometers and are deposited simultaneously.

[0133] Following the deposition of the first and second polysilicon gates 603, 604, a second dielectric layer 608 is deposited. In this example, the second dielectric layer 608 is SiO2 with a thickness of about 35 nanometers and is grown using low-pressure chemical vapor deposition (LPCVD). The third, fourth, and fifth polysilicon gates 605, 606, 607 are deposited on the second dielectric layer 608. In this example, the third, fourth, and fifth polysilicon gates 605, 606, 607 have a thickness of about 80 nanometers and are deposited simultaneously.

[0134] Each of the first, second, and fourth polysilicon gates 603, 604, 606 has a width of about 100 nanometers. The fourth polysilicon gate 606 is located between the first and second polysilicon gates 603, 604 and may overlap each of them by about 10 nanometers. The third polysilicon gate 605 may overlap the first polysilicon gate 603 by about 10 nanometers. The fifth polysilicon gate 607 may overlap the second polysilicon gate by about 10 nanometers. The second dielectric layer 608 functions as an electrically insulating barrier between the first and second polysilicon gates 603, 604 and the third, fourth, and fifth polysilicon gates 605, 606, 607.

[0135] The third and fifth polysilicon gates 605, 607 provide source and drain terminals and extend into the charge storage section. The first, second, and fourth polysilicon gates 603, 604, 606 define quantum dots at the interface between the silicon layer 601 and the first dielectric layer 602.

[0136] In another example, the integrated circuit element may comprise a different number of polysilicon gates. For example, seven or three. Typically, the polysilicon gates are deposited in two layers separated by an electrically insulating layer. Further examples of devices suitable for use as integrated circuit elements are disclosed in Duan et al, "Dispersive readout of reconfigurable ambipolar quantum dots in a silicon-on-insulator nanowire", arXiv:2009.13944v1 [cond-mat.mes-hall] (2020).

[0137] In yet another example, the integrated circuit element is a conventional floating gate metal oxide semiconductor field effect transistor.

[0138] As will be understood, a quantum device including an integrated circuit element for controlling the voltage applied to the gate of an inductive quantum dot is disclosed, along with a method of using the device. The integrated circuit element provides an addressable analog memory. The resistance value of the integrated circuit element can be adjusted to provide a controllable voltage to the gate of the quantum dot, which voltage can be maintained during operation of the device at cryogenic temperatures and does not require refreshing. During operation of the device, an AC-coupled control signal is used to condition and read out the state of qubits within the device.

Claims

1. It is a quantum device, A silicon layer on which multiple quantum dots can be induced, A first set of gates for a first inductive quantum dot, comprising two first barrier gates and a first plunger gate for controlling the electrical potential defining the first inductive quantum dot, wherein the first gate of the first set is either the first plunger gate or one of the two first barrier gates, A second set of gates for a second inductive quantum dot, comprising two second barrier gates and a second plunger gate for controlling the electrical potential defining the second inductive quantum dot, wherein the second gate of the second set is either the second plunger gate or one of the two second barrier gates, Adjustable first non-volatile resistance value R Ｆ A first integrated circuit element having a first gate voltage control, A second integrated circuit element having an adjustable second non-volatile resistance value and controlling the voltage of the second gate, Equipped with, The first integrated circuit element has an input voltage and a first output voltage, The first output voltage depends on the input voltage and the first non-volatile resistance value. The second integrated circuit element has the input voltage and the second output voltage, The second output voltage depends on the input voltage and the second non-volatile resistance value. The first integrated circuit element and the second integrated circuit element are electrically connected to the first gate and the second gate, respectively, such that the first output voltage and the second output voltage are applied to the first gate of the first inductive quantum dot and the second gate of the second inductive quantum dot, respectively. Quantum devices.

2. The quantum device according to claim 1, wherein the first integrated circuit element and / or the second integrated circuit element comprises a floating-gate metal oxide semiconductor field-effect transistor.

3. The quantum device according to claim 1, wherein the first integrated circuit element and / or the second integrated circuit element comprises a gate-defined multiple quantum dot device.

4. The first inductive quantum dot, when induced, exhibits a first resistance value (R Ｄ ) has, The first output voltage (V ｏｕｔ ) is the input voltage (V ｉｎ ) is proportional to, and the constant of proportionality is R Ｄ / (R Ｆ +R Ｄ ) is equal to, A quantum device according to any one of claims 1 to 3.

5. The quantum device further comprises a regulating field-effect transistor (FET), The quantum device according to any one of claims 1 to 3, wherein the adjusting field-effect transistor (FET) is electrically connected to the first integrated circuit element or the second integrated circuit element and is configured to enable or disable an adjusting voltage for the first integrated circuit element or the second integrated circuit element, respectively.

6. The quantum device according to any one of claims 1 to 3, wherein the first induced quantum dot and / or the second induced quantum dot are used as qubits.

7. The quantum device further comprises a qubit pulse control circuit configured to adjust the state of a first qubit and / or a second qubit. The quantum device according to claim 6, wherein the qubit pulse control circuit is electrically connected between the first integrated circuit element and / or the second integrated circuit element and the first inductive quantum dot and / or the second inductive quantum dot, respectively.

8. The quantum device further comprises a qubit readout control circuit configured to read out the state of a first qubit and / or a second qubit. The quantum device according to claim 7, wherein the qubit readout control circuit is electrically connected between the first integrated circuit element and / or the second integrated circuit element and the first inductive quantum dot and / or the second inductive quantum dot, respectively.

9. The quantum device according to claim 1, further comprising a crossbar array configured to be selectively electrically connected to the first integrated circuit element and / or the second integrated circuit element.

10. A method of using quantum devices, The aforementioned quantum device is A silicon layer on which multiple quantum dots can be induced, A first set of gates for a first inductive quantum dot, comprising two first barrier gates and a first plunger gate for controlling the electrical potential defining the first inductive quantum dot, wherein the first gate of the first set is either the first plunger gate or one of the two first barrier gates, A second set of gates for a second inductive quantum dot, comprising two second barrier gates and a second plunger gate for controlling the electrical potential defining the second inductive quantum dot, wherein the second gate of the second set is either the second plunger gate or one of the two second barrier gates, Adjustable first non-volatile resistance value (R Ｆ A first integrated circuit element having a first gate voltage control, A second integrated circuit element having an adjustable second non-volatile resistance value and controlling the voltage of the second gate, A crossbar array for selecting one or more integrated circuit elements and Equipped with, This method is A step of inducing a first quantum dot and a second quantum dot, The steps include selecting the first integrated circuit element, The steps include adjusting the first non-volatile resistance value of the first integrated circuit element to a first set non-volatile resistance value, The steps include selecting the second integrated circuit element, The steps include adjusting the second non-volatile resistance value of the second integrated circuit element to a second set non-volatile resistance value, A step of applying an input voltage to the first integrated circuit element and the second integrated circuit element, wherein the first output voltage of the first integrated circuit element and the second output voltage of the second integrated circuit element depend on the input voltage and the first set non-volatile resistance value and the second set non-volatile resistance value, respectively. The steps include applying the first output voltage of the first integrated circuit element to the first gate of the first inductive quantum dot, The steps include applying the second output voltage of the second integrated circuit element to the second gate of the second inductive quantum dot. Methods that include...

11. The quantum device further comprises a regulating field-effect transistor (FET) having a source terminal, a drain terminal, and a gate terminal. The step of adjusting the first non-volatile resistance value of the first integrated circuit element to the first set non-volatile resistance value, or adjusting the second non-volatile resistance value of the second integrated circuit element to the second set non-volatile resistance value, The steps include: applying a voltage to the gate terminal of the adjusting field-effect transistor (FET) to enable the adjusting field-effect transistor (FET) by causing current to flow between the source terminal and drain terminal of the adjusting field-effect transistor (FET); The steps include applying an adjustment voltage to the adjustment field-effect transistor (FET), Equipped with, The adjusting field-effect transistor (FET) is electrically connected to the first integrated circuit element or the second integrated circuit element, and by applying the adjustment voltage to the activated adjusting field-effect transistor (FET), the first non-volatile resistance value of the first integrated circuit element or the second non-volatile resistance value of the second integrated circuit element is adjusted. The first set non-volatile resistance value and the second set non-volatile resistance value depend on the adjustment voltage. The method according to claim 10.

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