Systems and methods for controlling a dynamic environment

Abstract

An apparatus and method for controlling and communicating with a plurality of devices in a dynamic environment. The controller can issue commands to one or more of the devices in the dynamic environment and can receive information based on signals from one or more of the devices in the dynamic environment. Commands from the controller and signals from the devices are converted by a flexible I / O circuit connected between the controller and the plurality of devices into different signaling types to establish compatible communication between the controller and the devices, thereby enabling adaptation to a wide variety of signaling types. A signal processing resource circuit (SPRe circuit) is additionally implemented between the controller and the devices to offload signal processing tasks from the controller to the SPRe circuit. The offloading can provide a low-latency response by the controller to conditions occurring in a complex dynamic environment and can further reduce the processing time associated with the signal processing tasks.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of priority to U.S. Patent Application No. 63 / 358,260, titled "Systems and Methods for Controlling Dynamic Environments," filed on July 5, 2022, which is hereby incorporated by reference in its entirety.

Background Art

[0002] Modern automatic control systems can include a number of controlled devices, sensors, actuators, cameras, and one or more controllers (e.g., microprocessors or microcontrollers). The controller can receive and process data from at least the sensors and cameras and issue commands to operate the controlled devices, at least partially based on the received data. Such automatic control systems operate in combination with dynamic environments where conditions within the environment change frequently, which can cause changes in one or more sensor outputs, changes in the responses by the control system, and changes in the control signals output by the controller.

Summary of the Invention

[0003] The inventors have recognized and understood that a sensing and control system for a dynamic environment should be fast (e.g., have a reflexive response) with very low latency between receiving signals and data from connected devices within the environment (such as sensors, motors, actuators, lighting fixtures, robotic devices, imaging devices such as cameras, etc.) and transmitting control signals to controlled devices operating within the dynamic environment. Further, the sensing and control system should be flexible to handle a wide variety of signaling types, including different digital and analog signaling types.

[0004] Previous research by the inventors relates to not only a fairly low latency control system for a dynamic environment but also a flexible input / output circuit that dynamically adapts to various different signal types (e.g., transmission and / or reception of single-ended digital and analog signaling types and / or differential digital and analog signaling types of analog signals) for a number of devices within the dynamic environment. With respect to this previous research, an exemplary implementation of the low latency control system can be found in U.S. Patent No. 9,459,607, entitled "Methods, Apparatus, and Systems for Monitoring and / or Controlling Dynamic Environments," issued on October 4, 2016, which patent is hereby incorporated by reference in its entirety. An exemplary implementation of the flexible input / output circuit can be found in U.S. Patent No. 11,182,326, entitled "Input / Output Apparatus and Methods for Monitoring and / or Controlling Dynamic Environments," issued on November 23, 2021, which patent is hereby incorporated by reference in its entirety.

[0005] From the foregoing, implementations of the invention described in this disclosure generally relate to extending the signal processing architecture of the inventors' previous research while at the same time, by adding a Signal Processing Resource circuit (SPRe circuit), maintaining or even reducing the latency of such systems (or increasing the reflection responsiveness). In various embodiments, the SPRe circuit is communicatively coupled to both a flexible input / output circuit and one or more controllers so as to form an encompassing control system for a dynamic environment. Examples of signal processing functions that may be performed by the SPRe circuit, not only on signals or other information received from the controller but also on signals or other information received from the flexible input / output circuit, include analog filtering; digital filtering; frequency and / or phase detection; normalization, scaling and / or other conversions (e.g., via one or more look-up tables i.e. "LUT"); digital signal generation; and analog signal generation, but are not limited thereto.

[0006] In various aspects, an SPRe circuit as disclosed herein can be specifically configured by one or more controllers (including those previously disclosed by the inventors) to perform various signal processing and / or signal generation functions. Further, the controller that configures the signal processing and / or signal generation functions of the SPRe circuit also provides one or more signals to be processed by the SPRe circuit (e.g., for eventual transmission via the flexible input / output circuit to one or more devices within a dynamic environment). Similarly, the SPRe circuit may receive one or more signals from the flexible input / output circuit (which signals, in a first instance, are provided to the flexible input / output circuit by one or more devices within a dynamic environment), the SPRe circuit can process these signals received from the flexible input / output circuit (in some instances, at least partially based on a particular configuration of the SPRe circuit by the controller), and then transmit the processed signals to the controller.

[0007] In some exemplary implementations, as will be discussed in further detail below, the SPRe circuit according to the inventive concept disclosed herein can include a number of processing resources. In one aspect, each of the processing resources of the SPRe circuit is specifically configured at a given time (e.g., by one or more controllers) to perform some type of signal processing or signal generation on a signal provided to the SPRe circuit by either a controller or a flexible input / output circuit. In one embodiment, the first processing resource of the SPRe circuit may be configured by a controller for first type of signal processing or signal generation on a first signal (received from a controller or from a flexible input / output circuit), and the second processing resource of the SPRe circuit may be configured by a controller for second type of signal processing or signal generation on the first signal and / or the second signal received from a controller or a flexible input / output circuit. Further, the first processing resource of the SPRe circuit may alternatively or additionally configure and / or trigger the operation of the second processing resource of the SPRe circuit to perform second type of signal processing or signal generation, or yet another type of signal processing or signal generation, on the first signal, the second signal, and / or the third signal received from the controller of the flexible input / output circuit.

[0008] From the foregoing points, it is of course possible that the respective processing resources of the SPRe circuit in various exemplary implementations are flexibly and dynamically configured (and reconfigured) to perform some type of signal processing and / or signal generation in relation to not only "outbound" signals (from the controller to the SPRe circuit, then to the flexible input / output circuit, and then to one or more devices within the dynamic environment), but also "inbound" signals (from one or more devices within the dynamic environment to the controller, via the flexible input / output circuit and the SPRe circuit). Additionally, it is of course possible that at least a first processing resource of the SPRe circuit communicates directly with one or more other processing resources of the SPRe circuit and, in some cases, configures and / or triggers the operation of one or more other processing resources, at least in part based on the processing or generation of signals by the first processing resource. In this way, a number of processing resources of the SPRe circuit can be employed in tandem (e.g., simultaneously and / or sequentially, as in an "event and action cascade") to perform the corresponding type of signal processing and / or signal generation with little or no intervention or configuration by the controller (or any significant use of the controller's processing bandwidth).

[0009] The foregoing concept of one processing resource of the SPRe circuit having the ability to dynamically configure and / or trigger the operation of one or more other processing resources of the SPRe circuit is referred to herein as "cross-communication among multiple processing resources." Thereby, the SPRe circuit can offload signal processing tasks that would otherwise be handled by the controller, freeing up the controller to participate in other system management and control tasks. In various aspects, offloading the signal processing bandwidth from the controller to the SPRe circuit, and the speed of the SPRe circuit, can significantly reduce the overall latency of the sensing and control system.

[0010] One implementation relates to a control system comprising: a controller for issuing a control signal for controlling at least one controlled device in a dynamic environment; a flexible input / output (I / O) circuit communicatively coupled to the controller and the at least one controlled device to convert at least one first signal of a first signaling type from the controller into a second signal of a second signaling type supported by a first controlled device of the at least one controlled devices; and a signal processing resource communicatively coupled to the controller and the flexible I / O circuit, the signal processing resource being configured to offload at least one signal processing task related to the first signal from the controller.

[0011] One implementation relates to a control system comprising: a controller for receiving signals and data from at least one connected device in a dynamic environment; a flexible input / output (I / O) circuit communicatively coupled to the controller and the at least one connected device to convert at least one first signal of a first signaling type from a first connected device of the at least one connected devices into a second signal of a second signaling type supported by the controller; and a signal processing resource communicatively coupled to the controller and the flexible I / O circuit, the signal processing resource being configured to offload at least one signal processing task from the controller related to the second signal.

[0012] Of course, all combinations of the foregoing concepts and additional concepts to be considered in more detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the subject matter of the invention disclosed herein. Specifically, all combinations of the claimed subject matter that appear at the end of this disclosure are contemplated as being part of the subject matter of the invention disclosed herein. It is also of course contemplated that terms explicitly employed herein that may also appear in any incorporated by reference disclosure should be given the meaning most consistent with the particular concepts disclosed herein.

Brief Description of the Drawings

[0013] Those skilled in the art will understand that the drawings are primarily for illustrative purposes and are not intended to limit the scope of the subject matter of the invention described herein. The drawings are not necessarily to scale, and in some instances, various aspects of the subject matter of the invention disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar elements and / or structurally similar elements).

[0014]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

[0015] I. Overview FIG. 1A illustrates an example of a sensing and control system 100 that includes a control system 102 and a plurality of connected devices 170 within a dynamic environment 105 communicatively coupled to a controller 110 within the control system 102. In FIG. 1A, for simplicity and illustrative purposes, the plurality of connected devices 170 are shown as including a first device 170A and a second device 170B, although of course, various devices may be deployed within the dynamic environment 105 to sense one or more aspects of the environment or states within the environment and / or to control one or more actions taken within the dynamic environment (as will be discussed in more detail below in connection with FIG. 1B). Also as illustrated in FIG. 1A, the control system 102 includes a controller 110, a signal processing resource circuit (SPRe circuit) 115, and a flexible input / output circuit (“flex I / O circuit”) 120.

[0016] Regarding the controller 110 of the control system 102, an exemplary implementation of the controller 110 can be found in U.S. Patent No. 9,459,607, entitled "Methods, Apparatus, and Systems for Monitoring and / or Controlling Dynamic Environments," issued on October 4, 2016, which is hereby incorporated by reference in its entirety. As described in this patent, generally, the controller 110 monitors and controls a dynamic environment 105 having a plurality of conditions in response to situations where multiple actions are required. In one aspect, the controller 100: 1) divides a plurality of conditions into a number of subsets including a first subset; 2) receives at least one input signal 111 representing at least one monitored condition among the plurality of conditions, and processes the at least one input signal to determine whether at least one condition of the first subset is satisfied, thereby evaluating the first subset of the plurality of conditions; and 3) is configured to provide first control information 113 representing at least one first action among the plurality of actions when at least one condition of the first subset is satisfied. As shown in FIG. 1A and further discussed below, in one aspect, the at least one input signal 111 may be provided to the controller 110 from one or more of a number of processing resources of the SPRe circuit 115. Similarly, the first control information 113 provided by the controller 110 may function as an input to one or more of a number of processing resources of the SPRe circuit 115.

[0017] Controller 110 can be implemented as a microprocessor, microcontroller, programmable logic controller, field programmable gate array, digital signal processor, application specific integrated circuit, logic circuit, or some combination thereof. In some implementations, controller 110 can be implemented as a networking component that generally operates on signals (e.g., Ethernet PHY, router, etc.). Controller 110 may also implement a signal isolation function (e.g., using magnetic, capacitive coupling, and / or optical isolators, not shown).

[0018] Regarding the flexible input / output circuit 120 of the control system 102, an exemplary implementation of the flexible input / output circuit 120 can be found in U.S. Patent No. 11,182,326, entitled "Input / Output Apparatus and Methods for Monitoring and / or Controlling Dynamic Environments," issued on November 23, 2021, which patent is hereby incorporated by reference in its entirety. Generally, the flexible input / output circuit 120 is communicatively coupled to the controller 110 to configure and support a first input / output (I / O) signaling channel 122A to facilitate communication between the flexible input / output circuit and a first device 170A among a plurality of devices 170 within the dynamic environment 105. The flexible input / output circuit 120 also configures and supports a second input / output (I / O) signaling channel 122B to facilitate communication between the flexible input / output circuit and a second device 170B among the plurality of devices 170 within the dynamic environment 105. In one aspect, the flexible input / output circuit 120 dynamically configures each of the first I / O signaling channel 122A and the second I / O signaling channel 122B based on at least one programming input 119 provided by the controller to support transmission and / or reception of single-ended digital and analog signaling types and / or differential digital and analog signaling types. For simplicity in FIG. 1A, only two I / O signaling channels 122A and 122B are shown, but of course, as contemplated in U.S. Patent No. 11,182,326 and as shown in FIG. 1B contemplated below, the flexible input / output circuit 120 may configure and support additional signaling channels to transmit and / or receive various analog and digital signal types.

[0019] The control system 102 shown in FIG. 1A also includes a signal processing resource (SPRe) circuit 115 communicatively coupled to and disposed between a controller 110 and a flexible input / output circuit 120. As will be discussed in more detail below, examples of signal processing and signal generation functions that may be performed by the SPRe circuit 115 in relation to signals or other information received from the controller 110 as well as signals or other information received from the flexible input / output circuit 120 include, but are not limited to, analog filtering; digital filtering; frequency and / or phase detection; normalization, scaling, and / or other transformations (e.g., via one or more look-up tables or “LUTs”); digital signal generation; and analog signal generation.

[0020] In various aspects, the SPRe circuit 115 can be specifically configured by the controller 110 to perform various signal processing and / or signal generation functions, and further, the controller 110 may also trigger the operation of the SPRe circuits 115 or provide one or more signals that are themselves processed by the SPRe circuit 115 (e.g., for ultimate transmission via the flexible input / output circuit 120 to one or more devices 170 within the dynamic environment 105). Similarly, the SPRe circuit 115 may receive one or more signals from the flexible input / output circuit 120 (which signals are, in a first instance, provided to the flexible input / output circuit by one or more devices 170 within the dynamic environment 105), the SPRe circuit 115 can process one or more signals received from the flexible input / output circuit 120 (in some instances, at least in part based on a particular configuration of the SPRe circuit 115 by the controller 110), and then transmit the processed signals to the controller 110.

[0021] As shown in FIG. 1A, the SPRe circuit 115 includes a first processing resource 115A for processing a first signal 117A transmitted to or received from a first I / O signaling channel 122A via a flexible input / output circuit 120. The SPRe circuit 115 further includes a second processing resource 115B for processing a second signal 117B transmitted to or received from the first I / O signaling channel 122A or a second I / O signaling channel 122B via the flexible input / output circuit 120. Each of the processing resources 115A and 115B of the SPRe circuit 115 may be specifically configured at a given time (e.g., by the controller 110) to perform some type of signal processing or signal generation on a signal provided to the SPRe circuit by either the controller 110 or the flexible input / output circuit 120.

[0022] As also shown in FIG. 1A, one or both of the first processing resource 115A and the second processing resource 115B of the SPRe circuit 115 provide at least one input signal 111 representing at least one monitored condition of a plurality of conditions within the dynamic environment 105 to the controller 110. In another aspect, at least one of the first processing resource 115A or the second processing resource 115B receives from the controller 110 first control information 113 representing at least one first action of a plurality of actions, and processes at least one of the first signal 117A or the second signal 117B based at least in part on the received first control information 113. As noted above, of course, the first control information 113 provided by the controller 110 may include configuration information for a given processing resource (e.g., for configuring a given processing resource to perform a particular signal processing or signal generation function), and additionally or alternatively, the first control information 113 provided by the controller 110 may include one or more signals that are themselves processed by one or more processing resources of the SPRe circuit or trigger the operation of one or more processing resources (e.g., in some cases, in accordance with configuration information previously provided to the processing resources).

[0023] In yet another aspect of the SPRe circuit 115 shown in FIG. 1A, the second processing resource 115B receives at least one SPRe control signal 114 (also referred to herein as the “master” signal) from the first processing resource 115A and processes a second signal 117B based at least in part on the SPRe control signal 114. In various aspects, the second processing resource 115B may use the first control information 113 and the SPRe control signal 114 for configuring a signal processing and / or signal generation function, may be used to configure one of the first control information 113 and the SPRe control signal 114 and the other for triggering the operation of the second processing resource 115B (e.g., for configuring the first control information 113 and for triggering the operation of the SPRe control signal 114), or may use only the SPRe control signal 114 for at least one of configuring or triggering the operation of the second processing resource 115B.

[0024] Accordingly, it may be understood from the foregoing that the first processing resource of the SPRe circuit 115 may be configured by the controller 110 for a first type of signal processing or signal generation on a first signal (received from the controller 110 or from the flexible input / output circuit 120), and that the second processing resource of the SPRe circuit 115 may be configured by the controller 110 for a second type of signal processing or signal generation on the first signal and / or a second signal received from the controller 110 or the flexible input / output circuit 120. Further, the first processing resource of the SPRe circuit 115 may alternatively or additionally configure and / or trigger the operation of the second processing resource of the SPRe circuit 115 to perform a second type of signal processing or signal generation, or yet another type of signal processing or signal generation, on the first signal, the second signal, and / or a third signal received from the controller of the flexible input / output circuit.

[0025] From the foregoing points, it is of course natural that each processing resource of the SPRe circuit 115 shown in FIG. 1A is related not only to the "outbound" signals (from the controller 110 to the SPRe circuit 115, then to the flexible input / output circuit 120, and then to one or more devices 170 within the dynamic environment 105), but also to the "inbound" signals (from one or more devices 170 within the dynamic environment 105 to the controller 110, via the flexible input / output circuit 120 and the SPRe circuit 115), and may be flexibly and dynamically configured (and reconfigured over time) to perform some type of signal processing and / or signal generation. In addition, it is of course natural that at least a first processing resource of the SPRe circuit 115 communicates directly with one or more other processing resources of the SPRe circuit 115 and, in some cases, configures and / or triggers the operation of one or more other processing resources, at least in part based on the processing or generation of signals by the first processing resource. In this way, a number of processing resources of the SPRe circuit 115 can be employed in tandem (e.g., simultaneously and / or sequentially, as in an "cascade" of events and actions) to perform the corresponding type of signal processing and / or signal generation with little or no intervention or configuration by the controller 110 (or any significant use of the controller 110's processing bandwidth).

[0026] The foregoing concept of one processing resource of the SPRe circuit 115 having the ability to dynamically configure and / or trigger the operation of one or more other processing resources of the SPRe circuit 115 is referred to herein as "cross-communication between multiple processing resources". Thereby, the SPRe circuit 115 can undertake signal processing tasks that would otherwise be handled by the controller 110, freeing the controller 110 to participate in other system management and control tasks. In various aspects, offloading of the signal processing bandwidth from the controller 110 to the SPRe circuit 115, and the speed of the SPRe circuit 115, can significantly reduce the overall latency of the sensing and control system 100.

[0027] The inventors have adopted this concept of cross-communication among multiple processing resources of the SPRe circuit 115 to be able to dynamically reconfigure each processing resource of the SPRe circuit, whereby a given processing resource acts as the "master" processing resource, and one or more other processing resources act as "slave" processing resources at a given time, and then the respective roles of the master and slave processing resources can be reconfigured later (thereby the master becomes the slave, or vice versa), and further recognized and understood. In one example to be further considered below, the first processing resource of the SPRe circuit 115 is configured to process one or more incoming signals from the first device 170A (e.g., the first stepper motor) in the dynamic environment 105 via the flexible input / output circuit 120. In this example, the first stepper motor provides the signal 122A to the flexible input / output circuit 120 upon completion of a specific task or upon reaching a certain state (e.g., completion of N shaft rotations). When the first processing resource 115A of the SPRe circuit 115 receives the signal provided by the first stepper motor indicating completion of a specific task / reaching a certain state, the first processing resource triggers the operation of the second processing resource 115B, which provides the signal 117B to the flexible input / output circuit 120 and then is configured to provide the signal 122B to the second device 170B (e.g., the second stepper motor) in the dynamic environment 105 to operate in a specific manner (e.g., increase the motor speed to 2000 RPM). In this way, the first processing resource 115A is the "master", and the second processing resource 115B is the "slave" in that the second stepper motor operates only after the first stepper motor has completed a specific task or reached a certain state.

[0028] At a later time, one or both of the first and second processing resources of the SPRe circuit 115 may be reconfigured (e.g., by the controller 110), whereby the second processing resource expects input from the second stepper motor and / or another device within the dynamic environment 105, and upon receipt of this new input, triggers the operation of the first processing resource or yet another processing resource to provide a signal to the first stepper motor or yet another device within the dynamic environment. In this way, the second processing resource 115B becomes the "master" that reconfigures and / or triggers the operation of another processing resource of the SPRe circuit 115.

[0029] Therefore, it may be readily understood that by providing flexible, dynamic, bidirectional, and reconfigurable signal processing and signal generation, the SPRe circuit 115 provides an advanced architecture with rich functionality for extending the control system for a dynamic environment.

[0030] In some implementations, as described in further detail below, each processing resource of the SPRe circuit can be implemented, at least in part, using dedicated circuitry (e.g., logic circuitry, code implemented on the gates of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a universal asynchronous receiver / transmitter (UART), a digital signal processor (DSP), etc., or some combination of such dedicated circuitry), such that the SPRe circuit can perform signal processing and / or signal generation tasks faster than the tasks that would otherwise be performed by the controller to which the SPRe circuit is coupled.

[0031] Figure 1B illustrates further details of the sensing and control system 100 shown in Figure 1A, specifically, a plurality of connected devices 170, which can include any subset or combination of one or more controlled devices 140, 142 (e.g., motors, conveyor belts, robotic arms, lighting fixtures, combinations of such devices), one or more imaging devices 150, 152 (e.g., photographic cameras, CCD imaging arrays, CMOS imaging arrays, combinations of such devices), and one or more sensors 160, 162 (e.g., temperature sensors, counters, rotary encoders, tachometers, pressure sensors, combinations of such devices). One or more of the connected devices 170 can be controlled by the controller 110 (e.g., the controlled device 140 or the imaging device 150 responds to control signals transmitted to the device to be controlled by the controller 110). Additionally, the controller 110 can receive information provided by signals transmitted from one or more of the connected devices 170, and may or may not respond thereto.

[0032] As described above, the flexible I / O circuit 120 facilitates communication between the controller 110 and the connected devices 170 (e.g., one or more controlled devices 140, 142, one or more cameras 150, 152, and / or one or more sensors 160, 162) operating within the dynamic environment 105. As shown in FIG. 1B, the flexible I / O circuit 120 may include a plurality of terminals 125 (connected to signaling channels within the flexible I / O circuit 120), each of which can be connected to a device within the dynamic environment 105. Each of the signaling channels can be configured to transmit signals from the corresponding terminal 125 and / or receive signals at the corresponding terminal 125 by the controller 110 (e.g., via the programming signal 119). Further, each signaling channel can be configured by the controller 110 to support two or more types of signaling protocols (e.g., current source analog signaling or differential analog signaling, single-ended digital signaling, or differential digital signaling, etc.). The signaling channel can include a plurality of circuit components within the flexible I / O circuit 120 and one or two links (e.g., wires) connected to the terminal 125 to transmit signals encoding information and / or at least one command. By using the flexible I / O circuit 120, the amount of interface components and cables between the controller 110 and the connected devices 170 within the dynamic environment 105 can be significantly reduced compared to conventional control systems.

[0033] Communication through a signaling channel between the flexible I / O circuit 120 (and / or the controller 110) and a connected device within the dynamic environment 105 can be in half-duplex mode for a portion of the connected device 170 that supports half-duplex communication. In some implementations, two signaling channels are connected from the flexible I / O circuit 120 to the connected device, and one signaling channel is used as a downlink to the connected device (from the controller 110 to the connected device), and the other signaling channel is used as an uplink to establish full-duplex communication with a connected device that supports full-duplex communication, for example, by transmitting data to the controller 110. In some cases, the signaling channels of the flexible I / O circuit 120 may be configured to implement more than one type of signaling simultaneously (e.g., providing current to a thermistor and reporting temperature from the thermistor while sampling voltage on the same channel to provide current through the signaling channel).

[0034] II. Signal Processing Resource Circuit Coupled to a Controller and Flexible I / O Circuit FIG. 2 illustrates, by way of one invention implementation, further details of one non-limiting example of the SPRe circuit 115 that can be communicatively coupled to the controller 110 and the flexible I / O circuit 120. The example of FIG. 2 shows an SPRe circuit that includes two processing resources, each dedicated to a particular direction of signal propagation. However, as is natural, as discussed above, a given processing resource of the SPRe circuit 115 need not be limited to processing signals propagating in a given direction within the sensing and control system, and the particular example discussed below in relation to FIG. 2 is provided primarily for the purpose of exemplifying a part of some notable concept underlying the signal processing and signal generation functions of the SPRe circuit 115.

[0035] More specifically, the SPRe circuit 115 shown in FIG. 2 includes a pre-processor 210 and a post-processor 220 for at least one signaling channel of the flexible I / O circuit 120, which is used to communicate with one or more connected devices 170 (e.g., one or more controlled devices, sensors, and / or cameras) within the dynamic environment 105. Generally, the pre-processor 210 can implement a function to process signals coming from the flexible I / O circuit 120 on the signaling channel (e.g., data from a sensor 160 connected to the signaling channel) and then transmit the result of the processed signal to the controller 110. The post-processor 220 can implement a function to process signals coming from the controller 110 and then transmit the result of the processed signal to the flexible I / O circuit 120 (e.g., output a waveform for controlling a motor). The flexible I / O circuit 120 can then transmit the result of the processed signal to the device 140 to be controlled via the corresponding signaling channel (using the signaling type supported by the device 140 to be controlled).

[0036] The drawing of FIG. 2 illustrates a preprocessor 210 and a postprocessor 220 for only one flexible I / O channel. In an exemplary implementation, the flexible I / O circuit 120 can have up to 8 or 16 flexible I / O signaling channels, each for communicating with one or more connected devices 170 within the dynamic environment 105, and each signaling channel can include at least one preprocessor 210 (and its associated hardware and software as illustrated in FIG. 2) and / or at least one postprocessor 220 (and its associated hardware and software as well as its associated hardware and software as illustrated in FIG. 2). However, the flexible I / O circuit 120 can be implemented using more or fewer flexible I / O channels, at least some of which may include or communicate with the preprocessor 210 and / or the postprocessor 220. The SPRe circuit 115 can be implemented using other processors (which may perform both preprocessing and postprocessing functions) as illustrated in FIG. 3.

[0037] Referring back to FIG. 2, the SPRe circuit 115 can be implemented at least in part using digital and / or analog circuit components (e.g., a frequency counter, a digital filter, a digital signal generator, an analog filter, an analog signal generator, etc., or some combination thereof). For example, the preprocessor 210 can include a frequency counter for determining the frequency of a received digital or analog signal.

[0038] In some cases, the SPRe circuit 115 can be implemented at least in part using machine language executed on the circuitry of at least one processor. Such processors can be microprocessors, microcontrollers, field programmable gate arrays (FPGAs), programmable logic controllers (PLCs), application specific integrated circuits (ASICs), digital signal processors (DSPs), custom programmable digital and / or analog circuitry, or some combination thereof. For example, the machine language executed on a digital signal processor can perform a filtering function on sampled analog signals received from the flexible I / O circuit 120.

[0039] By implementing the SPRe circuit 115 using dedicated circuitry, the SPRe circuit can perform signal processing tasks more quickly than would be possible for the controller 110 to process them. Thus, the SPRe circuit can offload processing tasks from the controller 110 and additionally increase the processing speed of the offloaded tasks.

[0040] In some cases, one or more processors used to implement the preprocessor or postprocessor of the SPRe circuit 115 can be shared, i.e., the selected processor(s) may be adapted to perform a portion of the functions of the SPRe circuit, a portion of the functions of the controller 110, and / or a portion of the functions of the flexible I / O circuit 120. In some implementations, the functions of the SPRe circuit 115 can be implemented in part by code executed on one or more processors of the controller 110 and in part by code executed on one or more processors of the flexible I / O circuit 120.

[0041] II.A. Preprocessor To operate on the signals received from the Flexible I / O Circuit 120, the Preprocessor 210 can include one or more frequency counters 215, one or more digital filters 211, one or more analog filters 216, one or more prescalers 219, and / or one or more look-up tables (LUTs) 218. The Preprocessor 210 may also receive digital signals from the Flexible I / O Circuit 120, which may or may not be processed by the Preprocessor 210. The unprocessed signals can be passed to the Controller 110 as digital inputs for further processing by the controller (as indicated by the dashed signal path within the preprocessor in FIG. 2). The results of the processed signals (e.g., a filtered version of the received signal or a value calculated based on the received signal) can be sent to the Controller 110, freeing the controller from the corresponding signal processing tasks (e.g., digital filtering, arithmetic) performed by the Preprocessor 210.

[0042] Referring to the point in time with respect to FIG. 1B, the digital signals received by the preprocessor can originate from one or more of the connected devices 170 (e.g., sensors 160, 162, cameras 150, 152, or devices 140, 142 to be controlled) within the dynamic environment 105. The received digital signal may be in its original form (1) transmitted by the connected device 140 and passed by the Flexible I / O Circuit 120, or (2) converted (by the Flexible I / O Circuit 120) from a first signaling type (e.g., analog, single-ended) received by the Flexible I / O Circuit 120 to a different second signaling type (e.g., digital TLT signal) provided to the Preprocessor 210.

[0043] Referring again to FIG. 2, in some cases, the digital signals received by the preprocessor 210 can be filtered by one or more digital filters 211 implemented within the preprocessor 210. Additionally or alternatively, the received digital signals can be provided to a frequency counter 215 or a phase detector (not shown in FIG. 2) implemented within the preprocessor 210 to detect at least one of the frequency of the digital signal, a change in frequency, the phase, or a change in phase. The detection of a change in frequency and / or phase may be for the purpose of signal demodulation. The outputs from the frequency counter and the phase detector can be provided to the controller 110 as input parameters for further processing by the controller 110.

[0044] Implementing digital filtering, frequency detection, and / or phase detection using dedicated circuitry between the flexible I / O circuit 120 and the controller 110 can offload such signal processing tasks from the controller 110 and enable the controller 110 to use more processing time to participate in overall system control tasks. In addition to increasing the speed of processing of the signals received from the flexible I / O circuit 120 and reducing the workload on the controller 110, the accuracy of the signal processing performed by the preprocessor 210 can be improved (e.g., for high-frequency signals) over the accuracy achievable using the controller 110 when the controller is tasked with other signal processing, commands, and control actions.

[0045] As described above, the pre-processor 210 can receive the analog signals sampled and digitized from the flexible I / O circuit 120 (shown as "analog input values in digital form" in FIG. 2). The received digitized analog signals are transferred to the controller 110 as analog inputs for further processing by the controller, either filtered or unfiltered digitized analog signals. Before that, they may or may not be filtered by at least one "analog" filter 216 implemented within the pre-processor 210. The analog filter 216 can be implemented in software code and operate on the digital signal representation of the analog signals received by the flexible I / O circuit 120 from one of the connected devices 170.

[0046] In some implementations, the flexible I / O circuit 120 can digitize one or more analog signals (such as analog waveforms) and / or one or more analog values (such as voltage or current readings) received from the connected device 140 within the dynamic environment 105 as illustrated in the exemplary implementations of FIGS. 2 and 3, and provide one or more corresponding digitized representations of the analog signals and / or analog values to the pre-processor 210 (displayed as analog input values in digital form). In such cases, the "analog filter" can be implemented in code to operate on the digitized signals. For example, the analog filter may calculate a moving average of the received digital values, where the average is based on N recently received digital values (where N is a positive integer). Other functions can be implemented using the "analog filter" (such as threshold detection, differentiation, elimination of values exceeding an acceptable deviation from the moving average, hysteresis, etc.). The connected device 140 can be communicatively coupled to the flexible I / O circuit 120 using two or more signaling channels to communicate two or more analog signals and / or two or more analog values.

[0047] The components of the preprocessor 210 (and the postprocessor 220) can be initialized by the controller 110 when use is started using configuration values (displayed as the processor configuration in FIGS. 2 and 3). Some of the configuration values that can be issued by the controller 110 to configure the "analog filter" 216 are the time constant τ , the deviation value E, the threshold value T, and the hysteresis H. The time constant τ can be expressed in time units (e.g., digital clock cycles) and can cover the time for which the input samples are averaged to produce a moving average of the input samples. The moving average can be provided to the controller 110 as a response to a query from the controller 110 for the detected input voltage or current on the corresponding channel of the flexible I / O circuit 120. The time constant value affects the weight that each new sample has on the moving average value. The time constant can be implemented using the digital counter of the analog filter 216, and its value can be updated frequently (e.g., every 8 μs in some implementations of the control system 102) at each sample time.

[0048] The deviation E can be the full-scale percentage by which a new sample is allowed to deviate from the current moving average value included in the cumulative total. Values exceeding the deviation limit can be excluded by the preprocessor 210. Selecting the deviation value E facilitates adjustment of the rejection of short transient noise spikes.

[0049] The threshold value T can be implemented as a value that, when exceeded, triggers interrupt-driven delivery of the input value to the controller 110 by the preprocessor 210. Interrupt-driven delivery can cause the controller 110 to take an action (which can be immediate) in response to the detected exceedance of the threshold value T by the preprocessor.

[0050] Hysteresis H can represent the deviation from the last moving average reported via an interrupt (e.g., in response to a threshold crossing) before a new interrupt-driven delivery is initiated via the pre-processor 210. For example, if the moving average value is typically about 50 and the threshold T is set to 80, a temporary increase in the moving average value to about 90 will be reported to the controller 110 by the pre-processor 210 using interrupt-driven delivery. When the hysteresis H is set to 30, the current moving average (about 90 in this example) must change by at least 30 before the new current moving average is reported to the controller 110 by the pre-processor 210 using interrupt-driven delivery.

[0051] In some implementations, the flexible I / O circuit 120 can provide the raw analog signal to the pre-processor 210, and the analog filter 216 can be implemented using circuit components (e.g., resistors, capacitors, inductors, op-amps, etc.) to form any suitable analog filter or analog function 217 (e.g., integrator, differentiator, threshold detector, etc.). Then, the analog-to-digital conversion 213 can be implemented after the analog filter (e.g., using the A / D converter within the pre-processor 210) before the filtered signal is provided to the controller 110.

[0052] In some cases, the output from the analog filter (or the A / D converter after the analog filter), or the output received directly from the flexible I / O circuit 120, can be provided to one or more look-up tables (LUTs) 218 for further signal processing. The LUT 218 can use each received value to address an entry in the table and read out the corresponding value passed to the controller 110 instead of or in addition to the value received by the LUT 218. The corresponding value passed to the controller can provide a more accurate representation than the received value of the physical parameter within the dynamic environment 105. The corresponding value may correct for system and / or device errors such as non-linear response by the device. Alternatively, the output from the analog filter (or A / D converter) can be provided directly to the controller 110 for further processing.

[0053] An exemplary application where benefits can be gained from the use of the LUT 218 is when the sensor 160 comprises a thermistor for sensing temperature within the dynamic environment 105. The thermistor typically has a non-linear behavior (resistance as a function of temperature), which is shown for a typical thermistor in FIG. 4 (the curve labeled "measured values"). Such a curve can be approximated by a mathematical function (the curve labeled "fit"), but the mathematical approximation can introduce an error of up to 7% in temperature when converting the resistance value sensed by the thermistor. The use of the LUT 218 to map the resistance value detected according to the actual response curve of the thermistor to temperature can result in a significantly lower error in the sensed temperature (e.g., less than 0.5 degrees Fahrenheit throughout the full operating range of the thermistor compared to several degrees throughout a portion of the full operating range of the thermistor of up to 200 degrees Fahrenheit maximum).

[0054] In some cases, the pre-processor 210 can include one or more scalers 219 that operate on the data received from the flexible I / O circuit 120. The scaler 219 may scale the received data before transmitting the scaled data to the controller 110. The scaling can change the data so as to cover the entire range of data values supported by the controller 110.

[0055] The components of the pre-processor 210 can be configured at any time by the controller 110 via one or more pre-processor configuration communication lines shown in FIG. 2 as connections to the LUT 218, the analog filter 216, and the digital filter 211. For example, the entries in the LUT 218 can be written to and / or rewritten by the controller 110, which can transmit new configuration data (new LUT entries) via the pre-processor configuration lines. Filter settings and other configuration values can also be set and revised by transmitting data via the pre-processor configuration lines.

[0056] The functionality of the pre-processor 210 may be implemented in other ways, as illustrated in FIG. 3 and further described below. One or more pre-processors 210 may be assigned by the controller 110 to the signaling channel of the flexible I / O circuit 120. Different types (e.g., the type illustrated in FIG. 2 and the type illustrated in FIG. 3) of pre-processors 210 may be assigned to a single signaling channel if the functionality of the signaling channel changes during operation of the control system 102. For example, the controller 110 may reassign the SPRe circuit, such that during a first period of operation of the control system 100, the first SPRe circuit 115 is assigned to the signaling channel, and then the controller may remove the assigned first SPRe circuit 115 and assign a second SPRe circuit 115 having a different pre-processor type to the signaling channel. There may be fewer, the same number, or more pre-processors 210 within the control system 102 available for assignment to the signaling channel of the flexible I / O circuit 120 than there are signaling channels within the flexible I / O circuit 120.

[0057] II.B. Postprocessor Referring again to FIG. 2, the post-processor 220 can receive a digital output or an “analog” output (in digital form) from the controller 110, process the digital or analog output, and provide the processed and / or unprocessed digital or analog output to the flexible I / O circuit 120. The flexible I / O circuit 120 can then pass the output to one or more connected devices 170 within the dynamic environment 105. The post-processing capabilities for “analog” and digital signaling types can be present for each channel of the flexible I / O circuit 120 and can be selected and / or configured at any time via the controller 110 (e.g., based on user input when initially configuring the control system 102 to operate with the connected devices 170 within the dynamic environment 105, or based on information received from at least one device within the dynamic environment 105 via the flexible I / O circuit 120).

[0058] In some cases, the analog output received from the controller 110 can be received from the controller as a digital signal that is intended to be converted to an analog signal (e.g., by a digital-to-analog converter) prior to transmission from the flexible I / O circuit 120 so that the analog signal is delivered to a device within the dynamic environment 105 to which the analog signal is communicatively coupled to the signaling channel. The D / A conversion may be performed, for example, in the flexible I / O circuit 120.

[0059] For the exemplary implementation of FIG. 2, the post-processor 220 can include one or more digital signal generators 225 and one or more “analog” signal generators 227, along with input data buffers 232, 234 and output data buffers 242, 244. The input data buffers 232, 234 arranged to receive information from the controller 110 can queue a number of commands from the controller 110 and thereby enable the controller 110 to be released for other tasks to participate. The input data buffers 232, 234 can be, for example, first-in, first-out (FIFO) data buffers.

[0060] The output data buffers 242, 244 are arranged to pass information to the flexible I / O circuit 120 and can also be FIFO data buffers. The output data buffers 242, 244 can enable signals generated from the digital signal generator and / or the analog signal generator to be queued. These buffers can also be used as completion buffers that communicate with the controller 110 to notify the controller when a particular signal has been (or is being) transmitted to the flexible I / O circuit 120.

[0061] The post-processor 220 also includes at least a first signal path for digital output provided to the flexible I / O circuit 120 and / or at least a second signal path for analog output provided to the flexible I / O circuit 120. Signal buffering may or may not be used on these first and second signal paths. Signal processing (e.g., filtering) may or may not be used on these first and second signal paths. In some cases, digital and / or analog signals from the controller 110 can pass through the post-processor 220 and be provided unprocessed to the flexible I / O circuit 120.

[0062] The digital signal generator 225 can be configured to output a binary waveform that is passed to the flexible I / O circuit 120 and then transmitted to at least one connected device 140 within the dynamic environment 105. An exemplary binary waveform can be, for example, a waveform used to control a stepper motor or other servo motor. Parameters for the digital waveform can be queued in the input data buffer 232 and then transmitted to the digital signal generator 225, and can be specified by the controller 110 as a post-processor configuration. Such a post-processor configuration can include characteristics of the digital waveform to be generated (e.g., conditions under which signal generation should start, frequency, start phase, end phase, duration, amplitude, duty cycle, rate of change of the waveform from the start state to the final state, conditions under which signal generation should end). In some cases, the digital signal generator 225 can be implemented using, for example, an FPGA, a DSP, and / or memory and logic gates to access memory.

[0063] The "analog" signal generator 227 can be configured to output a digital signal that is passed to the flexible I / O circuit 120, converted to an analog signal at some point after being generated by the analog signal generator 227, and then transmitted to at least one device 140 within the dynamic environment 105. The digital signal output by the analog signal generator can include a series of analog signal values (calculated or generated by the post-processor 220) that are digitally represented within the signal that is transmitted to the flexible I / O circuit 120. The conversion to an analog waveform may be performed by the flexible I / O circuit 120 or by a D / A converter prior to the flexible I / O circuit 120. Exemplary analog waveforms (after D / A conversion) can include sine waves, triangular waves, or sawtooth waves, voltage or current ramps, etc. The parameters of the analog waveform (which will be output from the flexible I / O circuit 120) can be queued in the input data buffer 234 and then specified by the controller 110 via a post-processor configuration that can be transmitted to the analog signal generator 227. Such a post-processor configuration can include the characteristics of the analog waveform to be generated (e.g., the conditions under which signal generation should start, frequency, start phase, end phase, duration, amplitude, duty cycle, the rate of change of the waveform from the start state to the final state, the conditions under which signal generation should end). The analog signal generator 227 can be implemented, for example, using an FPGA, a DSP, and / or memory and logic gates to access memory.

[0064] In some implementations, the analog signal generator 227 can receive a certain number of input parameters from the controller 110 that determines the analog waveform and executes code on at least one processor to generate the corresponding digital signal based on the received input parameters as described above. The digital signal includes a series of digital-represented analog values and is output to the flexible I / O circuit 120 where the desired analog signal will be output. For example, one or more of the following parameters can be received by the analog signal generator 227 as one or more configuration inputs from the controller 110. Amplitude - Specifies the amplitude of the generated analog waveform as a percentage of the full - scale capability of the output. Period - Specifies the time required for a complete cycle of the desired waveform. Start Phase - Specifies the starting transition of the generated waveform. This can be implemented as the location (address or entry) in the LUT that stores the series of data values representing the waveform. The address can output the value of the waveform where the waveform should start (corresponding to the selected start phase). The start phase may be specified by the user in terms of degrees, minutes, and seconds, or in some scale of radians (e.g., milliradians, micro - radians). End Phase / Duration - Specifies the end phase of the generated waveform. This can be implemented as the location (address or entry) in the waveform LUT of the value where the waveform should end. This configuration input from the controller may include a duration code that specifies the number of cycles of the waveform to be output before ending at the end phase or specifies the continuous output of the waveform. Wave Count - Specifies the number of complete cycles of the waveform to be output. Master channel - Identifies another channel of the flexible I / O circuit 120 whose activity enables the action of the current channel of the flexible I / O circuit 120 from which the signal is output. When identified, an event on the master channel (e.g., threshold exceedance, count value, etc.) activates the output of the signal from the current channel (e.g., starts the output of a waveform at a specified start phase). The start phase can then determine the relative phase of the output from the current channel with respect to the activation event on the master channel. Waveform LUT - Can identify which of a number of LUTs to use to generate a waveform. The post-processor can include different LUTs (not shown in FIG. 2) for different types of waveforms (e.g., sine wave, square, triangle, etc.). Forming the output waveform using a LUT can provide higher accuracy in implementing a sine wave (and other waveforms) than might be achieved in another way without using a LUT, in addition to making it considerably easier to implement other types of waveforms. Further, the LUT can be rewritten with values representing any desired waveform.

[0065] The types of motors that can be controlled by the SPRe circuit 115 include not only various types of servo motors, but also non-servo AC motors and DC motors. A servo motor refers to a motor implemented within a feedback control loop in order to achieve or maintain a specified location (rotation angle) or speed. The motor inside the loop can be any controllable motor such as a stepper motor or a switched reluctance motor (SRM). The control of the motor can be by pulse width modulation (PWM) or by using a pulse train. The location and / or speed data for providing feedback information to the control loop can be provided from one or more encoders and / or resolvers mechanically coupled to the motor being controlled or coupled to a rotating shaft driven by the motor. In some cases, the position sensor and / or rotation sensor can be implemented using a synchro (also called a selsyn), resolver (4-pole synchro), or potentiometer.

[0066] The switched reluctance motor (SRM) can be either an outrunner (where the fixed magnets on the rotor surround the drive poles on the stator) or an inrunner (where the stationary poles, the stator, surround the static permanent magnets on the inner rotor). The switching network driving the stator of the SRM is often driven in quadrature phases so that the duty cycle of each phase can be driven at a convenient 50% duty cycle.

[0067] The functionality of the post-processor 220 can be implemented in other ways, as illustrated in FIG. 3 and further described below. One or more post-processors 220 can be assigned to the signaling channel of the flexible I / O circuit 120 via the controller 110. Different types of post-processors 220 (e.g., different types as illustrated in FIGS. 2 and 3) can be assigned to a single signaling channel if the functionality of the signaling channel changes during operation of the control system 102. One way to change the type and / or functionality of the post-processor 220 (and / or pre-processor 210) is through configuration settings. For example, different configuration settings can be loaded into at least one of the buffers 232, 234, and each configuration setting can define the type and / or functionality of the post-processor 220. The configuration settings from the buffer can be activated in real time by receiving the first control information 113 from the controller 110 and / or by receiving the SPRe control signal 114 (also referred to as the "master signal") from one of the processors of the SPRe circuit to another processor of the SPRe circuit (loaded onto the SPRe 115 to configure the SPRe circuit for operation). In this way, different configuration settings can be switched during operation of the control system 100. There can be fewer, the same number, or more post-processors 220 within the control system 102 available for assignment to the signaling channel of the flexible I / O circuit 120 than there are signaling channels within the flexible I / O circuit 120.

[0068] II.B. Additional Implementations of Signal Processing Resource Circuit FIG. 3 illustrates an additional embodiment of the SPRe circuit 115 for at least one signaling channel of the flexible I / O circuit 120 that can be implemented within the control system of FIG. 1B. In this implementation, the SPRe circuit 115 can convert the signaling type to enable communication between the controller 110 and one or more connected devices 170 within the dynamic environment 105 (e.g., serialize a control signal output as an ASCII signal in a parallel format), and includes a universal asynchronous receiver / transmitter (UART) processor 260. The UART processor 260 can be implemented, for example, as a chip, or in machine language executed on an FPGA, and can be assigned to a signaling channel of the flexible I / O circuit 120. The UART processor 260 can include FIFO data buffers 261, 262 on an input signal path 212 and an output signal path 214, respectively, that communicatively couple the controller 110 and the flexible I / O circuit 120. The UART processor can implement a digital filter 263 and a deserializator 264 (for converting serial to parallel data transmission) on the input signal path 212, and can further implement a serializer 265 (for converting parallel to serial data transmission) on the output signal path 214. In this regard, the UART processor 260 implements both preprocessing and postprocessing functions to offload signal processing tasks from the controller 110.

[0069] The UART processor 260 can be reconfigured to handle conversions between three or more different signaling types, and the configuration of the UART processor for a particular signaling type can be set using parameters transmitted from the controller 110 to the UART processor 260 as the processor configuration shown in FIG. 3. Such configuration parameters can be associated with the particular signaling type for which the conversion occurs (e.g., baud rate, use of parity bits, start bits, stop bits, etc.).

[0070] The SPRe circuit 115 can alternatively or additionally include, for example, a resolver processor 222 for controlling a motor using a control loop within the dynamic environment 105. The resolver processor 222 can include an angle evaluator 250 adapted to interpret two signals from a resolver (which may be implemented as the sensor 160 within the dynamic environment 105). The two signals from the resolver (sensor 160) can be, for example, sine wave analog signals with different phases that together encode the rotational angle of the resolver's shaft. The two signals are received by the flexible I / O circuit 120 as analog signals and can be converted to digital signals (by the flexible I / O circuit 120 or by an A / D converter located between the flexible I / O circuit 120 and the angle evaluator 250) and provided to the angle evaluator 250 for processing. The angle evaluator 250 can process the two received digital signals (e.g., determine the phase difference between the two signals) and determine the angle of the resolver's shaft. The resolver processor 222 can output the calculated angle value of the resolver's shaft to the controller 110 as a digital data value. The resolver processor 222 can further output a series of digital values (shown in FIG. 3 as analog output values in digital form) that are converted to an analog sine waveform (by the flexible I / O circuit 120 or by a D / A converter located between the flexible I / O circuit 120 and the angle evaluator 250). For example, an analog waveform can be used to excite the resolver. The resolver processor can be reconfigured to handle different types of resolvers, and the configuration of the resolver processor can be set using parameters transmitted from the controller 110 to the resolver processor 222 as the processor configuration. Such configuration parameters may include the frequency and amplitude of the sine waveforms provided to and received from the resolver.According to some implementations, the resolver processor 222 and the angle evaluator 250 can be implemented, at least in part, using machine language executed on at least one FPGA or other processing device.

[0071] II.C. Additional Components of Signal Processing Resource Circuit In some implementations, the preprocessor 210 and / or the postprocessor 220 can include additional or alternative circuit components. For example, the preprocessor 210 and / or the postprocessor 220 can include a high-speed counter, with or without a comparison function. The use of the high-speed counter and comparison functionality can provide signal generation (e.g., start, stop) by one signal generator conditioned on the status of another signal generator. Such conditional operation can support the organized operation of multiple motors within the dynamic environment 105. The organized operation of the motors may be used for the organized multi-axis movement of a machine within the dynamic environment 105 (e.g., a robotic arm, a CNC machine, etc.).

[0072] The preprocessor 210 and / or the postprocessor 220 (or a processor implementing one or both of the preprocessor and postprocessor functions) can also include a dedicated comparator and channel memory. The dedicated comparator can detect significant changes in either or both of the analog and digital signals received from the flexible I / O circuit 120 and can trigger a specific entry on the event table of the controller 110. The event table can determine one or more actions to be taken in response to one or more detected conditions within the dynamic environment 105. The channel memory can be used for high-frequency sampling of the incoming analog signals received from the flexible I / O circuit 120.

[0073] Another component that can be included within the preprocessor 210 for each channel is the baud rate controller. This device can manage the delivery of signal values to the channel at a specified baud rate and character set. The baud rate controller can adapt the signaling to various communication protocols such as, but not limited to, CANBus, ProfiBus, or another protocol over RS485. An example of a device that can be used as the baud rate controller is the UART processor 260 illustrated in FIG. 3.

[0074] In FIG. 2, a plurality of components are shown for some of the components of the preprocessor 210 and the postprocessor 220. There can be one or more components for each channel of the flexible I / O circuit 120, and the components can be selected based on the configuration settings used to configure the SPRe circuit 115 for operation. For example, the SPRe circuit 115 can include different types of digital filters 211. The type of digital filter 211 can be selected for the SPRe circuit 115 by the "filter" configuration setting. The configuration settings for selecting the components (and for establishing the mode of operation of the SPRe circuit 115) may be instantiated by the controller 110 (e.g., at startup time during system operation, or on the fly). As further described below, the configuration settings for selecting the components can also be instantiated by another SPRe circuit 115 via the master input line 205.

[0075] In some cases, communication can be provided between the SPRe circuits 115 (affecting the operation of those components) across different signaling channels of the Flex I / O circuit 120. For example, a first SPRe circuit 115 assigned to a first signaling channel of the Flex I / O circuit can communicate with a second SPRe circuit 115 assigned to a second signaling channel of the Flex I / O circuit 120. The first SPRe circuit 115 can, for example, display the signal processing task status (e.g., idle, start, execute, complete) of the first SPRe circuit 115. In one embodiment, the status of the digital signal generator 225 and / or the analog signal generator 227 can communicate across the signaling channel to notify another SPRe circuit 115 when signal generation has started and / or stopped. Such cross-channel communication can enable an operating scenario where one signal generator for one signaling channel of the flexible I / O circuit 120 starts signal generation only after the completion of signal generation by another signal generator for another signaling channel in the post-processor 220. Cross-channel communication can also enable an operating scenario where signal generation is synchronized and occurs simultaneously for two or more signaling channels. As another way, or additionally, at least some of the components of the SPRe circuit 115 can communicate directly with the controller 110 (communication lines not shown in FIG. 2) to notify the controller 110 of the operating status of the components and / or directly receive configuration settings from the controller. Further, either the pre-processor configuration and post-processor configuration lines can include a FIFO buffer for queuing configuration settings to be transmitted to one or more components connected to the configuration line.The progress of these FIFOs (and the other FIFOs described above) may depend on the status of other channels of the flexible I / O circuit 120, the status of code executed on one or more processors of the control system 102 (e.g., the status of the SCORE program), and / or conditions occurring in machines that are controlled and / or monitored within the dynamic environment 105.

[0076] In some cases, the SPRe circuit 115 may involve more than three links to transmit signals and information between the SPRe circuit 115 and one of the connected devices 170. An example of this is shown in FIG. 3 for the resolver processor 222 (e.g., the resolver receives two analog signals and outputs one analog signal, with three links for exciting the resolver). In some implementations, two or more signaling channels of the flexible I / O circuit 120 can be connected to a single connected device to establish more than three links between the connected device and the SPRe circuit 115 and form a "signaling channel" for the connected device. In some cases, the flexible I / O circuit 120 can be modified to add additional signal paths for each signaling channel, and the terminals 125 of the flexible I / O circuit 120 can comprise multi-wire terminals including more than three wires for transmitting information and / or control signals, for example. Additional signal paths can be added to each signaling channel by duplicating the circuitry used for the existing signal paths within the flexible I / O circuit 120. Alternatively, a single signaling channel can be time-division multiplexed to establish two links on a single signaling channel.

[0077] III. Signal Negotiation According to some implementations, the control system 102 has the ability to negotiate and renegotiate signals with the connected device 170 within the dynamic environment 105. For example, the controller 110 may first communicate with the device 140 within the dynamic environment 105 according to a default communication protocol that uses a first signaling type. Once the communication is established, the device 140 may signal to the controller 110 a preferred signaling type that is different from the default signaling type. The controller 110 can then reconfigure the signaling channel by changing the configuration settings of the flexible I / O circuit 120 to continue communicating with the device 140 according to the preferred signaling type.

[0078] IV. Flexible Input / Output Circuit FIG. 5A is a circuit diagram for a flexible input / output circuit 120 that supports various types of single-ended digital and analog signaling types as well as various types of differential digital and analog signaling types. Aspects of this circuit are described in U.S. Patent No. 11,182,326, referenced above. The flexible I / O circuit 120 is adapted to convert a first control signal of a first signaling type (e.g., from the SPRe circuit 115) (e.g., a single-ended digital signal using a first logic high voltage) received into a second control signal of a second signaling type (e.g., a single-ended digital signal using a second logic high voltage different from the logic high voltage). The second signaling type may be supported by the connected devices 140, 150, 160, while the first signaling type is not supported. The flexible I / O circuit 120 can further convert a first data signal of a first signaling type received from the same or different connected devices into a second data signal of a second data signaling type supported by the controller (110).

[0079] As an example of signal conversion by the flexible I / O circuit 120 of FIG. 5A, a first signaling type having a first logic high voltage can be applied to a pin or terminal labeled DOUTP. This terminal can be connected to the digital output line from the SPRe circuit 115. The flexible I / O circuit includes an adjustable high-level logic driver 550 that can be implemented using a current mirror 552 and a relay driver 554. The current mirror 552 and the relay driver 554 are at any suitable voltage +V DC (coupled to the drain of transistor 584) can drive transistor 584 to switch to the signaling channel output (labeled IO in FIGS. 5A and 5B). In this way, the current mirror 552, the relay driver 554, and the applied voltage +V DC are supported by the connected devices 140, 150, 160 to which the signaling channel IO of the first digital signal type having the first logic high voltage received from the SPRe circuit 115 is connected thereto, for a second digital signal type having a second logic high voltage (+V DC determined by) can provide a conversion to.

[0080] The circuit of FIG. 5A further includes clamping a Zener diode D1 on the multiplexing chip 512 (between the chip supply and the signal input line to the chip). The clamping diode D1 can be used to implement a single-ended analog or single-ended digital signal signaling type while preventing overvoltage on the signal channel, which can cause an unwanted coupling of the signal to the non-selected port of the multiplexing chip 512.

[0081] FIG. 5B is a circuit diagram for a second implementation of the flexible input / output circuit 120 that can support various types of single-ended digital and analog signaling types as well as various types of differential digital signaling types. The circuit also includes a clamping diode D1 on its multiplexing chip 512.

[0082] V. Features of Control System Of course, the SPRe circuit 115 can provide several beneficial functions to the control system 102, some of which are described above. Such functions include the following. 1. Offloading signal processing and signal generation tasks from the controller 110, providing more time for the controller to perform system management and control tasks. 2. Increasing the speed of signal processing tasks using dedicated circuit components within the SPRe circuit 115. 3. Generation of digital or analog waveforms for controlling one or more motors and / or actuators without requiring the controller 110 to generate the waveforms. Instead, the controller 110 can output the waveform parameters used by the SPRe circuit 115 to generate the control waveforms. 4. Use of signal generators 225, 227 for signaling via frequency shift keying and / or phase shift keying. For example, the controller 110 can encode signals onto the outputs of the digital signal generator 225 (or analog signal generator 227) by repeatedly transmitting alternative values of the period or start phase to the selected signal generator using frequency shift or phase shift keying, respectively, to frequency shift or phase shift the output waveform and encode data bits. 5. Improvement in the accuracy of sensor data through the use of LUTs. 6. Implementing a proportional, integral, and derivative (PID) controller using the SPRe circuit 115 with feedback from the dynamic environment provided via the flexible I / O circuit 120. Logic (implemented in code or hardware) can be added to the SPRe circuit 115 to calculate the error between the setpoint and the measured process value (returned from sensors within the dynamic environment 105), and calculate the proportional, integral, and derivative terms for error correction.

[0083] VI. Conclusion Although various embodiments of the invention are described and illustrated herein, those skilled in the art will readily envision various other means and / or structures for performing the functions and / or obtaining one or more of the results and / or advantages described herein, and each of such variations and / or modifications is to be regarded as within the scope of the embodiments of the invention described herein. More generally, those skilled in the art will appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be illustrative, and that actual parameters, dimensions, materials, and / or configurations will depend on the particular application in which the teachings of the invention are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described herein. Accordingly, the foregoing embodiments are presented by way of example only, and within the scope of the appended claims and their equivalents, embodiments of the invention may be practiced otherwise than as specifically described and claimed. Embodiments of the invention disclosed herein are directed to each and every individual feature, system, article, material, kit, and / or method described herein. Additionally, any combination of two or more of such features, systems, articles, materials, kits, and / or methods is included within the scope of the invention disclosed herein if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent.

[0084] Also, various inventive concepts may be embodied as one or more methods, of which examples are provided. Acts performed as a part of the method may be ordered in any suitable manner. As a result, in exemplary embodiments, even though acts are shown as sequential acts, some acts may be performed concurrently, embodiments may be constructed in which acts are performed in a different order than illustrated, and still other embodiments may include acts that are repeated, omitted, or performed only once.

[0085] All definitions, as defined and used herein, are to be understood to control over dictionary definitions, definitions in incorporated documents by reference, and / or ordinary meanings of defined terms.

[0086] As used herein, the indefinite articles "a" and "an" are to be understood as meaning "at least one" unless explicitly stated to the contrary herein or in the claims.

[0087] As used herein, the phrase "and / or" is to be understood as meaning "either or both" of the elements so joined, i.e., elements that in some cases coexist and in other cases exist separately, in the claims and the specification. A number of elements listed using "and / or" are to be construed in the same manner, i.e., as "one or more" of the elements so joined. Other elements may optionally exist in addition to the elements specifically identified by the "and / or" clause, whether or not related to the specifically identified elements. Thus, by way of non-limiting example, reference to "A and / or B" can, when used in conjunction with language such as "comprising" that is free of limitations, in one embodiment, refer to only A (optionally including elements other than B), in another embodiment, refer to only B (optionally including elements other than A), in yet another embodiment, refer to both A and B (optionally including other elements), and so forth.

[0088] As used herein in the specification and claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" is inclusive, i.e., it includes at least one of the items in the number or list, but also includes two or more, and optionally, additional unlisted items should be construed to be included. Only terms that clearly indicate the opposite, such as "only one of...", or "exactly one of...", or when used in the claims, "consisting of...", refer to including exactly one element in the number of elements or list of elements. Generally, as used herein, the term "or" is construed only as indicating an exclusive alternative (i.e., "either one or the other but not both") when preceded by an exclusive term such as "any one of...", "only one of...", or "exactly one of...". When used in the claims, "consisting essentially of..." shall have its ordinary meaning as used in the field of patent law.

[0089] As used herein in the specification and claims, the phrase "at least one" with respect to a list of one or more elements means at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of every element specifically listed in the list of elements, and it should be understood that it does not exclude any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically identified in the list of elements referred to by the phrase "at least one", whether or not related to the specifically identified elements. Thus, by way of non-limiting example, "at least one of A and B" (or, equivalently, "at least one of A or B", or, equivalently, "at least one of A and / or B") can, in one embodiment, refer to including at least one, optionally two or more, of A and no B (and optionally including elements other than B); in another embodiment, it can refer to including at least one, optionally two or more, of B and no A (and optionally including elements other than A); and in yet another embodiment, it can refer to including at least one, optionally two or more, of A and at least one, optionally two or more, of B (and optionally including other elements), etc.

[0090] Not only in the claims, but also in the above specification, all transitional phrases such as "comprises", "includes", "carries", "has", "contains", "accompanies", "holds", "consists of", and the like are to be understood as being open-ended, i.e., meaning including but not limited to these. As described in section 2111.03 of the United States Patent and Trademark Office's Manual of Patent Examining Procedure, only the transitional phrases "consisting of" and "consisting essentially of" are to be considered closed or semi-closed transitional phrases, respectively.

Claims

1. A control system (100), A flexible input / output (I / O) circuit (120) communicatively coupled to connected devices (140, 150, 160) within the control system, the flexible I / O circuit being Adapting a received first control signal of a first signaling type to a second control signal of a second signaling type supported by the connected device and different from the first signaling type, and A flexible I / O circuit adapted to convert a first data signal of the second signaling type received from the connected device to a second data signal of the first signaling type supported by a controller (110) of the control system, and A signal processing resource circuit (SPRe circuit) (115) communicatively coupled to the controller and communicatively coupled to the flexible I / O circuit, the SPRe circuit performing the signal processing task and offloading a signal processing task related to a second control signal issued by the controller such that the first control signal is output instead of the controller performing the signal processing task. A control system comprising:

2. The control system according to claim 1, wherein the signal processing task includes generating a stream of digital values for a waveform, and the SPRe circuit is adapted to output the stream of digital values as the first control signal to the flexible I / O circuit.

3. The SPRe circuit includes a master signal input line, and The control system according to claim 1, wherein the SPRe circuit is configurable using a configuration setting that delays execution of the signal processing task until reception of a master signal on the master signal input line.

4. The SPRe circuit is a first SPRe circuit, the connected device is a first connected device, and the signal processing task is a first signal processing task, the system being A second SPRe circuit communicatively coupled to the controller and communicatively coupled to the flexible I / O circuit, The second SPRe circuit performs the second signal processing task and offloads the second signal processing task related to a third control signal issued by the controller so as to output a third control signal to the flexible I / O circuit instead of the controller that performs the second signal processing task, and The control system according to claim 3, further comprising the second SPRe circuit adapted to output the master signal to the first SPRe circuit in response to executing the second signal processing task.

5. The SPRe circuit is a first SPRe circuit, the connected device is a first connected device, and the signal processing task is a first signal processing task, and the system is A second SPRe circuit communicably coupled to the controller and communicably coupled to the flexible I / O circuit, The second SPRe circuit offloads the second signal processing task related to the second data signal received from the flexible I / O circuit so that the second SPRe circuit performs the second signal processing task instead of the controller that performs the second signal processing task, and The control system according to claim 3, further comprising the second SPRe circuit adapted to output the master signal to the first SPRe circuit in response to executing the second signal processing task.

6. A control system, A controller (110) for issuing a first control signal of a first signaling type to control connected devices (140, 150, 160) within a dynamic environment (105), and A flexible input / output (I / O) circuit (120) communicably coupled to the controller and the connected devices, converting the first control signal into a second control signal of a second signaling type different from the first signaling type and supported by the connected devices. A signal processing resource circuit (SPRe circuit) (115) communicably coupled to the controller and the flexible I / O circuit, wherein the SPRe circuit is adapted to offload a signal processing task related to the first control signal from the controller such that the SPRe circuit performs the signal processing task instead of the controller that performs the signal processing task, and a control system comprising the same. **Claim 7** The control system according to claim 6, wherein the signal processing task includes generating a stream of digital values for a waveform, and the SPRe circuit is adapted to output the stream of digital values to the flexible I / O circuit. **Claim 8** The control system according to claim 7, wherein the SPRe circuit is configured to receive at least one parameter defining at least one characteristic of the waveform. **Claim 9** The at least one parameter includes a start phase of the waveform, and an end phase of the waveform, and the control system according to claim 8. **Claim 10** The SPRe circuit is configured to receive data defining a master signaling channel of the flexible I / O circuit different from an output channel of the flexible I / O circuit on which the waveform is to be output, and thus the output of the waveform is conditioned on an event occurring on the master signaling channel, and the control system according to claim 7. **Claim 11** The control system according to claim 7, wherein the flexible I / O circuit is adapted to output a digital waveform based on the stream of digital values received from the SPRe circuit. **Claim 12** The control system according to claim 11, wherein the digital waveform is configured to control a motor. **Claim 13** The control system according to claim 7, wherein the flexible I / O circuit is adapted to output an analog waveform based on the stream of digital values received from the SPRe circuit. **Claim 14** The control system according to claim 13, wherein the analog waveform is configured to excite a resolver. **Claim 15** The SPRe circuit includes at least one digital signal generator (225), and at least one analog signal generator (227), and the control system according to claim 6. **Claim 16** The connected device includes a resolver, and the SPRe circuit outputs a waveform to excite the resolver, receives two signals from the flexible I / O circuit, the two signals representing two analog signals output by the resolver, and comprises a resolver processor adapted to evaluate the two signals to determine the rotational angle of the resolver, the system of claim 6. **Claim 17** The control system of claim 6, wherein the SPRe circuit comprises at least one field programmable gate array. **Claim 18** The control system of claim 6, wherein the SPRe circuit comprises at least one universal asynchronous receiver / transmitter (UART) device. **Claim 19** The control system of claim 6, wherein the SPRe circuit comprises at least one data buffer (232, 234, 262) for buffering data received from the controller. **Claim 20** The control system of claim 6, wherein the SPRe circuit comprises at least one data buffer (242, 244) for buffering data transmitted to the flexible I / O circuit. **Claim 21** The control system of claim 6, wherein the SPRe circuit comprises at least one data buffer (219, 261) for buffering data transmitted to the controller. **Claim 22** The controller is adapted to negotiate a signaling type with the connected device, the negotiating first transmitting a first communication to the connected device using a default signaling type, receiving a second communication from the connected device, the second communication identifying the second signaling type to the controller, and configuring the flexible I / O circuit to transmit the second control signal to the connected device using the second signaling type in response to receiving the second communication identifying the second signaling type, the control system of claim 6. **Claim 23** The flexible I / O circuit A multiplexing chip (512) for routing a signal received by the multiplexing chip on an input port to one of a number of output ports. A clamping diode (D1) connected between a power supply for the multiplexing chip (512) and the input port, to reduce or prevent an overvoltage received at the input port from being coupled to an unselected output port of the number of output ports. The control system according to claim 6. **Claim 24** A control system, A controller (110) for receiving information related to connected devices (140, 150, 160) within a dynamic environment (105), the information being based on a signal output from the connected device. A flexible I / O circuit (120) communicatively coupled to the controller and the connected device, for converting a first signal of a first signaling type from the connected device to a second signal of a second signaling type different from the first signaling type and supported by the controller. An SPR e circuit (115) communicatively coupled to the controller and the flexible I / O circuit, the SPR e circuit being adapted to offload a signal processing task associated with the second signal received from the flexible I / O circuit such that the SPR e circuit performs the signal processing task instead of the controller. A control system comprising the SPR e circuit. **Claim 25** The signal processing task includes correcting data values received from the connected device, and The correction of the data values uses a look-up table (LUT) stored in a memory accessed by the SPR e circuit. The control system according to claim 24. **Claim 26** The control system according to claim 25, wherein the SPR e circuit is configured to receive configuration parameters defining entries of the LUT. **Claim 27** The control system according to claim 25, wherein the SPR e circuit is configured to receive configuration parameters for identifying the LUT from among a plurality of LUTs stored in the memory. **Claim 28** The control system according to claim 25, wherein the LUT includes a temperature correction value for a thermistor. **Claim 29** The control system according to claim 24, wherein the SPR e circuit includes a filter for filtering the second signal. **Claim 30** The control system according to claim 29, wherein the SPR e circuit is configured to receive at least one configuration parameter to set or change the configuration of the filter. **Claim 31** The control system according to claim 30, wherein the at least one parameter includes a time constant τ for the filter. **Claim 32** The control system according to claim 30, wherein the at least one parameter includes a deviation value E for the filter. **Claim 33** The control system according to claim 30, wherein the at least one parameter includes a hysteresis value H for the filter. **Claim 34** The control system according to claim 30, wherein the filter is a digital filter. **Claim 35** The control system according to claim 24, wherein the SPR e circuit includes at least one frequency counter for detecting the frequency of a signal received from the flexible I / O circuit. **Claim 36** The control system according to claim 24, wherein the SPR e circuit includes at least one deserializator for converting a serial data signal received from the flexible I / O circuit by the SPR e circuit into a parallel data signal for transmission to the controller. **Claim 37** The control system according to claim 24, wherein the SPR e circuit includes at least one serializer for converting a parallel data signal received from the controller by the SPR e circuit into a serial data signal for transmission to the flexible I / O circuit. **Claim 38** The control system according to claim 24, wherein the SPR e circuit includes at least one field programmable gate array. **Claim 39** The control system according to claim 24, wherein the SPR e circuit includes at least one universal asynchronous receiver / transmitter (UART) device. **Claim 40** The control system according to claim 24, wherein the SPR e circuit includes at least one data buffer (232, 234, 262) for buffering data received from the controller. **Claim 41** The control system according to claim 24, wherein the SPR e circuit comprises at least one data buffer (242, 244) for buffering data transmitted to the flexible I / O circuit.

42. The control system according to claim 24, wherein the SPR e circuit comprises at least one data buffer (219, 261) for buffering data transmitted to the controller.

43. The flexible I / O circuit A multiplexing chip (512) for routing a signal received by the multiplexing chip on an input port to one of a plurality of output ports. A clamping diode (D1) connected between a power supply for the multiplexing chip (512) and the input port to reduce or prevent an overvoltage received at the input port from being coupled to an unselected output port of the plurality of output ports. The control system according to claim 24.

44. A system (102) A) A controller (110) for monitoring and controlling a dynamic environment (105) having a plurality of conditions in response to which a plurality of actions are required, Dividing the plurality of conditions into a plurality of subsets including a first subset, Receiving at least one input signal (111) representing at least one monitored condition of the plurality of conditions and evaluating the first subset of the plurality of conditions by processing the at least one input signal to determine whether at least one condition of the first subset is satisfied. A controller that provides first control information (113) representing at least one first action of the plurality of actions when at least one condition of the first subset is satisfied. B) A flexible input / output circuit (120) A first input / output (I / O) signaling channel (122A) for facilitating communication between the flexible input / output circuit and a first device (170A) of a plurality of devices (170) within the dynamic environment. A second input / output (I / O) signaling channel (122B) communicatively coupled to the controller (110) to facilitate communication between the flexible input / output circuitry and a second device (170B) of the plurality of devices (170) within the dynamic environment. The flexible input / output circuitry (120) dynamically configures each of the first I / O signaling channel (122A) and the second I / O signaling channel (122B) based on at least one programming input (119) provided by the controller to support transmission and / or reception of single-ended digital and analog signaling types and / or differential digital and analog signaling types. A flexible input / output circuitry. C) A signal processing resource (SPRe) circuit (115) communicatively coupled between and disposed between the controller (110) and the flexible input / output circuitry (120). A first processing resource (115A) for processing a first signal (117A) transmitted to or received from the first I / O signaling channel (122A) via the flexible input / output circuitry (120). A second processing resource (115B) for processing a second signal (117B) transmitted to or received from the first I / O signaling channel (122A) or the second I / O signaling channel (122B) via the flexible input / output circuitry (120). At least one of the first processing resource (115A) or the second processing resource (115B) of the SPRe circuit (115) provides the controller (110) with the at least one input signal (111) representative of the at least one monitored condition of the plurality of conditions within the dynamic environment (105). At least one of the first processing resource (115A) or the second processing resource (115B) receives the first control information (113) representing the at least one first action among the plurality of actions from the controller (110), and processes at least one of the first signal (117A) or the second signal (117B) at least partially based on the received first control information (113). A system comprising: an SPR e circuit in which the second processing resource (115B) receives at least one SPR e control signal (114) from the first processing resource (115A) and processes the second signal (117B) at least partially based on the SPR e control signal (114).

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