Display device and method for manufacturing the same

Abstract

The display device includes a substrate, a first alloy layer disposed on the substrate and including a titanium alloy containing at least one of copper and zinc, and a metal pattern including a first metal layer disposed on the first alloy layer, an active layer disposed on the metal pattern, a second alloy layer disposed on the active layer and including a titanium alloy containing at least one of copper and zinc, and a gate electrode including a second metal layer disposed on the second alloy layer.

Description

Technical Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device and a method for manufacturing the same.

Background Art

[0002] A display device is a device that displays an image for providing visual information to a user. Among display devices, recently, organic light-emitting display devices have attracted attention.

[0003] An organic light-emitting display device has self-luminous characteristics and, unlike a liquid crystal display device, does not require a separate light source, so that its thickness and weight can be reduced. In addition, an organic light-emitting display device exhibits high-quality characteristics such as low power consumption, high brightness, and high response speed.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a display device having high resolution.

[0005] Another object of the present invention is to provide a manufacturing method for manufacturing the display device.

[0006] However, the object of the present invention is not limited to the above-described object, and can be variously extended without departing from the spirit and scope of the present invention.

Means for Solving the Problems

[0007] To achieve the object of the present invention, a display device according to an embodiment may include a substrate, a first alloy layer disposed on the substrate and including a titanium alloy containing at least one of copper and zinc, and a metal pattern including a first metal layer disposed on the first alloy layer, an active layer disposed on the metal pattern, a second alloy layer disposed on the active layer and including a titanium alloy containing at least one of copper and zinc, and a gate electrode including a second metal layer disposed on the second alloy layer.

[0008] In one embodiment, each of the first metal layer and the second metal layer may contain copper.

[0009] In one embodiment, the active layer may contain an oxide semiconductor.

[0010] In one embodiment, the first alloy layer and the second alloy layer may contain the same substance as each other.

[0011] In one embodiment, the content of titanium contained in the titanium alloy is about 10 at% (atomic %) to about 80 at%, and the content of copper or zinc contained in the titanium alloy may be about 20 at% to about 90 at%.

[0012] In one embodiment, the content of titanium contained in the titanium alloy is about 20 at% to about 50 at%, and the content of copper or zinc contained in the titanium alloy may be about 50 at% to about 80 at%.

[0013] In one embodiment, each of the first alloy layer and the second alloy layer may contain a titanium alloy containing titanium, copper, and zinc.

[0014] In one embodiment, the thickness of each of the first alloy layer and the second alloy layer may be about 30 Å to about 100 Å.

[0015] In one embodiment, the thickness of each of the first metal layer and the second metal layer may be about 1500 Å to about 4500 Å.

[0016] In one embodiment, the thickness of the metal pattern may be the same as the thickness of the gate electrode.

[0017] To achieve other objects of the present invention, a method for manufacturing a display device according to an embodiment may include forming a first alloy layer including a titanium alloy including at least one of copper or zinc on a substrate; forming a first metal layer on the first alloy layer; patterning the first alloy layer and the first metal layer to form a metal pattern; forming an active layer on the first metal layer; forming a second alloy layer including a titanium alloy including at least one of copper or zinc on the active layer; forming a second metal layer on the second alloy layer; and patterning the second alloy layer and the second metal layer to form a gate electrode.

[0018] In one embodiment, the active layer may be formed of an oxide semiconductor.

[0019] In one embodiment, the step of forming the metal pattern may include etching the first alloy layer and the first metal layer by wet etching.

[0020] In one embodiment, the step of forming the gate electrode may etch the second alloy layer and the second metal layer by wet etching.

[0021] In one embodiment, the thickness of the metal pattern and the thickness of the gate electrode may be formed to be the same (for example, the thicknesses of the metal pattern and the gate electrode are the same).

[0022] In one embodiment, the first metal layer and the second metal layer may be formed of copper.

[0023] In one embodiment, the first alloy layer and the second alloy layer are formed of the titanium alloy, the content of titanium forming the titanium alloy is about 10 at% to about 80 at%, and the content of copper or zinc forming the titanium alloy may be about 20 at% to about 90 at%.

[0024] In one embodiment, the content of titanium forming the titanium alloy is about 20 at% to about 50 at%, and the content of copper or zinc forming the titanium alloy can be about 50 at% to about 80 at%.

[0025] In one embodiment, the thickness of each of the first alloy layer and the second alloy layer can be formed to be about 30 Å to about 100 Å.

[0026] In one embodiment, the thickness of each of the first metal layer and the second metal layer can be formed to be about 1500 Å to about 4500 Å.

Advantages of the Invention

[0027] In the display device according to the present invention, since the electrode or wiring included in the display device includes an alloy layer containing a titanium alloy, the width of the electrode or wiring can be easily controlled or selected. Therefore, a fine line width of the electrode or wiring included in the display device can be realized. In addition, hydrogen diffused from the electrode or wiring into the active layer can be prevented, and the performance of the transistor can be improved. Therefore, a high resolution can be realized in the display device including the electrode or wiring.

[0028] In addition, by realizing the fine line width of the electrode or wiring, the metal layer disposed on the alloy layer contains copper. Therefore, the resistance of the electrode and wiring can be reduced.

[0029] However, the effects of the present invention are not limited thereto, and can be variously extended without departing from the spirit and scope of the present invention.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0031] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. For the same components in the drawings, the same reference numerals are given, and redundant descriptions of the same components are omitted.

[0032] FIG. 1 is a plan view of a display device according to an embodiment of the present invention.

[0033] As shown in FIG. 1, the display device 10 may include a display area (DA) and a non-display area (NDA). The display area (DA) may be an area for displaying an image. The planar shape of the display area (DA) may be rectangular, or as shown in FIG. 1, rectangular with rounded corners. However, the planar shape of the display area (DA) is not limited thereto, and the display area (DA) may have an appropriate planar shape such as circular, elliptical, polygonal, etc.

[0034] The non-display area (NDA) may be disposed around the display area (DA). The non-display area (NDA) surrounds the display area (DA). The non-display area (NDA) is an area that does not display an image. In one embodiment, a driving unit for image display of the display area (DA) is disposed in the non-display area (NDA).

[0035] Pixels (PX) may be arranged in a matrix in the display area (DA). Signal lines such as gate lines (GL) and data lines (DL) may be arranged in the display area (DA). Each of the pixels (PX) may be connected to the signal lines such as the gate line (GL) and the data line (DL). Each of the pixels (PX) may be applied with a gate signal, a data signal, etc. from the signal lines.

[0036] FIG. 2 is a cross-sectional view taken along the line I-I' of FIG. 1.

[0037] As shown in FIGS. 1 and 2, the display device 10 may include a substrate 100, a display element layer 200, and a sealing layer 300. The display element layer 200 may include a circuit element layer 210 and a light-emitting element layer 220.

[0038] The circuit element layer 210 is disposed on the substrate 100 and may include a metal pattern (BML), a buffer layer (BFR), at least one transistor (TR), gate wiring, a connection electrode (CP), a first insulating layer (IL1), a second insulating layer (IL2), a third insulating layer (IL3), and a fourth insulating layer (IL4). The transistor (TR) may include an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). The light-emitting element layer 220 is disposed on the circuit element layer 210 and may include a fifth insulating layer (IL5), a spacer (SPC), and a light-emitting diode (LD). The light-emitting diode (LD) may include a first electrode (E1), a light-emitting layer (LEL), and a second electrode (E2).

[0039] The substrate 100 supports the display element layer 200. The substrate 100 is a base substrate or a base member and is made of an insulating material such as a polymer resin. For example, the substrate 100 is a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate 100 may include a flexible material and a rigid material.

[0040] The metal pattern (BML) may be disposed on the substrate 100.

[0041] The buffer layer (BFR) may be disposed on the substrate 100. The buffer layer (BFR) may cover the metal pattern (BML). The metal pattern (BML) and the buffer layer (BFR) may prevent or reduce the phenomenon of metal atoms and impurities diffusing from the substrate 100 into the active layer (ACT).

[0042] The active layer (ACT) may be disposed on the substrate 100. The active layer (ACT) may overlap the metal pattern (BML). The active layer (ACT) may be divided into a source region and a drain region doped with impurities and a channel region between the source region and the drain region.

[0043] The active layer (ACT) contains an oxide semiconductor. As the oxide semiconductor, there can be a monoelemental metal oxide such as indium oxide (In), tin oxide (Sn), or zinc oxide (Zn), a binary metal oxide such as an In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, or In-Ga-based oxide, a ternary metal oxide such as an In-Ga-Zn-based oxide, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, or In-Lu-Zn-based oxide, and a quaternary metal oxide such as an In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, or In-Hf-Al-Zn-based oxide. These substances can be used alone or in combination. For example, the active layer (ACT) can contain IGZO (Indium-Gallium-Zinc Oxide) among the In-Ga-Zn-based oxides.

[0044] The first insulating layer (IL1) can be disposed on the active layer (ACT). The first insulating layer (IL1) can overlap the active layer (ACT) and have an island shape. However, the present invention is not limited thereto. For example, the first insulating layer (IL1) can contain an inorganic substance.

[0045] The gate layer including the gate wiring and the gate electrode (GE) may be disposed on the first insulating layer (IL1). In one embodiment, the gate electrode (GE) may overlap the channel region of the active layer (ACT). However, the present invention is not limited thereto, and the gate electrode (GE) may be a part of the gate wiring. Therefore, the material forming the gate electrode (GE) and the thickness of the gate electrode (GE) may be the same as those of the gate wiring.

[0046] The second insulating layer (IL2) may be disposed on the buffer layer (BFR) and the active layer (ACT). Also, the second insulating layer (IL2) covers the active layer (ACT), the first insulating layer (IL1), and the gate electrode (GE), and may be disposed with substantially the same thickness along the contour surface (profile) of the active layer (ACT), the first insulating layer (IL1), and the gate electrode (GE). However, the present invention is not limited thereto.

[0047] The source electrode (SE) and the drain electrode (DE) may be disposed on the second insulating layer (IL2). The source electrode (SE) may be in contact with the metal pattern (BML) through a first contact hole formed in the buffer layer (BFR) and the second insulating layer (IL2). Also, the source electrode (SE) may be in contact with the source region of the active layer (ACT) through a second contact hole formed in the second insulating layer (IL2). The drain electrode (DE) may be in contact with the drain region of the active layer (ACT) through a third contact hole formed in the second insulating layer (IL2). However, the present invention is not limited thereto. In other embodiments, the drain electrode (DE) may be in contact with the metal pattern (BML) through a first contact hole formed in the first and second insulating layers (IL1, IL2), and may be in contact with the active layer (ACT) through a second contact hole formed in the second insulating layer (IL2). Also, the source electrode (SE) may be in contact with the active layer (ACT) through a third contact hole formed in the second insulating layer (IL2).

[0048] The third insulating layer (IL3) may be disposed on the second insulating layer (IL2). Also, the third insulating layer (IL3) may cover the source and drain electrodes (SE, DE), may not generate a step around the source and drain electrodes (SE, DE), and may have a substantially flat upper surface. For example, the third insulating layer (IL3) may contain an organic substance.

[0049] The connection electrode (CP) may be disposed on the third insulating layer (IL3). The connection electrode (CP) may be in contact with the source electrode (SE) or the drain electrode (DE) through a fourth contact hole formed in the third insulating layer (IL3).

[0050] The fourth insulating layer (IL4) can be disposed on the third insulating layer (IL3). Further, the fourth insulating layer (IL4) covers the connection electrode (CP), does not generate a step around the source and drain electrodes (SE, DE), and has a substantially flat upper surface. For example, the fourth insulating layer (IL4) may contain an organic substance.

[0051] The first electrode (E1) can be disposed on the fourth insulating layer (IL4). The first electrode (E1) has reflectivity or light-projecting property. For example, the first electrode (E1) may contain a metal.

[0052] The first electrode (E1) can be in contact with the connection electrode (CP) through a fifth contact hole formed in the fourth insulating layer (IL4). Thereby, the first electrode (E1) can be connected to the transistor (TR).

[0053] The fifth insulating layer (IL5) can be disposed on the fourth insulating layer (IL4), and an opening for exposing the upper surface of the first electrode (E1) can be defined in the fifth insulating layer (IL5). For example, the fifth insulating layer (IL5) may contain an organic substance or an inorganic substance.

[0054] The spacer (SPC) can be disposed on the fifth insulating layer (IL5). For example, the spacer (SPC) may contain an organic substance or an inorganic substance. The spacer (SPC) can maintain a gap between the sealing layer 300 and the substrate 100.

[0055] The spacer (SPC) may contain a substance different from that of the fifth insulating layer (IL5). The spacer (SPC) can be formed after the fifth insulating layer (IL5) is formed. However, embodiments according to the present invention are not limited thereto, and the spacer (SPC) may contain the same substance as that of the fifth insulating layer (IL5). Further, the fifth insulating layer (IL5) and the spacer (SPC) can be formed simultaneously using a halftone mask.

[0056] The light-emitting layer (LEL) can be disposed on the first electrode (E1). The light-emitting layer (LEL) can be disposed in the opening formed in the fifth insulating layer (IL5). In one embodiment, the light-emitting layer (LEL) can have a multilayer structure including a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. The organic light-emitting layer can contain a light-emitting substance.

[0057] The second electrode (E2) can cover the light-emitting layer (LEL) and can be disposed on the fifth insulating layer (IL5) and the spacer (SPC). In one embodiment, the second electrode (E2) can have a plate shape. Also, the second electrode (E2) can have light-emitting property or reflectivity. For example, the second electrode (E2) can contain a metal.

[0058] The encapsulation layer 300 can prevent moisture and oxygen from the outside from penetrating into the light-emitting diode (LD). For example, the encapsulation layer 300 can include a first inorganic encapsulation layer (IEL1), an organic encapsulation layer (OEL), and a second inorganic encapsulation layer (IEL2).

[0059] The first inorganic encapsulation layer (IEL1) can be disposed on the second electrode (E2) with substantially the same thickness along the profile of the second electrode (E2). The organic encapsulation layer (OEL) can be disposed on the first inorganic encapsulation layer (IEL1) and can have a substantially flat upper surface without generating a step around the first inorganic encapsulation layer (IEL1). The second inorganic encapsulation layer (IEL2) can be disposed on the organic encapsulation layer (OEL).

[0060] Figure 3 is a cross-sectional view showing an enlarged A region of Figure 2. Figure 4 is a cross-sectional view showing an enlarged B region of Figure 2.

[0061] For example, Figure 3 is a cross-sectional view showing the metal pattern (BML), and Figure 4 is a cross-sectional view showing the gate electrode (GE).

[0062] As shown in FIGS. 1 to 4, the metal pattern (BML) may include a first alloy layer (AL1) and a first metal layer (ML1). The first alloy layer (AL1) may be disposed on the substrate 100, and the first metal layer (ML1) may be disposed on the first alloy layer (AL1).

[0063] Each of the gate electrode (GE) and the gate wiring (GL) may include a second alloy layer (AL2) and a second metal layer (ML2). The second alloy layer (AL2) may be disposed on the first insulating layer (IL1), and the second metal layer (ML2) may be disposed on the second alloy layer (AL2). Hereinafter, the gate electrode (GE) will be mainly described.

[0064] The first metal layer (ML1) and the second metal layer (ML2) may contain copper. The first metal layer (ML1) and the second metal layer (ML2) may contain the same substance as each other.

[0065] The first alloy layer (AL1) may contain a titanium alloy. The titanium alloy contains titanium (Ti) and may contain at least one of copper (Cu) and zinc (Zn).

[0066] Similarly, the second alloy layer (AL2) may contain a titanium alloy. The titanium alloy contains titanium and may contain at least one of copper and zinc.

[0067] For example, each of the first alloy layer (AL1) and the second alloy layer (AL2) may contain a titanium alloy containing titanium and copper. However, the present invention is not limited thereto, and each of the first alloy layer (AL1) and the second alloy layer (AL2) may contain a titanium alloy containing titanium and zinc.

[0068] In one embodiment, the first alloy layer (AL1) and the second alloy layer (AL2) may contain the same substance as each other. However, the present invention is not limited thereto, and the first alloy layer (AL1) and the second alloy layer (AL2) may contain different substances from each other.

[0069] For example, the first alloy layer (AL1) and the second alloy layer (AL2) may contain the same titanium alloy. The titanium alloy may contain titanium and copper. The content of titanium contained in the titanium alloy may be from about 10 at% to about 80 at%. The content of copper contained in the titanium alloy may be from about 20 at% to about 90 at%.

[0070] The second alloy layer (AL2) containing titanium can prevent hydrogen diffusing from the second insulating layer (IL2) to the active layer (ACT). Also, the first alloy layer (AL1) containing titanium can prevent hydrogen diffusing from the substrate 100 to the active layer (ACT). That is, each of the first alloy layer (AL1) and the second alloy layer (AL2) can function as a hydrogen barrier.

[0071] When the content of titanium contained in the titanium alloy is about 10 at% or less, each of the first alloy layer (AL1) and the second alloy layer (AL2) may not be able to properly serve as a hydrogen barrier.

[0072] When the content of copper contained in the titanium alloy is about 20 at% or less, the difference between the etching rate of the titanium alloy and the etching rate of the copper becomes large. Therefore, when etching the first alloy layer (AL1) and the first metal layer (ML1), skew (for example, skew (SK1) in FIG. 13) may increase. The skew means the distance between the end of the photoresist pattern (see FIG. 13) and the end of the metal pattern (BML). Thus, when etching the first alloy layer (AL1) and the first metal layer (ML1), it may be difficult to control the width of the metal pattern (BML).

[0073] Similarly, when etching the second alloy layer (AL2) and the second metal layer (ML2), skew (e.g., skew (SK2) in FIG. 21) may increase. The skew means the distance between the end of the photoresist pattern (see FIG. 21) and the end of the gate electrode (GE). Therefore, when etching the second alloy layer (AL2) and the second metal layer (ML2), it may be difficult to control the width of the gate electrode (GE).

[0074] Desirably, the content of titanium contained in the titanium alloy is about 20 at% to about 50 at%, and the content of copper contained in the titanium alloy can be about 50 at% to about 80 at%.

[0075] When the content of titanium contained in the titanium alloy is about 20 at% to about 50 at% and the content of copper contained in the titanium alloy is about 50 at% to about 80 at%, each of the first alloy layer (AL1) and the second alloy layer (AL2) can sufficiently serve as a hydrogen barrier. Also, since the difference between the etching rate of the titanium alloy and the etching rate of copper decreases, when etching the first alloy layer (AL1) and the first metal layer (ML1), the skew can be reduced. For example, when etching the first alloy layer (AL1) and the first metal layer (ML1), the width of the metal pattern (BML) can be controlled or selected (e.g., can be easily controlled or selected). Similarly, when etching the second alloy layer (AL2) and the second metal layer (ML2), the skew can be reduced. For example, when etching the second alloy layer (AL2) and the second metal layer (ML2), the width of the gate electrode (GE) can be controlled or selected (e.g., can be easily controlled or selected).

[0076] Also, in other embodiments, each of the first alloy layer (AL1) and the second alloy layer (AL2) may include a titanium alloy containing titanium, copper, and zinc. For example, the titanium alloy may contain all of titanium, copper, and zinc.

[0077] In the above description, the case where the titanium alloy contains titanium and copper has been described as a reference. However, the present invention is not limited thereto, and the present invention can be similarly applied when the titanium alloy contains titanium and zinc, or when the titanium alloy contains titanium, copper, and zinc.

[0078] In one embodiment, each of the thickness (T1) of the first alloy layer (AL1) and the thickness (T2) of the second alloy layer (AL2) is about 30 Å to 100 Å. The first alloy layer (AL1) and the second alloy layer (AL2) have substantially the same thickness. However, the present invention is not limited thereto, and the first alloy layer (AL1) and the second alloy layer (AL2) may have different thicknesses from each other.

[0079] When each of the thickness (T1) of the first alloy layer (AL1) and the thickness (T2) of the second alloy layer (AL2) is less than about 30 Å, it is difficult to control each of the thickness (T1) of the first alloy layer (AL1) and the thickness (T2) of the second alloy layer (AL2) during the manufacturing process. Therefore, the reliability of the display device 10 decreases.

[0080] When each of the thickness (T1) of the first alloy layer (AL1) and the thickness (T2) of the second alloy layer (AL2) exceeds about 100 Å, when etching each of the first alloy layer (AL1) and the second alloy layer (AL2) in the manufacturing process, the etching time may take a long time. Therefore, since the manufacturing time of the display device 10 increases, the manufacturing efficiency may decrease.

[0081] In addition, when the thickness (T1) of the first alloy layer (AL1) and the thickness (T2) of the second alloy layer (AL2) are each 100 Å or more, when heat-treated at a high temperature, heat diffusion may occur between the titanium of each of the first alloy layer (AL1) and the second alloy layer (AL2) and the copper of each of the first metal layer (ML1) and the second metal layer (ML2). Therefore, a diffusion layer due to heat diffusion between titanium and copper may be formed between the first alloy layer (AL1) and the first metal layer (ML1), and between the second alloy layer (AL2) and the second metal layer (ML2). The thicker the thickness (T1) of the first alloy layer (AL1) and the thickness (T2) of the second alloy layer (AL2) are, the thicker the diffusion layer due to the heat diffusion may become. Also, the thicker the diffusion layer becomes, the more the resistance of each of the metal pattern (BML) and the gate electrode (GE) may increase.

[0082] In one embodiment, the thickness (T3) of the first metal layer (ML1) and the thickness (T4) of the second metal layer (ML2) are each about 1500 Å to 4500 Å. The first metal layer (ML1) and the second metal layer (ML2) have substantially the same thickness. However, the present invention is not limited thereto, and the first metal layer (ML1) and the second metal layer (ML2) may have different thicknesses from each other.

[0083] When the thickness (T3) of the first metal layer (ML1) and the thickness (T4) of the second metal layer (ML2) are each less than about 1500 Å, the resistance of each of the first metal layer (ML1) and the second metal layer (ML2) may increase.

[0084] When the thickness (T3) of the first metal layer (ML1) and the thickness (T4) of the second metal layer (ML2) are each more than about 4500 Å, in the stacked structure of the display device 10, each of the first metal layer (ML1) and the second metal layer (ML2) may affect the layer disposed on each of the first metal layer (ML1) and the second metal layer (ML2). Therefore, this may cause a defect in the display device 10.

[0085] In one embodiment, since the first alloy layer (AL1) and the second alloy layer (AL2) contain the same substance, and the first metal layer (ML1) and the second metal layer (ML2) contain the same substance, the metal pattern (BML) may contain substantially the same substance as the gate electrode (GE).

[0086] Also, the thickness (T5) of the metal pattern (BML) may be substantially the same as the thickness (T6) of the gate electrode (GE).

[0087] The metal pattern (BML) and the gate electrode (GE) may be connected to the gate wiring (GL). Here, since the metal pattern (BML) contains substantially the same substance as the gate electrode (GE) and the gate wiring (GL), and the thickness (T5) of the metal pattern (BML) is substantially the same as the thickness (T6) of the gate electrode (GE) and the thickness of the gate wiring (GL), the metal pattern (BML), the gate electrode (GE), and the gate wiring may have substantially the same resistance as each other. Therefore, signal transmission through the gate wiring may be facilitated. Also, since the metal pattern (BML), the gate electrode (GE), and the gate wiring are formed of the same substance and the same thickness, compatibility may be improved. Therefore, in the manufacturing process of the display device 10, the metal pattern (BML), the gate electrode (GE), and the gate wiring can be easily manufactured.

[0088] In one embodiment, the metal pattern (BML) included in the display device 10 includes the first alloy layer (AL1) containing the titanium alloy, and the gate electrode (GE) includes the second alloy layer (AL2) containing the titanium alloy, so that the widths of the metal pattern (BML) and the gate electrode (GE) can be controlled or selected (for example, can be easily controlled or selected). Therefore, the respective fine line widths of the metal pattern (BML) and the gate electrode (GE) included in the display device 10 can be realized. In one embodiment, the metal pattern (BML) and the gate electrode (GE) prevent or substantially prevent hydrogen from diffusing into the active layer (ACT), thereby improving the performance of the transistor (TR). Therefore, high resolution is realized in the display device 10 including the metal pattern (BML) and the gate electrode (GE), and the display quality is improved.

[0089] In addition, since each of the first metal layer (ML1) and the second metal layer (ML2) contains copper, the resistance of the electrodes and wirings including the first metal layer (ML1) and the second metal layer (ML2) can be reduced.

[0090] Hereinafter, the effects of the present invention will be described.

[0091] FIG. 5(a) is a graph showing bottom skew according to the thickness of wiring for the wiring according to an embodiment of the present invention and the wiring according to a comparative example. FIG. 5(b) is a graph showing top skew according to the thickness of wiring for the wiring according to an embodiment of the present invention and the wiring according to a comparative example.

[0092] <Examples 1 and 2, Comparative Examples 1 and 2> According to Example 1 and Example 2, after manufacturing a first layer (e.g., the first alloy layer (AL1) in FIG. 3 or the second alloy layer (AL2) in FIG. 4) containing about 50 at% titanium and about 50 at% copper, and a second layer containing copper (e.g., the first metal layer (ML1) in FIG. 3 or the second metal layer (ML2) in FIG. 4) on the first layer, the first layer and the second layer were wet-etched to manufacture wiring. According to Comparative Example 1 and Comparative Example 2, after manufacturing a first layer containing titanium and a second layer containing copper, the first layer and the second layer were wet-etched to manufacture wiring. The thickness of the first layer and the thickness of the second layer according to the Examples and Comparative Examples are as shown in Table 1.

[0093]

Table 1

[0094] As shown in Table 1, FIGS. 5(a) and 5(b), under the above conditions, in the Examples and Comparative Examples, the skew corresponding to the thickness of the first layer and the thickness of the second layer was measured. Here, skew means the distance between the end of the photoresist pattern and the end of the lower surface of the second layer in FIG. 5(a), and in FIG. 5(b), the distance between the end of the photoresist pattern and the end of the upper surface of the second layer (e.g., the skew (SK1) in FIG. 13 and the skew (SK2) in FIG. 21).

[0095] As shown in FIG. 5(a), when the thickness of the first layer according to the Example is the same as the thickness of the first layer according to the Comparative Example, it can be seen that the bottom skew (skew at the lower surface) of the second layer satisfying the Example is relatively small compared to the bottom skew of the second layer satisfying the Comparative Example.

[0096] Similarly, as shown in FIG. 5(b), when the thickness of the first layer according to the embodiment is the same as the thickness of the first layer according to the comparative example, the top skew (skew on the upper surface) of the second layer satisfying the embodiment is relatively smaller than the top skew of the second layer satisfying the comparative example.

[0097] From such results, it can be confirmed that when the display device according to the embodiment of the present invention includes the first layer containing a titanium-copper alloy, the skew of the second layer becomes smaller. Therefore, it can be seen that it is relatively easier to control the width of the wiring satisfying Examples 1 and 2 compared to the wiring satisfying Comparative Examples 1 and 2.

[0098] <Examples 1 and 2, Comparative Examples 3 and 4> By Examples 1 and 2, and Comparative Examples 3 and 4, after manufacturing a first layer containing about 50 at% titanium and about 50 at% copper, and a second layer containing copper on the first layer, the first layer and the second layer were wet-etched to manufacture wiring. The thickness of the first layer, the thickness of the second layer, and the width of the upper surface of the second layer according to the examples and comparative examples are as shown in Table 2.

[0099]

Table 2

[0100] As shown in Table 2 above, under the above conditions, in the examples and the comparative examples, the width of the upper surface of the second layer corresponding to the thickness of the first layer and the thickness of the second layer was measured.

[0101] As shown in Table 2 above, it can be seen that as the thickness of the first layer according to the examples and the comparative examples increases, the width of the upper surface of the second layer satisfying Examples 1 and 2 is relatively larger than the width of the upper surface of the second layer satisfying Comparative Examples 3 and 4.

[0102] From such results, it can be confirmed that the thinner the thickness of the first layer included in the display device according to the embodiment of the present invention, the relatively slightly smaller the width of the upper surface of the second layer. That is, it can be seen that the skew decreases as the thickness of the first layer decreases. Therefore, it can be confirmed that the wiring satisfying Example 1 and Example 2 can more easily control the width of the wiring compared to the wiring satisfying Comparative Example 3 and Comparative Example 4.

[0103] FIG. 6 is a graph showing the surface resistance value of the wiring according to the thickness of the wiring for the wiring according to the embodiment of the present invention and the wiring according to the comparative example.

[0104] <Examples 3 to 6, Comparative Example 5 and Comparative Example 6> In Examples 3 to 6, Comparative Example 5 and Comparative Example 6, a first layer containing about 50 at% of titanium and about 50 at% of copper was manufactured, and after manufacturing a second layer containing copper on the first layer, the first layer and the second layer were heat-treated at 400° C. for 1 hour to manufacture wiring. The thicknesses of the first layer and the second layer according to the examples and the comparative examples are as shown in Table 3.

[0105]

Table 3

[0106] As shown in Table 3 and FIG. 6, under the above conditions, in the examples and the comparative examples, the surface resistance before heat treatment and the surface resistance after heat treatment of the wiring were measured according to the thickness of the first layer and the thickness of the second layer.

[0107] As shown in Table 3 and FIG. 6, it can be confirmed that as the thickness of the first layer according to the examples increases, the surface resistance value after heat treatment of the wiring satisfying Examples 3 to 6 is smaller than or substantially the same as the surface resistance value before heat treatment of the wiring. On the other hand, it can be confirmed that as the thickness of the first layer according to the comparative examples increases, the surface resistance value after heat treatment of the wiring satisfying Comparative Example 5 and 6 is larger than the surface resistance value before heat treatment of the wiring.

[0108] From such results, it can be confirmed that the thinner the thickness of the first layer included in the display device according to the embodiment of the present invention, the relatively more the surface resistance value of the wiring decreases after the heat treatment of the wiring. Therefore, it can be confirmed that the resistance of the wiring satisfying Examples 3 to 6 is relatively smaller than that of the wiring satisfying Comparative Examples 5 and 6.

[0109] FIG. 7 is a graph showing the drive current (I GS ) according to the gate-source voltage (V DS ) of the transistors according to the examples and comparative examples.

[0110] <Example 7, Comparative Example 7, and Comparative Example 8> As shown in FIG. 7, in Example 7, after manufacturing a first layer containing about 50 at% of titanium and about 50 at% of copper and a second layer containing copper on the first layer, the first layer and the second layer were wet-etched to manufacture a gate electrode, and a transistor including the gate electrode was manufactured. According to Comparative Example 7, after manufacturing a first layer containing titanium and a second layer containing molybdenum (Mo) on the first layer, the first layer and the second layer were wet-etched to manufacture a gate electrode, and a transistor including the gate electrode was manufactured. According to Comparative Example 8, after manufacturing a first layer containing titanium and a second layer containing copper on the first layer, the first layer and the second layer were wet-etched to manufacture a gate electrode, and a transistor including the gate electrode was manufactured. Also, in Example 7, Comparative Example 7, and Comparative Example 8, the first layer was formed to have a thickness of about 100 Å.

[0111] Under the above conditions, in the above examples and comparative examples, the drive current according to the gate-source voltage was measured.

[0112] It can be confirmed that, at the drive current satisfying the above Example 7, the variation is smaller than that at the drive currents satisfying the above Comparative Examples 7 and 8. From such results, it can be confirmed that the gate electrode satisfying Example 7 of the present invention has improved transistor performance as compared with the gate electrodes satisfying Comparative Examples 7 and 8.

[0113] FIGS. 8 to 26 are cross-sectional views showing a method for manufacturing a display device according to an embodiment of the present invention.

[0114] For example, FIGS. 8 to 26 are diagrams for explaining the method for manufacturing the display device described with reference to FIGS. 1 to 4. Therefore, overlapping explanations may be omitted.

[0115] FIGS. 9 and 10 are cross-sectional views showing the C region of FIG. 8 enlarged and showing the stacking order.

[0116] As shown in FIGS. 8 to 11, a first alloy layer (AL1) can be formed on a substrate 100, and a first metal layer (ML1) can be formed on the first alloy layer (AL1). The first alloy layer (AL1) and the first metal layer (ML1) can form a raw metal layer (BMLa). The first alloy layer (AL1) can be formed of a titanium alloy containing at least one of copper and zinc. The first metal layer (ML1) can be formed of copper.

[0117] The titanium alloy can be formed of at least one of copper and zinc and titanium. For example, the titanium alloy can be formed of titanium and copper.

[0118] In one embodiment, the content of titanium forming the titanium alloy can be about 10 at% to about 80 at%. The content of copper forming the titanium alloy can be about 20 at% to about 90 at%.

[0119] Desirably, the content of titanium forming the titanium alloy is about 20 at% to about 50 at%, and the content of copper forming the titanium alloy can be about 50 at% to about 80 at%.

[0120] As shown in FIGS. 11 and 12, a first photoresist pattern (PR1) can be formed on the original metal layer (BMLa). Using the first photoresist pattern (PR1), the first alloy layer (AL1) and the first metal layer (ML1) can be patterned. That is, the original metal layer (BMLa) can be patterned to form a metal pattern (BML).

[0121] When the first alloy layer (AL1) and the first metal layer (ML1) are patterned, the first alloy layer (AL1) and the first metal layer (ML1) can be etched by wet etching.

[0122] FIG. 13 is a cross-sectional view showing an enlarged D region of FIG. 12.

[0123] Referring further to FIG. 13, the thickness (T1) of the first alloy layer (AL1) can be about 30 Å to about 100 Å. When the thickness (T1) of the first alloy layer (AL1) is about 30 Å to about 100 Å, in the manufacturing process, the width of the metal pattern (BML) is controlled or selected (for example, easily controlled or selected), and the etching time of the first alloy layer (AL1) is reduced, so the manufacturing time of the display device 10 is reduced, and the manufacturing efficiency can be increased.

[0124] Also, the thickness (T3) of the first metal layer (ML1) can be about 1500 Å to 4500 Å. When the thickness (T3) of the first metal layer (ML1) is about 1500 Å to 4500 Å, the first metal layer (ML1) can have little influence on the layer disposed on the first metal layer (ML1). Also, the resistance of the first metal layer (ML1) can be relatively small.

[0125] In one embodiment, since the first alloy layer (AL1) contains the titanium alloy, the etching rates of the first metal layer (ML1) and the first alloy layer (AL1) can be made the same. Therefore, the skew (SK1), which is the distance between the end of the first photoresist pattern (PR1) and the end of the gate electrode (GE) (or the gate wiring), can be reduced.

[0126] After the metal pattern (BML) is formed, the first photoresist pattern (PR1) can be removed.

[0127] As shown in FIGS. 14 and 15, a buffer layer (BFR) can be formed on the metal pattern (BML). The buffer layer (BFR) can be formed to cover the metal pattern (BML). An active layer (ACT) can be formed on the buffer layer (BFR).

[0128] The active layer (ACT) can be formed of an oxide semiconductor. For example, the active layer (ACT) can be formed of IGZO (Indium-Gallium-Zinc Oxide).

[0129] A first insulating layer (IL1) can be formed on the active layer (ACT). The first insulating layer (IL1) can be formed to cover the active layer (ACT).

[0130] FIGS. 16 and 17 are cross-sectional views showing the stacking order with an enlarged view of the E region in FIG. 15.

[0131] As shown in FIGS. 15 to 17, a second alloy layer (AL2) can be formed on the active layer (ACT), and a second metal layer (ML2) can be formed on the second alloy layer (AL2). The second alloy layer (AL2) can be formed of a titanium alloy containing at least one of copper and zinc. The second metal layer (ML2) can be formed of copper. The second alloy layer (AL2) and the second metal layer (ML2) can form a gate layer (GEa).

[0132] The titanium alloy can be formed of at least one of copper and zinc and titanium. For example, the titanium alloy can be formed of titanium and copper.

[0133] In one embodiment, the content of titanium forming the titanium alloy can be from about 10 at% to about 80 at%. The content of copper forming the titanium alloy can be from about 20 at% to about 90 at%.

[0134] Desirably, the content of titanium forming the titanium alloy is from about 20 at% to about 50 at%, and the content of copper forming the titanium alloy can be from about 50 at% to about 80 at%.

[0135] As shown in FIGS. 18 to 20, a second photoresist pattern (PR2) can be formed on the gate layer (GEa). Using the second photoresist pattern (PR2), the second alloy layer (AL2) and the second metal layer (ML2) can be patterned. That is, the gate layer (GEa) can be patterned to form a gate electrode (GE) and gate wiring.

[0136] When the second alloy layer (AL2) and the second metal layer (ML2) are patterned, the second alloy layer (AL2) and the second metal layer (ML2) can be etched by wet etching.

[0137] FIG. 21 is a cross-sectional view showing an enlarged view of the F region in FIG. 20.

[0138] Referring further to FIG. 21, the thickness (T2) of the second alloy layer (AL2) can be from about 30 Å to about 100 Å. When the thickness (T2) of the second alloy layer (AL2) is from about 30 Å to about 100 Å, in the manufacturing process, the widths of the gate electrode (GE) and the gate wiring (GL) can be controlled or selected (for example, can be easily controlled or selected), the etching time of the second alloy layer (AL2) is reduced, and the manufacturing time of the display device 10 is reduced, so the manufacturing efficiency can be increased.

[0139] Also, the thickness (T4) of the second metal layer (ML2) can be about 1500 Å to 4500 Å. When the thickness (T4) of the second metal layer (ML2) is about 1500 Å to 4500 Å, the second metal layer (ML2) can have relatively little influence on the layer disposed on the second metal layer (ML2). Also, the resistance of the second metal layer (ML2) can become relatively small.

[0140] In one embodiment, by including the titanium alloy in the second alloy layer (AL2), the etching rates of the second metal layer (ML2) and the second alloy layer (AL2) can be made similar. Thus, the skew (SK2), which is the distance between the end of the second photoresist pattern (PR2) and the end of the gate electrode (GE) (or the gate wiring (GL)), can be reduced.

[0141] As shown in FIGS. 13 and 21, the thickness (T5) of the metal pattern (BML) and the thickness (T6) of the gate electrode (GE) can be formed to be substantially the same as each other. By the thickness (T5) of the metal pattern (BML) and the thickness (T6) of the gate electrode (GE) being substantially the same as each other, the metal pattern (BML) and the gate electrode (GE) can have substantially the same resistance.

[0142] After the gate electrode (GE) and the gate wiring (GL) are formed, the second photoresist pattern (PR2) can be removed.

[0143] As shown in FIG. 22, the first insulating layer (IL1) can be patterned. Among the first insulating layer (IL1), the portion that does not overlap with the gate electrode (GE) and the gate wiring (GL) can be etched. Thus, the first insulating layer (IL1) overlaps with the gate electrode (GE) and the gate wiring (GL). However, the present invention is not limited thereto, and the first insulating layer (IL1) can be formed as a whole on the buffer layer (BFR).

[0144] As shown in FIG. 23, a second insulating layer (IL2) may be formed on the buffer layer (BFR) and the active layer (ACT). The second insulating layer (IL2) may be formed to cover the active layer (ACT), the first insulating layer (IL1), and the gate electrode (GE).

[0145] As shown in FIG. 24, a first contact hole may be formed in the buffer layer (BFR) and the second insulating layer (IL2), and a second contact hole and a third contact hole may be formed in the second insulating layer (IL2).

[0146] A source electrode (SE) and a drain electrode (DE) may be formed on the second insulating layer (IL2). The source electrode (SE) may contact the metal pattern (BML) through the first contact hole and may contact the source region of the active layer (ACT) through the second contact hole. The drain electrode (DE) may contact the drain region of the active layer (ACT) through the third contact hole. The active layer (ACT), the gate electrode (GE), the source electrode (SE), and the drain electrode (DE) may form a transistor (TR).

[0147] As shown in FIG. 25, a third insulating layer (IL3) may be formed on the second insulating layer (IL2) to cover the source electrode (SE) and the drain electrode (DE). A fourth contact hole may be formed in the third insulating layer (IL3). A connection electrode (CP) may be formed on the third insulating layer (IL3), and the connection electrode (CP) may contact the drain electrode (DE) through the fourth contact hole.

[0148] A fourth insulating layer (IL4) may be formed on the third insulating layer (IL3) to cover the connection electrode (CP). Thus, a circuit element layer 210 may be formed.

[0149] As shown in FIG. 26, a light-emitting element layer 220 may be formed on the fourth insulating layer (IL4). The circuit element layer 210 and the light-emitting element layer 220 may form a display element layer 200.

[0150] A sealing layer 300 may be formed on the light-emitting element layer 220. Thus, a display device 10 including the substrate 100, the display element layer 200, and the sealing layer 300 may be formed.

[0151] In one embodiment, since the first alloy layer (AL1) contains the titanium alloy, the etching rates of the first metal layer (ML1) and the first alloy layer (AL1) may be the same. Thus, the skew (SK1), which is the distance between the end of the first photoresist pattern (PR1) and the end of the metal pattern (BML), may be reduced, and the width of the metal pattern (BML) may be controlled or selected (for example, may be easily controlled or selected). Similarly, since the first alloy layer (AL1) contains the titanium alloy, the etching rates of the second metal layer (ML2) and the second alloy layer (AL2) may be the same. Thus, the skew (SK2), which is the distance between the end of the second photoresist pattern (PR2) and the end of the gate electrode (GE) (or gate wiring), may be reduced, and the width of the gate electrode (GE) may be controlled or selected (for example, may be easily controlled or selected). Thereby, high resolution can be realized in the display device 10.

[0152] Also, since the first alloy layer (AL1) and the second alloy layer (AL2) contain the titanium alloy, hydrogen diffusing from the first alloy layer (AL1) and the second alloy layer (AL2) into the active layer (ACT) can be prevented. Therefore, the performance of the transistor (TR) may be improved.

Industrial Applicability

[0153] The display device and the manufacturing method according to the embodiment of the present invention can be applied to display devices included in computers, notebook computers, mobile phones, smartphones, smart pads, PMPs, PDAs, MP3 players, and the like.

[0154] In the above, the embodiments of the present invention have been described with reference to the embodiments. However, those having ordinary knowledge in the technical field will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the following claims.

Claims

1. A substrate, a metal pattern including a first alloy layer disposed on the substrate and containing a titanium alloy including at least one of copper and zinc, and a first metal layer disposed on the first alloy layer, an active layer disposed on the metal pattern, a gate electrode including a second alloy layer disposed on the active layer and containing a titanium alloy including at least one of copper and zinc, and a second metal layer disposed on the second alloy layer. The display device is characterized by including these components.

2. The display device according to claim 1, wherein each of the first metal layer and the second metal layer contains copper.

3. The display device according to claim 1, wherein the active layer contains an oxide semiconductor.

4. The display device according to claim 1, wherein the first alloy layer and the second alloy layer contain the same substance as each other.

5. The display device according to claim 1, wherein the content of titanium contained in the titanium alloy is 10 at% to 80 at%, and the content of copper or zinc contained in the titanium alloy is 20 at% to 90 at%.

6. The display device according to claim 5, wherein the content of titanium contained in the titanium alloy is 20 at% to 50 at%, and the content of copper or zinc contained in the titanium alloy is 50 at% to 80 at%.

7. The display device according to claim 1, wherein each of the first alloy layer and the second alloy layer contains a titanium alloy including titanium, copper, and zinc.

8. The display device according to claim 1, wherein the thickness of each of the first alloy layer and the second alloy layer is 30 Å to 100 Å.

9. The display device according to claim 1, wherein the thickness of each of the first metal layer and the second metal layer is 1500 Å to 4500 Å.

10. The display device according to claim 1, wherein the thickness of the metal pattern is the same as the thickness of the gate electrode.

11. Applying a first alloy layer containing a titanium alloy including at least one of copper and zinc on a substrate; Applying a first metal layer on the first alloy layer; Patterning the first alloy layer and the first metal layer to form a metal pattern; Applying an active layer on the first metal layer; Applying a second alloy layer containing a titanium alloy containing at least one of copper or zinc on the active layer; Applying a second metal layer on the second alloy layer; A method for manufacturing a display device, comprising patterning the second alloy layer and the second metal layer to form a gate electrode.

12. The method for manufacturing a display device according to claim 11, wherein the active layer is formed of an oxide semiconductor.

13. The method for manufacturing a display device according to claim 11, wherein the step of patterning the first alloy layer and the first metal layer to form the metal pattern includes etching the first alloy layer and the first metal layer by wet etching.

14. The method for manufacturing a display device according to claim 11, wherein the step of patterning the second alloy layer and the second metal layer to form the gate electrode includes etching the second alloy layer and the second metal layer by wet etching.

15. The method for manufacturing a display device according to claim 11, wherein the thickness of the metal pattern and the thickness of the gate electrode are formed to be the same.

16. The method for manufacturing a display device according to claim 11, wherein the first metal layer and the second metal layer are formed of copper.

17. The first alloy layer and the second alloy layer are formed of the titanium alloy, The content of titanium forming the titanium alloy is 10 at% to 80 at%, and the content of copper or zinc forming the titanium alloy is 20 at% to 90 at%, the method for manufacturing a display device according to claim 11.

18. The method for manufacturing a display device according to claim 17, wherein the content of titanium forming the titanium alloy is 20 at% to 50 at%, and the content of copper or zinc forming the titanium alloy is 50 at% to 80 at%.

19. The method for manufacturing a display device according to claim 11, wherein the thickness of each of the first alloy layer and the second alloy layer is formed to be 30 Å to 100 Å.

20. The method for manufacturing a display device according to claim 11, wherein the thickness of each of the first metal layer and the second metal layer is formed to be 1500 Å to 4500 Å.

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