Display pixels comprising light-emitting diodes and display screens having such display pixels

Abstract

The present disclosure relates to a display pixel comprising an electronic circuit comprising at least one light emitting diode, a memory circuit for storing at least one digital signal, and a driver circuit configured to drive the light emitting diode by pulse width modulation, in a first operating mode, by switching the light emission on or off during first different durations (TA5, TA4, TA3, TA2, TA1) according to the logical state of the bits of the digital signal, or in a second operating mode, by switching the light emitting diode on or off during second different durations (TB5, TB4, TB3, TB2, TB1) that are at least partially different from the first duration according to the logical state of the bits of the digital signal.

Description

Technical Field

[0001] The present disclosure relates to display pixels including light emitting diodes and display screens having such display pixels.

Background Art

[0002] Pixels of an image correspond to unit elements of the image displayed by a display screen. For display of a color image, the display screen generally includes at least three components, also called display sub-pixels, each emitting a light emission, called an image pixel color component of a substantially single color (e.g., red, green, and blue), for display of each pixel of the image. The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with a colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for display of a pixel of the image is called a display pixel of the display screen. Each display sub-pixel may include a light source, particularly a light emitting diode.

[0003] The display pixels may be dispersed in an array, and each display pixel is located at the intersection of a row (also called a line) and a column of the array. Electrodes are provided along the rows and columns to connect each display pixel to a control circuit. Generally, each row of display pixels is continuously selected by signals transmitted along the row electrodes, and the display pixels of the selected row are programmed to display a desired image pixel by signals transmitted along the column electrodes.

[0004] The human eye is much more sensitive to changes in dark tones than to similar changes in bright tones. A photodetector typically provides an analog electrical image pixel signal that has a substantially linear relationship to the number of photons hitting the sensor. When a display system operates in a digital driving method such as pulse width modulation operation, a large number of bits would be required for the digital image pixel signal of dark tones to be described with sufficient accuracy. Digitization with a small number of bits results in posterization of the displayed image for dark tones.

[0005] To optimize the use of bits when encoding an image and / or to optimize the bandwidth used for transmitting the image, a non-linear operation generally called gamma encoding or gamma compression is applied to the image pixel signal provided by the photodetector, so that the native image sensor tone levels are redistributed to be more perceptually uniform to the human eye. Gamma encoding is defined, for example, by the following power law equation: Vout = Vin γ Here, the non-negative real input value Vin is raised to the power of γ to obtain the output value Vout. For example, Vin and Vout are in the range of 0 to 1. The exponent γ is usually equal to 1 / 2.2. To display an image pixel, an inverse non-linear operation called gamma decoding or gamma expansion is applied to the image pixel signal to effectively convert it back to the light from the original scene.

[0006] Figure 1 shows an example of an ideal gamma decoding function Igam corresponding to a power law equation with an exponent equal to 2.2, and shows a linear function Lin for comparison. In Figure 1, the y-axis indicates the number of output levels, and the number of levels of the luminance L of the image pixel is shown on the x-axis. To make the tones appear smooth and continuous in the image, it is usually sufficient to be able to encode at least 256 different levels for the luminance L, which theoretically requires only 8 bits.

[0007] However, when gamma encoding and gamma decoding are used, when the display system operates in a digital driving method such as pulse width modulation operation, posterization may still appear on the display image in very dark gradations.

[0008] FIG. 2 shows an enlarged view of the ideal gamma decoding function Igam of FIG. 1 and the gamma decoding function Rgam10 actually obtained by 10-bit encoding. As shown in FIG. 2, the curve Rgam10 is a step curve. This means that, for example, an image pixel having an ideal luminance L in the range of 0 to 8 results in the display of an image pixel having an actual luminance L equal to 0, or an image pixel having an ideal luminance L in the range of 9 to 13 results in the display of an image pixel having an actual luminance L having a constant value. At least 16-bit encoding should be used to correctly display dark gradations even when gamma encoding and gamma decoding are used. However, an increase in the number of bits of the digital image pixel signal requires a higher bandwidth interface for video data, which is not desirable. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] An object of an embodiment is to provide a display pixel including a light emitting diode and a display screen including such display pixels that overcome all or part of the drawbacks in an existing display pixel including a light emitting diode and a display screen including such display pixels.

[0010] Another object is to reduce and further suppress posterization of a display image for dark gradations.

[0011] Another object is to keep the number of bits of the digital image pixel signal low. MEANS FOR SOLVING THE PROBLEM

[0012] One embodiment provides a display pixel comprising at least one light emitting diode, a memory circuit storing at least one digital signal, and a driver circuit configured to drive the light emitting diode by pulse width modulation, in a first operating mode, by switching the light emitting diode on or off for different first durations according to the logical state of the bits of the digital signal, or in a second operating mode, by switching the light emitting diode on or off for different second durations that are at least partially different from the first duration according to the logical state of the bits of the digital signal.

[0013] This makes it possible to increase the number of different durations for controlling the light emitting diode by pulse width modulation without increasing the number of bits of the digital signal, and thus without increasing the bandwidth interface for video data.

[0014] According to an embodiment, the electronic circuit is configured to switch between a first operating mode and a second operating mode according to the logical state of a first binary signal. This can improve the encoding accuracy of the pixel image for only the dark tones to which the human eye is most sensitive.

[0015] According to an embodiment, the electronic circuit is configured to receive a first binary signal from outside the display pixel. The first binary signal can advantageously be determined by a control circuit of a display screen comprising the display pixel.

[0016] According to an embodiment, the digital signal includes NB bits bi i where i ranges from 1 to NB, bit b NB is the most significant bit, bit b1 is the least significant bit, the first duration includes NB first durations TA i with increasing values, the second duration includes NB second durations TB i with increasing values, and the driver circuit, in the first operating mode, the NB first durations TA iBy switching the light-emitting diode on or off therein, the light-emitting diode is configured to be driven by pulse-width modulation, and the light-emitting diode is bit b i is switched on during a first duration TA when in a first logic state i and is switched off during the first duration TA when bit b i is in a second logic state different from the first logic state. The driver circuit, in a second operating mode, switches the light-emitting diode on or off during NB second durations TB i such that the light-emitting diode is switched on during a second duration TB when bit b i is in a first logic state and is switched off during the second duration TB when bit b i is in a second logic state. i is switched on during a second duration TB when in a first logic state i and is switched off during the second duration TB when bit b i is in a second logic state.

[0017] According to an embodiment, at least some of the second durations are shorter than the first duration. According to an embodiment, at least one of the second durations is the same length as one of the first durations. According to an embodiment, at least the longest second duration is the same length as one of the first durations.

[0018] According to an embodiment, the display pixel includes at least a first conductive pad connected to the electronic circuit for receiving a second binary signal including pulses, some of the pulses being away from a first duration, some of the pulses being away from a second duration, and the electronic circuit is configured to turn on or off the light-emitting diode during the first duration or the second duration based on the pulses. The electronic circuit of each display pixel can advantageously generate a pulse-width modulation control signal in a first operating mode and a second operating mode based on the pulses. According to an embodiment, the pulses include a first pulse, the first pulse being away from a first duration, the pulses further include a second pulse, a second pulse follows each first pulse, and the first pulse and the subsequent second pulse are away from a second duration. The duration of the period in pulse-width modulation control in the first operating mode or the second operating mode does not advantageously increase compared to the pulse-width modulation control in a single operating mode.

[0019] According to an embodiment, the electronic circuit is configured to generate a third binary signal having a logic state changed at each first pulse and each second pulse from the second binary signal. Thus, the third binary signal can be set to a logic level "1" during the second duration.

[0020] According to an embodiment, the memory circuit includes a shift register configured to store a digital signal and provide consecutive bits of the stored digital signal clocked by the third binary signal.

[0021] According to an embodiment, the display pixel includes a controllable current source that supplies power to the light-emitting diode and is controlled by a fourth binary signal.

[0022] According to an embodiment, the electronic circuit has a first input for receiving the third binary signal, a first NOR-type logic gate having a second input for receiving the first binary signal, and bit b iIt includes a second NOR-type logic gate that has a first input for receiving the logical complement of [[ID=]], a second input connected to the output of the first logic gate, and provides a fourth binary signal.

[0023] According to an embodiment, the display pixel comprises at least a second conductive pad for receiving a fifth binary signal, connected to the electronic circuit, and the electronic circuit is configured to update the digital signal stored in the memory circuit from the second signal.

[0024] Another embodiment The previously disclosed display pixels arranged in rows and columns; A first conductive track extending along the row and connected to the electronic circuit of the display pixel; A second conductive track extending along the column and connected to the electronic circuit of the display pixel; and A control circuit connected to the first conductive track and the second conductive track provides a display screen.

[0025] According to an embodiment, the electronic circuit of each display pixel is configured to switch between a first and a second operating mode according to the logical state of the first binary signal. The control circuit is configured to determine the first binary signal for each digital signal and provide the first binary signal to the display pixel.

[0026] According to an embodiment, the control circuit is configured to supply a timing signal on each first conductive track, and the electronic circuit of each display pixel is configured to turn on or off the light-emitting diode during different first durations in the first operating mode, or during different second durations in the second operating mode, to generate a driving signal for driving the light-emitting diode by pulse-width modulation from the timing signal. The generation of the first and second durations by each display pixel is performed from the timing signal. The structure of the electronic circuit can advantageously be simplified.

[0027] According to an embodiment, the control circuit is configured to supply a timing signal equal to a second binary signal including at least a first pulse onto each first conductive track, the first pulse having a first duration and being spaced apart from a second pulse, a second pulse following each first pulse, and the first pulse and the subsequent second pulse being spaced apart from a second duration. A single timing signal is advantageously used by the display pixels to obtain the first duration and the second duration. Thereby, advantageously, the number of conductive pads of the display pixels can be reduced.

Brief Description of the Drawings

[0028] The foregoing features and advantages, as well as others, are described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings:

[0029]

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[0030] Similar features are designated by similar reference numerals in the various figures. In particular, structural and / or functional features that are common among the various embodiments may have the same reference numeral and may impart the same structural, dimensional, and material characteristics. For clarity, only steps and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0031] Unless otherwise indicated, when referring to two elements connected to each other, this means a direct connection without intermediate elements other than conductors, and when referring to two elements coupled to each other, this means that these two elements can be connected or that they can be coupled via one or more other elements. Also, a signal that alternates between a first steady state, for example a low logic state denoted as "0", and a second steady state, for example a high logic state denoted as "1", is called a "binary signal". The high and low states of different binary signals in the same electronic circuit may be different. In practice, a binary signal may correspond to a voltage or current that may not be completely constant in the high or low state. Also, in the following description, the source and drain of a MOS transistor are referred to as the "power terminals" of an insulated gate field effect transistor or a MOS transistor.

[0032] Also, unless otherwise specified, when referring to the voltage of the conductive pad, the difference between the potential at the conductive pad and the reference potential (e.g., a ground potential equivalent to 0 V) is considered.

[0033] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "degree" mean within 10%, preferably within 5%. Further, the expression "substantially constant" means changing by less than 10% over time with respect to the reference value.

[0034] In the following specification, embodiments for a color display screen with color display pixels are disclosed, and each display pixel includes a light-emitting diode adapted to emit radiation of different colors. However, these embodiments are also applicable to a monochromatic display screen with monochromatic display pixels, and each monochromatic display pixel includes only one or a plurality of light-emitting diodes adapted to emit radiation of a single color.

[0035] FIG. 3 shows a partial and schematic view of an embodiment of the display screen 10. The display screen 10 includes display pixels 12 arranged in, for example, M rows and N columns i,j where M is an integer that varies from 1 to 8,000, N is an integer that varies from 1 to 16,000, i is an integer that varies from 1 to M, and j is an integer that varies from 1 to N. As an example, in FIG. 3, M and N are equal to 6. Each display pixel 12 i,j is coupled to a low reference potential Gnd, such as a grounded source, via an electrode 14 i and to a source of a high reference potential Vcc via an electrode 16 j . As an example, the electrode 14 i is shown as being aligned along the rows of FIG. 3, and the electrode 16 jare shown aligned along a column in FIG. 3, although an inverse layout is also possible. The power supply voltage of the display screen corresponds to a voltage between a high reference potential Vcc and a low reference potential Gnd. The power supply voltage depends, inter alia, on the arrangement of the light emitting diodes and on the technology for manufacturing the light emitting diodes. By way of example, the power supply voltage may be in the order of 4V to 5V.

[0036] For each row, display pixels 12 in the row i,j At least one row electrode 18 i For each column, the display pixels 12 in the column i,j At least one column electrode 20 j The display screen 10 is coupled to row electrodes 18. i , each row electrode 18 i Timing signal Com i The display screen 10 includes a timing circuit 22 adapted to transmit a signal to the column electrodes 20. j Each column electrode 20 is coupled to j Data signal on j The timing circuit 22 and the data transmission circuit 24 are controlled by a circuit 26 which may, for example, comprise a microprocessor. In particular, the circuit 26 controls the display pixels 12 i,j Receives video data to be displayed by.

[0037] Typically, each row of display pixels is selected in sequence and the display pixels of the selected rows are programmed to display a desired image pixel. In a known method for selecting display pixels, a timing circuit 22 clocks the row electrodes 18 i Upper timing signal Com i Transmits and displays 12 pixels i,j , and the data transmission circuit 24 is adapted to sequentially select each row of the selected display pixels 12. i,j Each column electrode 20 represents color digital data stored in j Data signal on j The signal is adapted to transmit

[0038] FIG. 4 shows the display pixels 12 of the display screen 10 i,j and is a block diagram of an embodiment. For a color display screen, the display pixel 12 i,j includes at least three light-emitting diodes that emit different colored lights, and a single light-emitting diode LED is shown in FIG. 4. Each light-emitting diode LED is coupled in series to a controllable current source CS that includes, for example, a MOS transistor. In this example, for each light-emitting diode LED, the anode of the light-emitting diode LED receives the high reference potential Vcc received by the conductive pad P_Vcc of the display pixel 12 i,j , and the cathode of the light-emitting diode LED is coupled to the terminal of the controllable current source CS, and the other terminal of the controllable current source CS receives the low reference potential Gnd received at the conductive pad P_Gnd of the display pixel 12 i,j . As a modification, the cathode of the light-emitting diode LED receives the low reference potential Gnd, the anode of the light-emitting diode LED is coupled to the terminal of the controllable current source CS, and the other terminal of the controllable current source CS receives the high reference potential Vcc.

[0039] The display pixel 12 i,j further includes a circuit 40 for driving the controllable current source CS. The driver circuit 40 may particularly include electronic components such as MOS transistors. In order to supply power to the electronic components of the driver circuit 40, it may be desirable to use a reduced power supply voltage of less than 4V (for example, about 1V or 1.8V), and this reduced power supply voltage corresponds to, for example, a voltage that is likely to be applied between the power supply terminals of the MOS transistor. For this purpose, the display pixel 12 i,j may include a circuit 42 (Vdd generation) for transmitting the reduced power supply voltage Vdd used for the power supply of the driver circuit 40 from the power supply voltage Vcc. The circuit 42 includes, for example, a voltage divider.

[0040] According to the embodiment, the timing signal Com received by the conductive pad P_Row of each display pixel 12 i,j iis a binary signal that alternates between a low logic state "0" and a high logic state "1", where the low logic state corresponds to a low reference potential Gnd, and the high logic state corresponds to a low voltage, for example, about 1V, that is smaller than the reduced power supply voltage Vdd. Each display pixel 12 i,j The data signal Data received at the conductive pad P_Col of i,j j is a binary signal that alternates between a low logic state "0" and a high logic state "1", where the low logic state corresponds to a low reference potential Gnd, and the high logic state "1" corresponds to a low voltage, for example, about 1V, that is smaller than the reduced power supply voltage Vdd.

[0041] The driver circuit 40 includes a circuit 46 (mode selection), and the circuit 46 is coupled to the conductive pad P_Col that receives the data signal Data j and is coupled to the conductive pad P_Row that receives the timing signal Com i and is coupled to the conductive pad P_Row that receives the timing signal Com i or the data signal Data j and transmits the clock signal Clk from the data signal Data or the data signal Data from the data signal Data to the memory circuit 48 (color data register), or transmits the modulation timing signal PWM to the circuit 50 (LED driver) for controlling the controllable current source CS associated with each light emitting diode LED from the timing signal Com j The modulation timing signal PWM can be made equal to the timing signal Com during the display phase. The clock signal Clk can be made equal to the timing signal Com during the programming phase. i from the timing signal Com. i The modulation timing signal PWM can be made equal to the timing signal Com during the display phase. The clock signal Clk can be made equal to the timing signal Com during the programming phase. i from the timing signal Com.

[0042] When clocked by the clock signal Clk, the memory circuit 48 is configured to store the digital color signals R, G, B based on the received digital data Data. The digital color signals R, G, B represent the image pixel color components to be displayed. Each color digital signal R, G, B includes NB bits called bit j with j in the range of 1 to NB NBis the most significant bit and bit1 is the least significant bit. The circuit 50 (LED driver) is configured to control a controllable current source CS coupled to a light emitting diode LED with the digital color signals R, G, B and binary signals I_red, I_green, and I_blue derived from the modulation timing signal PWM.

[0043] Display Pixels 12 i,j A known method for driving a light emitting diode LED of a display pixel 12 i,j It is a pulse-width modulated drive in which each light-emitting diode LED is supplied with a pulse of current having a constant intensity, the duration of the pulse depending on the stored digital color signals R, G, B.

[0044] FIG. 5 illustrates an example of a display pixel 12 of FIG. 4 for displaying four different digital color signals R using the known pulse width modulation drive. i,j 1 shows a timing diagram of signals I_red_1, I_red_2, I_red_3, and I_red_4 and a modulation timing signal PWM corresponding to the signal I_red provided by the circuit 50 of FIG. 1. For this purpose, during the display phase, the timing signal PWM exhibits successive pulses PA in the logic state "1" that rate the operation of the circuit 50 for the control of each light-emitting diode LED by pulse width modulation. The number of pulses PA in the succession of pulses may be equal to NB+1.

[0045] As an example, when the current source CS corresponds to a MOS transistor, this transistor is turned on or off at the rate of the pulses of the modulation timing signal PWM according to the logical value "0" or "1" of each bit of the color signal R starting from the most significant bit of the color signal R, and this transistor is kept on or off until the next pulse of the modulation timing signal PWM. The duration TA between two successive pulses PA of the modulation timing signal PWM i(where \(i\) is in the range of \(1\) to \(NB\)) is divided by \(2\) each time, so that the total duration for which the light-emitting diode is on depends on the value of the digital color signal \(R\). The consecutive pulses \(PA\) of the modulation timing signal \(PWM\) can be repeated until the display of another image pixel. In that case, the consecutive pulses \(PA\) of the modulation timing signal \(PWM\) from the most significant bit to the least significant bit of the color signal \(R\) form a display period, and the display phase includes more than one display period.

[0046] In FIG. 5, as an example, the number of pulses \(PA\) in the display period of the modulation timing signal \(PWM\) is equal to \(8\), and only one display period is shown. The signal \(I\_red\_1\) is obtained for the display of the image pixel color component corresponding to the digital color signal \(R\) equal to "1010101". The signal \(I\_red\_2\) is obtained for the display of the image pixel color component corresponding to the digital color signal \(R\) equal to "0101010". The signal \(I\_red\_3\) is obtained for the display of the image pixel color component corresponding to the digital color signal \(R\) equal to "1111111". The signal \(I\_red\_4\) is obtained for the display of the image pixel color component corresponding to the digital color signal \(R\) equal to "0000000".

[0047] According to an embodiment, the modulation timing signal \(PWM\) is changed with respect to a known modulation timing signal \(PWM\), so that more different durations than \(NT\) are available for switching the on / off of the light-emitting diode, where \(NT\) is an integer that is strictly greater than \(NB\), preferably greater than \(NB + 1\), and most preferably greater than \(NB+2\). The display method according to this embodiment in which the modified modulation timing signal \(PWM\) provides \(NT\) different durations and the digital color signal includes \(NB\) bits is equivalent to a display method in which a known modulation timing signal \(PWM\) provides \(NT\) different durations and the digital color signal includes \(NT\) bits.

[0048] FIG. 6 shows the display pixel 12 of FIG. 4 in which the light-emitting diode \(LED\) is controlled by pulse-width modulation i,jFig. 6 shows the timing diagrams of signals PWM, PWM2, I_red_W, and I_red_B according to an embodiment of a method for driving a light-emitting diode LED. Signals I_red_W and I_red_B correspond to signal I_red provided by circuit 50 of Fig. 4 for the display of two different digital color signals R i,j Signal PWM2 is a signal generated by circuit 40 of Fig. 4 for display pixel 12 i,j In Fig. 6, the digital color signal R includes bits 1 to 5 which are 5 bits, bit 5 is the most significant bit, and bit 1 is the least significant bit.

[0049] According to an embodiment, the modulation timing signal PWM includes alternating first and second pulses for a display period, and each first pulse PA is followed by a second pulse PB. The first pulse PA corresponds to the pulse PA of the modulation timing signal disclosed previously in connection with Fig. 5, i.e., the duration TA i (where i ranges from 1 to NB) is divided by 2 each time. The duration TB j (where j ranges from 1 to NB) between the first pulse PA and the subsequent second pulse PB of the modulation timing signal PWM is divided by 2 with respect to the duration between the preceding consecutive first pulse PA and the second pulse PB. Signal PWM2 includes a rising edge at each first pulse PA and a falling edge at each second pulse PB. Thus, the pulses of signal PWM2 have a duration TB NB ~TB1.

[0050] According to an embodiment, the period includes NB + 1 first pulses PA and NB + 1 second pulses PB. Thus, there are NB decreasing durations TA i (where i ranges from 1 to NB) between each pair of consecutive first pulses PA, and there are NB decreasing durations TB i (where i ranges from 1 to NB) between each pair of consecutive first pulses PA and second pulses PB.

[0051] More generally, the timing signal PWM includes pulses, and some of the pulses have a first duration TA i (where i ranges from 1 to NB) and are separated from some of the pulses having a second duration TB i (where i ranges from 1 to NB). For example, the pulses used to determine the first duration TA i can precede or follow the pulses used to determine the second duration TB i . However, the previously disclosed embodiment in which the first and second pulses PA, PB alternate advantageously allows the duration of the display period not to increase when only the first duration TA i is used.

[0052] According to an embodiment, in the display period, one or more (but not all) of the durations TB1 to TB NB continue for the same length as at least one of the durations TA NB to TA1. According to an embodiment, the duration TB NB between the first pulse PA at the start of the display period and the subsequent second pulse PB is the same length as the duration TA NB to TA1 between two consecutive first pulses PA near the end of the display period, for example, the duration between the second-to-last first pulse and the last first pulse of the display period, or the duration between the third-to-last first pulse and the second-to-last first pulse of the display period. The group including all the durations of TA NB to TA1 and TB NB to TB1 has NT different values of duration, and NT is strictly more than NB and strictly less than 2*NB.

[0053] In FIG. 6, the modulated timing signal PWM includes six first pulses PA alternating with six second pulses PB. The duration TB NBis the same length as the duration TA2 between the third first pulse and the second first pulse from the end of the display period, and the duration TB between the second consecutive first pulse PA and the second pulse PB from the start of the display period NB-1 is the same length as the duration TA1 between the second first pulse and the last first pulse from the end of the display period. The last second pulse PB following the last first pulse PA shown in FIG. 6 is not used, so that even if in practice it may be easier to generate a second pulse PB after each first pulse PA to simplify the generation of the signal PWM2, it can be absent.

[0054] According to an embodiment, the index IB is associated with each value of the digital color signals R, G, B. The index IB can be binary. During the display operation, according to the logical state of the index IB, the duration TA NB ~TA1 or the duration TB NB ~TB1 is used to drive the light emitting diode LED.

[0055] According to an embodiment, the index IB is determined by the circuit 26 corresponding to the image pixel to be displayed by the display pixel 12 i,j for each initial digital color signal determined by the circuit 26, and then sent to the display pixel 12 i,j The index IB received by the display pixel 12 i,j can be stored in the memory of the display pixel 12 i,j According to an embodiment, the index IB can be determined by the circuit 26 based on one bit or a plurality of bits among bit1~bit NB of the initial digital color signals R, G, or B determined by the circuit 26. For example, the most significant bit bit NB of the initial digital color signals R, G, or B, the second most significant bit bit NB-1 the third most significant bit bit NB-2At least one of them is determined by circuit 26. A logic gate can be used to determine index IB by circuit 26. According to an embodiment, index IB is in a first logic state, for example, logic state "1", for an image pixel having a bright tone, and index IB is in a second logic state, for example, logic state "0", for an image pixel having a dark tone. According to an embodiment, index IB is all bits b of the initial digital color signal R, G, or B determined by circuit 26 NB ~b NB-NIB (NIB is an integer and equal to, for example, 0, 1, or 2) is in logic state "0", it can be set to logic state "0", and index IB is bit b of the initial digital color signal R, G, or B determined by circuit 26 NB ~b NB-NIB (NIB is an integer and equal to, for example, 0, 1, or 2) if at least one of them is in logic state "1", it can be set to logic state "1".

[0056] According to an embodiment, according to index IB determined based on the initial digital color signal R, G, or B, circuit 26 can calculate a new digital color signal R, G, or B, and the data signal Data sent to pixel 12 i,j corresponds to the new digital color signal R, G, or B then. According to an embodiment, the new digital color signal R, G, or B is determined when index IB corresponds to an image pixel having a dark tone, and the new digital color signal R, G, or B is not determined when index IB corresponds to an image pixel having a bright tone. When the new digital color signal R, G, or B is not determined, the data signal Data sent to pixel 12 j is then corresponding to the new digital color signal R, G, or B. According to an embodiment, the new digital color signal R, G, or B is determined when index IB corresponds to an image pixel having a dark tone, and when index IB corresponds to an image pixel having a bright tone, the new digital color signal R, G, or B is not determined. When the new digital color signal R, G, or B is not determined, pixel 12 i,j the data signal Data sent to jThen, it corresponds to the initial digital color signals R, G, or B. According to an embodiment, when the index IB corresponds to an image pixel having a dark tone, the new digital color signals R, G, or B are determined based on the initial digital color signals R, G, or B. As an example, when the index IB corresponds to an image pixel having a dark tone, the new digital color signals R, G, or B are determined by circuit 26 such that the image pixel information content is encoded over all NB bits of the digital color signals R, G, or B.

[0057] According to an embodiment, the index IB uses the data signal Data in addition to the bits of the initial or new digital color signals R, G, B j to send to the display pixel 12 i,j As an example, when the digital color signals R, G, B are encoded on NB bits and the index IB is encoded on one bit, the data signal Data j is used to send NB + 1 bits to the display pixel 12 i,j for each digital color signal R, G, B. According to another embodiment, the index IB uses both the data signal Data j and the timing signal Com i to send to the display pixel 12 j by providing a simultaneous specific pattern to the data signal Data i and the timing signal Com i,j . According to another embodiment, the index IB uses the data signal Data j to send to the display pixel 12 i,j by a specific determination of one of one or more bits of the digital color signals R, G, B, for example, the least significant bit bit1, the second least significant bit bit2, or the third least significant bit bit3 of the digital color signals R, G, B, according to the determined logic. The display pixel 12 i,j is then adapted to extract the index IB from the stored digital color signals R, G, B.

[0058] According to the embodiment, the index IB is in the logical state "1" for the image pixels having a bright tone, and the index IB is in the logical state "0" for the image pixels having a dark tone. More precisely, in the first operation mode, in order to display the image pixels having a bright tone (index IB in the logical state "1"), the duration TA NB ~TA1 is used to drive the light-emitting diode LED, and the current source CS that supplies power to the light-emitting diode LED is the most significant bit b of the digital color signal R, G, or B NB starting from each bit b of the digital color signal R, G, or B NB ~b1 is turned on or off according to the logical value "0" or "1", and in the second operation mode, in order to display the image pixels having a dark tone (index IB in the logical state "0"), the duration TB NB ~TB1 is used to drive the light-emitting diode LED, and the current source CS that supplies power to the light-emitting diode LED is the most significant bit b of the digital color signal R NB starting from each bit b of the digital color signal R, G, or B NB ~b1 is turned on or off according to the logical value "0" or "1", and is turned off during two consecutive durations TB NB ~TB1. As an example, in FIG. 6, the signal I_red_W is obtained using the duration TA NB ~TA1, and the signal I_red_B is obtained using the duration TB NB ~TB1. NB ~TA1, and the signal I_red_B is obtained using the duration TB NB ~TB1.

[0059] As a modification, when the current source CS corresponds to a MOS transistor, this transistor can be turned on or off according to the logical value "0" or "1" of each bit of the color signals R, G, or B from the least significant bit to the most significant bit during the duration TA i or TB j . In that case, the duration TA between two consecutive first pulses PA of the modulation timing signal PWM in the display period i(where \(i\) is in the range of \(NB\) to \(1\)) is multiplied by 2 each time, and is the duration \(TB\) between the first pulse \(PA\) and the subsequent second pulse \(PB\) of the modulation timing signal \(PWM\). j (where \(j\) is in the range of \(NB\) to \(1\)) is multiplied by 2 with respect to the duration between the preceding consecutive first pulse \(PA\) and second pulse \(PB\).

[0060] The display method according to this embodiment, where the modulation timing signal \(PWM\) includes the first and second pulses \(PA\), \(PB\), and the digital color signal includes \(NB\) bits, is such that the modulation timing signal \(PWM\) includes only the first pulse, and the digital color signal includes \(NT\) bits \(b\) j ’(where \(j\) is in the range of \(1\) to \(NT\)). Therefore, the color depth of \(NT\) bits is advantageously obtained using a color digital image encoded on \(NB\) bits. In FIG. 6, the bits \(b\) i (where \(i\) is in the range of \(1\) to \(5\)) and the bits \(b\) j ’(where \(j\) is in the range of \(1\) to \(8\)) are shown.

[0061] FIG. 7 shows a block diagram of an embodiment of a part of the circuit 40 in FIG. 4.

[0062] The circuit 40 includes - a circuit 60 configured to receive the modulation timing signal \(PWM\) and provide the signal \(PWM2\); - a storage circuit 48 including a shift register clocked by the signal \(PWM2\) in which the digital color signals \(R\), \(G\), or \(B\) are stored and which provides the binary signal / b j at its output \(QB\); - a circuit 62 configured to provide the binary index \(IB\); and - a logic circuit 64 that receives the signal / b i , \(IB\), and \(PWM2\) and is configured to provide the control binary signals \(I\_red\), \(I\_green\), or \(I\_blue\) and includes.

[0063] The binary signal / b i is the binary bit \(b\) of the digital color signal \(R\), \(G\), or \(B\) iis the logical complement of. When clocked by signal PWM2, shift register 48 has the most significant bit b NB starting from the complement of bit b i (where i ranges from NB to 1) which is the logical complement of bit / b i and continuously provides it at its output QB. Circuit 60 provides signal PWM2 which includes the rising edge in each first pulse PA and the falling edge in each second pulse PB.

[0064] According to an embodiment, circuit 62 comprises a memory in which index IB is stored when received by display pixel 12 i,j . According to an embodiment, index IB is stored in shift register 48 and is used to drive light emitting diode LED by pulse width modulation with the shortest of durations TA1 or TB1 so that it has substantially no influence on the total light emission duration of light emitting diode LED. As an example, when index IB is equal to the logical state "1" for a bright tone and is stored in shift register 48, driving light emitting diode LED by pulse width modulation with the shortest duration TA1 associated with index IB equal to "1" has substantially no influence on the total duration for which light emitting diode LED is on. The shortest duration TA1 is advantageously set as low as possible.

[0065] FIG. 8 shows a block diagram of an embodiment of logic circuit 64 of FIG. 7. Logic circuit 64 - has a first input for receiving binary signal PWM2 and a second input for receiving binary index IB, a first NOR-type logic gate NOR1; and - has a first input for receiving binary signal / b i and a second input for receiving the binary signal provided at the output of the first logic gate NOR1, and a second NOR-type logic gate NOR2 for providing control binary signal I_red (or I_green or I_blue) is provided.

[0066] In this embodiment, in the first operation mode, for bright gradations, the binary index IB is set to the logical value "1". Therefore, the output of the first logic gate NOR1 remains at the logical value "0" throughout the entire display period, and the output I_red (or I_green or I_blue) of the second logic gate NOR2 is the binary signal / b i equal to the binary logical complement of, that is, the bit b i equal to.

[0067] Since the shift register 48 is clocked by the signal PWM2, the logic circuit 64 preferably provides the NB bits of the digital color signal R clocked by the signal PWM2 at each rising edge of the signal PWM2. The rising edge of the signal PWM2 is simultaneous with the rising edge of the first pulse PA of the modulation timing signal PWM. Then, pulse width modulation is obtained in the first operation mode having the duration TA NB ~TA1.

[0068] In this embodiment, in the second operation mode, for dark gradations, the binary index IB is set to the logical value "0". Therefore, the output of the first logic gate NOR1 is equal to the logical complement of the binary signal PWM2. When the signal PWM2 is in the logical state "0", the output of the first logic gate NOR1 is equal to the logical state "1", and the output I_red of the second logic gate NOR2 is equal to the logical state "0". The light-emitting diode LED is then switched off. When the signal PWM2 is in the logical state "1", that is, between each first pulse PA and the subsequent second pulse PB, the output of the first logic gate NOR1 is set to the logical value "0", and the output I_red of the second logic gate NOR2 is the binary signal / b i equal to the logical complement of, that is, the bit b i of the digital color signal R stored in the shift register 48. NB equal to. Then, pulse width modulation is obtained in the second operation mode having the duration TB

[0069] As an example, Tables 1-1 to 1-4 below are - In the first column titled "Gray Scale (8 bits)", 256 gray scale values in decimal notation that can be encoded with 8 bits; - In the second column titled "Ideal Linear (9 bits)", the corresponding ideal values obtained in decimal notation after linear transformation; - In the third column titled "Ideal 2.2 (9 bits)", the corresponding ideal values obtained in decimal notation after gamma transformation with γ equal to 2.2; - In the fourth column titled "Actual (9 bits)", the corresponding actual values in decimal notation after gamma transformation with γ equal to 2.2 that can be encoded with 9 bits; - In the fifth column titled "Actual (9 bits) Binary without Change", the same values as in the fourth column in binary notation; - In the sixth column titled "Index IB", the index value IB associated corresponding to the values in the fifth column; - In the seventh column titled "Actual (9 bits) Binary with Change", the display pixel 12 i,j to which the 9-bit digital color signal is sent; - In the eighth column titled "Actual (9 + 1 bits)", the actual values obtained in decimal notation corresponding to the 9-bit digital color signal in the seventh column is provided.

[0070] In Tables 1-1 to 1-4, for all bits b NB ~b NB-2 of the digital color signals R, G, or B, if they are in the logical state "0", the index IB is set to the logical state "0", and for bits b NB ~b NB-2If at least one of them is in the logical state "1", the index IB is set to the logical state "1". When the index IB is set to the logical state "0", a new digital color signal R, G, or B is determined, and when the index IB is set to the logical state "0", the digital color signals R, G, or B do not change. The new digital color signals R, G, or B are obtained by encoding the image pixel information content over all 9 bits of the digital color signals R, G, or B, i.e., the bits b NB ~b NB-2 of the digital color signals R, G, or B that should originally be equal to the logical state "0", and are used to generate more values at darker tones when the index IB is set to the logical state "0". As an example, when the second duration TB i corresponds to the first duration TA i divided by 8, the new digital color signals R, G, or B are determined by multiplying the original image pixel values by 8.

[0071]

Table 1-1

[0072]

Table 1-2

[0073]

Table 1-3

[0074]

Table 1-4

[0075] Figure 9 is a diagram similar to Figure 2, showing an enlarged view of the ideal gamma decoding function Igam of Figure 2 and the gamma decoding function Rgam9 actually obtained using 9-bit encoding.

[0076] Figure 10 shows an enlarged view of the ideal gamma decoding function Igam of Figure 1 and the gamma decoding function Rgam9+1 actually obtained in an embodiment of a method for displaying image pixels corresponding to Tables 1-1 to 1-4, previously disclosed in connection with Figure 6. Curve Rgam9+1 follows curve Igam more closely than curve Rgam9 and also more closely than curve Rgam10 shown in Figure 2.

[0077] According to an embodiment of the display screen 10 shown in Figure 3, for each row, the display pixels 12 in the row i,j are coupled to a single row electrode 18 i For each column, the display pixels 12 in the column i,j are coupled to a single column electrode 20 j are coupled.

[0078] Figure 11 is a very simplified cross-sectional view of a known example of the display pixel 12, and Figure 12 is a bottom view of the display pixel 12 i,j Each display pixel 12 i,j is shown. i,jIt includes a control circuit 30 covered by a display circuit 32. The display circuit 32 includes at least one light-emitting diode LED, preferably at least three light-emitting diodes LEDs. The display pixel includes a lower surface 34 and an upper surface 35 facing the lower surface 34, and the surfaces 34 and 35 are preferably planar and parallel. The control circuit 30 further includes conductive pads P_Gnd, P_Vcc, P_Col, and P_Row on the lower surface 34. The control circuit 30 can correspond to an integrated circuit including electronic components, in particular, an insulated gate field effect transistor also called a MOS transistor, or a thin film transistor also called a TFT. Preferably, the display circuit 32 includes only the light-emitting diode LEDs and the conductive elements of these light-emitting diode LEDs, and the control circuit 30 includes all the electronic components necessary for controlling the light-emitting diode LEDs of the display circuit 32. As a variant, the display circuit 32 can also include other electronic components in addition to the light-emitting diode LEDs. The light-emitting diode LED can be a 2D light-emitting diode called a planar light-emitting diode with a stack of planar layers, or a 3D light-emitting diode with three-dimensional semiconductor elements each covered by an active region. In FIG. 11, the light-emitting diodes are shown as being connected to a common anode. However, it may be desirable to arrange the light-emitting diode LEDs with a different configuration. As an example, the light-emitting diodes can be connected to a common cathode or connected independently of each other.

[0079] According to an embodiment, the display pixel 12 i,j includes three display sub-pixels that emit light at the first, second, and third wavelengths. According to an embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm. As a variant, the display pixel 12 i,j can include only one light source that emits light at the first, second, or third wavelength, or only two light sources that emit light at two of the first, second, and third wavelengths.

[0080] Each of the conductive pads P_Gnd, P_Vcc, P_Col, and P_row is intended to be connected to one of the electrodes 14 i , 16 j , 18 i , 20 j shown schematically in FIG. 11. The first conductive pad P_Gnd is coupled to a source of a low reference potential Gnd. The second conductive pad P_Vcc is coupled to a source of a high reference potential Vcc. The third conductive pad P_Row is coupled to the row electrode 18 i and receives a timing signal Com i . The fourth conductive pad P_Col is coupled to the column electrode 20 j and receives a data signal Data j . The dimensions of the conductive pads P_Gnd, P_Vcc, P_Col, and P_row on the surface 34, and the layout of the conductive pads P_Gnd, P_Vcc, P_Col, and P_row, are particularly limited by the design rules of the display pixels 12 i,j , and the assembly method of the display pixels 12 i,j within the display screen 10.

[0081] Various embodiments and variations have been described. Those skilled in the art will understand that they can combine specific features of these embodiments, and other variations will be readily envisioned by those skilled in the art.

[0082] Finally, the actual implementation of the embodiments and variations described herein is within the ability of those skilled in the art based on the functional description provided above.

[0083] Cross - reference to related applications This application claims the benefit of priority of French Patent Application No. 22 / 06567, filed on Jun. 29, 2022, entitled "Display Pixel Comprising a Light - Emitting Diode and a Display Screen Having Such Display Pixels", which is incorporated herein by reference in the maximum extent permitted by law.

Claims

1. at least one light emitting diode (LED); A memory circuit (48) that stores at least one digital signal (R, G, B), and in a first operation mode, according to the logical state of the bits of the digital signal, a first different duration (TA ５ , TA ４ , TA ３ , TA ２ , TA １ ), by switching the light-emitting diode on or off within, or in a second operation mode, according to the logical state of the bits of the digital signal, a second different duration (TB ５ , TB ４ , TB ３ , TB ２ , TB １ ), which is at least partially different from the first duration, by switching the light-emitting diode on or off within, an electronic circuit (40) comprising a driver circuit (50) configured to drive the light-emitting diode by pulse width modulation and Comprising a display pixel (12 ｉ，ｊ ).

2. The display pixel according to claim 1, wherein the electronic circuit (40) is configured to switch between the first operation mode and the second operation mode according to a logical state of a first binary signal (IB).

3. The display pixel according to claim 2, wherein the electronic circuit (40) is configured to receive the first binary signal (IB) from outside the display pixel.

4. The digital signal (R, G, B) includes NB bits b ｉ where i ranges from 1 to NB, bit b ＮＢ is the most significant bit, bit b １ is the least significant bit, and the first duration includes NB first durations TA ｉ (TA ５ , TA ４ , TA ３ , TA ２ , TA １ ) with increasing values, and the second duration includes NB second durations TB ｉ (TB ５ , TB ４ , TB ３ , TB ２ , TB １ ) with increasing values. The driver circuit (50) is configured to drive the light-emitting diode by pulse-width modulation by switching the light-emitting diode on or off within the NB first durations TA ｉ (TA ５ , TA ４ , TA ３ , TA ２ , TA １ ) in the first operation mode. The light-emitting diode is switched on within the first duration TA ｉ when bit b ｉ is in the first logical state and switched off within the first duration TA ｉ when bit b ｉ is in a second logical state different from the first logical state. The driver circuit (50) is configured to drive the light-emitting diode by pulse-width modulation by switching the light-emitting diode on or off within the NB second durations TB ｉ (TB ５ , TB ４ , TB ３ , TB ２ , TB １ ) in the second operation mode. The light-emitting diode is switched on within the second duration TB ｉ when bit b ｉ is switched on therein, and bit b ｉ is switched off within a second duration TB when in the second logic state ｉ The display pixel according to any one of claims 1 to 3, which is switched off within a second duration TB when in the second logic state

5. At least some of the second duration (TB ５ , TB ４ ) is shorter than the first duration (TA ２ , TA １ ), the display pixel according to any one of claims 1 to 4.

6. At least one of the second durations (TB ５ , TB ４ ) is the same length as one of the first durations (TA ２ , TA １ ), the display pixel according to any one of claims 1 to 5.

7. At least the longest second duration (TB ５ ) is the same length as one of the first durations (TA ２ ), the display pixel according to claim 6.

8. connected to the electronic circuit (40) and comprising at least a first conductive pad (P_Row) for receiving a second binary signal (Com ｉ ) including pulses (PA, PB), some of said pulses being away from said first duration (TA ５ , TA ４ , TA ３ , TA ２ , TA １ ), some of said pulses being away from said second duration (TB ５ , TB ４ , TB ３ , TB ２ , TB １ ), the electronic circuit being configured to switch the light-emitting diode (LED) on or off during said first duration or said second duration based on said pulses, the display pixel according to any one of claims 1 to 7.

9. The pulse includes a first pulse (PA), and the first pulse is separated from the first duration (TA ５ , TA ４ , TA ３ , TA ２ , TA １ ). The pulse further includes a second pulse (PB), and a second pulse (PB) follows each first pulse (PA). The first pulse and the subsequent second pulse are separated from the second duration (TB ５ , TB ４ , TB ３ , TB ２ , TB １ ). The display pixel according to claim 8.

10. The electronic circuit (40) is configured to generate a third binary signal (PWM2) having a logic state that is changed in each first pulse (PA) and each second pulse (PB) from the second binary signal (Com ｉ )), the display pixel according to claim 9.

11. The display pixel according to claim 10, wherein the memory circuit (48) stores digital signals (R, G, B) and includes a shift register configured to provide consecutive bits of the stored digital signals, which are clocked by the third binary signal (PWM2).

12. The display pixel according to any one of claims 1 to 11, further comprising a controllable current source (CS) that supplies power to the light emitting diode (LED) and is controlled by a fourth binary signal (I_red, I_green, I_blue).

13. The electronic circuit (40) has a first input for receiving the third binary signal (PWM2) and a second input for receiving the first binary signal (IB), and a first NOR logic gate (NOR1); and a bit b ｉ ( / b ｉ ) having a first input for receiving the logical complement of, and a second input connected to the output of the first logic gate (NOR1), and a second NOR logic gate (NOR2) for providing the fourth binary signal (I_red, I_green, I_blue). The display pixel according to any one of claims 2, 4, and 12

14. connected to the electronic circuit (40) and comprising at least a second conductive pad (P_Col) for receiving a fifth binary signal (Data ｊ ), wherein the electronic circuit is configured to update the digital signals (R, G, B) stored in the memory circuit (48) from the second signal, the display pixel (12 ｉ，ｊ ) according to any one of claims 1 to 13.

15. The display pixels (12) according to any one of claims 1 to 14, arranged in rows and columns ｉ，ｊ ), and A first conductive track (18) extending along the row and connected to the electronic circuit (40) of the display pixel ｉ ), and A second conductive track (20) extending along the column and connected to the electronic circuit (40) of the display pixel ｉ ) and said first conductive track (18 ｉ ) and a control circuit (22, 24, 26) connected to said second conductive track (20 ｉ ) A display screen (10) comprising:

16. Each display pixel (12 ｉ，ｊ ), the electronic circuit (40) is configured to switch between the first and second operating modes according to the logical state of the first binary signal (IB), and the control circuits (22, 24, 26) determine the first binary signal (IB) for each digital signal (R, G, B), and the display screen (10) according to claim 15, wherein the first binary signal is provided to the display pixel (12 ｉ，ｊ ).

17. The control circuits (22, 24, 26) supply a timing signal (Com ｉ ) onto each first conductive track (18 ｉ ), and the electronic circuit (40) of each display pixel (12 ｉ，ｊ ) generates drive signals (I_red, I_green, I_blue) for driving the light emitting diode by pulse width modulation by switching the light emitting diode on or off during the first different durations (TA ５ , TA ４ , TA ３ , TA ２ , TA １ ) in a first operation mode, or by switching the light emitting diode on or off during the second different durations (TB ５ , TB ４ , TB ３ , TB ２ , TB １ ) in a second operation mode, from the timing signal, a display screen according to claim 15 or 16.

18. The control circuits (22, 24, 26) supply the timing signal (Com ｉ ), which is equal to a second binary signal (Com ｉ ) including at least a first pulse (PA), onto each first conductive track (18 ｉ ). The first pulse is separated from the first duration (TA ５ , TA ４ , TA ３ , TA ２ , TA １ ) and a second pulse (PB). A second pulse (PB) follows each first pulse (PA). The first pulse and the subsequent second pulse are separated from the second duration (TB ５ , TB ４ , TB ３ , TB ２ , TB １ ). The display screen according to claim 17.

Images