Synchronous voice communication and bus power via a multi-pair cable and connector

Abstract

In some examples of networks and methods, a data network includes nodes. The nodes include a main node (MN) and at least one sub-node. Each node includes a node transceiver. The node transceiver is operable to perform data communication according to a first network protocol for power over data via a first pair of conductors. The physical layer includes cable segments (e.g., bus cable segments) between each node. Each cable segment includes a plurality of pairs of conductors (e.g., pairs) and connectors (e.g., 8P8C connectors - however, other connectors having multiple pairs of conductors may be used) at each end. A first pair of conductors (e.g., connected to pins 4 and 5 of an 8P8C connector) implements a first network protocol between nodes. One or more of the remaining pairs of conductors provide auxiliary power to the nodes.

Description

Technical Field

[0001] Incorporation by Reference This application claims the benefit of priority to U.S. Non-Provisional Application No. 18 / 346,226, filed Jul. 1, 202e, “SYNCHRONOUS AUDIO COMMUNICATION AND BUS POWER OVER MULTI-PAIR CABLES AND CONNECTORS,” which claims the benefit of priority to U.S. Provisional Application No. 63 / 357,767, filed Jul. 1, 2022, “SYNCHRONOUS AUDIO COMMUNICATION AND BUS POWER OVER CAT CABLES WITH 8P8C CONNECTOR.” The entire disclosure of each is incorporated herein by reference.

[0002] The present disclosure relates to systems and devices within daisy-chain connected networks and / or point-to-point connected networks.

Background Art

[0003] As electronic components have become smaller and the expectations for performance have increased, more components are included in devices that previously did not have, or did not have as many, devices. In some settings, the communication infrastructure used to exchange signals between such components (e.g., within a vehicle) has required thick and heavy cable bundles.

[0004] The present disclosure is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or exhaustive description of the invention. Further limitations and disadvantages of conventional and traditional approaches will become apparent to those skilled in the art by comparing such systems with some aspects of the invention as described hereinafter in this application with reference to the drawings.

Summary of the Invention

Problems to be Solved by the Invention

[0005] This specification discloses systems and techniques for synchronous voice communication and bus power within a network bus via a cable with an 8P8C connector.

Means for Solving the Problems

[0006] The cable may be a variation of a CAT cable, such as a Category 5 (CAT5), Category 6 (CAT6), Category 7 (CAT7), or CAT8 (CAT8) cable, may be a shielded cable, may not be a shielded cable, and the cable may be an Ethernet cable. The connector may be an 8-position / 8-conductor (8P8C) connector, such as an RJ45 connector. The network bus may be a two-wire bus. In some examples, the network bus provided herein applies bus power in a stepwise and determined manner and shares differential communication line pairs with supply current and return current. This is in contrast to asynchronous packet-based Power over Ethernet (PoE). As described herein, the voice clock synchronous communication system provides many advantages. For example, it is simpler and allows for very short latency. In addition, Power over Data Line enables the reuse of communication cables for power, thus avoiding extra cables for power distribution. The combination of cable connectors is inexpensive, has good digital communication characteristics, and is readily available in many retail stores. Therefore, as described herein, it is desirable to also use it for synchronous voice communication. Therefore, this specification provides systems and techniques for reducing the complexity of PoE by providing different Power over Data Line schemes (PoD) for protecting a PoD device when plugged into a PoE PSD device and for protecting a PoE device when plugged into a PoD device.

Brief Description of the Drawings

[0007] This disclosure is best understood from the following detailed description when considered in conjunction with the accompanying drawings. In accordance with standard practice in the industry, various features are not necessarily drawn to scale and are shown for illustrative purposes only. When scale is explicitly or implicitly shown, only one example is provided as an illustration. In other embodiments, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. For ease of explanation, like reference numerals designate like structural elements. The embodiments are illustrated by way of example in the figures of the accompanying drawings and are not meant to be limiting.

[0008] To more fully understand the nature and advantages of the present invention, reference is made to the following detailed description of the preferred embodiments in connection with the accompanying drawings below.

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15A

Figure 15B

Figure 15C

Figure 16

Figure 17A

Figure 17B

Figure 17C

DETAILED DESCRIPTION OF THE INVENTION

[0010] This specification discloses systems and techniques for synchronous voice communication and bus power within a network bus via a cable with an 8P8C connector. The cable can be a shielded or unshielded CAT cable, such as a Category 5 (CAT5), Category 6 (CAT6), Category 7 (CAT7), or CAT8 (CAT8) cable, and the cable can be an Ethernet cable. The connector can be a shielded or unshielded 8-position / 8-conductor (8P8C) connector, such as an RJ45 connector. The network bus can be a two-wire bus. In some examples, the network bus provided herein applies bus power in a staged and negotiated manner and shares differential communication line pairs with supply current and return current. This is in contrast to asynchronous packet-based PoE.

[0011] Generally, since audio connections in studios and stages are analog, they are susceptible to noise and interference. Audio stages and studios are expected to migrate from the use of legacy analog wiring (e.g., guitar cables using a single monaural signal) to digital connections using multi-channel audio signals on the same cable (e.g., each of the six strings of a guitar can pick up the sound individually and communicate on the same cable as six separate audio channels). In building automation and conference rooms, CAT cables with 8P8C (RJ45) connectors are used to connect ceiling microphone arrays and speakers to Ethernet over distances up to 100m. However, since Ethernet is asynchronous packet-based communication, it is not ideal for audio. Ethernet packets need to be resynchronized and resynthesized to the audio clock and audio phase at each end node. Packet-based communication is inefficient and adds undesirable latency.

[0012] The audio clock synchronization communication system offers many advantages. It is simpler and enables very short latency. Power over data line is also highly desirable for enabling reuse of communication cables for power, thus avoiding extra cables for power wiring. PoE, as standardized by the IEEE, is complex and requires specialized PSE (Power Sourcing Equipment) and PD (Powered Device) to communicate / negotiate with external power pulses at the Ethernet PHY-MAC layer. CAT cables with 8P8C (RJ45) connectors are ubiquitous for Ethernet connections and may also have a voltage for PoE up to minus 57V. The cable connector combinations are inexpensive, have good digital communication characteristics, and are readily available in many retail stores. Therefore, it is desirable to use them not only in conference rooms but also for synchronous audio communication on stages, in audio studios, and for other digital audio wiring applications.

[0013] In this specification, systems and techniques are provided for reducing the complexity of PoE by providing different Power over Data Line schemes (PoD) for protecting a PoD device when plugged into a PoE PSD device and for protecting a PoE device when plugged into a PoD device. The PoD circuit does not need to support the supply voltage range of PoE and is not as complex as PoE when accidentally plugged into a PoE device. In PoE, the differential lines in pairs are biased together for power, and another pair of lines is biased for return current. In contrast, PoD biases one line of a pair with power and uses the other line of the pair as return current. Different from Ethernet which uses more expensive transformers, cost-effective inductors are used for bias injection into the communication line. Additionally, as described in this specification, in some examples, only one pair of lines is used for communication, and the other pairs are enabled to carry a high bus voltage negotiated without low-pass filtering (and without transformer coupling).

[0014] As described herein, the communication path on the communication line is high-pass filtered through a series capacitor, while on the same line, the bias is induced by a low-pass filter on one line of the differential pair and returned by a low-pass filter on the other line. The next sequential node draws power through a low-pass filter in the form of an inductor and communicates via a high-pass filter in the form of a series capacitor. The next sequential node uses bus power from the differential communication line for the bus transceiver and for a memory device (e.g., EEPROM). A current-limited low-voltage bus bias is applied to the communication line pair through a voltage regulator and a current-limiting device or directly by a current-limiting voltage regulator. The device has a power good (PG) or similar signal that indicates good operation only when there is no overcurrent situation. An overcurrent on the output side of such a device also reduces the output voltage and thus limits the power draw for overcurrent protection.

[0015] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and like numerals designate like parts throughout. By way of example, embodiments which may be practiced are shown. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense.

[0016] Various operations may be described in turn, in a manner most helpful in understanding the claimed subject matter, as a plurality of distinct actions or operations. However, the order of the description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. The operations described may be performed in a different order than the described embodiments. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0017] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0018] Although various components may be referred to or exemplified herein in the singular (e.g., "a processor", "a peripheral device", etc.), this is merely for ease of discussion, and any element referred to in the singular may include a plurality of such elements according to the teachings herein.

[0019] In this description, the phrases "in an embodiment" or "in embodiments" are used, each of which may refer to one or more of the same or different embodiments. Further, when used with respect to embodiments of the present disclosure, terms such as "comprising", "including", "having", etc. are synonyms. As used herein, the term "circuit" may refer to an application specific integrated circuit (ASIC), an electronic circuit, and an optical circuit, a (shared, dedicated, or group) processor and / or (shared, dedicated, or group) memory that executes one or more software programs or firmware programs, a combinational logic circuit that provides the described functionality, and / or other suitable hardware, may be a part thereof, or may include them.

[0020] Figure 1 is a block diagram of an exemplary half-duplex two-wire communication system 100 according to various embodiments. System 100 includes a host 110, a main node 102-1, and at least one sub-node 102-2. In Figure 1, three sub-nodes (0, 1, and 2) are illustrated. The depiction of the three sub-nodes 102-2 in Figure 1 is merely exemplary, and system 100 may include one, two, or more sub-nodes 102-2 as desired.

[0021] The main node 102-1 may communicate with the sub-nodes 102-2 via a two-wire bus 106. The bus 106 may include different two-wire bus links between adjacent nodes along the bus 106 to connect the nodes along the bus 106 in a daisy-chain fashion. For example, as shown in Figure 1, the bus 106 may include a link coupling the main node 102-1 to sub-node 0, a link coupling sub-node 0 to sub-node 1, and a link coupling sub-node 1 to sub-node 2. In some embodiments, each of the links of the bus 106 may be formed from a single twisted pair (e.g., an unshielded twisted pair). In some embodiments, each of the links of the bus 106 may be formed from a coaxial cable (e.g., having a core providing a "positive" line and a shield providing a "negative" line, or vice versa). The two-wire bus links together provide a complete electrical path (e.g., a forward current path and a return current path) such that no additional ground or voltage source lines are required.

[0022] Host 110 may include a processor that programs main node 102-1 and functions as the sender and receiver of various payloads transmitted along bus 106. In some embodiments, host 110 may be, or may include, for example, a microcontroller. Specifically, host 110 may be the master of Inter-Integrated Circuit (I2S) communication occurring along bus 106. Host 110 may communicate with main node 102-1 via the I2S / Time Division Multiplexing (TDM) protocol, the Serial Peripheral Interface (SPI) protocol, and / or the Inter-Integrated Circuit (I2C) protocol. In some embodiments, main node 1021 may be a transceiver (e.g., node transceiver 120 discussed below with reference to FIG. 2) located within the same housing as host 110. Main node 102-1 may be programmable by host 110 via the I2C bus for configuration and reading, and may be configured to generate the clocks, synchronization, and framing for all sub-nodes 102-2. In some embodiments, the extension of the I2C control bus between host 110 and main node 1021 may be embedded in the data stream transmitted via bus 106, enabling host 110 to directly access the registers and status information for one or more sub-nodes 102-2, and may also enable long-distance I2C-to-I2C communication, allowing host 110 to control peripheral device 108. In some embodiments, the extension of the SPI control bus between host 110 and main node 1021 may be embedded in the data stream transmitted via bus 106, enabling host 110 to directly access the registers and status information for one or more sub-nodes 102-2, and may also enable long-distance SPI-to-SPI communication or SPI-to-I2C communication, allowing host 110 to control peripheral device 108. In embodiments where system 100 is included in a vehicle, host 110 and / or main node 102-1 may be included in the head end of the vehicle.

[0023] The main node 102-1 can generate a "downstream" signal (e.g., a data signal, a power signal, etc. transmitted away from the main node 102-1 along the bus 106), and can receive an "upstream" signal (e.g., transmitted towards the main node 102-1 along the bus 106). The main node 102-1 can provide a clock signal for synchronous data transmission via the bus 106. As used herein, "synchronous data" can include data (e.g., an audio signal) that is continuously streamed at regular time intervals between two consecutive transmissions to / from the same node along the bus 106. In some embodiments, the clock signal provided by the main node 1021 can be derived from an I2S input provided to the main node 102-1 by the host 110. The sub-node 102-2 can be an addressable network connection point that represents a possible destination for a data frame transmitted downstream or upstream on the bus 106. The sub-node 102-2 can also represent a possible source of a downstream data frame or an upstream data frame. The system 100 can enable control information and other data to be transmitted bidirectionally from one node to the next via the bus 106. One or more of the sub-nodes 102-2 can also be powered by a signal transmitted via the bus 106.

[0024] Specifically, each of the main node 102-1 and the sub-node 102-2 may include a positive upstream terminal (shown as "AP"), a negative upstream terminal (shown as "AN"), a positive downstream terminal (shown as "BP"), and a negative downstream terminal (shown as "BN"). The positive and negative downstream terminals of the node may be respectively coupled to the positive and negative upstream terminals of the adjacent downstream node. As shown in FIG. 1, the main node 102-1 may include a positive upstream terminal and a negative upstream terminal, but these terminals may not be used. In other embodiments, the main node 102-1 may not include a positive upstream terminal and a negative upstream terminal. The last sub-node 1022 (sub-node 2 in FIG. 1) along the bus 106 may include a positive downstream terminal and a negative downstream terminal, but these terminals may not be used. In other embodiments, the last sub-node 102-2 along the bus may not include a positive downstream terminal and a negative downstream terminal.

[0025] As will be discussed in detail below, the main node 102-1 can optionally send a periodic synchronization control frame downstream, together with data directed to one or more of the sub-nodes 102-2. For example, the main node 102-1 can transmit the synchronization control frame at a frequency of 48 kHz every 1024 bits (representing a superframe), resulting in an effective bit rate of 49.152 Mbps on the bus 106. Other rates, including for example 44.1 kHz, can be supported. The synchronization control frame can enable the sub-nodes 102-2 to identify the start of each superframe, and, in combination with physical layer encoding / signaling, can enable each sub-node 102-2 to derive its internal operating clock from the bus 106. The synchronization control frame can include a preamble for signaling the start of synchronization, as well as a control field enabling various addressing modes (e.g., typically broadcast, discovery operations), configuration information (e.g., writing to registers of the sub-node 102-2), transmission of I2C information, transmission of SPI information, remote control of specific general-purpose input / output (GPIO) pins in the sub-node 102-2, and other services. A portion of the synchronization control frame following the preamble and payload data can be scrambled to reduce the likelihood that the information in the synchronization control frame will be mistaken for a new preamble and to flatten the spectrum of the associated electromagnetic radiation.

[0026] The synchronization control frame can be passed between sub - nodes 1022 until it reaches the last sub - node 102 - 2 (i.e., sub - node 2 in Figure - 1), which is configured as the last sub - node 102 - 2 by the main node 102 - 1 or self - identifies itself as the last sub - node 102 - 2. (Optionally, it can come from the main node 102 - 1, but additionally or alternatively, it can come from one or more upstream sub - nodes 1022 or from the sub - node 102 - 2 itself, along with other data). When receiving the synchronization control frame, the last sub - node 102 - 2 can send a synchronization response frame and then can send any data for which transmission is permitted (e.g., 24 - bit audio samples within a specified time slot). The synchronization response frame can be passed upstream between sub - nodes 102 - 2 (optionally, along with data from downstream sub - nodes 102 - 2), and based on the synchronization response frame, each sub - node 102 - 2 can identify, if any, the time slot for which the sub - node 102 - 2 is permitted to transmit.

[0027] In some embodiments, one or more of the sub-nodes 102-2 within the system 100 may be coupled to and communicate with a peripheral device 108. For example, the sub-node 102-2 may be configured to read data from and / or write data to an associated peripheral device 108 using, for example, the I2S protocol, the pulse density modulation (PDM) protocol, the TDM protocol, the SPI protocol, and / or the I2C protocol as discussed below. Although the "peripheral device 108" may be referred to herein in the singular, this is merely for ease of discussion, and a single sub-node 102-2 may be coupled to zero, one, or two or more peripheral devices. Examples of peripheral devices that may be included in the peripheral device 108 include a digital signal processor (DSP), a field programmable gate array (FPGA), an ASIC, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a codec, a microphone, a microphone array, a speaker, an audio amplifier, a protocol analyzer, an accelerometer or other motion sensor, an environmental condition sensor (e.g., a temperature sensor, a humidity sensor, and / or a gas sensor), a wired communication transceiver or a wireless communication transceiver, a display device (e.g., a touch screen display), a user interface component (e.g., a button, a dial, or other control key), a camera (e.g., a video camera), a memory device, or any other suitable device that transmits and / or receives data. Some examples of different peripheral device configurations are discussed in detail herein.

[0028] In some embodiments, the peripheral device 108 may include any device configured for I2S communication, and the peripheral device 108 may communicate with the associated sub-node 102-2 via the I2S protocol. In some embodiments, the peripheral device 108 may include any device configured for I2C communication, and the peripheral device 108 may communicate with the associated sub-node 102-2 via the I2C protocol. In some embodiments, the peripheral device 108 may include any device configured for SPI communication, and the peripheral device 108 may communicate with the associated sub-node 102-2 via the SPI protocol. In some embodiments, the sub-node 102-2 may not be coupled to any peripheral device 108.

[0029] The sub-node 102-2 and its associated peripheral device 108 may be housed in separate housings, may be coupled through a wired communication connection or a wireless communication connection, or may be housed in a common housing. For example, a speaker connected as the peripheral device 108 may be packaged with the hardware for the associated sub-node 102-2 (e.g., the node transceiver 120 discussed below with reference to FIG. 2) such that the hardware for the associated sub-node 102-2 is housed within a housing that includes other speaker components. The same may apply to any type of peripheral device 108.

[0030] As discussed above, the host 110 may communicate with and control the main node 102-1 using a multi-channel I2S communication protocol, an SPI communication protocol, and / or an I2C communication protocol. For example, the host 110 may transmit data via I2S to a frame buffer (not shown) within the main node 102-1, and the main node 102-1 may read the data from the frame buffer and transmit the data along the bus 106. Similarly, the main node 102-1 may store data received via the bus 106 within the frame buffer and then transmit the data to the host 110 via I2S.

[0031] Each sub-node 102-2 may have an internal control register, which may be configured by communication from the main node 102-1. Some such registers will be discussed in detail below. Each sub-node 102-2 may receive downstream data and retransmit the data further downstream. Each sub-node 102-2 may receive and / or generate upstream data and / or retransmit the data upstream and / or add the data to an upstream transaction.

[0032] Communication along the bus 106 may occur in periodic superframes. Each superframe may start with a downstream synchronization control frame and may be divided into a period of downstream transmission (also called the "downstream portion"), a period of upstream transmission (also called the "upstream portion"), and a period of no transmission (when the bus 106 is not being driven), and may end just prior to the transmission of another downstream synchronization control frame. The main node 102-1 may be programmed (by the host 110) with some downstream portions for transmitting to one or more of the sub-nodes 102-2 and some upstream portions for receiving from one or more of the sub-nodes 102-2. Each sub-node 102-2 may be programmed (by the main node 102-1) with some downstream portions for retransmitting down the bus 106, some downstream portions for consumption, some upstream portions for retransmitting up the bus 106, and some upstream portions where the sub-node 102-2 may transmit data received from the sub-node 102-2 from the associated peripheral device 108. Communication along the bus 106 will be discussed in further detail below with reference to FIGS. 2-12.

[0033] Embodiments of the communication system 100 disclosed herein are unique among conventional communication systems in that all sub-nodes 102-2 can receive output data via bus 106 within the same superframe (e.g., all sub-nodes 102-2 can receive the same audio sample without sample delay between nodes 102). In conventional communication systems, data is buffered and processed within each node before being passed to the next node downstream in the next frame. As a result, in these conventional communication systems, the latency of data transmission depends on the number of nodes (each node adds a delay for one audio sample). In the communication system 100 disclosed herein, bus 106 can add only one cycle of latency regardless of whether the first sub-node or the last sub-node 102-2 receives the data. The same applies to upstream communication, where data can be available at the upstream node 102 in the next superframe regardless of which sub-node 102-2 provided the data.

[0034] Furthermore, in the embodiments of the communication system 100 disclosed herein, downstream data (e.g., downstream voice data) may be placed on the bus 106 by the main node 102-1 or by any of the sub-nodes 102-2 upstream of the receiving sub-node 102-2. Similarly, upstream data (e.g., upstream voice data) may be placed on the bus 106 by any of the sub-nodes 102-2 downstream of the receiving node 102 (i.e., the main node 102-1 or the sub-node 102-2). Such an ability enables the sub-node 102-2 to provide both upstream and downstream data at a particular time (e.g., a particular voice sample time). In the case of voice data, this data can be received at the next voice sample of any downstream node 102 or upstream node 102 without further delay (except for a slight propagation delay that falls within the superframe boundary). As further discussed herein, control messages (e.g., of a Synchronization Control Frame (SCF)) can move to the last node 102 (which specifies a particular node 102 or a broadcast), and an upstream response (e.g., of a Synchronization Response Frame (SRF)) can be created by the last downstream node 102 within the same superframe. The node 102 addressed by the SCF modifies the content of the upstream SRF with its own response. As a result, within the same voice sample, control and response can be fully executed across multiple nodes 102. This is also in contrast to conventional communication systems where sample latency occurs between nodes (for relaying messages from one node to another).

[0035] Each of the main node 102-1 and the sub-node 102-2 may include a transceiver for managing communication between the components of the system 100. FIG. 2 is a block diagram of a node transceiver 120 that may be included in a node (e.g., the main node 102-1 or the sub-node 102-2) of the system 100 according to various embodiments. In some embodiments, the node transceiver 120 may be included in each of the nodes of the system 100, and a control signal may be provided to the node transceiver 120 via a main pin to indicate whether the node transceiver 120 functions as a main node (e.g., when the MAIN pin is high) or acts as a sub-node (e.g., when the main pin is low).

[0036] The node transceiver 120 may include an upstream differential signal (DS) transceiver 122 and a downstream DS transceiver 124. The upstream DS transceiver 122 may be coupled to the positive upstream terminal and the negative upstream terminal discussed above with reference to FIG. 1, and the downstream DS transceiver 124 may be coupled to the positive downstream terminal and the negative downstream terminal discussed above with reference to FIG. 1. In some embodiments, the upstream DS transceiver 122 may be a low voltage DS (LVDS) transceiver, and the downstream DS transceiver 124 may be an LVDS transceiver. Each node of the system 100 may be AC-coupled to the bus 106, and data signals may be transmitted along the bus 106 (e.g., via the upstream DS transceiver 122 and / or the downstream DS transceiver 124) using a predetermined form of DS (e.g., LVDS or multi-point LVDS (MLVDS) or similar signaling) with an appropriate encoding (e.g., differential Manchester encoding, binary mark encoding, Manchester encoding, non-return-to-zero, non-return-to-zero inverted (NRZI) encoding with run length limitation, or any other suitable encoding) for providing timing information.

[0037] The upstream DS transceiver 122 and the downstream DS transceiver 124 can communicate with the bus protocol circuit 126, and the bus protocol circuit 126 can communicate with, among other components, the phase-locked loop (PLL) 128 and the voltage regulator circuit 130. When the node transceiver 120 is powered on, the voltage regulator circuit 130 can raise a "power good" signal that is used as a power-on reset by the PLL 128.

[0038] As described above, one or more of the sub-nodes 102-2 of the system 100 can receive power transmitted via the bus 106 along with data. (Since some of the sub-nodes 102-2 can be configured to have their own dedicated local power supplies, this is optional.) For power distribution, the main node 102-1 can apply a DC bias to the bus link between the main node 102-1 and the sub-node 0 (e.g., by connecting one of the downstream terminals, through a low-pass filter, to a voltage source provided by a voltage regulator and grounding the other downstream terminal). The DC bias can be a predetermined voltage such as 5 volts, 8 volts, the voltage of an automotive battery, or a higher voltage. Each successive sub-node 102-2 can selectively tap the upstream bus link of each sub-node in order to recover power (e.g., using the voltage regulator circuit 130). This power can be used to power the sub-node 102-2 itself (and, optionally, one or more peripheral devices 108 coupled to the sub-node 1022). The sub-node 102-2 can also selectively bias the downstream bus link for the next sequential sub-node 102-2 with either the power recovered from the upstream bus link or the power recovered from a local power supply. For example, the sub-node 0 can use the DC bias on the upstream link of the bus 106 to recover power for the sub-node 0 itself and / or one or more associated peripheral devices 108, and / or the sub-node 0 can recover power from the upstream link of the bus 106 to bias the downstream link of the bus 106.

[0039] Accordingly, in some embodiments, each node of system 100 may supply power to the next downstream node via a downstream bus link. Power supply to the nodes may be performed sequentially. For example, after discovering and configuring sub-node 0 via bus 106, main node 102-1 may instruct sub-node 0 to supply power to its downstream link of bus 106 to supply power to sub-node 1. After sub-node 1 is discovered and configured, main node 102-1 may instruct sub-node 1 to supply power to its downstream link of bus 106 to supply power to sub-node 2 (and the same applies to additional sub-node 102-2 coupled to bus 106). In some embodiments, one or more of sub-nodes 102-2 may be locally powered instead of or in addition to being powered from its upstream bus link. In some such embodiments, a local power source for a given sub-node 102-2 may be used to supply power to one or more downstream sub-nodes.

[0040] In some embodiments, the upstream bus interface circuit 132 may be disposed between the upstream DS transceiver 122 and the voltage regulator circuit 130, and the downstream bus interface circuit 131 may be disposed between the downstream DS transceiver 124 and the voltage regulator circuit 130. Since each link of the bus 106 can carry an AC (signal) component and a DC (power) component, the upstream bus interface circuit 132 and the downstream bus interface circuit 131 can separate the AC component and the DC component, provide the AC component to the upstream DS transceiver 122 and the downstream DS transceiver 124, and provide the DC component to the voltage regulator circuit 130. The line-side AC coupling of the upstream DS transceiver 122 and the downstream DS transceiver 124 substantially isolates the transceivers 122 and 124 from the DC component on the line to enable high-speed bidirectional communication. As discussed above, the DC component may be tapped for power, and the upstream bus interface circuit 132 and the downstream bus interface circuit 131 may include, for example, a ferrite, a common-mode choke, or an inductor to reduce the AC component provided to the voltage regulator circuit 130. In some embodiments, the upstream bus interface circuit 132 may be included in the upstream DS transceiver 122, and / or the downstream bus interface circuit 131 may be included in the downstream DS transceiver 124. In other embodiments, the filtering circuit may be external to the transceivers 122 and 124.

[0041] The node transceiver 120 may include a transceiver 127 for I2S communication, TDM communication, and PDM communication between the node transceiver 120 and an external device 155. Although the "external device 155" may be referred to in the singular in this specification, this is merely for ease of illustration, and multiple external devices may communicate with the node transceiver 120 via the I2S / TDM / PDM transceiver 127. As is well known in the art, the I2S protocol is for carrying pulse code modulation (PCM) information (e.g., between audio chips on a printed circuit board (PCB)). As used herein, "I2S / TDM" may refer to the extension of I2S stereo (2-channel) content to multiple channels using TDM. As is well known in the art, PDM may be used in a sigma-delta converter, and specifically, the PDM format may represent a decimated, oversampled 1-bit sigma-delta ADC signal. The PDM format is often used as the output format of a digital microphone. The I2S / TDM / PDM transceiver 127 may communicate with a bus protocol circuit 126 and pins for communication with the external device 155. Six pins (BCLK, SYNC, DTX[1:0], and DRX[1:0]) are shown in FIG. 2. The BCLK pin may be used for the I2S bit clock, the SYNC pin may be used for the I2S frame synchronization signal, and the DTX[1:0] pins and DRX[1:0] pins are used for the transmit data channel and receive data channel, respectively. Two transmit pins (DTX[1:0]) and two receive pins (DRX[1:0]) are shown in FIG. 2, but any desired number of receive pins and / or transmit pins may be used.

[0042] When the node transceiver 120 is included in the main node 102-1, the external device 155 may include the host 110, and the I2S / TDM / PDM transceiver 127 may provide an I2S slave (for BCLK and SYNC) that can receive data from the host 110 and send the data to the host 110 in synchronization with the I2S interface clock of the host 110. Specifically, the I2S frame synchronization signal may be received at the SYNC pin as an input from the host 110, and the PLL 128 may use the signal to generate a clock. When the node transceiver 120 is included in the sub-node 102-2, the external device 155 may include one or more peripheral devices 108, and the I2S / TDM / PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC) that can control I2S communication with the peripheral device 108. Specifically, the I2S / TDM / PDM transceiver 127 may provide the I2S frame synchronization signal at the SYNC pin as an output. The registers of the node transceiver 120 may determine, via the bus 106 as a data slot, which I2S / TDM channel and how many I2S / TDM channels are being transmitted. The TDM mode (TDMMODE) register of the node transceiver 120 may store a value of the number of TDM channels that matches between consecutive SYNC pulses on the TDM transmit pin or the TDM receive pin. With knowledge of the channel size, the node transceiver 120 may automatically set the BCLK rate to match the number of bits within the sampling time (e.g., 48 kHz).

[0043] The node transceiver 120 may include a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157. Although the "external device 157" may be referred to in the singular in this specification, this is merely for ease of illustration, and multiple external devices may communicate with the node transceiver 120 via the I2C transceiver 129. As is well known in the art, the I2C protocol uses a clock (SCL) line and a data (SDA) line to provide data transfer. The I2C transceiver 129 may communicate with a bus protocol circuit 126 and pins for communication with the external device 157. Four pins (ADR1, ADR2, SDA, and SCL) are shown in FIG. 2, and ADR1 and ADR2 may be used to modify the I2C address used by the node transceiver 120 when the node transceiver 120 functions as an I2C slave (e.g., when it is included in the main node 102-1), and SDA and SCL are used for the I2C serial data and serial clock signals, respectively. When the node transceiver 120 is included in the main node 102-1, the external device 157 may include a host 110, and the I2C transceiver 129 may provide an I2C slave that can receive programming instructions from the host 110. Specifically, the I2C serial clock signal may be received at the SCL pin as an input from the host 110 for register access. When the node transceiver 120 is included in the sub-node 102-2, the external device 157 may include a peripheral device 108, and the I2C transceiver 129 may provide an I2C master to enable the I2C transceiver to program one or more peripheral devices according to instructions provided by the host 110 and transmitted to the node transceiver 120 via the bus 106. Specifically, the I2C transceiver 129 may provide the I2C serial clock signal at the SCL pin as an output.

[0044] The node transceiver 120 may include a transceiver 136 for SPI communication between the node transceiver 120 and an external device 138. Although the "external device 138" may be referred to in the singular in this specification, this is merely for ease of illustration, and multiple external devices may communicate with the node transceiver 120 via the SPI transceiver 136. As is well known in the art, the SPI protocol uses a slave select (SS) data line, a clock (BCLK) data line, a master out slave in (MOSI) data line, and a master in slave out (MISO) data line to provide data transfer, and the pins corresponding to these four lines are shown in FIG. 2. The SPI transceiver 136 may communicate with the bus protocol circuit 126 and the pins for communication with the external device 138. When the node transceiver 120 is included in the main node 102-1, the external device 138 may include the host 110 or another external device, and the SPI transceiver 136 may provide an SPI slave that can receive and respond to commands from the host 110 or other external devices. When the node transceiver 120 is included in the sub-node 102-2, the external device 138 may include the peripheral device 108, and the SPI transceiver 136 may provide an SPI host to enable the SPI transceiver 136 to send commands to one or more peripheral devices 108. The SPI transceiver 136 may include a read data first in first out (FIFO) buffer and a write data FIFO buffer. The read data FIFO buffer may be used to collect data read from other nodes 102 and may be read by the external device 138 when the external device 138 sends an appropriate read command. The write data FIFO buffer may be used to collect write data from the external device 138 before the write data is sent to another device.

[0045] The node transceiver 120 may include an interrupt request (IRQ) pin that communicates with the bus protocol circuit 126. When the node transceiver 120 is included in the main node 102-1, the bus protocol circuit 126 may provide an event-driven interrupt request to the host 110 via the IRQ pin. When the node transceiver 120 is included in the sub-node 102-2 (e.g., when the MSTR pin is low), the IRQ pin may function as a GPIO pin having interrupt request capabilities. The node transceiver 120 may include other pins in addition to those shown in FIG. 2 (e.g., as discussed below).

[0046] The system 100 may operate in any of several different operating modes. Each node on the bus 106 may have a register indicating which operating mode is currently enabled. Examples of the various operating modes that may be implemented are described below. In the standby operating mode, bus activity is suppressed to allow for comprehensive power savings, and the only traffic required is a minimal downstream preamble to maintain synchronization of each node's PLL (e.g., PLL 128). In the standby operating mode, reads and writes across the entire bus 106 are not supported. In the discovery operating mode, the main node 102-1 may send a predetermined signal along the bus 106 and wait for a suitable response to map the topology of the sub-nodes 102-2 distributed along the bus 106. In the normal operating mode, full register access to the sub-node 102-2 and from the sub-node 102-2 may be available, as well as access to and from the peripheral device 108 via the bus 106. The normal mode may be comprehensively configured by the host 110 regardless of the presence or absence of synchronous upstream data and regardless of the presence or absence of synchronous downstream data.

[0047] FIG. 3 is a diagram of a portion of a synchronization control frame 180 used for communication within system 100 according to various embodiments. Specifically, synchronization control frame 180 can be used for data clock recovery and PLL synchronization, as discussed below. As described above, since communication via bus 106 can occur in both directions, the communication can be time-division multiplexed into a downstream portion and an upstream portion. In the downstream portion, the synchronization control frame and downstream data can be transmitted from main node 102-1, while in the upstream portion, the synchronization response frame and upstream data can be transmitted from each of sub-nodes 102-2 to main node 102-1. Synchronization control frame 180 can include a preamble 182 and control data 184. Each sub-node 1022 can be configured to use the preamble 182 of the received synchronization control frame 180 as a time base for input to PLL 128. To facilitate this, preamble 182 does not follow the "rules" of valid control data 184 and can thus be easily distinguished from control data 184.

[0048] For example, in some embodiments, communication along bus 106 can be encoded using a differential Manchester encoding scheme that first transitions on clock and zero. According to such an encoding scheme, each bit time starts with a clock transition. If the data value is zero, the encoded signal transitions again in the middle of the bit time. If the data value is 1, the encoded signal does not transition again. The preamble 182 shown in FIG. 5 can violate the encoding protocol (by having clock transitions that do not occur, for example, at the start of bit times 5, 7, and 8), which means that the preamble 182 does not have to match any of the legitimate (e.g., correctly encoded) patterns for the control data 184. In addition, the preamble 182 cannot be replicated by taking a legitimate pattern for the control data 184 and forcing the bus 106 high or low for a period of a single bit time or multiple bit times. The preamble 182 shown in FIG. 5 is merely illustrative, and the synchronization control frame 180 can include a different preamble 182 that can violate the encoding used by the control data 184 in any suitable manner.

[0049] The bus protocol circuit 126 can include a differential Manchester decoder circuit that operates on the clock recovered from the bus 106 and detects the synchronization control frame 180 and sends a frame synchronization indicator to the PLL 128. In this way, the synchronization control frame 180 can be detected without using the system clock or a faster oversampling clock. As a result, the sub-node 102-2 can receive the PLL synchronization signal from the bus 106 without requiring a crystal clock source at the sub-node 102-2.

[0050] As described above, communication along bus 106 can occur in periodic superframes. FIG. 4 is a diagram of superframe 190 according to various embodiments. As shown in FIG. 6, the superframe can start with a synchronization control frame 180. When the synchronization control frame 180 is used as the timing source for PLL 128, the frequency at which the superframe is communicated (the "superframe frequency") can be the same as the synchronization signal frequency. In some embodiments where voice data is transmitted along bus 106, the superframe frequency can be the same as the voice sampling frequency used in system 100 (e.g., either 48 kHz or 44.1 kHz), although any suitable superframe frequency may be used. Each superframe 190 can be divided into a downstream transmission period 192, an upstream transmission period 194, and a non-transmission period 196 (e.g., when bus 106 is not being driven).

[0051] In FIG. 4, superframe 190 is shown with an initial downstream transmission period 192 and a later upstream transmission period 194. The downstream transmission period 192 can include a synchronization control frame 180 and X downstream data slots 198, where X can be zero. Substantially all signals on bus 106 can be line encoded, and the synchronization signal can be transferred downstream in the form of a synchronization preamble 182 within the synchronization control frame 180 from main node 102-1 to the last sub-node 102-2 (e.g., sub-node 102-2C). Downstream data, TDM data, and synchronization data may be included in the X downstream data slots 198 after the synchronization control frame 180. The downstream data slots 198 can have equal widths. As discussed above, PLL 128 can provide a clock that nodes use to time communication via bus 106. In some embodiments where bus 106 is used to transmit voice data, PLL 128 can operate at a multiple of the voice sampling frequency (e.g., 1024 times the voice sampling frequency, providing 1024 bit clocks per superframe).

[0052] The upstream transmission period 194 may include a synchronization response frame 197 and Y upstream data slots 199, where Y may be zero. In some embodiments, each sub-node 102-2 may consume a portion of the downstream data slot 198. The last sub-node (e.g., sub-node 2 in FIG. 1) may respond with the synchronization response frame 197 (after a predetermined response time stored in the register of the last sub-node). Upstream data, TDM data, and synchronization data may be added by each sub-node 102-2 to the upstream data slot 199 immediately after the synchronization response frame 197. The upstream data slots 199 may have equal widths. Sub-nodes 102-2 that are not the last sub-node (e.g., sub-nodes 0 and 1 in FIG. 1) may replace the received synchronization response frame 197 with their own upstream response if a read of one of their registers is requested in the synchronization control frame 180 of the superframe 190, or if a remote I2C read is requested in the synchronization control frame 180 of the superframe 190.

[0053] As discussed above, the synchronization control frame 180 may initiate each downstream transmission. In some embodiments, the synchronization control frame 180 may be 64 bits in length, although any other suitable length may be used. The synchronization control frame 180 may start with a preamble 182 as described above. In some embodiments, when the synchronization control frame 180 is retransmitted by a downstream sub-node 102-2 to a downstream sub-node 102-2, the preamble 182 may be generated by the transmitting sub-node 102-2 rather than being retransmitted.

[0054] The control data 184 of the synchronization control frame 180 may include fields that contain data used to control transactions via the bus 106. Examples of these fields are discussed below, and several embodiments are shown in FIG. 5. Specifically, FIG. 5 shows an exemplary format for the synchronization control frame 180 in the normal mode, I2C mode, and discovery mode according to various embodiments. In some embodiments, different preambles 182 or synchronization control frames 180 may all be used in standby mode so that the sub-node 102-2 does not need to receive all of the synchronization control frame 180 until a transition to the normal mode is sent.

[0055] In some embodiments, the synchronization control frame 180 may include a count (CNT) field. The CNT field may have any suitable length (e.g., 2 bits) and may be incremented from the value used in the previous superframe (subject to the field length). A sub-node 102-2 that receives an unexpected CNT value may be programmed to return an interrupt.

[0056] In some embodiments, the synchronization control frame 180 may include a node address specification (NAM) field. The NAM field may have any suitable length (e.g., 2 bits) and may be used to control access to the registers of the sub-node 102-2 via the bus 106. In the normal mode, the registers of the sub-node 102-2 may be read and / or written based on the ID of the sub-node 102-2 and the address of the register. A broadcast transaction is a write that all sub-nodes 102-2 should accept. In some embodiments, the NAM field may provide four node address specification modes, including "none" (e.g., data not addressed to any particular sub-node 102-2), "normal" (e.g., data unicast to a particular sub-node 102-2 specified in the address field discussed below), "broadcast" (e.g., addressed to all sub-nodes 102-2), and "discovery".

[0057] In some embodiments, the synchronization control frame 180 may include an I2C field. The I2C field may have any suitable length (e.g., 1 bit) and may be used to indicate that the downstream transmission period 192 includes an I2C transaction. The I2C field may indicate that the host 110 has provided an instruction for remotely accessing a peripheral device 108 that functions as an I2C slave with respect to the associated sub-node 102-2.

[0058] In some embodiments, the synchronization control frame 180 may include a node field. The node field may have any suitable length (e.g., 4 bits) and may be used to indicate which sub-node is addressed for normal access and I2C access. In discovery mode, this field may be used to program the identifier of the newly discovered sub-node 102-2 in the node ID register of the sub-node 102-2. Each sub-node 102-2 of the system 100 may be assigned a unique ID when the sub-node 102-2 is discovered by the main node 102-1, as discussed below. In some embodiments, the main node 102-1 does not have a node ID, while in other embodiments, the main node 102-1 may have a node ID. In some embodiments, the sub-node 102-2 attached to the main node 102-1 on the bus 106 (e.g., sub-node 0 in FIG. 1) is sub-node 0, and each successive sub-node 102-2 has a number one higher than the previous sub-node. However, this is merely illustrative, and any suitable sub-node identification system may be used.

[0059] In some embodiments, the synchronization control frame 180 may include a read / write (RW) field. The RW field may have any suitable length (e.g., 1 bit) and may be used to control whether the normal access is a read (e.g., RW == 1) or a write (e.g., RW == 0).

[0060] In some embodiments, the synchronization control frame 180 may include an address field. The address field may have any suitable length (e.g., 8 bits) and may be used to address a specific register of the sub-node 102-2 through the bus 106. In the case of an I2C transaction, the address field may be replaced by I2C control values such as start / stop, standby, RW, and data VLD. In the case of a discovery transaction, the address field may have a predetermined value (e.g., as shown in FIG. 5).

[0061] In some embodiments, the synchronization control frame 180 may include a data field. The data field may have any suitable length (e.g., 8 bits) and may be used for normal write, I2C write, and broadcast write. The (multiplied by 4) RESPCYCS value may be used to determine the number of cycles that a newly discovered node should allow between the start of the received synchronization control frame 180 and the start of the transmitted synchronization response frame 197. If the NAM field indicates the discovery mode, the node address field and the data field discussed below may be encoded as a RESPCYCS value that indicates in bits the time from the end of the synchronization control frame 180 to the start of the synchronization response frame 197 when multiplied by any suitable optional multiplier (e.g., 4). This allows the newly discovered sub-node 102-2 to determine an appropriate time slot for upstream transmission.

[0062] In some embodiments, the synchronization control frame 180 may include a cyclic redundancy check (CRC) field. The CRC field may have any suitable length (e.g., 16 bits) and may be used to transmit the CRC value of the control data 184 of the synchronization control frame 180 following the preamble 182. In some embodiments, the CRC may be calculated according to the CCITT-CRC error detection scheme.

[0063] In some embodiments, at least a portion of the synchronization control frame 180 between the preamble 182 and the CRC field may be scrambled in order to reduce the likelihood that the sequence of bits in this interval will periodically match the preamble 182 (and thus, at the start of a new superframe 190, can be misinterpreted by the sub-node 102-2), and to reduce electromagnetic radiation as described above. In some such embodiments, the CNT field of the synchronization control frame 180 may be used by the scrambling logic to ensure that the scrambled field is scrambled differently from one superframe to the next. Various embodiments of the system 100 described herein may omit the scrambling.

[0064] As discussed above, in addition to, or instead of, techniques such as scrambling and / or error coding, other techniques may be used to ensure that the preamble 182 can be uniquely identified by the sub-node 102-2, or to reduce the likelihood that the preamble 182 will appear elsewhere in the synchronization control frame 180. For example, a longer synchronization sequence may be used such that a particular coding of the remainder of the synchronization control frame 180 reduces the likelihood of a match thereto. Additionally or alternatively, the remainder of the synchronization control frame may be structured such that a synchronization sequence cannot occur, such as by setting fixed values of "0" or "1" to appropriate bits.

[0065] Main node 102-1 can send read requests and write requests, including both requests specific to communication on bus 106 and I2C requests, to sub-node 102-2. For example, main node 102-1 can send read requests and write requests (indicated using the RW field) to one or more specified sub-nodes 1022 (using the NAM field and node field), and the request can indicate whether it is a request for sub-node 102-2 specific to bus 106, an I2C request for sub-node 102-2, or an I2C request passed to an I2C-compatible peripheral device 108 coupled to sub-node 102-2 at one or more I2C ports of sub-node 102-2.

[0066] For upstream communication, the synchronous response frame 197 can initiate each upstream transmission. In some embodiments, the synchronous response frame 197 may be 64 bits long, but any other suitable length may be used. The synchronous response frame 197 can also include a preamble and a subsequent data portion, as discussed above with respect to the preamble 182 of the synchronous control frame 180. At the end of a downstream transmission, the last sub-node 102-2 on bus 106 can wait until the RESPCYCS counter expires and then start transmitting the synchronous response frame 197 upstream. If an upstream sub-node 102-2 is targeted by a normal read or write transaction, the sub-node 102-2 can generate its own synchronous response frame 197 and replace the one received from downstream. If, at any sub-node 102-2, the synchronous response frame 197 from the downstream sub-node 102-2 is not found within the expected time, the sub-node 102-2 generates its own synchronous response frame 197 and starts transmitting it upstream.

[0067] The data portion of the synchronous response frame 197 may include fields that contain data used to reply with response information to the main node 102-1. Examples of these fields are discussed below and several embodiments are shown in FIG. 6. Specifically, FIG. 6 shows an exemplary format for the synchronous response frame 197 in the normal mode, I2C mode, and discovery mode according to various embodiments.

[0068] In some embodiments, the synchronous response frame 197 may include a count (CNT) field. The CNT field may have any suitable length (e.g., 2 bits) and may be used to transmit the value of the CNT field of the previously received synchronous control frame 180.

[0069] In some embodiments, the synchronous response frame 197 may include an acknowledgment (ACK) field. The ACK field may have any suitable length (e.g., 2 bits) and may be inserted by the sub-node 102-2 to acknowledge the command received in the previous synchronous control frame 180 when the sub-node 102-2 generates the synchronous response frame 197. Exemplary indicators that may be communicated in the ACK field include standby, acknowledgment, negative acknowledgment (NACK), and retry. In some embodiments, the ACK field may be sized such that the sub-node 102-2 sends an acknowledgment (e.g., by sending a broadcast acknowledgment to the main node 102-1) for receiving and processing a broadcast message. In some such embodiments, the sub-node 102-2 may also indicate whether it has data to transmit (which can be used for request-based upstream transmissions, e.g., from a keypad or touch screen non-TDM input, or for prioritized upstream transmissions, e.g., when the sub-node 102-2 wants to report an error or emergency condition).

[0070] In some embodiments, the synchronization response frame 197 may include an I2C field. The I2C field may have any suitable length (e.g., 1 bit) and may be used to transmit the value of the I2C field of the previously received synchronization control frame 180.

[0071] In some embodiments, the synchronization response frame 197 may include a node field. The node field may have any suitable length (e.g., 4 bits) and may be used to transmit the ID of the sub-node 102-2 that generates the synchronization response frame 197.

[0072] In some embodiments, the synchronization response frame 197 may include a data field. The data field may have any suitable length (e.g., 8 bits), and its value may depend on the type of transaction and the ACK response of the sub-node 1022 that generates the synchronization response frame 197. In the case of a discovery transaction, the data field may include the value of the RESPCYCS field of the previously received synchronization control frame 180. When the ACK field indicates NACK or when the synchronization response frame 197 is responding to a broadcast transaction, the data field may include a broadcast acknowledgment (BA) indicator (which may indicate whether the last sub-node 102-2 received the broadcast write without error), a discovery error (DER) indicator (which indicates whether the newly discovered sub-node 102-2 in the discovery transaction matches an existing sub-node 102-2), and a CRC error (CER) indicator (which indicates whether the NACK was caused by a CRC error).

[0073] In some embodiments, the synchronization response frame 197 may include a CRC field. The CRC field may have any suitable length (e.g., 16 bits) and may be used to transmit the CRC value of the portion of the synchronization response frame 197 between the preamble and the CRC field.

[0074] In some embodiments, the synchronization response frame 197 may include an interrupt request (IRQ) field. The IRQ field may have any suitable length (e.g., 1 bit) and may be used to indicate that an interrupt has been signaled from the sub-node 102-2.

[0075] In some embodiments, the synchronization response frame 197 may include an IRQ node (IRQNODE) field. The IRQNODE field may have any suitable length (e.g., 4 bits) and may be used to transmit the ID of the sub-node 102-2 that signaled the interrupt indicated by the IRQ field. In some embodiments, the sub-node 102-2 for generating the IRQ field inserts its own ID into the IRQNODE field.

[0076] In some embodiments, the synchronization response frame 197 may include a second CRC (CRC-4) field. The CRC-4 field may have any suitable length (e.g., 4 bits) and may be used to transmit the CRC values of the IRQ field and the IRQNODE field.

[0077] In some embodiments, the synchronization response frame 197 may include an IRQ field, an IRQNODE field, and a CRC-4 field as the last bits (e.g., the last 10 bits) of the synchronization response frame 197. As discussed above, these interrupt-related fields may have their own CRC protection in the form of CRC-4 (thus not being protected by the previous CRC field). Any sub-node 102-2 that needs to signal an interrupt to the main node 102-1 inserts its interrupt information into these fields. In some embodiments, a sub-node 102-2 with an interrupt wait may have a higher priority than any further downstream sub-node 102-2 that also has an interrupt wait. The last sub-node 102-2 along the bus 106 (e.g., sub-node 2 in FIG. 1) can always populate these interrupt fields. If the last sub-node 102-2 does not have an interrupt wait, the last sub-node 102-2 may set the IRQ bit to 0, set the IRQNODE field to its node ID, and provide the correct CRC-4 value. For convenience, the synchronization response frame 197 that transmits an interrupt may be referred to herein as an "interrupt frame".

[0078] In some embodiments, at least a portion of the synchronization response frame 197 between the preamble 182 and the CRC field may be scrambled to reduce radiation. In some such embodiments, the CNT field of the synchronization response frame 197 may be used by the scrambling logic to ensure that the scrambled field is different from one superframe to the next. Various embodiments of the system 100 described herein may omit the scrambling.

[0079] As discussed above, in addition to or instead of techniques such as scrambling and / or error coding, other techniques may be used to ensure that the preamble 182 can be uniquely identified by the sub-node 102-2, or to reduce the likelihood that the preamble 182 appears elsewhere in the synchronization response frame 197. For example, a longer synchronization sequence may be used such that a particular coding of the remainder of the synchronization response frame 197 reduces the likelihood of a match. Additionally or alternatively, the remainder of the synchronization response frame may be structured such that a synchronization sequence cannot occur, such as by setting fixed values of "0" or "1" to appropriate bits.

[0080] Figure 7 is a block diagram of the bus protocol circuit 126 of FIG. 2 according to various embodiments. The bus protocol circuit 126 may include a control circuit 154 for controlling the operation of the node transceiver 120 in accordance with the protocol of the bus 106 described herein. Specifically, the control circuit 154 may control the generation of a transmission synchronization frame (e.g., a synchronization control frame or a synchronization response frame as discussed above), the processing of a received synchronization frame, and the execution of control operations specified by the received synchronization control frame. The control circuit 154 may include programmable registers as discussed below. The control circuit 154 may create and receive synchronization control frames, respond appropriately to received messages (e.g., when the bus protocol circuit 126 is included in the sub-node 102-2, in association with the synchronization control frame, or when the bus protocol circuit 126 is included in the main node 102-1, from an I2C device), and adjust the framing for different operation modes (e.g., normal, discovery, standby, etc.).

[0081] When node transceiver 120 is preparing data for transmission along bus 106, preamble circuit 156 may be configured to generate a preamble for the synchronization frame for transmission and to receive a preamble from the received synchronization frame. In some embodiments, the preamble of the downstream synchronization control frame may be sent by main node 102-1 every 1024 bits. As discussed above, one or more sub-nodes 102-2 may synchronize to the preamble of the downstream synchronization control frame and generate a local, phase-aligned main clock from the preamble.

[0082] CRC insertion circuit 158 may be configured to generate one or more CRCs for the synchronization frame for transmission. Frame / compression circuit 160 may take input data from I2S / TDM / PDM transceiver 127 (e.g., the frame buffer associated with transceiver 127), I2C transceiver 129, and / or SPI transceiver 136 and, optionally, compress the data and, optionally, generate parity check bits or error correction codes (ECCs) for the data. Multiplexer (MUX) 162 may multiplex the preamble from preamble circuit 156, the synchronization frame, and the data into a stream for transmission. In some embodiments, the transmission stream may be scrambled by scrambler circuit 164 before transmission.

[0083] For example, in some embodiments, frame / compression circuit 160 may apply a floating-point compression scheme. In such embodiments, control circuit 154 may transmit 3 bits indicating the number of repetition code bits, followed by the code bits and N-4 bits of data, where N is the size of the data transmitted via bus 106. The use of data compression may be configured by main node 102-1, if desired.

[0084] In some embodiments, the received stream entering node transceiver 120 can be descrambled by descrambling circuit 166. Demultiplexer (DEMUX) 168 can demultiplex a preamble, a synchronization frame, and data from the received stream. The receiving CRC check circuit 159 can check the received synchronization frame for correct CRC. When CRC check circuit 159 identifies a CRC defect in incoming synchronization control frame 180, control circuit 154 can be notified of the defect and will not execute any control commands of control data 184 of synchronization control frame 180. When CRC check circuit 159 identifies a CRC defect in incoming synchronization response frame 197, control circuit 154 can be notified of the defect and can generate an interrupt for transmission to host 110 in an interrupt frame. Frame release / restoration circuit 170 can receive received data, optionally check its parity, optionally perform error detection and correction (e.g., single error correction, double error detection (SECDED)), optionally restore the data, and write the received data to I2S / TDM / PDM transceiver 127 (e.g., a frame buffer associated with transceiver 127), I2C transceiver 129, and / or SPI transceiver 136.

[0085] As discussed above, upstream data and downstream data can be transmitted along bus 106 in TDM data slots within superframe 190. Control circuit 154 may include registers dedicated to the management of these data slots on bus 106, some examples of which are discussed below. When control circuit 154 is included in main node 102-1, the values of these registers can be programmed into control circuit 154 by host 110. When control circuit 154 is included in sub-node 102-2, the values of these registers can be programmed into control circuit 154 by main node 102-1.

[0086] In some embodiments, control circuit 154 may include a downstream slots (DNSLOTS) register. When node transceiver 120 is included in main node 102-1, this register may hold a value of the total number of downstream data slots. This register may also define the number of data slots used for I2S / TDM / PDM combined reception by I2S / TDM / PDM transceiver 127 of main node 102-1. At sub-node 102-2, as will be discussed in more detail below with respect to LDNSLOTS, this register may define the number of data slots passed downstream to the next sub-node 102-2, before or after the addition of locally generated downstream slots.

[0087] In some embodiments, control circuit 154 may include a local downstream slots (LDNSLOTS) register. This register may be unused at main node 102-1. At sub-node 102-2, this register may define the number of data slots that sub-node 102-2 uses and does not retransmit. Alternatively, this register may define the number of slots that sub-node 102-2 may contribute to the downstream link of bus 106.

[0088] In some embodiments, control circuit 154 may include an upstream slots (UPSLOTS) register. At main node 102-1, this register may hold a value of the total number of upstream data slots. This register may also define the number of slots used for I2S / TDM transmission by I2S / TDM transceiver 127 of main node 102-1. At sub-node 102-2, this register may define the number of data slots passed upstream before sub-node 1022 begins to add its own data.

[0089] In some embodiments, control circuit 154 may include a Local Upstream Slots (LUPSLOTS) register. This register may be unused at main node 102-1. At sub-node 102-2, this register may define the number of data slots that sub-node 102-2 adds to the data before it is sent upstream from data received downstream. This register may also define the number of data slots used for combined reception of I2S / TDM / PDM by the I2S / TDM / PDM transceiver 127 of sub-node 102-2.

[0090] In some embodiments, control circuit 154 may include a Broadcast Downstream Slots (BCDNSLOTS) register. This register may be unused at main node 102-1. At sub-node 102-2, this register may define the number of broadcast data slots. In some embodiments, broadcast data slots may always occur at the beginning of a data field. The data in the broadcast data slots may be used by multiple sub-nodes 102-2 and may be passed downstream by all sub-nodes 102-2 regardless of whether they are used or not.

[0091] In some embodiments, control circuit 154 may include a slot format (SLOTFMT) register. This register may define the format of data for upstream or downstream transmission. The data size of I2S / TDM / PDM transceiver 127 may also be determined by this register. In some embodiments, valid data sizes include 8 bits, 12 bits, 16 bits, 20 bits, 24 bits, 28 bits, and 32 bits. This register may also include bits to enable floating point compression for downstream or upstream traffic. When floating point compression is enabled, the I2S / TDM data size may be 4 bits larger than the data size via bus 106. All nodes of system 100 may have the same value for SLOTFMT when a data slot is enabled, and these nodes may be programmed by a broadcast write so that all nodes are updated with the same value.

[0092] Figures 8-11 illustrate examples of information exchange along bus 106 according to various embodiments of the bus protocol described herein. Specifically, Figures 8-11 illustrate embodiments in which each sub-node 102-2 is coupled to one or more speakers and / or one or more microphones as peripheral device 108. This is merely illustrative as any desired arrangement of peripheral device 108 may be coupled to any particular sub-node 102-2 in accordance with the techniques described herein.

[0093] First, FIG. 8 illustrates the signal transmission and timing considerations for bidirectional communication on bus 106 according to various embodiments. The sub-nodes 102-2 shown in FIG. 8 have various numbers of sensor / actuator elements, and thus, different amounts of data can be sent to or received from the various sub-nodes 102-2. Specifically, sub-node 1 has two elements, sub-node 4 has four elements, and sub-node 5 has three elements, and thus, the data transmitted by main node 102-1 includes two time slots for sub-node 1, four time slots for sub-node 4, and three time slots for sub-node 5. Similarly, sub-node 0 has three elements, sub-node 2 has three elements, sub-node 3 has three elements, sub-node 6 has one element, and sub-node 7 has four elements, and thus, the data transmitted upstream by those sub-nodes 102-2 includes the corresponding number of time slots. It should be noted that there may not be a one-to-one correlation between the elements and the time slots. For example, a microphone array having three microphones included in the peripheral device 108 may combine signals from the three microphones (and, optionally, information received from the main node 102-1 or other sub-nodes 1022) to produce a single data sample that may correspond to a single time slot or multiple time slots depending on the type of processing, and may include a DSP.

[0094] In FIG. 8, main node 102-1 transmits the SCF, followed by data for a speaker coupled to a particular sub-node 102-2 (SD). Each successive sub-node 1022 transfers the SCF and also transfers at least any data destined for a downstream sub-node 102-2. The particular sub-node 102-2 may transfer all data or may delete data destined for that sub-node 102-2. When the last sub-node 102-2 receives the SCF, that sub-node 102-2 transmits the SRF and optionally then transmits any data that the sub-node 102-2 is permitted to transmit. Each successive sub-node 102-2 transfers the SRF along with any data from a downstream sub-node 102-2 and optionally inserts data from one or more microphones coupled to a particular sub-node 102-2 (MD). In the example of FIG. 8, main node 102-1 sends data to sub-nodes 1, 4, and 5 (shown as active speakers in FIG. 8) and receives data from sub-nodes 7, 6, 3, 2, and 0 (shown as microphone arrays in FIG. 8).

[0095] FIG. 9 schematically illustrates the dynamic deletion of data from a downstream transmission and the insertion of data into an upstream transmission from the perspective of the downstream DS transceiver 124 according to various embodiments. In FIG. 9, similar to FIG. 8, the main node 102-1 transmits data for the SCF and then for the sub-nodes 1, 4, and 5 (SD) in reverse order (e.g., after the data for sub-node 5, the data for sub-node 4 follows, and then the data for sub-node 1 follows, etc.) (see the row labeled main). When this transmission is received by sub-node 1, sub-node 1 deletes its own data and transfers only the SCF and the subsequent data for sub-nodes 5 and 4 to sub-node 2. Sub-nodes 2 and 3 transfer the data transferred by sub-node 1 without modification so that the data is received by sub-node 4 (see the row labeled sub3) (see the row labeled sub2). Sub-node 4 deletes its own data and transfers only the SCF and the subsequent data for sub-node 5 to sub-node 5. Similarly, sub-node 5 deletes its own data and transfers only the SCF to sub-node 6. Sub-node 6 transfers the SCF to sub-node 7 (see the row labeled sub6).

[0096] At this point, sub-node 7 sends the SRF and then its own data to sub-node 6 (see the line marked as sub 6). Sub-node 6 transfers the SRF together with the data from sub-node 7 and its own data to sub-node 5. Next, sub-node 5 transfers the SRF together with the data from sub-node 7 and sub-node 6 to sub-node 4. Sub-node 4 has no data to add, so it simply transfers the data to sub-node 3 (see the line marked as sub 3). Sub-node 3 transfers the data together with its own data to sub-node 2 (see the line marked as sub 2). Next, sub-node 2 transfers the data together with its own data to sub-node 1. Sub-node 1 has no data to add, so it transfers the data to sub-node 0, and sub-node 0 transfers the data together with its own data. As a result, main node 102-1 receives the SRF and then the data from sub-nodes 7, 6, 3, 2, and 0 (see the line marked as main).

[0097] FIG. 10, similar to FIG. 9, illustrates another example of dynamic deletion of data from a downstream transmission and insertion of data into an upstream transmission from the perspective of the downstream DS transceiver 124. In FIG. 10, sub-node 102-2 is coupled to both a sensor and an actuator as peripheral devices 108 such that main node 102-1 sends data to all of the downstream sub-nodes 102-2 and receives data returning from all of the sub-nodes 102-2. Also in FIG. 10, the data is ordered based on the node address of its destination or the node address of its source. The data slot marked as "Y" can be used for data integrity checking or data correction.

[0098] FIG. 11, similar to FIG. 9, illustrates another example of dynamic deletion of data from a downstream transmission and insertion of data into an upstream transmission from the perspective of the downstream DS transceiver 124. In FIG. 11, however, the data is transmitted sequentially downstream and upstream, rather than in reverse order. Buffering at each sub-node 102-2 enables selective addition, deletion, and / or transfer of data.

[0099] As discussed above, each sub-node 102-2 may delete data from a downstream or upstream transmission and / or may add data to a downstream or upstream transmission. Thus, for example, the main node 102-1 may send distinct data samples to each of several sub-nodes 102-2, and each such sub-node 102-2 may delete its own data sample and transfer only the data directed to downstream sub-nodes 102-2. On the other hand, a sub-node 102-2 may receive data from a downstream sub-node 102-2 and transfer that data along with additional data. One advantage of transmitting only as little information as necessary is to reduce the amount of power consumed by the system 100 as a whole.

[0100] System 100 may also support broadcast transmissions (and multicast transmissions) from the main node 102-1 to the sub-nodes 102-2, specifically through the configuration of the downstream slot usage of the sub-nodes 102-2. Each sub-node 102-2 may process a broadcast transmission and pass it on to the next sub-node 102-2, but a particular sub-node 102-2 may "consume" (i.e., not pass on) the broadcast message to the next sub-node 102-2.

[0101] System 100 may also support upstream transmissions (e.g., from a particular sub-node 102-2 to one or more other sub-nodes 102-2). Such upstream transmissions may include unicast upstream transmissions, multicast upstream transmissions, and / or broadcast upstream transmissions. As discussed above with respect to downstream transmissions, through upstream addressing, sub-node 102-2 may determine whether to delete data from an upstream transmission and / or whether to forward the upstream transmission to the next upstream sub-node 102-2 based on the configuration of the upstream slot usage of sub-node 102-2. Thus, for example, data may be communicated to one or more other sub-nodes 102-2 in addition to or instead of communicating the data to main node 1021 by a particular sub-node 102-2. Such sub-sub relationships may be configured, for example, through main node 102-1.

[0102] Accordingly, in various embodiments, sub-node 102-2 may operate as an active / intelligent relay node having the ability to selectively transfer, delete, and add information. Since each sub-node 102-2 knows the associated time slots for receiving / transmitting data internally, sub-node 102-2 can generally perform such functions without necessarily decrypting / considering all of the data, and thus can delete data from or add data to a time slot. Sub-node 102-2 may typically re-clock the data being transmitted / forwarded even though it may not be necessary to decrypt / consider all of the data. This may enhance the robustness of system 100.

[0103] In some embodiments, bus 106 may be configured for one-way communication in a ring topology. For example, FIG. 12 illustrates an arrangement 1200 of main node 102-1 and four sub-nodes 102-2 in a ring topology, and illustrates signal transmission and timing considerations for one-way communication in arrangement 1200 according to various embodiments. In such embodiments, node transceiver 120 within a node may include a receive-only transceiver (main input) and a transmit-only transceiver (main output), rather than two bi-directional transceivers for upstream and downstream communication. In the link layer synchronization scheme shown in FIG. 12, main node 102-1 transmits synchronization control frame 180 and, optionally following that, "downstream" data 1202 for three speakers coupled to various sub-nodes 102-2 (as discussed above with reference to FIGS. 8-11, data for different speakers may be arranged in any suitable order), and each successive sub-node 102-2 transfers synchronization control frame 180 along with any "upstream" data from the previous sub-node 102-2 and its own "upstream" data to provide "upstream" data 1204 (e.g., as discussed above with reference to FIGS. 8-11, data from eight different microphones may be arranged in any suitable order).

[0104] As described herein, data may be communicated between elements of system 100 in any of several ways. In some embodiments, data may be sent upstream by subnode 102-2 (e.g., using data slot 199) or downstream by subnode 102-2 or main node 102-1 (e.g., using data slot 198) as part of a set of synchronization data slots. The amount of such data may be adjusted by changing the number of bits in a data slot or by including additional data slots. In system 100, data may also be communicated by inclusion in synchronization control frame 180 or synchronization response frame 197. Data communicated in this manner may include I2C control data from the host 110 (with responses from the peripheral device 108 associated with subnode 102-2), accesses to registers in subnode 102-2 (e.g., for slot and interface discovery and configuration), which may include write accesses from the host 110 / main node 102-1 to subnode 102-2 and read accesses from subnode 102-2 to the host 110 / main node 102-1, and event signaling via interrupts from the peripheral device 108 to the host 110. In some embodiments, a GPIO pin may be used to communicate information from subnode 102-2 to the main node 102-1 (e.g., by having the main node 102-1 poll the GPIO pin via I2C or by having the node transceiver 120 of subnode 102-2 generate an interrupt on an interrupt request pin). For example, in some such embodiments, the host 110 may send information to the main node 102-1 via I2C, which in turn may send that information to the subnode 102-2 via a GPIO pin. Any of the types of data discussed herein as being transmitted via the bus 106 may be transmitted using any one or more of these communication paths. Other types of data and data communication techniques within the system 100 may be disclosed herein.

[0105] Embodiments of the present disclosure can be implemented within a system using any suitable hardware and / or software to configure as desired. FIG. 13 schematically illustrates a device 1300 that can function as a host or node (e.g., host 110, main node 102-1, or sub-node 102-2) in a system 100 according to various embodiments. Although several components are shown in FIG. 13 as being included in the device 1300, any one or more of these components can be omitted or replicated as suitable for the application.

[0106] In addition, in various embodiments, the device 1300 may not include one or more of the components shown in FIG. 13, but the device 1300 may include an interface circuit for coupling to one or more of those components. For example, the device 1300 may not include a display device 1306, but may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1306 can be coupled. In another set of examples, the device 1300 may not include an audio input device 1324 or an audio output device 1308, but may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1324 or the audio output device 1308 can be coupled.

[0107] According to any of the embodiments disclosed herein, device 1300 may include a node transceiver 120 for managing communication along bus 106 when device 1300 is coupled to bus 106. Device 1300 may include a processing device 1302 (e.g., one or more processing devices) that may be included in node transceiver 120 or may be separate from node transceiver 120. As used herein, the term "processing device" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that may be stored in registers and / or memory. Processing device 1302 may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptographic processors, or any other suitable processing device. Device 1300 may include a memory 1304, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or hard disk drive.

[0108] In some embodiments, memory 1304 may be used to store a working copy and a permanent copy of programming instructions that cause device 1300 to execute any suitable one of the techniques disclosed herein. In some embodiments, machine-accessible media (including non-transitory computer-readable storage media), methods, systems, and devices for performing the above techniques are examples as illustrations of the embodiments disclosed herein. For example, a computer-readable medium (e.g., memory 1304) may have stored instructions that, when executed by one or more of the processing devices included in processing device 1302, cause device 1300 to execute any of the techniques disclosed herein.

[0109] In some embodiments, device 1300 may include another communication chip 1312 (e.g., one or more other communication chips). For example, communication chip 1312 may be configured to manage wireless communication for data transfer to and from device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated devices do not include any wiring, although in some embodiments they may not.

[0110] The communication chip 1312 can implement any one of several wireless standards or protocols, including Wi-Fi (IEEE802.11 family), Institute of Electrical and Electronics Engineers (IEEE) standards including the IEEE802.16 standard (e.g., IEEE802.16-2005 amendment), any amendments, updates, and / or revisions (e.g., the Long Term Evolution (LTE) project, the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2", etc.), but not limited thereto. The IEEE802.16 compatible broadband wireless access (BWA) network is generally called a WiMAX network, which is an acronym representing Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass the IEEE802.16 standard compliance test and interoperability test. One or more communication chips 1312 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or an LTE network. One or more communication chips 1312 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). One or more communication chips 1312 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and later. In other embodiments, the communication chip 1312 can operate according to other wireless protocols. The device 1300 can include an antenna 1322 to facilitate wireless communication and / or receive other wireless communications (such as AM radio transmission or FM radio transmission).

[0111] In some embodiments, communication chip 1312 may manage wired communication using a protocol other than the protocol for bus 106 described herein. Wired communication may include an electrical communication protocol, an optical communication protocol, or any other suitable communication protocol. Examples of wired communication protocols that may be enabled by communication chip 1312 include Ethernet, controller area network (CAN), I2C, media-oriented systems transport (MOST), or any other suitable wired communication protocol.

[0112] As described above, communication chip 1312 may include a plurality of communication chips. For example, a first communication chip 1312 may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth®, and a second communication chip 1312 may be dedicated to global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other long-range wireless communication. In some embodiments, the first communication chip 1312 may be dedicated to wireless communication, and the second communication chip 1312 may be dedicated to wired communication.

[0113] Device 1300 may include a battery / power circuit 1314. Battery / power circuit 1314 may include one or more energy storage devices (e.g., a battery or a capacitor), and / or circuitry for coupling components of device 1300 to an energy source separate from device 1300 (e.g., an AC line power supply, a voltage provided by an automotive battery, etc.). For example, battery / power circuit 1314 may include upstream bus interface circuit 132 and downstream bus interface circuit 131 discussed above with reference to FIG. 2 and may be charged by a bias on bus 106.

[0114] Device 1300 may include a display device 1306 (or a corresponding interface circuit as discussed above). The display device 1306 may include any visual indicator, such as, for example, a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0115] Device 1300 may include an audio output device 1308 (or a corresponding interface circuit as discussed above). The audio output device 1308 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earphones.

[0116] Device 1300 may include an audio input device 1324 (or a corresponding interface circuit as discussed above). The audio input device 1324 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device having MIDI output).

[0117] Device 1300 may include a GPS device 1318 (or a corresponding interface circuit as discussed above). As is well known in the art, the GPS device 1318 may communicate with a satellite-based system and receive the location of the device 1300.

[0118] Device 1300 may include another output device 1310 (or a corresponding interface circuit as discussed above). Examples of another output device 1310 may include an audio codec, a video codec, a printer, a wired transmitter or a wireless transmitter for providing information to other devices, or an additional storage device. Additionally, any suitable one of the peripheral devices 108 discussed herein may be included in another output device 1310.

[0119] Device 1300 may include another input device 1320 (or a corresponding interface circuit as discussed above). Examples of another input device 1320 may include an accelerometer, a gyroscope, an image capture device, a keyboard, a cursor control device (such as a mouse, a touch pen, a touch pad, etc.), a barcode reader, a quick response (QR) code reader, or a radio frequency identification (RFID) reader. Additionally, any suitable one of the sensors or peripheral devices 108 discussed herein may be included in another input device 1320.

[0120] Any suitable one of the display device, input device, output device, communication device, or memory device described above with respect to device 1300 may function as a peripheral device 108 of system 100. Alternatively or additionally, a suitable one of the display device, input device, output device, communication device, or memory device described above with respect to device 1300 may be included in a host (such as host 110) or a node (such as main node 102-1 or sub-node 102-2).

[0121] The elements of system 100 can be selected and configured to provide voice control and / or light control via bus 106. In some embodiments, system 100 may be configured to function as a light control system in a vehicle or other environment, comprising a lighting device (e.g., a strip line light emitting diode (LED) or other LED arrangement) that functions as a peripheral device 108 communicating with node 102 along bus 106, and data may be communicated via bus 106 to control the color, intensity, duty cycle, and / or other parameters of the lighting device. In some embodiments, system 100 may be configured to function as a voice control system in a vehicle or other environment, comprising a microphone or other device that includes an accelerometer and functions as a peripheral device 108 communicating with node 102 along bus 106, and data from the accelerometer may be communicated via bus 106 to control other peripheral devices 108 along bus 106. For example, large spikes in acceleration data or other predetermined acceleration data patterns may be used to cause the generation of acoustic effects such as couvettes or drum hits by a processing device coupled to node 102, and the acoustic effects may be output by a speaker coupled to the processing device and / or a speaker coupled to another node 102 along bus 106. Some embodiments of system 100 may combine any of the lighting control techniques and / or voice control techniques disclosed herein.

[0122] While the various embodiments discussed above describe system 100 in a vehicle setting, this is merely illustrative and system 100 can be implemented in any desired setting. For example, in some embodiments, a "portable" implementation of system 100 may include a portable housing containing the desired components of system 100, and such an implementation may be particularly suitable for portable applications such as portable karaoke or entertainment systems.

[0123] Figures 14-18 illustrate exemplary systems and techniques for synchronous voice communication and bus power via a CAT cable with an 8P8C connector. The cable can be a shielded or unshielded TIA CAT cable such as a Category 5 (CAT5), Category 6 (CAT6), Category 7 (CAT7), or CAT8 (CAT8) cable, and the cable can be an Ethernet cable. The connector can be an 8-position / 8-conductor (8P8C) shielded or unshielded connector such as an RJ45 connector. (For example, in an embodiment of System 100) the network bus can be a two-wire bus. In some examples, the network bus provided herein applies bus power in a stepwise and negotiated manner and shares differential communication line pairs with supply and return currents. This is in contrast to asynchronous packet-based PoE.

[0124] Generally, since audio connections in studios and stages are analog, they are susceptible to noise and interference. It is expected that audio stages and studios will transition from the use of legacy analog wiring (e.g., guitar cables using a single monaural signal) to digital connections using multi-channel audio signals on the same cable (e.g., each of the six strings of a guitar can pick up its sound individually and communicate on the same cable as six separate audio channels). In building automation and conference rooms, CAT cables with 8P8C (RJ45) connectors are used to connect ceiling-mounted microphone arrays and speakers to Ethernet over distances of up to 100 m. However, Ethernet is asynchronous packet-based communication and is not ideal for audio. Ethernet packets need to be resynchronized and resynthesized into the audio clock and audio phase at each end node. Packet-based communication is inefficient and adds undesirable latency.

[0125] An audio clock synchronization communication system offers many advantages. It is simpler and enables a very short latency. Power over data line is also highly desirable for enabling the reuse of communication cables for power, thus avoiding extra cables for power wiring. PoE, as standardized by the IEEE, is complex and requires specialized PSEs and PDs that communicate / negotiate with power pulses external to the Ethernet PHY-MAC layer. CAT cables with 8P8C (RJ45) connectors are ubiquitous for Ethernet connections and may even carry voltages up to minus 57V for PoE. The cable connector combinations are inexpensive, have good digital communication characteristics, and are readily available in many retail stores. Therefore, it is desirable to use them not only in conference rooms but also on stages, inside audio studios, and for other digital audio wiring applications for synchronous audio communication.

[0126] In this specification, systems and techniques are provided for reducing the complexity of PoE by providing different Power over Data Line schemes (PoDs) for protecting a PoD device when plugged into a PoE PSE device and for protecting a PoE device when plugged into a PoD device. The PoD circuit does not need to support the supply voltage range of PoE nor the complexity of PoE when accidentally plugged into a PoE device. In PoE, the paired differential lines are biased together for power, and another pair is biased for return current. In contrast, PoD biases one line of a pair with power and uses the other line of the pair as return current. Different from Ethernet, which uses more expensive transformers, cost-effective inductors are used for bias injection into the communication line. Additionally, as described in this specification, in some examples, only one pair of lines is used for communication, and the other pairs are capable of carrying a high bus voltage negotiated without low-pass filtering (and without transformer coupling).

[0127] The communication path on the communication line is high-pass filtered through a series capacitor, while on the same line, the bias is induced by a low-pass filter on one line of the differential line pair and returned by a low-pass filter on the other line. The next sequential node draws power with a low-pass filter in the form of an inductor and communicates via a high-pass filter in the form of a series capacitor. The next sequential node uses bus power from the differential communication line for the bus transceiver and for a memory device (e.g., EEPROM). The current-limited low-voltage bus bias is applied to the communication line pair through a voltage regulator and a current-limiting device or directly by a current-limiting voltage regulator. The device has a PG or similar signal that indicates good operation only when there is no overcurrent situation. An overcurrent on the output side of such a device also reduces the output voltage and thus limits the power draw for overcurrent protection.

[0128] In various embodiments, a method for providing synchronous voice communication and bus power via a CAT cable with an 8P8C connector includes several steps. First, the current is limited and a low-voltage bus bias is applied to the communication line pair. In some examples, the low-voltage bus bias is applied with a slow ramp. An overcurrent event (e.g., a short circuit of the wire) prevents progression to the next step and periodic retries can be attempted after a waiting period. Since the communication transformer of the differential line pair is short-circuited, a connection to an Ethernet device is considered an overcurrent event.

[0129] Second, communication is initiated and the next sequential node is discovered. If communication cannot be established, perhaps no valid node is connected. Periodic retries from the first step can be attempted after a waiting period.

[0130] Third, the next sequential memory (e.g., EEPROM) is read for information regarding the node and the node capabilities including power capabilities. If it does not match the expected content, there may be an unsupported device. Periodic retries from the first step can be attempted after a waiting period.

[0131] Fourthly, high voltage and high power are applied to other bus lines according to the power supply capabilities of the next-order nodes. This can be performed as part of rediscovery and may include PFET or NFET using a slow ramp method and a charge pump to prevent excessive current draw during charging of the capacitor of the bus power supply node. Line current protection can be applied by sensing a series resistor to prevent overcurrent situations during incorrect handling of the connector. Line diagnostics coupled to the sense resistor and FET switch can determine whether there is an open circuit or short circuit. If there is a problem with the line diagnostics, after a waiting period, a periodic retry from step 1 can be attempted.

[0132] Fifthly, when high voltage is supplied, the next-order node can be powered to the device at that voltage, provide the derived low-voltage current-limiting bias to the next link, repeat the process with the next node, discover multiple daisy-chain-connected nodes, and further, power the nodes of it.

[0133] The above sequence tests the link using a current-limited low current, low voltage source. Thus, the method protects against overcurrent that can damage the Ethernet transformer (when accidentally plugged into an Ethernet device) or the risk of fire during a hard short. As shown in FIGS. 15A - 15C, FIGS. 16, and FIGS. 17A - 17C, the use of the pins will cause an immediate short circuit when the PoE device is plugged into the PoD device and will retreat from the power supply to the connector.

[0134] FIG. 14 is a flowchart 1400 showing a discovery sequence method applied at the main node of a network bus. First, a low voltage, low current bias is applied to the downstream communication line (if not already applied previously). Next, it is determined whether there is a power good (or similar) signal from a low voltage, low current voltage regulator. The PG signal indicates that there is no overcurrent. In some examples, the method searches for the PG signal for a selected period, and if the PG signal is not detected during the selected period, it is determined that the PG signal does not exist. If there is no PG signal, the method skips to the last step of periodically (e.g., every second) retrying the method starting from the first step. If there is a PG signal, the downstream node is discovered. Next, it is determined whether the discovery of the downstream node was successful. If the discovery of the downstream node was not successful, the method skips to the last step as described above.

[0135] If the discovery of the downstream node is successful, the method proceeds to read the memory contents (e.g., EEPROM contents) of the discovered downstream node for node identification and node capability information. Node capabilities can include indicating whether the node is locally powered or bus-powered, whether high voltage is used, and the amount of power used to operate the node.

[0136] When node information is read, it is determined whether the discovered downstream node is supported. If the downstream node is not supported, the method skips to the last step as described above. If the downstream node is supported, it is determined whether the downstream node uses a high bus power voltage and whether it can provide the required high bus power voltage. If the node uses a high bus power voltage and can provide the required high bus power voltage, the method proceeds to attempt to apply the high voltage to the 8P8C connector pins that carry the high voltage. This can also occur as part of rediscovery. Line diagnostics are performed to determine whether there is an overcurrent problem. If there is an overcurrent problem (or if the line diagnostics are not OK), the method skips to the second to last step, turns off the downstream high voltage bus power, and proceeds to the last step as described above. If the line diagnostics are OK and there is no overcurrent problem, the downstream node is fully initialized and in some examples, peripheral devices are enabled. Similarly, if the downstream node does not use a high bus power voltage, the method skips the high voltage application step and the line diagnostics step and proceeds to fully initialize the downstream node.

[0137] Next, it is determined whether HV = 1 or the downstream node is locally powered and whether there are more nodes to be discovered. If not, the bus is fully discovered and the method ends. In some examples, the method can further retry periodically to check whether additional nodes have been added. If so, the downstream node becomes the node that discovers the next downstream node and the method restarts at the beginning of the method.

[0138] Figures 15A - 15C are block diagrams of a system for synchronous voice communication and bus power according to various embodiments of the present disclosure. Specifically, FIG. 15A shows a main node 1502 connected to a bus - powered sub - node 1504 via an 8P8C connector 1506. The 8P8C connector includes eight pins arranged in four pairs. In various examples, pin 1 and pin 2 are paired, pin 3 and pin 6 are paired, pin 4 and pin 5 are paired, and pin 7 and pin 8 are paired. In some examples, pins 2 and 3 are connected to each other but are biased differently. In some examples, pins 4 and 5 form a communication channel. Pins 4 and 5 have a strong twist.

[0139] An Ethernet cable is used, but Ethernet or PoE bus biasing is not used. Thus, a typical Ethernet connector plugged into connector 1506 will cause a short - circuit. For example, pins 1 and 2 of connector 1506 form a twisted pair, pin 1 is connected to ground, and pin 2 has a positive power supply. However, in a typical Ethernet connector, since pins 1 and 2 enter the transformer, it is transformer - coupled. Thus, when the main node 1502 is plugged into a typical Ethernet connector, a short - circuit will occur because it follows the transformer. Therefore, when the main node or sub - node of the present disclosure is plugged into a typical Ethernet connector, a short - circuit will occur. Similarly, when a PoE device is plugged into connector 1806, a short - circuit will occur.

[0140] FIG. 15B shows the detailed architecture of the main node 1502 according to various embodiments of the present disclosure. FIG. 15C shows the detailed architecture of the bus - powered sub - node 1504 according to various embodiments of the present disclosure.

[0141] In FIG. 15B, a voltage regulator (e.g., a 5V voltage regulator) or a current limiter is used to ensure that when there is a short circuit, the bias is as weak as possible (e.g., a maximum of 50 mA) and the circuit stops. The bias (e.g., 50 mA) is sufficient to power the sub-node and, in some examples, the EEPROM. The EEPROM can provide information regarding the node, as described above with respect to the method of FIG. 14.

[0142] The NFET (NFET1) connected to pins 2, 3, and 7 can provide a voltage and thus provide bus power when it is confirmed that the sub-node has been discovered and approved. The voltage can be, for example, 24 volts. The voltage provides the sub-node with full bus power capabilities. Further, as shown in FIG. 15C, the voltage drives a voltage regulator (e.g., a 5V regulator) coupled to the next sub-node and, when the next sub-node is discovered and approved, can turn on the NFET within the sub-node to provide a voltage to the next sub-node.

[0143] FIG. 16 is a diagram showing an architecture for separation on the A side of a local power supply node according to various embodiments of the present disclosure. The sub-node SN can use local power instead of bus power. Such local power can be a source as a DC supply from a wall-mounted transformer with a rectifier (simplified and drawn as just a transformer in the local power diagram). In such a node, auxiliary bus power is not used, but may or may not be wired. Here, the differential signal transformer on the communication line ensures galvanic isolation of the sub-node from the upstream sub-node. The signal transformer consists of windings facing two connectors and windings facing two transceivers. The windings facing the transceivers are joined directly (or indirectly, e.g., via a capacitor) at an intermediate point and capacitively coupled to a local ground or local bias point. The other ends of the windings are connected to the transceivers as AC-coupled (through the transformer) communication signals. The outer tails of the windings facing the connectors are coupled to the connectors. The inner tails of the windings facing the connectors are AC-coupled trough capacitors and provide a resistive termination that matches the impedance of the cable. The inner tails of the inner tails are also connected (through a resistor) to the optocoupler LED. Thereby, the secondary side of the optocoupler can sense the bus bias ("A-side detection"). This uses a power enable signal for the voltage regulator or power gating device of the local power supply node. This is one way to combine galvanic isolation, differential and common-mode line terminations, and galvanic isolation remote power enable through the bus bias sensed from the upstream node. The upstream node provides the bus bias only when it wants to enable the downstream node.

[0144] FIGS. 17A-17C are diagrams showing the architecture of a locally powered sub-node. As shown in FIGS. 16 and 17A-17C, the locally powered sub-node includes an optocoupler that functions as a wake-up of the sub-node, so the node is not powered unless it is turned on.

[0145] In various examples, the main node can include a negative-side (low-side) switch to enable line diagnostics.

[0146] In some examples, the NFET within the main node can include a charge pump to make the NFET more efficient. If the voltage accumulation due to current is too much, the switch can be opened to prevent further voltage accumulation.

[0147] Repeating, at the main node, when looking for a short to ground through the VSENSEP and VSENSEN pins, the positive and negative lines are charged simultaneously with a bias voltage where the limited current exceeds ground. Here, since there is no N-side switch, the connection to the load capacitance of the 24V supply is differential. The load capacitance is higher than ground to prevent false detection of a ground short. More current is provided to charge the differential capacitor. A diode and a resistor are included to pull VSENSEP higher than the voltage above ground. When it is determined that there is no short, 24 volts are applied to the NFET, and the diode and resistor help prevent the 24 volts from returning to VIN.

[0148] Selected embodiments Embodiment 1 provides a system for synchronous communication and power via a network bus that includes a main node, a sub-node, and an 8-pin connector.

[0149] Embodiment 2 includes the subject matter according to any of the preceding embodiments and / or subsequent embodiments,

[0150] Embodiment 3 includes the subject matter according to any of the preceding embodiments and / or subsequent embodiments, and further specifies that the sub-node is coupled to a peripheral device in any of the two-wire communication systems disclosed herein.

[0151] Embodiment 4 provides a system according to any of the preceding embodiments and / or subsequent embodiments where the peripheral device includes one or more microphones.

[0152] Example 5 provides a system according to any of the preceding and / or subsequent examples, further comprising a two-wire bus, wherein the memory is positioned on a sub-node of the network bus.

[0153] Variations and embodiments As such, while several aspects and embodiments of the technology of this application have been described, it is to be understood by those skilled in the art that various changes, modifications, and improvements will readily occur. Such changes, modifications, and improvements are intended to be within the spirit and scope of the technology described in this application. For example, those skilled in the art can readily envision various other means and / or structures for performing the functions and / or obtaining one or more of the results and / or advantages described herein, and each such variation and / or modification is considered to be within the scope of the embodiments described herein.

[0154] Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. Accordingly, the foregoing embodiments are presented by way of example only, and it is to be understood that inventive embodiments may be practiced otherwise than as specifically described within the scope of the appended claims and their equivalents. Additionally, any combination of two or more of the features, systems, articles, materials, kits, and / or methods described herein is included within the scope of the present disclosure if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent.

[0155] The foregoing outlines features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable those skilled in the art (PHOSITA) to better understand the various aspects of the present disclosure. Certain well-understood terms, as well as underlying technologies and / or standards, may be referred to without detailed explanation. It is expected that the PHOSITA has, or can access, background knowledge or information in these technologies and standards sufficient to practice the teachings of the present disclosure.

[0156] One of ordinary skill in the art will appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes, structures, or variations to perform the same functions and / or achieve the same advantages as the embodiments described herein. One of ordinary skill in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

[0157] The above-described embodiments may be implemented in any of a number of ways. One or more aspects and embodiments of the present application involving the performance of a process or method may utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform or control the performance of the process or method.

[0158] In this regard, various inventive concepts may be embodied as one or more programs encoded on a computer-readable storage medium (or multiple computer-readable storage media) (e.g., computer memory, one or more floppy disks, compact disks, optical disks, magnetic tapes, flash memories, circuit configurations of field programmable gate arrays or other semiconductor devices, or other tangible computer storage media), and when the one or more programs are executed on one or more computers or other processors, perform a method of implementing one or more of the various embodiments described above.

[0159] A computer-readable medium may be transportable such that the program stored thereon can be loaded onto one or more different computers or other processors to implement various ones of the aspects described above. In some embodiments, the computer-readable medium may be a non-transitory medium.

[0160] The activities discussed above with reference to the drawings, which are applicable to any integrated circuit involving signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), and in particular can execute specialized software programs or algorithms, some of which may be associated with the processing of digitized real-time data.

[0161] In some cases, the teachings of this disclosure, when executed, may be encoded on one or more tangible non-transitory computer-readable media that store executable instructions for instructing a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. If the teachings of this specification are at least partially embodied in a hardware device (such as an ASIC, IP block, or SoC), the non-transitory medium may include a hardware device that is hardware-programmed with the logic for performing the methods or functions disclosed herein. The teachings can also be implemented in the form of a register transfer level (RTL), or other hardware description languages such as VHDL or Verilog, which can be used to program a manufacturing process for creating the disclosed hardware elements.

[0162] In an exemplary implementation, at least some portions of the processing activities outlined herein may also be implemented in software. In some embodiments, one or more of these features may be implemented in hardware provided external to the elements of the disclosed figures, or integrated in any suitable manner to achieve the intended function. The various components may include software (or interconnected software) that can be associated to achieve the operations as outlined herein. In still other embodiments, these elements may include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that facilitate their operations.

[0163] Any appropriately configured processor component can execute any kind of instructions associated with data to achieve the operations detailed herein. Any processor disclosed herein can transform an element or article (e.g., data) from one state or thing to another state or thing. In another example, some of the activities outlined herein may be implemented in fixed logic or programmable logic (e.g., software and / or computer instructions executed by a processor), and the elements identified herein can be of some kind of programmable processor, programmable digital logic (e.g., FPGA, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), digital logic, software, code, electronic instructions, flash memory, optical disk, CD-ROM, DVD ROM, magnetic card or optical card, other kinds of machine-readable media suitable for storing electronic instructions, or an ASIC including any suitable combination thereof.

[0164] During operation, the processor can store information in any suitable kind of non-transitory storage medium (e.g., random access memory (RAM), read-only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or, as needed and based on specific needs, any other suitable component, device, element, or object. Further, the information being tracked, sent, received, or stored by the processor can be provided in any database, register, table, cache, queue, control list, or storage structure, all of which can be referenced in any suitable time frame, based on specific needs and implementation examples.

[0165] Any of the memory items discussed in this specification should be construed as being included in the broad sense of "memory". Similarly, any of the potential processing elements, modules, and machines described in this specification should be construed as being included in the broad sense of "microprocessor" or "processor". Further, in various embodiments, the processors, memories, network cards, buses, storage devices, associated peripheral devices, and other hardware elements described in this specification may be implemented by processors, memories, and other associated devices configured by software or firmware to emulate or virtualize the functions of those hardware elements.

[0166] Furthermore, it should be understood that the computer can be embodied in any of several forms, by way of non-limiting example, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, the computer may be embedded in a device having suitable processing capabilities, including, but not limited to, personal digital assistants (PDAs), smartphones, mobile phones, iPads (registered trademark), or any other suitable portable or fixed electronic device.

[0167] Also, the computer may have one or more input devices and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include a printer or display screen for visual presentation of output, and a speaker or other audio generating device for audible presentation of output. Examples of input devices that can be used for a user interface include a keyboard, as well as pointing devices such as a mouse, touchpad, and digitizing tablet. As another example, the computer may receive input information through speech recognition or in other audible formats.

[0168] Such computers can be interconnected by one or more networks in any suitable form, including local area networks such as enterprise networks or wide area networks, and intelligent networks (IN) or the Internet. Such networks may be based on any suitable technology, may operate according to any suitable protocol, and may include wireless networks or wired networks.

[0169] Computer-executable instructions may be in many forms such as program modules, which are executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. Typically, the functions of program modules may be combined or distributed as desired in various embodiments.

[0170] The term "program" or "software" as used herein is used in a general sense and refers to any type of computer code or set of computer-executable instructions employed to program a computer or other processor to implement various aspects of the embodiments described above. Additionally, according to one aspect, it should be understood that one or more computer programs that, when executed, implement the methods of the present application need not be present on a single computer or processor, but may be distributed in a modular fashion among several different computers or processors for implementing various aspects of the present application.

[0171] Also, the data structure can be stored in a computer-readable medium in any suitable form. For the sake of simplicity of explanation, it can be shown that the data structure has fields associated through locations within the data structure. Such relationships may likewise be achieved by allocating a storage device for fields having locations within the computer-readable medium that convey relationships between the fields. However, any suitable mechanism can be used to establish relationships between information within fields of the data structure, including the use of pointers, tags, or other mechanisms for establishing relationships between data elements.

[0172] When implemented in software, the software code can be executed on any suitable processor or set of processors, whether provided on a single computer or distributed among multiple computers.

[0173] The computer program logic for implementing all or part of the functions described herein can be embodied in various forms including, but not limited to, source code form, computer-executable form, hardware description form, and various intermediate forms (e.g., mask work, or forms generated by an assembler, compiler, linker, or locator). In one example, the source code includes a series of computer program instructions implemented in various programming languages such as object code, assembly language, or high-level languages such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA (registered trademark), or HTML for use with various operating systems or operating environments. The source code can define and use various data structures and communication messages. The source code can be in computer-executable form (e.g., via an interpreter program), or the source code can be converted to computer-executable form (e.g., via a converter, assembler, or compiler).

[0174] In some embodiments, any number of electrical circuits in the drawings may be implemented on a substrate of an associated electronic device. The substrate can be a general circuit board that can house various components of the internal electronic system of the electronic device and can further provide connectors for other peripheral devices. More specifically, the substrate can provide electrical connections that enable electrical communication between other components of the system. Any suitable processors, memory elements, etc. (including digital signal processors, microprocessors, support chip sets, etc.) can be appropriately coupled to the substrate based on specific configuration needs, processing requirements, computer designs, etc.

[0175] Other components such as external storage, additional sensors, audio / video display controllers, and peripheral devices may be attached to the substrate via a cable as a plug-in card or may be incorporated into the substrate itself. In another exemplary embodiment, the electrical circuits in the drawings may be implemented as a stand-alone module (e.g., a device having associated components and circuits configured to perform a specific application or function) or as a plug-in module on the application-specific hardware of the electronic device.

[0176] Note that in many of the examples provided herein, the interactions may be described with respect to two, three, four, or more electrical components. However, this is done for clarity and illustration purposes only. It should be understood that the system can be established in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in the drawings may be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure.

[0177] In some cases, by referring to only a limited number of electrical elements, one or more functions of a given flow set can be more easily described. It should be understood that the electrical circuits in the drawings and their teachings are readily extensible and can accommodate more components, as well as more complex / sophisticated arrangements and configurations. Thus, the examples provided are not intended to limit the scope or impede the broad teachings of electrical circuits when potentially applied to numerous other architectures.

[0178] Also, as described, some aspects can be embodied in one or more ways. The operations performed as part of a method may be ordered in any suitable manner. Thus, although illustrated in exemplary embodiments as sequential acts, embodiments can be constructed in which acts are performed in a different order than illustrated, including performing some operations simultaneously.

[0179] Interpretation of Terms All definitions defined and used in this specification are to be understood to govern over dictionary definitions, definitions in incorporated documents by reference, and / or the ordinary meaning of defined terms. Throughout this specification and the claims, unless the context clearly requires otherwise,

[0180] "Comprise", "comprising", etc. should be interpreted in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0181] "Connected", "coupled", or any variation thereof means any direct or indirect connection or coupling between two or more elements, and the coupling or connection between elements can be physical, logical, or a combination thereof.

[0182] As used to describe this specification, the terms "this specification", "above", "below", and words of similar meaning refer to the entire specification and not to any particular part of the specification.

[0183] "Or" as related to a list of two or more items encompasses all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

[0184] The singular forms "a", "an", and "the" also include any appropriate plural meanings.

[0185] The words indicating directions such as "vertical", "transverse", "horizontal", "upward", "downward", "forward", "backward", "inward", "outward", "vertical", "transverse", "left", "right", "front", "back", "top", "bottom", "below", "above", "under", etc. used in this specification depend on the specific directions of the devices described and illustrated. The subject matter described in this specification can assume various other directions. Therefore, these directional terms are not strictly defined and should not be construed narrowly.

[0186] The indefinite articles "a" and "an" used in this specification in the specification and claims should be understood to mean "at least one" unless expressly indicated to the contrary.

[0187] As used herein in the specification and claims, the phrase "and / or" is to be understood to mean "either or both" of the elements so conjoined, i.e., elements that may be present conjunctively in some cases and disjunctively in other cases. Multiple elements listed using "and / or" are to be construed in the same manner, i.e., "one or more" of the elements so conjoined.

[0188] Elements other than those specifically recited by the "and / or" clause may optionally be present, whether or not related to those specifically recited elements. Thus, by way of non-limiting example, a reference to "A and / or B", when used in combination with open-ended language such as "comprising", may in one embodiment refer to only A (optionally including elements other than B), in another embodiment refer to only B (optionally including elements other than A), and in yet another embodiment refer to both A and B (optionally including other elements).

[0189] As used in the specification and claims of this application, the phrase "at least one" in reference to a list of one or more elements is to be understood to mean at least one element selected from any one or more of the elements in the list of elements, and need not include at least one of each and every element specifically listed within the list of elements, nor does it exclude any combinations of elements in the list of elements. This definition also allows that elements other than those specifically identified within the list of elements referred to by the phrase "at least one" may optionally be present, whether or not related to those specifically identified elements.

[0190] Thus, by way of non-limiting example, “at least one of A and B” (or equivalently, “at least one of A or B”, or equivalently, “at least one of A and / or B”) may, in one embodiment, refer to at least one A, optionally including a plurality, in the absence of B (and optionally including elements other than B); in another embodiment, it may refer to at least one B, optionally including a plurality, in the absence of A (and optionally including elements other than A); in yet another embodiment, it may refer to at least one A, optionally including a plurality; or it may refer to at least one B, optionally including a plurality (and optionally including other elements), etc.

[0191] As used herein, the term “between” should be inclusive unless otherwise indicated. For example, “between A and B” includes A and B unless otherwise indicated.

[0192] Also, the syntax and terminology used herein are for illustrative purposes and should not be construed as limiting. The use of “including”, “comprising”, “having”, “containing”, “involving” and variations thereof herein is meant to encompass the listed items and their equivalents, as well as additional items.

[0193] In the claims and the above specification, all transitional phrases such as "comprising", "including", "carrying", "having", "containing", "involving", "holding", "composed of", etc. should be understood to be open-ended, i.e., meaning including but not limited to these. Only the transitional phrases "consisting of" and "consisting essentially of" are closed transitional phrases or semi-closed transitional phrases, respectively.

[0194] Numerous other changes, substitutions, variations, modifications and amendments may be ascertained by those skilled in the art, and the present disclosure is intended to embrace all such changes, substitutions, variations, modifications and amendments as being within the scope of the appended claims.

[0195] When the United States Patent and Trademark Office (USPTO), and additionally, any reader of any patent issued with respect to this application, interprets the claims appended hereto, Applicant desires that Applicant be considered not to intend to invoke 35 U.S.C. § 112(f) with respect to any of the appended claims unless the phrase "means for" or "step for" is specifically used in a particular claim, and that no description in the present disclosure is intended to limit the disclosure in any way not otherwise reflected in the appended claims.

[0196] Accordingly, the present invention should be considered not to be limited to the above specific embodiments. Many modification processes, equivalent processes, and structures to which the present invention may be applicable will readily become apparent to those skilled in the art to which the present invention pertains upon review of the present disclosure.

[0197] Exemplary Embodiments Example 1. A system for synchronous voice communication via a network bus and bus power, comprising a main node having a power source, a transceiver, and a field effect transistor, a sub-node, and an 8-pin connector between the main node and the bus node, wherein the main node and the sub-node communicate via the 8-pin connector, and the main node supplies power to the sub-node via the 8-pin connector.

[0198] Example 1A: The sub-node is a first sub-node, the network bus includes a plurality of daisy-chain connected nodes including the first sub-node, and the main node transmits power to at least a second sub-node among the daisy-chain connected nodes through the first sub-node, the system according to Example 1.

[0199] In some embodiments of both the network and the method, the data communication network includes a plurality of nodes 102. The nodes 102 include a main node (MN) 102-1 / 1502 and at least one sub-node 102-2 / 1504 (SN i =SN0,…SN X ). Each node 102 includes a node transceiver 120. The node transceiver 120 is operable to perform data communication according to a first network protocol for power over data via a pair of conductors (e.g., the conductors of bus 106). The physical layer includes cable segments (e.g., the cable segments of bus 106) between each node 120. Each cable segment includes a plurality of pairs of conductors (e.g., pair 1510) and connectors (e.g., 8P8C connector 1520, however, other connectors having a plurality of pairs of conductors may be used) at each end. A first pair of conductors 1510a (connected to pins 4 and 5 of, for example, 8P8C connector 1520) implements the first network protocol between nodes. One or more of the remaining pairs of conductors (e.g., 1510b, 1510c) provide auxiliary power to the node 102.

[0200] In some embodiments, the auxiliary power is parallel power across the remaining pairs (e.g., the pairs attached to pins 3 and 6 of 1510b, 1510c, and the 8P8C connector 1520). In some embodiments, the connector is an 8-position 8-contact (8P8C) connector 1520. In some such embodiments, pins 4 and 5 of each 8P8C connector 1520 correspond to the first pair 1510a. In some embodiments, the first network protocol is an in-vehicle audio bus (A2B).

[0201] In some embodiments, each SN102-2 further includes a memory (such as EEPROM1530). The memory communicates with the corresponding node transceiver 120 (e.g., AD2437 1540). The memory stores on the memory the configuration information of each SN102-2 that identifies at least one power characteristic of each SN102-2. In such embodiments, the network further includes an auxiliary power supply (e.g., VREG1 ADP2360 1550) and a host processor (e.g., MCU / DSP / USBi Host 1560). The host processor communicates with i) the auxiliary power supply (e.g., VREG1 ADP2360 1550), ii) MN102-1, and ii) one or more SN102-2s in series via MN 102-1 and the physical layer using a first network protocol. The host processor is operable to cooperate with MN102-1 and each given SN102-2 to progressively apply a first power downstream for each given SN102-2 (e.g., first SN0, then SN1, etc.) to a first pair (e.g., 1510a). The host processor then uses the applied first power to read the configuration information of the given SN102-2 from the memory (e.g., 1530) of the given SN102-2. The host processor then determines, based on the read configuration information, whether the given SN102-2 requires auxiliary power. If it is determined that the given SN102-2 requires auxiliary power, the host processor applies auxiliary power via the auxiliary power supply (e.g., VREG1 ADP2360 1550) and the remaining pair. In some embodiments, the host processor is separate from MN102-1. In some embodiments, the first protocol power and the auxiliary power are from a source integrated with the node transceiver 120, while in some embodiments, one or more of the first protocol power and any auxiliary power are from separate devices.

[0202] In some such examples, the host processor is further operable to detect whether a preferred power state exists for a first pair (e.g., 1510a) after applying a first power. The host processor can then discover a given SN102-2 via a first protocol before reading configuration information if it determines that a preferred power state exists for the first pair. In such an embodiment, reading the first configuration information is conditioned on discovering a given SN102-2.

[0203] In some embodiments, the steps of this multi-step process (detecting a preferred power state at the next sub-node, reading the characteristics of the next sub-node, and powering up the auxiliary power at the next sub-node) can be performed in other orders and combinations (including other combinations of power sources). Generally, an exemplary approach is for a first (and not an incompatible node) protocol node to confirm that there is a downstream multi-pair connector and then identify the characteristics (including power demand) of the downstream sub-node and provide those power demands using a combination of the first protocol power and complementary power.

Description of the Reference Numerals

[0204] 100 Communication system 102-1 Main node 102-2 Sub-node 106 Bus 108 Peripheral device 110 Host 120 Node transceiver 122 Upstream differential signal (DS) transceiver 124 Downstream DS transceiver 126 Bus protocol circuit 127 I2S / TDM / PDM transceiver 128 Phase-locked loop (PLL) 129 I2C transceiver 130 Voltage regulator circuit 131 Downstream bus interface circuit 132 Upstream bus interface circuit 136 SPI transceiver 138 External device 154 Control circuit 155 External device 156 Preamble circuit 157 External device 158 CRC insertion circuit 159 CRC check circuit 160 Compression circuit 162 Multiplexer (MUX) 164 Scramble circuit 166 Descramble circuit 168 Demultiplexer (DEMUX) 170 Restoration circuit 180 Synchronization control frame 182 Preamble 184 Control data 190 Superframe 192 Period 194 Period 196 Period 197 Synchronization response frame 198 Downstream data slot 199 Upstream data slot 1021 Main node 1022 Sub-node 1200 Arrangement 1202 Data 1204 Data 1300 Device 1302 Processing device 1304 Memory 1306 Display device 1308 Audio output device 1310 Output device 1312 Communication chip 1314 Power circuit 1318 GPS device 1320 Input device 1322 Antenna 1324 Audio input device 1400 Flowchart 1502 Main Node 1504 Bus Power Supply Sub-Node 1506 Connector 1510 Pair 1520 P8C Connector 1530 EEPROM 1806 Connector

Claims

1. A data communication network, A main node (MN) and at least one sub-node (SN ｉ = SN ０ , … SN Ｘ ) comprising a plurality of nodes, each node being operable to perform data communication according to a first network protocol for power via data via a pair of conductors, the plurality of nodes comprising node transceivers comprising a physical layer including cable segments between nodes, each cable segment including a plurality of pairs of conductors and connectors at each end, comprising, a first pair of said conductors implementing said first network protocol between said nodes, the remaining pairs of said conductors providing auxiliary power to said nodes, a data communication network.

2. The data communication network according to claim 1, wherein said auxiliary power is parallel power across said remaining pairs.

3. The data communication network according to claim 1, wherein said connector is an 8-position 8-contact (8P8C) connector.

4. The data communication network according to claim 3, wherein pins 4 and 5 of each 8P8C connector correspond to said first pair.

5. The data communication network according to claim 1, wherein said first network protocol is an in-vehicle audio bus (A2B).

6. each SN being a memory, communicating with the corresponding node transceiver, storing on the memory configuration information of each SN for identifying at least one power characteristic of the corresponding SN, further comprising, the data communication network an auxiliary power supply, a host processor, further comprising, the host processor i) communicating with said auxiliary power supply, ii) said MN, and iii) one or more SNs in series via said MN and said physical layer using said first network protocol, cooperating with said MN and each given SN to progressively downstream for each given SN, applying a first power to said first pair, using the applied first power to read said configuration information of said given SN from the memory of said given SN, determining based on the read configuration information whether said given SN requires auxiliary power, when it is determined that said given SN requires auxiliary power via said auxiliary power supply and said remaining pairs, applying, is operable to perform, the data communication network according to claim 1.

7. said host processor, after applying said first power, detecting whether a preferred power state exists in said first pair, when it is determined via said first network protocol that a preferred power state exists in said first pair, discovering said given SN before reading said configuration information, is further operable to perform, reading the first configuration information is conditional upon discovering the given SN, The data communication network according to claim 6.

8. A method for data communication network operation, A data communication network, A main node (MN) and at least one sub-node (SN ｉ = SN ０ , … SN Ｘ ), a plurality of nodes, each node being A node transceiver operable to perform data communication according to a first network protocol for power over data via a pair of conductors, A memory that communicates with the corresponding node transceiver and stores on the memory configuration information of the SN that identifies at least one power characteristic of the SN, including a plurality of nodes, A physical layer including cable segments between each node, each cable segment including a plurality of pairs of conductors and connectors at each end, the first pair of the plurality of pairs implementing the first network protocol between the nodes, and the remaining pairs providing auxiliary power to the nodes, An auxiliary power supply, A host processor that communicates with i) the auxiliary power supply, ii) the MN, and ii) one or more SNs in series via the MN and the physical layer using the first network protocol, In a data communication network comprising: In cooperation with the MN and each given SN, by the host processor, progressively downstream for each given SN, applying a first power to the first pair, using the applied first power to read the configuration information of the given SN from the memory of the given SN, determining whether the given SN requires auxiliary power based on the read configuration information, when it is determined that the given SN requires auxiliary power via the auxiliary power supply and the remaining pairs, applying, including a method.

9. The method being, after applying the first power, detecting whether a preferred power state exists in the first pair, when it is determined that a preferred power state exists in the first pair, discovering the given SN before reading the configuration information, further including, The data communication network according to claim 8, wherein reading the first configuration information is conditional upon discovering the given SN.

10. The data communication network according to claim8, wherein the auxiliary power is parallel power across the remaining pairs.

11. The data communication network according to claim 8, wherein the connector is an 8-position 8-contact (8P8C) connector.

12. The data communication network according to claim 11, wherein pins 4 and 5 of each 8P8C connector correspond to the first pair.

13. The data communication network according to claim 8, wherein the first network protocol is an in-vehicle audio bus (A2B).

Images