Battery management chip and system, and vehicle

Abstract

The vehicle includes a battery management chip and a battery management system. The battery management chip comprises a battery cell data sampling module, a data processing module, a first communication module, and a first power module. The battery cell data sampling module is used to acquire the battery cell data of the battery cell. The data processing module is connected to the battery cell data sampling module and is used to process the battery cell data. The first communication module is connected to the data processing module and is used to send the processed battery cell data to the control module. The first power module is connected to the battery cell and the data processing module, receives the initial voltage output by the battery cell, and is used to perform a boost process on the initial voltage to provide an operating voltage to the data processing module.

Description

Technical Field

[0001] Cross - reference to Related Applications This disclosure claims priority to Chinese Patent Application No. 202210756825.0, titled "BATTERY MANAGEMENT CHIP AND SYSTEM, AND VEHICLE", filed on June 30, 2022, which is hereby incorporated by reference in its entirety.

[0002] This disclosure relates to the field of vehicle technology, and more particularly, to battery management chips and systems, and vehicles.

Background Art

[0003] A battery management system (BMS) mainly acquires the voltage, current, temperature, dynamic internal resistance, and other data of a battery pack, and transmits the data using a conventional wiring harness communication mode to an upper - level control module, thereby realizing interactive control of data transmission.

[0004] Currently, a battery pack composed of multiple battery cells is monitored by a battery management chip. The high voltage of the battery pack poses a major challenge to the process and safety of the battery management chip. Secondly, the normal operation of the battery management chip requires a low voltage. To ensure the consistency of all the electrical quantities of the battery cells in the battery pack, it is necessary to obtain power from the total voltage and obtain the voltage that the chip can use after step-down processing, which increases the unnecessary energy loss of the battery cells. In addition, the battery management chip monitors multiple battery cells simultaneously, and there is a risk that the chip may malfunction during the long-term operation of the vehicle, resulting in the loss of cell data of multiple battery cells and an increase in the failure rate of the vehicle. Finally, although multiple battery cells are monitored by the management chip, the management chip will use a complex sampling wiring harness and connectors, which will simultaneously complicate the design of the sampling board of the battery management chip. On the one hand, it will lead to a sharp increase in cost, and on the other hand, the stability and reliability of the harness connectors will increase the failure rate of the vehicle. At the same time, the boost circuit of the electronic power technology cannot guarantee the normal operation of the chip under a wide range of low voltages. Summary of the Invention Problems to be Solved by the Invention

[0005] The present disclosure aims to solve at least to some extent one of the technical problems in the related art. Means for Solving the Problems

[0006] Accordingly, a first objective of the present disclosure is to propose a battery management chip, which arranges a first power module to boost the initial voltage output by a battery cell to provide an operating voltage for a data processing module, ensures that the battery management chip can operate at a wide range of low voltages, and monitors one battery cell via one battery management chip. The first aspect is that the battery management chip does not need to face the high voltage generated by a plurality of series-connected battery cells, avoids the battery cell operating under high voltage to avoid unnecessary energy loss, thereby reducing the process requirements of chip manufacturing and saving energy consumption. The second aspect is that the failure risk of the chip can be reduced, the data of a plurality of battery cells can be avoided from being lost at one time, and the failure rate of the vehicle can be reduced. The third aspect is that the flexibility of the battery management chip can be improved, the use of a large number of wiring harnesses and connectors can be reduced, the complexity of the battery management chip can be reduced, and the stability and reliability of the battery management chip can be improved.

[0007] Accordingly, a second objective of the present disclosure is to propose a battery management system.

[0008] Accordingly, a third objective of the present disclosure is to propose a vehicle.

[0009] To achieve the above objectives, an embodiment of the first aspect of the present disclosure proposes a battery management chip connected corresponding to a single battery cell. The battery management chip includes a battery cell data sampling module for acquiring battery cell data of the battery cell, a data processing module connected to the battery cell data sampling module and used for processing the battery cell data, a first communication module connected to the data processing module and used for transmitting the processed battery cell data to a control module, and a first power module connected to the battery cell and the data processing module, receiving the initial voltage output by the battery cell, and performing a boosting process on the initial voltage to provide an operating voltage for the data processing module.

[0010] According to one embodiment of the present disclosure, a battery management chip boosts an initial voltage output by a battery cell via a first power module, provides an operating voltage to a data processing module, ensures that the battery management chip can operate at a wide range of low voltages, and monitors one battery cell via one battery management chip. The first aspect is that the battery management chip does not need to face the high voltage generated by a plurality of series-connected battery cells, avoids the battery cells operating under high voltage to avoid unnecessary energy loss, thereby reducing the process requirements of chip manufacturing and saving energy consumption. The second aspect is that the failure risk of the chip can be reduced, the data of a plurality of battery cells can be avoided from being lost at one time, and the failure rate of the vehicle can be reduced. The third aspect is that the flexibility of the battery management chip can be improved, the use of a large number of wiring harnesses and connectors can be reduced, the complexity of the battery management chip can be reduced, and the stability and reliability of the battery management chip can be improved.

[0011] In some embodiments, the first power module includes a boost circuit unit that is connected to the battery cell and is used to perform a boost process on the initial voltage output by the battery cell to output an initial target voltage.

[0012] In some embodiments, the first power module further includes an input filtering voltage stabilization circuit unit. The input terminal of the input filtering voltage stabilization circuit unit is connected to the voltage output terminal of the battery cell and is used to reduce the voltage ripple interference of the initial voltage output by the battery cell and output a DC voltage.

[0013] In some embodiments, the first power module further includes an output filtering voltage stabilization circuit unit. The output filtering voltage stabilization circuit unit is connected to the boost circuit unit, performs filtering and voltage stabilization processing on the initial target voltage to obtain a target voltage, outputs the target voltage, and is used to provide an operating voltage to the data processing module.

[0014] In some embodiments, the first power module further includes a sampling feedback unit, which is connected to the output filtering voltage stabilization circuit unit and the boost circuit unit respectively, and is used to obtain the voltage value of the target voltage and feedback the voltage value of the target voltage to the boost circuit unit.

[0015] In some embodiments, the boost circuit unit is further configured to receive the voltage value of the target voltage and adjust the boost action based on the voltage value of the target voltage. As a result, the initial target voltage of the adjusted output is filtered and stabilized by the output filtering voltage stabilization circuit unit (132) to output a target voltage within a preset voltage range.

[0016] In some embodiments, the boost circuit unit is a PWM generation circuit subunit. The first terminal of the PWM generation circuit subunit is connected to the output terminal of the input filtering voltage stabilization circuit unit, the second terminal of the PWM generation circuit subunit is grounded, and the third terminal of the PWM generation circuit subunit is used to output a PWM (pulse width modulation technology) signal. The boost circuit unit further includes a charge pump boost subunit. The first terminal of the charge pump boost subunit is connected to the third terminal of the PWM generation circuit subunit and is used to adjust the frequency and duty cycle of the PWM signal in real time until the initial target voltage is obtained.

[0017] In some embodiments, the PWM generation circuit subunit includes an energy storage subunit, where one terminal of the energy storage subunit is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the other terminal of the energy storage subunit is grounded; a waveform generation subunit, where the first terminal of the waveform generation subunit is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the second terminal of the waveform generation subunit is grounded; a voltage follower circuit, where the first terminal of the voltage follower circuit is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the third terminal is grounded; a first comparator, where the non-inverting input terminal of the first comparator is connected to the first terminal of the waveform generation subunit; a second comparator, where the non-inverting input terminal of the second comparator is connected to the third terminal of the voltage follower circuit, the inverting input terminal of the second comparator is connected to the inverting input terminal of the first comparator, and the output terminal of the second comparator is connected to the first terminal of the charge pump boost subunit; a charge and discharge capacitor, where one terminal of the charge and discharge capacitor is connected to the inverting input terminals of the first comparator and the second comparator, and the other terminal of the charge and discharge capacitor is grounded; and a duty cycle adjustment resistor, where one terminal of the duty cycle adjustment resistor is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the other terminal of the duty cycle adjustment resistor is connected to the second terminal of the voltage follower circuit.

[0018] In some embodiments, the waveform generation sub-unit is a voltage adjustment sub-unit, where the first terminal of the voltage adjustment sub-unit is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the second terminal of the voltage adjustment sub-unit is grounded; and a charge and discharge sub-unit, where one terminal of the charge and discharge sub-unit is connected to the output terminal of the first comparator, and the other terminal of the charge and discharge sub-unit is connected to one terminal of the charge and discharge capacitor.

[0019] In some embodiments, the voltage adjustment sub-unit includes a first resistor, where one terminal of the first resistor is connected to the output terminal of the input filtering voltage stabilization circuit unit; a second resistor, where one terminal of the second resistor is connected to the output terminal of the input filtering voltage stabilization circuit unit; a third resistor, where one terminal of the third resistor is connected to the other terminal of the first resistor, and the other terminal of the third resistor is connected to the other terminal of the second resistor; and a fourth resistor, where one terminal of the fourth resistor is connected to the positive-phase input terminal of the first comparator, and the other terminal of the fourth resistor is grounded.

[0020] In some embodiments, the charge and discharge sub-unit includes a fifth resistor.

[0021] In some embodiments, the voltage follower circuit includes a voltage division sub-unit, where one terminal of the voltage division sub-unit is connected to the other terminal of the duty cycle adjustment resistor, and the other terminal of the voltage division sub-unit is grounded; and a voltage difference output unit, where the first terminal of the voltage difference output unit is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the second terminal of the voltage difference output unit is connected to one terminal of the voltage division sub-unit.

[0022] In some embodiments, the voltage difference output unit includes a seventh resistor, one terminal of the seventh resistor being connected to one terminal of the duty cycle adjustment resistor; a triode, the base electrode of the triode being connected to the other terminal of the duty cycle adjustment resistor, and the collector electrode of the triode being connected to the other terminal of the seventh resistor; and a voltage stabilizing energy storage capacitor, one terminal of the voltage stabilizing energy storage capacitor being connected to the emitter electrode of the triode, and the other terminal of the voltage stabilizing energy storage capacitor being grounded.

[0023] In some embodiments, the charge pump boost sub-unit includes a filtering voltage stabilizing capacitor, one terminal of the filtering voltage stabilizing capacitor being connected to the output terminal of the input filtering voltage stabilizing circuit unit, and the other terminal of the filtering voltage stabilizing capacitor being grounded; a feedback adjustment sub-unit, the first terminal of the feedback adjustment sub-unit being connected to one terminal of the filtering voltage stabilizing capacitor, and the second terminal of the feedback adjustment sub-unit being grounded; a charge and discharge control sub-unit, the first terminal of the charge and discharge control sub-unit being connected to one terminal of the filtering voltage stabilizing capacitor, and the second terminal of the charge and discharge control sub-unit being connected to the output terminal of the second comparator; and an energy storage capacitor, one terminal of the energy storage capacitor being connected to the third terminal of the charge and discharge control sub-unit, the other terminal of the energy storage capacitor being grounded, and the energy storage capacitor being used for charging when the second switching transistor and the fourth switching transistor are switched on.

[0024] In some embodiments, the charge and discharge control sub-unit includes a first switching transistor, where the gate electrode of the first switching transistor is connected to the output terminal of a second comparator; an inverter, where the input terminal of the inverter is connected to the output terminal of the second comparator; a second switch transistor, where the gate electrode of the second switch transistor is connected to the output terminal of the inverter; a third switch transistor, where the drain electrode of the third switch transistor is connected to the source electrode of the second switch transistor and the gate electrode of the third switch transistor is connected to the gate electrode of the first switch transistor; a fourth switch transistor, where the source electrode of the fourth switch transistor is connected to the source electrode of the third switch transistor and the gate of the fourth switch transistor is connected to the output terminal of the inverter; and a pump capacitor, where one terminal of the pump capacitor is connected to the drain electrode of the second switch transistor, the other terminal of the pump capacitor is connected to the source electrode of the fourth switch transistor, and the pump capacitor is used for charging when the first switch transistor and the third switch transistor are switched on.

[0025] In some embodiments, the feedback adjustment subunit includes a tuning resistor, where the first terminal of the tuning resistor is connected to the output terminal of the input filtering voltage stabilization circuit unit, and the second terminal of the tuning resistor is connected to the first terminal of the charge and discharge control subunit; a first feedback resistor, where one terminal of the first feedback resistor is connected to one terminal of the energy storage capacitor; a second feedback resistor, where one terminal of the second feedback resistor is connected to the other terminal of the first feedback resistor, and the other terminal of the second feedback resistor is grounded; an eighth resistor, where one terminal of the eighth resistor is connected to one terminal of the first feedback resistor, and the other terminal of the eighth resistor is connected to the other terminal of the second feedback resistor; a feedback comparator, where the inverting input terminal of the feedback comparator is connected to the other terminal of the first feedback resistor, and the non-inverting input terminal of the feedback comparator is connected to the output terminal of the sampling feedback unit; and a logic subunit, where the input terminal of the logic subunit is connected to the output terminal of the feedback comparator, and the output terminal of the logic subunit is connected to the adjustment terminal of the tuning resistor.

[0026] In some embodiments, the first communication module includes a first wireless communication unit.

[0027] In some embodiments, the first power module is connected to the first wireless communication unit and is used to supply power to the first wireless communication unit.

[0028] In some embodiments, the data processing module includes a multiplexing switch module connected to the battery cell data sampling module and configured to select battery cell data, a conversion module connected to the multiplexing switch module and configured to perform analog / digital conversion or digital / analog conversion on the selected battery cell data to obtain digital information and / or analog information of the battery cell data, a filtering module connected to the conversion module and configured to remove interference information in the digital information and / or analog information, and an arithmetic and storage module connected to the filtering module and configured to perform arithmetic and storage of the filtered digital information and / or analog signal.

[0029] In some embodiments, the battery cell data sampling module includes at least one of a voltage sampling module configured to obtain voltage data of the battery cell, a current sampling module configured to obtain power data of the battery cell, a temperature acquisition module configured to obtain temperature data of the battery cell, and a resistance sampling module configured to obtain resistance data of the battery cell.

[0030] In some embodiments, the battery management chip further includes an equalization module connected to the battery cell and configured to perform consistency processing on the voltage of the battery cell so that the difference between the voltage of the battery cell and the minimum voltage of the remaining battery cells is within a preset voltage range.

[0031] In some embodiments, the temperature acquisition module includes a temperature sensor integrally disposed within the temperature acquisition module.

[0032] To achieve the above object, an embodiment of the second aspect of the present disclosure proposes a battery management system. The battery management system includes at least one battery management chip described in the above embodiment, at least one battery cell connected to at least one of the battery management chips in a one-to-one correspondence, and a control module that communicates with the battery management chip.

[0033] In some embodiments, the control module includes a second communication module that communicates with the first communication module of the battery management chip, and a micro control unit that receives battery cell data transmitted by the battery management chip via the second communication module so that the battery management chip can control the battery cell connected to the battery management chip, and transmits a control signal to the battery management chip via the second communication module. The control module further includes a second power supply module connected to the micro control unit and configured to supply power to the micro control unit.

[0034] In some embodiments, the second communication module includes a second wireless communication unit, and the second power module is connected to the second wireless communication unit and is used to supply power to the second wireless communication unit.

[0035] To achieve the above object, an embodiment of the third aspect of the present disclosure provides a vehicle including the battery management system described in the above embodiment.

[0036] Additional aspects and advantages of the present disclosure are provided in part in the following description, some of which will be apparent from the following description or can be learned from the practice of the present disclosure.

[0037] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the description of the embodiments used in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

DETAILED DESCRIPTION OF THE INVENTION

[0039] Embodiments of the present disclosure are described in detail below, and the embodiments described with reference to the accompanying drawings are examples.

[0040] The battery management chip acquires voltage data, current data, temperature data, and resistance data of battery cells, and transmits the data to a control module. As a result, the control module can analyze and process the data to realize the operation of the battery cells.

[0041] Hereinafter, with reference to FIGS. 1 to 4, a battery management chip according to an embodiment of the present disclosure will be described as an example.

[0042] As shown in FIG. 1, a battery management chip 1 according to an embodiment of the present disclosure includes a battery cell data sampling module 10, a data processing module 11, a first communication module 12, and a first power module 13.

[0043] The battery cell data sampling module 10 is configured to acquire battery cell data of a battery cell (BC). The data processing module 11 is connected to the battery cell data sampling module 10 and is used to process the battery cell data. The first communication module 12 is connected to the data processing module 11 and is used to transmit the processed battery cell data to the control module. The first power module 13 is connected to the battery cell and the data processing module 11, receives the initial voltage output by the battery cell, and is used to perform a boost process on the initial voltage to provide an operating voltage to the data processing module 11. It can be understood that the battery management chip 1 is connected corresponding to a single battery cell, avoiding the battery cell from operating under high voltage, thereby avoiding the problem that the battery cell needs to be bucked to supply power to the battery management chip 1 and reducing unnecessary energy loss. Furthermore, the battery management chip is connected to a single battery cell to detect the single battery cell, thereby greatly reducing the risk of the battery management chip failing during long-term operation of the vehicle and reducing the failure rate of the vehicle. Finally, since the battery management chip is connected to a single battery cell, the use of wiring harnesses and connectors can be greatly reduced, the complexity of chip design can be reduced, and the design becomes more flexible.

[0044] In one embodiment, when the battery management chip 1 receives a valid operation command such as a voltage acquisition command, the battery cell data sampling module 10 of the battery cell acquires the battery cell data of the battery cell according to the received corresponding operation command. Since the initial voltage of the battery cell is a wide-range low voltage signal, for example, the initial voltage of the battery cell is between 2.5V and 5.5V, the normal operation of the battery management chip 1 cannot be guaranteed. At this point, in order to provide an operating voltage for the normal operation of the data processing module 11, the initial voltage of the battery cell is boosted by the first power module 13. For example, the operating voltage after the boosting process is between 3.3V and 5V. As a result, after receiving the battery cell data transmitted by the battery cell data sampling module 10, the data processing module 11 processes the battery cell data and transmits the processed battery cell data to the control module via the first communication module 12. The control module analyzes and processes the received battery cell data and issues a corresponding operation command to the battery cell. By setting the first power module 13, the initial voltage output from the battery cell is boosted to provide an operating voltage for the data processing module 11. As a result, the battery management chip 1 can operate normally under a wide range of low voltages.

[0045] According to an embodiment of the present disclosure, a battery management chip boosts the initial voltage output by a battery cell through a first power module, provides an operating voltage to a data processing module, ensures that the battery management chip can operate at a wide range of low voltages, and monitors one battery cell through one battery management chip. The first aspect is that the battery management chip does not need to face the high voltage generated by a plurality of series-connected battery cells, avoids the battery cells operating under high voltage to avoid unnecessary energy loss, thereby reducing the process requirements of chip manufacturing and saving energy consumption. The second aspect is that the failure risk of the chip can be reduced, the data of a plurality of battery cells can be avoided from being lost at one time, and the failure rate of the vehicle is reduced. The third aspect is that the flexibility of the battery management chip can be improved, the use of a large number of wiring harnesses and connectors can be reduced, the complexity of the battery management chip can be reduced, and the stability and reliability of the battery management chip can be improved.

[0046] For example, FIG. 2 shows a block diagram of a first power module 13 according to an embodiment of the present disclosure. The first power module 13 includes an input filtering voltage stabilization circuit unit 130, a boost circuit unit 131, and an output filtering voltage stabilization circuit unit 132. The input terminal of the input filtering voltage stabilization circuit unit 130 is connected to the voltage output terminal of the battery cell, reduces the voltage ripple interference of the initial voltage output by the battery cell, and is used to output a DC voltage. The boost circuit unit 131 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130 and is used to boost the DC voltage to obtain an initial target voltage. The output filtering voltage stabilization circuit unit 132 is connected to the boost circuit unit 131, filters and stabilizes the initial target voltage to obtain a target voltage, outputs the target voltage, and is used to provide an operating voltage to the data processing module 11.

[0047] In an embodiment, the initial voltage is provided by a single battery cell. After the single battery cell outputs the initial voltage, the input filtering voltage stabilization circuit unit 130 receives the initial voltage, reduces the voltage ripple interference of the initial voltage to obtain a relatively stable DC voltage, and outputs the DC voltage. The output DC voltage is boosted by the boost circuit unit 131 to obtain the initial target voltage, and the initial target voltage is transmitted to the output filtering voltage stabilization circuit unit 132. The output filtering voltage stabilization circuit unit 132 performs filtering and stabilization on the received initial target voltage to obtain the target voltage, outputs the target voltage to the data processing module 11, and provides the operating voltage to the data processing module 11. It can be understood that the initial voltage is a wide range of low voltages, and in order to obtain the initial target voltage, the DC voltage, which is the initial voltage with the voltage ripple interference removed, is processed by the boost circuit unit 131. The initial target voltage provides the operating voltage for the normal operation of the battery management chip 1. The initial target voltage is stabilized and filtered to obtain a relatively stable initial target voltage, and the relatively stable initial target voltage is adopted as the target voltage. The initial voltage output from the battery cell is boosted by the boost circuit unit 131 to provide the operating voltage to the data processing module 11, ensuring that the battery management chip can operate at a wide range of low voltages.

[0048] In some embodiments, as shown in FIG. 2, the boost circuit unit 131 is integrally arranged in the first power module 13. By integrating the boost circuit unit 131 into the first power module 13, it is possible to save the layout space and reduce the cost compared with the case of using devices that cannot be integrated, such as inductors and transformers.

[0049] In some embodiments, as shown in FIG. 2, the first power module 13 further includes a sampling feedback unit 133. The sampling feedback unit 133 is connected to the output filtering voltage stabilization circuit unit 132 and the boost circuit unit 131 respectively, and is used to obtain the voltage value of the target voltage and feedback the voltage value of the target voltage to the boost circuit unit 131. The boost circuit unit 131 is further used to receive the voltage value of the target voltage and adjust the boost operation of the DC voltage based on the voltage value of the target voltage. As a result, the initial target voltage output after adjustment is filtered and stabilized by the output filtering stabilization circuit unit 132, and the output target voltage is within a preset voltage range.

[0050] In one embodiment, the preset voltage range is a voltage range that guarantees the normal operation of the battery management chip 1, for example, 3.3V to 5V. Considering that the current consumption of the battery management chip 1 varies depending on the operation mode and the target voltage changes greatly, after the output filtering voltage stabilization circuit unit 132 outputs the target voltage, at this time, the sampling feedback unit 133 detects the initial target voltage, and the boost operation of the boost circuit unit 131 is adjusted in real time based on the voltage value of the target voltage to ensure that the output target voltage is within the preset voltage range. In other words, it is guaranteed that the output target voltage does not change greatly due to the change of the operation mode.

[0051] In some embodiments, FIG. 3 shows a schematic diagram of the circuit structure of the boost circuit unit 131 according to an embodiment of the present disclosure. The boost circuit unit 131 includes a PWM generation circuit subunit 134, where the first terminal of the PWM generation circuit subunit 134 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, the second terminal of the PWM generation circuit subunit 134 is grounded, and the third terminal of the PWM generation circuit subunit 134 is used to output a PWM signal, and a charge pump boost subunit 135, where the first terminal of the charge pump boost subunit 135 is connected to the third terminal of the PWM generation circuit subunit 134 and is used to adjust the frequency and duty cycle of the PWM signal in real time until an initial target voltage is obtained. Among them, the charge pump boost subunit 135 adopts the principle of charge pump circuit boosting and operates by charge transfer. The pump capacitor can transfer charges from the input terminal to the output terminal to provide the current required by the load, adopts a capacitor for storing energy, has no EMI interference, little noise, low cost, small quiescent current, small output voltage ripple, and can provide high-current operation through feedback adjustment.

[0052] In one embodiment, the front stage of the boost circuit unit 131 is the PWM generation circuit subunit 134, and the rear stage is the charge pump boost subunit 135. The charge pump boost subunit 135 controls the frequency and duty cycle of the PWM signal. The boost circuit unit 131 continuously boosts the DC voltage through the PWM generation circuit subunit 134 and the charge pump boost subunit 135 until an initial target voltage is obtained.

[0053] In some embodiments, as shown in FIG. 3, the PWM generation circuit subunit 134 includes an energy storage subunit C1, a waveform generation subunit 136, a voltage follower circuit 137, a first comparator Q1, a second comparator Q2, a charge and discharge capacitor C2, and a duty cycle adjustment resistor RE1. Among these, one terminal of the energy storage subunit C1 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the other terminal of the energy storage subunit C1 is grounded. The first terminal of the waveform generation subunit 136 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the second terminal of the waveform generation subunit 136 is grounded. The first terminal of the voltage follower circuit 137 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the third terminal of the voltage follower circuit 137 is grounded. The positive phase input terminal of the first comparator Q1 is connected to the first terminal of the waveform generation subunit 136. The positive phase input terminal of the second comparator Q2 is connected to the third terminal of the voltage follower circuit 137, the inverting input terminal of the second comparator Q2 is connected to the inverting input terminal of the first comparator Q1, and the output terminal of the second comparator Q2 is connected to the first terminal of the charge pump boost subunit 135. One terminal of the charge and discharge capacitor C2 is connected to the inverting input terminals of the first comparator Q1 and the second comparator Q2, and the other terminal of the charge and discharge capacitor C2 is grounded. One terminal of the duty cycle adjustment resistor RE1 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130, and the other terminal of the duty cycle adjustment resistor RE1 is connected to the second terminal of the voltage follower circuit 137.

[0054] In an embodiment, the charge and discharge capacitor C2 and the first comparator Q1 within the PWM generation circuit subunit 134 output a sawtooth wave, and the duty cycle adjustment resistor RE1 is adjusted to output a PWM signal for use in a subsequent circuit via the voltage follower circuit 137 and the second comparator Q2.

[0055] For example, as shown in FIG. 3, the waveform generation subunit 136 includes a voltage adjustment subunit and a charge / discharge subunit. The voltage adjustment subunit includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The charge / discharge subunit includes a fifth resistor R5. One terminal of the first resistor R1 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130. One terminal of the second resistor R2 is connected to the output terminal of the input filtering voltage stabilization circuit unit 130. One terminal of the third resistor R3 is connected to the other terminal of the first resistor R1, and the other terminal of the third resistor R3 is connected to the other terminal of the second resistor R2. One terminal of the fourth resistor R4 is connected to the positive-phase input terminal of the first comparator Q1, and the other terminal of the fourth resistor R4 is grounded. One terminal of the fifth resistor R5 is connected to the output terminal of the first comparator Q1, and the other terminal of the fifth resistor R5 is connected to one terminal of the charge / discharge capacitor C2.

[0056] It is understood that the PWM generation circuit subunit 134 can be divided into three stages when outputting a PWM pulse waveform. In the first stage, the voltage at the inverting input terminal of the first comparator Q1 is 0, and the voltage at the non-inverting input terminal is R4*VBAT / (R4+((R2+R3) / / R1)). At this point, the first comparator Q1 outputs a high level, charges the charge-discharge capacitor C2 through the fifth resistor R5. In the second stage, when the charging voltage of the charge-discharge capacitor C2 reaches the voltage of the non-inverting input terminal of the first comparator Q1, that is, reaches R4*VBAT / (R4+((R2+R3) / / R1)), the first comparator Q1 outputs a low level, and the voltage at the non-inverting input terminal of the first comparator Q1 is (R3 / / R4)*VBAT / ((R3 / / R4)+R1), and the charge-discharge capacitor C2 is discharged through the fifth resistor R5. In the third stage, when the voltage discharged by the charge-discharge capacitor C2 to the non-inverting input terminal of the first comparator Q1 is lower than (R3 / / R4)*VBAT / ((R3 / / R4)+R1), the first comparator Q1 outputs a high level and returns to the first stage again, thereby realizing the output PWM pulse waveform.

[0057] FIG. 4 is a schematic diagram of the voltage waveform of the charge-discharge capacitor C2 according to an embodiment of the present disclosure. As can be seen from FIG. 4, the waveform in the charge-discharge capacitor C2 varies depending on the stage.

[0058] In some embodiments, as shown in FIG. 3, the voltage follower circuit 137 includes a voltage division subunit and a voltage difference output subunit. One terminal of the voltage division subunit is connected to the other terminal of the duty cycle adjustment resistor RE1, and the other terminal of the voltage division subunit is grounded. Specifically, the voltage division subunit includes a sixth resistor, and the voltage difference output subunit includes a triode Q3, a seventh resistor R7, and a voltage stabilizing energy storage capacitor C3. One terminal of the seventh resistor R7 is connected to one terminal of the duty adjustment resistor RE1. The base electrode of the triode Q3 is connected to the other terminal of the duty adjustment resistor RE1, and the collector electrode of the triode Q3 is connected to the other terminal of the seventh resistor R7. One terminal of the voltage stabilizing energy storage capacitor C3 is connected to the emitter electrode of the triode Q3, and the other terminal of the voltage stabilizing energy storage capacitor C3 is grounded.

[0059] In an embodiment, the duty cycle adjustment resistor RE1 is an adjustable resistor, and the duty cycle adjustment resistor RE1 and the sixth resistor R6 are connected in series to realize the voltage adjustment of the base electrode of the triode Q3. According to the change of the voltage of the base electrode of the triode Q3, the voltage of the voltage stabilizing energy storage capacitor C3 changes. The voltage of the positive phase input terminal in the second comparator Q2 is R6*VBAT / (R6+RE1 - 0.7V). Among them, the seventh resistor R7 provides the load capacitance of the triode Q3. It is understood that the load capacitance is the magnitude of the output resistance in the circuit.

[0060] FIG. 5 is a schematic diagram of a pulse waveform output by the second comparator Q2 according to an embodiment of the present disclosure. As can be seen from FIG. 5, the second comparator Q2 outputs a PWM waveform, and the duty cycle of the PWM waveform is adjusted by adjusting the duty cycle adjustment resistor RE1.

[0061] In some embodiments, as shown in FIG. 3, the charge pump boost sub-unit includes a filtering voltage stabilizing capacitor C4, a feedback adjustment sub-unit, a charge and discharge control sub-unit, and an energy storage capacitor C5. One terminal of the filtering voltage stabilizing capacitor C4 is connected to the output terminal of the input filtering voltage stabilizing circuit unit 130, and the other terminal of the filtering voltage stabilizing capacitor C4 is grounded. The first terminal of the feedback adjustment sub-unit is connected to one terminal of the filtering voltage stabilizing capacitor C4, and the second terminal of the feedback adjustment sub-unit is grounded. The first terminal of the charge and discharge control sub-unit is connected to one terminal of the filtering voltage stabilizing capacitor C4, and the second terminal of the charge and discharge control sub-unit is connected to the output terminal of the second comparator Q2. One terminal of the energy storage capacitor C5 is connected to the third terminal of the charge and discharge control sub-unit, the other terminal of the energy storage capacitor C5 is grounded, and the energy storage capacitor C5 is used for charging when the second switch transistor Q5 and the fourth switch transistor Q7 are switched on.

[0062] Among these, the charge and discharge control subunit includes a first switch transistor Q4, an inverter 138, a second switch transistor Q5, a third switch transistor Q6, a fourth switch transistor Q7, and a pump capacitor CE1. The feedback adjustment subunit includes a tuning resistor RON, a first feedback resistor Rf1, a second feedback resistor Rf2, a feedback comparator Q3', an eighth resistor Rload, and a logic subunit 139. Specifically, the gate electrode of the first switch transistor Q4 is connected to the output terminal of the second comparator Q2, the input terminal of the inverter 138 is connected to the output terminal of the second comparator Q2, the gate electrode of the second switch transistor Q5 is connected to the output terminal of the inverter 138, the drain electrode of the third switch transistor Q6 is connected to the source electrode of the second switch transistor Q5, and the gate electrode of the third switch transistor Q6 is connected to the gate of the first switch transistor Q4. The source electrode of the fourth switch transistor Q7 is connected to the source electrode of the third switch transistor Q6, the gate electrode of the fourth switch transistor Q7 is connected to the output terminal of the inverter 138, one terminal of the pump capacitor is connected to the drain electrode of the second switch transistor Q5, the other terminal of the pump capacitor CE1 is connected to the source of the fourth switch transistor Q7, and the pump capacitor is used for charging when the first switch transistor Q4 and the third switch transistor Q6 are switched on.The first terminal of the adjustable resistor RON is connected to the output terminal of the input filtering voltage stabilization circuit unit 130. The second terminal of the adjustable resistor RON is connected to the first terminal of the charge and discharge control subunit. One terminal of the first feedback resistor Rf1 is connected to one terminal of the energy storage capacitor C5. One terminal of the second feedback resistor Rf2 is connected to the other terminal of the first feedback resistor Rf1. The other terminal of the second feedback resistor Rf2 is grounded. One terminal of the eighth resistor Rload is connected to one terminal of the first feedback resistor. The other terminal of the eighth resistor Rload is connected to the other terminal of the second feedback resistor Rf2. The inverting input terminal of the feedback comparator Q3’ is connected to the other terminal of the first feedback resistor Rf1. The non-inverting input terminal of the feedback comparator Q3’ is connected to the output terminal of the sampling feedback unit 133. The input terminal of the logic subunit 139 is connected to the output terminal of the feedback comparator Q3’. The output terminal of the logic subunit 139 is connected to the adjustment terminal of the tuning resistor RON.

[0063] The PWM wave outputs the PWM1 waveform via the inverter 138 and outputs the PWM2 waveform on another path that does not pass through the inverter 138. It should be understood that the waveform passing through the inverter 138 is opposite to the waveform not passing through the inverter 138.

[0064] In the embodiment, after the operation of the boost circuit unit 131, in the first half cycle, PWM2 is low, the PWM generation circuit sub-unit 134 is low, and the first switch transistor Q4 and the third switch transistor Q6 are controlled to be switched on to charge the pump capacitor CE1. At this point, the PWM signal is PWM1 output via the inverter 138 to high, and the second switch transistor Q5 and the fourth switch transistor Q7 are controlled to be closed. In the second half cycle, the second switch transistor Q5 and the fourth switch transistor Q7 are switched on, the first switch transistor Q4 and the third switch transistor Q6 are closed, the third capacitor C5 is charged by the pump capacitor CE1, the current required by the load is supplied, and by controlling the PWM frequency and the duty cycle, the voltage is continuously boosted to the voltage and current required by the battery management chip. To further control the output, the charging current to the pump capacitor CE1 is controlled by the output feedback adjustment circuit.

[0065] Among them, the third switch transistor Q6 is closed, and the pump capacitor CE1 charges the energy storage capacitor C5 to provide the required amount of electricity to the load. The energy storage capacitor C5 is the energy storage capacitor of the charge pump boost subunit and provides current to the eighth resistor Rload. The feedback comparator Q3' is the feedback regulated voltage output after boosting and is realized by the series voltage division of the high-precision first feedback resistor Rf1 and the second feedback resistor Rf2. The voltage at the inverting input terminal of the feedback comparator Q3' is Rf2*Vout / (Rf1 + Rf2). When the voltage at the inverting input terminal of the feedback comparator Q3' is lower than the voltage at the output terminal of the sampling feedback unit 133, the feedback comparator Q3' sends a signal indicating that the output voltage is too low to the logic subunit 139. The logic subunit 139 adjusts the tuning resistor RON after the determination process and controls the charge pump boost subunit to boost the voltage to reach the target voltage.

[0066] When the voltage at the inverting input terminal of the feedback comparator Q3' is higher than the voltage at the output terminal of the sampling feedback unit 133, the feedback comparator Q3' sends a signal indicating that the output voltage is too high to the logic subunit 139. The logic subunit 139 adjusts the tuning resistor RON after the judgment process and controls the charge pump boost subunit to step down the voltage to reach the target voltage.

[0067] Currently, the communication modes adopted by general battery management chips mainly are twisted pair daisy chain cables. For this wired communication mode using twisted pair daisy chain cables, in order to ensure the reliability and stability of vehicle communication in a complex interference environment, it is necessary to add insulation devices and electromagnetic compatibility protection devices to the communication terminals. Second, when the twisted pair daisy chain cable wired communication mode synchronously monitors battery cell information, due to the requirements of serial transmission mode and bidirectional transmission, data reception is delayed, and the demand for timing processing in synchronous monitoring increases. Finally, the wired communication method requires wiring harnesses and connectors, which also pose great challenges to the reliability, stability, and cost of wiring harness connectors.

[0068] Therefore, as shown in FIG. 1, the first communication module 12 of the embodiment of the present disclosure adopts a first wireless communication unit, and the wireless communication transmission of the battery management chip 1 is realized by using the first wireless communication unit. First, this wireless communication transmission reduces the insulation devices and protection devices required for the coupled interference of wired communication harness noise, thereby improving communication quality, ensuring accurate transmission and interaction of data, reducing the complexity of the sampling board, and enabling more flexible application. Second, the communication mode of the first wireless communication unit is adopted. Compared with the wired communication mode using twisted pair daisy chain cables, the wireless communication mode makes the interaction of information more flexible and convenient, realizes natural time synchronization measurement, and supports more synchronization induction functions. Furthermore, it can avoid the problem of battery information loss caused by wiring harnesses and improve the safety of the entire vehicle. Finally, by reducing complex wiring harnesses and connectors, the weight and complexity of the entire vehicle can be reduced, the design flexibility can be improved, and maintenance can be made simpler and more convenient.

[0069] In some embodiments, as shown in FIG. 1, the first power module 13 is connected to the first wireless communication unit and is used to supply power to the first wireless communication unit. The first power module 13 supplies power to the first wireless communication unit to ensure normal communication of the first wireless communication unit.

[0070] In some embodiments, the first wireless communication unit includes at least one of Bluetooth, RFID (Radio Frequency Identification) unit, electromagnetic wave wireless communication unit, and SparkLink communication unit. In other words, the first wireless communication unit can implement wireless communication by at least one of Bluetooth communication method, RFID communication method, electromagnetic wave communication method, and SparkLink communication method, but is not limited thereto. It is understood that the SparkLink communication method uses SparkLink technology for wireless communication. SparkLink technology is a short-distance communication technology that can be used to realize wireless interconnection for implementing data interaction and transmission in vehicle application scenarios. SparkLink technology has the advantages of ultra-low latency, ultra-high reliability, and accurate synchronization.

[0071] In some embodiments, as shown in conjunction with FIGS. 1 and 6, the data processing module 11 includes a multiplexing switch module 110, a conversion module 111, a filtering module 112, and an arithmetic storage module 113. The multiplexing switch module 110 is connected to the battery cell data sampling module 10 and is used to select battery cell data. The conversion module 111 is connected to the multiplexing switch module 110 and is used to perform analog / digital conversion or digital / analog conversion on the selected battery cell data to obtain digital information and / or analog information of the battery cell data. The filtering module 112 is connected to the conversion module 111 and is used to remove interference information in the digital information and / or analog information. The arithmetic storage module 113 is connected to the filtering module 112 and is used for the arithmetic and storage of the filtered digital information and / or analog signals.

[0072] In one embodiment, in order to transmit battery cell data via the first wireless communication unit, the battery cell data is processed by the multiplexing switch module 110, the conversion module 111, the filtering module 112, and the arithmetic storage module 113 to obtain the processed battery cell data.

[0073] In some embodiments, as shown in FIG. 6, the battery cell data sampling module 10 includes at least one of a voltage sampling module (VSM) for obtaining voltage data of the battery cell, a current sampling module (CSM) for obtaining power data of the battery cell, a temperature acquisition module (TAM) for obtaining temperature data of the battery cell, and a resistance sampling module (RSM) for obtaining resistance data of the battery cell. By setting the corresponding sampling module, the acquisition of battery cell data is realized.

[0074] In some embodiments, as shown in FIG. 6, the battery management chip 1 further includes an equalization module 14. The equalization module 14 is connected to the battery cells and is used to perform consistency processing on the voltages of the battery cells so that the difference between the voltage of a battery cell and the minimum voltage of the remaining battery cells falls within a preset voltage range. By setting the equalization module 14, when the voltage consistency of the battery cells is abnormal, that is, when the voltage of a certain battery cell is high, the voltage of the battery cell is reduced by the equalization module 14. As a result, the difference between the voltage of the battery cell and the minimum voltage of the remaining battery cells becomes smaller, and it can be understood that the voltage consistency between individual battery cells is guaranteed.

[0075] In some embodiments, as shown in FIG. 6, the battery management chip 1 further includes a clock module 15. The clock module 15 is connected to the first power module 13 to determine the transmission and reception timing of battery cell data. By setting the clock module 15, the transmission and reception timing of battery cell data is controlled so that the battery cell data is transmitted and received according to a specific timing sequence.

[0076] Currently, the temperature monitoring of battery packs, chips, environments, etc. mainly calculates and determines the temperature through the change in the resistance value of a temperature-sensitive resistor. In this method, since it takes time for the resistance value to change, the temperature information is not sufficiently timely, leading to early thermal failures and detection and monitoring failures. Therefore, as shown in FIG. 6, in one embodiment of the present disclosure, the temperature acquisition module includes a temperature sensor. By arranging the temperature sensor in the temperature acquisition module to obtain the temperature data of the battery cells, compared with the case of using a temperature-sensitive resistor, the temperature sensor is more sensitive and responsive to the temperature data, thus significantly improving the temperature response processing speed.

[0077] In some embodiments, the temperature sensor is integrally arranged within the temperature acquisition module, thereby saving the layout space and cost of the battery management chip 1.

[0078] According to an embodiment of the present disclosure, the battery management chip 1 boosts the initial voltage output by the battery cell through the first power module, provides an operating voltage to the data processing module, ensures that the battery management chip can operate at a wide range of low voltages, and monitors one battery cell through one battery management chip in a corresponding manner. The first aspect is that the battery management chip does not need to face the high voltage generated by a plurality of series-connected battery cells, avoids the battery cell operating under high voltage to avoid unnecessary energy loss, thereby reducing the process requirements of chip manufacturing and saving energy consumption. The second aspect is that the failure risk of the chip can be reduced, the data of a plurality of battery cells can be avoided from being lost at one time, and the failure rate of the vehicle can be reduced. The third aspect is that the flexibility of the battery management chip can be improved, the use of a large number of wiring harnesses and connectors can be reduced, the complexity of the battery management chip can be reduced, and the stability and reliability of the battery management chip can be improved.

[0079] A battery management system according to an embodiment of the present disclosure will be described below.

[0080] As illustrated in FIG. 7, a battery management system 2 according to an embodiment of the present disclosure includes at least one battery management chip 1 described in the above embodiment, at least one battery cell (not shown) connected to at least one of the battery management chips in a one-to-one correspondence, and a control module 21 that communicates with the battery management chip 1.

[0081] According to one embodiment of the present disclosure, the battery management system 2 boosts the initial voltage output by the battery cells via the first power module, provides an operating voltage to the data processing module, ensures that the battery management chip can operate at a wide range of low voltages, and monitors one battery cell via one battery management chip. The first aspect is that the battery management chip does not need to face the high voltage generated by a plurality of series-connected battery cells, avoids the battery cells operating under high voltage to avoid unnecessary energy loss, thereby reducing the process requirements for chip manufacturing and saving energy consumption. The second aspect is that the failure risk of the chip can be reduced, the data of a plurality of battery cells can be prevented from being lost at one time, and the failure rate of the vehicle can be reduced. The third aspect is that the flexibility of the battery management chip can be improved, the use of a large number of wiring harnesses and connectors can be reduced, the complexity of the battery management chip can be reduced, and the stability and reliability of the battery management chip can be improved.

[0082] In some embodiments, the control module 21 includes a second communication module 22 that communicates with the first communication module of the battery management chip 1, and a micro control unit 23 that receives the battery cell data transmitted by the battery management chip 1 via the second communication module 22 so that the battery management chip 1 can control the battery cells connected to the battery management chip 1, and transmits a control signal to the battery management chip 1 via the second communication module 22, and a second power module 24 connected to the micro control unit 23 and used to supply power to the micro control unit 23. One battery management chip 1 manages one battery cell, the control module 22 can perform data interaction processing with a plurality of battery management chips 1 at the same time, the control module 22 sends effective operation instructions, and when the battery management chip 1 receives the instructions via wireless communication, it starts to acquire and monitor the battery cell data of a single battery cell, and then transmits the battery cell data to the control module 21 via wireless communication for data analysis and processing, and waits for the next operation.

[0083] In some embodiments, the second communication module 22 includes a second wireless communication unit. Wireless communication can be realized between the first wireless communication unit and the second wireless communication unit, and more synchronization detection functions are supported. As a result, the use of communication becomes more free and flexible. Data transmission by wireless communication is another major innovation in the twisted pair daisy chain wired communication method. First, data transmission by wireless communication reduces the insulation devices and electromagnetic compatibility protection devices required for the coupling interference of wired communication harness noise. On the one hand, data transmission by wireless communication reduces the complexity of the battery sampling board, and on the other hand, the application becomes more flexible. Second, compared with twisted pair daisy chain serial wired communication, wireless communication makes the exchange of information more flexible and convenient, can naturally realize time synchronization measurement, can support more synchronization induction functions, and avoids the problem of multi-string battery information loss in serial communication caused by wiring harnesses, thereby improving the safety of the entire vehicle. Finally, the absence of complex wiring harnesses and connectors from a structural perspective reduces the weight and complexity of the entire vehicle, improves the flexibility of design, and makes maintenance simpler and more convenient.

[0084] In some embodiments, the second power module 24 is connected to the second wireless communication unit and is used to supply power to the second wireless communication unit. The second power module is the working piece of the second wireless communication unit to ensure the normal operation of the wireless communication unit.

[0085] A vehicle according to an embodiment of the present disclosure is described below.

[0086] As illustrated in FIG. 8, a vehicle 3 according to an embodiment of the present disclosure includes the battery management system 2 described in the above embodiment.

[0087] According to an embodiment of the present disclosure, a vehicle 3 boosts an initial voltage output by a battery cell via a first power module, provides an operating voltage to a data processing module, ensures that a battery management chip can operate at a wide range of low voltages, and monitors one battery cell through one battery management chip. The first aspect is that the battery management chip does not need to face the high voltage generated by a plurality of series-connected battery cells, avoids the battery cells operating under high voltage to avoid unnecessary energy loss, thereby reducing the process requirements of chip manufacturing and saving energy consumption. The second aspect is that the failure risk of the chip can be reduced, the data of a plurality of battery cells can be avoided from being lost at one time, and the failure rate of the vehicle can be reduced. The third aspect is that the flexibility of the battery management chip can be improved, the use of a large number of wiring harnesses and connectors can be reduced, the complexity of the battery management chip can be reduced, and the stability and reliability of the battery management chip can be improved.

[0088] In the description of this specification, references to terms such as "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example.

[0089] Although embodiments of the present disclosure are shown and described above, it can be understood by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the above embodiments without departing from the principles and ideas of the present disclosure, and the scope is defined by the claims and their equivalents.

Description of Reference Numerals

[0090] 1 Battery Management Chip (BMC) 10 Battery Cell Data Sampling Module (BCDSM) 11 Data Processing Module (DPM) 12 First communication module (FCM) 13 First power module (FPM) 130 Input filtering voltage stabilization circuit unit (IFVSCU) 131 Boost circuit unit (BCU) 132 Output filtering voltage stabilization circuit unit (OFVSCU) 133 Sampling · feedback · unit (SFU) 134 PWM generation circuit subunit 135 Charge pump boost subunit 136 Waveform generation subunit 137 Voltage follower circuit 138 Inverter 139 Logic subunit 110 Multiplexing switch · module (MSM) 111 Conversion module (CONVM) 112 Filtering · module (FLTM) 113 Arithmetic storage module (ASM) 14 Equalization module (EQM) 15 Clock · module (CLKM) 2 Battery management system (BMC) 21 Control module (CTRLM) 22 Second communication module (SCM) 23 Microcontroller unit (MCU) 24 Second power module (SPM) 3 Vehicle

Claims

1. A battery management chip (1), wherein the battery management chip (1) is connected corresponding to a single battery cell, and the battery management chip (1) A battery cell data sampling module (10) used to obtain battery cell data of the battery cell, A data processing module (11) connected to the battery cell data sampling module (10) and used to process the battery cell data, A first communication module (12) connected to the data processing module (11) and used to transmit the processed battery cell data to a control module, A first power module (13) connected to the battery cell and the data processing module (11), receiving an initial voltage output by the battery cell, and performing a boost process on the initial voltage to provide an operating voltage to the data processing module (11). The battery management chip (1) comprising the above.

2. The first power module (13) Comprises a boost circuit unit (131), and the boost circuit unit (131) is connected to the battery cell and used to perform a boost process on the initial voltage output from the battery cell to obtain an initial target voltage. The battery management chip (1) according to Claim 1.

3. The first power module (13) Further comprises an input filtering voltage stabilization circuit unit (130). The input terminal of the input filtering voltage stabilization circuit unit (130) is connected to the voltage output terminal of the battery cell, and is used to reduce the voltage ripple interference of the initial voltage output by the battery cell and output a DC voltage. The battery management chip (1) according to Claim 2.

4. The first power module (13) Further comprises an output filtering voltage stabilization circuit unit (132). The output filtering voltage stabilization circuit unit (132) is connected to the boost circuit unit (131), performs filtering and stabilization on the initial target voltage to obtain a target voltage, outputs the target voltage, and is used to provide an operating voltage to the data processing module (11). The battery management chip (1) according to Claim 2 or 3.

5. The first power module (13) Further comprising a sampling feedback unit (133), the sampling feedback unit (133) is connected to the output filtering voltage stabilization circuit unit (132) and the boost circuit unit (131), obtains the voltage value of the target voltage, and is used to feedback the voltage value of the target voltage to the boost circuit unit (131). The battery management chip (1) according to claim 4.

6. The boost circuit unit (131) is further configured to receive the voltage value of the target voltage and adjust the boost action based on the voltage value of the target voltage. As a result, the initial target voltage output after adjustment is filtered and stabilized by the output filtering voltage stabilization circuit unit (132), and the output target voltage is within a preset voltage range. The battery management chip (1) according to claim 5.

7. The boost circuit unit (131) is A PWM generation circuit subunit (134), wherein a first terminal of the PWM generation circuit subunit (134) is connected to an output terminal of the input filtering voltage stabilization circuit unit (130), a second terminal of the PWM generation circuit subunit (134) is grounded, and a third terminal of the PWM generation circuit subunit (134) is used to output a PWM signal. The PWM generation circuit subunit (134) and A charge pump boost subunit (135), wherein a first terminal of the charge pump boost subunit (135) is connected to the third terminal of the PWM generation circuit subunit (134), and is used to adjust the frequency and duty cycle of the PWM signal in real time until the initial target voltage is obtained. The charge pump boost subunit (135) Comprising the battery management chip (1) according to claim 5 or 6.

8. The PWM generation circuit subunit (134) is An energy storage subunit (C1), wherein one terminal of the energy storage subunit (C1) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the other terminal of the energy storage subunit (C1) is grounded. The energy storage subunit (C1) A waveform generation sub-unit (136), wherein a first terminal of the waveform generation sub-unit (136) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and a second terminal of the waveform generation sub-unit (136) is grounded, the waveform generation sub-unit (136); A voltage follower circuit (137), wherein a first terminal of the voltage follower circuit (137) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and a third terminal of the voltage follower circuit (137) is grounded, the voltage follower circuit (137); A first comparator (Q1), wherein a non-inverting input terminal of the first comparator (Q1) is connected to the first terminal of the waveform generation sub-unit (136), the first comparator (Q1); A second comparator (Q2), wherein a non-inverting input terminal of the second comparator (Q2) is connected to the third terminal of the voltage follower circuit (137), an inverting input terminal of the second comparator (Q2) is connected to an inverting input terminal of the first comparator (Q1), and an output terminal of the second comparator (Q2) is connected to the first terminal of the charge pump boost sub-unit (135), the second comparator (Q2); A charge and discharge capacitor (C2), wherein one terminal of the charge and discharge capacitor (C2) is connected to the inverting input terminal of the first comparator (Q1) and the inverting input terminal of the second comparator (Q2), and the other terminal of the charge and discharge capacitor (C2) is grounded, the charge and discharge capacitor (C2); A duty cycle adjustment resistor (RE1), wherein one terminal of the duty cycle adjustment resistor (RE1) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and the other terminal of the duty cycle adjustment resistor (RE1) is connected to the second terminal of the voltage follower circuit (137), the duty cycle adjustment resistor (RE1) The battery management chip (1) according to claim 7, comprising.

9. The waveform generation sub-unit (136) is A voltage regulation sub-unit, wherein a first terminal of the voltage regulation sub-unit is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and a second terminal of the voltage regulation sub-unit is grounded. A charge and discharge sub-unit, wherein one terminal of the charge and discharge sub-unit is connected to the output terminal of the first comparator (Q1), and the other terminal of the charge and discharge sub-unit is connected to one terminal of the charge and discharge capacitor (C2). The battery management chip (1) according to claim 8, comprising the above.

10. The voltage regulation sub-unit is A first resistor (R1), wherein one terminal of the first resistor (R1) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130). A second resistor (R2), wherein one terminal of the second resistor (R2) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130). A third resistor (R3), wherein one terminal of the third resistor (R3) is connected to the other terminal of the first resistor (R1), and the other terminal of the third resistor (R3) is connected to the other terminal of the second resistor (R2). A fourth resistor (R4), wherein one terminal of the fourth resistor (R4) is connected to the positive-phase input terminal of the first comparator (Q1), and the other terminal of the fourth resistor (R4) is grounded. The battery management chip (1) according to claim 9, comprising the above.

11. The battery management chip (1) according to claim 9 or 10, wherein the charge and discharge sub-unit includes a fifth resistor (R5).

12. The voltage follower circuit (137) is A voltage division sub-unit, wherein one terminal of the voltage division sub-unit is connected to the other terminal of the duty cycle adjustment resistor (RE1), and the other terminal of the voltage division sub-unit is grounded. A voltage difference output unit, wherein a first terminal of the voltage difference output unit is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and a second terminal of the voltage difference output unit is connected to one terminal of the voltage division sub-unit. The battery management chip (1) according to any one of claims 8 to 11, comprising

13. wherein the voltage difference output unit is a seventh resistor (R7), one terminal of the seventh resistor (R7) being connected to one terminal of the duty cycle adjustment resistor (RE1), the seventh resistor (R7); is a triode (Q3), the base electrode of the triode (Q3) being connected to the other terminal of the duty cycle adjustment resistor (RE1), the collector electrode of the triode (Q3) being connected to the other terminal of the seventh resistor (R7), the triode (Q3); is a voltage stabilizing energy storage capacitor, one terminal of the voltage stabilizing energy storage capacitor being connected to the emitter electrode of the triode, the other terminal of the voltage stabilizing energy storage capacitor being grounded, the voltage stabilizing energy storage capacitor The battery management chip (1) according to claim 11 or 12, comprising

14. wherein the charge pump boost subunit (135) is a filtering voltage stabilizing capacitor (C4), one terminal of the filtering voltage stabilizing capacitor (C4) being connected to the output terminal of the input filtering voltage stabilizing circuit unit (130), the other terminal of the filtering voltage stabilizing capacitor (C4) being grounded, the filtering voltage stabilizing capacitor (C4); is a feedback adjustment subunit, a first terminal of the feedback adjustment subunit being connected to one terminal of the filtering voltage stabilizing capacitor (C4), a second terminal of the feedback adjustment subunit being grounded, the feedback adjustment subunit; is a charge and discharge control subunit, a first terminal of the charge and discharge control subunit being connected to one terminal of the filtering voltage stabilizing capacitor (C4), a second terminal of the charge and discharge control subunit being connected to the output terminal of the second comparator (Q2), the charge and discharge control subunit An energy storage capacitor (C5), wherein one terminal of the energy storage capacitor (C5) is connected to a third terminal of the charge and discharge control subunit, the other terminal of the energy storage capacitor (C5) is grounded, and the energy storage capacitor (C5) is used for charging when the second switch transistor (Q5) and the fourth switch transistor (Q7) are switched on, and the energy storage capacitor (C5) The battery management chip (1) according to any one of claims 8 to 13, comprising

15. The charge and discharge control subunit is A first switch transistor (Q4), wherein a gate electrode of the first switch transistor (Q4) is connected to the output terminal of the second comparator (Q2), and the first switch transistor (Q4) An inverter (138), wherein an input terminal of the inverter (138) is connected to the output terminal of the second comparator (Q2), and the inverter (138) A second switch transistor (Q5), wherein a gate electrode of the second switch transistor (Q5) is connected to the output terminal of the inverter (138), and the second switch transistor (Q5) A third switch transistor (Q6), wherein a drain electrode of the third switch transistor (Q6) is connected to a source electrode of the second switch transistor (Q5), and a gate electrode of the third switch transistor (Q6) is connected to the gate electrode of the first switch transistor (Q4), and the third switch transistor (Q6) A fourth switch transistor (Q7), wherein a source electrode of the fourth switch transistor (Q7) is connected to a source electrode of the third switch transistor (Q6), and a gate electrode of the fourth switch transistor (Q7) is connected to the output terminal of the inverter (138), and the fourth switch transistor (Q7) A pump capacitor (CE1), wherein one terminal of the pump capacitor (CE1) is connected to the drain electrode of the second switch transistor (Q5), the other terminal of the pump capacitor (CE1) is connected to the source electrode of the fourth switch transistor (Q7), and the pump capacitor (CE1) is used for charging when the first switch transistor (Q4) and the third switch transistor (Q6) are switched on, the pump capacitor (CE1) and The battery management chip (1) according to claim 14, comprising.

16. The feedback adjustment subunit is A tuning resistor (RON), wherein a first terminal of the tuning resistor (RON) is connected to the output terminal of the input filtering voltage stabilization circuit unit (130), and a second terminal of the tuning resistor (RON) is connected to the first terminal of the charge and discharge control subunit, the tuning resistor (RON) and A first feedback resistor (Rf1), wherein one terminal of the first feedback resistor (Rf1) is connected to one terminal of the energy storage capacitor (C5), the first feedback resistor (Rf1) and A second feedback resistor (Rf2), wherein one terminal of the second feedback resistor (Rf2) is connected to the other terminal of the first feedback resistor (Rf1), and the other terminal of the second feedback resistor (Rf2) is grounded, the second feedback resistor (Rf2) and An eighth resistor (Rload), wherein one terminal of the eighth resistor (Rload) is connected to one terminal of the first feedback resistor (Rf1), and the other terminal of the eighth resistor (Rload) is connected to the other terminal of the second feedback resistor (Rf2), the eighth resistor (Rload) and A feedback comparator (Q3'), wherein the inverting input terminal of the feedback comparator (Q3') is connected to the other terminal of the first feedback resistor (Rf1), and the non-inverting input terminal of the feedback comparator (Q3') is connected to the output terminal of the sampling feedback unit (133), the feedback comparator (Q3') and A logic sub-unit (139), wherein an input terminal of the logic sub-unit (139) is connected to an output terminal of the feedback comparator (Q3'), and an output terminal of the logic sub-unit (139) is connected to an adjustment terminal of the tuning resistor (RON), the logic sub-unit (139) and The battery management chip (1) according to claim 14 or 15, comprising the same.

17. The battery management chip (1) according to any one of claims 1 to 16, wherein the first communication module (12) comprises a first wireless communication unit.

18. The battery management chip (1) according to claim 17, wherein the first power module (13) is connected to the first wireless communication unit and is used to supply power to the first wireless communication unit.

19. The data processing module (11) is A multiplexing switch module (110) connected to the battery cell data sampling module (10) and used to select the battery cell data; A conversion module (111) connected to the multiplexing switch module (110) and used to perform analog / digital conversion or digital / analog conversion on the selected battery cell data to obtain digital information and / or analog information of the battery cell data; A filtering module (112) connected to the conversion module (111) and used to remove interference information in the digital information and / or analog information; An arithmetic storage module (113) connected to the filtering module (112) and used for arithmetic and storage of the filtered digital information and / or analog signal The battery management chip (1) according to any one of claims 2 to 16, comprising the same.

20. The battery cell data sampling module (10) is A voltage sampling module for obtaining voltage data of the battery cell; A current sampling module for obtaining power data of the battery cell; A temperature acquisition module for obtaining temperature data of the battery cell; and A resistance sampling module for obtaining resistance data of the battery cell The battery management chip (1) according to any one of claims 1 to 19, comprising at least one of the above.

21. An equalization module (14) that is connected to the battery cell and is used to perform consistency processing on the voltage of the battery cell so that the difference between the voltage of the battery cell and the minimum voltage of the remaining battery cells falls within a preset voltage range. The battery management chip (1) according to any one of claims 1 to 20, further comprising.

22. The battery management chip (1) according to claim 20, wherein the temperature acquisition module includes a temperature sensor, and the temperature sensor is integrally disposed within the temperature acquisition module.

23. At least one battery management chip (1) according to any one of claims 1 to 22, At least one battery cell connected to at least one of the battery management chips (1) in a one-to-one correspondence, A control module (21) that communicates with the battery management chip (1) A battery management system comprising.

24. The control module (21) is A second communication module (22) that communicates with the first communication module (12) of the battery management chip (1), Receives battery cell data transmitted via the second communication module (22) by the battery management chip (1) so that the battery management chip (1) can control the battery cell connected to the battery management chip (1), and transmits a control signal to the battery management chip (1) via the second communication module (22). A micro control unit (23), A second power module (24) connected to the micro control unit (23) and used to supply power to the micro control unit (23) The battery management system according to claim 23, comprising.

25. The battery management system according to claim 24, wherein the second communication module (22) includes a second wireless communication unit, and the second power module (24) is connected to the second wireless communication unit and used to supply power to the second wireless communication unit.

26. A vehicle (3) comprising the battery management system according to any one of claims 23 to 25.

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