Gate driving circuit and display panel

Abstract

In the gate driving circuit and display panel provided in the embodiments of the present application, the gate driving unit in the gate driving circuit includes a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module. The pull-up control module is electrically connected to the pull-up node. The pull-down control module is electrically connected to the pull-down node and the previous stage scanning signal input terminal or the second stage previous scanning signal input terminal. The pull-down control module is electrically connected to the pull-up node and the pull-down node.

Description

[Technical Field]

[0001] The present application relates to the field of display technology, and in particular to gate driving circuits and display panels. [Background technology]

[0002] Gate-driver on array (GOA) technology is a driving method that realizes progressive scanning by fabricating gate drive circuits on a thin film transistor array substrate using the thin film transistor array process. The gate drive circuit includes multiple cascaded gate drive units.

[0003] The gate driver unit includes a pull-up node and a pull-down node. The pull-up node is the gate control point of the output transistor in the GOA. When the potential of the pull-up node is high, the output transistor is turned on and the gate driver unit outputs a driving signal to the corresponding scan line. The pull-down node is the gate control point of the pull-down control transistor. When the potential of the pull-down node is high, the pull-down control transistor is turned on and the gate driver unit stops outputting a driving signal to the corresponding scan line.

[0004] In conventional gate drive circuits, the potential of the pull-up node and the potential of the pull-down node interact with each other, and if the potential of the pull-up node is not sufficient to turn on the pull-down control transistor and pull down the high potential of the pull-down node, the potential of the pull-up node will be in a conflict state where it is pulled up and pulled down at the same time, which creates a charging delay issue for the pull-up node. Summary of the Invention [Problem to be solved by the invention]

[0005] The objective of the present application is to provide a gate driving circuit and a display panel, which can improve the problem of charging delay existing in the pull-up node. [Means for solving the problem]

[0006] An embodiment of the present application provides a gate drive circuit, the gate drive circuit including a plurality of gate drive units arranged in a cascade connection, the gate drive unit including a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module. The pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node. The pull-down control module is not electrically connected to the pull-up node, and the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node. The pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node by controlling the potential of the pull-down node.

[0007] Meanwhile, the present application provides a display panel including a pixel unit and a gate drive circuit, the gate drive circuit being electrically connected to the pixel unit and including a plurality of gate drive units arranged in cascade, the gate drive unit including a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module. The pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node. The pull-down control module is not electrically connected to the pull-up node, and the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node. The pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node by controlling the potential of the pull-down node. [Effects of the Invention]

[0008] In a gate driving circuit and a display panel provided by an embodiment of the present application, the gate driving circuit includes a plurality of gate driving units arranged in a cascade connection, and the gate driving unit includes a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module. The pull-up control module is electrically connected to a previous stage scanning signal input terminal and the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node. The pull-down control module is not electrically connected to the pull-up node, and the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node. The pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node by controlling the potential of the pull-down node. The gate driving circuit is configured so that the pull-down control module is electrically connected to the previous stage scanning signal input terminal or the second stage previous scanning signal input terminal, so that the potential of the pull-down node is controlled by the potential of the scanning signal input to the previous stage scanning signal input terminal or the second stage previous scanning signal input terminal, rather than by the potential of the pull-up node, thereby alleviating the problem of delay in charging of the pull-up node caused by the high potential of the pull-down node not being pulled down in a timely manner. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram illustrating a gate drive circuit according to an embodiment of the present application. [Figure 2] 2 is a schematic diagram showing a gate driving unit in the gate driving circuit shown in FIG. 1; FIG. [Figure 3] 3 is a schematic diagram showing a first partial circuit of the gate driving unit according to FIG. 2; FIG. [Figure 4] 3 is a schematic diagram showing a second partial circuit of the gate driving unit according to FIG. 2; FIG. [Figure 5] 3 is a schematic diagram showing a third partial circuit of the gate driving unit according to FIG. 2; FIG. [Figure 6] FIG. 10 is a comparison diagram showing simulation results of the gate driving unit of the present invention and a conventional gate driving unit. [Figure 7] 3 is a schematic diagram showing a fourth partial circuit of the gate driving unit according to FIG. 2; FIG. [Figure 8] 3 is a schematic diagram showing a fifth sub-circuit of the gate driving unit according to FIG. 2; FIG. [Figure 9] 3 is a schematic diagram showing a sixth sub-circuit of the gate driving unit according to FIG. 2; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Below, the technical solutions in the embodiments of the present application will be described in accordance with the drawings in the embodiments of the present application. It should be understood that the described embodiments are merely for the purpose of explaining and illustrating the ideas of the present application and are not intended to limit the present application.

[0011] In a conventional display panel, the gate driving circuit charges the pull-up node in the gate driving unit, causing the pull-up node to have a high potential and turning on the pull-down control transistor, thereby realizing the pull-down of the pull-down node to a high potential. The pull-down control transistor has a threshold voltage (Vth). When the difference between the gate voltage (Vg) of the pull-down control transistor and the source voltage (Vs) of the pull-down control transistor is greater than Vth, the pull-down transistor is turned on. Therefore, when the pull-up node switches from a low potential to a high potential, if the difference between the potential of the pull-up node and the potential of the source of the pull-down control transistor is less than Vth, the pull-down control transistor does not turn on and the high potential of the pull-down node is not pulled down. As a result, the pull-down transistor controlled by the potential of the pull-down node remains on, and the potential of the pull-up node is pulled down by the pull-down transistor. The rise speed of the potential of the pull-up node is too slow, and the pull-down transistor remains on when the pull-up node is charging, turning on the reference low-level signal terminal and the reference high-level signal terminal, which is likely to cause short-circuit burns.

[0012] An embodiment of the present application provides a display panel, which includes a pixel unit and a gate driving circuit, the gate driving circuit being electrically connected to the pixel unit.

[0013] The display panel includes a plurality of pixel units arranged in an array and a plurality of scan lines, each of which is electrically connected to a row of pixel units. The gate driving circuit includes a plurality of gate driving units arranged in a cascade connection. Each gate driving unit is electrically connected to a corresponding scan line, and the gate driving unit provides a driving signal to the corresponding scan line to control the thin film transistors in the corresponding row of pixel units to be turned on.

[0014] The gate driving circuit in the display panel provided by the embodiment of the present application can solve the problem of delay in charging the pull-up node caused by the high potential of the pull-down node not being pulled down in a timely manner.

[0015] The transistors used in all embodiments of the present application may be thin-film transistors or other devices with the same characteristics. To distinguish between the two poles of a transistor other than the gate, one of the source and drain is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode. Based on the configuration of the accompanying drawings, the intermediate input terminal of the transistor is referred to as the gate, the signal input terminal is referred to as the first electrode, and the signal output terminal is referred to as the second electrode. The transistors used in the embodiments of the present application are P-type or N-type transistors. Here, a P-type transistor is turned on when its gate is at a low potential and turned off when its gate is at a high potential. An N-type transistor is turned on when its gate is at a high potential and turned off when its gate is at a low potential.

[0016] As shown in Figure 1, the gate driver circuit provided by the embodiment of the present application includes a plurality of gate driver units arranged in a cascade connection, which shows an N-1th stage gate driver unit GOA(n-1), an Nth stage gate driver unit GOA(n), and an N+1th stage gate driver unit GOA(n+1) as an example.

[0017] The N-1th stage gate driving unit GOA(n-1), the Nth stage gate driving unit GOA(n) and the N+1th stage gate driving unit GOA(n+1) are respectively connected to the scan lines G(n-1), G(n) and G(n+1), where the Nth stage gate driving unit GOA(n) receives the stage transmission signal ST(n-1) output from the N-1th stage gate driving unit GOA(n-1), and the N+1th stage gate driving unit GOA(n+1) is connected to receive the stage transmission signal ST(n) output from the Nth stage gate driving unit GOA(n). Meanwhile, the N-1th stage gate driving unit GOA(n-1) transmits a scanning signal to the scanning line G(n-1) connected to the N-1th stage gate driving unit GOA(n), the Nth stage gate driving unit GOA(n) transmits a scanning signal to the scanning line G(n) connected to the Nth stage gate driving unit GOA(n), and the N+1th stage gate driving unit GOA(n+1) transmits a scanning signal to the scanning line G(n+1) connected to the N+1th stage gate driving unit GOA(n+1).

[0018] Here, in response to a start signal STV, the first stage gate driver unit GOA(1) transmits a scan signal to the first scan line G(1) connected to the first stage gate driver unit GOA(1) and transmits a stage transmission signal ST(1) to the second stage gate driver unit GOA(2). Note that the Nth stage gate driver unit (N is a positive integer greater than 1) can transmit a scan signal to the Nth scan line G(n) and transmit a stage transmission signal ST(n) to the N+1th stage gate driver unit GOA(n+1).

[0019] The scan drive control signals include a first clock signal CK1 and a second clock signal CK2.

[0020] When the Nth stage gate drive unit operates, the scanning signal output by the Nth stage gate drive unit GOA(n) is high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel and charge the pixel electrode of each pixel with the data signal. The scanning signal is used to control the operation of the N+1th stage gate drive unit. When the N+1th stage gate drive unit GOA(n+1) operates, the scanning signal output by the N+1th stage gate drive unit GOA(n+1) is high potential, while the scanning signal output by the Nth stage gate drive unit GOA(n) is low potential.

[0021] As shown in FIG. 2, this gate driver unit is a non-start stage gate driver unit, and this gate driver unit includes a pull-up control module 101, a pull-up node Q, a pull-down control module 102, a pull-down node P, and a pull-down module 103.

[0022] The pull-up control module 101 is electrically connected to the previous stage scan signal input terminal G(N-1) and the pull-up node Q, and is used to pull up the potential of the pull-up node Q.

[0023] The pull-down control module 102 is not electrically connected to the pull-up node Q. Specifically, the pull-down control module 102 is electrically connected to the previous stage scanning signal input terminal G(N-1) or the second stage previous scanning signal input terminal G(N-2), and the pull-down control module 102 is further electrically connected to the pull-down node P, and the pull-down control module 102 is used to pull down the potential of the pull-down node P.

[0024] The pull-down module 103 is electrically connected to the pull-up node Q and the pull-down node P, and the pull-down module 103 is used to pull down the potential of the pull-up node Q by controlling the potential of the pull-down node P.

[0025] The gate driver unit further includes an output control module 104 and an output module 105. Here, the output control module 104 is electrically connected to the pull-down node P, and is used to pull up the potential of the pull-down node P. The output module 105 is electrically connected to the pull-up node Q, and is used to output the scanning signal G(N), and the output module 105 may include an output transistor. The output module 105 and the output control module 104 may have the same configuration as conventional ones.

[0026] In the gate driving circuit provided by the embodiments of the present application, the pull-down control module 102 is arranged to be electrically connected to the previous stage scanning signal input terminal G(N-1) or the second stage previous scanning signal input terminal G(N-2), so that the potential of the pull-down node P is controlled by the potential of the scanning signal input to the previous stage scanning signal input terminal G(N-1) or the second stage previous scanning signal input terminal G(N-2), rather than by the potential of the pull-up node Q, thereby alleviating the problem of the high potential of the pull-down node P not being pulled down in a timely manner, which causes a delay in charging the pull-up node Q.

[0027] As shown in FIGS. 3 and 4, the pull-up control module 101 includes a first transistor T1, the gate of which is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of which is electrically connected to the reference high level signal input terminal VGH, and the second electrode of which is electrically connected to the pull-up node Q.

[0028] The pull-down module 103 includes a fifth transistor T5, the gate of which is electrically connected to the pull-down node P, the first electrode of which is electrically connected to the reference low level signal input terminal VGL, and the second electrode of which is electrically connected to the pull-up node Q.

[0029] As shown in FIG. 3, the pull-down control module 102 includes a second transistor T2, the gate of which is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of which is electrically connected to the reference low level signal input terminal VGL, and the second electrode of which is electrically connected to the pull-down node P.

[0030] As shown in FIG. 4, the pull-down control module 102 includes a second transistor T2, the gate of which is electrically connected to the second stage previous scanning signal input terminal G(N-2), the first electrode of which is electrically connected to the reference low level signal input terminal VGL, and the second electrode of which is electrically connected to the pull-down node P.

[0031] As shown in FIG. 5, the pull-down control module 102 includes a third transistor T3, a fourth transistor T4, and a first node K.

[0032] The gate of the third transistor T3 is electrically connected to the first node K, the first electrode of the third transistor T3 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the pull-down node P.

[0033] The pull-up control module 101 includes a first transistor T1, the gate of which is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of which is electrically connected to the reference high level signal input terminal VGH, and the second electrode of which is electrically connected to the pull-up node Q.

[0034] The pull-down module 103 includes a fifth transistor T5, the gate of which is electrically connected to the pull-down node P, the first electrode of which is electrically connected to the reference low level signal input terminal VGL, and the second electrode of which is electrically connected to the pull-up node Q.

[0035] The gate of the fourth transistor T4 is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of the fourth transistor T4 is electrically connected to the reference high level signal input terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the first node K. Alternatively, the gate of the fourth transistor T4 is electrically connected to the second stage previous scanning signal input terminal G(N-2) (not shown).

[0036] 6, in the gate driver unit of a conventional display panel, the potential of the pull-up node Q must be pulled up until the difference between the potential of the pull-up node Q and the potential of the source of the pull-down control transistor is greater than the threshold voltage of the pull-down control transistor in order to turn on the pull-down control transistor, thereby pulling down the high potential of the pull-down node P and turning off the pull-down transistor, preventing a low-level signal from causing the pull-down transistor to pull down the potential of the pull-up node Q. Because the pull-up node Q receives both a high-level signal and a low-level signal at this stage, the charging of the pull-up node Q is delayed by time t. Accordingly, the time it takes for the pull-down node P to be pulled down to the predetermined low potential is delayed by time t. As a result, the pull-up node Q cannot be charged to the predetermined high potential within the predetermined time, which affects the display effect of the display panel.

[0037] 7, the pull-down module 103 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is electrically connected to the pull-down node P, the first electrode of the fifth transistor T5 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the fifth transistor T5 is electrically connected to the pull-up node Q.

[0038] The gate of the sixth transistor T6 is electrically connected to the next stage scanning signal input terminal G(N+1), the first electrode of the sixth transistor T6 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the pull-up node Q.

[0039] The pull-up control module 101 includes a first transistor T1, the gate of which is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of which is electrically connected to the reference high level signal input terminal VGH, and the second electrode of which is electrically connected to the pull-up node Q.

[0040] The pull-down control module 102 includes a second transistor T2, the gate of which is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of which is electrically connected to the reference low level signal input terminal VGL, and the second electrode of which is electrically connected to the pull-down node P. Alternatively, the gate of the second transistor T2 is electrically connected to the two-stage previous scanning signal input terminal G(N-2) (not shown).

[0041] The sixth transistor T6 is provided in the gate driver units other than the final stage gate driver unit, that is, only the final stage gate driver unit does not include the sixth transistor T6.

[0042] The gate driving circuit provided in the embodiments of the present application further includes a sixth transistor T6 in at least some of the gate driving units, which ensures that the potential of the pull-up node Q is pulled down in a timely manner when the gate driving unit completes signal output, so that the high potential of the pull-up node Q continues to output a signal after the signal output is completed, thereby avoiding the mischarge phenomenon occurring in the pixel units in the display.

[0043] As shown in FIGS. 8 and 9, the pull-up control module 101 includes a first transistor T1, the gate of which is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of which is electrically connected to the reference high level signal input terminal VGH, and the second electrode of which is electrically connected to the pull-up node Q.

[0044] The pull-down control module 102 includes a second transistor T2, the gate of which is electrically connected to the previous stage scanning signal input terminal G(N-1), the first electrode of which is electrically connected to the reference low level signal input terminal VGL, and the second electrode of which is electrically connected to the pull-down node P. Alternatively, the gate of the second transistor T2 is electrically connected to the second stage previous scanning signal input terminal G(N-2) (not shown), the first electrode of which is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the pull-down node P.

[0045] The pull-down module 103 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is electrically connected to the pull-down node P, the first electrode of the fifth transistor T5 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the fifth transistor T5 is electrically connected to the pull-up node Q.

[0046] The gate of the sixth transistor T6 is electrically connected to the next stage scanning signal input terminal G(N+1), the first electrode of the sixth transistor T6 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the pull-up node Q.

[0047] As shown in FIG. 8, the gate of the seventh transistor T7 is electrically connected to the next stage clock signal input terminal CK(N+1), the first electrode of the seventh transistor T7 is electrically connected to the reference low level signal input terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the pull-up node Q.

[0048] As shown in FIG. 9, the gate of the seventh transistor T7 is electrically connected to the next stage clock signal input terminal CK(N+1), the first electrode of the seventh transistor T7 is electrically connected to the full-on control signal input terminal GAS, and the second electrode of the seventh transistor T7 is electrically connected to the pull-up node Q.

[0049] The seventh transistor T7 is provided in the gate driver unit of the final stage.

[0050] The gate driver circuit provided by the embodiment of the present application further includes a seventh transistor T7 in at least some of the gate driver units, where the gate of the seventh transistor T7 is electrically connected to the next-stage clock signal input terminal CK(N+1), which outputs a periodic square wave signal. The signal output period and frequency of the next-stage clock signal input terminal CK(N+1) are the same as the source signal CKN of the output transistor, and the phase of the clock signal input to the next-stage clock signal input terminal CK(N+1) is slower than the source signal CKN of the output transistor. After the gate driver unit completes signal output, a high-level clock signal is input to the next-stage clock signal input terminal CK(N+1), which pulls down the high potential of the pull-up node Q to a low potential. The next-stage clock signal input terminal CK(N+1) receives a high-level clock signal, which pulls down the potential of the pull-up node Q. At the same time, the seventh transistor T7 can prevent the performance of the pull-down transistor from deteriorating in a harsh environment or after long-term operation, resulting in attenuation of the on-state current. The clock signal input to the next stage clock signal input terminal CK(N+1) is a periodic signal, and every time the amplitude value of the clock signal input to the next stage clock signal input terminal CK(N+1) becomes high, the pull-up node Q is pulled down low, thereby realizing a multi-pulse output by increasing the number of pull-downs.

[0051] The above provides a detailed description of the gate driving circuit and display panel provided by the embodiments of the present application. However, it should be understood that the description of the above embodiments is intended to aid in understanding the core idea of the present application, and is not intended to limit the present application. [Explanation of symbols]

[0052] 101: Pull-up control module 102: Pull-down control module 103: Pull-down module 104: Output control module 105: Output module CK: Clock signal input terminal G: Scan signal input terminal G: Scanning line GAS: Full-on control signal input terminal GOA: Stage gate drive unit K: First node P: Pull-down node Q: Pull-up node ST: Stage transmission signal STV: Start signal T1: First transistor T2: Second transistor T3: Third transistor T4: Fourth transistor T5: Fifth transistor T6: 6th transistor T7: Seventh transistor VGH: Reference high level signal input terminal VGL: Reference low level signal input terminal

Claims

1. a plurality of gate drive units arranged in a cascade connection, each gate drive unit including a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module; the pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node; the pull-down control module is not electrically connected to the pull-up node, the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node; the pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node by controlling the potential of the pull-down node; Gate drive circuit.

2. the pull-up control module includes a first transistor, a gate of the first transistor electrically connected to a previous stage scanning signal input terminal, a first electrode of the first transistor electrically connected to a reference high level signal input terminal, and a second electrode of the first transistor electrically connected to the pull-up node; 2. The gate drive circuit of claim 1.

3. the pull-down control module includes a second transistor, the gate of the second transistor is electrically connected to the previous stage scanning signal input terminal or the second stage previous scanning signal input terminal, the first electrode of the second transistor is electrically connected to the reference low level signal input terminal, and the second electrode of the second transistor is electrically connected to the pull-down node; 2. The gate drive circuit of claim 1.

4. the pull-down control module includes a third transistor and a fourth transistor, a first electrode of the third transistor electrically connected to a reference low level signal input terminal, and a second electrode of the third transistor electrically connected to the pull-down node; a gate of the fourth transistor electrically connected to a previous stage scanning signal input terminal or a second stage previous scanning signal input terminal, a first electrode of the fourth transistor electrically connected to a reference high level signal input terminal, and a second electrode of the fourth transistor electrically connected to the gate of the third transistor; 2. The gate drive circuit of claim 1.

5. the pull-down module includes a fifth transistor, the gate of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to a reference low level signal input terminal, and the second electrode of the fifth transistor is electrically connected to the pull-up node; 2. The gate drive circuit of claim 1.

6. the pull-down module further includes a sixth transistor, the gate of which is electrically connected to the next stage scanning signal input terminal, the first electrode of which is electrically connected to the reference low level signal input terminal, and the second electrode of which is electrically connected to the pull-up node; 6. The gate drive circuit according to claim 5.

7. The sixth transistor is provided in the gate driving units except for the gate driving unit of the final stage; 7. The gate drive circuit of claim 6.

8. The pull-down module further includes a seventh transistor, the gate of which is electrically connected to the next stage clock signal input terminal, the first electrode of which is electrically connected to the reference low level signal input terminal or the full-on control signal input terminal, and the second electrode of which is electrically connected to the pull-up node; 6. The gate drive circuit according to claim 5.

9. the seventh transistor is provided in the gate driver unit of the final stage; 9. The gate drive circuit of claim 8.

10. The gate driver unit further includes an output control module and an output module, the output control module is electrically connected to the pull-down node, and the output control module is used to pull up the potential of the pull-down node; the output module is electrically connected to the pull-up node, and the output module is used to output a scanning signal; 2. The gate drive circuit of claim 1.

11. The pixel circuit includes a pixel unit and a gate driving circuit, the gate driving circuit is electrically connected to the pixel unit, and the gate driving circuit includes a plurality of gate driving units arranged in a cascade connection, the gate driving unit including a pull-up control module, a pull-up node, a pull-down control module, a pull-down node and a pull-down module; the pull-up control module is electrically connected to the pull-up node, and the pull-up control module is used to pull up the potential of the pull-up node; the pull-down control module is not electrically connected to the pull-up node, the pull-down control module is electrically connected to the pull-down node, and the pull-down control module is used to pull down the potential of the pull-down node; the pull-down module is electrically connected to the pull-up node and the pull-down node, and the pull-down module is used to pull down the potential of the pull-up node by controlling the potential of the pull-down node; Display panel.

12. the pull-up control module includes a first transistor, a gate of the first transistor electrically connected to a previous stage scanning signal input terminal, a first electrode of the first transistor electrically connected to a reference high level signal input terminal, and a second electrode of the first transistor electrically connected to the pull-up node; The display panel according to claim 11 .

13. the pull-down control module includes a second transistor, the gate of the second transistor is electrically connected to the previous stage scanning signal input terminal or the second stage previous scanning signal input terminal, the first electrode of the second transistor is electrically connected to the reference low level signal input terminal, and the second electrode of the second transistor is electrically connected to the pull-down node; The display panel according to claim 11 .

14. the pull-down control module includes a third transistor and a fourth transistor, a first electrode of the third transistor electrically connected to a reference low level signal input terminal, and a second electrode of the third transistor electrically connected to the pull-down node; a gate of the fourth transistor electrically connected to a previous stage scanning signal input terminal or a second stage previous scanning signal input terminal, a first electrode of the fourth transistor electrically connected to a reference high level signal input terminal, and a second electrode of the fourth transistor electrically connected to the gate of the third transistor; The display panel according to claim 11 .

15. the pull-down module includes a fifth transistor, the gate of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to a reference low level signal input terminal, and the second electrode of the fifth transistor is electrically connected to the pull-up node; The display panel according to claim 11 .

16. the pull-down module further includes a sixth transistor, the gate of which is electrically connected to the next stage scanning signal input terminal, the first electrode of which is electrically connected to the reference low level signal input terminal, and the second electrode of which is electrically connected to the pull-up node; The display panel according to claim 15.

17. The sixth transistor is provided in the gate driving units except for the gate driving unit of the final stage; The display panel according to claim 16.

18. The pull-down module further includes a seventh transistor, the gate of which is electrically connected to the next stage clock signal input terminal, the first electrode of which is electrically connected to the reference low level signal input terminal or the full-on control signal input terminal, and the second electrode of which is electrically connected to the pull-up node; The display panel according to claim 15.

19. the seventh transistor is provided in the gate driver unit of the final stage; 19. The display panel according to claim 18.

20. The gate driver unit further includes an output control module and an output module, the output control module is electrically connected to the pull-down node, and the output control module is used to pull up the potential of the pull-down node; the output module is electrically connected to the pull-up node, and the output module is used to output a scanning signal; The display panel according to claim 11 .

Images