Neural network-based quantum error correction decoding method, device, equipment, and chip

Abstract

A neural network-based quantum error correction decoding method, device, equipment, and chip, relating to the fields of artificial intelligence and quantum technology, includes the steps of: acquiring error syndrome information by performing syndrome measurements on a quantum circuit (1010); extracting feature information from the error syndrome information using a neural network decoder (1020); performing a decoding process on the feature information using the neural network decoder to obtain a decoding result (1030); and determining error result information based on the decoding result (1040). The method significantly improves decoding performance, shortens decoding time, and is relatively easy to implement in hardware engineering.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on November 22, 2022, bearing application number 202211468927.9 and entitled "Neural network-based quantum error correction decoding method, device, equipment, and chip," the entire contents of which are incorporated herein by reference.

[0002] The embodiments of the present application relate to the fields of artificial intelligence and quantum technology, and in particular to a neural network-based quantum error correction decoding method, device, apparatus, and chip. [Background technology]

[0003] All operational processes in real quantum computing, including quantum gates and quantum measurements, are noisy, meaning that the circuits used for quantum error correction are themselves noisy.

[0004] In fault-tolerant quantum error correction, syndrome measurements are performed on a quantum circuit to obtain corresponding error syndrome information, and then the error syndrome information is decoded to determine the quantum bit in the quantum circuit where the error occurred and its corresponding error type. Related art provides several methods for decoding error syndrome information, such as a decoding method based on Minimum Weight Perfect Matching (MWPM), a decoding method based on a Renormalization Group (RG) algorithm, a decoding method based on Cellular Automaton (CA), and a decoding method based on a neural network. Currently, the decoding method based on a neural network still has some shortcomings in terms of decoding capability. Summary of the Invention

[0005] The embodiments of the present application provide a neural network-based quantum error correction decoding method, device, equipment, and chip. The technical solutions are as follows:

[0006] According to one aspect of an embodiment of the present application, there is provided a quantum error correction decoding method based on a neural network, the method being executed by a control device, and including the steps of: acquiring error syndrome information obtained by performing syndrome measurement on a quantum circuit; extracting feature information from the error syndrome information by a neural network decoder; performing a decoding process on the feature information by the neural network decoder to obtain a decoding result; and determining error result information of the quantum circuit based on the decoding result.

[0007] According to one aspect of the present invention, there is provided a neural network-based quantum error correction decoding device, the device comprising: a syndrome acquisition module configured to acquire error syndrome information obtained by performing syndrome measurement on the quantum circuit; a feature extraction module configured to extract feature information from the error syndrome information by a neural network decoder; a feature decoding module configured to perform a decoding process on the feature information using the neural network decoder to obtain a decoding result; and a result determination module configured to determine error result information of the quantum circuit based on the decoding result.

[0008] According to one aspect of an embodiment of the present application, there is provided a computer device comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to realize the above-mentioned method.

[0009] According to one aspect of an embodiment of the present application, there is provided a computer-readable storage medium having a computer program stored thereon, the computer program being loaded and executed by a processor to implement the above-described method.

[0010] According to one aspect of the present invention, there is provided a computer program product including a computer program, which is loaded and executed by a processor to implement the above method.

[0011] According to one aspect of the present invention, there is provided a chip on which a neural network decoder is disposed, the neural network decoder being used to implement the above method. [Effects of the Invention]

[0012] The present embodiment provides an error correction decoding scheme based on a multi-task learning neural network model, which uses a neural network decoder to extract corresponding feature information from input error syndrome information, and then uses the neural network decoder to decode the feature information to output a decoded result of noise-decomposed local information distribution, and then determines error result information based on the decoding result.Compared with the scheme using multiple neural network decoders, the present scheme can accurately determine error result information using a single neural network decoder, which can significantly improve decoding performance and shorten decoding time without increasing algorithm complexity and while maintaining scalability, and is also relatively easy to implement in hardware. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic diagram of a surface of revolution code according to one embodiment of the present application; [Figure 2] FIG. 1 is a schematic diagram of error occurrence in a surface code according to one embodiment of the present application. [Figure 3]FIG. 2 is a schematic diagram illustrating a comparison of the decoding performance and decoding time of several decoding schemes shown in one embodiment of the present application. [Figure 4] 1 is a schematic diagram of an application scenario of a solution according to one embodiment of the present application; [Figure 5] FIG. 5 is a schematic diagram of an error correction decoding process according to the application scenario of the solution shown in FIG. 4; [Figure 6] 1 is a schematic diagram of a simplified representation corresponding to syndrome points in a surface code of revolution according to one embodiment of the present application; FIG. [Figure 7] FIG. 1 is a schematic diagram of a syndrome measurement circuit according to one embodiment of the present application. [Figure 8] 1 is a schematic diagram of a three-dimensional syndrome distribution according to one embodiment of the present application. [Figure 9] FIG. 1 is an architecture diagram of decoding using multiple neural network models according to one embodiment of the present application. [Figure 10] 1 is a flowchart of a neural network-based quantum error correction decoding method according to one embodiment of the present application. [Figure 11] FIG. 1 is an architecture diagram of a neural network decoder based on multi-task learning according to one embodiment of the present application. [Figure 12] FIG. 2 is a schematic diagram of a decoding process of a first type decoder according to one embodiment of the present application; [Figure 13] FIG. 2 is a schematic diagram of a decoding process of a second type decoder according to one embodiment of the present application; [Figure 14] FIG. 4 is a schematic diagram of a decoding process of a second type decoder according to another embodiment of the present application; [Figure 15] FIG. 1 is a schematic diagram of local feature extraction mapping by a feature extraction sub-network according to one embodiment of the present application; [Figure 16] FIG. 2 is a schematic diagram of the associated noise generated by a syndrome measurement circuit according to one embodiment of the present application. [Figure 17] FIG. 1 is a schematic diagram of a splitting of a physical qubit according to one embodiment of the present application. [Figure 18]FIG. 1 is a schematic diagram of a splitting of a physical qubit according to another embodiment of the present application. [Figure 19] 1 is a schematic diagram of a multi-core architecture according to one embodiment of the present application; [Figure 20] FIG. 2 is a schematic diagram of experimental result data corresponding to a first error decomposition scheme according to one embodiment of the present application; [Figure 21] FIG. 1 is a schematic diagram of a chip layout according to one embodiment of the present application. [Figure 22] FIG. 10 is a schematic diagram of experimental result data corresponding to a first error decomposition scheme according to another embodiment of the present application; [Figure 23] FIG. 10 is a schematic diagram of experimental result data corresponding to a second error decomposition scheme according to one embodiment of the present application. [Figure 24] FIG. 1 is a block diagram of a neural network-based quantum error correction decoding device according to one embodiment of the present application. [Figure 25] 1 is a schematic diagram of a computer device according to one embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0014] Before describing the embodiments of the present application, some terms used in the present application will be explained.

[0015] 1. Quantum Computation (QC): A method that utilizes the properties of superposition and entanglement of quantum states to perform specific computational tasks at high speed.

[0016] 2. Quantum Error Correction (QEC) code: This is a method of encoding a quantum state by mapping it to one subspace in the Hilbert space of a many-body quantum system. Quantum noise causes the encoded quantum state to transition to another subspace. By continuously observing the quantum state's location space (syndrome extraction), quantum noise can be evaluated and corrected without interfering with the encoded quantum state, thereby preventing the encoded quantum state from being interfered with by quantum noise. Specifically, one TIFF2025528263000002.tif6170 A quantum error-correcting code represents the encoding of k logical qubits in n physical qubits, and any error occurring in any single qubit TIFF2025528263000003.tif is used to correct 5170 errors.

[0017] 3. Data quantum state: The quantum state of a data qubit used to store quantum information during quantum computing.

[0018] 4. Stabilizer generator: Also called parity check operator. The occurrence of quantum noise (error) causes some changes in the eigenvalues ​​of the stabilizer generator, and therefore quantum error correction can be performed based on this information.

[0019] 5. Stabilizer group: A stabilizer group is a group generated by stabilizer generators. For example, an abelian group generated by stabilizer generators is called a stabilizer generating group. If there are k stabilizer generators, the stabilizer group has 2 k It contains elements and is an Abelian group.

[0020] 6. Error syndrome: When there are no errors, the eigenvalue of the stabilizer generator is 0. When quantum noise occurs, the eigenvalue of the stabilizer generator (parity check operator) of some error-correcting codes that anti-commutate with errors becomes 1. A bit string consisting of these syndrome bits of 0 and 1 is called an error syndrome.

[0021] 7. Topological quantum error-correcting code: This is a special type of quantum error-correcting code. The quantum bits of this type of error-correcting code are distributed in a lattice-like arrangement that is larger than two dimensions. The lattice constitutes a discrete structure of a higher-dimensional manifold. In this case, the stabilizer generator of the error-correcting code is defined on a limited number of geometrically adjacent quantum bits, so it is geometrically local and physically easy to measure. The quantum bits on which the logical operators of this type of error-correcting code act constitute a kind of topologically nontrivial geometric object on the lattice-like arrangement manifold.

[0022] 8. Surface Code: A surface code is a type of topological quantum error-correcting code defined on a two-dimensional manifold. Its stabilizer generators are usually supported by four qubits (two qubits at the boundary), and the logical operators are nontrivial chains that cross the array in a strip-like fashion. The specific two-dimensional structure of a surface code (7x7, including 49 data qubits and 48 auxiliary qubits, for a total of 97 physical qubits, capable of correcting any error occurring in two qubits) is shown in Figure 1, where the black circle points 11 represent the data qubits used in quantum computation, and the crosses 12 represent the auxiliary qubits. The auxiliary qubits are initially It is prepared in the TIFF2025528263000004.tif7170 state. The hatched and white filled blocks represent two types of stabilizer generators for detecting Z-errors and X-errors, respectively.

[0023] 9. Surface code scale TIFF2025528263000005.tif4170: One-quarter of the perimeter of the surface code array. Surface code array in Figure 1 TIFF2025528263000006.tif4170, which has a total of 97 physical qubits, including 49 data qubits and 48 ancillary qubits.

[0024] 10. X and Z errors: These are errors caused by the Pauli X and Pauli Z operators that randomly occur in the quantum state of a physical qubit. According to quantum error correction theory, if an error-correcting code can correct X and Z errors, it can also correct errors that occur in any single qubit.

[0025] 11. Fault-tolerant quantum error correction (FTQEC): All operational processes in actual quantum computing, including quantum gates and quantum measurements, are accompanied by noise. This means that the circuits used for quantum error correction themselves contain noise. Fault-tolerant quantum error correction refers to a clever design that makes it possible to correct errors even using noisy correction circuits, thereby achieving the goal of correcting errors and preventing them from spreading over time.

[0026] 12. Fault-tolerant quantum computation (FTQC): In the process of quantum computing, any physical operation, including the quantum error correction circuit itself and quantum bit measurement, is accompanied by noise. Assuming that classical operations (such as inputting instructions and decoding error-correcting codes) are noise-free, fault-tolerant quantum computing is a technical solution for effectively controlling and correcting errors in the process of quantum computing using noisy quantum bits by rationally designing a quantum error correction scheme and performing quantum gate operations in a specific manner on the encoded logical quantum state.

[0027] 13. Physical qubit: A qubit realized using an actual physical device.

[0028] 14. Logical qubit: A mathematical degree of freedom in a Hilbert subspace defined by an error-correcting code. Its quantum state is typically described as a multi-body entangled state, typically a two-dimensional subspace of a combination of multiple physical qubits and Hilbert space. Fault-tolerant quantum computation must be performed on logical qubits protected by error-correcting codes.

[0029] 15. Quantum gates / circuits: Quantum gates / circuits that operate on physical qubits.

[0030] 16. Threshold theorem: For a quantum computing scheme that meets the requirements of fault-tolerant quantum computing, if the error rate of all operations is lower than a certain threshold, the accuracy rate of the computation can be arbitrarily approached to 1 by using better error-correcting codes, more quantum bits, and more quantum operations, and at the same time, these additional resource consumptions are negligible compared to the exponential acceleration of quantum computing.

[0031] 17. Neural Network: An artificial neural network is an adaptive, nonlinear dynamic system composed of a large number of interconnected simple basic elements called neurons. While the structure and function of each neuron are relatively simple, the system behavior generated by the combination of a large number of neurons is extremely complex, and in principle, it can represent any function.

[0032] 18. Convolutional Neural Network (CNN): A convolutional neural network is a type of feedforward neural network that includes convolutional operations and has a deep structure. The convolutional layer is the core foundation of a convolutional neural network, which performs convolution operations between a discrete two-dimensional or three-dimensional filter (also called a convolution kernel, which is a two-dimensional or three-dimensional matrix, respectively) and a two-dimensional or three-dimensional data point cloud.

[0033] 19, Linear rectification layer (Rectified Linear Units layer, ReLU layer): Linear rectification (Rectified Linear Units, ReLU) TIFF2025528263000007.tif5170 is used as the excitation function for the neural network.

[0034] 20. The Leaky Rectified Linear Unit Layer (LeakyReLU Unit) is a type of activation function based on ReLU, but instead of a flat slope for negative values, it has a very small slope.

[0035] 21. Back Propagation (BP): This is a type of supervised learning algorithm in artificial neural networks. The BP neural network algorithm can theoretically approximate any function. Its basic structure is composed of nonlinear transformation units, and it has very powerful nonlinear mapping capabilities.

[0036] 22. Field Programmable Gate Array (FPGA): This is a further developed product based on programmable devices such as PAL (Programmable Array Logic) and GAL (Generic Array Logic). It emerged as a kind of semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), solving the shortage of custom circuits and overcoming the drawback of the limited number of gate circuits in traditional programmable devices.

[0037] 23. Application Specific Integrated Circuit (ASIC): Refers to an integrated circuit designed and manufactured according to the requirements of a specific user and the needs of a specific electronic system. Designing ASICs using CPLDs (Complex Programmable Logic Devices) and FPGAs is one of the most popular methods. What they have in common is that they are both field programmable by the user and support boundary scan technology, but they have their own characteristics in terms of integration density, speed, and programming method.

[0038] 24. Single Flux Quantum (SFQ) Circuit: Also known as an RSFQ (Rapid Single Flux Quantum) circuit, this is a circuit composed of Josephson junctions (JJs), and represents "1" or "0" depending on the presence or absence of a flux quantum. In the circuit, "X" represents a Josephson junction. The top and bottom layers are made of superconductors, and the middle layer is made of a very thin insulator. It can be used for digital logic calculations.

[0039] 25. Multi-task learning: In this application, multi-task learning is defined as using the same neural network model to simultaneously perform multiple classification tasks. Multiple neural networks are configured into one large neural network, and some neural networks are shared as much as possible to achieve the goal of reducing the overall computational complexity and space complexity.

[0040] 26. Canonical Pauli Operator: For a particular stabilizer code, the Pauli operators of an equivalent class can be expressed as a representative Pauli operator. This representative Pauli operator is called the canonical Pauli operator of that operator class.

[0041] 27. Adam (Adaptive moment estimation): A type of algorithm that performs first-order gradient optimization for a random objective function, based on adaptive low-order moment estimation. The Adam algorithm is easy to implement, highly computationally efficient, and requires low memory.

[0042] The solution provided in the embodiments of the present application relates to the application of artificial intelligence machine learning technology to the field of quantum technology, specifically to the application of machine learning technology to the decoding algorithm of quantum error correcting codes, and will be described with reference to the embodiments shown below.

[0043] Because qubits are highly susceptible to noise, achieving quantum computing directly on physical qubits is not yet feasible with current technology. Developments in quantum error correction and fault-tolerant quantum computing technology offer the possibility of achieving quantum computing with arbitrary precision on noisy qubits. Generally, measuring the stabilizer generator of a quantum error-correcting code (also known as a qubit parity check) requires the introduction of long-range quantum gates, while simultaneously requiring the preparation of complex quantum auxiliary states using additional qubits to achieve fault-tolerant error correction. Due to limitations in current experimental tools, people do not yet have the ability to achieve high-precision long-range quantum gates or the preparation of complex quantum auxiliary states. On the other hand, methods for fault-tolerant quantum error correction and fault-tolerant quantum computing using surface codes do not require the use of long-range quantum gates or the preparation of complex quantum auxiliary states, and are therefore considered highly likely to realize universal fault-tolerant quantum computers using current technology.

[0044] For an error-correcting code, after an error occurs, a parity check can be used to obtain an error syndrome. Based on these syndromes, the location and type of the error (X error, Z error, or Y error, which includes both) must be determined based on the specific decoding algorithm of the error-correcting code. In the case of a surface code, the error and error syndrome have a specific spatial location. If an error causes a syndrome, the eigenvalue of the ancillary quantum bit at the corresponding location is 1 (a point particle can be considered to appear at that location). If there is no error, the eigenvalue of the ancillary quantum bit at the corresponding location is 0. In this case, decoding can be reduced to the following problem: given a spatial digital array (two or three dimensions, with values ​​of 0 or 1), based on a specific error generation model (i.e., the error probability distribution of the quantum bits), infer which quantum bit is most likely to generate an error and its specific error type, and then perform error correction based on this inference.

[0045] Figure 2 is a schematic diagram of error generation in a surface code. Quantum bits are located on the edges of a two-dimensional array, and auxiliary quantum bits that measure error syndromes are located at the nodes of the two-dimensional array (these syndromes are perfect measurements). In Figure 2, the black edges 21 represent error chains formed by quantum bits with errors, and the shaded circle portions 22 represent points where the syndrome value is 1 caused by an error. If chain-like errors can be identified based on the point-like syndromes, decoding can be accomplished.

[0046] As mentioned above, by employing a decoding algorithm (also called a decoder) for error-correcting codes to decode the error syndrome information, the corresponding error result information, including the location and type of the error, can be obtained. The decoding capability of a decoder can be evaluated based on several important indicators: decoding algorithm complexity, decoding time, decoding performance, suitability for real-time error correction, and engineering implementation difficulty.

[0047] Decoding algorithm complexity: refers to the total number of basic calculation steps required to operate the decoding algorithm, and corresponds to the computational complexity. The higher the complexity, the greater the amount of calculation required.

[0048] Decoding time: The time here is an abstract concept and is different from the actual decoding time, but it is strongly related. Here, it refers to the depth of the algorithm after fully parallelizing the decoding algorithm. This depth determines the lower limit of the execution time of the actual decoding algorithm, i.e., the execution time of the algorithm required after maximum parallelization.

[0049] Decoding performance: After decoding and correcting errors based on a specific noise model, the error rate generated by the logical qubits is used to evaluate the performance. For the same physical qubit error rate, the lower the logical error rate, the higher the decoding performance.

[0050] Suitability for real-time error correction: Due to the relatively short lifetime of qubits (for example, the lifetime of a superconducting qubit is about 150 microseconds under favorable process conditions, and after multiple syndrome measurements, real-time decoding and error correction are performed based on these syndromes. During the decoding process, the system enters an idle state, and errors accumulate over time. In theory, the entire error correction process must consume less than 1 / 1000 to 1 / 100 of the superconducting qubit lifetime, meaning the tolerance for the entire correction time is about 150 to 1500 nanoseconds. Beyond that, the error rate may exceed the correction capability of the surface code). Therefore, central processing units (CPUs) and graphics processing units (GPUs) have issues such as memory read and write time uncertainty, cache hit uncertainty, and branch jumps, which result in relatively long delays and make it impossible to meet requirements. In addition, the CPU / GPU computing microarchitecture is not optimized for decoding algorithms, making it impossible to achieve performance indicators for general purpose applications. This application considers porting the decoding algorithm to specific computing devices such as FPGAs or ASICs, which are well suited to parallelizing simple steps (e.g., vector dot products, matrix multiplications, etc.) but are not well suited to executing instructions involving complex conditional tests or jumps.

[0051] Engineering implementation difficulty: From an engineering perspective, this refers to the ease of hardware implementation of a decoder. Even if the theoretical time complexity of a decoding algorithm is low, in practice, its control may be relatively complex or the actual computational complexity may remain large, requiring multiple computing devices to work together to perform parallel calculations. The delays caused by inter-chip communication can be greater than the computational delays themselves, which is unacceptable for real-time decoding. Therefore, an algorithm that is easy to implement in engineering must ensure that the computational complexity is reduced, and the number of computing devices used and the communication between them must be reduced. Furthermore, because most of the chip area of ​​an FPGA / ASIC is used for real-time calculations, the remaining on-chip high-speed cache is limited. Therefore, it is necessary to avoid preloading a large amount of data on-chip. Specifically, when applied to neural network decoders, the number of available network parameters must not be too large, and this should not increase excessively as the scale of the error-correcting code increases. Furthermore, it is required that the on-chip memory pre-allocated on the chip be easy to read.

[0052] Currently known quantum error correction decoding schemes include those based on MWPM, RG algorithm, CA, MCMC (Monte Carlo Markov Chain), MLD (Maximum Likelihood Decoding), and NN (Neural Network). Figure 3 shows a comparison of the decoding performance and decoding time of each decoding scheme. In Figure 3, the black dots corresponding to MWPM represent the decoding performance and decoding time of the MWPM-based decoding scheme, the black dots corresponding to RG represent the decoding performance and decoding time of the RG algorithm-based decoding scheme, the black dots corresponding to CA represent the decoding performance and decoding time of the CA algorithm-based decoding scheme, the black dots corresponding to MCMC represent the decoding performance and decoding time of the MCMC algorithm-based decoding scheme, the black dots corresponding to MLD represent the decoding performance and decoding time of the MLD algorithm-based decoding scheme, and the black dots corresponding to NNbD represent the decoding performance and decoding time of the neural network-based decoding scheme. In summary, as can be seen from FIG. 3, the neural network based decoding scheme can achieve good decoding performance for small scale surface codes and requires a relatively short decoding time.

[0053] This paper proposes an end-to-end machine learning decoding method based on multi-task learning. This method has low algorithmic complexity (computational complexity TIFF2025528263000008.tif6170, decoding time While maintaining scalability without increasing the size of TIFF2025528263000009.tif5170, it significantly improves decoding performance and simultaneously optimizes decoding time and performance, as shown in the dotted-line area 30 in the lower right corner of Figure 3. At the same time, its structure is simpler, i.e., TIFF2025528263000010.tif from 6170 models This reduces the number of files to 5170, eliminating the need for communication between models and making hardware implementation easier in engineering.

[0054] 4 is a schematic diagram of an application scenario of the solution according to one embodiment of the present application. As shown in FIG. 4, the application scenario may be a superconducting quantum computing platform, which may include a quantum circuit 41, a dilution refrigerator 42, a control device 43, and a computer 44.

[0055] The quantum circuit 41 is a circuit that operates on physical quantum bits, and the quantum circuit 41 can be realized as a quantum chip, such as a superconducting quantum chip at near absolute zero. The dilution refrigerator 42 is used to provide an absolute zero environment for the superconducting quantum chip.

[0056] A control device 43 is used to control the quantum circuit 41, and a computer 44 is used to control the control device 43. For example, a created quantum program is compiled into instructions by software in the computer 44 and sent to the control device 43 (e.g., an electronic / microwave control system), and the control device 43 converts the instructions into electronic / microwave control signals and inputs them into the dilution refrigerator 42 to control the 10 mK superconducting quantum bits. The readout process is the reverse of this.

[0057] 5, the neural network-based quantum error correction decoding method according to the embodiment of the present application works in conjunction with a control device 43 (e.g., integrating the decoding algorithm into an electronic / microwave control system). After an overall control system 43a (e.g., a central board FPGA) of the control device 43 reads the error syndrome information from the quantum circuit 41, the overall control system 43a sends an error correction command to the error correction module 43b of the control device 43. The error correction command includes the error syndrome information of the quantum circuit 41. The error correction module 43b can be an FPGA or an ASIC chip. The error correction module 43b executes the neural network-based quantum error correction decoding algorithm to decode the error syndrome information, and converts the error result information obtained by decoding in real time into an error correction control signal and sends it to the quantum circuit 41 for error correction.

[0058] To facilitate the following explanation, we first introduce some basic concepts proposed in this application.

[0059] 1.Canonical representation of the Pauli operators Any Pauli operator TIFF2025528263000012.tif4170, and error correction code The generator of stabilizer groups for TIFF2025528263000013.tif4170 (this application uses a rotation surface code as an example, but any topological error-correcting code can be defined in a similar way) Given TIFF2025528263000014.tif4170, the Pauli operator acting on a physical qubit supporting an error-correcting code TIFF2025528263000015.tif4170 can be decomposed as follows: TIFF2025528263000016.tif5170

[0060] where: TIFF2025528263000017.tif5170 TIFF2025528263000018.tif4170 TIFF2025528263000019.tif4170 and the generator of the anticommuting part (Pauli operator TIFF2025528263000020.tif4170 syndrome) TIFF2025528263000021.tif5170 can be considered a bit array consisting of 0s and 1s. TIFF2025528263000022.tif5170 is the Pauli operator generated by mapping based on part of this generator. In quantum mechanics, if operators F and G satisfy FG=GF, they are said to commute, and if operators F and G satisfy FG=-GF, they are said to anticommutate. TIFF2025528263000023.tif5170 and TIFF2025528263000024.tif5170 is a one-to-one correspondence, This is called the simple representation of TIFF2025528263000025.tif4170. In the case of the surface of revolution code, a geometrically meaningful definition can be given for the simple representation, i.e., the shortest distance connecting the syndrome to the boundary, TIFF2025528263000026.tif4170. Figure 6 is a schematic diagram of a simple representation corresponding to a syndrome point in a rotation surface code. In Figure 6, the circle point a represents a syndrome point with a single value of 1, and the line 61 represents an X-type Pauli operator. This X-type Pauli operator is the shortest, Similarly, the circle b represents a syndrome point with a single value of 1, and the line 62 represents a Z-type Pauli operator, which is the shortest line connecting syndrome point b to the boundary. TIFF2025528263000028.tif4170 is the Pauli operator that anticommutates with . In general, all topological error-correcting codes can have similar simple representation mappings.

[0061] TIFF2025528263000029.tif5170 This is one specific operator in the logical type of error-correcting code to which TIFF2025528263000030.tif4170 belongs (once selected, it is fixed). Another Pauli operator If we consider TIFF2025528263000031.tif5170, a similar decomposition applies. TIFF2025528263000032.tif5170

[0062] TIFF2025528263000033.tif5170, TIFF2025528263000034.tif5170 and If TIFF2025528263000035.tif5170 belongs to the same logical type, TIFF2025528263000036.tif5170 and TIFF2025528263000037.tif4170 differ by one element of the stabilizer group, i.e., they are equivalent in terms of error correction. Then, any Pauli operator For TIFF2025528263000038.tif4170, it can be defined as follows: TIFF2025528263000039.tif5170

[0063] where: TIFF2025528263000040.tif5170 TIFF2025528263000041.tif5170 is one fixed representative element of the logical type to which it belongs, TIFF2025528263000042.tif5170 It is called the canonical representation of TIFF2025528263000043.tif4170, TIFF2025528263000044.tif5170 This is called the canonical decomposition of TIFF2025528263000045.tif4170. It converts all Pauli operators into their equivalent canonical representations. This significantly limits the unnecessary diversity of Pauli operators, which significantly reduces the difficulty of model training and improves the convergence speed of the training process, especially when Pauli operators are selected as the model output.

[0064] 2. Fault-tolerant and error-correcting multi-model learning According to theory, the fault-tolerant and error-correcting surface codes are After 5170 syndrome measurements, all collected syndrome information can be decoded together, thereby ensuring that the error correction capability of the error correction code is not affected even in fault-tolerant scenarios.

[0065] For example, the syndrome measurement circuit may be as shown in FIG. 7. Here, FIG. 7(a) shows an eigenvalue measurement circuit for a stabilizer generator that detects Z errors, and FIG. 7(b) shows an eigenvalue measurement circuit for a stabilizer generator that detects X errors. In this circuit, the order of the controlled NOT gates (CNOT) is very important and must not be reversed. Otherwise, collisions will occur due to different quantum gates using the same quantum bit. In this process, all steps, including the controlled NOT gates, the preparation of the auxiliary states, and the measurement of the final auxiliary state, will cause noise. This is because the controlled NOT gates propagate errors, and the two types of syndrome measurements, X and Z, are nested within each other. The arrangement shown in FIG. 7 minimizes error propagation and minimizes the impact on correction capability. Arrangements in other orders significantly degrade correction capability.

[0066] Thus, after multiple syndrome measurements, the error syndrome information obtained by the syndrome measurement circuit becomes a three-dimensional 0-1 array as shown in FIG. 8. FIG. 8 shows a schematic diagram of a three-dimensional syndrome distribution, with the vertical direction representing time. This can be viewed as a three-dimensional data array consisting of 0s and 1s. FIG. 8 contains a total of four slices 81, each representing the error syndrome information obtained in one measurement. Line 82 represents the syndrome caused by Z error, line 83 represents the syndrome caused by X error, and line 84 represents the measurement error.

[0067] After 5170 such syndrome measurements, the mathematical definition of the fault-tolerant optimal decoder (Maximum a posterior, MAP) is as follows: TIFF2025528263000048.tif6170 (This formula will be referred to as Formula 1)

[0068] where: TIFF2025528263000049.tif4170 is a three-dimensional data array consisting of 0s and 1s, and represents error syndrome information. TIFF2025528263000050.tif5170 is the most likely error in a two-dimensional data qubit that can be inferred based on measured error syndrome information. This applies the operation corresponding to TIFF2025528263000051.tif5170 and corrects the physical errors that occurred in it. TIFF2025528263000052.tif5170 and the error that actually exists in the physical qubit TIFF2025528263000053.tif6170 does not need to match, and the weight of the difference between them TIFF2025528263000054.tif6170 is small enough, It is sufficient to ensure that TIFF2025528263000055.tif6170 can be corrected in the next correction process. The classification results corresponding to each data qubit include four cases: I, X, Y, and Z, where I represents no error, X represents an X error, Z represents a Z error, and Y represents the presence of both an X error and a Z error. A quantum circuit with an error-correcting code scale of L contains data qubits with a scale of L. 2 Therefore, Possible alternatives for TIFF2025528263000056.tif4170 are TIFF2025528263000057.tif5170 Contains different Pauli operators. Traverse all Since it is impossible to calculate the probability of TIFF2025528263000058.tif4170, the decoding problem is #P-Complete in computational complexity. To perform efficient decoding, we need to simplify it. Canonical representation of TIFF2025528263000059.tif4170, i.e., By using TIFF2025528263000060.tif5170, all equivalent TIFF2025528263000061.tif4170. This reduces the number of Pauli operators that need to be traversed to TIFF2025528263000062.tif10170. The reason is that for an error correcting code, all errors multiplied by one element of the stabilizer group are equivalent, so when classifying errors, these equivalent errors can be grouped together, and the stabilizer group has TIFF2025528263000063.tif contains 5170 elements, so here TIFF2025528263000064.tif5170 types of errors need to be traversed. Regarding TIFF2025528263000065.tif4170, the canonical representation representing the equivalent Pauli operator without distinction is Use TIFF2025528263000066.tif5170.

[0069] Furthermore, it is necessary to represent the error information and divide and conquer the represented information into different information blocks, thereby reducing the traversal complexity. This application provides two error decomposition methods.

[0070] The first method is a canonical decomposition method of the canonical representation. TIFF2025528263000067.tif A set of 5170 syndromes TIFF2025528263000068.tif6170, It can be described using the TIFF2025528263000069.tif6170 element, TIFF2025528263000070.tif5170 TIFF2025528263000071.tif6170 and This can be determined based on TIFF2025528263000072.tif6170. TIFF2025528263000073.tif5170 and TIFF2025528263000074.tif5170 is called the canonical syndrome of the decoding output. Taking TIFF2025528263000075.tif5170 as an example, it can be broken down as follows: TIFF2025528263000076.tif6170

[0071] each TIFF2025528263000077.tif6170 contains some X-type syndrome bits. There is a similar decomposition for Z-type syndrome bits. Therefore, the MAP decoding process for Z-type errors is approximately as follows: TIFF2025528263000078.tif7170

[0072] Similar processing can be performed for X-type errors, and the MAP decoding process for X-type errors is approximately as follows: TIFF2025528263000079.tif7170

[0073] The second method is to directly decompose the Pauli error according to its distribution in the physical qubits, which can be divided into disjoint sets of different blocks. TIFF2025528263000080.tif5170

[0074] This division If we write TIFF2025528263000081.tif5170, the following formula holds: TIFF2025528263000082.tif5170

[0075] where: TIFF2025528263000083.tif5170 is Works on TIFF2025528263000084.tif5170 is the Pauli operator of TIFF2025528263000085.tif4170, TIFF2025528263000086.tif5170 represents a Cartesian product. Thus, the decoding process can be approximately simplified as follows: TIFF2025528263000087.tif6170

[0076] where The formula TIFF2025528263000088.tif14170 is This is the marginal probability distribution of TIFF2025528263000089.tif5170, TIFF2025528263000090.tif7170 is Block TIFF2025528263000091.tif4170 TIFF2025528263000092.tif4170, where the value of i is an integer in the range [1, m]. As in the case of canonical representation decomposition, we further TIFF2025528263000093.tif6170 and It can also be decomposed into TIFF2025528263000094.tif6170 and decoded using approximate MAP. TIFF2025528263000095.tif7170

[0077] In any method, the division method selected is TIFF2025528263000096.tif7170 or TIFF2025528263000097.tif5170, i.e., there is an upper limit to its size, and this upper limit does not depend on the scale of the error-correcting code. Under this constraint, we must improve the decoding performance as much as possible. The reason for this selection is based on the intuition that there is a limited correlation between the syndrome and the errors occurring in the physical bits, and that the scale of this correlation does not increase with L.

[0078] In addition, MWPM is TIFF2025528263000098.tif5170 using only syndromes of type Decoding errors of type TIFF2025528263000099.tif5170. However, to decode the X and Z errors, it may be necessary to use all syndrome bit information simultaneously. This is because the Z and X errors are interrelated, and the corresponding syndrome bits are not completely independent. By considering all syndromes together, the location of the X and Z errors can be determined more accurately. However, MWPM or other algorithms have not yet taken advantage of this.

[0079] The purpose of using machine learning based methods is to: TIFF2025528263000100.tif7170, TIFF2025528263000101.tif7170, TIFF2025528263000102.tif5170These distribution functions are simply approximated using neural networks. Because these functions all share a common input S (three-dimensional syndrome bits), a straightforward approach is to use a neural network model to approximate each distribution function, normalizing it using a Softmax function at the end of the network to generate a corresponding probability distribution, summarizing error information based on the distribution results, and correcting the data qubits. The overall decoding process is shown in Figure 9, in which m (m is greater than 1) neural network models each perform decoding processing on the error syndrome information S to obtain m sets of probability distributions, and then determining error result information based on the m sets of probability distributions. The error result information indicates the data qubits where errors occur and the corresponding error types.

[0080] It should be noted that there is a maximum limit on the output size of each network. Therefore, the number of neural networks and the number of physical qubits TIFF2025528263000103.tif5170 is directly proportional.

[0081] If there is no noise in each syndrome measurement, only one level of syndrome measurement is sufficient, and there is no need to infer the simple error part in the canonical representation of the error operator, so that the above equation 1 can be simplified as follows: TIFF2025528263000104.tif6170

[0082] For surface codes encoding a single bit, this decoding scheme simplifies to a four-classification problem, so a single network can accomplish the decoding task. From a topology perspective, in fault-tolerant scenarios with measurement noise, the decoding problem cannot be reduced to a similar simple classification problem. Therefore, fault-tolerant decoding using neural networks is much more complex than in the perfect syndrome case.

[0083] FIG. 10 is a flowchart of a neural network-based quantum error correction decoding method according to one embodiment of the present application, which is applicable to the control device of the application scenario shown in FIG. 4, and which may include at least one of the following steps 1010 to 1040:

[0084] In step 1010, error syndrome information obtained by performing syndrome measurement on the quantum circuit is acquired.

[0085] Here, the error syndrome information is a data array made up of eigenvalues ​​of the stabilizer generator of the quantum error correcting code.

[0086] By performing error syndrome measurements on a quantum circuit using a quantum error correcting code, corresponding error syndrome information can be obtained, where the error syndrome information is a data array consisting of eigenvalues ​​of a stabilizer generator of the quantum error correcting code. Exemplarily, the error syndrome information is a two-dimensional or three-dimensional data array consisting of 0s and 1s. For example, if there is no error, the eigenvalue of the stabilizer generator is 0, and if an error occurs, the eigenvalue of the stabilizer generator is 1.

[0087] Taking the quantum error correcting code as a surface code for example, in the case of a surface code, errors and error syndromes have specific spatial locations. When an error causes a syndrome, the eigenvalue of the ancillary quantum bit at the corresponding location is 1 (which can be considered as a point particle appearing at that location), and when there is no error, the eigenvalue of the ancillary quantum bit at the corresponding location is 0. Therefore, for a surface code, if the error of the correction process itself is not taken into account (i.e., the measurement process is perfect, in this case it is called a perfect syndrome), the error syndrome information can be considered as a two-dimensional data array consisting of 0s and 1s.

[0088] For example, if multiple syndrome measurements are performed on a quantum circuit, error syndrome information in the form of a two-dimensional data array can be obtained from each syndrome measurement, and error syndrome information in the form of a three-dimensional data array can be obtained from multiple syndrome measurements, as shown in FIG. 8.

[0089] In step 1020, a neural network decoder is used to extract feature information from the error syndrome information.

[0090] In one possible embodiment, when using a neural network decoder to extract feature information from the error syndrome information, the control device can perform feature extraction on the error syndrome information through a feature extraction network of the neural network decoder to obtain the feature information, where the neural network decoder includes a feature extraction network and n feature decoding networks, where n is an integer greater than 1.

[0091] The neural network decoder is a machine learning model based on a neural network for decoding error syndrome information, whose input data is the error syndrome information and whose output data is the error result information corresponding to the error syndrome information.

[0092] In an embodiment of the present application, the neural network decoder includes one feature extraction network and multiple feature decoding networks. Here, the feature extraction network is used to perform feature extraction on the error syndrome information to obtain feature information. The feature information output from the feature extraction network is input to multiple feature decoding networks, which then perform decoding processing on the feature information to obtain decoding results corresponding to each feature decoding network.

[0093] In some embodiments, the feature extraction network can be based on a CNN. In some embodiments, the feature decoding network can be based on a FCN (Fully Connected Neural Network). Of course, the present application is not limited to the feature extraction network and the feature decoding network, and the feature extraction network and the feature decoding network may have other network structures.

[0094] In Figure 9, the number of models is the number of bits. The computational complexity increases linearly with increasing size, resulting in a large increase in computational complexity. Too many models also significantly increase the difficulty of implementing the algorithm on specific hardware. Although these models can be executed in parallel, the increased complexity rapidly increases the amount of hardware resources consumed, requiring a large number of FPGA or ASIC chips, which creates difficulties in system integration. Therefore, We try to extract as many reusable parts as possible from 6170 models and construct a single frontend, i.e., a feature extraction network. The output of the frontend is The output is sent to TIFF2025528263000107.tif6170 simplified feature decoding networks, such as feed-forward fully connected networks (FFNs), which generate n probability distributions to perform decoding, and these n different feature decoding networks form the backend of the model.

[0095] For example, the entire model is shown in FIG. 11. The front end is a feature extraction network, which may include multiple cascaded feature extraction subnetworks and one feature fusion subnetwork. The role of the feature extraction subnetworks is to extract local feature information in a divide-and-conquer manner, and the feature fusion subnetwork finally aggregates and compresses all the local feature information to obtain the final feature information. Here, the feature extraction subnetworks can be built based on CNN, for example, each feature extraction subnetwork includes one or more convolutional layers. The feature fusion subnetworks can be built based on a fully connected network, for example, including one or two fully connected layers.

[0096] This is a typical multi-task learning neural network model, and its effectiveness is based on the premise that the features extracted at the front end are sufficiently large, and can be provided to any back-end feature decoding network to accurately estimate the local information distribution of noise decomposition (e.g., TIFF2025528263000108.tif7170, TIFF2025528263000109.tif7170, TIFF2025528263000110.tif5170) can be generated synthetically. This makes sense in principle, because the backend TIFF2025528263000111.tif6170It can be considered as a localized simplified version of a global classifier, and the premise for this is that the information provided by the front end can, in principle, be used to classify the global classifier. TIFF2025528263000112.tif6170 The goal is to provide a method for calculating the Pauli operator distribution. Furthermore, the front-end computational complexity must be acceptable for engineering purposes, provided that decoding performance is not affected.

[0097] The scale of the front-end and back-end networks is determined according to the specific situation. According to the current experimental results, the size of the back-end feature decoding network (e.g., when using a fully connected layer) is approximately the same as the error correction code scale. The number of model parameters in the backend is independent of TIFF2025528263000113.tif4170. TIFF2025528263000114.tif6170, and the calculated depth is TIFF2025528263000115.tif5170. The computational complexity of the entire backend is TIFF2025528263000116.tif6170. The computational complexity of the front end and the overall algorithm will be explained later.

[0098] In addition, both of the above-mentioned error decomposition methods can use a model architecture based on the multi-task learning. The advantage of the first error decomposition method is that the actual network size is relatively small, but the performance of the resulting decoder may be limited due to the constraints of the training data generation method. The second error decomposition method provides end-to-end training and can significantly improve decoding performance by using X-type and Z-type syndromes for decoding. In the present embodiment, a neural network decoder that uses the first error decomposition method for training and inference is referred to as a "type 1 decoder," and a neural network decoder that uses the second error decomposition method for training and inference is referred to as a "type 2 decoder."

[0099] For example, the feature extraction network of the neural network decoder employs a block-partitioning feature extraction method based on the idea of ​​dividing and processing when performing feature extraction on error syndrome information. That is, each or some of the feature extraction sub-networks are used to perform block-partitioning feature extraction on input data. The so-called block-partitioning feature extraction refers to the feature extraction sub-networks dividing the input data into blocks, dividing it into multiple small blocks, and performing feature extraction on each small block when extracting feature information. That is, block-partitioning feature extraction refers to dividing the input data into blocks to obtain at least two blocks, and then using at least two feature extraction units to perform feature extraction processing on the at least two blocks in parallel. Here, the at least two blocks and the at least two feature extraction units correspond one-to-one, and each feature extraction unit is used to perform feature extraction on one block, and the number of blocks and feature extraction units is the same. Furthermore, the at least two blocks perform feature extraction in parallel, i.e., simultaneously, which helps to shorten the time required for feature extraction. For example, as shown in FIG. 11, the error syndrome information is a three-dimensional syndrome bit, and the three-dimensional syndrome bit is divided into C1 blocks. After that, the first feature extraction sub-network performs feature extraction on the C1 blocks in parallel to obtain C2 blocks. Similarly, the second feature extraction sub-network performs feature extraction on the C2 blocks in parallel to obtain C3 blocks. Similarly, the kth feature extraction sub-network performs feature extraction on the C2 blocks in parallel to obtain C3 blocks. k Feature extraction is performed on blocks in parallel, and C k+1 Finally, the feature fusion sub-network is used to obtain the above C k+1 Fusion and compression processes are performed on these blocks to obtain feature information, which is used as input for the backend.

[0100] In step 1030, the neural network decoder performs a decoding process on the feature information to obtain a decoding result.

[0101] In one possible embodiment, when the neural network decoder includes a feature extraction network and n feature decoding networks, the control device can perform decoding processing on the feature information through the n feature decoding networks respectively, and obtain decoding results corresponding to the n feature decoding networks respectively, where the n feature decoding networks are networks trained using a multi-task learning method and have the ability to generate different decoding results.

[0102] For a first type decoder, step 1030 comprises: Performing decoding processing on the feature information by n1 feature decoding networks respectively, and obtaining decoding results corresponding to the n1 feature decoding networks respectively, wherein for an i-th feature decoding network among the n1 feature decoding networks, the decoding result corresponding to the i-th feature decoding network includes an i-th term canonical syndrome associated with a target error type, where i is a positive integer equal to or less than n1, and the canonical syndrome refers to a canonical decomposition result of the error syndrome information; The method may include: performing decoding processing on the feature information by n2 feature decoding networks respectively, and obtaining decoding results corresponding to the n2 feature decoding networks respectively, wherein for a j-th feature decoding network among the n2 feature decoding networks, the decoding result corresponding to the j-th feature decoding network includes a fixed representative element related to a target error type, and j is a positive integer less than or equal to n2, where the sum of n1 and n2 is equal to n, and n1 and n2 are positive integers.

[0103] In some embodiments, the target error types include a Pauli X error and a Pauli Z error, n1 is equal to the sum of m1 and m2, where m1 and m2 are positive integers, and n2 is 2; Among the n1 feature decoding networks, m1 feature decoding networks are used to perform decoding processing on the feature information, respectively, to obtain m1 canonical syndromes related to the Pauli X-errors, Among the n1 feature decoding networks, m2 feature decoding networks are used to perform decoding processing on the feature information, respectively, to obtain m2-term canonical syndromes related to the Pauli Z error, One of the n feature decoding networks is used to perform a decoding process on the feature information to obtain a fixed representative element related to the Pauli X error; Another feature decoding network among the n2 feature decoding networks is used to perform a decoding process on the feature information and obtain a fixed representative element related to the Pauli Z error.

[0104] Exemplarily, the values ​​of m1 and m2 may be the same or different. Exemplarily, the error syndrome information includes Z-type syndrome information and X-type syndrome information, decoding is performed based on the Z-type syndrome information to obtain X-type error result information, the X-type error result information indicating a quantum bit in which a Pauli X error has occurred in the quantum circuit, and decoding is performed based on the X-type syndrome information to obtain Z-type error result information, the Z-type error result information indicating a quantum bit in which a Pauli Z error has occurred in the quantum circuit.

[0105] For example, the canonical syndrome of the m1 term associated with the Pauli X error above is TIFF2025528263000117.tif6170, and each TIFF2025528263000118.tif6170 contains some Z-type syndrome bits, which are used in decoding to determine X-type errors. The m-term canonical syndrome associated with the Pauli Z error above is TIFF2025528263000119.tif6170, and each TIFF2025528263000120.tif6170 contains some X-type syndrome bits, which are used in decoding to determine Z-type errors. The fixed representative elements associated with the Pauli X-errors above are: TIFF2025528263000121.tif6170. The fixed representative element associated with the Pauli Z error above is It can be expressed as TIFF2025528263000122.tif6170.

[0106] For the second type of decoder, the qubits included in the quantum circuit are divided into n blocks, each block including at least one qubit. For a kth feature decoding network among the n feature decoding networks, the decoding result corresponding to the kth feature decoding network includes a Pauli operator acting on the qubits included in the kth block among the n blocks, where k is a positive integer less than or equal to n.

[0107] For example, the kth block is TIFF2025528263000123.tif5170, and the kth block The Pauli operator acting on the quantum bit in TIFF2025528263000124.tif5170 is TIFF2025528263000125.tif5170. In this way, the n feature decoding networks are constructed by Pauli operators acting on the n blocks respectively. You can get TIFF2025528263000126.tif5170.

[0108] In step 1040, the error result information of the quantum circuit is determined based on the decoding result.

[0109] In some embodiments, the error result information indicates the qubit in the quantum circuit where the error occurred.

[0110] For example, the error result information may also indicate an error type corresponding to a quantum bit in which an error has occurred in the quantum circuit.

[0111] In one possible embodiment, when the neural network decoder includes a feature extraction network and n feature decoding networks, the control device can determine the error result information based on the decoding results corresponding to the n feature decoding networks, respectively.

[0112] Based on the error result information output from the neural network decoder, it is possible to determine the qubit in which the error occurred in the quantum circuit and the corresponding error type, for example, the position of the data qubit in which the error occurred in the quantum circuit and the error type of the data qubit in which the error occurred at that position (e.g., whether it is a Pauli X error, a Pauli Z error, or a Pauli Y error which includes both Pauli X and Z errors).

[0113] For a first type decoder, step 1040 may include:

[0114] Based on the fixed representative element associated with the Pauli X error and the canonical syndrome of the m1 term associated with the Pauli X error, X-type error result information is determined, and the X-type error result information indicates the qubit in the quantum circuit where the Pauli X error occurred. That is, TIFF2025528263000127.tif6170 and X type error result information based on TIFF2025528263000128.tif6170 Determine TIFF2025528263000129.tif5170; Based on the fixed representative element associated with the Pauli Z error and the canonical syndrome of the m2 term associated with the Pauli Z error, Z-type error result information is determined, and the Z-type error result information indicates the qubit in the quantum circuit where the Pauli Z error occurred. That is, TIFF2025528263000130.tif6170 and Z type error result information based on TIFF2025528263000131.tif6170 Determine TIFF2025528263000132.tif5170; the above TIFF2025528263000133.tif5170 and For the specific principle of determining TIFF2025528263000134.tif5170, please refer to the introduction in the above examples.

[0115] In some embodiments, for the first-type decoder, two neural network decoders can be trained, referred to as the first neural network decoder and the second neural network decoder, respectively. As shown in Figure 12, a feature extraction network of the first neural network decoder performs feature extraction on the Z-type error syndrome information to obtain first feature information. Then, m1+1 feature decoding networks of the first neural network decoder perform decoding processes on the first feature information, respectively, to obtain decoding results corresponding to the m1+1 feature decoding networks, where the decoding results corresponding to the m1 feature decoding networks include m1-term canonical syndromes related to the Pauli X error, and the decoding result corresponding to another feature decoding network includes a fixed representative element related to the Pauli X error. X-type error result information is determined based on the m1-term canonical syndromes related to the Pauli X error and the fixed representative element related to the Pauli X error, and the X-type error result information indicates a quantum bit in the quantum circuit where a Pauli X error has occurred. Furthermore, the feature extraction network of the second neural network decoder performs feature extraction on the X-type error syndrome information to obtain second feature information, and then the m2+1 feature decoding networks of the second neural network decoder perform decoding processing on the second feature information respectively to obtain decoding results corresponding to the m2+1 feature decoding networks, where the decoding results corresponding to the m2 feature decoding networks include an m2-term canonical syndrome related to the Pauli-Z error, and the decoding result corresponding to another feature decoding network includes a fixed representative element related to the Pauli-Z error, and Z-type error result information is determined based on the m2-term canonical syndrome related to the Pauli-Z error and the fixed representative element related to the Pauli-Z error, and the Z-type error result information indicates a quantum bit in the quantum circuit where a Pauli-Z error has occurred.Both the first neural network decoder and the second neural network decoder can be trained using the multi-task learning method introduced above, and the number of feature decoding networks included in the first neural network decoder and the second neural network decoder can be the same or different, and the present application is not limited thereto.

[0116] 12 only illustrates the example of decomposing the error syndrome information into two parts, Z-type error syndrome information and X-type error syndrome information, which are input to the first and second neural network decoders, respectively. This helps reduce the computational complexity of the neural network decoders. In some other embodiments, the error syndrome information can be directly input to the first and second neural network decoders without being decomposed, so that the first neural network decoder obtains X-type error result information based on the error syndrome information, and the second neural network decoder obtains Z-type error result information based on the error syndrome information.

[0117] For a second type of decoder, step 1040 may include determining error result information based on a Pauli operator acting on each of the n blocks, i.e. Error result information based on TIFF2025528263000135.tif5170 TIFF2025528263000136.tif5170 is determined as above. For the specific principle of determining TIFF2025528263000137.tif5170, please refer to the introduction in the above examples.

[0118] In some embodiments, as shown in FIG. 13 , for a second-type decoder, the error result information indicates the quantum bit in which a Pauli X error occurred and the quantum bit in which a Pauli Z error occurred in the quantum circuit. That is, the error syndrome information does not distinguish between X-type error syndrome information and Z-type error syndrome information, but instead simultaneously uses all syndrome bits to decode the X and Z errors. Correspondingly, the decoding result does not distinguish between X-type error result information and Z-type error result information, but instead directly decodes to obtain error result information including X-type and Z-type errors. Because X and Z errors are interrelated, the above method allows for more accurate determination of the locations of X and Z errors by considering all syndrome bits together. Experimental data, described below, confirms that this approach significantly improves decoding performance. In this case, decoding of the error syndrome information and obtaining error result information can be performed using only one neural network decoder.

[0119] In some embodiments, the second-type decoder may use two neural network decoders, referred to as the first neural network decoder and the second neural network decoder, respectively. As shown in FIG. 14, the first neural network decoder and the second neural network decoder both receive error syndrome information, and do not distinguish between X-type error syndrome information and Z-type error syndrome information. Instead, they simultaneously use all syndrome bits to decode the X and Z errors. The feature extraction network of the first neural network decoder performs feature extraction on the error syndrome information to obtain first feature information. Then, n feature decoding networks of the first neural network decoder perform decoding processes on the first feature information, respectively, to obtain first decoding results corresponding to the n feature decoding networks, where the first decoding result corresponding to the kth feature decoding network includes a Pauli operator related to an X-type error acting on the kth block. Based on the first decoding results corresponding to the n feature decoding networks, X-type error result information is determined, and the X-type error result information indicates a quantum bit in the quantum circuit where a Pauli X error occurs. In addition, a feature extraction network of the second neural network decoder performs feature extraction on the error syndrome information to obtain second feature information, and then n feature decoding networks of the second neural network decoder perform decoding processes on the second feature information respectively to obtain second decoding results corresponding to the n feature decoding networks, where the second decoding result corresponding to the kth feature decoding network includes a Pauli operator related to a Z-type error acting on the kth block, and Z-type error result information is determined based on the second decoding results corresponding to the n feature decoding networks respectively, and the Z-type error result information indicates a quantum bit in the quantum circuit where a Pauli Z error has occurred.Both the first neural network decoder and the second neural network decoder can be trained using the multi-task learning method introduced above, and the number of feature decoding networks included in the first neural network decoder and the second neural network decoder can be the same or different, and the present application is not limited thereto.

[0120] In the present embodiment, the output type of the neural network decoder is not limited. In one possible embodiment, a physical level output is adopted, and the model of the physical level output directly generates information about the quantum bit where a specific error occurred, i.e., the type of error that specifically occurred on which quantum bit. In another possible embodiment, a logical level output is adopted, and the model of the logical level output outputs a logical error type into which the specific error is converted through a specific mapping. Then, based on this logical error type, the equivalent error specifically occurred on the quantum bit can be calculated (this calculated error may not be identical to the original error, but the effect is the same. This is an error degeneracy phenomenon specific to quantum error correcting codes). For example, to reduce the complexity of the neural network decoder and further shorten the decoding time, the neural network decoder can use a logical level output.

[0121] In some embodiments, the neural network decoder performs the measurement collection process of new error syndrome information in parallel with the process of decoding previously acquired error syndrome information. By parallelizing the syndrome measurement and decoding, This eliminates the need to wait until all 170 syndrome measurements are complete before starting decoding. The corresponding calculation can begin when enough syndrome bits are available to perform the smallest calculation (e.g., a single convolution operation). In this way, decoding can begin during subsequent syndrome measurements, and both are parallelized. This reduces the overall delay time caused by performing error correction after the final syndrome measurement is complete. The shorter this delay, the better, to prevent errors from accumulating during the error correction process.

[0122] In some embodiments, the feature extraction network and the n feature decoding networks included in the neural network decoder are located on the same chip. Illustratively, the chip may be an FPGA or an ASIC. Illustratively, if two neural network decoders are required in some embodiments, the two neural network decoders may be located on the same chip or on two chips, and the present application is not limited thereto.

[0123] As described above, the technical solution provided in the embodiments of the present application provides an error correction decoding scheme based on a multi-task learning neural network model, in which a neural network decoder extracts corresponding feature information from input error syndrome information, then the neural network decoder performs decoding on the feature information, outputs a decoded result of noise-decomposed local information distribution, and then determines error result information based on the decoding result.Compared with the scheme using multiple neural network decoders, the scheme of the present application can accurately determine error result information with only a single neural network decoder, thereby significantly improving decoding performance and shortening decoding time without increasing algorithm complexity and maintaining scalability, and furthermore, the hardware implementation is relatively easy in engineering. For example, in the above embodiment, the neural network decoder is designed as a structure including a feature extraction network and multiple feature decoding networks, where the feature extraction network extracts corresponding feature information from the input error syndrome information, and the feature information is simultaneously used as the input for multiple feature decoding networks, which output noise-decomposed local information distributions, and then error result information is determined based on the decoding results of the multiple feature decoding networks.Compared to the solution using multiple neural network decoders, this solution can significantly improve decoding performance and shorten decoding time without increasing algorithm complexity and while maintaining scalability, and is also relatively easy to implement in hardware.

[0124] In addition, for the second type of decoder, a direct decomposition method based on the distribution of Pauli errors in physical qubits can provide end-to-end reasoning and training. Furthermore, because X and Z errors are interrelated, decoding using both X-type and Z-type syndromes simultaneously can take all syndrome bits into account, allowing for more accurate determination of the location of X and Z errors, significantly improving decoding performance.

[0125] In some embodiments, for the feature extraction network of the neural network decoder, this application proposes to use Local Feature Extraction Mapping (LFEM) to reduce the computational complexity.

[0126] In addition to the complexity of the output terminal due to measurement noise (which can be solved by multi-task learning), another complexity of a neural network decoder is the complexity of its own training and inference. In the embodiment of this application, the following solution is proposed: a large-scale error correcting code is considered as multiple small-scale error correcting codes (which can be called "small error correcting codes"), and "decoding" is performed locally on the "small error correcting codes", and then the obtained information is aggregated at a higher level and "decoding" is performed. This process can be performed recursively until the final decoded information is the error that needs to be corrected. The decoding of the "small error correcting codes" of a specific region in each layer can be called LFEM.

[0127] In some embodiments, the feature extraction network includes multiple cascaded feature extraction sub-networks, where the input data of the first feature extraction sub-network includes error syndrome information, the input data of the sth feature extraction sub-network includes output data of the s-1th feature extraction sub-network, and the output data of the last feature extraction sub-network includes feature information, and s is an integer greater than 1.

[0128] For a target feature extraction subnetwork among the plurality of cascaded feature extraction subnetworks, input data for the target feature extraction subnetwork is divided into a plurality of input data blocks having the same scale. The target feature extraction subnetwork may be any one of the plurality of cascaded feature extraction subnetworks. The target feature extraction subnetwork is used to perform local feature extraction mapping on the plurality of input data blocks multiple times to obtain a plurality of sets of mapping output data. Here, each local feature extraction mapping is used to perform a mapping process on regions at the same positions in the plurality of input data blocks to obtain a set of mapping output data, and different local feature extraction mappings are used to perform a mapping process on regions at different positions in the plurality of input data blocks to obtain a plurality of sets of mapping output data. The target feature extraction subnetwork is further used to obtain output data for the target feature extraction subnetwork based on the plurality of sets of mapping output data.

[0129] Fig. 15 shows an example of a schematic diagram of local feature extraction mapping by a feature extraction sub-network. Fig. 15 shows the process of performing LFEM on two differently positioned regions (identified by symbols (1) and (2) in the figure), and one LFEM is input. TIFF2025528263000139.tif5170 input data blocks operate on the same region. Different iterations of LFEM operate on the same region in the input data blocks. TIFF2025528263000140.tif operates on regions at different positions in 5170 input data blocks, and two regions at different positions (1) and (2) are shown in the figure.

[0130] In some embodiments, there is overlap between regions at different locations. The existence of overlap between regions at different locations means that there is overlapping data between regions at different locations. Also, there may be overlap in some or all three-dimensional directions. To reduce the computational complexity, the overlap between the "small error correction codes" of each layer is small in three-dimensional directions. In this way, increasing the number of layers of local "error correction" TIFF2025528263000141.tif5170. Setting overlap between regions at different positions can improve the decoding effect because the same information can be cross-validated after being acted on twice by LFEM, thereby improving decoding performance. However, excessive overlapping does not increase the computational complexity. Note that the parameters of the networks for different LFEMs are the same; only the input regions they act on are different.

[0131] In some embodiments, the target feature extraction sub-network includes at least one convolutional layer and at least one fully connected layer. The at least one convolutional layer is used to perform local feature extraction mapping on a plurality of input data blocks multiple times to obtain a plurality of sets of mapping output data. The at least one fully connected layer is used to obtain output data of the target feature extraction sub-network based on the plurality of sets of mapping output data.

[0132] The simplest method for constructing a feature extraction sub-network is to use a single-layer 3D CNN. However, the representation capability of this neural network is limited, and when the scale of the error-correcting code is large, it significantly affects the decoding performance. Therefore, it is necessary to ensure that the 3D CNN kernels are distributed over all input 3D information blocks (total After operating on the same region (5170 pixels) (dashed box with the same symbol in Figure 15), it is considered to connect to an FFN for further information integration and compression. This FFN may contain fully connected layers with different numbers of layers, and in practice the maximum number of layers can be limited to 2.

[0133] Regarding the overall parameter complexity analysis, when performing real-time decoding in hardware, the parameters must be set in advance in the computing device (such as FPGA or ASIC). The number of parameters determines the amount of on-chip memory that will ultimately be used. The number of parameters in each feature extraction sub-network is determined by its LFEM structure. Here, TIFF2025528263000143.tif4170The number of 3D CNN parameters in layers is TIFF2025528263000144.tif6170, where TIFF2025528263000145.tif5170 is the edge size of the maximum scale convolution kernel. The FFN parameter is The file is TIFF2025528263000146.tif5170. If the file is TIFF2025528263000147.tif5170, the total number of parameters in the front end is as follows: TIFF2025528263000148.tif16170

[0134] The number of backend parameters is TIFF2025528263000149.tif6170, and therefore the total number of parameters is The result is TIFF2025528263000150.tif6170. The constants hidden under TIFF2025528263000151.tif4170 are usually large, so If TIFF2025528263000152.tif4170 is small, the front end may actually occupy more parameters than the back end. Whether this asymptotic increase or the actual parameters of a real model obtained from testing is acceptable in practical engineering.

[0135] The depth (or computation time) of the entire algorithm is determined by how fast multiplication and addition can be performed. All multiplication operations in the 3D CNN and FFN parts of the feature extraction subnetwork (FFN layer count <= 2) are performed at the fastest speed. TIFF2025528263000153.tif5170 hours to complete, and the cumulative processing after multiplication requires TIFF2025528263000154.tif5170 steps are required, so the total computation time for a single feature extraction subnetwork is TIFF2025528263000155.tif5170. Total TIFF2025528263000156.tifThere are 5170 feature extraction sub-networks, so the total computation time (depth) of the front-end is The total computation time of the backend is fully parallelizable, and the TIFF2025528263000158.tif6170 feature decoding network scale is The number of layers is independent of TIFF2025528263000159.tif4170 TIFF2025528263000160.tif5170, and the multiplication calculation time is TIFF2025528263000161.tif5170, and the cumulative calculation time is TIFF2025528263000162.tif5170. Therefore, the depth of the entire algorithm is TIFF2025528263000163.tif5170. This algorithm time is the shortest computation time that can be theoretically achieved if the computational resources are sufficient.

[0136] Regarding the overall computational complexity analysis, the input 3D feature block of each layer is the output feature block of the previous layer. TIFF2025528263000164.tif5170, and the number of output feature blocks is Assume the file is TIFF2025528263000165.tif5170. TIFF2025528263000166.tif5170, and the input scale of each LFEM is TIFF2025528263000167.tif5170, then the number of LFEMs that need to act on this layer is TIFF2025528263000168.tif9170, where TIFF2025528263000169.tif5170 is the minimum convolution kernel for the entire network. The front-end multiplication complexity is: TIFF2025528263000170.tif16170

[0137] It is mainly a multiplication calculation, and the back-end multiplication calculation amount is TIFF2025528263000171.tif6170, so the computational complexity of the whole decoding process is TIFF2025528263000172.tif6170. Without multitask learning, the computational complexity of the entire decoding process is This increases to TIFF2025528263000173.tif6170, which is unacceptable in practical engineering.

[0138] Furthermore, there are various different types of activation layers in neural networks. For convenience of hardware implementation, this application uses two of them, namely, ReLU and LeakyReLU, where LeakyReLU is defined as follows: TIFF2025528263000174.tif9170

[0139] TIFF2025528263000175.tif4170 Select TIFF2025528263000176.tif4170, and TIFF2025528263000177.tif8170, TIFF2025528263000178.tif5170 represents the set of positive integers. By doing this, the activation layer calculation only requires determining the sign bit and right-shifting a limited number of bits, greatly simplifying the implementation. Simulation results have confirmed that LeakyReLU can achieve sufficiently good results.

[0140] In some embodiments, the training process for the neural network decoder is as follows.

[0141] 1. Obtain sample error syndrome information and sample error result information corresponding to the sample error syndrome information sample.

[0142] 2. The neural network decoder to be trained obtains the predicted decoding results corresponding to each of the n feature decoding networks based on the sample error syndrome information.

[0143] 3. Determine loss function values ​​corresponding to the n feature decoding networks, respectively, based on the predicted decoding results corresponding to the n feature decoding networks and the labeled decoding results corresponding to the n feature decoding networks, respectively, determined based on the sample error result information.

[0144] 4. Determine a total loss function value based on the loss function values ​​corresponding to the n feature decoding networks.

[0145] 5. Based on the total loss function value, the parameters of the neural network decoder to be trained are adjusted to obtain a trained neural network decoder.

[0146] After the model network structure is set, the model must be trained. Because multiple distribution functions need to be learned at the output terminal, training is performed using a cross entropy loss function on the output of the n feature decoding networks. Furthermore, when generating input-output training data, the input terminal is a randomly generated syndrome (which may be a single X or Z syndrome, or a combination of these two types of syndromes), and the output terminal is the output corresponding to the syndrome, using one-hot encoding. It should be noted that different outputs may correspond to inputs with the same syndrome. This diversity of output terminals ultimately allows the model to learn an output probability distribution based on a specific input syndrome during the training process.

[0147] For the i-th feature decoding network among the n feature decoding networks, a loss function value corresponding to the i-th feature decoding network is determined based on the predicted decoding result corresponding to the i-th feature decoding network and the labeled decoding result corresponding to the i-th feature decoding network determined based on the sample error result information. Here, the loss function value corresponding to the i-th feature decoding network is used to measure the similarity between the predicted decoding result corresponding to the i-th feature decoding network and the labeled decoding result corresponding to the i-th feature decoding network. The labeled decoding result corresponding to the i-th feature decoding network is the preset output label of the i-th feature decoding network, and can also be understood as the expected output result. The goal of training the i-th feature decoding network is to make its corresponding predicted decoding result match or approximate the labeled decoding result as closely as possible. For each feature decoding network among the n feature decoding networks, the loss function value corresponding to the feature decoding network can be determined using the above method.

[0148] After obtaining the loss function values ​​corresponding to the n feature decoding networks, the loss function values ​​corresponding to the n feature decoding networks can be weighted and added to obtain a total loss function value. The total loss function value is used to represent the performance of the entire neural network decoder. In addition, the weight values ​​corresponding to each feature decoding network can be the same or different, and the present application is not limited thereto.

[0149] Then, a gradient descent method is used to calculate a parameter adjustment gradient for the neural network decoder with the goal of minimizing the total loss function value, and parameters of the neural network decoder to be trained are adjusted based on the parameter adjustment gradient to obtain a trained neural network decoder, where the parameters of the neural network decoder include weight parameters of each neural network included in the neural network decoder.

[0150] When using error canonical decomposition as the output (first decomposition method), it is necessary to ensure a one-to-one correspondence between input and output in the training data, because one input syndrome can be used to estimate multiple output syndromes. In the case of TIFF2025528263000179.tif5170, the correlation between the inference syndromes is severed, so in this single-input, multi-output case, This is because it causes a local canonical syndrome inference discrepancy with a certain probability. Unlike noise inference occurring on physical bits, once a canonical syndrome inference discrepancy occurs, TIFF2025528263000181.tif5170 immediately causes a decoding failure with a certain probability. Generating training data directly from simulated data cannot guarantee a one-to-one correspondence between input and output. Therefore, when using canonical representation decomposition, a third-party decoder must be used to generate a one-to-one correspondence between input and output. A natural option is to use an MWPM decoder to generate a single output based on the syndromes generated in the simulation. If computational complexity is not a consideration, consider using a better, more complex known decoder. In this case, the two types of syndromes can be separated and used to decode the two types of errors (because these are the input / output patterns generated by MWPM), minimizing the increase in computational complexity while reducing overall computational complexity.

[0151] The second decomposition method directly uses the canonical representation of the original error data generated by simulation as the output label for multi-task training, while simultaneously using X- and Z-type syndromes as model inputs. This allows the same input syndrome to correspond to multiple output errors in the training set. This is because different results inferred based on the physical bit distribution will at most cause localized residual physical bit errors, not logical errors. Furthermore, by learning the physical error distribution in addition to maximum likelihood training, better decoding performance can be achieved.

[0152] In the actual training process, the classic Adam algorithm can be used for the two decomposition methods, and the batch size can be more than 1000. The loss function corresponding to the feature decoding network is TIFF2025528263000182.tif5170 (where i represents the ith feature decoding network and is a positive integer), then all loss functions can be added together to generate a total loss function: TIFF2025528263000183.tif12170

[0153] where: TIFF2025528263000184.tif4170 represents the total loss function of the neural network decoder, TIFF2025528263000185.tif5170 represents the loss function corresponding to the i-th feature decoding network, TIFF2025528263000186.tif5170 represents the weight value of the loss function corresponding to the i-th feature decoding network. Then, the loss function Gradient descent multi-task federated learning is performed on TIFF2025528263000187.tif4170. In practice, all TIFF2025528263000188.tif5170 can be set to 1, or of course it can be set to other values. In each training epoch, the learning rate can be gradually decreased, or it can be increased first and then decreased, depending on the actual situation.

[0154] In some embodiments, the division of blocks is related to correlation between errors, such that qubits included in the same block are prone to correlated errors.

[0155] Here, the fact that quantum bits included in the same block are more likely to cause related errors means that the probability of related errors occurring between quantum bits included in the same block is greater than the probability of related errors occurring between quantum bits included in different blocks.

[0156] For example, the probability of a correlated Pauli X or Z error occurring between qubits in the same block is greater than the probability of a correlated Pauli X or Z error occurring between qubits in different blocks.

[0157] As mentioned above, when using the second decomposition method, instead of training the model using indirect error data generated by another decoder, the original errors generated during the simulation process can be used. As mentioned above, to reduce the complexity of the error correction algorithm on a large scale, the physical qubits can be divided as follows: TIFF2025528263000189.tif5170

[0158] During multitask learning, Error affecting TIFF2025528263000190.tif5170 TIFF2025528263000191.tif6170 and Only consider TIFF2025528263000192.tif6170. Selecting TIFF2025528263000193.tif5170 has a significant impact on decoding performance because: While keeping the number of quantum bits contained in TIFF2025528263000194.tif5170 within a certain constant, This is because it is desirable for TIFF2025528263000195.tif5170 to cover as many local error correlations as possible. The most typical error correlations among these are those caused by the syndrome measurement circuit. As shown in Figure 16, typical correlation errors generated by the syndrome measurement circuit are two-body X-errors and Z-errors along the diagonal lines. In Figure 16, dotted frame 161 represents two-body X-errors, and dotted frame 162 represents two-body Z-errors. Therefore, the bit area When segmenting TIFF2025528263000196.tif4170, it is necessary to include as many of these diagonal distributions as possible for the two types of errors.

[0159] Figure 17 shows Qubit division method for Z errors in the case of TIFF2025528263000197.tif4170 TIFF2025528263000198.tif5170. In Figure 17, each small white circle represents a physical quantum bit, and the physical quantum bits connected by each thick black line belong to the same block. Looking at this scheme from bottom to top, The quantity of TIFF2025528263000199.tif5170 is TIFF2025528263000200.tif5170 Pauli errors in physical qubits TIFF2025528263000201.tif5170. For an X-type error, each divided subset of qubits must be rotated by 90 degrees.

[0160] By taking into account the correlation between errors when dividing the physical qubits of a quantum circuit into blocks, it becomes easier to generate correlated errors in qubits included in the same block, which helps to further improve decoding performance.

[0161] In some embodiments, during training of the neural network decoder, the qubits included in the sample quantum circuit are divided using a plurality of different block division schemes, and the neural network decoder is subjected to joint training based on the plurality of different block division schemes. During use of the neural network decoder, the qubits included in the quantum circuit are divided using one of the plurality of different block division schemes.

[0162] Considering the second type of decoder, after end-to-end training using the original errors generated during the simulation process, the so-called error floor phenomenon appears in the decoding effect in the range of low physical error rates, that is, at low physical error rates, the logical error decreases very slowly with the decrease in physical error, and the original decoding effect of the error-correcting code is lost.

[0163] This is because, when the physical error rate is sufficiently low, it is the higher-order related errors that play a dominant role. And these errors are Same area of ​​TIFF2025528263000202.tif5170 It is difficult to cover all the relationships in the TIFF2025528263000203.tif5170 simultaneously. Therefore, when decoding, the obtained marginal probabilities cannot cover all the relationships. It is necessary to keep the size of TIFF2025528263000204.tif5170 within a certain range and reduce the complexity of the output terminal. In reality, unless all physical bits are covered, The number of qubits included in TIFF2025528263000205.tif5170 is not necessarily better; what is more important is whether it can effectively encompass possible high-order related noise. To mitigate the impact of high-order related noise under this constraint, we employ multiple types of splitting and use a cross-validation method during training. The specific method is as follows:

[0164] Like below TIFF2025528263000206.tif4170 species division is considered. TIFF2025528263000207.tif37170

[0165] These divisions should yield maximum differentiation, while allowing for differences in associated noise. TIFF2025528263000208.tif4170 shows another division of the qubits, which differs from the division scheme in FIG. 17.

[0166] In the training phase, the backend of the decoding neural network is TIFF2025528263000209.tif7170 multi-task networks are simultaneously deployed. During the training phase, joint training is performed on the distributions of corresponding regions of these different partitions. Specifically, the total loss function needs to be redefined as follows: TIFF2025528263000210.tif12170

[0167] Moreover, it uses stochastic gradient descent for learning, which serves the purpose of cross-validation during the training phase, eliminating the influence of higher-order related errors as much as possible during the training phase. Once training is complete, only one of these splits, e.g., TIFF2025528263000211.tif7170 is used. By doing so, the complexity of the training increases, but the complexity and calculation time of the error correction algorithm itself do not change, and there is no impact on the actual decoding delay or implementation in engineering. As a result of simulation experiments, It has been shown that TIFF2025528263000212.tif4170 alone can largely eliminate the effects of higher-order related errors and significantly improve the logical error rate of error correction algorithms in low physical error rate areas.

[0168] In some embodiments, a chip implementing the neural network decoder described above may employ a single-core architecture or a multi-core architecture, where single-core and multi-core architecture refer to the number of processors (or processing cores, also called cores) included.

[0169] When a single-core architecture is adopted, the chip includes a single processor, which performs all steps of the neural network decoder described in the above embodiment. As mentioned above, the computational complexity of the decoding method provided in this application is TIFF2025528263000213.tif6170, and when L is small, a single-core architecture can tolerate this computational complexity, but when L is large, the single-core architecture has its limitations. Therefore, this application proposes a multi-architecture solution.

[0170] When a multi-core architecture is adopted, the chip includes multiple processors in a tree structure. In the embodiment of the present application, the number of processors included in the chip is not limited in the multi-core architecture. Specifically, the design can be made taking into account the size of L and the computational complexity, and the overall decoding algorithm can be performed on the premise that the computing power of each processor is fully utilized.

[0171] When a multi-core architecture is adopted, any two unconnected processors have parallelism, thereby maximizing the computing power of each processor and shortening the decoding time. Also, any two connected processors can execute sequentially. For example, FIG. 19 shows a schematic diagram of a multi-core architecture. Processors 1 through p may not be connected to each other, and these p processors can execute in parallel, for example, using a division and processing method to process different blocks of error syndrome information in parallel and / or using LFEM (Local Feature Extraction Mapping) to perform local feature extraction mapping on different input data blocks. The feature data extracted by processors 1 through p is sent to processor p+1, which processes the feature data provided by processors 1 through p to obtain feature information. The feature information is then input to processors p+2 through N, respectively. Processors p+2 through N may not be connected to each other, and the multiple processors can execute in parallel, with each processor implementing a feature decoding network to perform decoding on the feature information and obtain corresponding decoding results. Finally, a processor can determine error result information based on the decoding results corresponding to each feature decoding network.

[0172] For multiple processors that run in parallel, the information to be processed can be sent to each processor simultaneously, allowing the multiple processors to execute in parallel. For example, for processor 1 through processor p in the above example, different blocks of error syndrome information can be sent to each processor simultaneously, thereby allowing the p processors to execute in parallel. In another example, for processor p+2 through processor N in the above example, feature information can be sent to each processor simultaneously, thereby allowing the multiple processors to execute in parallel. In some other embodiments, a single controller or processor can be installed to control the execution sequence of each processor. For example, by controlling multiple parallel processors to start execution simultaneously or controlling serial processors to process in sequence, the operations of each processor can be more appropriately coordinated and the accuracy and stability of the processing flow can be ensured.

[0173] The neural network decoder based on multitask learning provided in this application has inherent parallelism, whether it is the feature extraction part or the feature decoding part, so it can be easily distributed and executed on multiple different processors. In addition, the inputs of different processors are almost independent, so communication between processors is almost unnecessary, and communication for data transmission is only performed between a small number of processors. In principle, this method can be parallelized infinitely, and when each processor is fully utilized, the calculation scale can be expanded by always adding processors, The decoding delay of TIFF2025528263000214.tif5170 can be maintained.

[0174] Simulation experiments have shown that the technical solutions provided in this application can bring several improvements, such as:

[0175] 1. Reduce the number of models and make it easier to implement hardware systems Regardless of the scale of the error-correcting code, two models are used: one that outputs X-type errors and one that outputs Z-type errors. Considering the computational capabilities of current FPGAs, we first focus on the first type of decoder (output-end error canonical decomposition). As shown in the simulation results in Figure 20, after training using indirect training data generated by MWPM, the decoding performance for different output canonical syndrome sizes is shown. In this case, we can see that the decoding performance is almost independent of the output canonical syndrome size. Furthermore, even when using only two models, the decoding performance is almost comparable to that trained with the MWPM decoder, especially in the case of low physical error rates. This indicates that the shared front-end of the multi-task learning decoder proposed in this application can reliably capture all the feature information required for high-performance decoding.

[0176] Regarding the performance of the actual hardware implementation, TIFF2025528263000215.tif4170 (49 data bits and auxiliary bits in total), and we conducted 10 syndrome measurements. We considered dividing the output terminal into three outputs, each TIFF2025528263000216.tif7170 and two canonical syndromes containing 12 bits of information each TIFF2025528263000217.tif7170, The model corresponds to TIFF2025528263000218.tif7170. The corresponding model uses 330,000 parameters. After 8-bit unsigned quantization (UINT8) of this model, the two networks are implemented on two Intel Stratix 10 SX FPGAs. As shown in Figure 21, 201 and 202 in the figure represent the two Intel Stratix 10 SX FPGAs, which are used to decode X-type errors and Z-type errors, respectively.

[0177] To simulate the entire decoding process, we simulated quantum noise generation and the execution of a noise-infused syndrome measurement circuit on the computer side. After performing 10 syndrome measurements, the resulting syndrome (120 classical bits) was divided into X-type and Z-type syndromes (60 each) and sent to two FPGAs via different ports on the network. After the FPGA completed the decoding, it sent the error information obtained by the decoding to the computer side to determine whether the decoding was successful. After extensive Monte Carlo simulations, the FPGA decoding performance was shown in Figure 22, with an overall decoding latency of 700 ns. When using the higher-performance Intel Stratix 10 SX and decoding was initiated upon receiving a partial syndrome, the total time from receiving the syndrome to completing the entire decoding process was 280 ns, achieving the fastest time ever for 49-bit hardware decoding.

[0178] 2. Significant improvement in decoding performance Using the second type of decoder, the decoding performance can be significantly improved by using the following method.

[0179] (1) Second type error decomposition (2) Two types of syndromes are used simultaneously as the decoding output. (3) Dividing the output area into parts that take into account the occurrence patterns of related errors (4) Federated learning and cross-validation in the training phase using multiple different partitioning methods The decoder provided in this application can significantly improve the actual decoding performance with low computational complexity, network complexity, and computation depth.

[0180] Figure 23 shows TIFF2025528263000219.tif4170 and The case of TIFF2025528263000220.tif4170 (corresponding to 49 and 97 physical bits, respectively, including data bits and auxiliary bits) is shown. As can be seen from the figure, the second type decoder shows better decoding performance than MWPM in all physical error regions, and its logical error rate is less than half that of MWPM. This is one of the best fault-tolerant decoders currently known.

[0181] The following are examples of apparatuses of the present application that can be used to perform the method embodiments of the present application. For details not disclosed in the apparatus embodiments of the present application, please refer to the method embodiments of the present application.

[0182] 24 is a block diagram of a neural network-based quantum error correction decoding device according to one embodiment of the present application. The device has functions for implementing the above-described exemplary method, which can be implemented in hardware or by executing corresponding software by hardware. The device may be a computer device or may be located in a computer device. The device 2400 may include a syndrome acquisition module 2410, a feature extraction module 2420, a feature decoding module 2430, and a result determination module 2440.

[0183] The syndrome acquisition module 2410 is configured to acquire error syndrome information obtained by performing syndrome measurements on the quantum circuit.

[0184] The feature extraction module 2420 is configured to extract feature information from the error syndrome information using a neural network decoder, where the neural network decoder includes the feature extraction network and n feature decoding networks, where n is an integer greater than 1.

[0185] The feature decoding module 2430 is configured to perform a decoding process on the feature information by the neural network decoder to obtain a decoding result.

[0186] The result determination module 2440 is configured to determine error result information of the quantum circuit based on the decoding result.

[0187] In some embodiments, the feature extraction module 2420 is configured to perform feature extraction on the error syndrome information via a feature extraction network of a neural network decoder to obtain feature information, where the neural network decoder includes the feature extraction network and n feature decoding networks, where n is an integer greater than 1.

[0188] The feature decoding module 2430 is configured to perform decoding processing on the feature information through the n feature decoding networks respectively, and obtain decoding results corresponding to the n feature decoding networks respectively, where the n feature decoding networks are networks trained in a multi-task learning manner so as to have the ability to generate different decoding results.

[0189] The result determination module 2440 is configured to determine error result information based on the decoding results corresponding to the n feature decoding networks, respectively.

[0190] In some embodiments, the qubits included in the quantum circuit are divided into n blocks, each block including at least one qubit, and for a kth feature decoding network among the n feature decoding networks, a decoding result corresponding to the kth feature decoding network includes a Pauli operator acting on the qubits included in the kth block among the n blocks, where k is a positive integer less than or equal to n.

[0191] The result determination module 2440 is configured to determine the error result information based on a Pauli operator acting on each of the n blocks.

[0192] In some embodiments, the error result information indicates qubits in the quantum circuit in which a Pauli X error has occurred and qubits in which a Pauli Z error has occurred.

[0193] In some embodiments, the division of the blocks is related to correlation between errors, such that qubits included in the same block are prone to correlated errors.

[0194] In some embodiments, during the training of the neural network decoder, the qubits included in the sample quantum circuit are divided using a plurality of different block division schemes, and joint training is performed on the neural network decoder based on the plurality of different block division schemes. During the use of the neural network decoder, the qubits included in the quantum circuit are divided using one of the plurality of different block division schemes.

[0195] In some embodiments, the feature decoding module 2430 comprises: performing a decoding process on the feature information using n1 feature decoding networks respectively to obtain decoding results corresponding to the n1 feature decoding networks respectively, and for an i-th feature decoding network among the n1 feature decoding networks, the decoding result corresponding to the i-th feature decoding network includes an i-th term canonical syndrome associated with a target error type, where i is a positive integer not greater than n1, and the canonical syndrome refers to a canonical decomposition result of the error syndrome information; The feature information is decoded by n2 feature decoding networks, respectively, to obtain decoding results corresponding to the n2 feature decoding networks, where for a j-th feature decoding network among the n2 feature decoding networks, the decoding result corresponding to the j-th feature decoding network includes a fixed representative element associated with the target error type, where j is a positive integer not greater than n2; Here, the sum of n1 and n2 is equal to n, and n1 and n2 are positive integers.

[0196] In some embodiments, the target error types include Pauli X errors and Pauli Z errors, n1 is equal to the sum of m1 and m2, m1 and m2 are positive integers, and n2 is 2; m feature decoding networks among the n feature decoding networks are used to perform decoding processing on the feature information, respectively, to obtain m canonical syndromes related to the Pauli X-errors; m feature decoding networks among the n feature decoding networks are used to perform decoding processing on the feature information, respectively, to obtain m canonical syndromes associated with the Pauli Z errors; One feature decoding network among the n feature decoding networks is used to perform a decoding process on the feature information to obtain a fixed representative element associated with the Pauli X error; Another feature decoding network among the n feature decoding networks is used to perform a decoding process on the feature information to obtain a fixed representative element associated with the Pauli Z error; The outcome determination module 2440: determining X-type error result information based on a fixed representative element associated with the Pauli X error and an m1-term canonical syndrome associated with the Pauli X error, the X-type error result information indicating a qubit in the quantum circuit at which the Pauli X error occurred; The method is configured to determine Z-type error result information based on a fixed representative element associated with the Pauli-Z error and an m-term canonical syndrome associated with the Pauli-Z error, the Z-type error result information indicating a quantum bit in the quantum circuit at which the Pauli-Z error occurred.

[0197] In some embodiments, the feature extraction network comprises a plurality of cascaded feature extraction sub-networks, wherein input data of a first feature extraction sub-network comprises the error syndrome information, input data of an s-th feature extraction sub-network comprises output data of an s-1-th feature extraction sub-network, and output data of a last feature extraction sub-network comprises the feature information, where s is an integer greater than 1; For a target feature extraction sub-network among the plurality of cascaded feature extraction sub-networks, input data of the target feature extraction sub-network is divided into a plurality of input data blocks having the same scale; the target feature extraction sub-network is used to perform local feature extraction mapping on the plurality of input data blocks a plurality of times to obtain a plurality of sets of mapping output data, wherein each local feature extraction mapping is used to perform mapping processing on regions at the same positions in the plurality of input data blocks to obtain a set of mapping output data, and different local feature extraction mappings are used to perform mapping processing on regions at different positions in the plurality of input data blocks to obtain the plurality of sets of mapping output data; The target feature extraction sub-network is further used to obtain output data of the target feature extraction sub-network based on the sets of mapping output data.

[0198] In some embodiments, there is an overlap between the differently positioned regions.

[0199] In some embodiments, the target feature extraction sub-network includes at least one convolutional layer and at least one fully connected layer; the at least one convolutional layer is used to perform the local feature extraction mapping multiple times on the multiple input data blocks to obtain the multiple sets of mapping output data; The at least one fully connected layer is used to obtain output data of the target feature extraction sub-network based on the sets of mapping output data.

[0200] In some embodiments, the neural network decoder performs a measurement collection process for new error syndrome information in parallel with the process of decoding the error syndrome information already obtained.

[0201] In some embodiments, the neural network decoder training process comprises: Obtaining sample error syndrome information and sample error result information corresponding to the sample error syndrome information samples; Obtaining predictive decoding results corresponding to the n feature decoding networks respectively based on the sample error syndrome information by the neural network decoder to be trained; determining loss function values ​​corresponding to the n feature decoding networks, respectively, based on predicted decoding results corresponding to the n feature decoding networks, and labeled decoding results corresponding to the n feature decoding networks, respectively, determined based on the sample error result information; determining a total loss function value based on loss function values ​​corresponding to each of the n feature decoding networks; and adjusting parameters of the neural network decoder to be trained based on the total loss function value to obtain the neural network decoder after training.

[0202] In some embodiments, the feature extraction network and the n feature decoding networks included in the neural network decoder are located on the same chip.

[0203] In some embodiments, the chip on which the neural network decoder is implemented includes a plurality of processors in a tree structure, and any two processors that do not have a connection relationship have parallelism.

[0204] It should be noted that the division of the above functional modules into which the functions of the device provided in the above embodiments are realized is merely an illustrative example, and in actual applications, the above functions can be assigned to different functional modules as needed, that is, all or part of the above-described functions can be achieved by dividing the internal structure of the device into different functional modules. Furthermore, the device provided in the above embodiments belongs to the same concept as the method embodiments, and the specific implementation process thereof can be referred to the method embodiments, and will not be repeated here.

[0205] Referring to Figure 25, Figure 25 is a schematic diagram showing the structure of a computer device according to an embodiment of the present application. The computer device can be the control device 43 in the application scenario of the configuration shown in Figure 4. The computer device can be used to implement the quantum error correction decoding method based on a neural network according to the above embodiment. Specifically, it is as follows.

[0206] The computing device 2500 includes a processing unit 2501 (e.g., including a CPU and / or GPU), a system memory 2504 including random access memory (RAM) 2502 and read-only memory (ROM) 2503, and a system bus 2505 connecting the system memory 2504 and the processing unit 2501. The computing device 2500 further includes a basic input / output system (I / O system: Input / Output) 2506 that facilitates the transfer of information between devices within the computing device, and a mass storage device 2507 that stores an operating system 2513, applications 2514, and other program modules 2515.

[0207] The basic input / output system 2506 includes a display 2508 for displaying information and input devices 2509, such as a mouse and a keyboard, for a user to input information. Both the display 2508 and the input devices 2509 are connected to the processing unit 2501 via an input / output controller 2510 connected to the system bus 2505. The basic input / output system 2506 may further include an input / output controller 2510 for receiving and processing input from a number of other devices, such as a keyboard, a mouse, or an electronic stylus.

[0208] The mass storage device 2507 is connected to the processing unit 2501 via a mass storage controller (not shown) connected to the system bus 2505. The mass storage device 2507 and its associated computer device-readable media provide non-volatile storage for the computer device 2500. That is, the mass storage device 2507 may include a computer-readable medium (not shown), such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0209] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include RAM, ROM, EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other solid-state storage device technology, CD-ROM, DVD (Digital Video Disc) or other optical storage, magnetic tape cartridge, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer equipment is not limited to those described above. The system memory 2504 and mass storage device 2507 described above may be collectively referred to as memory.

[0210] According to various embodiments of the present application, the computing device 2500 may also be implemented via a network, such as the Internet, in connection with a remote computing device connected to the network, i.e., the computing device 2500 may be connected to a network 2512 via a network interface unit 2511 connected to the system bus 2505, or may use the network interface unit 2511 to connect to another type of network or remote computer system (not shown).

[0211] The memory stores a computer program that causes one or more processors to execute the neural network-based quantum error correction decoding method according to the above embodiment.

[0212] In an exemplary embodiment, a computer-readable storage medium having a computer program stored thereon is further provided, the computer program causing a processor of a computer device to execute the neural network-based quantum error correction decoding method according to the above embodiment. In an exemplary embodiment, the computer-readable storage medium may be a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0213] An exemplary embodiment further provides a computer program product, which, when executed by the chip, is used to realize the neural network-based quantum error correction decoding method according to the above embodiment.

[0214] In an exemplary embodiment, a chip is further provided, the chip including a programmable logic circuit and / or program instructions, the chip causing a computing device to perform the neural network based quantum error correction decoding method according to the above embodiment.

[0215] Optionally, the chip is an FPGA chip or an ASIC chip.

Claims

1. A neural network-based quantum error correction decoding method executed by a control device, comprising: acquiring error syndrome information obtained by performing syndrome measurement on the quantum circuit; extracting feature information from the error syndrome information using a neural network decoder; performing a decoding process on the feature information by the neural network decoder to obtain a decoding result; and determining error result information of the quantum circuit based on the decoding result.

2. The step of extracting feature information from the error syndrome information using the neural network decoder includes: performing feature extraction on the error syndrome information by a feature extraction network of the neural network decoder to obtain feature information, wherein the neural network decoder includes the feature extraction network and n feature decoding networks, where n is an integer greater than 1; The step of performing a decoding process on the feature information by the neural network decoder to obtain a decoding result includes: The method includes a step of performing a decoding process on the feature information by the n feature decoding networks respectively, and obtaining decoding results corresponding to the n feature decoding networks respectively, wherein the n feature decoding networks are networks trained in a multi-task learning manner so as to have the ability to generate different decoding results; The step of determining error result information of the quantum circuit based on the decoding result includes: determining the error result information based on decoding results corresponding to the n feature decoding networks, 2. The quantum error correction decoding method of claim 1.

3. The quantum bits included in the quantum circuit are divided into n blocks, each block including at least one quantum bit; For a k-th feature decoding network among the n feature decoding networks, a decoding result corresponding to the k-th feature decoding network includes a Pauli operator acting on a quantum bit included in a k-th block among the n blocks, where k is a positive integer equal to or less than n; The step of determining the error result information based on the decoding results corresponding to the n feature decoding networks, respectively, comprises: determining the error result information based on a Pauli operator acting on each of the n blocks; 3. The quantum error correction decoding method according to claim 2.

4. The error result information indicates a quantum bit in which a Pauli X error has occurred and a quantum bit in which a Pauli Z error has occurred in the quantum circuit.

4. The quantum error correction decoding method according to claim 3.

5. The division of the blocks is related to correlation between errors, and the probability that correlated errors occur between quantum bits included in the same block is greater than the probability that correlated errors occur between quantum bits included in different blocks.

5. The quantum error correction decoding method according to claim 3 or 4.

6. During the training of the neural network decoder, a plurality of different block division schemes are used to divide the qubits included in the sample quantum circuit, and joint training is performed on the neural network decoder based on the plurality of different block division schemes; During use of the neural network decoder, the quantum bits included in the quantum circuit are divided using one of the plurality of different block division schemes. The quantum error correction decoding method according to any one of claims 3 to 5.

7. The step of performing a decoding process on the feature information by the n feature decoding networks, respectively, and obtaining decoding results corresponding to the n feature decoding networks, respectively, comprises: n １ The feature information is decoded by each of the n feature decoding networks, １ obtaining decoding results corresponding to the n feature decoding networks, １ For an ith feature decoding network among the feature decoding networks, the decoding result corresponding to the ith feature decoding network includes an ith term of canonical syndromes associated with a target error type, where i is n １ is a positive integer less than or equal to , and the canonical syndrome refers to a canonical decomposition result of the error syndrome information; n ２ The feature information is decoded by each of the n feature decoding networks, ２ obtaining decoding results corresponding to the n feature decoding networks, ２ For a j-th feature decoding network among the feature decoding networks, the decoding result corresponding to the j-th feature decoding network includes a fixed representative element associated with the target error type, and j is n ２ and a step, n １ and ２ The sum of is equal to n, １ and ２ is a positive integer, The quantum error correction decoding method according to any one of claims 2 to 6.

8. The target error types include Pauli X errors and Pauli Z errors, １ is m １ and m ２ is equal to the sum of m １ and m ２ is a positive integer, and n ２ is 2, The n １ m of the feature decoding networks １ The feature decoding networks each perform a decoding process on the feature information, and １ is used to obtain the canonical syndrome of the term, The n １ m of the feature decoding networks ２ The feature decoding networks each perform a decoding process on the feature information, and ２ is used to obtain the canonical syndrome of the term, The n ２ one of the feature decoding networks is used to perform a decoding process on the feature information to obtain a fixed representative element associated with the Pauli X error; The n ２ another feature decoding network among the feature decoding networks is used to perform a decoding process on the feature information to obtain a fixed representative element associated with the Pauli-Z error; The step of determining the error result information based on the decoding results corresponding to the n feature decoding networks, respectively, comprises: a fixed representative element associated with the Pauli X error, and m １ determining X-type error result information based on a canonical syndrome of terms, the X-type error result information indicating a qubit in the quantum circuit at which the Pauli X error occurred; a fixed representative element associated with the Pauli Z error, and m ２ determining Z-type error result information based on a canonical syndrome of terms, the Z-type error result information indicating a qubit in the quantum circuit at which the Pauli Z error occurred; 8. The quantum error correction decoding method according to claim 7.

9. the feature extraction network includes a plurality of cascaded feature extraction sub-networks, wherein input data of a first feature extraction sub-network includes the error syndrome information, input data of an s-th feature extraction sub-network includes output data of an s-1-th feature extraction sub-network, and output data of a last feature extraction sub-network includes the feature information, where s is an integer greater than 1; For a target feature extraction sub-network among the plurality of cascaded feature extraction sub-networks, input data of the target feature extraction sub-network is divided into a plurality of input data blocks having the same scale; the target feature extraction sub-network is used to perform local feature extraction mapping on the plurality of input data blocks a plurality of times to obtain a plurality of sets of mapping output data, each local feature extraction mapping being used to perform mapping processing on regions at the same positions in the plurality of input data blocks to obtain a set of mapping output data, and each local feature extraction mapping being used to perform mapping processing on regions at different positions in the plurality of input data blocks a different number of times to obtain the plurality of sets of mapping output data; the target feature extraction sub-network is further used to obtain output data of the target feature extraction sub-network based on the plurality of sets of mapping output data. The quantum error correction decoding method according to any one of claims 2 to 7.

10. There is an overlap between the regions at different locations.

10. The quantum error correction decoding method according to claim 9.

11. the target feature extraction sub-network includes at least one convolutional layer and at least one fully connected layer; the at least one convolutional layer is used to perform the local feature extraction mapping multiple times on the multiple input data blocks to obtain the multiple sets of mapping output data; the at least one fully connected layer is used to obtain output data of the target feature extraction sub-network based on the plurality of sets of mapping output data; 11. The quantum error correction decoding method according to claim 9 or 10.

12. The neural network decoder performs a process of measuring and collecting new error syndrome information in parallel with the process of decoding the error syndrome information already acquired. The quantum error correction decoding method according to any one of claims 1 to 11.

13. The training process of the neural network decoder is as follows: Obtaining sample error syndrome information and sample error result information corresponding to the sample error syndrome information samples; Obtaining predictive decoding results corresponding to the n feature decoding networks respectively based on the sample error syndrome information by the neural network decoder to be trained; determining loss function values ​​corresponding to the n feature decoding networks, respectively, based on predicted decoding results corresponding to the n feature decoding networks, and labeled decoding results corresponding to the n feature decoding networks, respectively, determined based on the sample error result information; determining a total loss function value based on loss function values ​​corresponding to each of the n feature decoding networks; and adjusting parameters of the neural network decoder to be trained based on the total loss function value to obtain the neural network decoder after training. The quantum error correction decoding method according to any one of claims 2 to 12.

14. The feature extraction network and the n feature decoding networks included in the neural network decoder are arranged on the same chip. The quantum error correction decoding method according to any one of claims 2 to 13.

15. The chip on which the neural network decoder is arranged includes a plurality of processors in a tree structure, and any two processors that do not have a connection relationship have parallelism. The quantum error correction decoding method according to any one of claims 1 to 14.

16. A neural network-based quantum error correction decoding device, comprising: a syndrome acquisition module configured to acquire error syndrome information obtained by performing syndrome measurement on the quantum circuit; a feature extraction module configured to extract feature information from the error syndrome information using a neural network decoder, the neural network decoder including the feature extraction network and n feature decoding networks, n being an integer greater than 1; a feature decoding module configured to perform a decoding process on the feature information using the neural network decoder to obtain a decoding result; a result determination module configured to determine error result information of the quantum circuit based on the decoding result.

17. A computer device comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to realize the quantum error correction decoding method according to any one of claims 1 to 15. The computer device.

18. A computer-readable storage medium on which a computer program is stored, the computer program being loaded and executed by a processor to realize the quantum error correction decoding method according to any one of claims 1 to 15. A computer-readable storage medium.

19. A computer program product including a computer program, wherein the computer program is loaded and executed by a processor to realize the quantum error correction decoding method according to any one of claims 1 to 15. A computer program product.

20. A chip on which a neural network decoder is arranged, the neural network decoder being used to realize the quantum error correction decoding method according to any one of claims 1 to 15.

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