Photodiode with high power conversion efficiency and positive temperature coefficient

Abstract

The present disclosure provides techniques related to the fabrication and application of power photodiode structures and devices based on III-metal nitride substrates and gallium-based substrates. More specifically, embodiments of the present disclosure include techniques for fabricating photodiode devices, structures, and devices that include one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN. Such structures or devices can be used in a variety of applications, including optoelectronic devices, photodiodes, power-over-fiber receivers, and the like.

Description

Description of Related Applications

[0001] This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 356,231, filed June 28, 2022, and U.S. Provisional Patent Application No. 63 / 500,862, filed May 8, 2023, each of which is incorporated herein by reference. [Technical Field]

[0002] The present disclosure relates generally to nitride-based photodiodes for converting optical energy into electrical energy, particularly at high optical and current densities, and methods of fabrication. The present disclosure is particularly applicable to applications involving the conversion of optical energy into electrical energy by optical fibers, other optoelectronic devices, and similar products. [Background technology]

[0003] Electrical power is typically transmitted through electrical wires, e.g., conductors. However, such wires can be heavy, cumbersome, and expensive, and the transmitted power can be subject to electromagnetic interference. Some of these limitations can be overcome by transmitting power through optical fibers. Unfortunately, with current conventional designs, such an approach is not yet commercially viable. In addition, current approaches generally involve light in infrared wavelengths, which have certain drawbacks relative to visible light and visible light radiation, such as greater sensitivity to temperature changes in the surrounding environment.

[0004] Gallium nitride (GaN)-based optoelectronic and electronic devices are of great commercial importance. The most advanced of these devices are light-emitting diodes (LEDs) and laser diodes, with GaN-based power diodes and transistors becoming increasingly important. New applications are also of interest. De Santi and co-authors [1] described an application in which electrical power is converted to optical power using a laser diode, coupled into an optical fiber for transmission to a remote location, and then converted back to electrical power using a photodiode. Both the laser diode and the photodiode were GaN-on-sapphire devices, and system performance was relatively low. The photodiode is particularly challenging, with a reported efficiency of 17%. GaN-based solar cells have also been reported by many groups, typically utilizing GaN-on-sapphire structures for low-power (single-solar) applications. Even concentrator solar cell structures known in the art for other material systems can only produce significantly lower current densities than those that are the focus of this invention.

[0005] Related applications have been disclosed using GaAs-based lasers and photodiodes at near-infrared wavelengths. However, due to their larger band gap, nitride-based photodiodes should be able to achieve significantly higher open-circuit voltages and superior efficiency at higher temperatures and higher input power levels than corresponding GaAs-based devices and systems.

[0006] Currently, Cardwell and D'Evelyn [Patent Documents 1 and 2] have disclosed numerous embodiments of nitride-based photodiode structures, devices, and optics. The performance of nitride photodiodes with indium gallium nitride (InGaN) absorber layers can suffer from the generation of strain-induced defects, especially when the absorber layer is relatively thick or has a relatively high In concentration. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0020798 [Patent Document 2] US Patent Application Publication No. 2021 / 0167231 [Non-patent literature]

[0008] [Non-Patent Document 1] Materials 11, 153 (2018) Summary of the Invention [Problem to be solved by the invention]

[0009] Such defects can reduce the external quantum efficiency, fill factor, and open circuit voltage of a photodiode. Under monochromatic illumination, the power conversion efficiency (PCE) is proportional to the zero-bias external quantum efficiency (EQE), fill factor (FF), and open circuit voltage (V). oc / hν(where, V oc It can be expressed as the product of (where ν is the open circuit voltage, e is the electron charge, and hν is the photon energy). Further improvements are highly desirable. [Means for solving the problem]

[0010] In one example, the present invention provides a photodiode device. The photodiode device includes a gallium-nitrogen-containing substrate member having a back surface and a top surface. The device includes an N-type gallium-nitrogen-containing material with a silicon dopant overlying the top surface, the N-type gallium-nitrogen-containing material configured as a buffer material. In one example, the buffer material has a thickness ranging from about 0.5 micrometers to 1.5 micrometers. The device includes a superlattice (SL) indium-gallium-nitrogen-containing material overlying the N-type gallium-nitrogen-containing material. The superlattice includes multiple indium-gallium-nitrogen-containing material layers and gallium-nitrogen-containing material layers. The superlattice is a periodic structure having 25 to 80 indium-gallium-nitrogen-containing material layers and gallium-nitrogen-containing material layers. The device includes a bottom barrier (LB) indium-gallium-nitrogen-containing material overlying the SL indium-gallium-nitrogen-containing material. The indium concentration of the LB material ranges from 0 to 4 percent. The thickness of the LB material ranges from 6 to 14 nanometers. In one example, the device has a plurality of quantum well regions spanning 30 to 50 quantum wells above an indium-gallium-nitrogen-containing material. Each quantum well has an indium gallium nitride material having a thickness of 2.0 to 4.0 nanometers and an indium concentration ranging from 10 to 14 percent, and a gallium nitride material having a thickness of 1.0 to 2.5 nanometers. In one example, the plurality of quantum well regions are undoped. The device has an upper barrier layer above the plurality of quantum well regions, comprising an indium gallium-nitrogen-containing material. The indium gallium nitride in the upper barrier layer has a concentration ranging from 0 to 4 percent and a thickness ranging from 4 to 10 nanometers. In one example, the upper barrier material is undoped. The device has an upper cladding layer above the upper barrier layer, comprising a gallium-nitrogen-containing material. The gallium-nitrogen-containing material in the upper cladding layer has a concentration ranging from 8×10 19 atoms / cm 3 From 6 x 10 20 atoms / cm 3and a thickness of 16 nanometers to 24 nanometers. The device has a P-type gallium-nitrogen-containing material over an indium-gallium-nitrogen-containing material in an upper cladding layer. The P-type material is a cap material. Illustratively, the device has a P-type contact comprising a gallium-nitrogen material with a magnesium dopant material. Illustratively, the P-type contact is in electrical and physical contact with the P-type gallium-nitrogen-containing material.

[0011] In one example, the present invention provides a photodiode device. The device includes a gallium-nitrogen-containing substrate member having a back surface and a top surface. The device includes an absorber layer including a plurality of quantum well regions overlying the top surface. The device includes a plurality of hexagonal pyramid structures spatially arranged along the back surface. In one example, each of the hexagonal pyramid structures has a height ranging from about 0.3 micrometers to about 30 micrometers and a base ranging from about 0.3 micrometers to about 30 micrometers. In one example, each of the hexagonal pyramid structures extends from a crystalline structure of the gallium-nitrogen-containing substrate member and has a size irregularity ranging from 0% to 50%, although other irregularities are possible. In one example, the device includes an interior region (typically planar) disposed between pairs of the plurality of hexagonal pyramid structures. The device has a plurality of nanodots spatially arranged over the interior region and over the surface region of each of the hexagonal pyramidal structures, the nanodots configured to direct electromagnetic radiation having a wavelength ranging from 360 to 500 nanometers toward the absorber layer to increase absorption of the radiation in the absorber layer, thereby coupling additional radiation into the absorber layer.

[0012] 1 W / cm at one or more wavelengths between 360 nm and 500 nm 2 Disclosed herein are nitride photodiodes having a positive fill factor temperature coefficient in one or more temperature intervals above -50°C, a fill factor of greater than 70% at one or more temperatures above -50°C, and a power conversion efficiency of greater than 40% at one or more temperatures above -50°C when irradiated with a power density of greater than 1000 kJ / s. [Brief explanation of the drawings]

[0013] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments thereof, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and are therefore not to be considered limiting of the scope thereof, as other equally effective embodiments may be recognized. [Figure 1] 1 is a simplified diagram illustrating illumination current versus voltage curves for a photodiode device according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a simplified diagram illustrating a nitride-based power photodiode structure prepared according to an embodiment of the present disclosure. [Figure 3] 1 is a simplified diagram illustrating a light trapping structure fabricated on a photodiode device according to an embodiment of the present disclosure. [Figure 4] 1 is a simplified diagram illustrating a simple optical resonator that can be used with nitride-based power photodiodes, according to an embodiment of the present disclosure. [Figure 5] Scanning electron micrograph of a textured region on the backside of a nitride-based power photodiode structure prepared according to embodiments of the present disclosure. [Figure 6] 1 is a simplified diagram illustrating illumination current versus voltage behavior of a photodiode according to an embodiment of the present disclosure. [Figure 7] FIG. 1 is a simplified diagram illustrating a process flow for forming nanostructures on the backside of a nitride-based power photodiode structure according to an embodiment of the present disclosure. [Figure 8] Scanning electron micrograph of the nanostructure of the textured region on the backside of a nitride-based power photodiode structure prepared according to embodiments of the present disclosure. [Figure 9] FIG. 1 is a simplified diagram illustrating a fiber illumination current-voltage test setup that can be used to measure the illumination current-voltage curve of a nitride photodiode chip, according to an embodiment of the present disclosure. [Figure 10A]1 is a simplified diagram illustrating a measured illumination current versus voltage curve as a function of stage current, according to an embodiment of the present disclosure. [Figure 10B] FIG. 10B is a simplified diagram illustrating an expanded portion of the illumination current versus voltage curve shown in FIG. 10A, according to an embodiment of the present disclosure. [Figure 11] FIG. 1 is a simplified diagram illustrating fill factor (FF), zero-bias external quantum efficiency (EQE), power conversion efficiency (PCE), and (eVoc / hν) as a function of stage current, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] To facilitate understanding, the same reference numerals have been used, wherever possible, to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0015] The present disclosure provides techniques related to the fabrication and application of power photodiode structures and devices based on III-metal nitride substrates and gallium-based substrates. More particularly, embodiments of the present disclosure include techniques for fabricating photodiode devices, structures, and devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN. Certain aspects of the present invention may also extend to other material systems. Such structures or devices may be used in a variety of applications, including optoelectronic devices, photodiodes, power-over-fiber receivers, and the like.

[0016] As mentioned earlier, lasers and photodiodes have been successfully developed in the GaAs material system. One key difference in material properties between arsenide and nitride systems is that the bandgap can be easily varied with minimal effect on the lattice constant when using arsenides, e.g., AlGaAs, while this is not the case for nitrides. Conventional photodiode packaging structures incorporating nitride absorber layers can require absorber layer thicknesses on the order of hundreds of nanometers to absorb most of the incident light. The absorption coefficient of the absorber layer can be increased to 1×10 5 cm -1 Assuming this, the light absorption in a single pass is approximately 39%, 63%, 87%, 95%, and 98% for thicknesses of 50, 100, 200, 300, and 400 nm, respectively. In the case of nitrides, such thicknesses of InGaN, which have enough indium (In) to efficiently absorb blue and violet light, may be too strained to avoid relaxation due to dislocation generation and crack formation, resulting in poor electrical performance of the resulting device. Cardwell and D'Evelyn [Patent Documents 1 and 2] disclosed a technique to circumvent this problem, which involves delivering electromagnetic radiation along a long optical path through the optical absorber layer to achieve near-100% optical absorption, even when a power photodiode structure is provided that includes a relatively thin absorber layer. This technique also has the additional advantages of excellent heat dissipation, zero or very low grid shadow losses, and a long effective minority carrier lifetime. Here, the effective minority carrier lifetime includes photon recycling, which is defined as the reabsorption of photons emitted by the absorber layer. The terms "light" and "optical radiation" are often used interchangeably herein, and both are intended to generally refer to electromagnetic radiation of one or more wavelengths, unless the context of the discussion dictates otherwise.

[0017] Many of the embodiments disclosed by Cardwell and D'Evelyn [Patent Documents 1 and 2] utilize multiple optical passes through the device layers via an optical cavity to achieve the desired power conversion efficiency (PCE). The inventors have discovered that a subset of these structures, along with numerous additions, modifications, and / or improvements, provide excellent PCE with only two passes through the device layers, resulting in surprising advantages in device performance at high temperatures. In particular, the structures of the present invention enable power photodiodes in which the fill factor (FF), external quantum efficiency (EQE), and power conversion efficiency (PCE) temperature coefficients are all positive. The inventors are unaware of any previously disclosed power photodiode structure or device possessing all of these properties.

[0018] In particular, in nitride photodiodes, the use of a multiple quantum well (MQW) absorber layer, also known as the active region or active layer, with (Al)InGaN wells and an (Al)(In)GaN barrier between the wells surrounding the absorber region can delay the onset of strain-induced defect generation, allowing for a larger total absorber (Al)InGaN thickness in the absorber region or a higher indium (In) fraction in the absorber layer for a given absorber thickness. However, the presence of the barrier layer can hinder the collection of photogenerated carriers from the absorber region, leading to a reduced fill factor, especially at high input optical power densities. This carrier collection issue can be exacerbated by built-in polarization fields generated in the nitride. For a given photodiode operating temperature, input wavelength, and input power density / distribution, it has been shown that the power conversion efficiency of a photodiode can be maximized, even with a two-pass device architecture, by tailoring the photodiode epitaxial structure so that the fill factor and power conversion efficiency have positive temperature coefficients near the photodiode operating temperature. Tuning the photodiode epitaxial structure includes optimizing the thickness and composition of well and barrier layers, the thickness and composition of superlattice layers, and the doping levels and thicknesses of dopant, cladding, and contact layers.

[0019] Power nitride photodiodes, which efficiently convert light energy into electrical energy and can operate at high temperatures, are suitable for applications requiring high-temperature operation where more traditional low-bandgap photodiodes or solar cells degrade more significantly at high temperatures. Furthermore, nitride photodiodes maintain high efficiency even at high temperatures and high power levels, enabling high-power-density packaged photodiode modules without the need for active cooling. Power nitride photodiodes can be used in power-over-fiber and power-over-air systems. Applications in such systems include automotive, aviation, and lighting.

[0020] The power conversion efficiency (PCE) η of a photodiode is η=V mp ×I mp / P in where P in is the input radiated power, and V mp is the voltage at the maximum available power, and I mp is the current at maximum available power. Another way to express PCE is as η=V, as shown schematically in Figure 1. oc ×I sc ×FF / P in In the formula, V oc is the open circuit voltage and I sc is the short circuit current and FF is the fill factor. The fill factor (FF) is calculated by the formula (I mp ×V mp ) / (I sc ×V oc ), which is shown in Figure 1 as the ratio of the areas of the small dot rectangular area and the large dot rectangular area. Yet another way to express the PCE of a semiconductor photodiode is η = (eC oc / E g )×OA×IQE×FF×E g / (hν), where e is the charge of an electron and E gwhere ∑ is the bandgap of the semiconductor, OA is the optical absorption (or the fraction of incident photons absorbed in the absorber layer), IQE is the internal quantum efficiency (the fraction of absorbed photons that generate electron-hole pairs that are collected), h is Planck's constant, and ν is the photon frequency. In preferred embodiments, the FF is greater than 70%, 80%, 90%, or 95%. A high fill factor implies the ability of a device or device structure to efficiently collect photogenerated electrons and holes under forward bias, unlike the operating mode of, for example, a photodetector. In general, achieving a high FF requires careful optimization of the band offset and electric field within the device structure, including doping levels, over a range of bias conditions. Further details on considerations for achieving a high FF in nitrides, such as optimizing cladding layers, are described in Cardwell and D'Evelyn [Patent Documents 1 and 2], which are incorporated herein by reference in their entirety.

[0021] Compared to prior art photodiodes designed for much lower photon fluxes, primarily fabricated using GaN-on-sapphire structures, the present photodiodes, including GaN-on-GaN structures, feature high conversion efficiency due to careful optimization of the semiconductor layer composition and doping, and large-area p-side electrical contacts with high reflectivity for use in a dual-reflection pumping architecture and very low contact resistance to minimize lateral ohmic losses at high current densities. In certain embodiments, the present photodiode structures are designed for applications where illumination is provided by a single laser or multiple lasers and enters the structure through an edge or aperture. In certain embodiments, laser light is coupled into an aperture formed in the photodiode structure using an optical fiber, lens, or waveguide. In certain embodiments, the present photodiode structures incorporate much lower dislocation densities, resulting in longer minority carrier diffusion lengths, enabling higher currents as well as longer minority carrier lifetimes, resulting in higher open-circuit voltages and fill factors. Additionally, the present device can include a conductive substrate to enable vertical transport in vertically aligned power devices for simpler design and reduced series resistance, and a transparent substrate with a refractive index very similar to that of the absorber layer to minimize optical loss. For example, as shown in Figure 2, vertical current transport is directed in the Z direction from the substrate 101.

[0022] FIG. 2 shows a simplified diagram of a III-metal nitride-based photodiode structure 1000 (or device 1000). Referring to FIG. 2, a substrate 101 is provided. In certain embodiments, the substrate 101 is made of a single-crystal III-metal nitride, a gallium-containing nitride, or gallium nitride. The substrate 101 can be grown by HVPE, ammonothermal, or flux methods. In certain embodiments, the substrate 101 is a template, and a single-crystal III-metal nitride layer 1104 is deposited or grown on the template substrate 1101, which is made of or includes a material such as sapphire (Al2O3), silicon carbide (SiC), or silicon. One or both large-area surfaces of the substrate 101 may be polished and / or chemically mechanically polished. In certain embodiments, the template substrate 1101 is made of or includes sapphire and has a large-area surface 1102 with a crystallographic orientation within 5 degrees, 2 degrees, 1 degree, or 0.5 degrees of the (0001) crystal plane. The large-area surface 102 of the substrate 101 can be characterized by a miscut in the <10-10>m direction of between about 0.2 degrees and about 1 degree, and a miscut in the <11-20>a direction of less than about 0.2 degrees. In certain embodiments, the template substrate 1101 has a cubic crystal structure and has a large-area surface 1102 with a crystallographic orientation within 5 degrees, 2 degrees, 1 degree, or 0.5 degrees of the {111} crystal plane. Other orientations may be selected.

[0023] The large-area surface 102 can have a maximum dimension between about 0.2 millimeters and about 600 millimeters and a minimum dimension between about 0.2 millimeters and about 600 millimeters, and the substrate 101 can have a thickness between about 10 micrometers and about 10 millimeters, or between about 100 micrometers and about 2 millimeters. In certain embodiments, the substrate 101 is substantially circular and has one or more alignment flats or notches. In alternative embodiments, the substrate 101 is substantially rectangular. In certain embodiments, the large-area surface 102 has a maximum diameter dimension or rectangular edge dimension of about 50 mm, 100 mm, 125 mm, 150 mm, 200 mm, 250 mm, 300 mm, or 450 mm. The variation in crystallographic orientation of the large-area surface 102 can be less than about 5 degrees, less than about 2 degrees, less than about 1 degree, less than about 0.5 degrees, less than about 0.2 degrees, less than about 0.1 degrees, or less than about 0.05 degrees relative to the average crystallographic orientation of the large-area surface.

[0024] The large area surface 102 of the substrate 101 is approximately 10 10 cm -2 Less than, about 10 9 cm -2 Less than, about 10 8 cm -2 Less than, about 10 7 cm -2 Less than, about 10 6 cm -2 Less than, about 10 5 cm -2 Less than, about 10 4 cm -2 Less than, about 10 3 cm -2 Less than or about 10 2 cm -2 The large area surface 102 of the substrate 101 may have a threading dislocation density of less than about 10 4 cm -1 Less than, about 10 3 cm -1 Less than, about 10 2 cm -1 Less than 10cm -1 Less than or about 1 cm -1The large-area surface 102 of the substrate 101 may have a stacking fault concentration of less than about 500 arc seconds, less than about 300 arc seconds, less than about 200 arc seconds, less than about 100 arc seconds, less than about 50 arc seconds, less than about 35 arc seconds, less than about 25 arc seconds, or less than about 15 arc seconds. The large-area surface 102 of the substrate 101 may have a crystallographic radius of curvature in at least one direction or at least two independent or orthogonal directions of greater than 0.1 meter, greater than 1 meter, greater than 10 meters, greater than 100 meters, or greater than 1000 meters. In a specific embodiment, the large-area surface 102 of the substrate 101 may have a crystallographic radius of curvature in at least one direction or at least two independent or orthogonal directions of greater than 0.1 meter, greater than 1 meter, greater than 10 meters, greater than 100 meters, or greater than 1000 meters. 5 cm -2 Threading dislocation density of less than about 10 cm -1 and a symmetrical X-ray rocking curve full width at half maximum (FWHM) of less than about 50 arc seconds. Relative to most prior art photodiodes, the reduced dislocation density of the substrate 101 results in a reduced dislocation density in the semiconductor layers of the photodiode and a higher open circuit voltage V oc and is expected to result in higher efficiency at high current densities.

[0025] Substrate 101 may have a thickness between about 10 micrometers and about 100 millimeters, or between about 0.1 millimeters and about 10 millimeters. Substrate 101 may have dimensions, including diameter, of at least about 5 millimeters, at least about 10 millimeters, at least about 25 millimeters, at least about 50 millimeters, at least about 75 millimeters, at least about 100 millimeters, at least about 150 millimeters, at least about 200 millimeters, at least about 300 millimeters, at least about 400 millimeters, or at least about 600 millimeters. In specific embodiments, substrate 101 has a thickness between about 250 micrometers and about 600 micrometers, a maximum lateral dimension or diameter between about 15 millimeters and about 160 millimeters, and a threading dislocation concentration of about 10 4 cm -2 Includes areas less than.

[0026] In certain embodiments, the substrate 101 consists of or includes a single-crystalline group-III metal nitride layer 1104 bonded to or formed on the surface of the template substrate 1101. The single-crystalline group-III metal nitride layer 1104 may include gallium. The single-crystalline group-III metal nitride layer 1104 may be deposited by HVPE, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like. The single-crystalline group-III metal nitride layer 1104 may have a thickness between about 1 micrometer and about 100 micrometers, between about 2 micrometers and about 25 micrometers, or between about 3 micrometers and about 15 micrometers. In certain embodiments, the single-crystalline group-III metal nitride layer 1104 has a wurtzite crystal structure and a crystallographic orientation within 5 degrees, within 2 degrees, within 1 degree, or within 0.5 degrees of the (0001)+ c-plane. In certain embodiments, a nucleation layer (not shown) is present at the interface between the template substrate 1101 and the monocrystalline group III metal nitride layer 1104. In certain embodiments, the nucleation layer consists of or includes one or more of aluminum nitride, gallium nitride, and zinc oxide. In certain embodiments, the nucleation layer is deposited on the template substrate 1101 by at least one of low-temperature MOCVD, sputtering, and electron beam evaporation. In certain embodiments, the nucleation layer has a thickness between about 1 nanometer and about 200 nanometers, or between about 10 nanometers and about 50 nanometers. In certain embodiments, the substrate further includes one or more strain management layers, such as an AlGaN layer or a strained superlattice.

[0027] In certain embodiments, the substrate includes Al u In v Ga 1-u-v One or more n-type layers 105 made of GaN, or in a specific embodiment, an N layer (where 0≦u, v, u+v≦1), are deposited. The carrier concentration in the n-type layer is about 10 16 cm -3 and 10 20 cm -3In certain embodiments, silicon, germanium, or oxygen is the n-type dopant in n-type layer 105. In certain embodiments, the n-type carrier concentration in n-type layer 105 can range between 1×10 18 cm -3 and 8×10 18 cm -3 The doping level ranges between about 0.2 micrometers and about 5 micrometers. A high doping level may be particularly desirable when the substrate 101 has a (0001)+ c-plane orientation because the piezoelectric field may be more effectively shielded for efficient carrier collection. A high doping level may also be desirable when the template substrate 1101 is electrically insulating or highly resistive. Deposition may be performed using metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In certain embodiments, the n-type layer 105 has a thickness between about 0.2 micrometers and about 5 micrometers, or between about 0.5 micrometers and about 1.5 micrometers.

[0028] In certain embodiments, a strained layer superlattice (SLS) 106 is deposited on or over the n-type layer 105. In certain embodiments, the SLS includes or consists of alternating layers of AlInGaN, where the difference in In content of the alternating layers is between about 0.5 atomic % and about 4 atomic %, where atomic % is expressed as a metal fraction (i.e., as a percentage of the total of In, Ga, and Al). In specific embodiments, the SLS includes or consists of alternating layers of GaN and InGaN, where the InGaN has an In content between about 0.5 atomic % and about 4 atomic %, or between about 1 atomic % and about 3 atomic %, and the layer thickness is between about 0.5 nanometers and about 3 nanometers, or between about 1 nanometer and about 2 nanometers, for a total of between about 25 and 80 GaN / InGaN layers. The layers of the SLS may be n-type doped, for example, using Si, Ge, and / or O, and have a doping density of about 1×10 18 cm -3 and about 5 × 10 19 cm -3 or approximately 2 x 10 18 cm -3 and about 4 × 1018 cm -3 The dopant level may be between 0.01 and 0.1.

[0029] In certain embodiments, a lower cladding layer 107, also referred to herein as a lower barrier layer, may be deposited on or over the strained layer superlattice 106. The lower cladding layer 107 may comprise or consist of InGaN with 0-4 atomic % In, and may have a thickness of about 1×10 19 cm -3 and about 5 × 10 19 cm -3 In one example, the lower cladding layer 107 includes up to about 4 atomic percent indium (In), such as between 0.1 atomic percent and 4 atomic percent. As noted by Cardwell and D'Evelyn, high doping levels and / or the presence of In can improve carrier transport through favorable band alignment in +c-plane oriented device structures. High doping levels may be particularly desirable when the substrate 101 has a (0001)+c-plane orientation, since the piezoelectric field can be more effectively blocked for efficient carrier collection. The lower cladding layer 107 may have a thickness between about 6 nanometers and about 14 nanometers.

[0030] The absorber layer 108, also referred to herein as the active layer, may be deposited on or over the lower cladding layer 107. The absorber layer 108 may comprise, for example, Al w In x Ga 1-w-x N well layer and Al y In z Ga 1-y-zThe semiconductor device may include or consist of a multiple quantum well (MQW) including alternating layers of N barrier layers, where 0≦w, x, y, z, w+x, y+z≦1, and w<u、yおよび / またはx> v, z. The absorber layer 108 may include between 25 and 100, between 30 and 75, or between 35 and 50 quantum wells (not shown). The quantum wells may include InGaN well layers and GaN barrier layers. Each of the well layers may have a thickness between about 2 nanometers and about 5 nanometers, or between about 2.5 nanometers and about 4 nanometers. Each of the barrier layers may have a thickness between about 0.5 nanometers and about 2.5 nanometers, or between about 1 nanometer and about 2 nanometers. In certain embodiments, the absorber layer 108 is deposited by MOCVD at a substrate temperature between about 700° C. and about 950° C.

[0031] In certain embodiments, the absorber layer 108 is unintentionally doped. In certain embodiments, the absorber layer 108 is doped to a concentration of about 5×10 using oxygen, silicon, or germanium as a dopant. 15 cm -3 and about 5 × 10 19 cm -3 or about 5 x 10 16 cm -3 and about 5 × 10 18 cm -3 In a particular embodiment, the absorber layer 108 is n-doped with a dopant concentration between about 5×10 and 100 μm, using Mg as the dopant. 15 cm -3 and about 5 × 10 19 cm -3 or about 5 x 10 16 cm -3 and about 5 × 10 18 cm -3In some embodiments, the absorber layer 108 has a bandgap wavelength between about 360 nanometers and about 550 nanometers, for example, between about 400 nanometers and about 500 nanometers.

[0032] The composition and structure of the absorber layer 108 are selected to provide optical absorption at a preselected wavelength, for example, near 405 nanometers or near 450 nanometers. In certain embodiments, the wavelength for optimal absorption is selected to be between about 360 nanometers and about 500 nanometers. The absorber layer 108 can be characterized by photoluminescence spectroscopy. In certain embodiments, the composition of the absorber layer 108 is selected so that the photoluminescence spectrum has a peak between 5 nanometers and 50 nanometers, or between 10 nanometers and 25 nanometers, longer than the desired absorption wavelength of the photodiode structure 1000. In certain embodiments, the well layer contains between about 10 atomic % and about 14 atomic % In. In certain embodiments, the quality and layer thickness within the absorber layer 108 are characterized by X-ray diffraction.

[0033] In certain embodiments, the absorber layer 108 is terminated by an upper barrier layer 109, sometimes referred to herein as a first upper barrier layer. The upper barrier layer 109 may be comprised of GaN or InGaN containing 0-4 atomic % indium (In). In one example, the upper barrier layer 109 contains up to about 4 atomic % indium (In), such as between 0.1 atomic % and 4 atomic % indium (In). The upper barrier layer 109 may have a thickness between about 4 nanometers and about 10 nanometers. In certain embodiments, the upper barrier layer 109 is unintentionally doped. In certain embodiments, the upper barrier layer 109 has a graded composition in which the In concentration varies between a first level and a second level.

[0034] In certain embodiments, an upper cladding layer 110, sometimes also referred to herein as a second upper barrier layer, is deposited on or over the upper barrier layer 109. The upper cladding layer 110 may comprise or consist of heavily Mg-doped GaN and may have a thickness between about 10 nanometers and about 30 nanometers, or between about 16 nanometers and about 24 nanometers. The upper cladding layer 110 has a thickness of about 8×10 19 cm -3 and approximately 6 × 10 20 cm -3 or approximately 1.5 x 10 20 cm -3 and about 4 × 10 20 cm -3 The magnesium concentration may be between 0.01 and 0.1.

[0035] Next, Al, where 0≦q, r, q+r≦1. q In r Ga 1-q-r A p-type layer 111 formed from N or GaN is deposited on or over the upper cladding layer 110. The p-type layer 111 has a thickness of about 10 18 cm -3 and about 10 21 cm -3 Between, or about 10 19 cm -3 and approximately 8 x 10 19 cm -3 and may have a thickness between about 5 nanometers and about 100 nanometers, or between about 25 nanometers and about 75 nanometers.

[0036] A p-contact layer 112 may then be deposited on or over the p-type layer 111. The p-contact layer 112 may have a thickness of about 10 19 cm -3 and about 10 22 cm -3 Between, or about 10 20 cm -3 and approximately 6 × 10 20 cm -3and may have a thickness between about 2 nanometers and about 50 nanometers, or between about 10 nanometers and about 25 nanometers.

[0037] The semiconductor layers, including the n-type layer 105, strained layer superlattice 106, lower cladding layer 107, absorber layer 108, upper barrier layer 109, upper cladding layer 110, p-type layer 111, and p-contact layer 112, are epitaxial, have the same crystal orientation as the large-area surface 102 of the substrate 101 within about 2 degrees, within about 1 degree, within about 0.5 degrees, or within about 0.2 degrees, have very high crystal quality, contain nitrogen, and 9 cm -2 The semiconductor layer may have a surface dislocation density of less than 10 10 cm -2 Less than 10 9 cm -2 Less than 10 8 cm -2 Less than 10 7 cm -2 Less than 10 6 cm -2 Less than 10 5 cm -2 Less than 10 4 cm -2 Less than 10 3 cm -2 Less than or equal to 10 2 cm -2 The semiconductor layer may have a surface dislocation density that is within 5 times, 2 times, or 1.2 times the dislocation density of the large-area surface 102.

[0038] In specific embodiments, the semiconductor layer has an orientation within 5 degrees of the (0001) c-plane, and the FWHM of the 0002 X-ray rocking curve of the top surface is less than 300 arc seconds, less than 100 arc seconds, or less than 50 arc seconds.

[0039] To maximize the efficiency of a packaged photodiode, it may be important to maximize the reflectivity of the top surface of the photodiode structure 1000 and minimize the electrical resistance of the contacts within the photodiode structure. Referring again to FIG. 2 , the p-side reflective electrical contact 113 may be deposited on or over the p-type layer 111, or, if present, on the p-contact layer 112. In preferred embodiments, the average reflectivity of the reflective p-side electrical contact is greater than 70%, greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 97%, or greater than 98% at a particular angle or range of angles at which light is incident during operation, e.g., an angle 135 between 0 and 20 degrees from the normal (i.e., perpendicular to the large-area surface 102 in FIG. 2 ). From Snell's Law, the angle of incidence 135 within the semiconductor layer will generally be smaller than the angle of incidence of light on the planar portion of the back surface 130. In general, the term "average reflectance" as used herein is intended to broadly describe a reflectance value calculated by averaging at least two reflectance measurement data points on a surface at a particular wavelength between 360 nanometers and 500 nanometers and at one or more angles relative to the surface of the layer that are representative of a range of angles of incidence during device operation. In some embodiments, light is coupled into the device through aperture 120, and the angle of incidence into p-side reflective electrical contact 113 is between about 0 degrees and about 60 degrees, between about 0.2 degrees and about 40 degrees, or between about 0.3 degrees and about 20 degrees, measured from the plane of the semiconductor layer. The contact resistance of the p-side reflective electrical contact is 3×10 -3 Ωcm 2 Less than 1×10 -3 Ωcm 2 Less than 5 x 10 -4 Ωcm 2 Less than 2 x 10 -4 Ωcm 2 Less than 10 -4 Ωcm 2 Less than 5 x 10 -5 Ωcm 2 Less than 2 x 10 -5 Ωcm 2 Less than or equal to 10 -5 Ωcm 2 In a preferred embodiment, the contact resistance is less than 1×10-4 Ωcm 2The p-side reflective electrical contact may comprise at least one of silver, gold, aluminum, nickel, platinum, rhodium, palladium, titanium, chromium, germanium, ruthenium, magnesium, scandium, etc. In some embodiments, the p-side reflective electrical contact 113 may comprise or consist of at least two layers: a first layer provides good electrical contact, comprises platinum, nickel, aluminum, or titanium, and has a thickness between 0.1 nanometers and 5 nanometers; and a second layer provides excellent optical reflectivity, comprises silver, gold, or nickel, and has a thickness between 0.4 nanometers and 1 micrometer. In particular embodiments, the p-side reflective electrical contact 113 may comprise or consist of at least three layers, at least four layers, or at least five layers. In certain embodiments, the p-side reflective electrical contact 113 includes three layers: a first layer includes silver and has a thickness between about 1 nanometer and about 200 nanometers; a second layer includes a moderately oxophilic metal and has a thickness between about 0.5 nanometers and about 2 nanometers; and a third layer includes silver and has a thickness between about 50 nanometers and about 200 nanometers. In certain embodiments, the moderately oxophilic metal includes or consists of nickel. In certain embodiments, the moderately oxophilic metal includes or consists of one or more of copper, cobalt, iron, and manganese. In certain embodiments, the reflective p-side electrical contact is annealed after deposition to improve its reflectivity and / or reduce its contact resistance. In certain embodiments, the annealing is performed in a rapid thermal annealing (RTA) furnace to a temperature between about 300° C. and about 1000° C. In a specific embodiment, the p-side reflective electrical contact 113 is annealed at a temperature between about 500°C and about 900°C in a controlled atmosphere containing oxygen at a partial pressure between about 0.1 Torr (about 13 Pa) and about 200 Torr (about 27 kPa) to induce interdiffusion between the moderately oxygen-philic metal and silver, introducing a controlled concentration of oxygen atoms into the p-side reflective electrical contact layer.In a preferred embodiment, the oxygen partial pressure is increased to about 10° C. before the p-side reflective electrical contact is cooled to below a temperature of about 250° C. to avoid the formation of excess silver oxide. -4 In a specific embodiment, the p-side reflective electrical contact 113 is cooled to less than about 1×10 20 cm -3 and about 7 x 10 20 cm -3 The p-side electrical contact comprises oxygen at a maximum local concentration between about 0.25 nanometers and about 3 nanometers, or between about 0.5 nanometers and about 2 nanometers. In certain embodiments, the p-side electrical contact comprises or consists of at least four layers: a first layer comprises or consists of at least one of platinum or nickel and has a thickness between about 0.25 nanometers and about 3 nanometers, or between about 0.5 nanometers and about 2 nanometers; a second layer comprises silver and has a thickness between about 1 nanometer and about 200 nanometers; a third layer comprises a moderately oxygen-philic metal and has a thickness between about 0.5 nanometers and about 2 nanometers; and a fourth layer comprises at least one of silver or gold and has a thickness between about 50 nanometers and about 500 nanometers. The p-side reflective electrical contact can be deposited by thermal evaporation, electron beam evaporation, sputtering, or other suitable technique. In preferred embodiments, the p-side reflective electrical contact functions as the p-side electrode of the power photodiode. In certain embodiments, the p-side reflective electrical contact is planar and parallel to the semiconductor layers, which can be useful for maximizing reflectivity. In alternative embodiments, the p-side reflective electrical contact is patterned or textured.

[0040] 2, in certain embodiments, an n-side reflective electrical contact 114 having an average reflectivity of greater than about 70% is deposited on or over the backside of the substrate 101. In preferred embodiments, the average reflectivity of the reflective n-side electrical contact is greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 97%, or greater than 98% at a particular angle or range of angles at which light is incident during operation. The contact resistance of the reflective n-side electrical contact is greater than 1×10 -3 Ωcm 2 Less than 5 x 10-4 Ωcm 2 Less than 2 x 10 -4 Ωcm 2 Less than 10 -4 Ωcm 2 Less than 5 x 10 -5 Ωcm 2 Less than 2 x 10 -5 Ωcm 2 Less than or equal to 10 -5 Ωcm 2 In a preferred embodiment, the contact resistance is less than 5×10 -5 Ωcm 2 The reflective n-side electrical contact may comprise at least one of silver, gold, aluminum, nickel, platinum, rhodium, palladium, titanium, chromium, etc. In some embodiments, the reflective n-side electrical contact may comprise or consist of at least two layers: a first layer provides good electrical contact, comprises aluminum or titanium, and has a thickness between 0.1 nanometers and 5 nanometers; and a second layer provides excellent optical reflectivity, comprises aluminum, nickel, platinum, gold, or silver, and has a thickness between 10 nanometers and 10 micrometers. In certain embodiments, the n-side reflective electrical contact may comprise or consist of at least three layers, at least four layers, or at least five layers to co-optimize reflectivity (maximize), contact resistance (minimize), and robustness (maximize). The reflective n-side electrical contact may be deposited by thermal evaporation, e-beam evaporation, sputtering, or other suitable techniques. In certain embodiments, the n-side reflective electrical contact serves as the n-side electrode of the power photodiode. In certain embodiments, the n-side reflective electrical contact is planar and aligned parallel to the semiconductor layers, which is useful for maximizing reflectivity. In alternative embodiments, the n-side reflective electrical contact is patterned or textured, which can be useful for light injection or extraction, for example, within an aperture.

[0041] In certain embodiments, particularly those in which the n-side reflective electrical contact comprises aluminum, the backside of the substrate 101 is treated by reactive ion etching (RIE) using a chlorine-containing gas or plasma to reduce the contact resistance of the n-side reflective electrical contact. In one specific embodiment, the chlorine-containing gas or plasma comprises SiCl. In certain embodiments, an additional cleaning step is performed to reduce the contact resistance of the n-side reflective electrical contact. In certain embodiments, the additional cleaning step includes or consists of one or more of treatment with a mineral acid, such as hydrochloric acid, nitric acid, or aqua regia; a buffered oxide etch; a dry etch; or a plasma, such as an argon plasma.

[0042] In certain embodiments, for example, when substrate 101 is a template comprising an insulating template substrate 1101, an n-side electrical contact is instead deposited at the bottom of a trench (not shown) formed through a portion of at least one of n-type layer 105, strained layer superlattice (SLS) 106, or lower cladding layer 107, e.g., absorber layer 108.

[0043] The photodiode structure 1000 described in this disclosure is intended for use with a photodiode die disposed within a packaged photodiode assembly, typically including a single reflector arrangement. The photodiode die, or simply "die," typically includes a portion of a substrate formed by singulation, cleaving, or other similar processes, and including the various photodiode structure 1000 elements described herein. In some embodiments, the photodiode die is disposed within the packaged photodiode assembly and includes a photodiode structure having an aperture 120 ( FIG. 2 ) configured to receive one or more wavelengths of electromagnetic radiation, also referred to herein as light, from an illumination source 251. The illumination source 251 may include a laser, a fiber optic cable coupled to a laser, or other useful radiation source. Referring again to FIG. 2 , in certain embodiments, the back surface 130 of the substrate 101 is smooth. In certain embodiments, an anti-reflective coating is deposited on the back surface 130. The anti-reflective coating may comprise a material selected from the group including MgF2, SiO2, Al2O3, HfO2, LaTiO3, Si3N4, or TiO2, and may be deposited by electron beam evaporation, ion beam evaporation, sputtering, or other suitable deposition techniques. One or more dies may be prepared from the above-described photodiode structure by, for example, dicing, singulation, cleaving, etc. The dies may have square, rectangular, triangular, or other shapes. The dies may be bounded by edge structures such as one or more of a passivation layer and a reflective coating.

[0044] In certain embodiments, at least a portion of the backside surface 130 of the substrate 101 is roughened to facilitate light penetration into the device structure and to aid in light trapping, as shown generally in FIG. 3 . In certain embodiments, an anti-reflective coating is applied to the roughened backside surface. In certain embodiments, the backside roughening is provided by forming pyramidal structures on the backside surface 130. In one specific embodiment, the backside surface 130 consists essentially of GaN having a crystallographic orientation within about 5 degrees of (000-1), and the hexagonal pyramidal structures 132 are formed by exposure to a solution comprising at least one of potassium hydroxide (KOH) and sodium hydroxide (NaOH) at a concentration between about 0.1 molar and about 12 molar, at a temperature between about 0° C. and about 90° C., for a time between about 30 seconds and about 5 hours. In certain embodiments, each of the hexagonal pyramid structures 132 has a peak-to-peak height ranging from about 0.3 micrometers to about 30 micrometers and a lateral dimension or diameter of the base region ranging from about 0.3 micrometers to about 30 micrometers. In certain embodiments, each of the plurality of hexagonal pyramid structures 132 extends from the crystalline structure of the gallium-nitrogen-containing substrate member and has a size irregularity ranging from 0% to 50%, although other irregularities are possible. In certain embodiments, the back surface 130 has interior regions 135 (typically planar) disposed between pairs of the plurality of hexagonal pyramid structures 132. In certain embodiments, the pyramid structures are present on 50% to 100% of the surface area of ​​the exposed portion of the back surface.

[0045] Referring again to FIG. 3 , in certain embodiments, nanodot or nanopillar structures are fabricated on the back surface 130, e.g., on the pyramidal structures 132, to further improve light incidence and coupling to the active layer for absorption. In certain embodiments, the back surface 130 has a plurality of nanodot structures 136 spatially arranged to cover the interior region 135 and cover the surface region of each of the plurality of hexagonal pyramidal structures 132, and configured to direct incident electromagnetic radiation 137 having a wavelength ranging from 360 to 500 nanometers toward the absorber layer 108 to increase absorption of the radiation in the absorber layer, thereby coupling additional radiation into the absorber layer. The nanodot structures 136 generally include a plurality of facets formed on the surfaces of the pyramidal structures 132. In one example, as shown in FIG. 8 , the faceted structures of the nanodot structures 136 are between about 0.05 micrometers (μm) and about 0.6 micrometers (μm). 3, incident electromagnetic radiation 137 is provided to the back surface 130, and the nanodot structures 136 are configured to increase the amount of transmitted radiation 138 relative to the amount of reflected radiation 139. In this manner, the nanodot structures are configured to increase the absorption of radiation in the absorber layer 108, thereby coupling additional radiation into the absorber layer during operation. The nanodot structures may include gallium nitride.

[0046] In certain embodiments, a chip or die containing a photodiode structure such as those described above is incorporated into an optical resonator, many examples of which are described by Cardwell and D'Evelyn. In one specific embodiment, the optical resonator may comprise a tapered hole in a silver foil or plate, as shown schematically in FIG. 4. Light may enter through a resonator aperture having a diameter D2 onto a backside 130 having a die entrance aperture D1 (which may correspond to aperture 120 in FIG. 2). Any reflected light may be reflected off the conical sides of the resonator and back toward the die entrance aperture 120, especially if reflected at an oblique angle (as in FIG. 3).

[0047] In the inventive structures described herein, the absorber layer 108 includes multiple, relatively thin well and barrier layers, which allow for fairly stable external quantum efficiency even though light passes through the absorber layer only twice, and the thinness of the MQW layers (specifically, the barrier layers) serves the dual purpose of strain management and maintaining high carrier collection efficiency and an improved fill factor. This combination, along with the addition of an upper barrier layer, which the inventors have found to improve device performance, has been found to produce the unexpected and surprising result that the fill factor, external quantum efficiency, and power conversion efficiency each increase over a temperature range between 25°C and 80°C. In certain embodiments, the fill factor increases by at least 2%, at least 3%, at least 4%, at least 5%, or at least 6% as the temperature of the semiconductor layers in the photodiode device area increases from 25°C to 80°C. In certain embodiments, the external quantum efficiency increases by at least 1%, at least 2%, or at least 3% as the temperature of the semiconductor layer in the photodiode device area increases from 25° C. to 80° C. In certain embodiments, the power conversion efficiency increases by at least 2%, at least 3%, at least 4%, at least 5%, or at least 6% as the temperature of the semiconductor layer in the photodiode device area increases from 25° C. to 80° C. In certain embodiments, the fill factor, external quantum efficiency, and power conversion efficiency each increase monotonically over the temperature range between 25° C. and 70° C. Without intending to be bound by theory, the inventors believe that this phenomenon is due to phonon-assisted tunneling. In other words, phonons in the semiconductor layer can assist carriers in overcoming the barrier heights formed by various barrier layers, including those in the multiple quantum wells in the absorber layer 108 and the upper barrier layer 109. We further believe that the SLS placed below the lower cladding layer helps to reduce the concentration of point defects, such as Shockley-Read-Hall defects, in the absorber and cladding layers, which can lead to non-radiative recombination, thereby improving the EQE. [Example]

[0048] The embodiments provided by the present disclosure are further described by reference to the following comparative examples and illustrative process examples. It will be apparent to those skilled in the art that many modifications, both to materials and methods, can be practiced without departing from the scope of the present disclosure.

[0049] Example 1 An epitaxial structure similar to that shown in Figure 2 is grown on a bulk GaN substrate whose crystal surface orientation is miscut by approximately 0.4 degrees in the <10-10>m direction from (0001). 18 cm -3 n-type layers having a silicon dopant concentration of about 3×10 were grown on the substrate by MOCVD to a thickness of about 1 micrometer, followed by 18 cm -3 and a thickness of about 1.5 nanometers. 0.04 Ga 0.96 A strained layer superlattice consisting of 50 alternating layers of N and GaN is then grown to a thickness of about 10 nanometers and a density of about 3 × 10 19 cm -3 In with a silicon dopant concentration of 0.04 Ga 0.96 A lower cladding layer of N is then deposited. A multi-quantum well consisting essentially of 40 pairs of 3.5-nanometer-thick unintentionally doped InGaN well layers and 1.5-nanometer-thick unintentionally doped GaN barrier layers is then grown, followed by an 8-nanometer-thick unintentionally doped GaN upper cladding layer. A magnesium dopant concentration of approximately 2×10 20 cm -3 , with a thickness of about 20 nanometers. 0.04 Ga 0.96 N is deposited, followed by a magnesium dopant concentration of approximately 3×10 19 cm -3 , a p-type layer consisting essentially of GaN having a thickness of about 60 nanometers, followed by deposition of a magnesium dopant concentration of about 3×10 20 cm -3A p-contact layer consisting essentially of GaN is deposited to a thickness of approximately 15 nanometers. The substrate and semiconductor layers are then removed from the MOCVD reactor and placed in an electron beam evaporator, where a three-layer p-contact is deposited, including a 100-nanometer layer of silver, a 1-nanometer layer of nickel, and a 100-nanometer layer of silver.

[0050] The substrate is then exposed to a 2.3 molar KOH solution at a temperature of about 60°C for about 1 hour to form hexagonal pyramidal structures on the backside of the substrate. The morphology of the hexagonal pyramidal structures is similar to that shown in Figure 5. A reflective n-contact, including a 200 nanometer thick Al layer, a 100 nanometer thick Ti layer, a 100 nanometer thick Ni layer, and then a 200 nanometer thick Au layer, is sequentially deposited on a portion of the roughened backside substrate surface by electron beam evaporation, leaving another portion of the roughened backside substrate surface exposed. An anti-reflective coating consisting essentially of SiO2 and having a thickness of about 70 nanometers is then deposited on at least the exposed portion of the backside of the substrate by an ion beam evaporation process. A simple optical resonator is provided, including a silver (Ag) plate with a countersunk hole similar to that shown schematically in Figure 4. In one configuration as shown in Figure 4, the entrance portion (i.e., the light-receiving portion) of the countersunk hole has a diameter D2, and the exit end of the countersunk hole region has a diameter D1, which is larger than D2. In a specific example, the values ​​of D1 and D2 are 0.6 mm and 1.7 mm, respectively. Next, wafer-level current-voltage (IV) measurements are performed on one of the devices on the substrate, both in the dark and under illumination with 406 nm laser light at a power level of 0.4 to 0.5 watts, measured using a calibrated power meter. The light-current-voltage (LIV) response at room temperature is shown in Figure 6. With the optical cavity present, the external quantum efficiency is measured to be 82.9%, and the wall-plug efficiency is measured to be 62.3%. With the optical cavity removed, the external quantum efficiency is measured to be 78.6%, and the wall-plug efficiency is measured to be 59.2%. In both cases, the fill factor is approximately 85%. The similarity of the values ​​without and with the optical cavity indicates that the majority of power generation comes from just two passes of light through the absorber layer: the first pass after it enters the opening 120 formed between the reflective n-contacts on the backside 130, and the second pass after it reflects off the p-side reflective electrical contact 113.

[0051] Example 2 A hexagonal pyramidal structure similar to that shown in FIG. 5 is formed on the backside of a photodiode substrate using a process similar to that described in Example 1. Next, a silver layer approximately 100 nanometers thick is deposited on the hexagonal pyramidal structure by electron beam evaporation. The silver layer is then exposed to an inductively coupled plasma (ICP) containing Cl2 to form an AgCl hard mask. The coated hexagonal pyramidal structure is etched by the ICP plasma for approximately 200 seconds, after which the remaining AgCl residue is removed by immersion in aqueous hydrochloric acid. This process flow is shown schematically in FIG. 7. As shown in FIG. 8, multiple nanodot structures 136 similar to those shown schematically in FIG. 3 are formed.

[0052] Example 3 A device structure similar to that described in Example 1 and shown in Figure 2 is fabricated. A reflective Aln-type metal contact including two peripheral conductor pads is deposited on the backside of the substrate. Individual dies, chips, or devices are prepared by singulating the substrate and depositing SiO2 mesa edge passivation. The electroluminescence peak wavelength of this device is 418 nanometers.

[0053] The electrical and optoelectrical characteristics of the device are measured using a setup similar to that shown in Figure 9. Figure 9 is a schematic diagram of the fiber-illumination current-voltage test setup used to measure the illumination current-voltage curve of a nitride photodiode chip. The photodiode is mounted on an electrically and thermally conductive sample stage, which provides the surfaces for the positive sense and positive force probes. Two peripheral conductor pads provide the surfaces for the corresponding negative sense and negative force probes.

[0054] The die or chip described above is subjected to a fiber irradiation current-voltage test using a 410 nanometer wavelength laser light at a power level of 3.78 watts as measured using a calibrated power meter, using the test configuration shown in Figure 9. The stage is heated using a thin film resistive heater. A thermocouple mounted on the sample stage measures the test temperature of the photodiode chip. The dark and light IV responses are measured at stage temperatures ranging from 25°C to 82°C. The LIV response is shown in Figure 10A, and a magnified view of a portion of the results shown in Figure 10A is shown in Figure 10B. The open circuit voltage ratio (eV oc The LIV curves at each temperature are evaluated for fill factor (FF), external quantum efficiency (ECE), and power conversion efficiency (PCE). The results are shown in Figure 11. As expected from the known temperature-dependent bandgap decrease, the open-circuit voltage ratio is seen to decrease with temperature. However, for the first time in a semiconductor-based photodiode, to the inventors' knowledge, the fill factor, external quantum efficiency, and power conversion efficiency all increase with stage temperatures between 25°C and 75°C. Specifically, the PCE increases by 4.9%, from 59% at 25°C to 62% at 82°C. This is due to the increase in both fill factor (5.4% increase) and EQE (2.6% increase) with increasing temperature. oc This overcomes the predicted decrease in hν (3.0% decrease). Therefore, in applications where the operating temperature of the photodiode device is elevated above ambient temperature, device performance will be improved. Therefore, in some applications, there may be less need to actively cool the photodiode device, while in other configurations, active heating may be desirable to improve the performance of the photodiode device.

[0055] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. In a photodiode device, A die including at least one multiple quantum well layer disposed between an n-type layer and an upper barrier layer, with a p-type layer overlying the upper barrier layer, wherein each of the at least one multiple quantum well layer, the n-type layer, the upper barrier layer, and the p-type layer is Al ｘ In ｙ Ga １－ｘ－ｙ N (wherein 0≦x, y, x+y≦1), and １０ cm －２ a die having a dislocation density of less than Equipped with the at least one multiple quantum well layer includes at least 25 pairs of well layers and barrier layers, the well layers having a thickness, measured in a first direction, between about 2 nanometers and about 5 nanometers, and the barrier layers having a thickness, measured in the first direction, between about 0.5 nanometers and about 2.5 nanometers; the p-type layer has a thickness, measured in the first direction, between 1 nanometer and 1000 nanometers; the upper barrier layer has a thickness between about 4 nanometers and about 10 nanometers and comprises, on a metallic basis, up to about 4 atomic percent indium (In); each of the at least one multiple quantum well layer, the n-type layer, the upper barrier layer, and the p-type layer has a crystallographic orientation within 5 degrees of a c-plane and is parallel to a first plane oriented perpendicular to the first direction; The die is characterized by a fill factor (FF) that increases in value as the temperature of the die increases from about 25°C to about 80°C, the fill factor being measured using light having a wavelength between 360 nanometers and 500 nanometers.

2. 10. The photodiode device of claim 1, wherein the fill factor is at least 70% at a temperature of about 25[deg.]C and increases by at least 2% when the temperature of the die is increased to about 80[deg.]C.

3. 10. The photodiode device of claim 1, wherein the die is further characterized by an external quantum efficiency that increases in value when the temperature of the die is increased from about 25[deg.]C to about 80[deg.]C.

4. 4. The photodiode device of claim 3, wherein the external quantum efficiency is at least 70% at a temperature of about 25°C and increases by at least 1% when the temperature of the die is increased to about 80°C.

5. 10. The photodiode device of claim 1, wherein the die is further characterized by a power conversion efficiency that increases in value as the temperature of the die increases from about 25 degrees Celsius to about 80 degrees Celsius.

6. 6. The photodiode device of claim 5, wherein the power conversion efficiency is at least 50% at a temperature of about 25°C and increases by at least 2% when the temperature of the die is increased to about 80°C.

7. 2. The photodiode device of claim 1, wherein the well layer has an In content between 10 and 14 atomic percent.

8. The photodiode device of claim 1 , wherein each of said at least one multiple quantum well layer and said upper barrier layer is unintentionally doped.

9. the n-type layer has a thickness, measured in the first direction, between about 0.2 micrometers and about 5 micrometers, and １７ cm －３ and about 6 x 10 １９ cm －３ 2. The photodiode device of claim 1, having an n-type dopant concentration between .gtoreq..times ...

10. the p-type layer has a thickness, measured in the first direction, between about 5 nanometers and about 100 nanometers, １８ cm －３ and about 10 ２１ cm －３ 2. The photodiode device of claim 1, having a p-type dopant concentration between .gtoreq..times ...

11. and a lower cladding layer underlying the at least one multiple quantum well layer, the lower cladding layer having a thickness in the first direction of between about 6 nanometers and about 14 nanometers and a thickness of about 1×10 １９ cm －３ and about 5 x 10 １９ cm －３ 10. The photodiode device of claim 1, having an n-type dopant concentration between about 0.1 and about 1.0 atomic percent, including up to about 4 atomic percent In.

12. and an upper cladding layer overlying the upper barrier layer, the upper cladding layer having a thickness in the first direction of between about 10 nanometers and about 30 nanometers and a thickness of about 8×10 １９ cm －３ and about 6 x 10 ２０ cm －３ 2. The photodiode device of claim 1, having an n-type dopant concentration between .gtoreq..times ...

13. 10. The photodiode device of claim 1, further comprising a strained layer superlattice overlying the n-type layer, the strained layer superlattice comprising between about 25 and about 80 alternating layers of AlInGaN, the In content of the alternating layers differing between about 0.5 atomic % and about 4 atomic %, and the thickness of the alternating layers being between about 0.5 nanometers and about 3 nanometers.

14. 10. The photodiode device of claim 1, further comprising a p-side reflective electrical contact, the p-side reflective electrical contact having an average reflectivity greater than 70% for angles between 0 and 20 degrees from the first direction at wavelengths between about 360 nanometers and about 500 nanometers.

15. 15. The photodiode device of claim 14, wherein the p-side reflective electrical contact comprises at least a first layer and a second layer, the first layer comprising silver and having a thickness between about 1 nanometer and about 100 nanometers, and the second layer comprising at least one of nickel, copper, cobalt, iron, and manganese and having a thickness between about 0.5 nanometers and about 2 nanometers.

16. 16. The photodiode device of claim 15, wherein the p-side reflective electrical contact further comprises a third layer underlying the first layer, the third layer comprising at least one of nickel and platinum and having a thickness between about 0.25 nanometers and about 3 nanometers.

17. a substrate having a backside and a top side, wherein the at least one multiple quantum well layer, the n-type layer, the upper barrier layer, and the p-type layer each overlie the top side; 10. The photodiode device of claim 1, wherein the back surface has a plurality of hexagonal pyramid structures, each of the hexagonal pyramid structures having a peak height ranging from about 0.3 micrometers to about 30 micrometers and a base dimension ranging from about 0.3 micrometers to about 30 micrometers, a size irregularity ranging from 0% to 50%, and an interior region disposed between pairs of the plurality of hexagonal pyramid structures.

18. 18. The photodiode device of claim 17, further comprising a plurality of nanodot structures spatially arranged over the interior region and over a portion of the hexagonal-pyramid structure, the plurality of nanodots configured to direct electromagnetic radiation having a wavelength ranging from 360 to 500 nanometers toward the absorber layer.

19. 20. The photodiode device of claim 18, wherein the plurality of hexagonal pyramid structures comprise between 50% and 100% of a surface area of ​​the back surface, the surface area being measured in a direction parallel to the top surface.

20. 20. The photodiode device of claim 18, wherein the substrate, the plurality of hexagonal pyramid structures, and the nanodot structures are each made from gallium nitride.

21. In a photodiode device, A die including at least one multiple quantum well layer disposed between an n-type layer and an upper barrier layer, with a p-type layer overlying the upper barrier layer, wherein each of the at least one multiple quantum well layer, the n-type layer, the upper barrier layer, and the p-type layer is Al ｘ In ｙ Ga １－ｘ－ｙ N (wherein 0≦x, y, x+y≦1), and １０ cm －２ a die having a dislocation density of less than Equipped with the at least one multiple quantum well layer includes at least 25 pairs of well layers and barrier layers, the well layers having a thickness, measured in a first direction, between about 2 nanometers and about 5 nanometers, and the barrier layers having a thickness, measured in the first direction, between about 0.5 nanometers and about 2.5 nanometers; the p-type layer has a thickness, measured in the first direction, between 1 nanometer and 1000 nanometers; the upper barrier layer has a thickness between about 4 nanometers and about 10 nanometers and comprises, on a metallic basis, up to about 4 atomic percent indium (In); each of the at least one multiple quantum well layer, the n-type layer, the upper barrier layer, and the p-type layer has a crystallographic orientation within 5 degrees of a c-plane and is parallel to a first plane oriented perpendicular to the first direction; The die is a fill factor (FF) that is at least 70% at room temperature and that increases in value by at least 2% when the temperature of the die is increased from about 25° C. to about 80° C.; an external quantum efficiency (EQE) of at least 70% that increases in value by at least 1% when the temperature of the die is increased from about 25° C. to about 80° C.; and a power conversion efficiency of at least 50% at room temperature and increasing in value by at least 2% when the temperature of the die is increased from about 25° C. to about 80° C.; It is characterized by a photodiode device, wherein the fill factor, the external quantum efficiency, and the power conversion efficiency are each measured using light having a wavelength between 360 nanometers and 500 nanometers and a power between 0.1 watts and 10 watts.

22. The die is a fill factor (FF) that is at least 75% at room temperature and that increases in value by at least 3% when the temperature of the die is increased from about 25° C. to about 80° C.; an external quantum efficiency (EQE) of at least 75% that increases in value by at least 2% when the temperature of the die is increased from about 25° C. to about 80° C.; and a power conversion efficiency of at least 55% at room temperature, which increases in value by at least 3% when the temperature of the die is increased from about 25° C. to about 80° C.; 22. The die of claim 21, characterized by:

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