Distributed configuration of programmable devices

Abstract

Embodiments herein describe a distributed configuration system for configurable devices. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems within a device, embodiments herein include configuration interface managers (CIMs) that are distributed to different regions of the device, whether these regions are within one integrated circuit or comprise multiple integrated circuits. Embodiments can still use the central configuration manager to distribute configuration information within a device image to multiple CIMs, which can then forward the configuration information to their assigned regions.

Description

[Technical Field]

[0001] Examples of the present disclosure generally relate to a distributed system for configuring devices that include one or more integrated circuits. [Background technology]

[0002] Traditionally, configurable devices are configured via a central configuration manager. As a result, the configuration manager typically becomes a bottleneck in configuring the device. This was acceptable when the device (e.g., an integrated circuit) was small and did not contain different subsystems. However, modern configurable devices can include systems-on-chips (SoCs), which include heterogeneous computing systems that may include networks-on-chips (NoCs), memory controllers, data processing engines, processor subsystems, programmable logic, and other subsystems that require their own programming information. In addition, these subsystems can directly interface with programmable logic, which has grown by orders of magnitude, especially with the advent of stacked-die devices. Any configuration (or partial reconfiguration) of these devices requires the mixing of various configuration partitions transferred through separate interfaces. The size and heterogeneity of the programming images for these devices further renders configuration via a central configuration manager inefficient. Summary of the Invention

[0003] One embodiment describes a configurable device including a central configuration manager circuit and a plurality of configuration interface manager (CIM) circuits connected to the central configuration manager circuit and distributed throughout the configurable device. The central configuration manager circuit is configured to receive a device image for configuring the configurable device, analyze the device image to identify configuration packets for the plurality of CIM circuits, and transmit the configuration packets to the plurality of CIM circuits. Further, the plurality of CIM circuits are configured to forward the configuration packets to assigned regions of the configurable device. The hardware accelerator is configured to...

[0004] Another embodiment described herein is a method that includes receiving, at a central configuration manager circuit, a device image for configuring a configurable device; analyzing the device image to identify configuration packets for a plurality of CIM circuits in the configurable device; transmitting the configuration packets from the central configuration manager circuit to the plurality of CIM circuits; and forwarding the configuration packets by the plurality of CIM circuits to assigned regions of the configurable device.

[0005] Another embodiment described herein is a configurable device including a central configuration manager circuit, a network, and a plurality of configuration interface manager (CIM) circuits connected to the central configuration manager circuit via the network. The central configuration manager circuit is configured to receive a device image for configuring the configurable device, identify portions of the device image intended for each of the plurality of CIM circuits, and transmit the portions of the device image to the plurality of CIM circuits. Further, the plurality of CIM circuits are configured to transfer the portions of the device image to assigned regions of the configurable device. [Brief explanation of the drawings]

[0006] In a manner in which the above-recited features may be understood in detail, a more particular description briefly summarized above can be had by reference to exemplary embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical exemplary embodiments and therefore should not be considered as limiting the scope thereof. [Figure 1] 1 illustrates configuring an integrated circuit using a distributed system, according to one embodiment. [Figure 2A] 1 illustrates configuring multiple integrated circuits using a distributed configuration system, according to one embodiment. [Figure 2B] 1 illustrates configuring multiple integrated circuits using a distributed configuration system, according to one embodiment. [Figure 3] 1 is a flowchart for configuring a device using a distributed system, according to one embodiment. [Figure 4] 1 illustrates configuring devices using a distributed system, according to one embodiment. [Figure 5] 1 illustrates a portion of a device image according to one embodiment. [Figure 6] 1 illustrates a packet in a device image according to one embodiment.

[0007] For ease of understanding, wherever possible, identical reference numbers have been used to indicate identical elements common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0008] Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by similar reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description or as limitations on the scope of the claims. Additionally, the illustrated example need not have all the aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in any other embodiment, even if not so illustrated or explicitly described.

[0009] Embodiments herein describe a distributed configuration system for configurable devices. Instead of relying solely on a central configuration manager circuit to distribute configuration information to various subsystems within a device, embodiments herein include configuration interface managers (CIMs) (also referred to as CIM circuits) that are distributed to different regions of the device, whether these regions are within a single integrated circuit or spread across multiple integrated circuits. Embodiments can still use the central configuration manager to enforce security on the system and provide a uniform application programming interface (API) for users to interface with. Additionally, the central configuration manager can provide the underlying infrastructure to parallelize the configuration information contained in the device image and distribute responsibility for analyzing and programming the regions to the CIMs.

[0010] In one embodiment, each domain in a configurable device has its own dedicated configuration interface that is accessed by its dedicated CIM. Furthermore, the CIMs can operate in parallel. This distributed architecture improves the time required to configure and bring up a device by orders of magnitude, without adding additional complexity to the user when designing their system.

[0011] 1 illustrates configuring a configurable device 100 using a distributed system, according to one embodiment. In this example, configurable device 100 includes a single integrated circuit (IC) 110. In one embodiment, IC 110 includes a heterogeneous computing system that includes different types of subsystems (e.g., NoC, data processing engine, memory controller, programmable logic, etc.) that are configured using configuration information in device image 105. For example, IC 110 can be an SoC or an application-specific integrated circuit (ASIC).

[0012] In another embodiment, IC 110 comprises a homogeneous computing system. While the distributed configuration system described herein may provide the greatest improvement for devices with heterogeneous computing systems (due to having a mix of various configuration partitions transferred through separate interfaces), embodiments herein may also improve the process of configuring homogeneous computing systems, especially as those systems become larger. For example, IC 110 may be a large field programmable array (FPGA) that includes programmable logic configured by device image 105.

[0013] In particular, configurable devices are not limited to having programmable logic. That is, embodiments herein may be applied to configurable devices that include or do not include programmable logic. The distributed configuration system described herein may be used in any configurable device that relies on a received device image 105 to configure at least one subsystem within the device before the device begins to perform user functions.

[0014] IC 110 includes a stream engine 115 (e.g., circuitry) that receives device images 105 for configuring device 100. Stream engine 115 is an example of a central configuration manager circuit; in other embodiments, the stream functionality may be implemented using back-to-back memory-mapped transfers at the physical interface level. Thus, stream engine 115 may be a memory-mapped engine that receives device images via memory-mapped data writes.

[0015] As shown, the stream engine 115 receives the device image 105, which consists of packetized configuration data, and then forwards each configuration (config) packet 125 to different areas within the IC 110. The stream engine 115 can function as a user interface with an API for communicating with an external host computing system (not shown). The stream engine 115 is described in more detail below, but in general, this hardware component distributes the configuration information contained in the device image 105 in the form of config packets 125 to various areas of the IC 110.

[0016] To deliver the config packets 125, the IC 110 includes a hardware network 120. In one embodiment, the network 120 is, but is not limited to, an NoC. For example, the IC 110 may have a dedicated configuration trace that is used to distribute the config packets 125 to different regions within the IC 110. The type of hardware network used can affect how stream data is transferred at the physical level from the central configuration manager (e.g., stream engine 115) to the distributed CIM circuits 130.

[0017] 1, IC 110 is subdivided into different regions (e.g., Region A and Region B). Although two regions are shown, IC 110 can be divided into any number of regions. One advantage of a distributed configuration system is that it easily scales with the size of configurable device 100. That is, as the size of IC 110 increases, additional regions can be added.

[0018] Each region in IC 110 includes a dedicated CIM circuit 130 for distributing configuration information to the subsystems in that region. That is, stream engine 115 can receive device image 105 and deliver packetized configuration information such that data used to configure the subsystems in region A is sent to CIM circuit 130A, and data used to configure the subsystems in region B is sent to CIM circuit 130B.

[0019] Although not shown here, CIM circuit 130 may have respective interfaces or ports to the subsystems in each region. For example, CIM circuit 130A may parse received config packet 125A and send configuration information to different circuits within the region. In this example, region A includes first circuit 135A and second circuit 135B. These circuits may be different (i.e., heterogeneous) circuits. For example, first circuit 135A may be a memory controller, and second circuit 135B may be an enhanced data processing engine. These circuits may use different types of interfaces to communicate with CIM circuit 130A and use different types of configuration data. Rather than having to parse and distribute configuration information to all subsystems within the IC, in this example, stream circuit 115 may forward the configuration information to each region, and it is then up to CIM circuit 130 to distribute the configuration information to the circuits within that region using different interfaces. However, in other embodiments, the first and second circuits 135A and 135B may be homogenous circuits (e.g., both may be memory controllers or both may be programmable logic blocks). Thus, embodiments herein may be used when regions have heterogeneous or homogenous circuits.

[0020] Furthermore, because stream circuit 115 distributes configuration information to different regions with dedicated CIM circuits 130, the CIM circuits 130 in each region can operate in parallel. That is, CIM circuit 130A can distribute configuration information to first and second circuits 135A and 135B, while CIM circuit 130B can distribute configuration information to third and fourth circuits 135C and 135D. In this manner, regions within IC 110 can be configured in parallel by dedicated CIM circuits 130.

[0021] 2A and 2B illustrate configuring multiple integrated circuits in a configurable device 200 using a distributed system, according to one embodiment. Unlike distributed device 100 of FIG. 1, configurable device 200 of FIG. 2A and 2B included multiple ICs, namely, IC 110, IC 205, and IC 210. These ICs may be located in the same package. Although three ICs are shown, configurable device 200 may include any number of ICs.

[0022] In configurable device 200A of FIG. 2A, ICs are arranged in a 3D stack. For example, IC 110 may be a base die, with ICs 205 and 210 stacked on top of the base die. For example, the base die may include peripherals and communication interfaces for communicating with an external host, while ICs 205 and 210 include different types of circuitry 220 (e.g., an array of programmable logic or data processing engines). The ICs may use through-vias to transmit data to each other.

[0023] The IC 110 in Figure 2A may be the same IC 110 as shown in Figure 1, including multiple regions, each containing a dedicated CIM circuit 130. Rather than being allocated 2D regions within the same IC as shown in Figure 1, in Figure 2A the CIM circuit is allocated a 3D region spanning three ICs. That is, CIM circuit 130A is allocated region A, which may include circuitry within IC 110 (not shown), circuit 220A within IC 205, and circuit 220C within IC 210. CIM circuit 130B is allocated region B, which may include circuitry within IC 110 (not shown), circuit 220B within IC 205, and circuit 220D within IC 210.

[0024] The circuits 220 in each of ICs 205 and 210 may be the same or different. In one example, circuits 220A and 220B in IC 205 may be the same (e.g., programmable logic), and circuits 220C and 220D in IC 210 may be the same (e.g., data processing engines). Furthermore, circuits 220A-D in both ICs 205 and 210 may be the same, e.g., all data processing engines.

[0025] While FIG. 2A shows a stack of ICs, in another embodiment, the ICs may be placed on an interposer (i.e., side-by-side), with the interposer providing a communication channel for transmitting data between the ICs. For example, IC 110 may be the anchor die, and ICs 205 and 210 are chiplets. In this example, ICs 205 and 210 may be placed on different sides of IC 110. The anchor die may include common blocks such as a processor subsystem (PS) or a memory subsystem (DDR controller). The chiplets may include dedicated logic such as a data processing engine, a high-speed transceiver, or a high-bandwidth memory. In that case, although the area is not a 3D area, each CIM circuit 130 may nevertheless be assigned an area that includes portions from each of the three ICs in FIG. 2A.

[0026] 2A illustrates using CIM circuitry 130 in one IC to configure circuitry 220 in a different IC. Thus, ICs 205 and 210 do not have their own CIM circuitry.

[0027] Like Figure 2A, Figure 2B shows a configurable device 200B having multiple ICs, but unlike Figure 2A, each IC has at least one CIM circuit 130. Furthermore, unlike Figure 2A, where a region extends across multiple ICs, in Figure 2B, a region may be confined within one IC.

[0028] In particular, the three ICs in FIG. 2B can be arranged as a 3D stack as shown in FIG. 2A or side-by-side on an interposer.

[0029] Network 120 within IC 110 can be used to forward config packets to other ICs 205 and 210. That is, in addition to identifying config packets for regions on IC 110, stream engine 115 also distributes config packets for regions within ICs 205 and 210. Because IC 205 includes two regions (regions C and D) with dedicated CIM circuits 130C and 130D, stream engine 115 sends config packet 125C to CIM circuit 130C to configure the circuitry in region C (not shown) and sends a different config packet 125D to CIM circuit 130D to configure the circuitry in region D (not shown).

[0030] However, IC 210 is not (or may be) divided into multiple regions. In this case, stream engine 115 sends config packet 125E to CIM circuit 130E to configure the circuits in IC 210. For example, IC 210 may be smaller than IC 205 or may have less configurable circuits than IC 210, and therefore IC 210 is not divided into multiple regions.

[0031] 2B shows a configurable device 200B that includes multiple ICs, where a central configuration manager (e.g., stream engine 115) on one of the ICs can distribute config packets 125 to CIM circuits 130 on different ICs, each of which can have two or more CIM circuits 130, depending on how many regions there are in the IC.

[0032] 3 is a flowchart of a method 300 for configuring a device using a distributed system, according to one embodiment. At block 305, a stream engine (e.g., a central configuration manager) receives a device image for configuring a configurable device. The device image can be received as streaming data or memory-mapped data.

[0033] A configurable device may include only one IC that includes multiple CIM circuits as shown in Figure 1, or a configurable device may include multiple ICs as shown in Figures 2A and 2B. In either case, in one embodiment, there is only one stream engine (i.e., only one central configuration manager) within the configurable device.

[0034] In block 310, the stream circuit configures a network within the configurable device. In one embodiment, the network is located on the same IC that includes the stream circuit. The stream circuit may first be configured so that the stream circuit distributes configuration information to the CIM circuit within the configurable device. For example, if the stream circuit uses an NoC to communicate with the CIM circuit, the device image may include data for configuring the NoC so that the NoC can communicate with the CIM circuit.

[0035] In one embodiment, the stream circuitry includes its own CIM circuitry for configuring the network. That is, the stream circuitry can identify configuration information in received device images that are intended to configure the network and forward this information to its CIM circuitry, which then configures the network. The network can be configured to send data not only to CIM circuitry on the same IC, but also to CIM circuitry on other ICs (if the configurable device has multiple ICs with their own CIM circuitry).

[0036] In block 315, the stream circuitry analyzes the device image to identify configuration information (e.g., configuration packets) for the CIM circuits within the configurable device. In one embodiment, the device image may include an embedded header that indicates which data is intended for which region. That is, a software tool within the host that generates and sends the device image to the configurable device can recognize the regions within the configurable device. Thus, when generating the device image, the software application can organize the device image such that configuration information for circuits within a particular region of the device is organized as packet data. Thus, when analyzing the device image, the stream circuitry can easily identify different portions of the device image that are destined for different regions (e.g., different CIM circuits), which may be arranged as packets of data. This is described in more detail in FIG. 5.

[0037] In one embodiment, packetization of configuration information within a device image may be performed by a stream circuit based on a dynamic scheduling algorithm of relocatable configuration contexts.

[0038] In block 320, the stream circuitry sends the config packets to the CIM circuits. That is, after identifying the data in the device image intended for the destination regions, the stream circuitry can forward the corresponding config packets to the dedicated CIM circuits in those regions. Thus, each region receives only the configuration information used to configure the circuits in that region.

[0039] In one embodiment, the configurable device includes at least two CIM circuits. These CIM circuits may be on the same IC or multiple ICs. Furthermore, the region may include an entire IC, a 2D region that includes only a small portion of an IC, or a 3D region that spans multiple ICs. Figure 2B shows an example where the region may include an entire IC (e.g., IC 210), Figure 1 shows a 2D region that covers a subportion of an IC (e.g., IC 110), and Figure 2A shows a 3D region that spans multiple ICs.

[0040] In one embodiment, communications between the stream circuit and the plurality of CIM circuits are encrypted such that each of the plurality of CIM circuits decrypts portions (e.g., configuration packets) received from the central configuration manager circuit. Further, in one embodiment, each of the plurality of CIM circuits is configured to perform an integrity check on portions (packets) received from the stream circuit.

[0041] In block 325, the CIM circuit forwards the config information to circuits within the domain assigned to the CIM circuit. That is, the CIM circuit analyzes the received packet, which may have configuration information for multiple subsystems within the domain, and identifies which configuration information should be sent to which subsystem. The CIM circuit may use different interfaces or ports for different subsystems within the domain if those subsystems are heterogeneous systems.

[0042] Advantageously, in method 300, the streaming circuitry is primarily responsible for streaming configuration information to the various CIM circuits as specified by the device image, with the actual processing and transfer of configuration data to the particular circuit being configured being delegated to the CIM.

[0043] In one embodiment, the CIM circuit operates in two modes: In the first mode, a direct memory access (DMA) circuit in the stream circuit distributes configuration information for a region as a continuous stream to the CIM circuit responsible for that region; once the configuration packets for a region are buffered in the CIM circuit, the CIM circuit can process the packets, and the stream circuit sends the configuration packets to the CIM circuit in the configurable device.

[0044] In the second mode, the stream circuitry copies constituent packets for all regions in a contiguous partition to DRAM a priori and instructs the CIM circuitry to simultaneously pull packets from those regions in DRAM. A contiguous partition is one in which all data within that partition is intended to be processed by a single CIM. Local storage within the CIM circuitry is used to store packets fetched by the CIM circuitry from DRAM for hashing and authentication before use.

[0045] FIG. 4 illustrates configuring a configurable device 400 using a distributed system, according to one embodiment. As shown, the configurable device 400 receives a device image 105 at the stream circuit 115. As described above, in addition to distributing configuration information in the device image 105 to different regions, the stream circuit 115 (e.g., a central configuration manager) can perform other functions. First, the stream circuit 115 can create a level of abstraction that remains consistent across devices. That is, the stream circuit 115 can maintain a consistent protocol for all functions performed by the stream circuit 115, regardless of the size of the device 400 and the combination of features in the device 400. Second, the stream circuit 115 can serve as a root-of-trust for the device 400. In one embodiment, the stream circuit 115 authenticates the device image 105 before it is delivered to the CIM circuit. Third, the stream circuit 115 can include debug interface logic as well as a debug packet controller to identify errors that may occur during the configuration process.

[0046] In one embodiment, the stream circuitry 115 is implemented within a processor that may be a general-purpose processor, however, in other embodiments, the stream circuitry 115 may be dedicated circuitry for performing the functions described herein.

[0047] Device 400 includes N regions corresponding to N CIMs 405. Here, region 0 is assumed to be located on the same IC as stream circuit 115. This region includes CIM circuit 405A, PS 410, NoC 415, and peripheral device 420.

[0048] The PS 410 may be a general-purpose processor including any number of cores. The PS 410 may be one or more processing subsystems that are also configured with a corresponding CIM, i.e., CIM circuit 405A.

[0049] Although not shown, NoC 415 may extend throughout device 400 to enable various components in device 400 to communicate with one another. For example, in one physical implementation, stream circuit 115 may be located in the upper right portion of an IC within configurable device 400, while CIMs 405B and 405C are located in the upper and lower left portions of the IC (or on separate ICs). However, using NoC 415, stream circuit 115 can still communicate with CIM circuits 405B and 405C in those regions. However, in an embodiment, stream circuit 115 may first be required to configure NoC 415 before it can send configuration information to CIM circuits 405B and 405C, as described above in block 310 of method 300.

[0050] Peripherals 420 may include I / O circuitry for communicating with external computing systems or devices. For example, peripherals 420 may include a DMA engine for retrieving memory from a host computing system.

[0051] Although shown as separate, in one embodiment, the CIM circuit 405A is part of the stream circuit 115. Customizing firmware within the stream circuit 115 (e.g., a central configuration manager) to configure each subsystem adds complexity, hinders optimization, and results in larger code size, inefficient execution, and verification difficulties. Because processing for a region is instead performed by the CIM, and the stream circuit simply streams packets to the CIM, a common portion of firmware can be used to push a configuration image to all regions on the device. These regions can contain different IP and functionality. Furthermore, including the CIM circuit within the stream circuit allows the same programming model to be employed for regions that communicate directly with or are integrated with the stream circuit on the same IC. Examples of configuration performed by the local CIM circuit 405A within the stream circuit 115 are configuration of the PS 410, NoC 415, and peripherals 420.

[0052] In this embodiment, Region 1 and Region n may contain similar circuit elements, but this is not a requirement. That is, both regions include programmable logic (PL) blocks 425, hard IP 430, interfaces to chiplets 440 (when using the configuration shown in FIG. 2A), and memory controllers 445. Alternatively, Region 1 may contain only programmable logic and Region n may contain only DPE segments.

[0053] CIM circuits 405B and 405C may include separate interfaces or ports to different circuit elements in Region 1 and Region n. Region 1 and Region n may be in the same IC as Region 0 or may be in separate ICs. For example, Region 0 may be located on a first IC and Regions 1 through n may be located on a second IC, or Region 0 may be located on a first IC, Region 1 may be located on a second IC, and Region n may be located on a third IC.

[0054] PL blocks 425 in regions 1 and n can contain any amount of programmable logic. Using configuration information in device image 105, CIM circuits 405B and 405C can configure PL blocks 425 to perform user-defined functions during operation.

[0055] The hard IP 430 may include any of a variety of enhanced circuits that may be configured using the device image 105 .

[0056] Data processing engine (DPE) segment 435 may include multiple DPEs, which may be arranged in a grid, cluster, or checkerboard pattern within device 400. Furthermore, each segment 435 may be any size and have any number of rows and columns formed by DPEs. In one embodiment, the DPEs within segment 435 are identical. That is, each of the DPEs (also called tiles or blocks) may have the same hardware components or circuitry. Furthermore, embodiments herein are not limited to DPEs. Alternatively, device 400 may include an array of any type of processing element; for example, a DPE may be a digital signal processing engine, a cryptographic engine, a forward error correction (FEC) engine, or other dedicated hardware for performing one or more specialized tasks.

[0057] Chiplet 440 may be part of an anchor / chiplet configuration such as that described above in Figure 2A. For example, CIM circuitry 405B may be tasked with transferring configuration information to chiplet 440A, and CIM circuitry 405C is tasked with transferring configuration information to chiplet 440B.

[0058] It would be performance and power inefficient to have the stream circuit 115 (e.g., a central configuration manager) involved in low-level data movement at the device level for configuration. Therefore, as explained above, the stream circuit 115 streams configuration information over a network (e.g., NoC 415) to CIM circuits 405 distributed across devices. By using hardware to stream configuration information directly to the CIM circuits 405, the stream circuit 115 does not create a bottleneck. Also, the config packets (which make up the continuous stream shown in FIG. 4) are transferred from the stream circuit to the CIM circuits 405 at full burst capacity, avoiding overloading the NoC 415 with many small, independent memory transfers.

[0059] Figure 5 illustrates a portion of a device image 105, according to one embodiment. Figure 5 illustrates a high-level organization that may be used in a device image 105 for a configurable device. The image 105 includes a boot header and multiple programming partitions, each addressed to a specific area within the configurable device. The boot header provides information used to authenticate access to the device and process the rest of the image 105, including authentication and decryption.

[0060] Partition 505 in device image 105 is a main partition that may always be present and contains, for example, platform loader and manager (PLM) firmware running on a processor that also contains streaming circuitry or a central configuration manager. In one embodiment, main partition 505 is loaded by read-only memory (ROM) in the processor, and the loading of the other partitions is done by PLM firmware along with CIM circuitry.

[0061] In this example, each subsequent partition 510 includes a secure partition header that is processed by the stream circuitry to establish keys and other configuration information used by the CIM circuitry to process the partition. The remainder of the partition 510 is divided into packets that the stream circuitry routes to specific CIM circuits (e.g., CIM a, CIM b, CIM c, etc.) for processing. The packet headers for the packets within partition 510 identify the target CIM circuit, so the stream circuitry knows the destination for each of the packets. In this way, the stream circuitry can packetize the data and forward the packets to specific CIM circuits, as described in block 315 of method 300.

[0062] Furthermore, the packet data in each packet within partition 510 is processed by the CIM circuits rather than the stream circuits, and therefore the processing of the configuration information in the data packets (and the forwarding of that configuration information to the particular circuits being configured) is delegated to the CIM circuits when the packets are received by those circuits.

[0063] Figure 6 illustrates a CIM packet 600 within a device image, according to one embodiment. That is, Figure 6 illustrates an example format for a packet within partition 510 of Figure 5. Packet 600 is divided into a header 605 and packet data 610 (payload). The first quadword in packet 600 specifies the target CIM (using the CIM ID), packet length, header length, and packet attributes.

[0064] In one embodiment, the length of packet 600 and header 605 is always a multiple of a quadword. Additionally, the least significant bit of the packet attribute can indicate whether the packet is the last packet in a partition that needs to be transferred using, for example, direct memory access (DMA).

[0065] The packet header 605 also includes a SHA hash (e.g., or any other suitable cryptographic element) for the next packet. Padding within the header 605 can be used to ensure that the packet length meets the requirements of the SHA-3 architecture. The last packet in one of the partitions 510 in Figure 5 may not include a SHA hash and padding because there is no next packet in that partition 510.

[0066] In one embodiment, the CIM packet 600 is hashed in its entirety, including the header 605 and the payload, i.e., packet data 610. In one embodiment, each CIM circuit includes sufficient internal storage to buffer at least two packets. Buffering the packet 600 within the CIM circuit also allows the packet 600 to be verified to ensure data integrity and decrypted to ensure data privacy.

[0067] In the foregoing, reference is made to the embodiments presented in this disclosure. However, the scope of the disclosure is not limited to the specific described embodiments. Instead, any combination of the described features and elements, whether associated with different embodiments or not, is contemplated for implementing and practicing the contemplated embodiments. Moreover, while the embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of the disclosure. Accordingly, the foregoing aspects, features, embodiments, and advantages are merely illustrative and are not considered elements or limitations of the appended claims unless expressly recited in the claims.

[0068] As will be appreciated by one skilled in the art, embodiments disclosed herein may be embodied as a system, method, or computer program product. Accordingly, aspects may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "module," or "system." Furthermore, aspects may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer-readable program code embodied therein.

[0069] Any combination of one or more computer-readable media may be utilized. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer-readable storage media include an electrical connection having one or more wires, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this specification, a computer-readable storage medium is any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0070] A computer-readable signal medium may include a propagated data signal in which computer-readable program code is embodied, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium is not a computer-readable storage medium but may be any computer-readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0071] The program code embodied on the computer readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

[0072] Computer program code for carrying out operations of aspects of the present disclosure may be written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Java, Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider).

[0073] Aspects of the present disclosure are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments presented in this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in the flowchart and / or block diagram blocks.

[0074] These computer program instructions may also be stored on a computer-readable storage medium, and the instructions may direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner to produce an article of manufacture including instructions that perform the functions / acts specified in the flowchart and / or block diagram blocks.

[0075] Computer program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process, such that the instructions executing on the computer or other programmable apparatus provide a process for performing the functions / acts specified in the flowchart and / or block diagram blocks.

[0076] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or acts or a combination of dedicated hardware and computer instructions.

[0077] The techniques described above can be illustrated in several non-limiting examples described below.

[0078] Example 1. A configurable device comprising: a central configuration manager circuit; a plurality of configuration interface manager (CIM) circuits connected to a central configuration manager circuit and distributed throughout the configurable devices; a central configuration manager circuit comprising: receiving a device image for configuring the configurable device; Analyzes device images to identify the configuration packets of multiple CIM circuits, configured to send a configuration packet to a plurality of CIM circuits; A configurable device, wherein the plurality of CIM circuits are configured to forward configuration packets to assigned regions of the configurable device.

[0079] Example 2. The configurable device of example 1, wherein the device image is received at least one of: (i) as streaming data at a central configuration manager circuit; or (ii) through memory-mapped data writes at a central configuration manager circuit.

[0080] Example 3. The configurable device of example 2, wherein the streaming data or memory-mapped data includes an embedded header that indicates which configuration data within the streaming data or memory-mapped data is intended for which of the allocated regions.

[0081] Example 4. The configurable device of example 3, wherein each of the plurality of CIM circuits is assigned to only one region, and each of the plurality of CIM circuits receives only configuration data intended for its assigned region.

[0082] Example 5. The configurable device of example 1 further comprising only one integrated circuit, wherein the allocated regions divide subsystems within the integrated circuit.

[0083] Example 6. The configurable device of example 1, further comprising a plurality of integrated circuits, wherein at least one of the allocated regions spans the plurality of integrated circuits.

[0084] Example 7. The configurable device of example 6, wherein at least two of the allocated regions span multiple integrated circuits.

[0085] Example 8. The configurable device of example 1, wherein the central configuration manager circuit is configured to configure a network within the configurable device using configuration information in the device image before sending the configuration packets to the plurality of CIM circuits, the network communicatively coupling the plurality of CIM circuits to the central configuration manager.

[0086] Example 9. The configurable device of example 8, wherein the central configuration manager circuit comprises one of a plurality of CIM circuits that configures the network using the configuration information.

[0087] Example 10. A method comprising: receiving, at a central configuration manager circuit, a device image for configuring a configurable device; analyzing the device image to identify configuration packets for a plurality of CIM circuits in the configurable device; transmitting a configuration packet from a central configuration manager circuit to a plurality of CIM circuits; forwarding, by the plurality of CIM circuits, the configuration packet to an assigned region of the configurable device; A method comprising:

[0088] Example 11. The method of example 10, wherein the device image is received at least one of: (i) as streaming data at a central configuration manager circuit; or (ii) through memory-mapped data writes at a central configuration manager circuit.

[0089] Example 12. The method of Example 11, wherein the streaming data or memory-mapped data includes an embedded header that indicates which configuration data within the streaming data or memory-mapped data is intended for which of the allocated regions.

[0090] Example 13. The method of example 12, wherein each of the plurality of CIM circuits is assigned to only one region, and each of the plurality of CIM circuits receives only configuration data intended for its assigned region.

[0091] Example 14. The method of example 10, wherein the configurable device includes only one integrated circuit, and the allocated regions divide subsystems within the integrated circuit.

[0092] Example 15. The method of example 10, wherein the configurable device includes multiple integrated circuits, and at least one of the allocated regions spans the multiple integrated circuits.

[0093] Example 16. The method of example 10, further comprising configuring a network within the configurable device using configuration information within the device image prior to sending the configuration packets to the plurality of CIM circuits, the network communicatively coupling the plurality of CIM circuits to a central configuration manager.

[0094] Example 17. The method of example 16, wherein the central configuration manager circuit comprises one of a plurality of CIM circuits that configures the network using the configuration information.

[0095] Example 18. A configurable device, comprising: a central configuration manager circuit; Network and a plurality of configuration interface manager (CIM) circuits connected via a network to a central configuration manager circuit; Equipped with The central configuration manager circuit receiving a device image for configuring the configurable device; Identifying a portion of the device image intended for each of the plurality of CIM circuits; configured to transmit portions of the device image to a plurality of CIM circuits; A configurable device, wherein the plurality of CIM circuits are configured to transfer portions of the device image to assigned regions of the configurable device.

[0096] Example 19. The configurable device of example 18, wherein the device image includes an embedded header that indicates which portion of the device image is intended for which of the allocated regions.

[0097] Embodiment 20. Communications between a central configuration manager circuit and a plurality of CIM circuits are encrypted, and each of the plurality of CIM circuits decrypts a portion received from the central configuration manager circuit; 19. The configurable device of example 18, wherein each of the plurality of CIM circuits is configured to perform an integrity check on the portion received from the central configuration manager circuit.

[0098] While the above is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A configurable device comprising: a central configuration manager circuit; a plurality of configuration interface manager (CIM) circuits connected to the central configuration manager circuit and distributed throughout the configurable devices; Equipped with the central configuration manager circuit receiving a device image for configuring the configurable device; analyzing the device image to identify configuration packets of the plurality of CIM circuits; configured to transmit the configuration packet to the plurality of CIM circuits; The configurable device, wherein the plurality of CIM circuits are configured to forward the configuration packets to assigned regions of the configurable device.

2. 10. The configurable device of claim 1, wherein the device image is received at least one of: (i) as streaming data at the central configuration manager circuit; or (ii) through memory-mapped data writes at the central configuration manager circuit.

3. The configurable device of claim 1 further comprising only one integrated circuit, the allocated regions dividing subsystems within the integrated circuit.

4. The configurable device of claim 1 , further comprising a plurality of integrated circuits, wherein at least one of the allocated regions spans across the plurality of integrated circuits.

5. The configurable device of claim 4 , wherein at least two of the allocated regions span across the plurality of integrated circuits.

6. 2. The configurable device of claim 1, wherein the central configuration manager circuit is configured to configure a network within the configurable device using configuration information in the device image before sending the configuration packets to the plurality of CIM circuits, the network communicatively coupling the plurality of CIM circuits to the central configuration manager.

7. 1. A method comprising: receiving, at a central configuration manager circuit, a device image for configuring a configurable device; analyzing the device image to identify configuration packets for a plurality of CIM circuits within the configurable device; transmitting said configuration packet from said central configuration manager circuit to said plurality of CIM circuits; forwarding, by the plurality of CIM circuits, the configuration packet to an assigned region of the configurable device; A method comprising:

8. 8. The method of claim 7, wherein the device image is received at least one of: (i) as streaming data at the central configuration manager circuit; or (ii) through memory-mapped data writes at the central configuration manager circuit.

9. 9. The method of claim 8, wherein the streaming data or the memory-mapped data includes an embedded header that indicates which configuration data within the streaming data or the memory-mapped data is intended for which of the allocated regions.

10. The method of claim 7 , wherein the configurable device includes only one integrated circuit, and the allocated regions divide subsystems within the integrated circuit.

11. The method of claim 7 , wherein the configurable device includes multiple integrated circuits, and at least one of the allocated regions spans across the multiple integrated circuits.

12. 8. The method of claim 7, further comprising configuring a network within the configurable device using configuration information in the device image prior to sending the configuration packets to the plurality of CIM circuits, the network communicatively coupling the plurality of CIM circuits to the central configuration manager.

13. 1. A configurable device comprising: a central configuration manager circuit; Network and a plurality of configuration interface manager (CIM) circuits connected to said central configuration manager circuit via said network; Equipped with the central configuration manager circuit receiving a device image for configuring the configurable device; identifying a portion of the device image intended for each of the plurality of CIM circuits; configured to transmit the portions of the device image to the plurality of CIM circuits; The configurable device, wherein the plurality of CIM circuits are configured to transfer the portions of the device image to assigned regions of the configurable device.

14. The configurable device of claim 13 , wherein the device image includes an embedded header that indicates which portions of the device image are intended for which of the allocated regions.

15. communications between the central configuration manager circuit and the plurality of CIM circuits are encrypted, and each of the plurality of CIM circuits decrypts the portion received from the central configuration manager circuit; 14. The configurable device of claim 13, wherein each of the plurality of CIM circuits is configured to perform an integrity check on the portion received from the central configuration manager circuit.

Images