Real-time CPU availability monitoring

Abstract

One or more processors of the computing device may determine processor availability of the one or more processors based at least in part on the one or more processor statistics and the one or more processor mode statistics. The one or more processors may determine whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability of the one or more processors. In response to determining that the one or more processors are available to perform the one or more tasks, the one or more processors may perform the one or more tasks with the one or more processors.

Description

[Technical Field]

[0001] Related Applications This application claims priority to U.S. Patent Application No. 18 / 175,499, filed February 27, 2023, which in turn claims priority to U.S. Provisional Patent Application No. 63 / 371,375, filed August 12, 2022, the entire contents of each of which are incorporated herein by reference. [Background technology]

[0002] Vehicles may include a so-called "head unit" or other integrated computing device that presents an interface (e.g., a graphical user interface - GUI) for controlling vehicle systems, such as the heating, ventilation, and air conditioning (HVAC) system, the lighting system (which controls interior and / or exterior lighting), the entertainment system, the seating system (which controls the position of the driver's seat and / or passenger seats), etc. The head unit may run applications such as a virtual assistant application, a navigation application, a music application, and applications that provide various functions of the head unit. During head unit startup, various applications and processes may compete to perform tasks. Summary of the Invention

[0003] Generally, this disclosure describes techniques for monitoring real-time processor availability of a computing device, such as a vehicle head unit. When a computing device starts up, various applications and / or services may perform various tasks so that the applications and / or services are available to a user of the computing device, which may place a high processing load on the processor of the computing device. A job scheduler may schedule tasks to be executed based on processor availability and task priority, and may pause scheduling of new tasks to be executed by the processor of the computing device until the job scheduler determines that the processor's processor availability percentage is above a specified threshold.

[0004] According to aspects of the present disclosure, a computing device may be capable of scheduling tasks based on processing loads of processors of the computing device. The computing device may determine processor availability of one or more processors of the computing device. The computing device may determine whether one or more processors are available to execute one or more tasks based at least in part on the processor availability of the one or more processors. The computing device may schedule execution of one or more tasks in response to determining that one or more processors are available to execute one or more tasks.

[0005] In some aspects, techniques described herein relate to a method that includes determining, by one or more processors, processor availability for one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determining, by the one or more processors, whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability for the one or more processors; and executing, by the one or more processors, the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0006] In some aspects, techniques described herein relate to a computing device comprising: a memory; and one or more processors communicatively coupled to the memory, wherein the one or more processors are configured to: determine processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determine whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability for the one or more processors; and perform the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0007] In some aspects, the techniques described herein relate to an apparatus comprising: means for determining processor availability for one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; means for determining whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability for the one or more processors; and means for performing the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0008] In some aspects, techniques described herein relate to a non-transitory computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors of a computing device to: determine processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determine whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability for the one or more processors; and perform the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0009] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram illustrating an example computing device 102 configured to perform various aspects of the techniques described in this disclosure. [Figure 2A]2 is a block diagram illustrating an embodiment of the computing device of FIG. 1 in more detail. [Figure 2B] 2 is a block diagram illustrating an embodiment of the computing device of FIG. 1 in more detail. [Figure 3] 2 is a flowchart illustrating an example operation of the example computing device of FIG. 1 for managing disk access usage of applications. DETAILED DESCRIPTION OF THE INVENTION

[0011] 1 is a block diagram illustrating an example computing device 102 configured to perform various aspects of the techniques described in this disclosure. In the example of FIG. 1, computing device 102 may be a head unit of vehicle 100. In other examples, computing device 102 may be a mobile computing device, a smartphone, a tablet computer, a wearable computing device, a laptop computer, a desktop computer, a server, or any other suitable computing device.

[0012] In the following description, it is assumed that vehicle 100 is an automobile. However, the techniques described in this disclosure also apply to any type of vehicle capable of carrying one or more occupants from place to place, such as motorcycles, buses, recreational vehicles (RVs), semi-trailer trucks, tractors or other types of agricultural equipment, trains, airplanes, drones, helicopters, and personal transportation vehicles. Furthermore, the techniques described in this disclosure may also apply to any type of computing device, such as a laptop computer, desktop computer, smartphone, wearable device, tablet computer, or any other device that may or may not be included in a vehicle.

[0013] 1, computing device 102 includes one or more processors 112, a graphics processing unit (GPU) 114, and memory 116. In some embodiments, one or more processors 112, GPU 114, and a transceiver module (not shown in FIG. 1) may be formed as an integrated circuit (IC). For example, the IC may be considered a processing chip within a chip package and may be a system-on-chip (SoC).

[0014] Examples of the one or more processors 112 and GPU 114 include, but are not limited to, one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. The one or more processors 112 may represent the central processing unit (CPU) of the vehicle 100. In some embodiments, the GPU 114 may be dedicated hardware including integrated and / or discrete logic circuits that provide the GPU 114 with massively parallel processing capabilities suitable for graphics processing. In some instances, the GPU 114 may also have general-purpose processing capabilities and may be referred to as a general-purpose GPU (GPGPU) when performing general-purpose processing tasks (i.e., non-graphics-related tasks). While illustrated as a dedicated GPU 114, the GPU 114 may represent an integrated GPU integrated into an underlying circuit board (such as a so-called "motherboard") or otherwise incorporated into one or more processors 112.

[0015] In some embodiments, one or more processors 112 may include processor cores 118A-118M (“processor cores 118”). Each of the processor cores may be a separate processing unit of one or more processors 112 on a single integrated circuit, and one or more processors 112 may execute instructions for the separate processor cores 118 simultaneously.

[0016] The one or more processors 112 may execute an operating system (OS) 130 and various types of applications 125A-125N (“applications 125”) stored in memory 116. Examples of applications 125 include a virtual assistant application, a navigation application such as mapping, a music application, a video application, a dashcam application, an over-the-air (OTA) update application, or other applications that generate visual objects for display. Memory 116 may function as system memory for computing device 102 and may store execution instructions for applications 125. When an application is executed by one or more processors 112, the one or more processors 112 generate graphics data for image content to display. The one or more processors 112 may send the graphics data for image content to GPU 114 for further processing based on instructions or commands sent by the one or more processors 112 to GPU 114. In some examples, one or more processors 112 may also execute applications that do not generate visual objects for display. For example, one or more processors 112 may execute background services, eg, background services that act as core components of other applications that generate visual objects for display.

[0017] The one or more processors 112 may communicate with the GPU 114 according to an application programming interface (API). Furthermore, the techniques described in this disclosure need not function according to an API; the one or more processors 112 and the GPU 114 may utilize any technique for communicating with the GPU 114.

[0018] Memory 116 may represent the memory of vehicle 100. Memory 116 may comprise one or more computer-readable storage media. Examples of memory 116 include one or more solid-state storage devices that can be used to carry or store desired program code in the form of instructions and / or data structures and that can be accessed by a computer or processor.

[0019] In some aspects, memory 116 may include instructions that cause one or more processors 112 to perform functions that are ascribed to one or more processors 112 in this disclosure. Thus, memory 116 may be a non-transitory computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors (e.g., one or more processors 112) to perform various functions.

[0020] Memory 116 is a non-transitory storage medium. The term "non-transitory" indicates that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be interpreted to mean that memory 116 is non-removable or that its contents are static. As one example, memory 116 may be removed from vehicle 100 and moved to another device, such as in the case of a Secure Digital (SD) card or Universal Serial Bus (USB) mass storage device. As another example, memory substantially similar to memory 116 may be inserted into autonomous vehicle 100. In particular examples, non-transitory storage media may store data that may change over time.

[0021] 1 , vehicle 100 may include vehicle systems 126. Vehicle systems 126 may include a heating, ventilation, and air conditioning (HVAC) system, a climate control system (which may include, for example, heated and / or cooled seats in addition to an HVAC system), a lighting system (which provides interior and / or exterior lighting), a seat control system (which adjusts the position of passenger seats), a mirror control system (which controls interior and / or exterior mirrors, including rearview mirrors, side mirrors, visor mirrors, etc.), a windshield wiper control system, an entertainment system (which controls radio playback, video playback, image display, etc.), safety assistance systems (which control parking assistance, backing assistance, etc.), a sunroof / moonroof control system (which controls a sunroof and / or moonroof), and any other type of vehicle system controllable via one or more processors 112. An example of vehicle system 126 may be an electronic control unit (ECU), which may control any of the aforementioned embodiments of vehicle system 126.

[0022] As further shown in the example of FIG. 1 , vehicle 100 may include a display 120 and a user interface 122, which may be integrated within computing device 102 or communicatively connected to computing device 102. Display 120 may represent any type of reflective passive screen onto which an image may be projected, or a reflective, emissive, or transmissive active display capable of displaying an image, such as a light-emitting diode (LED) display, an organic LED (OLED) display, a liquid crystal display (LCD), or any other type of active display. While vehicle 100 is shown as including a single display 120, it may include multiple displays that may be located throughout the cabin of vehicle 100. In some examples, a passive version of display 120 or an active version of a particular type of display 120 (e.g., an OLED display) may be integrated into a seat, a table, a roof liner, a floor, a window (or a wall in the case of a vehicle with no or few windows), or other aspect of the vehicle's cabin. If display 120 represents a passive display, display 120 may also include a projector or other image projection device capable of projecting or otherwise reproducing an image onto passive display 120. Additionally, display 120 may include a display integrated into the driver's side dashboard that virtually represents a physical quantity gauge cluster (showing speed, rpm, engine temperature, etc.).

[0023] Display 120 may also represent a display in wired or wireless communication with autonomous vehicle 100. Display 120 may represent a computing device such as, for example, a laptop computer, a head-up display, a head-mounted display, an augmented reality computing device or display (such as "smart glasses"), a virtual reality computing device or display, a mobile phone (including so-called "smartphones"), a tablet computer, a gaming system, or another type of computing device that can function as an extension of, or in place of, a display integrated into vehicle 100.

[0024] User interface 122 may represent any type of physical or virtual interface with which a user may interface to control various functions of vehicle 100. User interface 122 may include physical buttons, knobs, sliders, or other physical control implementations. User interface (UI) 122 may also include a virtual interface whereby an occupant of vehicle 100 interacts with virtual buttons, knobs, sliders, or other virtual interface elements, by way of example, via a touch-sensitive screen or via a touchless interface. An occupant may interface with user interface 122 to control one or more of the air within vehicle 100, audio playback by vehicle 100, video playback by vehicle 100, communications through vehicle 100 (such as cellular phone calls), or any other operation capable of being performed by vehicle 100.

[0025] User interface 122 may also represent an interface extended to display 120 when functioning as an extension of or in place of a display integrated into vehicle 100. That is, user interface 122 may include a virtual interface presented via a heads-up display (HUD), an augmented reality computing device, a virtual reality computing device or display, a tablet computer, or any other of the various types of augmented displays listed above.

[0026] In the context of vehicle 100, user interface 122 may further represent physical elements used to manually or semi-manually control vehicle 100. For example, user interface 122 may include one or more steering wheels for controlling the direction of travel of vehicle 100, one or more pedals for controlling the speed of travel of vehicle 100, one or more handbrakes, etc.

[0027] 1 , one or more processors 112, GPU 114, memory 116, display 120, and user interface 122 may collectively represent, at least in part, what is referred to as computing device 102. In the context of an automobile, computing device 102 may represent any integrated or separate computing device that can interface with various aspects of vehicle 100 (e.g., vehicle systems 126) and / or provide entertainment and / or information about vehicle 100 to occupants (such a head unit may be referred to as an “infotainment unit” or “infotainment system”).

[0028] Each processor core of processor cores 118 may be associated with a respective CPU frequency policy, which is also referred to herein as a CPU statistic or processor statistic. Such CPU frequency policies may be stored on a disk of computing device 102, such as in memory 116. The kernel of operating system 130 may expose available CPU frequency policies, which are files in a CPU frequency policy directory. In some embodiments, the available CPU frequency policies reside in memory 116 at the path / sys / devices / system / cpu / cpufreq / policy{M}, where M is a policy ID. Each policy directory contains the following files related to the CPU processor statistics for a given policy: related_cpus: IDs of online / offline CPU cores related to the policy. affected_cpus: IDs of online CPU cores affected by the policy. · cpuinfo_max_freq: The maximum CPU frequency at which the policy can run. ·scaling_max_freq: The maximum CPU frequency at which the policy can run. cpuinfo_cur_freq: The current CPU frequency obtained from the hardware. This file cannot be present if the actual frequency cannot be determined. scaling_cur_freq: The frequency of the most recent P-state requested by the scaling driver from the hardware. This may be the frequency the CPU is actually running at. · stats / time_in_state: The amount of CPU time spent at the various frequencies supported by the policy since the system was started or since the frequency statistics were reset.

[0029] The contents of the related_cpus, cpuinfo_max_freq, and scaling_max_freq files are static, meaning they do not change across system boots. Thus, these files may be read once after boot and may not need to be read thereafter.

[0030] The cpuinfo_cur_freq and scaling_cur_freq files may specify the frequency at which the CPU is running at any given moment. However, if operating system 130 monitors the CPU frequency of one or more processors 112 by periodically polling these files, the frequencies reported in these files may not accurately represent the frequency at which the CPU ran between polling intervals.

[0031] The stats / time_in_state file determines the amount of CPU time spent at various frequencies since the system booted or a frequency reset was performed. The statistics provided in this file can be used to derive the CPU time spent at various frequencies between two different polling intervals. However, the stats / time_in_state file may only be available if the kernel setting CONFIG_CPU_FREQ_STAT is enabled. Furthermore, this file may report the CPU time spent at various frequencies even if the processor cores associated with a CPU frequency policy or all processor cores are disabled.

[0032] In some embodiments, one or more processors 112 may also be associated with processor mode statistics, which may include statistics regarding the amount of time one or more processors 112 spend in each of a plurality of processor modes. For example, the kernel may expose in the / proc / stat file the amount of CPU time spent in each CPU mode since system startup or since the CPU was enabled for all online CPU cores. Thus, this file may include the amount of CPU time each of the processor cores 118 spent on idle tasks. One or more processors 112 may execute the operating system 130 to monitor CPU availability by periodically polling the / proc / stat file and may use the statistics reported in this file to derive the CPU time spent by one or more of the processor cores 118 in non-idle and idle modes between two polling periods. CPU time spent in various CPU modes is not reported in the / proc / stat file for disabled CPU cores, and when a previously disabled CPU core is re-enabled, the CPU time spent in various CPU modes is reset in the / proc / stat file.

[0033] Because CPU resource utilization is dynamic and can depend on scheduled tasks and the implementation of one or more task schedulers for the CPU, predicting future CPU load or CPU availability can be difficult. Recent past CPU load can be used to determine load stability and CPU availability. If the CPU load is stable over a period of time, the CPU utilization over that period can be used as an indicator of CPU availability.

[0034] If a system has multiple CPU cores with different core sizes, the current operating frequency of each CPU core may be less than the corresponding maximum operating frequency, and thus the current availability of each CPU core is scaled relative to the maximum CPU frequency.

[0035] According to aspects of the present disclosure, an application, such as application 125A, may schedule one or more tasks to be executed by one or more processors 112. Operating system 130 may execute on one or more processors 112 to monitor statistics of one or more processors 112, for example, by monitoring one or more processor statistics and / or processor mode statistics, to determine whether one or more processors 112 are available to execute one or more tasks. In response to determining that one or more processors 112 are available to execute one or more tasks, one or more processors 112 may execute operating system 130 to schedule execution of the one or more tasks by one or more processors 112 or cause one or more processors 112 to execute the one or more tasks.

[0036] To determine whether one or more processors 112 are available to perform one or more tasks, operating system 130 may perform on one or more processors 112 periodic calculations, such as every N seconds, of a processor availability percentage, such as the processor availability percentage of a processor core among processor cores 118, using the following formula:

number

[0037] In equation (1), for a given one of processor cores 118, the current CPU frequency may be the current processor frequency of the processor core, and the maximum CPU frequency may be the maximum core frequency of the processor core. The milliseconds spent on idle tasks may be the amount of time the processor core has spent in an idle state since the availability percentage of the processor core was last determined, e.g., the amount of time spent in an idle state out of the last N seconds.

[0038] Furthermore, because N in equation (1) is specified in seconds, and because the time spent in the idle task in equation (1) is specified as milliseconds spent in the idle task, N is multiplied by 1000 in the numerator and denominator of equation (1). If N and / or the time spent in the idle task were specified in other units of time, N could be multiplied by a different number. For example, if the time spent in the idle task in equation (1) were specified in nanoseconds, N in equation (1) could be multiplied by 100.

[0039] In some embodiments, operating system 130 may execute on one or more processors 112 to determine the current processor frequency of a processor core by calculating the current average processor frequency from the processor time spent at various frequencies that the kernel of operating system 130 reports in the processor core's processor statistics (e.g., file / sys / devices / system / cpu / cpufreq / policy{M} / time_in_state, where M is a policy ID). Operating system 130 may read the maximum processor frequency of a processor core from either the cpuinfo_max_freq file or the scaling_max_freq file, which reside in location / sys / devices / system / cpu / cpufreq / policy{M}, where M is a policy ID. Operating system 130 may read the processor time spent on idle tasks, and the total processor time may be read from the processor mode statistics (e.g., file / proc / stat).

[0040] In an embodiment in which a CPU, such as one or more processors 112, has multiple processor cores 118 (e.g., processor cores a-z) with different operating frequencies, operating system 130 may execute on one or more processors 112 to calculate the average processor availability percentage for one or more processors 112 every N seconds using the following formula:

number

[0041] In this equation (2), AP i is the current availability percentage of processor core i determined using equation (1), and F i is the maximum processor frequency of processor core i. As shown in equation (2), for one or more processors 112 having multiple processor cores 118 a through z, the average processor availability percentage of one or more processors 112 is a function of multiplying the current availability percentage of the processor core by the maximum processor frequency of each of the processor cores 118 and dividing the sum of the results by the sum of the maximum processor frequencies of each of the processor cores 118.

[0042] In some embodiments, if the average CPU availability percentage for a specified period, such as 30 seconds, 60 seconds, etc., is within 5%, the operating system 130 may determine that the CPU load is stable, and the operating system 130 may use the average CPU availability percentage as an indicator of CPU availability.

[0043] Processor cores 118 may not always operate at their respective maximum processor frequencies. The upper limit of the operating frequency of a processor core 118 may depend on various factors, such as the current processor scheduling policy or thermal throttling. Thus, when determining the processor availability of a processor core, one or more processors 112 may consider the achievable processor frequency of the processor core 118, which may be based on historical processor statistics.

[0044] In some embodiments, one or more processors 112 may track achievable processor frequencies per processor scheduling policy and use such information when calculating processor availability for a processor core 118 given the current processor scheduling policy. For example, in equations (1) and (2) above, the maximum processor frequency may be the maximum processor frequency specified in the processor frequency policy and / or the maximum achievable processor frequency for the processor core. Furthermore, in some embodiments, equations (1) and (2) may be updated to take into account information such as processor thermal information to provide more accurate information about processor availability.

[0045] In this manner, operating system 130 may be able to determine processor availability for one or more processors 112. For one or more tasks scheduled for execution by one or more processors 112, operating system 130 may determine whether one or more processors 112 have availability to execute the one or more tasks based on the processor statistics and processor mode statistics, such as by determining an average processor availability percentage for one or more processors 112. If operating system 130 determines that the average processor availability percentage for one or more processors 112 is above a specified threshold, such as 70%, operating system 130 may determine that one or more processors 112 have availability to execute the one or more tasks, and operating system 130 may schedule execution of the one or more tasks on one or more processors 112.

[0046] In some embodiments, processor core(s) 118 may include a big processor core and a little processor core. That is, processor core(s) 118 may include one or more little processor cores designed for power efficiency and one or more big processor cores designed for computational performance. In some embodiments, the big processor cores and little processor cores are arranged in a big.little design, and such big processor cores and little processor cores may be arranged in any suitable configuration, such as cluster switched, in-kernel switched, and heterogeneous multiprocessing. One or more processors 112 are also referred to as central processing units (CPUs) throughout this disclosure.

[0047] In a cluster switch, processor cores 118 are arranged into a big processor core cluster and a LITTLE processor core cluster that are identical in size, and at any given time, only one cluster of a big.LITTLE cluster pair can be online. That is, considering a pair of a big cluster of big processor cores and a LITTLE cluster of LITTLE processor cores, only one of the two clusters of the cluster pair is online at a given time. Each cluster of processor cores can be associated with a CPU frequency policy, and one or more processors 112 can execute the operating system 130 to determine a current CPU frequency from the CPU frequency policy belonging to the online cluster of processor cores 118. One or more processors 112 can also execute the operating system to determine a maximum CPU frequency from the CPU frequency policy belonging to the cluster including the big processor core. Thus, one or more processors 112 can execute the operating system 130 to calculate CPU availability using equations (1) and (2).

[0048] When processor cores 118 are arranged into multiple big.LITTLE cluster pairs in a cluster switch configuration, one or more processors 112 may execute operating system 130 to determine a pair-to-pair mapping of big clusters and LITTLE clusters (i.e., which big clusters of processor cores 118 are paired with which LITTLE clusters of processor cores 118) and calculate CPU availability using equations (1) and (2). Such pair-to-pair mapping of big clusters and LITTLE clusters may be configurable as a resource overlay configuration. The mapping may be specific to a given system-on-chip (SoC) (e.g., one or more processors 112) and scheduler implementation. Because the pair-to-pair mapping of big clusters and LITTLE clusters may not change during runtime of the computing device 102, operating system 130 does not need to update the pair-to-pair mapping of big clusters and LITTLE clusters during runtime.

[0049] In the in-kernel switch configuration, the kernel of the operating system 130 may pair the big and little processor cores of the processor cores 118 as a single virtual core (or logical core), and the kernel of the operating system 130 may maintain one CPU frequency policy for each virtual core. The CPU frequency policy of a virtual core determines the current CPU frequency and the maximum CPU frequency based on the online core and the big core, respectively. Thus, when the processor cores 118 are arranged according to the in-kernel switch configuration, one or more processors 112 may execute the operating system 130 to calculate the CPU availability of the one or more processors 112 using equations (1) and (2) based on the CPU frequency policy of the currently online virtual core.

[0050] In a heterogeneous multiprocessing configuration, all processor cores 118 may be available at all times, and a kernel scheduler of operating system 130 may schedule tasks for processor cores 118 based on, for example, the CPU load of one or more processors 112. When processor cores 118 are arranged according to a heterogeneous multiprocessing configuration, one or more processors 112 may execute operating system 130 to calculate the CPU availability of one or more processors 112 using equations (1) and (2) based on the CPU frequency policy of the processor cores 118.

[0051] In a virtualized environment, the kernel of a guest operating system may provide CPU frequency information for the virtual CPUs assigned to the guest operating system. One or more processors 112 may execute operating system 130 to calculate the CPU availability of the virtual CPUs using equations (1) and (2) based on such information provided by the kernel of the guest operating system. Thus, the average CPU availability percentage remains valid from which the availability of the virtual CPUs assigned to the guest OS is calculated.

[0052] In a virtualized environment, CPU steal time can vary based on the amount of time a guest operating system spends waiting for a physical processor while the hypervisor provides another virtual processor. CPU steal time can affect the CPU availability percentage of a guest operating system. Therefore, calculations of CPU availability in a virtualized environment can include CPU steal time. Therefore, the average CPU availability percentage in a virtualized environment can reflect the actual percentage of CPU resources available to applications / services running in the guest operating systems.

[0053] In some embodiments, the kernel of operating system 130 may provide a mechanism for assigning a set of CPUs (e.g., one or more processors 112) and memory nodes that point to online nodes containing memory (e.g., memory 116) to a set of tasks. Such a mechanism is referred to as a CPU set or cpuset. Operating system 130 may provide the following CPU sets available to all applications 125, depending on the state of the applications: Top App: The foreground application running with user focus. · Foreground: All foreground applications. · Background: All background applications.

[0054] Each CPU set may be associated with a CPU frequency policy, and one or more processors 112 may execute operating system 130 to determine processor availability for the CPU set based on the CPU frequency policy associated with the CPU set. The processors available to each CPU set (e.g., processor cores 118 of one or more processors 112) may vary based on system configuration. Generally, the top app CPU set includes all available processor cores 118, while the background CPU set includes little ones of the processor cores 118.

[0055] Foreground applications among applications 125 may use dedicated CPU sets configured as top app CPU sets or foreground CPU sets, which may be pre-set by the manufacturer of computing device 102. The dedicated CPU sets may guarantee any applications among applications 125 running in the foreground exclusive access to processor cores 118 in those CPU sets. When an application switches to the background, the switched-to background application may lose access to processor cores 118 in those CPU sets. This mechanism of guaranteeing dedicated CPU sets to foreground applications may improve the performance of user-facing applications in the foreground.

[0056] 2A and 2B are block diagrams illustrating an embodiment of computing device 102 of FIG. 1 in more detail. Computing device 202A shown in the embodiment of FIG. 2A is one embodiment of computing device 102 shown in FIG. 1. Computing device 202A may include one or more processors 212, memory 216, a display 220, and a UI 222. One or more processors 212 are an embodiment of one or more processors 112 shown in FIG. 1 and include processor cores 218A-218M (processor cores 218), which are an embodiment of processor core 118 shown in FIG. 1. Memory 216 is an embodiment of memory 116 of FIG. 1. Display 220 is an embodiment of display 120 of FIG. 1. UI 222 is an embodiment of UI 122 of FIG. 1. Memory 216 may include an application 225, which is an example of one of applications 125 shown in FIG. 1, an operating system 230, which is an example of operating system 130 in FIG. 1, and system files 236.

[0057] 2A , operating system 230 includes performance manager 232 and operating system services 234. One or more processors 212 may execute software applications 225 to register processor availability change listeners with performance manager 232 and / or remove processor availability change listeners from performance manager 232. For example, to execute one or more tasks on one or more processors 212, software application 225 may register a processor availability change listener with performance manager 232 to receive notification of changes in processor availability of one or more processors 212.

[0058] In response to software application 225 registering a processor availability change listener with performance manager 232, one or more processors 212 may execute performance manager 232 to send a request to operating system service 234 to begin monitoring processor availability of one or more processors 212. The request may indicate a current listener ID, which may be unique per listener and per instance of performance manager 232, lower and upper bounds for the processor availability percentage, and a timeout value.

[0059] In response to the listener being registered, one or more processors 212 may execute operating system services 234 to periodically determine the average processor availability percentage of one or more processors 212, for example, every N seconds, according to equations (1) and (2). For example, N seconds may be 30 seconds, 45 seconds, 60 seconds, etc.

[0060] Each time operating system service 234 determines the average processor availability percentage of one or more processors 212, operating system service 234 may read the latest processor statistics from system file 236. Each time operating system service 234 determines the average processor availability percentage of one or more processors 212, operating system service 234 may determine whether the average processor availability percentage has stabilized and whether the average processor availability percentage has exceeded / fallen one of the specified limits. If operating system service 234 determines that the average processor availability percentage has exceeded / fallen one of the limits, operating system service 234 may notify performance manager 232 that the average processor availability percentage has exceeded / fallen one of the specified limits.

[0061] In response to receiving a notification from operating system services 234 that the average processor availability percentage has exceeded / fallen below one of the specified limits, one or more processors 212 may execute performance manager 232 to similarly send a notification to software application 225. For example, if the average processor availability percentage exceeds (e.g., is greater than) an upper limit for the average processor availability percentage, such exceeding the upper limit may indicate to software application 225 that one or more processors 212 are available to perform one or more tasks. Thus, in response to receiving a notification that the average processor availability percentage has exceeded the upper limit for the average processor availability percentage, software application 225 may cause one or more processors 212 to perform one or more tasks, for example, by scheduling the processing of the one or more tasks by one or more processors 212.

[0062] Computing device 202B shown in the example of FIG. 2B is an embodiment of computing device 102 shown in FIG. 1. Computing device 202B may include one or more processors 212, memory 216, display 220, and UI 222. One or more processors 212 are an embodiment of one or more processors 112 shown in FIG. 1 and include processor cores 218A-218M (processor cores 218), which are an embodiment of processor core 118 shown in FIG. 1. Memory 216 is an embodiment of memory 116 of FIG. 1. Display 220 is an embodiment of display 120 of FIG. 1. UI 222 is an embodiment of UI 122 of FIG. 1. Memory 216 may include application 225, which is an embodiment of one of applications 125 shown in FIG. 1, operating system 230, which is an embodiment of operating system 130 of FIG. 1, and system files 236.

[0063] 2B , operating system 230 includes system server 250, which includes job scheduler service 252 and processor monitor 254. Operating system 230 also includes processor information reader 238. One or more processors 212 may execute operating system 230 to periodically determine an average processor availability percentage of one or more processors 212, for example, every N seconds (e.g., every 15 seconds, every 30 seconds, every 60 seconds, etc.), using, for example, equations (1) and (2). To determine the average processor availability percentage of one or more processors 212, operating system 230 may read information from system files 236, which may include files in the / proc and / sys directories, such as files in the / sys / devices / system / cpu / cpufreq / policy{M} directory (where M is a policy ID, as described throughout this disclosure). One or more processors 212 may execute operating system 230 to read information from system file 236 once every N seconds (e.g., every 15 seconds, every 30 seconds, every 60 seconds, etc.) to periodically determine the average processor availability percentage of one or more processors 212.

[0064] In some embodiments, the frequency at which operating system 230 determines the average processor availability percentage for one or more processors 212 is set as a read-only system property of computing device 202B, which may be adjustable based on the performance overhead at which operating system 230 calculates the average processor availability percentage for one or more processors 212. In some embodiments, the frequency at which operating system 230 determines the average processor availability percentage for one or more processors 212 varies based on the system state of computing device 202B. For example, the frequency may depend on whether computing device 202B is in a system awake state, a user switched state, or another state.

[0065] In some embodiments, operating system 230 may collect a Perfetto trace while operating system 230 determines the average processor availability percentage of one or more processors 212 to provide insight into the processor overhead for performing these calculations. The processor overhead may be scaled to determine maximum and minimum processor overhead depending on the device specifications of computing device 202B, available power saving modes of computing device 202B (e.g., when computing device 202B uses battery power), etc.

[0066] One or more processors 212 may execute software application 225 to perform one or more tasks. In some embodiments, software application 225 may communicate with job scheduler service 252 to schedule one or more tasks to be executed by one or more processors 212. Job scheduler service 252 may execute to schedule one or more tasks of software application 225. To schedule one or more tasks, job scheduler service 252 may determine an average processor availability percentage of one or more processors 212 that may be required to make one or more processors 212 available to perform one or more tasks.

[0067] Thus, the job scheduler service 252 may register an associated listener with the processor monitor 254 to listen for the average processor availability percentage of one or more processors 212 determined by the processor monitor 254 in response to the software application 225 scheduling one or more tasks. In some embodiments, the job scheduler service 252 may register a processor availability change listener and / or a processor utilization listener. The processor availability change listener may listen for processor availability change notifications. The processor monitor 254 may send a processor availability change notification to the job scheduler service 252 when the processor availability of one or more processors 212 rises above / falls below a threshold, which may be specified in a CpuAvailabilityMonitoringConfig configuration file or another configuration specified by the processor monitor 254. For example, the processor monitor 254 may determine a value of a processor availability percentage of one or more processors 212 that may indicate that one or more processors 212 are available to perform one or more tasks, and may set that value of the processor availability percentage of one or more processors 212 to a threshold value.

[0068] In some embodiments, a processor utilization listener may listen for processor utilization statistics of one or more processors 212. The processor monitor 254 may send the utilization statistics to the job scheduler service 252 every N seconds, e.g., every 15 seconds, every 30 seconds, every 60 seconds, etc.

[0069] One or more processors 212 may execute processor monitor 254 to periodically, for example, every N seconds, determine an average processor availability percentage of one or more processors 212 according to equations (1) and (2). In some embodiments, in response to job scheduler service 252 registering a processor availability change listener, processor monitor 254 may begin periodically determining an average processor availability percentage of one or more processors 212 every N seconds (e.g., every 15 seconds, every 30 seconds, every 60 seconds, etc.).

[0070] Each time processor monitor 254 calculates the average processor availability percentage for one or more processors 212, processor monitor 254 may use processor information reader 238 to read the latest processor statistics from system file 236. Processor information reader 238 may include an information reader interface and an information reader daemon. Each time processor monitor 254 calculates the average processor availability percentage for one or more processors 212, the processor monitor may communicate with the information reader interface of processor information reader 238, the information reader daemon of processor information reader 238 may read the information from system file 236, and the information reader interface of processor information reader 238 may make the information obtained by the information reader daemon readable by processor monitor 254.

[0071] Each time processor monitor 254 determines the average processor availability percentage of one or more processors 212, processor monitor 254 may compare the currently determined average processor availability percentage with the average processor availability percentage determined over a previous period, such as the last 30 seconds, against an average processor availability percentage threshold specified by job scheduler service 252. If the currently determined average processor availability percentage and the average processor availability percentage determined over a previous period exceed the average processor availability percentage threshold, processor monitor 254 may notify job scheduler service 252, such as by sending a notification, that one or more processors 212 are available to execute one or more tasks.

[0072] In response to receiving notification that one or more processors 212 are available to execute one or more tasks, one or more processors 212 may execute job scheduler service 252 to remove listeners and cause one or more processors 212 to execute the one or more tasks, such as by scheduling execution of the one or more tasks by one or more processors 212. In some embodiments, processor monitor 254 may continue to periodically determine the average processor availability percentage of one or more processors 212 as long as at least one listener is registered with processor monitor 254. If no listeners are registered with processor monitor 254, processor monitor 254 may cease determining the average processor availability percentage of one or more processors 212 until a listener is registered with processor monitor 254.

[0073] Below is exemplary pseudocode for the various components of operating system 230 shown in Figures 2A and 2B.

[0074] CPU Monitor: package com.android.server.job.cpu; public final class CpuMonitor { / ** A listener that gets CPU availability change notifications. * / public interface CpuAvailabilityChangeListener { / ** *Since the last notice, *The most recent or last 30 seconds' average CPU availability percentage *{@link CpuAvailabilityMonitoringConfig# mThresholds} * Called when the value exceeds / falls below the limit. * * The listener will be invoked on the executor specified below. *{@link CarPerformanceManager#addCpuAvailabilityChangeListener} * *@param info CPU availability information. * / void onChanged(@NonNull CpuAvailabilityInfo info); } / ** * Add a {@link CpuAvailabilityChangeListener} to the caller. * *A listener is added to notify the current CPU availability percentage. * The listener is called. * *@param config CPU availability monitoring configuration. *@param listener A {@link CpuAvailabilityChangeListener} interface. * Listener to implement. * * @throws IllegalStateException, if the {@code listener} has already been added. * / public void addCpuAvailabilityChangeListener( @CallbackExecutor Executor, CpuAvailabilityMonitoringConfig config, CpuAvailabilityChangeListener listener); / ** * Removes the calling {@link CpuAvailabilityChangeListener}. * *@param listener A {@link CpuAvailabilityChangeListener} interface. * Listener to implement. * / public void removeCpuAvailabilityChangeListener( CpuAvailabilityChangeListener listener); / ** * Returns the current CPU monitoring interval in seconds. * / public int getCpuMonitoringIntervalSeconds(); / ** A listener that retrieves the latest CPU usage statistics. * / public interface CpuUsageListener { / ** *Called when the latest CPU usage statistics are available. * *CPU usage statistics are * Available every {@link getCpuMonitoringIntervalSeconds} seconds. * / void onLatestCpuUsageStats(@NonNull CpuUsageStats stats); } / ** * Add a {@link CpuUsageListener} to the caller. * *@param listener A {@link CpuAvailabilityChangeListener} interface. * Listener to implement. * * @throws IllegalStateException, if the {@code listener} has already been added. * / public void setCpuUsageListener( @CallbackExecutor Executor, CpuAvailabilityMonitoringConfig config, CpuAvailabilityChangeListener listener); / ** * Removes the calling {@link CpuAvailabilityChangeListener}. * *@param listener A {@link CpuAvailabilityChangeListener} interface. * Listener to implement. * / public void removeCpuUsageListener(CpuAvailabilityChangeListener listener); }

[0075] CPU availability monitoring configuration package com.android.server.job.cpu; / **CPU availability monitoring configuration. * / @DataClass(genToString = true, genBuilder = true, genHiddenConstDefs = true) public final class CpuAvailabilityMonitoringConfig { / **Constants for monitoring all cpusets. * / public static final int CPUSET_ALL = 1; / **Constants for monitoring background cpusets. * / public static final int CPUSET_BACKGROUND = 2; / ** *The set of CPUs to be monitored. * / private int mCpuset = CPUSET_ALL; / ** *CPU availability percentage threshold. * * CPU availability change notifications have been sent since the last notification. *The average CPU availability percentage for the most recent or last 30 seconds *Sent when any of these thresholds are exceeded / undertaken. * / Private List <int>mThresholds; }

[0076] CPU availability information package com.android.server.job.cpu; / **CPU availability information. * / @DataClass(genToString = true, genBuilder = true, genHiddenConstDefs = true) public final class CpuAvailabilityInfo implements Parcelable { / ** A constant indicating the percentage of CPU availability that is lacking. * / public static final int MISSING_CPU_AVAILABILITY_PERCENT = -1; / ** * Returns the CPUSETs whose availability information is recorded in this object. * *< / int> The returned CPUSET value is *One of the CPUSET_* constants from {@link CpuAvailabilityMonitoringConfig}. * / private int mCpuset; / ** Returns the most recent average CPU availability percentage. * / private int mLatestAvgAvailabilityPercent; / ** Returns the average CPU availability percentage over the last 30 seconds. * / private

[0077] CPU usage statistics package com.android.server.job.cpu; / **CPU usage statistics. * / @DataClass(genToString = true, genBuilder = true, genHiddenConstDefs = true) public final class CpuUsageStats{ / ** * A list of UID CPU usage statistics for all UIDs running on the system since the last update. *CPU usage statistics are reported only for UIDs with a CPU load of 1% or more. * / private SparseArray <uidcpustats>mCpuStatsByUid; / ** * CPU load used system-wide since the last update. * / private int mTotalCpuLoadPercent; / ** *CPU usage statistics for UID. * / public final class UidCpuStats { / ** *The UID for which this object reports CPU statistics. * / private int mUid; / ** *CPU load percentage used by UID. * / private int mCpuLoadPercent; } }

[0078] Vehicle Performance Manager package android.car.performance; / **@hide* / @SystemApi public final class CarPerformanceManager extends CarManagerBase { / ** *A listener that gets notifications of changes in CPU availability. ** < / uidcpustats> The application implements the listener method, *Perform one of the following actions: *1. When CPU availability percentage exceeds the specified upper limit percentage, *Performing CPU-intensive tasks. *2. When the CPU availability percentage falls below the specified lower limit percentage, *Stop CPU-intensive tasks from running. 3. Handle CPU availability timeouts. * / public interface CpuAvailabilityChangeListener { / ** *Called on one of the following events: *1. CPU availability percentage is *{@link CpuAvailabilityMonitoringConfig#getLowerBoundPercent} *When a specified minimum percentage is reached or falls below. *2. CPU availability percentage is *{@link CpuAvailabilityMonitoringConfig#getUpperBoundPercent} *When the specified limit percentage is met or exceeded. *3. When CPU availability monitoring reaches the timeout specified below. *{@link CpuAvailabilityMonitoringConfig#getTimeoutInSeconds} ** The listener will be invoked on the executor specified below. *{@link CarPerformanceManager#addCpuAvailabilityChangeListener} ** @param info CPU availability information. * / void onCpuAvailabilityChange(@NonNull CpuAvailabilityInfo info); } / ** * Add a {@link CpuAvailabilityChangeListener} to the calling package. ** @param config CPU availability monitoring configuration. *@param listener A {@link CpuAvailabilityChangeListener} interface. * Listener to implement. ** @throws IllegalStateException, if the {@code listener} has already been added. * / @RequiresPermission(Car.PERMISSION_COLLECT_CAR_PERFORMANCE_CPU_INFO) public void addCpuAvailabilityChangeListener( @NonNull @CallbackExecutor Executor, @NonNull CpuAvailabilityMonitoringConfig config, @NonNull CpuAvailabilityChangeListener listener); / ** * Remove the {@link CpuAvailabilityChangeListener} in the calling package. ** @param listener A {@link CpuAvailabilityChangeListener} interface * Listener to implement. * / @RequiresPermission(Car.PERMISSION_COLLECT_CAR_PERFORMANCE_CPU_INFO) public void removeCpuAvailabilityChangeListener( @NonNull CpuAvailabilityChangeListener listener); }

[0079] 3 is a flowchart illustrating an example operation of the example computing device 102 of FIG. 1 for managing disk access usage of applications. FIG. 3 is described with respect to FIG.

[0080] 3, one or more processors 112 of computing device 102 may determine processor availability for one or more processors 112 based at least in part on one or more processor statistics and one or more processor mode statistics (302). One or more processors 112 may determine whether one or more processors 112 are available to perform one or more tasks based at least in part on the processor availability for one or more processors 112 (304). One or more processors 112 may perform one or more tasks in response to determining that one or more processors 112 are available to perform one or more tasks (306).

[0081] In some embodiments, the one or more processors 112 include multiple processor cores 118, and to determine processor availability, the one or more processors 112 may determine a respective processor availability for each of the multiple processor cores, determine an average processor availability of the one or more processors 112 based at least in part on the respective processor availability for each of the multiple processor cores, and determine whether the one or more processors 112 are available to perform one or more tasks based at least in part on the average processor availability of the one or more processors 112.

[0082] In some embodiments, to determine each processor availability for each of the plurality of processor cores, the one or more processors 112 may determine each processor availability for a processor core among the plurality of processor cores as a function of the processor core's current processor frequency, a maximum processor frequency, and an amount of idle time for the processor core. In some embodiments, to determine each processor availability for a processor core among the plurality of processor cores, the one or more processors 112 may determine an amount of time spent by the processor core at each of the plurality of processor frequencies based at least in part on one or more processor statistics, and determine a current processor frequency for the processor core based at least in part on the amount of time spent by the processor core at each of the plurality of processor frequencies.

[0083] In some embodiments, to determine each processor availability for a processor core among the plurality of processor cores, one or more processors 112 may determine the amount of idle time of the processor core based at least in part on one or more processor mode statistics.

[0084] In some embodiments, to determine the average processor availability, the one or more processors 112 may determine the average processor availability of the one or more processors 112 as a function of the respective processor availability for each of the plurality of processor cores and the respective maximum processor frequency for each of the plurality of processor cores. In some embodiments, to determine each processor availability for a processor core of the plurality of processor cores, the one or more processors 112 may calculate the processor availability percentage of the processor core as follows:

number

number

[0085] In some examples, in response to determining that one or more processors 112 are available to perform the one or more tasks, the one or more processors 112 may listen, by a software application executing on the one or more processors 112, for notifications of processor availability of the one or more processors 112; determine, by the software application executing on the one or more processors 112, whether the one or more processors 112 are available to perform the one or more tasks based at least in part on the notifications of processor availability of the one or more processors 112; and, in response to determining that one or more processors 112 are available to perform the one or more tasks, perform the one or more tasks.

[0086] Aspects of the present disclosure include the following examples.

[0087] Example 1. A method comprising: determining, by one or more processors, processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determining, by the one or more processors, whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability for the one or more processors; and executing, by the one or more processors, the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0088] Example 2. The method of example 1, wherein the one or more processors include a plurality of processor cores, and wherein determining the processor availability includes: determining, by the one or more processors, a respective processor availability for each of the plurality of processor cores; determining, by the one or more processors, an average processor availability of the one or more processors based at least in part on the respective processor availability for each of the plurality of processor cores; and determining, by the one or more processors, whether the one or more processors are available to execute the one or more tasks based at least in part on the average processor availability of the one or more processors.

[0089] Example 3. The method of Example 2, wherein determining the respective processor availability for each of the plurality of processor cores further includes determining, by the one or more processors, the respective processor availability for a processor core among the plurality of processor cores according to the current processor frequency of the processor core, a maximum processor frequency, and an amount of idle time of the processor core.

[0090] Example 4. The method of Example 3, wherein for a processor core of the plurality of processor cores, determining the respective processor availability further includes: determining, by the one or more processors, an amount of time spent by the processor core at each of a plurality of processor frequencies based at least in part on the one or more processor statistics; and determining, by the one or more processors, the current processor frequency of the processor core based at least in part on the amount of time spent by the processor core at each of the plurality of processor frequencies.

[0091] Example 5. The method of any of Examples 3 and 4, wherein determining each processor availability for the processor cores of the plurality of processor cores further includes determining, by the one or more processors, the amount of idle time for the processor core based at least in part on the one or more processor mode statistics.

[0092] Example 6. A method according to any of Examples 3 to 5, wherein determining the average processor availability further includes determining, by the one or more processors, the average processor availability of the one or more processors in response to the respective processor availability for each of the plurality of processor cores and the respective maximum processor frequency for each of the plurality of processor cores.

[0093] Example 7. The method of Example 6, wherein determining each processor availability for a processor core among the plurality of processor cores further includes determining, by the one or more processors, a processor availability percentage for the processor core, where N is the number of seconds that have elapsed since the one or more processors last determined the processor availability percentage.

[0094] Example 8. Determining the average processor availability of the one or more processors further comprises: determining, by the one or more processors, an average processor availability percentage of the one or more processors, wherein the range of processor cores is processor core a through processor core z, and i is the average processor percentage of processor core i, and F i 8. The method of example 7, comprising determining, where i is the maximum processor frequency of the processor core i.

[0095] Example 9. The method of any of Examples 1-8, wherein executing the one or more tasks in response to determining that the one or more processors are available to execute the one or more tasks further includes: listening, by a software application executing on the one or more processors, for notifications of processor availability of the one or more processors; determining, by the software application executing on the one or more processors, whether the one or more processors are available to execute the one or more tasks based at least in part on the notifications of processor availability of the one or more processors; and executing the one or more tasks by the one or more processors in response to determining that the one or more processors are available to execute the one or more tasks.

[0096] Example 10. A computing device comprising a memory and one or more processors communicatively connected to the memory, wherein the one or more processors are configured to: determine processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determine whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability for the one or more processors; and perform the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0097] Example 11. The computing device of Example 10, wherein the one or more processors include a plurality of processor cores, and wherein, to determine the processor availability, the one or more processors are further configured to: determine, for each of the plurality of processor cores, a respective processor availability; determine, based at least in part on the respective processor availability for each of the plurality of processor cores, an average processor availability of the one or more processors; and determine, based at least in part on the average processor availability of the one or more processors, whether the one or more processors are available to perform the one or more tasks.

[0098] Example 12. The computing device of Example 11, wherein, to determine the respective processor availability for each of the plurality of processor cores, the one or more processors are further configured to perform the following: determining the respective processor availability for a processor core among the plurality of processor cores according to the current processor frequency of the processor core, a maximum processor frequency, and an amount of idle time of the processor core.

[0099] Example 13. The computing device of Example 12, wherein, to determine the respective processor availability for a processor core of the plurality of processor cores, the one or more processors are further configured to: determine an amount of time spent by the processor core at each of a plurality of processor frequencies based at least in part on the one or more processor statistics; and determine the current processor frequency of the processor core based at least in part on the amount of time spent by the processor core at each of the plurality of processor frequencies.

[0100] Example 14. A computing device as described in any of Examples 12 and 13, wherein, to determine the respective processor availability for the processor cores among the plurality of processor cores, the one or more processors are further configured to determine the amount of idle time of the processor cores based at least in part on the one or more processor mode statistics.

[0101] Example 15. A computing device described in any of Examples 12 to 14, wherein, to determine the average processor availability, the one or more processors are further configured to: determine the average processor availability of the one or more processors according to the respective processor availability for each of the plurality of processor cores and the respective maximum processor frequency for each of the plurality of processor cores.

[0102] Example 16. The computing device of Example 15, wherein, to determine the processor availability for each processor core among the plurality of processor cores, the one or more processors are further configured to determine a processor availability percentage for the processor core, where N is the number of seconds that have elapsed since the one or more processors last determined the processor availability percentage.

[0103] Example 17. To determine the average processor availability of the one or more processors, the one or more processors further: determining an average processor availability percentage of the one or more processors, wherein the range of processor cores is processor core a through processor core z, and i is the average processor percentage of processor core i, and F i 17. The computing device of example 16, configured to determine, wherein i is the maximum processor frequency of the processor core i.

[0104] Example 18. The computing device of any of Examples 10 to 17, wherein in response to determining that the one or more processors are available to perform the one or more tasks, the one or more processors are further configured to: listen, by a software application executing on the one or more processors, for notifications of processor availability of the one or more processors; determine, by the software application executing on the one or more processors, whether the one or more processors are available to perform the one or more tasks based at least in part on the notifications of processor availability of the one or more processors; and execute the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0105] Example 19. A non-transitory computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors of a computing device to: determine processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determine whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability for the one or more processors; and perform the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks.

[0106] Example 20. The non-transitory computer-readable storage medium of Example 19, wherein the one or more processors include a plurality of processor cores, and the instructions further cause the one or more processors to: determine, for each of the plurality of processor cores, a respective processor availability; determine, based at least in part on the respective processor availability for each of the plurality of processor cores, an average processor availability of the one or more processors; and determine, based at least in part on the average processor availability of the one or more processors, whether the one or more processors are available to perform the one or more tasks.

[0107] The techniques described in this disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented within one or more processors, including one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry, as well as any combination of such components. The term "processor" or "processing circuitry" may generally refer to any of the aforementioned logic circuits alone or in combination with other logic circuits, or any other equivalent circuitry. A control unit including hardware may also perform one or more of the techniques of this disclosure.

[0108] Such hardware, software, and firmware may be implemented within the same device or within separate devices to support the various operations and functions described in this disclosure. Furthermore, any of the described units, modules, or components may be implemented together or separately as distinct but interoperable logical devices. The depiction of various features as modules or units is intended to emphasize different functional aspects and does not imply that such modules or units must necessarily be realized by distinct hardware or software components. Rather, functionality associated with one or more modules or units may be performed by distinct hardware or software components or integrated within a common or distinct hardware or software component.

[0109] The techniques described in this disclosure may also be embodied in or encoded on a computer-readable medium, such as a computer-readable storage medium containing instructions. The instructions embodied in or encoded on the computer-readable medium, when executed, may cause a programmable processor or other processor to perform the method, for example. Computer-readable media may include non-transitory computer-readable storage media and transitory communication media. Tangible, non-transitory computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), flash memory, hard disks, CD-ROMs, floppy disks, cassettes, magnetic media, optical media, or other computer-readable storage media. It should be understood that the term "computer-readable storage medium" refers to a physical storage medium, and not to a signal, carrier wave, or other transitory medium.

[0110] Various embodiments have been described. These and other embodiments are within the scope of the following claims.

Claims

1. determining, by one or more processors, processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determining, by the one or more processors, whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability of the one or more processors; executing, by the one or more processors, the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks; and A method comprising:

2. The one or more processors include a plurality of processor cores, and determining processor availability comprises: determining, by the one or more processors, a respective processor availability for each of the plurality of processor cores; determining, by the one or more processors, an average processor availability of the one or more processors based at least in part on the respective processor availability for each of the plurality of processor cores; determining, by the one or more processors, whether the one or more processors are available to perform the one or more tasks based at least in part on the average processor availability of the one or more processors; The method of claim 1 , comprising:

3. Determining the respective processor availability for each of the plurality of processor cores further includes:

3. The method of claim 2, further comprising determining, by the one or more processors, for a processor core of the plurality of processor cores, the processor availability as a function of a current processor frequency of the processor core, a maximum processor frequency, and an amount of idle time of the processor core.

4. Determining each processor availability for the processor cores of the plurality of processor cores further includes: determining, by the one or more processors, an amount of time spent by the processor core at each of a plurality of processor frequencies based at least in part on the one or more processor statistics; determining, by the one or more processors, the current processor frequency of the processor core based at least in part on the amount of time spent by the processor core at each of the plurality of processor frequencies; The method of claim 3, comprising:

5. Determining each processor availability for the processor cores of the plurality of processor cores further includes:

5. The method of claim 3, further comprising determining, by the one or more processors, the amount of idle time of the processor cores based at least in part on the one or more processor mode statistics.

6. Determining the average processor availability further comprises:

6. The method of claim 3, further comprising determining, by the one or more processors, the average processor availability of the one or more processors as a function of the respective processor availability for each of the plurality of processor cores and the respective maximum processor frequency for each of the plurality of processor cores.

7. Determining each processor availability for the processor cores of the plurality of processor cores further includes: determining, by the one or more processors, a processor availability percentage of the processor core; [Equation 1] 7. The method of claim 6, comprising determining N=N, where N is the number of seconds that have elapsed since the one or more processors last determined the processor availability percentage.

8. Determining the average processor availability of the one or more processors further comprises: determining, by the one or more processors, an average processor availability percentage of the one or more processors; [Equation 2] the range of the plurality of processor cores is processor core a to processor core z, and ｉ is the average processor percentage of processor core i, and F ｉ The method of claim 7 , wherein: i is the maximum processor frequency of the processor core i.

9. In response to determining that the one or more processors are available to perform the one or more tasks, performing the one or more tasks further comprises: listening, by a software application executing on the one or more processors, for notifications of processor availability of the one or more processors; determining, by the software application executing on the one or more processors, whether the one or more processors are available to perform the one or more tasks based at least in part on the notification of processor availability of the one or more processors; executing, by the one or more processors, the one or more tasks in response to determining that the one or more processors are available to perform the one or more tasks; and The method according to any one of claims 1 to 8, comprising:

10. Memory and one or more processors communicatively connected to the memory; 1. A computing device comprising: determining processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determining whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability of the one or more processors; In response to determining that the one or more processors are available to perform the one or more tasks, performing the one or more tasks; and 1. A computing device configured to execute the

11. The one or more processors include a plurality of processor cores, and to determine the processor availability, the one or more processors further comprise: determining a respective processor availability for each of the plurality of processor cores; determining an average processor availability of the one or more processors based at least in part on the respective processor availability for each of the plurality of processor cores; determining whether the one or more processors are available to perform the one or more tasks based at least in part on the average processor availability of the one or more processors; The computing device of claim 10 configured to execute:

12. To determine the respective processor availability for each of the plurality of processor cores, the one or more processors further 12. The computing device of claim 11, configured to perform the determining of each processor availability for a processor core of the plurality of processor cores as a function of a current processor frequency of the processor core, a maximum processor frequency, and an amount of idle time of the processor core.

13. To determine the respective processor availability for the processor cores of the plurality of processor cores, the one or more processors further determining an amount of time spent by the processor core at each of a plurality of processor frequencies based at least in part on the one or more processor statistics; determining the current processor frequency of the processor core based at least in part on the amount of time spent by the processor core at each of the plurality of processor frequencies; The computing device of claim 12 configured to execute:

14. To determine the respective processor availability for the processor cores of the plurality of processor cores, the one or more processors further 14. The computing device of claim 12, configured to perform determining the amount of idle time of the processor core based at least in part on the one or more processor mode statistics.

15. To determine the average processor availability, the one or more processors further:

15. The computing device of claim 12, configured to perform determining the average processor availability of the one or more processors as a function of the respective processor availability for each of the plurality of processor cores and a respective maximum processor frequency for each of the plurality of processor cores.

16. To determine the respective processor availability for the processor cores of the plurality of processor cores, the one or more processors further a processor availability percentage of said processor core; [Equation 3] 16. The computing device of claim 15, configured to determine N = N = N, where N is the number of seconds that have elapsed since the one or more processors last determined the processor availability percentage.

17. To determine the average processor availability of the one or more processors, the one or more processors further an average processor availability percentage of said one or more processors; [Equation 4] the range of the plurality of processor cores is processor core a to processor core z, and ｉ is the average processor percentage of processor core i, and F ｉ 17. The computing device of claim 16, wherein: i is the maximum processor frequency of the processor core i.

18. In response to determining that the one or more processors are available to perform the one or more tasks, the one or more processors further listening, by a software application executing on the one or more processors, for notifications of processor availability of the one or more processors; determining, by the software application executing on the one or more processors, whether the one or more processors are available to perform the one or more tasks based at least in part on the notification of processor availability of the one or more processors; In response to determining that the one or more processors are available to perform the one or more tasks, performing the one or more tasks; and A computing device according to any one of claims 10 to 17, configured to execute:

19. A non-transitory computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors of a computing device to: determining processor availability for the one or more processors based at least in part on one or more processor statistics and one or more processor mode statistics; determining whether the one or more processors are available to perform one or more tasks based at least in part on the processor availability of the one or more processors; In response to determining that the one or more processors are available to perform the one or more tasks, performing the one or more tasks; and A non-transitory computer-readable storage medium for executing the method.

20. The one or more processors include a plurality of processor cores, and the instructions cause the one or more processors to further: determining a respective processor availability for each of the plurality of processor cores; determining an average processor availability of the one or more processors based at least in part on the respective processor availability for each of the plurality of processor cores; determining whether the one or more processors are available to perform the one or more tasks based at least in part on the average processor availability of the one or more processors; 20. The non-transitory computer-readable storage medium of claim 19, wherein the non-transitory computer-readable storage medium executes:

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