I2c Register Map with Virtual Extensions

Abstract

A system (110) is proposed that includes at least one inter-integrated circuit node (I2C node) (112), at least one master controller (114), and at least one inter-integrated circuit (I2C) (116). The I2C (116) is configured to transmit data between the I2C node (112) and the master controller (114). The I2C node (112) provides a register map (118). The master controller (114) is configured to read the register map (118) byte by byte. The I2C node (112) is configured to increment a register address for each byte. The register map (118) includes a physical register map (120). Data in the physical register map (120) has a physical address in the memory of the I2C node (122). The I2C node (112) is configured to generate data that is larger in size than the physical register map (120). The register map (118) includes a virtual section, and data in the virtual section has addresses in further memory locations (124). The master controller (114) is configured to read the virtual section by performing transactions that start in the physical register map (118) and increment register addresses beyond the physical register map size.

Description

[Technical Field]

[0001] The present invention relates to a system including at least one Inter-Integrated Circuit (I2C) node, a mobile device, a method for data transmission between at least one I2C node and at least one master controller, and several applications. Such methods and devices can be used generally for surveillance or monitoring purposes, particularly in the infrared (IR) spectral region, and in particular in the near-infrared (NIR) spectral region, as well as for heat, flame, fire, or smoke detection. However, further applications are possible. [Background technology]

[0002] Infrared spectrometers can be integrated into mobile devices, such as smartphones. Such spectrometers typically consist of a number of infrared sensors (also called pixels), each equipped with a different wavelength filter, capable of measuring the light intensity at a specific wavelength. The acquired data may then be transferred to the mobile device, where it can be further processed by its processor, in particular its central processing unit (CPU). Data transfer in mobile devices often uses the so-called I2C (Inter-Integrated Circuit) protocol, which is designed for relatively simple components that transfer small amounts of data.

[0003] Non-Patent Document 1 (Semiconductor Corporation Cypress: "Master Slave 1.20", PSoC Creator Component Data Sheet, 2015-12-20, pages 1-36, XP093019583) provides a general description of I2C slave and master configuration.

[0004] Typically, I2C nodes, such as sensor modules, provide a standard 8-bit register map. For example, an I2C node may generate data larger than the register map. The master can read and write to the register map byte by byte, and the node automatically increments the address after each byte, allowing multiple bytes to be included in a single transaction.

[0005] However, in the case of spectrometers, the data can quickly become very large. This is because there are different sensors (pixels) that each provide a value. Furthermore, multiple measurements may be taken to improve the signal. Therefore, fast readout of the generated data is problematic and can be performed using complex techniques. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Non-patent document 1: Semiconductor Corporation Cypress: "Master Slave 1.20", PSoC Creator Component Data Sheet, 2015-12-20, pages 1-36, XP093019583 Summary of the Invention [Problem to be solved by the invention]

[0007] The problem addressed by the present invention is therefore to provide a system, a mobile device and a data transmission method which at least substantially avoid the drawbacks of known methods and devices of this type. In particular, it is desirable to provide a method and a device which ensures high speed data readout in a simple manner.

[0008] This problem is solved by a system, a mobile device and a data transmission method with the features of the independent claims. Advantageous embodiments, which can be realized independently or in any combination, are set out in the dependent claims and in the entire specification. [Means for solving the problem]

[0009] In a first aspect of the present invention, a system is disclosed that includes at least one inter-integrated circuit (I2C) node, at least one master controller, and at least one inter-integrated circuit (I2C). The I2C is configured to transmit data between the I2C node and the master controller. The I2C node provides a register map. The master controller is configured to read the register map byte by byte. The I2C node is configured to increment a register address for each byte. The register map includes a physical register map. Data in the physical register map has a physical address in a memory of the I2C node. The I2C node is configured to generate data of a size larger than the physical register map. The register map includes a virtual section. Data in the virtual section has an address in a further memory location. The master controller is configured to read the virtual section by executing a transaction that starts in the physical register map. The transaction length of the transaction exceeds the size of the physical register map. In particular, the transaction starts at a start address, and the transaction length is greater than the size of the physical register map.

[0010] The term "system" as used herein is a broad term and is given its ordinary and customary meaning to those skilled in the art, without being limited to any special or customized meaning. The term may refer to, but is not limited to, any collection of interacting or interdependent components forming a whole. In particular, the components may interact to perform at least one common function. At least two components may be treated independently or may be coupled or connectable. A system includes at least one inter-integrated circuit node (I2C node), at least one master controller, and at least one inter-integrated circuit (I2C).

[0011] As used herein, the term "inter-integrated circuit" is a broad term and is given its ordinary and customary meaning to those skilled in the art, without being limited to any special or customized meaning. This term may refer to, but is not limited to, a data bus configured to connect integrated circuits. For example, I2C may be designed as described in https: / / www.nxp.com / docs / en / user-guide / UM10204.pdf, www.ipd.kit.edu / ~buchmann / microcontroller / i2c.htm, or www.ti.com / lit / an / slva704 / slva704.pdf. I2C may be a synchronous, packet-switched, single-ended, serial communications bus. Specifically, I2C is a hierarchical bus system with a so-called master-slave architecture, including at least one master controller and at least one I2C node.

[0012] A system may include one or more I2C nodes. As used herein, the term "I2C node" (also referred to as "slave") is a broad term and is given its ordinary and customary meaning to those skilled in the art, without being limited to any special or customized meaning. This term may refer to, but is not limited to, any I2C device connected to an I2C bus. For example, an I2C node may include at least one sensor. The sensor may include at least one element selected from the group consisting of at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel photosensor, and any sensor with a data buffer and automatic data storage (smart sensor). For example, an I2C node may be a spectrometer. The spectrometer includes multiple pixels, each with a different wavelength filter, and each pixel can measure light intensity at a specific wavelength. An I2C node may further include at least one processor, such as at least one microprocessor, at least one microcontroller, and / or at least one computer.

[0013] The term "processor," as used herein, is a broad term and should be given its ordinary and accustomed meaning to those skilled in the art, without being limited to any special or customized meaning. The term may specifically, but not exclusively, refer to any logic circuitry configured to perform the basic operations of a computer or system, and / or, generally, to a device configured to perform calculations or logical operations. In particular, a processor may be configured to process the basic instructions that run a computer or system. By way of example, a processor may include at least one arithmetic logic unit (ALU), at least one floating-point unit (FPU), such as a math coprocessor or numeric coprocessor, multiple registers, particularly registers configured to provide operands to the ALU and store operation results, and memory, such as an L1 cache memory and an L2 cache memory. In particular, a processor may be a multi-core processor. In particular, a processor may be or include a central processing unit (CPU). The processor may be or include a microprocessor, and thus, in particular, the elements of the processor may be included in one single integrated circuit (IC) chip. The processor may further include one or more chips, such as one or more application specific integrated circuits (ASICs) and / or one or more field programmable gate arrays (FPGAs) and / or one or more tensor processing units (TPUs) and / or dedicated machine learning optimization chips. The processor may be, in particular, configured, such as by software programming, to perform one or more evaluation operations.

[0014] A system may include one or more master controllers. As used herein, the term "master controller," also referred to as master, is a broad term and should be given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. This term may refer to at least one processor, such as, but not limited to, at least one microprocessor, at least one microcontroller, and / or at least one computer, assigned as the master of the system. A master controller may be configured to address one or more I2C nodes, but not vice versa.

[0015] I2C is configured to transmit data between an I2C node and a master controller. The transmission may include a data exchange. The data may be transferred in a sequence of 8 bits. During each clock cycle, one data bit may be transferred.

[0016] The I2C bus may be based on two lines, where one line is used to transmit a clock signal (serial clock line, SCL) and the other line is used to transmit data bits (serial data line, SDA). The clock signal may be generated by a master controller. The master controller may be configured to initiate data transmission by sending a query to the I2C nodes. To initiate data transmission, the master controller may be configured to specify the addresses of the I2C nodes with which to exchange data. Each I2C node may include a 4-bit address hardwired into the I2C node's chip. Furthermore, each I2C node's chip may include multiple address pins, which can be assigned arbitrary addresses. Multiple bits (e.g., 7 bits) may be used to address and transfer each I2C node. At least one additional bit may be used to specify whether the master controller is sending data to (i.e., writing) or receiving data from (i.e., reading) the I2C node. As described in www.ti.com / lit / an / slva704 / slva704.pdf, the steps for the master controller to read data from an I2C node are as follows: - The master controller sends a START condition to address the I2C node. A START condition is defined as a high-to-low transition of the SDA line while SCL is high; - The master controller sends the requested register to the I2C node; - The master controller receives data from the I2C node; - The master controller defines a STOP condition to terminate a transfer when the SDA line transitions from low to high while SCL is high.

[0017] An I2C node may include one or more registers. As used herein, the term "register" is a broad term and is given its ordinary and customary meaning to those skilled in the art, without being limited to any special or customized meaning. The term may refer to, but is not limited to, a location in the memory of an I2C node configured to store information. The information may be configuration information and / or data acquired by at least one sensor of the I2C node. The information stored in a register may be one or more of the following values, particularly a measurement value, a measurement uncertainty, a calibration value, a (system) setting value, or a measurement parameter. Each register may have a unique address. Each register may contain 8 bits. The master controller is configured to read and, optionally, write the register map byte by byte. The master controller can read and write the register map byte by byte. The I2C node is configured to increment the register address for each byte.

[0018] Typically, reading from a register may be performed as described, for example, in www.ti.com / lit / an / slva704 / slva704.pdf. The master controller may be configured to instruct the I2C node which register map to read from. The master controller may be configured to initiate transmission by sending an address with a write bit, followed by the register address it wishes to read. After the I2C node acknowledges this register address, the master controller may again send a START condition, followed by the I2C node address with a read bit. The I2C node may acknowledge the read request. The master controller may continue to send clock pulses, but release the SDA line so the I2C node can send data. After each byte of data is completed, the master controller may send an ACK (Acknowledge) to the I2C node, informing the I2C node that more data is ready. Once the master controller has received the expected number of bytes, it sends a NACK (Not Acknowledge), informing the I2C node to stop communication and re-lease the bus. The master controller may follow this with a STOP condition. The master controller can read and write the register map on a byte-by-byte basis. I2C nodes may be configured to auto-increment the address after each byte, allowing one transaction to contain multiple bytes.

[0019] An I2C node provides a register map. As used herein, the term "register map" is a broad term and is given its ordinary and customary meaning to those skilled in the art, without being limited to any special or customized meaning. The term may refer to, but is not limited to, an ordered list of registers. An I2C node may include one or more registers. Each register may have a unique address. The register map may include a register map layout. The register map may include multiple columns and rows. The register map may include an index N for each register. For example, the register map may include two columns, the first column containing the index and the second column containing the register name. The register map may include a size. The size of the index N may be equal to the size of the register map.

[0020] The register map includes a physical register map. Data in the physical register map has physical addresses in the memory of the I2C node. The I2C node is configured to generate data of a size larger than the physical register map. As used herein, the term "physical register map" is a broad term and is given its ordinary and customary meaning to those skilled in the art, without limitation to any special or customized meaning. The term may refer to, but is not limited to, a portion of the register map that includes registers with physical addresses in the memory of the I2C node. As used herein, the term "memory" is a broad term and is given its ordinary and customary meaning to those skilled in the art, without limitation to any special or customized meaning. The term may refer to, but is not limited to, a device or system configured to store data. The memory of the I2C node may include semiconductor memory. The memory of the I2C node may include volatile memory and / or nonvolatile memory. For example, the memory of the I2C node may include one or more RAMs, such as dynamic random access memory (DRAM) or static random access memory (SRAM). For example, the memory of the I2C node may include one or more of flash memory, ROM, PROM, EPROM, EEPROM memory, and ferroelectric random access memory (FRAM). The physical register map may include a physical register map size. The I2C node is configured to provide the physical register map as a standard 8-bit register map. The physical register map size is N≦256. The I2C node may be configured to generate data of size N greater than 256 bytes.

[0021] Typically, the size of the physical register map is 256 bytes, and index N may range from 0 to 255. However, an I2C node may generate data larger than the size of the physical register map (e.g., greater than 256 bytes). In this case, for example, the register map size may be increased. However, this may not be possible in some circumstances, such as when the I2C node does not have enough RAM or when the register address size is fixed at 8 bits for software compatibility reasons. Additionally or alternatively, the register map may be divided into smaller pieces and data transfers may be performed using multiple transactions. For example, data may be divided into smaller pieces that fit into the register map, such as the size of a 128-byte value. The register map may also contain a special control register called a "partition index" that controls which partition is accessed by the master controller. To read all data, the master controller may first perform a write transaction to the partition index, followed by a read transaction that can transfer up to 254 bytes. This pair of transactions must be performed multiple times until all data is transferred. Therefore, if the data is partitioned and a partition index is used, multiple transactions must be executed. However, with partitioning, gaps in the transfer between transactions occur. These gaps occur between all transactions due to one or more of the following reasons: a) the bus may be in use by another sensor; b) natural processing delays, i.e., starting a new transaction takes several CPU cycles; or c) the process requesting the next transfer sleeps and waits to be scheduled again (in systems with an operating system). The contributions of a) and b) depend mainly on the system load and processor performance. Depending on the number of bytes and the operating system, these gaps can be large (e.g., in non-real-time operating systems like Linux or Android).

[0022] Specifically, to enable high-speed reads even when an I2C node generates data larger than the physical register map, the present invention proposes a register map that includes a virtual section. The register map may be virtually expanded. Data in the virtual section has addresses in additional memory locations. As used herein, the term "virtual section" is a broad term, given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. This term may refer to, but is not limited to, an additional portion of the register map, i.e., registers that include registers with addresses in additional memory locations in addition to the physical register map. As used herein, the term "additional memory locations" is a broad term, given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. This term may refer to, but is not limited to, any memory location other than the memory that constitutes the data associated with the physical register map. The additional memory locations may be physical storage locations in the I2C node that are different from the memory, and / or the additional memory locations may be memory locations external to the I2C node. The additional memory locations may be memory locations where all data is available in contiguous format. Because of the serial format, an I2C node can read all the data in one transaction.

[0023] A virtual section cannot be directly addressed. The master controller is configured to read a virtual section by executing a transaction that starts in the physical register map. The transaction length of the transaction exceeds the physical register map size. In particular, a transaction begins at a starting address and is greater than the size of the physical register map. To read all data generated by an I2C node, the master controller may start reading the first value (e.g., register address 0) and continue reading, even after reading value 255, until all data in the virtual section's registers (e.g., values ​​256 to N, where N > 256) has been transferred. In this approach, all data is transferred in a single read transaction. Virtually extending the register map may provide the fastest possible solution for transferring all data.

[0024] As mentioned above, the I2C node may be configured to automatically increment the address after each byte. When the address reaches the end of the physical register map, it is no longer possible to fetch data from the next consecutive physical address. The I2C node may be configured to provide the next data from the first register in the virtual section. The I2C node may be configured to provide the next data when the register address reaches the end of the physical register map by translating between the address of a further memory location and a physical address in memory.

[0025] For example, an I2C node may be configured to fill a physical register map with values ​​from a virtual section and reset the physical address to zero when the register address reaches the end of the physical register map. This process may be transparent to the master controller. The master controller may be configured to read as many values ​​and / or bytes from the virtual section as necessary and / or a predefined number, such as through a driver. This process may occur whenever the address of an additional memory location reaches a multiple of the size of the physical register map. The I2C node may be configured to update and / or refill the physical register map with the original values ​​from page 0 after the transfer is complete.

[0026] An I2C node may be configured to operate with at least one special purpose register. An I2C node may be configured to operate with multiple special purpose registers. A virtual extension of the physical register map may be available only if a read is initiated from a special purpose register (or one of multiple special purpose registers). As used herein, the term "special purpose register" is a broad term and is given its ordinary and accustomed meaning to those skilled in the art and is not limited to any special or customized meaning. The term may refer to, but is not limited to, a register in the physical register map that has a predefined and / or preassigned function. A special purpose register may be any register or multiple registers in the physical register map. For example, a special purpose register may be register 0 or the last register in the physical register map. For example, a special purpose register may be located after all register values ​​(if any) in the physical register map. An I2C node may be configured to provide data stored in an additional memory location when a master controller initiates a read of the special purpose register. This may be transparent to the master controller. For example, when the master controller initiates a read of a special register, the I2C node may send data internally that is stored in another memory location. If the read is initiated from a special register, the I2C node may fetch the data not from the physical register map, but from a special memory location where all data is available contiguously. The address of this special memory location may be defined by another register (e.g., an offset from the location of the special register).

[0027] In a further aspect, a mobile device is disclosed that includes at least one system according to the present invention, for example according to any one of the system embodiments as described above or in more detail below. For further details regarding the mobile device, reference may be made to the system description above and the more detailed description below. The mobile device is at least one element selected from the group consisting of a notebook computer, a tablet, a mobile phone, a smartphone, a smartwatch, and a wearable computer. The mobile device is configured to use at least one I2C protocol for data transfer within the mobile device.

[0028] In a further aspect, a method for data transmission between at least one inter-integrated circuit node (I2C node) and at least one master controller is disclosed, the method comprising using a system according to the invention as described above or according to any one of the system embodiments described in more detail below, the method comprising the steps of: - generating data of a size larger than the physical register map and providing the register map using an I2C node; - reading the register map byte by byte using the master controller and incrementing the register address byte by byte using the I2C node; - reading a virtual section of the register map by executing a transaction starting in the physical register map using the master controller, wherein a transaction length of the transaction extends register addresses beyond the physical register map size.

[0029] The method steps may be performed in the order shown. However, it should be noted that different orders are possible. The method may include additional method steps not listed. Furthermore, one or more method steps may be performed once or repeatedly. Furthermore, two or more method steps may be performed simultaneously or with overlapping timing. The method may include repeating steps a predefined number of times or sequentially.

[0030] The method may be computer-implemented. As used herein, the term "computer-implemented method" is a broad term and should be given its ordinary and customary meaning to those skilled in the art, and should not be limited to any special or customized meaning. This term may specifically, but not exclusively, refer to a method that includes at least one computer and / or at least one computer network. The computer and / or computer network may include at least one processor configured to perform at least one of the method steps of the method according to the invention. In particular, each of the method steps is performed by the computer and / or computer network. The method may be performed fully automatically, in particular without user interaction.

[0031] The method may include transmitting sensor data generated by an I2C node. The I2C node may include at least one sensor. The sensor may include at least one element selected from the group consisting of at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel photosensor, and any sensor with a data buffer and automatic data storage. For example, the I2C node is a spectrometer. The spectrometer includes multiple pixels, each with a different wavelength filter, capable of measuring light intensity at a specific wavelength.

[0032] When an I2C node reaches the end of the physical register map, it may provide the next data by translating between the address of a further memory location and a physical address in memory.

[0033] When the register address reaches the end of the physical register map, the I2C node fills the physical register map with the values ​​from the virtual section and resets the physical address to zero. This process may be transparent to the master controller. The master controller may read values ​​and / or bytes from the virtual section as needed and / or as many as predefined by a driver, etc. This process may occur whenever the address of an additional memory location reaches a multiple of the size of the physical register map.

[0034] An I2C node may operate on at least one special register. When the master controller initiates a read of said special register, the I2C node may provide data to be stored in a further memory location. This process may be transparent to the master controller.

[0035] Further disclosed and proposed herein is a computer program comprising computer-executable instructions for carrying out the method according to the present invention in one or more of the embodiments encompassed herein when the program is run on a computer or a computer network. In particular, the computer program may be stored on a computer-readable data carrier and / or on a computer-readable storage medium.

[0036] As used herein, the terms "computer-readable data carrier" and "computer-readable storage medium" may particularly denote non-transitory data storage means such as hardware storage media on which computer-executable instructions are stored. A computer-readable data carrier or storage medium may particularly be or include a storage medium such as a random access memory (RAM) and / or a read-only memory (ROM).

[0037] Thus, in particular, one, more than one or all of the method steps as set out above may be carried out using a computer or computer network, preferably using a computer program.

[0038] Further disclosed and proposed herein is a computer program product having program code means for carrying out the method according to the invention in one or more of the embodiments encompassed herein when the program is run on a computer or a computer network. In particular, the program code means may be stored on a computer-readable data carrier and / or on a computer-readable storage medium.

[0039] Further disclosed and suggested in this specification is a data carrier having a data structure stored thereon, which may be loaded into a computer or computer network, for example into a working memory or main memory of the computer or computer network, and subsequently perform a method according to one or more embodiments disclosed in this specification.

[0040] Further disclosed and proposed herein is a computer program product having program code means stored on a machine-readable carrier for performing a method according to one or more embodiments disclosed herein when the program is run on a computer or a computer network. In this specification, a computer program product refers to a program as a tradeable product. The product can generally be present in any form, such as a paper medium, or on a computer-readable data carrier and / or computer-readable storage medium. In particular, the computer program product may be distributed via a data network.

[0041] Finally, disclosed and suggested herein is a modulated data signal containing instructions readable by a computer system or computer network for carrying out a method according to one or more embodiments disclosed herein.

[0042] With reference to computer-implemented aspects of the invention, one or more, or even all, of the method steps of the methods according to one or more of the embodiments disclosed herein may be performed using a computer or a computer network. Thus, in general, any of the method steps involving providing and / or manipulating data may be performed using a computer or a computer network. In general, these method steps may include any of the method steps, except those that typically require manual intervention, such as certain aspects of providing a sample and / or performing the actual measurement.

[0043] Specifically, further disclosed herein are: a computer or computer network comprising at least one processor, the processor being adapted to execute a method according to one of the embodiments described herein, - a computer-loadable data structure adapted to perform a method according to one of the embodiments described herein while the data structure is being executed on a computer; a computer program adapted to carry out a method according to one of the embodiments described herein while the program is running on a computer, a computer program comprising program means for carrying out the method according to one of the embodiments described herein while said computer program is running on a computer or on a computer network, a computer program comprising program means according to the embodiment, the program means being stored on a computer-readable storage medium; a storage medium having a data structure stored thereon, the storage medium being adapted to perform a method according to one of the embodiments described herein after the data structure has been loaded into a main and / or working storage device of a computer or a computer network; and - a computer program product having program code means, which may be stored on or is stored on a storage medium for performing a method according to one of the embodiments described herein when the program code means is executed on a computer or on a computer network.

[0044] In a further aspect of the invention, the use of a system according to any one of the embodiments described above or in more detail below with reference to the system is disclosed for a purpose selected from the group consisting of: infrared detection applications, heat detection applications, thermometer applications, heat seeking applications, flame detection applications, fire detection applications, smoke detection applications, temperature detection applications, spectroscopy applications, exhaust gas monitoring applications, combustion process monitoring applications, pollution monitoring applications, industrial process monitoring applications, chemical process monitoring applications; food processing process monitoring applications, water quality monitoring applications, air quality monitoring applications, quality control applications, temperature control applications, motion control applications, emissions control applications, gas detection applications, gas analysis applications, motion detection applications, chemical sensing applications, mobile applications, medical applications, mobile spectroscopy applications, food analysis applications.

[0045] As used herein, the terms "have," "comprise," "include," or any grammatical variations thereof, are used in a non-exclusive sense. Thus, these terms may refer to both the absence of any additional features in the entity described in this context, other than the features introduced by these terms, as well as the presence of one or more additional features. As an example, the expressions "A has B," "A comprises B," and "A includes B" may refer to both the absence of any other elements in A besides B (i.e., A consists only of B), and the presence of one or more additional elements in entity A besides B, such as element C, elements C and D, or further elements.

[0046] Furthermore, it should be noted that the terms "at least one," "one or more," or similar expressions indicating that a feature or element may be present one or more times are typically used only once when introducing each feature or element. In most cases, the phrase "at least one" or "one or more" will not be repeated when referring to each feature or element, regardless of the fact that each feature or element may be present one or more times.

[0047] Furthermore, as used herein, the terms "preferably," "more preferably," "particularly," "more particularly," "particularly," "more particularly," or similar terms are used in combination with any feature without limiting its alternative possibilities. Features introduced by these terms are therefore optional features and are not intended to limit the scope of the claims in any way. The present invention can be practiced using alternative features, as will be recognized by those skilled in the art. Similarly, features introduced by "in an embodiment of the invention" or similar expressions are intended to be optional features, without any limitation on alternative embodiments of the invention, without any limitation on the scope of the invention, and without any limitation on the possibility of combining the feature so introduced with other optional or non-optional features of the invention.

[0048] In summary, without excluding further possible embodiments, the following embodiments are envisaged:

[0049] "Embodiment 1" 1. A system including at least one inter-integrated circuit (I2C) node, at least one master controller, and at least one inter-integrated circuit (I2C) configured to transfer data between the I2C node and the master controller, the I2C node providing a register map, the master controller configured to read the register map byte by byte, the I2C node configured to increment register addresses for each byte, the register map including a physical register map, wherein data in the physical register map have physical addresses in a memory of the I2C node, the I2C node configured to generate data having a size larger than the physical register map, the register map including a virtual section, the data in the virtual section having addresses of further memory locations, and the master controller configured to read the virtual section by performing a transaction starting at the physical register map and incrementing register addresses beyond the physical register map size.

[0050] "Embodiment 2" 2. The system of claim 1, wherein the I2C node is configured to provide next data by translating between an address in a further memory location and a physical address in memory when the register address reaches the end of the physical register map.

[0051] "Embodiment 3" 3. The system of claim 1 or 2, wherein when the register address reaches the end of the physical register map, the I2C node is configured to fill the physical register map with values ​​from the virtual section and reset the physical address to zero, and this process is transparent to the master controller.

[0052] "Embodiment 4" A system according to embodiment 3, wherein the master controller is configured to read as many values ​​and / or bytes as needed and / or as many predefined numbers from the virtual section.

[0053] "Embodiment 5" 5. A system according to any one of embodiments 3 to 4, wherein this process occurs whenever the address of a further memory location reaches a multiple of the size of the physical register map.

[0054] "Embodiment 6" 6. A system as described in any one of embodiments 1 to 5, wherein the I2C node is configured to operate with at least one special register, and when the master controller initiates a read of the special register, the I2C node is configured to provide data to be stored in a further memory location, and this process is transparent to the master controller.

[0055] "Embodiment 7" 7. The system of embodiment 6, wherein the I2C node is configured to operate with a plurality of special registers.

[0056] "Embodiment 8" 8. The system of claim 6 or 7, wherein the special register is one or more of register 0, which is the last register of the physical register map.

[0057] "Embodiment 9" 9. A system according to any one of embodiments 1 to 8, wherein the further memory location is a memory location in which all data is available in a contiguous form.

[0058] "Embodiment 10" 10. The system of any one of embodiments 1 to 9, wherein the I2C node is configured to provide the physical register map as a standard 8-bit register map, and the I2C node is configured to generate data having a size N greater than 256 bytes.

[0059] "Embodiment 11" 12. The system of embodiment 11, wherein the I2C node comprises at least one sensor, the sensor comprising at least one element selected from the group consisting of at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, any sensor having a data buffer and automatic data storage.

[0060] "Embodiment 12" 12. The system of embodiment 11, wherein the I2C node is a spectrometer, the spectrometer being composed of a number of pixels, each having a different wavelength filter, and each pixel being capable of measuring light intensity at a particular wavelength.

[0061] "Embodiment 13" A mobile device comprising at least one system according to any one of embodiments 1 to 12, wherein the mobile device is at least one element selected from the group consisting of a notebook computer, a tablet, a mobile phone, a smartphone, a smart watch, and a wearable computer, and the mobile device is configured to use at least one I2C protocol for data transfer within the mobile device.

[0062] "Embodiment 14" 1. A method for data transmission between at least one inter-integrated circuit node (I2C node) and at least one master controller, the method comprising using a system according to any one of the preceding embodiments referring to the system, the method comprising the steps of: - generating data with a size larger than the physical register map and providing the register map using an I2C node; - Using the master controller to read the register map byte by byte and using an I2C node to increment the register address for each byte; - performing transactions starting in the physical register map and reading a virtual section of the register map by increasing register addresses beyond the physical register map size using the master controller; A method comprising:

[0063] "Embodiment 15" 15. The method of embodiment 14, wherein the I2C node provides the next data by translating between an address in a further memory location and a physical address in memory when the register address reaches the end of the physical register map.

[0064] "Embodiment 16" 10. The method of claim 1, wherein when a register address reaches the end of the physical register map, the I2C node fills the physical register map with values ​​from the virtual section and resets the physical address to zero, and this process is transparent to the master controller.

[0065] "Embodiment 17" 17. The method of embodiment 16, wherein the master controller reads as many values ​​and / or bytes as needed and / or as many predefined numbers from the virtual section.

[0066] "Embodiment 18" 18. The method of embodiment 16 or 17, wherein this process occurs each time the address of a further memory location reaches a multiple of the size of the physical register map.

[0067] "Embodiment 19" 10. A method as in any one of the preceding embodiments referring to a method, wherein an I2C node operates on at least one special register, and when a master controller initiates a read of said special register, the I2C node provides data to be stored in a further memory location, and this process is transparent to the master controller.

[0068] "Embodiment 20" 10. A method as in any one of the preceding embodiments referring to a method, the method including transmitting sensor data generated by an I2C node, the I2C node including at least one sensor, the sensor including at least one element selected from the group consisting of at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel optical sensor, any sensor having a data buffer and automatic data storage.

[0069] "Embodiment 21" 21. The method of embodiment 20, wherein the I2C node is a spectrometer, and the spectrometer includes a number of pixels, each having a different wavelength filter, and each pixel can measure light intensity at a specific wavelength.

[0070] "Embodiment 22" The method according to any one of the preceding method embodiments, wherein the method is computer-implemented.

[0071] "Embodiment 23" A computer program comprising instructions which, when the program is executed by a system according to any one of the preceding embodiments referring to a system, cause the system to perform a method according to any one of the preceding embodiments referring to a method.

[0072] "Embodiment 24" A computer-readable storage medium comprising instructions that, when executed by a system according to any one of the preceding embodiments referring to a system, cause the system to perform a method according to any one of the preceding embodiments referring to a method.

[0073] "Embodiment 25" A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method according to any one of the preceding embodiments referring to a method.

[0074] "Embodiment 26" Use of the system of any one of the preceding embodiments referring to the system for an intended use selected from the group consisting of: infrared detection applications; heat detection applications; thermometer applications; heat seeking applications; flame detection applications; fire detection applications; smoke detection applications; temperature detection applications; spectroscopy applications; exhaust gas monitoring applications; combustion process monitoring applications; pollution monitoring applications; industrial process monitoring applications; chemical process monitoring applications; food processing process monitoring applications, water quality monitoring applications, air quality monitoring applications, quality control applications, temperature control applications, motion control applications, exhaust control applications, gas detection applications, gas analysis applications, motion detection applications, chemical detection applications, mobile applications, medical applications, mobile spectroscopy applications, food analysis applications. [Brief explanation of the drawings]

[0075] Further optional features and embodiments are disclosed in more detail in the description of the following embodiments, preferably in conjunction with the dependent claims, where each optional feature may be realized in isolation as well as in any possible combination, as understood by a person skilled in the art. The scope of the present invention is not limited by the preferred embodiments. The embodiments are schematically depicted in the figures, where identical reference numerals in these figures represent identical or functionally equivalent elements. [Figure 1] FIG. 1 shows one embodiment of a system according to the present invention. [Figure 2] 2A and 2B show the reading of data. [Figure 3] FIG. 3 illustrates an embodiment of the method according to the invention. [Figure 4] FIG. 4 shows a further embodiment of the method according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0076] FIG. 1 illustrates one embodiment of a system 110, e.g., a mobile device 111, in accordance with the present invention. The system 110 includes at least one inter-integrated circuit node (I2C node) 112, at least one master controller 114, and at least one inter-integrated circuit (I2C) 116. The I2C 116 is configured to transfer data between the I2C node 112 and the master controller 114. The I2C node 112 provides a register map 118. The master controller 114 is configured to read the register map 118 byte by byte. The I2C node 112 is configured to increment a register address for each byte. The register map 118 includes a physical register map 120. Data in the physical register map 120 has a physical address in the memory 122 of the I2C node 112. The I2C node 112 is configured to generate data of a size larger than the physical register map 120. The register map 118 includes a virtual section. The data in the virtual section has an address in a further memory location 124. The master controller 114 is configured to read the virtual section by executing a transaction that starts in the physical register map 120. The transaction length of the transaction exceeds the physical register map size. In particular, the transaction starts at a start address and the transaction length is greater than the size of the physical register map.

[0077] The inter-integrated circuit 116 may be a data bus configured to connect integrated circuits. For example, the I2C 116 may be designed as described in https: / / www.nxp.com / docs / en / user-guide / UM10204.pdf, www.ipd.kit.edu / ~buchmann / microcontroller / i2c.htm, or www.ti.com / lit / an / slva704 / slva704.pdf. The I2C 116 may be a synchronous, packet-switched, single-ended, serial communication bus. Specifically, the I2C 116 is a hierarchical bus system with a so-called master-slave architecture, including a master controller 114 and an I2C node 112.

[0078] The system 110 may include one or more I2C nodes 112. The I2C node 112 may be any I2C device connected to the I2C bus 116. For example, the I2C node 112 includes at least one sensor. The sensor may include at least one element selected from the group consisting of at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel photosensor, and any sensor with a data buffer and automatic data storage (smart sensor). For example, the I2C node 112 is a spectrometer. The spectrometer includes multiple pixels, each with a different wavelength filter, and each pixel can measure light intensity at a specific wavelength. The I2C node 112 may further include at least one processor, such as at least one microprocessor, at least one microcontroller, and / or at least one computer.

[0079] The system may include one or more master controllers 114. The master controller 114 may be or include at least one processor, such as at least one microprocessor, at least one microcontroller, and / or at least one computer assigned to be the master of the system. The master controller 114 may be configured to address one or more I2C nodes 112, but not vice versa. The I2C 116 is configured to transmit data between the I2C nodes 112 and the master controller 114. The transmission may include a data exchange. The data may be transferred in a sequence of 8 bits. One data bit may be transferred during each clock cycle.

[0080] The I2C bus 116 may be based on two lines, where one line is used to transmit a clock signal (serial clock line, SCL) and the other line is used to transmit data bits (serial data line, SDA). The clock signal may be generated by a master controller 114. The master controller 114 may be configured to initiate data transmission by sending a query to the I2C nodes 112. To initiate data transmission, the master controller 114 may be configured to specify the addresses of the I2C nodes 112 with which to exchange data. Each I2C node 112 may have a specific 4-bit address hardwired into its chip. Furthermore, each I2C node 112 chip may include multiple address pins to which any address can be assigned. Multiple bits, for example, 7 bits, may be used and transferred to address each I2C node 112. At least one additional bit may be used to specify whether the master controller 114 is sending (i.e., writing) data to or receiving (i.e., reading) data from the I2C node 112. As described in www.ti.com / lit / an / slva704 / slva704.pdf, the procedure for the master controller 114 to read data from an I2C node is as follows:

[0081] - The master controller 114 sends a START condition and addresses the I2C node 112; - The master controller 114 sends the requested register to the I2C node 112; - The master controller 114 receives data from the I2C node 112; The master controller 114 defines a STOP condition to end a transfer when the SDA line transitions from low to high while SCL is high.

[0082] The I2C node 112 may include one or more registers. A register may be a location in the memory 122, 124 of the I2C node 112 configured to store information. The information may be configuration information and / or data acquired by at least one sensor of the I2C node 112. The information stored in a register may be one or more of values, particularly a measurement value, a measurement uncertainty, a calibration value, a (system) configuration value, and a measurement parameter. Each register may have a unique address. Each register may contain 8 bits. The master controller 114 is configured to read and optionally write the register map byte by byte. The master controller 114 can read and write the register map byte by byte. The I2C node 112 is configured to increment the register address for each byte.

[0083] Typically, reading from a register may be performed, for example, as follows: www.ti.com / lit / an / slva704 / slva704.pdf. Master controller 114 may be configured to instruct I2C node 112 which register map 118 to read from. Master controller 114 may be configured to initiate transmission by sending an address including a bit designated for writing, followed by the register address desired to read. After I2C node 112 acknowledges this register address, master controller 114 may again send a START condition, followed by the I2C node address with a bit designated for reading. I2C node 112 may acknowledge the read request. Master controller 114 may continue sending clock pulses, but release the SDA line to allow I2C node 112 to send data. After each byte of data, the master controller 114 may send an ACK (acknowledge) to the I2C node 112, informing the I2C node 112 that more data is ready. When the master controller 114 receives the expected number of bytes, it may send a NACK (not acknowledge) to inform the I2C node 112 to stop communication and release the bus. The master controller 114 may then send a STOP condition. The master controller 114 can read and write to the register map 118 byte by byte. The I2C node 112 may be configured to automatically increment the address after each byte, allowing a single transaction to include multiple bytes.

[0084] As described above, the I2C node 112 provides a register map 118. The register map may be an ordered list of registers. The I2C node 112 may include one or more registers. Each register may have a unique address. The register map 118 may include a register map layout. The register map 118 may include multiple columns and rows. The register map 118 may include an index N for each register. For example, as shown in FIG. 1, the register map 118 may include two columns, where the first column contains the index and the second column contains the register name. The register map 118 may include a size. The size of the index N may be equal to the size of the register map 118.

[0085] The register map 118 includes a physical register map 120. Data in the physical register map 120 has physical addresses in the memory 122 of the I2C node 112. The I2C node 112 is configured to generate data that is larger in size than the physical register map 120. The physical register map 120 may be part of the register map 118, which includes registers with physical addresses in the memory 122 of the I2C node 112. The memory 122 may be or include a device or system configured to store data. The memory 122 may include semiconductor memory. The memory 122 of the I2C node 112 may include volatile memory and / or non-volatile memory. For example, the memory 122 of the I2C node 112 may include one or more RAMs, such as dynamic random access memory (DRAM) or static random access memory (SRAM). For example, memory 122 of I2C node 112 may include one or more of flash memory, ROM, PROM, EPROM, EEPROM memory, and ferroelectric random access memory (FRAM). Physical register map 120 may include a physical register map size. I2C node 112 may be configured to provide physical register map 120 as a standard 8-bit register map. The physical register map size may be N≦256. I2C node 112 may be configured to generate data whose size N exceeds 256 bytes.

[0086] Typically, the size of the physical register map 120 is 256 bytes, with index N ranging from 0 to 255. However, the I2C node 112 may generate data that is larger in size (e.g., greater than 256 bytes) than the physical register map 120 (size N>256). In this case, for example, the register map size may be increased. However, this may not be possible under certain circumstances, such as when the I2C node 112 does not have enough RAM or when the register address size is fixed at 8 bits for software compatibility. Additionally or alternatively, the register map 118 may be divided into smaller sizes and data transfers may be performed using multiple transactions. An example is shown in the table below:

[0087] [Table 1]

[0088] For example, data is divided into small pieces, such as 128-byte values, that fit into the register map 118. The register map 118 may include a special control register named "partition index" that controls which partition is accessed by the master controller. To read all the data, the master controller may first perform a write transaction to the partition index, followed by a read transaction that can transfer up to 254 bytes. This pair of transactions must be performed multiple times until all the data is transferred. Therefore, if the data is partitioned (segmented) and a partition index is used, multiple transactions must be performed. Such a data transfer is shown in Figure 2A. However, with partitioning, gaps in the transfer between transactions occur. The gaps between transactions are due to one or more of the following: a) the bus may be in use by another sensor; b) natural processing delays, i.e., starting a new transaction takes several CPU cycles; or c) the process requesting the next transfer sleeps and waits to be rescheduled (on systems with an operating system). The contributions of a) and b) primarily depend on the system load and processor performance. Depending on the number of bytes and the operating system, these gaps can be large (e.g., non-real-time operating systems like Linux or Android).

[0089] Specifically, to enable high-speed reads when the I2C node 112 generates data larger than the physical register map 120, the present invention proposes a register map 118 that includes a virtual section. The register map 118 may be virtually expanded. The data in the virtual section have addresses in additional memory locations 124. The virtual section may be an additional portion of the register map 118, i.e., registers that have addresses in additional memory locations 124 in addition to the physical register map 120. The additional memory locations 124 may be physical storage locations in the I2C node 112 that are different from the memory 122. The additional memory locations 124 may be memory locations where all data is available in a contiguous format. Because of the contiguous format, the I2C node 112 can provide all data for reading in a single transaction.

[0090] The following table shows an example of a register map layout using virtual extensions:

[0091] [Table 2]

[0092] The virtual section cannot be directly addressed. The master controller 114 is configured to read the virtual section by executing a transaction starting in the physical register map 120. The length of the transaction exceeds the physical register map size. To read all data generated by the I2C node 112, the master controller 114 can start reading the first value (e.g., register address 0) and continue reading even after reading value 255 until all data in the registers of the virtual section (e.g., values ​​256 to N, where N > 256) has been transferred. In this approach, all data is transferred in a single read transaction. Virtually expanding the register map may provide the fastest solution for transferring all data. Such a data transfer is shown in Figure 2B.

[0093] As described above, the I2C node 112 may be configured to automatically increment the address by byte. When the address reaches the end of the physical register map 120, data cannot be fetched from the next consecutive physical address. The I2C node 112 may be configured to provide the next data from the first register in the virtual section. When the register address reaches the end of the physical register map 120, the I2C node 112 may be configured to provide the next data by translating between an address in a further memory location 124 and a physical address in memory 122.

[0094] For example, as shown in FIG. 3 , the master controller may read 1 byte of N bytes (reference numeral 126). If the transfer ends but the end of the register map (reference numeral 128) has not been reached (reference numeral 130), the I2C node 112 updates and / or refills the physical register map 120 with the original values ​​from page 0 (reference numeral 132). If the end of the register map (reference numeral 128) has not been reached and the transfer does not end (reference numeral 130), the master controller continues reading 1 byte of N bytes (reference numeral 126). However, if the end of the register map (reference numeral 128) is reached before the end of the transfer, the I2C node 112 may be configured to fill and / or update the physical register map 120 with values ​​from the virtual section (reference numeral 134) and reset the physical address to zero when the register address reaches the end of the physical register map 120 (reference numeral 128). This process may be transparent to the master controller 114. The master controller 114 may be configured to read as many values ​​and / or bytes from the virtual section as needed and / or as predefined, for example via a driver. This process may occur whenever the address in the further memory locations 124 reaches a multiple of the size of the physical register map 120. The I2C node 112 may be configured to update and / or refill the physical register map 120 with the original values ​​from page 0 after the transfer is complete (reference numeral 132).

[0095] FIG. 4 illustrates a further embodiment in which the I2C node 112 may be configured to operate with at least one special register. The I2C node 112 may also be configured to operate with multiple special registers. A virtual extension of the physical register map 120 may be available only if a read is initiated from a special register (or one of multiple special registers). A special register may be a register in the physical register map 120 with a predefined and / or preassigned function. A special register may be any register or multiple registers in the physical register map 120. Other embodiments are possible. For example, a special register may be located after all register values ​​(if any) in the physical register map. The I2C node 112 may be configured to provide data to be stored in an additional memory location 124 when the master controller 114 initiates a read of the special register. This may also be transparent to the master controller 114. For example, the I2C node 112 may internally transmit data stored in a different memory location when the master controller 114 correctly initiates a read of the special register. If the read is initiated from a special register, the I2C node 112 may fetch the data from a special memory location where all data is available contiguously, rather than from the physical register map 120. The address of the further memory location 124 may be defined by an offset from the location of another register, e.g., the special register. As shown in Figure 4, in step 136, the master controller reads N bytes. If the special register has not been reached (reference numeral 138), the I2C node transmits data from the physical register map (reference numeral 140). If the special register has been reached (reference numeral 138), the I2C node transmits data from the further memory location (reference numeral 142). [Explanation of symbols]

[0096] 110 System 111 Mobile Devices 112 I2C nodes 114 Master Controller 116 I2C 118 Register Map 120 Physical Register Map 122 Memory 124 more memory locations 126 Master controller reads 1 byte out of N bytes 128 End of register map 130 Transfer Completed 132 Updating and / or refilling the physical register map 134 Filling and / or updating the physical register map 120 with values ​​from the virtual section 136 Master controller reads N bytes 138 Special Enrollment Reached? 140 I2C nodes send data from the physical register map 142 I2C node sends data from more memory locations

Claims

1. A system (110) comprising at least one inter-integrated circuit node (I2C node) (112), at least one master controller (114), and at least one inter-integrated circuit (I2C) (116), wherein the I2C (116) is configured to transfer data between the I2C node (112) and the master controller (114), wherein the I2C node (112) provides a register map (118), the master controller (114) is configured to read the register map (118) byte by byte, the I2C node (112) is configured to increment a register address for each byte, and the register map (118) is configured to provide a physical register map (118). 20), wherein data in a physical register map (120) has physical addresses in a memory of an I2C node (122), the I2C node (112) is configured to generate data that is larger in size than the physical register map (120), the register map (118) includes a virtual section, data in the virtual section having addresses in further memory locations (124), and the master controller (114) is configured to read the virtual section by executing a transaction starting from the physical register map (118), the transaction length of the transaction exceeding the physical register map size.

2. 2. The system of claim 1, wherein the I2C node is configured to provide next data when the register address reaches the end of the physical register map by translating between an address in a further memory location and a physical address in the memory.

3. 3. The system of claim 1, wherein when the register address reaches the end of the physical register map, the I2C node is configured to fill the physical register map with values ​​from the virtual section and reset the physical address to zero, the process being transparent to the master controller.

4. 4. The system of claim 3, wherein the master controller is configured to read a required and / or predefined number of values ​​and / or bytes from the virtual section.

5. 4. The system (110) of claim 3, wherein this process occurs each time the address of the additional memory location (124) reaches a multiple of the size of the physical register map (120).

6. 3. The system (110) of claim 1 or 2, wherein the I2C node (112) is configured to operate with at least one special register, and when the master controller (114) initiates a read of the special register, the I2C node (112) is configured to provide data to be stored in a further memory location (124), the process being transparent to the master controller (114).

7. 3. The system (110) of claim 1 or 2, wherein the further memory location (124) is a memory location in which all data is available in contiguous form.

8. 8. The system of claim 7, wherein the I2C node comprises at least one sensor, the sensor comprising at least one element selected from the group consisting of at least one spectrometer, at least one multi-channel IR sensor, at least one multi-channel light sensor, and any sensor having a data buffer and automatic data storage.

9. A mobile device (111) comprising at least one system (110) according to claim 1 or 2, wherein the mobile device (111) is at least one element selected from the group consisting of a notebook computer, a tablet, a mobile phone, a smartphone, a smart watch, and a wearable computer, and the mobile device (111) is configured to use at least one I2C protocol for data transfer within the mobile device (111).

10. A method for data transmission between at least one inter-integrated circuit node (I2C node) (112) and at least one master controller (114), the method comprising using a system (110) according to claim 1 or 2 referring to the system, the method comprising the following steps: - generating data of a size larger than the physical register map (120) and providing the register map (118) using an I2C node (112); - reading the register map (118) byte by byte using the master controller (114) and incrementing the register address byte by byte using the I2C node (112); - reading a virtual section of a register map (118) using a master controller (114) by executing a transaction starting from a physical register map (120), the transaction length of the transaction exceeding the physical register map size; A method comprising:

11. 11. The method of claim 10, wherein the method is computer-implemented.

12. A computer program comprising instructions that, when executed by a system (110) according to claim 1 referring to a system, cause the system (110) to perform the method according to claim 10 referring to a method.

13. A computer-readable storage medium comprising instructions that, when executed by a system (110) as recited in claim 1, cause the system (110) to perform the method as recited in claim 10.

14. 11. A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform the method of claim 10.

15. 3. Use of the system (110) of claim 1 or 2, referring to a system, for an intended use selected from the group consisting of: infrared detection applications; heat detection applications; thermometer applications; heat seeking applications; flame detection applications; fire detection applications; smoke detection applications; temperature detection applications; spectroscopy applications; exhaust gas monitoring applications; combustion process monitoring applications; pollution monitoring applications; industrial process monitoring applications; chemical process monitoring applications; food processing process monitoring applications, water quality monitoring applications, air quality monitoring applications, quality control applications, temperature control applications, motion control applications, emission control applications, gas detection applications, gas analysis applications, motion detection applications, chemical detection applications, mobile applications, medical applications, mobile spectroscopy applications, and food analysis applications.

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