Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate includes a display area AA, the display area AA includes a translucent display area A1, the display substrate includes a plurality of light-emitting elements and a plurality of pixel circuits, the plurality of light-emitting elements include a plurality of first-type light-emitting elements L1 located in the translucent display area A1, the plurality of pixel circuits include a plurality of first-type pixel circuits P1 located in the translucent display area A1, at least one first-type pixel circuit P1 among the plurality of first-type pixel circuits P1 is electrically connected to at least two first-type light-emitting elements L1 that emit light of the same color, and the first-type pixel circuit P1 is configured to drive the emission of the at least two first-type light-emitting elements L1, and there is an overlapping portion between the orthogonal projection at a base of the at least one first-type pixel circuit P1 and the orthogonal projection at a base of the at least one first-type light-emitting element L1.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and more particularly to display substrates and display devices. [Background technology]

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices that offer advantages such as autonomous light emission, wide viewing angles, high contrast, low power consumption, extremely fast response speed, light weight, bendability, and low cost. Under-display camera technology is a completely new technology proposed to improve the screen occupancy rate of display devices. Summary of the Invention

[0003] The following is a summary of the subject matter described herein, which does not limit the scope of protection of the claims.

[0004] In a first aspect, the present invention provides a display substrate, the display substrate including a display area and a peripheral area at least partially surrounding the display area, the display area including a light-transmitting display area and a normal display area located at least on one side of the light-transmitting display area, and a light transmittance of the light-transmitting display area is greater than that of the normal display area; the display substrate includes a base and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the base, the plurality of light-emitting elements including a plurality of first-type light-emitting elements located in the light-transmitting display area, the plurality of pixel circuits including a plurality of first-type pixel circuits located in the light-transmitting display area, at least one first-type pixel circuit among the plurality of first-type pixel circuits is electrically connected to at least two first-type light-emitting elements emitting light of the same color, and the first-type pixel circuit is configured to drive the emission of the at least two first-type light-emitting elements; There is an overlap between the orthogonal projection of the at least one first-type pixel circuit on the base and the orthogonal projection of the at least one first-type light-emitting element on the base.

[0005] In an exemplary embodiment, there is an overlap between the orthogonal projection of the at least one first-type pixel circuit on the base and the orthogonal projection of at least some of the first-type light-emitting elements of the at least two first-type light-emitting elements electrically connected to the at least one first-type pixel circuit on the base.

[0006] In an exemplary embodiment, the pixel circuit further includes a plurality of first signal lines, and the at least one first-type pixel circuit is electrically connected to at least one first signal line; The plurality of first signal lines include at least one of a scanning signal line, a reset signal line, an initial signal line, and a light-emitting signal line.

[0007] In an exemplary embodiment, the plurality of first signal lines include a plurality of sub-signal lines, and adjacent sub-signal lines of the first signal lines are electrically connected via the first type pixel circuits that electrically connect them.

[0008] In an exemplary embodiment, the pixel circuit further includes a plurality of second signal lines, and the at least one first-type pixel circuit is electrically connected to at least one second signal line; The plurality of second signal lines include at least one of data signal lines and first power supply lines, the plurality of data signal lines and the plurality of first power supply lines extend along a first direction, the data signal lines and first power supply lines electrically connected to the first type pixel circuits are located between adjacent sub-signal lines of the first signal lines, and orthogonal projections of the data signal lines and first power supply lines electrically connected to the first type pixel circuits at the base overlap with orthogonal projections of the first type pixel circuits at the base.

[0009] In an exemplary embodiment, the orthogonal projection of at least one of the scanning signal line, the reset signal line, the initial signal line, the light emitting signal line, the data signal line, and the first power supply line on the base partially overlaps with the orthogonal projection of the first type light emitting element on the base.

[0010] In an exemplary embodiment, the plurality of first-type light-emitting elements includes at least a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light; an anode area of ​​at least one first light-emitting element among the plurality of first light-emitting elements is larger than an anode area of ​​at least one third light-emitting element among the plurality of third light-emitting elements, an anode area of ​​at least one second light-emitting element among the plurality of second light-emitting elements is larger than an anode area of ​​the at least one third light-emitting element, and an anode area of ​​at least one second light-emitting element among the plurality of second light-emitting elements is larger than an anode area of ​​at least one first light-emitting element among the plurality of first light-emitting elements; The first color light is red light, the second color light is blue light, and the third color light is green light.

[0011] In an exemplary embodiment, the first-type pixel circuit includes a plurality of transistors and at least one capacitor, and in a direction perpendicular to the display substrate, the light-transmitting display region includes at least a semiconductor layer disposed on the base, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer; the semiconductor layer includes at least active layers of a plurality of transistors of the first type pixel circuit; the first conductive layer includes at least control electrodes of a plurality of transistors of the first type pixel circuits and first plates of capacitors; the second conductive layer includes at least a second plate of a capacitor of the first type pixel circuit; the third conductive layer includes at least first and second electrodes of a plurality of transistors of the first type pixel circuit and a plurality of connecting electrodes; the transparent conductive layer includes at least a plurality of first signal lines, a plurality of second signal lines, and a plurality of anode connecting lines, at least one anode connecting line among the plurality of anode connecting lines is electrically connected to at least one first-type pixel circuit and an anode of at least two first-type light-emitting elements that emit light of the same color, and the at least one first-type pixel circuit is electrically connected to at least one first signal line and at least one second signal line; The fourth conductive layer includes at least a plurality of signal connection lines.

[0012] In an exemplary embodiment, the plurality of first-type light-emitting elements are arranged in the following manner: The plurality of third light-emitting elements are arranged in an i-th row at regular intervals, the second light-emitting elements and the first light-emitting elements are alternately arranged in adjacent rows of the i-th row, the first light-emitting elements and the second light-emitting elements are alternately arranged in a j-th column, the plurality of third light-emitting elements are arranged in adjacent columns of the j-th column at regular intervals, the first light-emitting elements and the third light-emitting elements are alternately arranged along a third direction, and the second light-emitting elements and the third light-emitting elements are alternately arranged along a fourth direction, the third direction and the fourth direction intersect with the first direction and the second direction, respectively, the first direction is a column direction, and the second direction is a row direction.

[0013] In an exemplary embodiment, the plurality of first-type pixel circuits include at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit, and at least one fourth pixel circuit, wherein the first pixel circuit is electrically connected to two of the first light-emitting elements, the second pixel circuit is electrically connected to two of the second light-emitting elements, the third pixel circuit is electrically connected to two of the third light-emitting elements, and the fourth pixel circuit is electrically connected to two of the third light-emitting elements, and the third pixel circuit and the third light-emitting element electrically connected to the fourth pixel circuit are different.

[0014] In an exemplary embodiment, the two first light-emitting elements electrically connected to the first pixel circuit are located in the same row, the two second light-emitting elements electrically connected to the second pixel circuit are located in the same row, the two third light-emitting elements electrically connected to the third pixel circuit are located in the same row, and the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same row.

[0015] In an exemplary embodiment, an orthogonal projection of the first pixel circuit on the base partially overlaps an orthogonal projection of one of the first light-emitting elements electrically connecting thereto on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps an orthogonal projection of the first light-emitting element located between two second light-emitting elements electrically connected to the second pixel circuit on the base; an orthogonal projection of the third pixel circuit on the base partially overlaps with an orthogonal projection of the second light-emitting element on the base, and the second light-emitting element overlapping with the third pixel circuit is located in a row adjacent to a row in which two of the third light-emitting elements electrically connected to the third pixel circuit are located, and is located in a middle column in which two of the third light-emitting elements electrically connected to the third pixel circuit are located; The orthogonal projection of the fourth pixel circuit on the base partially overlaps with the orthogonal projection of the second light-emitting element on the base, the second light-emitting element overlapping with the fourth pixel circuit is located in a row adjacent to the row in which the two third light-emitting elements electrically connected to the fourth pixel circuit are located, and is located in an intermediate column between the columns in which the two third light-emitting elements electrically connected to the fourth pixel circuit are located, and the second light-emitting element overlapping with the third pixel circuit is a light-emitting element different from the second light-emitting element overlapping with the fourth pixel circuit.

[0016] In an exemplary embodiment, the first signal line extends along a second direction; the anode connecting lines include a first anode connecting line, a second anode connecting line, a third anode connecting line, and a fourth anode connecting line; the first anode connecting line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line extends along the second direction; the second anode connecting line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line extends along the second direction; the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the second direction; the third anode connecting line is located between a data signal line electrically connected to the third pixel circuit and a first power supply line; the fourth anode connecting line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connecting line extends along the second direction; and the fourth anode connecting line is located between a data signal line electrically connected to the fourth pixel circuit and a first power supply line.

[0017] In an exemplary embodiment, first power supply lines electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced apart first power supply lines located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer; The data signal lines electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced apart data signal lines located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.

[0018] In an exemplary embodiment, the two first light-emitting elements electrically connected to the first pixel circuit are arranged along a third direction, the two second light-emitting elements electrically connected to the second pixel circuit are arranged along a fourth direction, the two third light-emitting elements electrically connected to the third pixel circuit are located in the same column, and the two third light-emitting elements electrically connected to the fourth pixel circuit are located in the same column.

[0019] an orthogonal projection of the first pixel circuit on the base partially overlaps with an orthogonal projection of one of the first light-emitting elements electrically connected thereto on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; an orthogonal projection of the third pixel circuit on the base partially overlaps with an orthogonal projection of one of the third light-emitting elements electrically connected thereto on the base; The orthogonal projection of the fourth pixel circuit on the base partially overlaps with the orthogonal projection of one of the third light-emitting elements electrically connected thereto on the base, and the third light-emitting element overlapping with the third pixel circuit is a light-emitting element different from the third light-emitting element overlapping with the fourth pixel circuit.

[0020] In an exemplary embodiment, the anode connecting lines include a first anode connecting line, a second anode connecting line, a third anode connecting line, and a fourth anode connecting line; the first anode connecting line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line extends along the first direction; the second anode connecting line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line extends along the first direction; the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the first direction; the third anode connecting line is located on a side of the first power supply line remote from the data signal line to which the third pixel circuit is electrically connected; the fourth anode connecting line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connecting line extends along the first direction; and the fourth anode connecting line is located on a side of the first power supply line remote from the data signal line to which the fourth pixel circuit is electrically connected.

[0021] In an exemplary embodiment, the data signal line electrically connecting first type pixel circuits located in the same column is the same signal line, the first power supply lines electrically connecting at least two adjacent first type pixel circuits located in the same column are spaced apart, and the spaced apart first power supply lines located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.

[0022] In an exemplary embodiment, the transparent conductive layer further includes a power connection line, at least a portion of the power connection line extending along a second direction; The power supply connection lines are each electrically connected to a first power supply line that electrically connects two adjacent first-type pixel circuits located in the same row, and the first power supply lines and the power supply connection lines are electrically connected via a connection electrode located in the third conductive layer.

[0023] In this exemplary embodiment, for the same first type pixel circuit, the first power supply line includes a power supply main body portion extending along the first direction and a power supply connection portion extending along the second direction, and the power supply connection portion is located on a side of the power supply main body away from the data signal line, The power supply connection line is electrically connected to the power supply connection portion of one of the first-type pixel circuits and the power supply main body portion of the other of the first-type pixel circuits located in the same row.

[0024] In an exemplary embodiment, the plurality of first-type light-emitting elements are arranged in the following manner: The plurality of second light-emitting elements are arranged in a jth column, the first light-emitting elements and the third light-emitting elements are arranged alternately in adjacent jth columns, the plurality of second light-emitting elements are arranged in an ith row, and the first light-emitting elements and the third light-emitting elements are installed between adjacent second light-emitting elements located in the same row.

[0025] In an exemplary embodiment, the plurality of first-type pixel circuits include at least one first pixel circuit, at least one second pixel circuit, and at least one third pixel circuit, wherein the first pixel circuit is electrically connected to two of the first light-emitting elements, the second pixel circuit is electrically connected to two of the second light-emitting elements, and the third pixel circuit is electrically connected to two of the third light-emitting elements.

[0026] In an exemplary embodiment, the two first light-emitting elements electrically connected to the first pixel circuit are located in the same row, the two second light-emitting elements electrically connected to the second pixel circuit are located in the same row, and the two third light-emitting elements electrically connected to the third pixel circuit are located in the same row.

[0027] In an exemplary embodiment, an orthogonal projection of the first pixel circuit on the base partially overlaps an orthogonal projection of one of the first light-emitting elements electrically connecting thereto on the base;

[0028] an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; The orthogonal projection of the third pixel circuit on the base partially overlaps with the orthogonal projection of one of the third light-emitting elements electrically connected thereto on the base.

[0029] In an exemplary embodiment, at least two of the first light emitting element overlapping the first pixel circuit, the second light emitting element overlapping the second pixel circuit, and the third light emitting element overlapping the third pixel circuit are adjacent.

[0030] In an exemplary embodiment, an orthogonal projection of the first pixel circuit on the base partially overlaps an orthogonal projection of one of the first light-emitting elements electrically connecting thereto on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; The orthogonal projection of the third pixel circuit on the base partially overlaps with the orthogonal projection on the base of the second light-emitting element located between the two third light-emitting elements electrically connected by the third pixel circuit.

[0031] In an exemplary embodiment, an orthogonal projection of the first pixel circuit on the base partially overlaps an orthogonal projection of a second light-emitting element located between two of the first light-emitting elements electrically connected to the first pixel circuit, on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; The orthogonal projection of the third pixel circuit on the base partially overlaps with the orthogonal projection of one of the third light-emitting elements electrically connected thereto on the base.

[0032] In an exemplary embodiment, the anode connection lines include a first anode connection line, a second anode connection line, and a third anode connection line; The first anode connecting line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line extends along the second direction, the second anode connecting line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line extends along the second direction, and the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the second direction.

[0033] In an exemplary embodiment, the data signal line electrically connecting first type pixel circuits located in the same column is the same signal line, the first power supply lines electrically connecting at least two adjacent first type pixel circuits located in the same column are spaced apart, and the spaced apart first power supply lines located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.

[0034] In an exemplary embodiment, the plurality of light-emitting elements further includes a plurality of second-type light-emitting elements located in the normal display area, and the plurality of pixel circuits further includes a plurality of second-type pixel circuits located in the normal display area; At least one second-type light-emitting element among the plurality of second-type light-emitting elements is electrically connected to at least one second-type pixel circuit among the plurality of second-type pixel circuits, and there is an overlapping portion between the orthogonal projection of the second-type light-emitting element on the base and the orthogonal projection of the second-type pixel circuit electrically connected to it on the base.

[0035] In a second aspect, the present disclosure further provides a display device comprising the display substrate.

[0036] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0037] [Figure 1] 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 2] 1 is a schematic diagram 1 of an arrangement of a first type of light-emitting element in a light-transmitting display area according to at least one embodiment of the present disclosure. [Figure 3] 2 is a schematic diagram 2 of the arrangement of the first type of light-emitting element in the light-transmitting display area according to at least one embodiment of the present disclosure. [Figure 4] 1 is a schematic diagram 1 illustrating a layout relationship between a first-type pixel circuit and a first-type light-emitting element in a light-transmitting display area according to an exemplary embodiment; [Figure 5] FIG. 2 is a schematic diagram 2 illustrating the arrangement relationship between the first-type pixel circuits and the first-type light-emitting elements in the light-transmitting display area according to an exemplary embodiment; [Figure 6] 3 is a schematic diagram 3 of the arrangement relationship between the first-type pixel circuits and the first-type light-emitting elements in the light-transmitting display area according to an exemplary embodiment; FIG. [Figure 7] 4 is a schematic diagram 4 illustrating the arrangement relationship between the first-type pixel circuits and the first-type light-emitting elements in the light-transmitting display area according to an exemplary embodiment; FIG. [Figure 8] 5 is a schematic diagram 5 of the arrangement relationship between the first-type pixel circuits and the first-type light-emitting elements in the light-transmitting display area according to an exemplary embodiment; FIG. [Figure 9] 6 is a schematic diagram 6 illustrating the arrangement relationship between the first-type pixel circuits and the first-type light-emitting elements in the light-transmitting display area according to an exemplary embodiment; [Figure 10] FIG. 2 is an equivalent circuit diagram of a first type pixel circuit. [Figure 11] 11 is an operation timing chart of the first type pixel circuit in FIG. 10. [Figure 12] 1 is a partial plan view of a translucent display area according to an exemplary embodiment; [Figure 13] FIG. 2 is a partial plan view of a translucent display area according to an exemplary embodiment. [Figure 14] 3 is a partial plan view 3 of a translucent display area according to an exemplary embodiment. [Figure 15A] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a semiconductor pattern is formed therein. [Figure 15B] 13 is a schematic diagram of a first conductive layer pattern in the light-transmitting display area shown in FIG. 12. FIG. [Figure 15C] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a first conductive layer pattern is formed. FIG. [Figure 15D] 13 is a schematic diagram of a second conductive layer pattern in the light-transmitting display area shown in FIG. 12. FIG. [Figure 15E] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a second conductive layer pattern is formed. FIG. [Figure 15F] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a third insulating layer pattern is formed. FIG. [Figure 15G] 13 is a schematic diagram of a third conductive layer pattern in the light-transmitting display area shown in FIG. 12. FIG. [Figure 15H] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a third conductive layer pattern is formed. FIG. [Figure 15I] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a fourth insulating layer pattern is formed. FIG. [Figure 15J]13 is a schematic diagram of a transparent conductive layer pattern in the light-transmitting display area shown in FIG. 12. FIG. [Figure 15K] 13 is a schematic diagram of the transparent display area according to FIG. 12 after a transparent conductive layer pattern is formed therein. [Figure 15L] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a first flat layer is formed. FIG. [Figure 15M] 13 is a schematic diagram of a fourth conductive layer pattern in the light-transmitting display area shown in FIG. 12. FIG. [Figure 15N] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a fourth conductive layer pattern is formed. FIG. [Figure 15O] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after a second flat layer pattern is formed. FIG. [Figure 15P] 13 is a schematic diagram of an anode conductive layer pattern in the light-transmitting display area shown in FIG. 12. FIG. [Figure 15Q] 13 is a schematic diagram of the transparent display area shown in FIG. 12 after an anode conductive layer pattern is formed. FIG. [Figure 16A] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a semiconductor pattern is formed therein. [Figure 16B] 14 is a schematic diagram of a first conductive layer pattern in the light-transmitting display area shown in FIG. 13. FIG. [Figure 16C] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a first conductive layer pattern is formed. FIG. [Figure 16D] 14 is a schematic diagram of a second conductive layer pattern in the light-transmitting display area shown in FIG. 13. FIG. [Figure 16E] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a second conductive layer pattern is formed. FIG. [Figure 16F] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a third insulating layer pattern is formed. FIG. [Figure 16G] 14 is a schematic diagram of a third conductive layer pattern in the light-transmitting display area shown in FIG. 13. FIG. [Figure 16H] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a third conductive layer pattern is formed. FIG. [Figure 16I] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a fourth insulating layer pattern is formed. FIG. [Figure 16J] 14 is a schematic diagram of a transparent conductive layer pattern in the light-transmitting display area shown in FIG. 13. FIG. [Figure 16K] 14 is a schematic diagram of the transparent display area according to FIG. 13 after a transparent conductive layer pattern is formed therein. [Figure 16L] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a first flat layer is formed. FIG. [Figure 16M] 14 is a schematic diagram of a fourth conductive layer pattern in the light-transmitting display area shown in FIG. 13. FIG. [Figure 16N] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a fourth conductive layer pattern is formed. FIG. [Figure 16O] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after a second flat layer pattern is formed. FIG. [Figure 16P] 14 is a schematic diagram of an anode conductive layer pattern in the light-transmitting display area shown in FIG. 13. FIG. [Figure 16Q] 14 is a schematic diagram of the transparent display area shown in FIG. 13 after an anode conductive layer pattern is formed. [Figure 17A] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a semiconductor pattern is formed therein. [Figure 17B] 15 is a schematic diagram of a first conductive layer pattern in the light-transmitting display area shown in FIG. 14. FIG. [Figure 17C] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a first conductive layer pattern is formed. FIG. [Figure 17D] 15 is a schematic diagram of a second conductive layer pattern in the light-transmitting display area shown in FIG. 14. FIG. [Figure 17E] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a second conductive layer pattern is formed. FIG. [Figure 17F] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a third insulating layer pattern is formed. FIG. [Figure 17G] 15 is a schematic diagram of a third conductive layer pattern in the light-transmitting display area shown in FIG. 14. FIG. [Figure 17H] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a third conductive layer pattern is formed. FIG. [Figure 17I] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a fourth insulating layer pattern is formed. FIG. [Figure 17J] 15 is a schematic diagram of a transparent conductive layer pattern in the light-transmitting display area shown in FIG. 14. FIG. [Figure 17K] 15 is a schematic diagram of the transparent display area according to FIG. 14 after a transparent conductive layer pattern is formed therein. [Figure 17L] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a first flat layer is formed. FIG. [Figure 17M] 15 is a schematic diagram of a fourth conductive layer pattern in the light-transmitting display area shown in FIG. 14. FIG. [Figure 17N] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a fourth conductive layer pattern is formed. FIG. [Figure 17O] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after a second flat layer pattern is formed. FIG. [Figure 17P] 15 is a schematic diagram of an anode conductive layer pattern in the light-transmitting display area shown in FIG. 14. FIG. [Figure 17Q] 15 is a schematic diagram of the transparent display area shown in FIG. 14 after an anode conductive layer pattern is formed. [Figure 18] 1 is a structural schematic diagram of a display device according to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a cross-sectional view taken along the line AA in FIG. 18. DETAILED DESCRIPTION OF THE INVENTION

[0038] The drawings are intended to facilitate a better understanding of the technical solution of the present disclosure, constitute a part of the specification, and are used to explain the technical solution of the present disclosure together with the embodiments of the present application, and are not intended to limit the technical solution of the present disclosure. The shape and size of one or more components in the drawings are intended only to provide a rough description of the present disclosure and do not reflect the true proportions.

[0039] The following describes in detail the embodiments of the present disclosure with reference to the drawings. The embodiments can be implemented in a variety of forms. Those skilled in the art can easily understand that the method and content can be converted into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to only those described in the following embodiments. Unless there is a conflict, the embodiments and features in the embodiments in the present disclosure can be arbitrarily combined.

[0040] In the drawings, for clarity, the size of one or more components, the thickness of layers, or the area thereof may be exaggerated. Therefore, one embodiment of the present disclosure is not necessarily limited to the dimensions, and the shape and size of one or more parts in the drawings do not reflect the true ratio. Furthermore, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, etc. shown in the drawings.

[0041] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of elements and are not intended to limit the quantity. In this disclosure, "plurality" means two or more.

[0042] For convenience, the present specification uses terms indicating orientations or positional relationships, such as "center," "top," "bottom," "front," "rear," "vertical," "horizontal," "upper," "bottom," "inner," and "outer," to describe the positional relationships of components with reference to the drawings. This is merely to facilitate and simplify the description of the specification, and does not indicate or imply that the devices or components referred to must have a specific orientation, be configured, or operate in a specific orientation, and is not intended to limit the present disclosure. The positional relationships of components may be changed as appropriate depending on the orientation of the components described. Therefore, the terms used in the description are not limited to those used in the description, and may be changed as appropriate depending on the situation.

[0043] In this specification, unless otherwise clearly specified or limited, the terms "attached," "coupled," and "connected" should be understood in a broad sense. For example, they may refer to a fixed connection, a detachable connection, or an integral connection, or may be a mechanical connection or connection. They may be a direct connection, an indirect connection via middleware, or internal communication between two elements. Those skilled in the art can understand the meaning of the above terms in this disclosure depending on the context.

[0044] In this specification, "electrically connected" includes cases where components are connected via an element having some kind of electrical function. The "element having some kind of electrical function" is not particularly limited as long as it allows transmission of an electrical signal between the connected components. Examples of the "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0045] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, a channel region refers to a region through which current mainly flows.

[0046] As used herein, the first pole may be the drain and the second pole may be the source, or the first pole may be the source and the second pole may be the drain. The functions of "source" and "drain" may be interchanged, such as when using transistors with reversed polarity or when the direction of current flow changes during circuit operation. Therefore, as used herein, "source" and "drain" may be interchangeable. The gate may also be referred to as the control pole.

[0047] In this specification, "parallel" refers to a state in which the angle between two lines is between -10° and 10°, inclusive, and also includes a state in which the angle is between -5° and 5°, inclusive. "Perpendicular" refers to a state in which the angle between two lines is between 80° and 100°, inclusive, and also includes a state in which the angle is between 85° and 95°, inclusive.

[0048] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the ratio of the luminous flux transmitted through a transparent or translucent body to the luminous flux incident thereon.

[0049] In this disclosure, the terms "about" and "approximately" do not strictly limit the scope of the invention, but rather refer to the scope of acceptable process or measurement error. In this disclosure, "almost the same" refers to the case where the difference in the numerical value is within 10%.

[0050] At least one embodiment of the present disclosure provides a display substrate, including a display area and a peripheral area at least partially surrounding the display area, the display area including a translucent display area and a normal display area located on at least one side of the translucent display area, the light transmittance of the translucent display area being greater than that of the normal display area, the display substrate including a base and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the base, the plurality of light-emitting elements including a plurality of first-type light-emitting elements located in the translucent display area, the plurality of pixel circuits including a plurality of first-type pixel circuits located in the translucent display area, at least one first-type pixel circuit among the plurality of first-type pixel circuits is electrically connected to at least two first-type light-emitting elements that emit light of the same color, the first-type pixel circuit is configured to drive the emission of the at least two first-type light-emitting elements, and there is an overlap between an orthogonal projection of the at least one first-type pixel circuit at the base and an orthogonal projection of the at least one first-type light-emitting element at the base.

[0051] The display substrate according to the embodiment of the present disclosure reduces the number of first-type pixel circuits in the translucent display area, and drives at least two first-type light-emitting elements emitting light of the same color with one first-type pixel circuit, thereby ensuring that the resolution (PPI) of the display area of ​​the display substrate is consistent, improving the light transmittance of the translucent display area, and reducing diffraction of light from the translucent display area during imaging. The display substrate according to the embodiment can be applied to a QHD (Quarter High Definition) display device, but the embodiment is not limited thereto.

[0052] In an exemplary embodiment, there is an overlap between the orthogonal projection at the base of at least one first-type pixel circuit and the orthogonal projection at the base of at least some of the first-type light-emitting elements of the at least two first-type light-emitting elements electrically connected to the at least one first-type pixel circuit.

[0053] In an exemplary embodiment, the display substrate may further include a plurality of first signal lines, and at least one first-type pixel circuit is electrically connected to the at least one first signal line, the plurality of first signal lines including at least one of a scan signal line, a reset signal line, an initial signal line, and a light-emitting signal line.

[0054] In an exemplary embodiment, the plurality of first signal lines includes a plurality of sub-signal lines, and adjacent sub-signal lines of the first signal lines are electrically connected via electrically connecting first type pixel circuits.

[0055] In an exemplary embodiment, the display substrate may further include a plurality of second signal lines, wherein at least one first-type pixel circuit is electrically connected to the at least one second signal line, the plurality of second signal lines including at least one of a data signal line and a first power supply line, and the plurality of data signal lines and the plurality of first power supply lines extend along a first direction.

[0056] In an exemplary embodiment, the data signal line and the first power supply line electrically connected by the first type pixel circuit are located between adjacent sub-signal lines of the first signal line, and the orthogonal projections of the data signal line and the first power supply line electrically connected by the first type pixel circuit at their bases overlap with the orthogonal projections of the first type pixel circuit at their bases.

[0057] In an exemplary embodiment, the orthogonal projections at the base of at least one of the scanning signal line, the reset signal line, the initial signal line, the light emitting signal line, the data signal line, and the first power supply line partially overlap with the orthogonal projections at the base of the first type of light emitting element.

[0058] In an exemplary embodiment, the plurality of first-type light-emitting elements includes at least a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light. An anode area of ​​at least one first light-emitting element of the plurality of first light-emitting elements is larger than an anode area of ​​at least one third light-emitting element of the plurality of third light-emitting elements, and an anode area of ​​at least one second light-emitting element of the plurality of second light-emitting elements is larger than an anode area of ​​at least one third light-emitting element. In some examples, the first color light may be red light, the second color light may be blue light, and the third color light may be green light.

[0059] The present embodiment will be described below with some examples.

[0060] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In an exemplary embodiment, as shown in FIG. 1, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a light-transmitting display area A1 and a normal display area A2 located on at least one side of the light-transmitting display area A1. In some examples, the light-transmitting display area A1 is the aforementioned light-transmitting display area, and the light-transmitting display area A1 may also be referred to as an under-display camera (UDC) area. The normal display area A2 may also be referred to as a normal display area. For example, the orthographic projection of hardware such as a photosensitive sensor (e.g., a camera or an infrared sensor) on the display substrate may be located within the light-transmitting display area A1 of the display substrate. In some examples, as shown in FIG. 1, the light-transmitting display area A1 may be circular, and the size of the orthographic projection of the photosensitive sensor on the display substrate may be equal to or smaller than the size of the light-transmitting display area A1. However, this embodiment is not limited thereto.

[0061] In some other examples, the light-transmitting display area may be rectangular, and the size of the orthogonal projection of the photosensitive sensor on the display substrate may be equal to or smaller than the size of the inscribed circle of the light-transmitting display area.

[0062] In an exemplary embodiment, as shown in FIG. 1 , the translucent display area A1 may be located in the center of the top edge of the display area AA. The normal display area A2 may surround the translucent display area A1. However, this embodiment is not limited to this. For example, the translucent display area A1 may be located in another position, such as the upper left corner or the upper right corner of the display area AA.

[0063] In an exemplary embodiment, as shown in FIG. 1, the display area AA may be rectangular, such as a rectangle with rounded corners. The translucent display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the translucent display area may be rectangular, pentagonal, hexagonal, or another shape.

[0064] In an exemplary embodiment, the display area AA includes at least a plurality of regularly arranged pixel units, a plurality of gate lines (e.g., including scan signal lines, reset signal lines, and light-emitting signal lines) extending along a first direction Y, a plurality of data signal lines extending along a second direction X, and a first power supply line. The first direction Y and the second direction X are in the same plane, and the first direction Y intersects with the second direction X, for example, the first direction Y is perpendicular to the second direction X.

[0065] In an exemplary embodiment, one pixel unit in the display area AA may include three subpixels, which may be red, green, and blue subpixels, respectively. However, this embodiment is not limited thereto. In some examples, one pixel unit may include four subpixels, which may be red, green, blue, and white subpixels, respectively.

[0066] In an exemplary embodiment, the shape of the subpixel may be rectangular, diamond, pentagonal, or hexagonal. When one pixel unit includes three subpixels, the three subpixels may be arranged in a horizontal parallel-array, vertical parallel-array, or square-shaped manner. When one pixel unit includes four subpixels, the four subpixels may be arranged in a horizontal parallel-array, vertical parallel-array, or square-shaped manner. However, this embodiment is not limited thereto.

[0067] In an exemplary embodiment, at least one subpixel includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the electrically connected light-emitting element. For example, the pixel circuit is configured to supply a drive current that drives the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C (three transistors and one capacitor) structure, an 8T1C (eight transistors and one capacitor) structure, a 7T1C (seven transistors and one capacitor) structure, or a 5T1C (five transistors and one capacitor) structure. In some examples, the light-emitting element may be an organic light-emitting diode (OLED), which emits red light, green light, blue light, white light, or the like under the driving of a corresponding pixel circuit. The emission color of the light-emitting element can be set as needed. The light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0068] 1, the display substrate includes a base and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the base. The plurality of light-emitting elements may include a plurality of first-type light-emitting elements L1 located in the transparent display area A1 and a plurality of second-type light-emitting elements L2 located in the normal display area A2, and the plurality of pixel circuits may include a plurality of first-type pixel circuits P1 located in the transparent display area A1 and a plurality of second-type pixel circuits P2 located in the normal display area A2.

[0069] In the exemplary embodiment, the translucent display area A1 includes a plurality of first-type light-emitting elements and a plurality of first-type pixel circuits. At least one first-type pixel circuit is electrically connected to at least two first-type light-emitting elements emitting light of the same color. That is, at least two subpixels of the same color in the translucent display area A1 share one first-type pixel circuit. The normal display area A2 includes a plurality of second-type light-emitting elements and a plurality of second-type pixel circuits. The plurality of second-type light-emitting elements and the plurality of second-type pixel circuits are electrically connected in a one-to-one correspondence. The display substrate of this exemplary embodiment employs a design in which one first-type pixel circuit drives at least two first-type light-emitting elements in the translucent display area A1. This ensures consistent resolution across the display areas of the display substrate while improving the light transmittance of the translucent display area and reducing diffraction during imaging. However, this embodiment is not limited to this.

[0070] FIG. 2 is a schematic diagram 1 of an arrangement of first-type light-emitting elements in a light-transmitting display area according to at least one embodiment of the present disclosure, and FIG. 3 is a schematic diagram 2 of an arrangement of first-type light-emitting elements in a light-transmitting display area according to at least one embodiment of the present disclosure. In an exemplary embodiment, as shown in FIGS. 2 and 3 , the plurality of first-type light-emitting elements in the light-transmitting display area A1 may include a plurality of first light-emitting elements 11 that emit a first color light, a plurality of second light-emitting elements 12 that emit a second color light, and a plurality of third light-emitting elements 13 that emit a third color light. For example, the first color light may be red light, the second color light may be blue light, and the third color light may be green light. That is, the first light-emitting elements 11 may be red light-emitting elements, the second light-emitting elements 12 may be blue light-emitting elements, and the third light-emitting elements 13 may be green light-emitting elements. However, this embodiment is not limited thereto.

[0071] 2, the plurality of first-type light-emitting elements in the translucent display area A1 may be arranged in a pentile structure, where the plurality of third light-emitting elements 13 are arranged at regular intervals in the i-th row, the second light-emitting elements 12 and the first light-emitting elements 11 are alternately arranged in adjacent rows of the i-th row, the first light-emitting elements 11 and the second light-emitting elements 12 are alternately arranged in the j-th column, the plurality of third light-emitting elements 13 are arranged at regular intervals in adjacent columns of the j-th column, the first light-emitting elements 11 and the third light-emitting elements 13 are alternately arranged along a third direction F1, and the second light-emitting elements 12 and the third light-emitting elements 13 are alternately arranged along a fourth direction F2, and the third direction F1 and the fourth direction F4 intersect with the first direction Y and the second direction X, respectively, where the first direction Y is the column direction and the second direction X is the row direction. For example, "a plurality of third light-emitting elements 13 are arranged at regular intervals in the i-th row, and the second light-emitting elements 12 and the first light-emitting elements 11 are alternately arranged in adjacent rows of the i-th row" means that a plurality of third light-emitting elements 13 are arranged at regular intervals in the i-th row, the second light-emitting elements 12 and the first light-emitting elements 11 are alternately arranged in the i+1-th row adjacent to the i-th row, a plurality of third light-emitting elements 13 are arranged at regular intervals in the i+2-th row adjacent to the i+1-th row, and the first light-emitting elements 11 and the second light-emitting elements 12 are alternately arranged in the i+3-th row adjacent to the i+2-th row. A plurality of rows of the first type light-emitting elements can be repeatedly arranged according to the above rules. For example, "the first light-emitting elements 11 and the second light-emitting elements 12 are alternately arranged in the jth column, and a plurality of third light-emitting elements 13 are arranged in adjacent columns of the jth column at regular intervals" refers to "the first light-emitting elements 11 and the second light-emitting elements 12 are alternately arranged in the jth column, a plurality of third light-emitting elements 13 are arranged in the j+1th column adjacent to the jth column at regular intervals," "the first light-emitting elements 11 and the second light-emitting elements 12 are alternately arranged in the j+2th column adjacent to the j+1th column, and a plurality of third light-emitting elements 13 are arranged in the j+3th column at regular intervals." Multiple columns of first-type light-emitting elements can be repeatedly arranged according to the above rules. In this example, the sizes of the first light-emitting elements 11 and the second light-emitting elements 12 may both be larger than the size of the third light-emitting elements 13. Both i and j are integers.

[0072] 2 , the light emitting area 110 of the first light emitting element 11, the light emitting area 120 of the second light emitting element 12, and the light emitting area 130 of the third light emitting element 13 may all be circular or elliptical. The light emitting area 110 of the first light emitting element 11 may be larger than the light emitting area 130 of the third light emitting element 13, and the light emitting area 120 of the second light emitting element 12 may be larger than the light emitting area 130 of the third light emitting element 13. In this example, the light emitting area of ​​the light emitting element may be a portion of the light emitting element located in a pixel opening of the pixel definition layer.

[0073] In an exemplary embodiment, the light-emitting area of ​​the first-type light-emitting element in the light-transmitting display region A1 may be smaller than the light-emitting area of ​​the second-type light-emitting element that emits light of the same color in the normal display region A2. For example, the area of ​​the light-emitting area of ​​the first-type light-emitting element may be 40% to 60%, e.g., approximately 50%, of the area of ​​the light-emitting area of ​​the second-type light-emitting element that emits light of the same color. In this example, by reducing the aperture ratio of the light-transmitting display region A1, the light-transmitting area of ​​the light-transmitting display region A1 can be increased, and the light transmittance of the light-transmitting display region A1 can be improved.

[0074] 3, the plurality of first-type light-emitting elements in the transparent display area A1 may be arranged in a square-shaped manner. The plurality of second light-emitting elements 12 are arranged in the jth column, the first light-emitting elements 11 and the third light-emitting elements 13 are alternately arranged in adjacent columns of the jth column, and the plurality of second light-emitting elements 12 are arranged in the ith row, and the first light-emitting elements 11 and the third light-emitting elements 13 are arranged between adjacent second light-emitting elements 12 in the same row. Exemplarily, "the plurality of second light-emitting elements 12 are arranged in the jth column and the first light-emitting elements 11 and the third light-emitting elements 13 are alternately arranged in adjacent columns of the jth column" refers to the plurality of second light-emitting elements 12 being arranged at regular intervals in the jth column, the first light-emitting elements 11 and the third light-emitting elements 13 being alternately arranged in the j+1th column adjacent to the jth column, the plurality of second light-emitting elements 12 being arranged at regular intervals in the j+2th column adjacent to the j+1th column, and the first light-emitting elements 11 and the second light-emitting elements 12 being alternately arranged in the j+3th column adjacent to the j+2th column. According to the above rules, multiple rows of the first type light emitting elements can be repeatedly arranged.

[0075] Fig. 4 is a schematic diagram 1 showing the arrangement of first-type pixel circuits and first-type light-emitting elements in a translucent display area according to an exemplary embodiment, Fig. 5 is a schematic diagram 2 showing the arrangement of first-type pixel circuits and first-type light-emitting elements in a translucent display area according to an exemplary embodiment, Fig. 6 is a schematic diagram 3 showing the arrangement of first-type pixel circuits and first-type light-emitting elements in a translucent display area according to an exemplary embodiment, Fig. 7 is a schematic diagram 4 showing the arrangement of first-type pixel circuits and first-type light-emitting elements in a translucent display area according to an exemplary embodiment, Fig. 8 is a schematic diagram 5 showing the arrangement of first-type pixel circuits and first-type light-emitting elements in a translucent display area according to an exemplary embodiment, and Fig. 9 is a schematic diagram 6 showing the arrangement of first-type pixel circuits and first-type light-emitting elements in a translucent display area according to an exemplary embodiment. In Figs. 4 to 9, the positions of the first-type pixel circuits are indicated by rectangles. 4 and 5 illustrate an example in which a plurality of first-type light-emitting elements in the translucent display area A1 can be arranged in a pentile structure, and FIGS. 6 to 9 illustrate an example in which a plurality of first-type light-emitting elements in the translucent display area A1 can be arranged in a square shape. All of FIGS. 4 to 9 illustrate an example in which one first-type pixel circuit connects two first-type light-emitting elements.

[0076] In an exemplary embodiment, as shown in FIGS. 4 to 9, the area of ​​the anode 111 of the first light-emitting element (e.g., the first light-emitting elements 11a and 11b) is larger than the area of ​​the anode 131 of the third light-emitting element (e.g., the third light-emitting elements 13a and 13b), and the area of ​​the anode 121 of the second light-emitting element (e.g., the second light-emitting elements 12a and 12b) is larger than the area of ​​the anode 131 of the third light-emitting element (e.g., the third light-emitting elements 13a and 13b).

[0077] In an exemplary embodiment, the plurality of first-type pixel circuits include at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit, and at least one fourth pixel circuit, wherein the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, the third pixel circuit is electrically connected to two third light-emitting elements, and the fourth pixel circuit is electrically connected to two third light-emitting elements, and the third light-emitting elements electrically connected to the third pixel circuit and the fourth pixel circuit are different.

[0078] In an exemplary embodiment, as shown in FIG. 4 , the plurality of first-type pixel circuits in the translucent display area may include at least a first pixel circuit 15a, a second pixel circuit 15b, a third pixel circuit 15c, and a fourth pixel circuit 15d. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b that emit a first color light and is configured to drive the light emission of the two first light-emitting elements 11a and 11b. There is an overlap between the orthogonal projection of the base of the first pixel circuit 15a and the orthogonal projection of the base of the anode 111 of the first light-emitting element 11a, but there is no overlap between the orthogonal projection of the base of the anode of the first light-emitting element 11b. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b that emit a second color light and is configured to drive the light emission of the two second light-emitting elements 12a and 12b. There is no overlap between the orthogonal projection of the second pixel circuit 15b at the base and the orthogonal projection of the second light-emitting elements 12a and 12b at the bases of the anodes of the second light-emitting elements 12a and 12b, but there is overlap with the orthogonal projection of the first light-emitting element 11b located between the second light-emitting elements 12a and 12b at the base. The third pixel circuit 15c is electrically connected to the two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the emission of the two third light-emitting elements 13a and 13b. The orthogonal projection of the base of the third pixel circuit 15c and the orthogonal projection of the base of the anode of the second LIGHT EMITTING element 12a overlap, but the orthogonal projections of the bases of the anodes of the two third LIGHT EMITTING elements 13a and 13b do not overlap. The second LIGHT EMITTING element 12a overlapping with the third pixel circuit 15c is located in a row above the row in which the two third LIGHT EMITTING elements 13a and 13b are located and in the middle column in which the two third LIGHT EMITTING elements 13a and 13b are located. The fourth pixel circuit 15d is electrically connected to the two third LIGHT EMITTING elements 13c and 13d that emit third color light and is configured to drive the emission of the two third LIGHT EMITTING elements 13c and 13d. There is an overlapping portion between the orthogonal projection at the base of the fourth pixel circuit 15d and the orthogonal projection at the base of the anode of the second light-emitting element 12b, but there is no overlapping portion between the orthogonal projections at the bases of the anodes of the two third light-emitting elements 13c and 13d. The second light-emitting element 12b that overlaps with the fourth pixel circuit 15d is located one row above the row in which the two third light-emitting elements 13c and 13d are located, and is located in the middle column of the column in which the third light-emitting elements 13c and 13d are located.

[0079] 4, the first-type pixel circuit is located below the anode of the first or second light-emitting element having a relatively large anode area, and does not overlap with the anode of the third light-emitting element having a relatively small anode area. In this example, by arranging the first-type pixel circuit below the first-type light-emitting element having a relatively large anode area and not arranging the first-type pixel circuit below the first-type light-emitting element having a relatively small anode area, the light transmittance of the translucent display region can be improved.

[0080] 4 , the two first L-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are in the second direction X (i.e., the two first L-emitting elements 11a and 11b are located in the same row), the two second L-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are in the second direction X (i.e., the two second L-emitting elements 12a and 12b are located in the same row), the two third L-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are in the second direction X (i.e., the two third L-emitting elements 13a and 13b are located in the same row), and the two third L-emitting elements 13c and 13d electrically connected to the fourth pixel circuit 15d are in the second direction X (i.e., the two third L-emitting elements 13c and 13d are located in the same row).

[0081] 5, the plurality of first-type pixel circuits in the translucent display area may include at least a first pixel circuit 15a, a second pixel circuit 15b, a third pixel circuit 15c, and a fourth pixel circuit 15d. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b that emit a first color light and is configured to drive the light emission of the two first light-emitting elements 11a and 11b. There is an overlap between the orthogonal projection of the base of the first pixel circuit 15a and the orthogonal projection of the base of the anode 111 of the first light-emitting element 11a, but there is no overlap between the orthogonal projection of the base of the anode of the first light-emitting element 11b. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b that emit a second color light and is configured to drive the light emission of the two second light-emitting elements 12a and 12b. There is an overlapping portion between the orthogonal projection at the base of the second pixel circuit 15b and the orthogonal projection at the base of the anode of the second light-emitting element 12a, but there is no overlapping portion between the orthogonal projection at the base of the anode of the second light-emitting element 12b. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light and is configured to drive the emission of the two third light-emitting elements 13a and 13b. There is an overlapping portion between the orthogonal projection at the base of the third pixel circuit 15c and the orthogonal projection at the base of the anode of the third light-emitting element 13a, but there is no overlapping portion between the orthogonal projection at the base of the anode of the third light-emitting element 13b. The fourth pixel circuit 15d is electrically connected to two third light-emitting elements 13c and 13d that emit third color light and is configured to drive the emission of the two third light-emitting elements 13c and 13d. There is an overlapping portion between the orthogonal projection on the base of the fourth pixel circuit 15d and the orthogonal projection on the base of the anode of the third light-emitting element 13c, but there is no overlapping portion between the orthogonal projection on the base of the anode of the third light-emitting element 13d.

[0082] 5, the two first light-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are aligned in the third direction F1. The two second light-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are aligned in the third direction F1. The two third light-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are aligned in the first direction Y (i.e., the two third light-emitting elements 13a and 13b are located in the same column). The two third light-emitting elements 13c and 13d electrically connected to the fourth pixel circuit 15d are aligned in the first direction Y (i.e., the two third light-emitting elements 13c and 13d are located in the same column).

[0083] In an exemplary embodiment, the plurality of first-type pixel circuits may include at least one first pixel circuit, at least one second pixel circuit, and at least one third pixel circuit, where the first pixel circuit is electrically connected to two first light-emitting elements, the second pixel circuit is electrically connected to two second light-emitting elements, and the third pixel circuit is electrically connected to two third light-emitting elements.

[0084] In an exemplary embodiment, as shown in FIG. 6 , the plurality of first-type pixel circuits in the translucent display area may include at least a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b that emit a first color light and is configured to drive the light emission of the two first light-emitting elements 11a and 11b. There is an overlap between the orthogonal projection of the base of the first pixel circuit 15a and the orthogonal projection of the base of the anode 111 of the first light-emitting element 11a, but there is no overlap between the orthogonal projection of the base of the anode of the first light-emitting element 11b. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b that emit a second color light and is configured to drive the light emission of the two second light-emitting elements 12a and 12b. There is an overlapping portion between the orthogonal projection at the base of the second pixel circuit 15b and the orthogonal projection at the base of the anode of the second light-emitting element 12a, but there is no overlapping portion between the orthogonal projection at the base of the second light-emitting element 12b. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the emission of the two third light-emitting elements 13a and 13b. There is an overlapping portion between the orthogonal projection at the base of the third pixel circuit 15c and the orthogonal projection at the base of the anode of the third light-emitting element 13a, but there is no overlapping portion between the orthogonal projection at the base of the anode of the third light-emitting element 13b.

[0085] 7, the plurality of first-type pixel circuits in the translucent display area may include at least a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b that emit a first color light and is configured to drive the light emission of the two first light-emitting elements 11a and 11b. There is an overlap between the orthogonal projection of the base of the first pixel circuit 15a and the orthogonal projection of the base of the anode 111 of the first light-emitting element 11b, but there is no overlap between the orthogonal projection of the base of the anode of the first light-emitting element 11a. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b that emit a second color light and is configured to drive the light emission of the two second light-emitting elements 12a and 12b. There is an overlapping portion between the orthogonal projection at the base of the second pixel circuit 15b and the orthogonal projection at the base of the anode of the second light-emitting element 12a, but there is no overlapping portion between the orthogonal projection at the base of the second light-emitting element 12b. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the emission of the two third light-emitting elements 13a and 13b. There is an overlapping portion between the orthogonal projection at the base of the third pixel circuit 15c and the orthogonal projection at the base of the anode of the third light-emitting element 13a, but there is no overlapping portion between the orthogonal projection at the base of the anode of the third light-emitting element 13b.

[0086] 8 , the plurality of first-type pixel circuits in the translucent display area may include at least a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b that emit a first color light and is configured to drive the light emission of the two first light-emitting elements 11a and 11b. There is an overlap between the orthogonal projection of the base of the first pixel circuit 15a and the orthogonal projection of the base of the anode 111 of the first light-emitting element 11a, but there is no overlap between the orthogonal projection of the base of the anode of the first light-emitting element 11b. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b that emit a second color light and is configured to drive the light emission of the two second light-emitting elements 12a and 12b. There is an overlapping portion between the orthogonal projection at the base of the second pixel circuit 15b and the orthogonal projection at the base of the anode of the second light-emitting element 12a, but there is no overlapping portion between the orthogonal projection at the base of the second light-emitting element 12b. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light and is configured to drive the emission of the two third light-emitting elements 13a and 13b. There is no overlapping portion between the orthogonal projection at the base of the third pixel circuit 15c and the orthogonal projection at the base of the anode of the two third light-emitting elements 13a and 13b, but there is an overlapping portion between the orthogonal projection at the base of the anode of the second light-emitting element 12b located between the two third light-emitting elements 13a and 13b.

[0087] 9 , the plurality of first-type pixel circuits in the translucent display area may include at least a first pixel circuit 15a, a second pixel circuit 15b, and a third pixel circuit 15c. The first pixel circuit 15a is electrically connected to two first light-emitting elements 11a and 11b that emit a first color light and is configured to drive the light emission of the two first light-emitting elements 11a and 11b. There is no overlap between the orthogonal projection of the base of the first pixel circuit 15a and the orthogonal projection of the base of the anode 111 of the first light-emitting elements 11a and 11b, but there is an overlap between the orthogonal projection of the base of the anode of the second light-emitting element 12b located between the first light-emitting elements 11a and 11b. The second pixel circuit 15b is electrically connected to two second light-emitting elements 12a and 12b that emit a second color light and is configured to drive the light emission of the two second light-emitting elements 12a and 12b. There is an overlapping portion between the orthogonal projection at the base of the second pixel circuit 15b and the orthogonal projection at the base of the anode of the second light-emitting element 12a, but there is no overlapping portion between the orthogonal projection at the base of the second light-emitting element 12b. The third pixel circuit 15c is electrically connected to two third light-emitting elements 13a and 13b that emit third color light, and is configured to drive the emission of the two third light-emitting elements 13a and 13b. There is an overlapping portion between the orthogonal projection at the base of the third pixel circuit 15c and the orthogonal projection at the base of the anode of the third light-emitting element 13a, but there is no overlapping portion between the orthogonal projection at the base of the anode of the third light-emitting element 13b.

[0088] In an exemplary embodiment, as shown in FIGS. 6 to 9 , the two first light-emitting elements 11a and 11b electrically connected to the first pixel circuit 15a are in the second direction X (i.e., the two first light-emitting elements 11a and 11b are located in the same row), the two second light-emitting elements 12a and 12b electrically connected to the second pixel circuit 15b are in the second direction X (i.e., the two second light-emitting elements 12a and 12b are located in the same row), and the two third light-emitting elements 13a and 13b electrically connected to the third pixel circuit 15c are in the second direction X (i.e., the two third light-emitting elements 13a and 13b are located in the same row).

[0089] In an exemplary embodiment, at least two of the first light-emitting element overlapping the first pixel circuit, the second light-emitting element overlapping the second pixel circuit, and the third light-emitting element overlapping the third pixel circuit are adjacent to each other. Fig. 7 illustrates an example in which the first light-emitting element overlapping the first pixel circuit, the second light-emitting element overlapping the second pixel circuit, and the third light-emitting element overlapping the third pixel circuit are located in the same light-emitting unit, while Figs. 6, 8, and 9 illustrate an example in which the first light-emitting element overlapping the first pixel circuit, the second light-emitting element overlapping the second pixel circuit, and the third light-emitting element overlapping the third pixel circuit are located in the same light-emitting unit, and are located in two light-emitting units, and the light-emitting unit includes the first light-emitting element, the second light-emitting element, and the third light-emitting element.

[0090] In an exemplary embodiment, in the translucent display area, at least two first-type light-emitting elements that emit light of the same color are driven by one first-type pixel circuit, and the first-type pixel circuit is placed under an anode having the first light-emitting element, the second light-emitting element, and the third light-emitting element, thereby ensuring the resolution of the display substrate while improving the light transmittance.

[0091] 10 is an equivalent circuit diagram of a first-type pixel circuit. In an exemplary embodiment, as shown in FIG. 10, the first-type pixel circuit of this exemplary embodiment may have an 8T1C structure including a first transistor T1 to a seventh transistor T7 and a capacitor C. The first-type light-emitting elements EL1 and EL2 may emit light of the same color and may each include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. In this example, the third transistor T3 is a driving transistor.

[0092] 10 , the first-type pixel circuits are electrically connected to a scan signal line Gate, a reset signal line RST, an initial signal line INIT, an emission signal line EM, a data signal line Data, a first power supply line VDD, and a second power supply line VSS. Exemplarily, the first power supply line VDD is configured to supply a constant first voltage signal to the first-type pixel circuits, and the second power supply line VSS is configured to supply a constant second voltage signal to the first-type pixel circuits, the voltage value of the first voltage signal being greater than the voltage value of the second voltage signal. The scan signal line Gate is configured to supply a scan signal to the first-type pixel circuits, the data signal line Data is configured to supply a data signal to the first-type pixel circuits, the emission signal line EM is configured to supply an emission control signal to the first-type pixel circuits, and the reset signal line RST is configured to supply a reset control signal to the first-type pixel circuits. In some examples, for the first-type pixel circuits in the nth row, the reset signal line RST may be connected to the scan signal line Gate of the first-type pixel circuits in the (n-1)th row. This allows the number of signal lines on the display substrate to be reduced, and the frame of the display substrate to be narrowed.

[0093] 10, in an exemplary embodiment, the control pole of the first transistor T1 is electrically connected to the reset signal line RST, the first pole of the first transistor T1 is electrically connected to the initial signal line INIT, and the second pole of the first transistor T1 is electrically connected to the first node N1. The control pole of the second transistor T2 is electrically connected to the scan signal line Gate, the first pole of the second transistor T2 is electrically connected to the first node N1, and the second pole of the second transistor T2 is electrically connected to the third node N3. The control pole of the third transistor T3 is electrically connected to the first node N1, the first pole of the third transistor T3 is electrically connected to the second node N2, and the second pole of the third transistor T3 is electrically connected to the third node N3. The control pole of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first pole of the fourth transistor T4 is electrically connected to the data signal line Data, and the second pole of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the scanning signal line Gate, the first electrode of the seventh transistor T7 is electrically connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the first power supply line VDD.

[0094] In this example, the first node N1 is a connection point between the capacitor C, the first transistor T1, and the third transistor T3; the second node N2 is a connection point between the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is a connection point between the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is a connection point between the sixth transistor T6, the seventh transistor T7, and the two first-type light-emitting elements EL1 and EL2.

[0095] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 of the first type pixel circuit may all be P-type transistors or all be N-type transistors.

[0096] In an exemplary embodiment, the first-type transistors (e.g., the first transistor T1 to the seventh transistor T7) of the first-type pixel circuit may be low-temperature polysilicon thin-film transistors or oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistors uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistors uses an oxide semiconductor (oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, the advantages of both can be utilized, enabling low-frequency driving, reducing power consumption, and improving display quality. However, this embodiment is not limited thereto. For example, the multiple transistors of the first-type pixel circuit may all be low-temperature polysilicon thin-film transistors or all be oxide thin-film transistors.

[0097] Figure 11 is an operation timing chart of the first type pixel circuit according to Figure 10. Next, with reference to Figure 11, an operation process of the first type pixel circuit shown in Figure 10 will be described. The first transistor T1 to the seventh transistor T7 of the first type pixel circuit are P-type transistors.

[0098] In an exemplary embodiment, as shown in FIGS. 10 and 11, in one frame display period, the operation process of the first type pixel circuit may include a first stage S1, a second stage S2, and a third stage S3.

[0099] The first stage S1 is called the reset stage. The signal supplied from the reset signal line RST is a low-level signal, turning on the first transistor T1. The initial signal supplied from the initial signal line INIT is supplied to the first node N1, which initializes the first node N1 and clears the original data voltage of the capacitor C. The signal supplied from the scanning signal line Gate is a high-level signal, and the light-emitting control signal EM supplied from the light-emitting signal line EM is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6. In this stage, the first-type light-emitting elements EL1 and EL2 do not emit light.

[0100] The second stage S2 is called a data writing stage or threshold compensation stage. The signal supplied from the scanning signal line Gate is a low-level signal, and data is output from the data signal line Data. In this stage, the signal at the first node N1 is a low-level signal, so the third transistor T3 is turned on. A signal supplied from the scanning signal line Gate turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. When the second transistor T2 and the fourth transistor T4 are turned on, the data voltage Vdata output by the data signal line Data is supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, and the difference between the data voltage Vdata output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C. The voltage of the first electrode of the capacitor C (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. When the seventh transistor T7 is turned on, the initialization signal Vinit provided from the initialization signal line INIT is provided to the fourth node N4, which initializes (resets) the anodes of the two first-type light-emitting elements EL1 and EL2 and clears the pre-stored voltages therein to complete the initialization, ensuring that the first-type light-emitting elements EL1 and EL2 do not emit light. The signal provided from the reset signal line RST is a high-level signal, which turns off the first transistor T1. The signal provided from the emission signal line EM is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0101] The third stage S3 is called the light-emitting stage. The signal supplied from the light-emitting signal line EM is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6. The signals supplied from the scanning signal line Gate and the reset signal line RST are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the first transistor T1. The first voltage signal output from the first power supply line VDD supplies a driving voltage to the anodes of the first-type light-emitting elements EL1 and EL2 via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the two first-type light-emitting elements EL1 and EL2 to emit light.

[0102] In the driving process of the first type pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control pole and first pole. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is given by the following formula:

[0103] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0104] where I is the driving current flowing through the third transistor T3, i.e., the driving current driving the first type light-emitting element, K is a constant, Vgs is the voltage difference between the control pole and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, and VDD is the first voltage signal output by the first power supply line PL1.

[0105] From the above equation, it can be seen that the current flowing through the first-type light emitting element is independent of the threshold voltage of the third transistor T3, so the first-type pixel circuit of this embodiment can well compensate for the threshold voltage of the third transistor T3.

[0106] Fig. 12 is a local plan view 1 of a translucent display area according to an exemplary embodiment, Fig. 13 is a local plan view 2 of a translucent display area according to an exemplary embodiment, and Fig. 14 is a local plan view 3 of a translucent display area according to an exemplary embodiment. Fig. 12 illustrates the translucent display area according to Fig. 4 as an example, Fig. 13 illustrates the translucent display area according to Fig. 5 as an example, and Fig. 14 illustrates the translucent display area according to Fig. 6 as an example.

[0107] In an exemplary embodiment, the first type pixel circuit includes a plurality of transistors and at least one capacitor, and in a direction perpendicular to the display substrate, the light-transmitting display region includes at least a semiconductor layer disposed on a base, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer.

[0108] the semiconductor layer includes at least active layers of a plurality of transistors of the first type pixel circuit; the first conductive layer includes at least control poles of a plurality of transistors of the first type pixel circuits and first plates of capacitors; the second conductive layer includes at least a second plate of a capacitor of the first type pixel circuit; the third conductive layer includes at least first and second electrodes of the plurality of transistors of the first type pixel circuit and a plurality of connecting electrodes; the transparent conductive layer includes at least a plurality of first signal lines, a plurality of second signal lines, and a plurality of anode connecting lines, at least one anode connecting line among the plurality of anode connecting lines is electrically connected to at least one first-type pixel circuit and to anodes of at least two first-type light-emitting elements that emit light of the same color, and the at least one first-type pixel circuit is electrically connected to at least one first signal line and at least one second signal line; The fourth conductive layer includes at least a plurality of signal connection lines.

[0109] In an exemplary embodiment, as shown in Figures 12 to 14, at least one first signal line includes a plurality of sub-signal lines, and adjacent sub-signal lines of the first signal line are electrically connected via a first-type pixel circuit. Exemplarily, the plurality of first signal lines include at least one of a scan signal line, a reset signal line, an initial signal line, and an emission signal line. Figures 12 to 14 illustrate an example in which the scan signal line includes two sub-signal lines Gate_1 and Gate_2, the reset signal line includes two sub-signal lines RST_1 and RST_2, the initial signal line includes two sub-signal lines INIT_1 and INIT_2, and the emission signal line includes two sub-signal lines EM_1 and EM_2.

[0110] 12 to 14 , the plurality of second signal lines includes a plurality of data signal lines Data and a plurality of first power supply lines VDD, and at least a portion of the data signal lines Data and the first power supply lines VDD extend along the first direction Y. The data signal lines Data and the first power supply lines VDD electrically connected to the first type pixel circuits are located between adjacent sub-signal lines of the first type pixel circuits, and the orthogonal projections at the bases of the first type pixel circuits overlap with the orthogonal projections at the bases of the first type pixel circuits.

[0111] In an exemplary embodiment, as shown in FIG. 12, the sub-signal lines of the first signal line are polygonal lines, and at least a portion of the sub-signal lines of the first signal line extends along the second direction X.

[0112] 12 , the anode connecting lines may include a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, and a fourth anode connecting line AL4. The first anode connecting line AL1, the second anode connecting line AL2, the third anode connecting line AL3, and the fourth anode connecting line AL4 may be polygonal lines. The first anode connecting line AL1 may be electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line AL1 may extend along the second direction X. The second anode connecting line AL2 is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line AL2 extends along the second direction X. The third anode connecting line AL3 is electrically connected to the third pixel circuit and the third light-emitting element, at least a portion of the third anode connecting line AL3 extends along the second direction X, and the third anode connecting line AL3 is located between the data signal line Data and the first power supply line VDD to which the third pixel circuit is electrically connected. The fourth anode connecting line AL4 is electrically connected to the fourth pixel circuit and the third light-emitting element, at least a portion of the fourth anode connecting line AL4 extends along the second direction X, and the fourth anode connecting line AL4 is located between the data signal line Data and the first power supply line VDD to which the fourth pixel circuit is electrically connected.

[0113] In an exemplary embodiment, as shown in FIG. 12 , first power supply lines electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced-apart first power supply lines located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.

[0114] In an exemplary embodiment, as shown in FIG. 12, at least two adjacent first-type pixel circuits located in the same column are electrically connected to data signal lines Data spaced apart, and the spaced apart data signal lines Data located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.

[0115] In an exemplary embodiment, as shown in FIG. 13, the sub-signal lines of the first signal line are polygonal lines, and at least a portion of the sub-signal lines of the first signal line extends along the first direction Y.

[0116] 13 , the anode connecting lines include a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, and a fourth anode connecting line AL4. The first anode connecting line AL1, the second anode connecting line AL2, the third anode connecting line AL3, and the fourth anode connecting line AL4 may be polygonal lines. The first anode connecting line AL1 is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line AL1 extends along the first direction Y. The second anode connecting line AL2 is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line AL2 extends along the first direction Y. The third anode connecting line AL3 is electrically connected to the third pixel circuit and the third light-emitting element, at least a portion of which extends along the first direction Y, and is located away from the data signal line Data of the first power supply line VDD to which the third pixel circuit is electrically connected. The fourth anode connecting line AL4 is electrically connected to the fourth pixel circuit and the third light-emitting element, at least a portion of which extends along the first direction Y, and is located away from the data signal line Data of the first power supply line VDD to which the fourth pixel circuit is electrically connected.

[0117] In the exemplary embodiment, as shown in FIG. 13, the data signal line Data to which the first type pixel circuits located in the same column are electrically connected is the same signal line.

[0118] In an exemplary embodiment, as shown in FIG. 13 , the first power supply lines VDD electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced-apart first power supply lines VDD located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.

[0119] 13 , the transparent conductive layer may further include a power supply connecting line VCL, at least a portion of which extends along the second direction X. The power supply connecting line VCL is electrically connected to a first power supply line VDD that electrically connects two adjacent pixel circuits located in the same row, and the first power supply line VDD and the power supply connecting line VCL are electrically connected via a connection electrode located in the third conductive layer.

[0120] 13 , for the same first-type pixel circuit, the first power supply line VDD may include a power supply main portion VDDM extending along the first direction Y and a power supply connection portion VDDS at least a portion of which extends along the second direction X, where the power supply connection portion VDDS is located on the side of the power supply main portion VDDM away from the data signal line. The power supply connection line VDDS is electrically connected to the power supply connection portion of one first-type pixel circuit and the power supply main portion of the other first-type pixel circuit among adjacent first-type pixel circuits located in the same row.

[0121] In an exemplary embodiment, as shown in FIG. 14, the sub-signal lines of the first signal line may be polygonal lines, and at least a portion of the sub-signal lines of the first signal line may extend along the second direction X.

[0122] 14 , the anode connecting lines may include a first anode connecting line AL1, a second anode connecting line AL2, and a third anode connecting line AL3, and the first anode connecting line AL1, the second anode connecting line AL2, and the third anode connecting line AL3 may be polygonal lines. The first anode connecting line AL1 is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line AL1 extends along the second direction X. The second anode connecting line AL2 is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line AL2 extends along the second direction X. The third anode connecting line AL3 is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line AL3 extends along the second direction X.

[0123] In an exemplary embodiment, as shown in FIG. 14, the data signal line Data to which pixel circuits located in the same column are electrically connected is the same signal line.

[0124] In an exemplary embodiment, as shown in FIG. 14 , the first power supply lines VDD electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced-apart first power supply lines VDD located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer.

[0125] The structure of a display substrate will be described below using an example of a manufacturing process for a display substrate. In this embodiment, the "patterning process" refers to processes such as photoresist application, mask exposure, development, etching, and photoresist stripping for metal, inorganic, and transparent conductive materials, and organic material application, mask exposure, and development for organic materials. Deposition may be performed by one or more of sputtering, evaporation, and chemical vapor deposition; application may be performed by one or more of spraying, spin coating, and inkjet printing; and etching may be performed by one or more of dry etching and wet etching; these processes are not limited to these methods. A "thin film" refers to a thin film layer fabricated using deposition, coating, or other processes based on a certain material. If the "thin film" does not require a patterning process in the overall manufacturing process, it can also be referred to as a "layer." If the "thin film" requires a patterning process in the overall manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern."

[0126] In an exemplary embodiment, the manufacturing process of the translucent display area according to FIG. 12 may include the following operations.

[0127] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in FIG. 15A, forming a semiconductor layer pattern may include sequentially depositing a semiconductor thin film on a base and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. FIG. 15A is a schematic diagram of the transparent display area after forming a semiconductor pattern according to FIG. 12.

[0128] 15A, the semiconductor layer pattern includes an active layer T11 of the first transistor to an active layer T71 of the seventh transistor, which are connected to each other in an integrated structure.

[0129] In an exemplary embodiment, as shown in FIG. 15A , in the second direction X, the active layer T21 of the second transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may be located on the same side of the active layer T31 of the third transistor in the subpixel; the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in the subpixel; and the active layer T21 of the second transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in the subpixel. In the first direction Y, the active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T41 of the fourth transistor, and the active layer T71 of the seventh transistor may be located on the same side of the active layer T31 of the third transistor in the subpixel, and the active layer T51 of the fifth transistor and the active layer T61 of the sixth transistor may be located on the other side of the active layer T31 of the third transistor in the subpixel.

[0130] In an exemplary embodiment, as shown in FIG. 15A, the active layer T11 of the first transistor may have an “n” shape, the active layer T21 of the second transistor may have an “L” shape, the active layer T31 of the third transistor may have an “Ω” shape, and the active layer T41 of the fourth transistor, the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may have an “I” shape.

[0131] (2) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 15B and 15C, forming the first conductive layer pattern may include sequentially depositing a first insulating thin film and a first conductive thin film on the patterned base, and patterning the first conductive thin film through a patterning process to form a first insulating layer covering the semiconductor layer pattern and a first conductive layer pattern located on the first insulating layer. FIG. 15B is a schematic diagram of the first conductive layer pattern in the translucent display area according to FIG. 12, and FIG. 15C is a schematic diagram of the translucent display area according to FIG. 12 after the first conductive layer pattern has been formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0132] In an exemplary embodiment, as shown in FIGS. 15B and 15C, the first conductive layer pattern may include a control pole T12 of the first transistor through a control pole T72 of the seventh transistor, and a first plate C1 of the capacitor.

[0133] 15B and 15C, the shape of the first plate C1 of the capacitor may be rectangular, the corners of the rectangle may be chamfered, and the orthogonal projection of the first plate C1 of the capacitor on the base at least partially overlaps with the orthogonal projection of the base of the active layer of the third transistor T3. In the exemplary embodiment, the first plate C1 of the capacitor may simultaneously serve as the control pole T32 of the third transistor.

[0134] In an exemplary embodiment, the control pole T12 of the first transistor may have a linear shape extending along the second direction X, as shown in FIGS. 15B and 15C.

[0135] In an exemplary embodiment, as shown in FIGS. 15B and 15C, the control pole T22 of the second transistor, the control pole T42 of the fourth transistor, and the control pole T72 of the seventh transistor may be an integrally molded structure and may have a linear shape extending along the second direction X.

[0136] In an exemplary embodiment, as shown in FIGS. 15B and 15C, the control pole T52 of the fifth transistor and the control pole T62 of the sixth transistor may be an integrally molded structure, and may have a linear shape extending along the second direction X.

[0137] In an exemplary embodiment, as shown in FIG. 15C , after forming the first conductive layer pattern, the semiconductor layer can be subjected to a conductive treatment using the first conductive layer as a shield, and the semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the first conductive layer is made conductive, that is, the first and second regions of the active layer of the first transistor to the seventh transistor are all made conductive, and the first and second regions of the active layer of the third transistor that has been made conductive are made conductive. The first region of the active layer of the third transistor (which is also the second region of the active layer of the fourth transistor and the second region of the active layer of the fifth transistor) that has been conductive may simultaneously be the first pole T33 of the third transistor, the second pole T44 of the fourth transistor, and the second pole T54 of the fifth transistor, and the second region of the active layer of the conductive third transistor (which is also the second region of the active layer of the second transistor and the first region of the active layer of the sixth transistor) may simultaneously be the second pole T24 of the second transistor, the second pole T34 of the third transistor, and the first pole T63 of the sixth transistor.

[0138] (3) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 15D and 15E, forming the second conductive layer pattern may include depositing a second insulating layer thin film and a second conductive thin film on the patterned base, and patterning the second conductive thin film by a patterning process to form a second conductive layer pattern in the second insulating layer. FIG. 15D is a schematic diagram of the second conductive layer pattern in the light-transmitting display area according to FIG. 12, and FIG. 15E is a schematic diagram of the light-transmitting display area after the second conductive layer pattern has been formed according to FIG. 12. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0139] In an exemplary embodiment, as shown in FIGS. 15D and 15E, the second conductive layer pattern may include a first connecting electrode VL1 and a second plate C2 of the capacitor.

[0140] In an exemplary embodiment, as shown in FIGS. 15D and 15E, at least a portion of the first connection electrode VL1 may extend along the second direction X.

[0141] 15D and 15E, the contour shape of the second plate C2 may be an "L" shape, and there is an overlapping area between the orthogonal projection at the base of the second plate C2 and the orthogonal projection at the base of the first plate C1, and the second plate C2 is the other plate of the capacitor. The first plate C1 and the second plate C2 constitute the capacitor of the pixel circuit.

[0142] (4) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in FIG. 15F, forming the third insulating layer pattern may include depositing a third insulating thin film on the patterned base, and patterning the third insulating thin film through a patterning process to form a third insulating layer covering the second conductive layer, and forming a plurality of vias in the third insulating layer. FIG. 15F is a schematic diagram of the transparent display area according to FIG. 12 after the third insulating layer pattern is formed.

[0143] 15F , the plurality of vias may include a first via V1 to a sixth via V6 provided in the first to third insulating layers, a seventh via V7 to a thirteenth via V13 provided in the second and third insulating layers, and a fourteenth via V14 to a sixteenth via V16 provided in the third insulating layer. The first via V1 exposes a connection portion between the active layer of the first transistor and the active layer of the second transistor, the second via V2 exposes a connection portion between the active layer of the first transistor and the active layer of the seventh transistor, the third via V3 exposes the active layer of the fourth transistor, the fourth via V4 exposes the active layer of the fifth transistor, the fifth via V5 exposes the active layer of the sixth transistor, the sixth via V6 exposes the active layer of the seventh transistor, the seventh via V7 and the eighth via V8 expose both ends of the control electrode of the first transistor, and the ninth via V14 exposes the active layer of the fifth transistor. The vias V10 and V10 expose both ends of the integrally molded structure of the control pole of the second transistor, the control pole of the fourth transistor, and the control pole of the seventh transistor, respectively; the vias V11 and V12 expose both ends of the integrally molded structure of the control pole of the fifth transistor and the control pole of the sixth transistor, respectively; the via V13 exposes the first electrode plate of the capacitor; the via V14 exposes the second electrode plate of the capacitor; and the vias V15 and V16 expose both ends of the first connecting electrode, respectively.

[0144] (5) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 15G and 15H, forming the third conductive layer may include depositing a third conductive thin film on the patterned base and patterning the third conductive thin film through a patterning process to form a third conductive layer disposed on the third insulating layer. FIG. 15G is a schematic diagram of the third conductive layer pattern in the light-transmitting display area according to FIG. 12, and FIG. 15H is a schematic diagram of the light-transmitting display area after the third conductive layer pattern has been formed according to FIG. 12. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0145] In an exemplary embodiment, as shown in Figures 15G and 15H, the third conductive layer pattern may include a first pole T13 and a second pole T14 of the first transistor, a first pole T23 of the second transistor, a first pole T43 of the fourth transistor, a first pole T53 of the fifth transistor, a second pole T64 of the sixth transistor, a first pole T73 and a second pole T74 of the seventh transistor, a second connecting electrode VL2 to an eleventh connecting electrode VL11, and a shield electrode SL.

[0146] 15G and 15H, in an exemplary embodiment, the first pole T13 of the first transistor may simultaneously serve as the first pole T73 of the seventh transistor, the second pole T14 of the first transistor may simultaneously serve as the first pole T23 of the second transistor, the second pole T64 of the sixth transistor may simultaneously serve as the second pole T74 of the seventh transistor, and the first pole T43 of the fourth transistor and the first pole T53 of the fifth transistor may be separately located. The first pole T13 of the first transistor and the second pole T14 of the first transistor may be L-shaped, the first pole T43 of the fourth transistor has a block structure, the first pole T53 of the fifth transistor has a horizontally inverted "L" shape, and the second pole of the sixth transistor may be a broken line extending along the first direction Y.

[0147] In an exemplary embodiment, as shown in Figures 15G and 15H, the second connection electrode VL2 to the eighth connection electrode VL8 have a block structure, and the ninth connection electrode VL9 to the eleventh connection electrode VL11 have a linear or broken line shape extending along the first direction Y.

[0148] In an exemplary embodiment, as shown in FIGS. 15G and 15H, the shield electrode SL has a block structure, the orthogonal projection at the base of which overlaps the orthogonal projection at the base of the control electrode of the first transistor.

[0149] 15G and 15H, in an exemplary embodiment, the first pole T13 of the first transistor is electrically connected to the junction between the active layer of the first transistor and the active layer of the seventh transistor through the second via and to the first connecting electrode through the sixteenth via; the second pole T14 of the first transistor is electrically connected to the junction between the active layer of the first transistor and the active layer of the second transistor through the first via and to the first plate of the capacitor through the thirteenth via; the first pole T43 of the fourth transistor is electrically connected to the active layer of the fourth transistor through the third via; the first pole T53 of the fifth transistor is electrically connected to the active layer of the fifth transistor through the fourth via and to the second plate of the capacitor through the fourteenth via; the second pole T64 of the sixth transistor is electrically connected to the active layer of the sixth transistor through the fifth via and to the active layer of the seventh transistor through the sixth via; and the second connecting electrode VL2 is electrically connected to the control pole of the first transistor through the seventh via. The third connection electrode VL3 is electrically connected to the control electrode of the first transistor through the eighth via, the fourth connection electrode VL4 is electrically connected to the control electrode of the fourth transistor through the ninth via, the fifth connection electrode VL5 is electrically connected to the control electrode of the fourth transistor through the tenth via, the sixth connection electrode VL6 is electrically connected to the control electrode of the fifth transistor through the eleventh via, the seventh connection electrode VL7 is electrically connected to the control electrode of the fifth transistor through the twelfth via, and the eighth connection electrode VL8 is electrically connected to the first connection electrode through the fifteenth via.

[0150] (6) Forming a fourth insulating layer. In an exemplary embodiment, as shown in FIG. 15I, forming a fourth insulating layer pattern includes depositing a fourth insulating thin film on the patterned base and patterning the fourth insulating thin film through a patterning process to form a fourth insulating layer covering the third conductive layer, and providing a plurality of vias in the fourth insulating layer. FIG. 15I is a schematic diagram of the transparent display area according to FIG. 12 after the fourth insulating layer pattern is formed.

[0151] 15I, the plurality of vias in the fourth insulating layer pattern may include a 17th via V17 to a 31st via V31. The 17th via V17 exposes the first electrode of the first transistor, the 18th via V18 exposes the first electrode of the fourth transistor, the 19th via V19 exposes the first electrode of the fifth transistor, the 20th via V20 exposes the second electrode of the sixth transistor, the 21st via V21 exposes the second connecting electrode, the 22nd via V22 exposes the third connecting electrode, and the 23rd via V23 exposes the fourth connecting electrode. , the 24th via V24 exposes the 5th connecting electrode, the 25th via V25 exposes the 6th connecting electrode, the 26th via V26 exposes the 7th connecting electrode, the 27th via V27 exposes the 8th connecting electrode, the 28th via V28 exposes the shield electrode, the 29th via V29 exposes the 9th connecting electrode, the 30th via V30 exposes the 10th connecting electrode, and the 31st via V31 exposes the 11th connecting electrode.

[0152] In an exemplary embodiment, the number of the 29th vias V29 may be two, and the two 29th vias may be arranged along the first direction Y and located at both ends of the 9th connection electrode, respectively.

[0153] In an exemplary embodiment, the number of the 30th vias V30 may be two, and the two 30th vias V30 may be arranged along the first direction Y and located at both ends of the 10th connecting electrode, respectively.

[0154] In an exemplary embodiment, the number of the 31st vias V31 may be two, and the two 31st vias V31 may be arranged along the first direction Y and located at both ends of the 11th connecting electrode, respectively.

[0155] (7) Forming a transparent conductive layer pattern. In this exemplary embodiment, as shown in Figures 15J and 15K, forming a transparent conductive layer pattern may include depositing a transparent conductive thin film on the patterned base, and patterning the transparent conductive thin film through a patterning process to form a transparent conductive layer on the fourth insulating layer. Figure 15J is a schematic view of the transparent display area after the fourth insulating layer pattern is formed according to Figure 12, and Figure 15K is a schematic view of the transparent conductive layer pattern in the transparent display area according to Figure 12.

[0156] In an exemplary embodiment, as shown in Figures 15J and 15K, the transparent conductive layer pattern may include a data signal line Data, a first power supply line VDD, a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, a fourth anode connecting line AL4, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scanning signal line, two sub-signal lines EM_1 and EM_2 of the emission signal line, a twelfth connecting electrode VL12 and a thirteenth connecting electrode VL13.

[0157] In an exemplary embodiment, as shown in Figures 15J and 15K, the data signal line Data and the first power supply line VDD may be located between two sub-signal lines of a plurality of first signal lines electrically connected to the first type pixel circuits to which the data signal line Data and the first power supply line VDD are electrically connected, and there is an overlapping portion between the orthogonal projection at the base and the orthogonal projection at the base of the first type pixel circuit.

[0158] 15J and 15K, in an exemplary embodiment, the data signal line Data may be a polygonal line, and at least a portion of the data signal line Data may extend along the first direction Y. The data signal lines Data electrically connecting adjacent first-type pixel circuits located in the same column may be the same signal line or may be spaced apart. The data signal lines Data electrically connecting two adjacent first-type pixel circuits located in the same column but spaced apart may be electrically connected to the ninth connecting electrode via the 29th via, and the data signal lines Data electrically connecting first-type pixel circuits located in the same column but spaced apart may be electrically connected via the 9th connecting electrode. The data signal line is electrically connected to the first electrode of the fourth transistor of the first-type pixel circuit electrically connecting via the 18th via.

[0159] In an exemplary embodiment, as shown in FIGS. 15J and 15K, the first power supply line VDD may be a polygonal line, at least a portion of which may extend along the first direction Y. The first power supply lines VDD electrically connecting adjacent first-type pixel circuits located in the same column may be spaced apart. The first power supply line is electrically connected to the first electrodes of the fifth transistors of the first-type pixel circuits electrically connecting through vias 19 and 28, and electrically connected to the shield electrode through via 28. Exemplarily, the first power supply lines VDD electrically connecting two adjacent first-type pixel circuits located in the same column and spaced apart may be electrically connected directly through a single tenth connection electrode, or may be electrically connected through tenth, twelfth, and tenth connection electrodes, respectively. The first power supply line VDD and the twelfth connection electrode electrically connecting the first-type pixel circuits may be electrically connected to the tenth connection electrode through via 30.

[0160] In an exemplary embodiment, the first to fourth anode connecting lines AL1 to AL4 may be polygonal lines.

[0161] In an exemplary embodiment, as shown in FIGS. 15J and 15K, the first anode connecting line AL1 is located between the first power supply lines spaced apart, at least a portion of the first anode connecting line AL1 extends along the second direction X, and the first anode connecting line AL1 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit to which it is electrically connected through the 20th via.

[0162] In an exemplary embodiment, as shown in FIGS. 15J and 15K, the second anode connecting line AL2 is located between the first power supply lines spaced apart, at least a portion of the second anode connecting line AL2 extends along the second direction X, and the second anode connecting line AL2 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit to which it is electrically connected through the 20th via, and is electrically connected to the 11th connecting electrode through the 31st via.

[0163] In an exemplary embodiment, as shown in FIGS. 15J and 15K, the third anode connecting line AL3 is located between the data signal line Data and the first power supply line VDD to which the first-type pixel circuit to which it is electrically connected is electrically connected, at least a portion of the third anode connecting line AL3 extends along the second direction X, and the third anode connecting line AL3 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit to which it is electrically connected through the 20th via.

[0164] In an exemplary embodiment, as shown in FIGS. 15J and 15K, the fourth anode connecting line AL4 is located between the data signal line Data and the first power supply line VDD to which the first-type pixel circuit to which it is electrically connected is electrically connected, at least a portion of the fourth anode connecting line AL4 extends along the second direction X, and the fourth anode connecting line AL4 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit to which it is electrically connected through the 20th via.

[0165] 15J and 15K, at least a portion of the 13th connecting electrode VL13 extends along the second direction X and is electrically connected to the 11th connecting electrode through the 31st via. The second anode connecting line AL1 is electrically connected to the first type pixel circuit, the 11th connecting electrode, and the 13th connecting electrode, respectively.

[0166] 15J and 15K, in an exemplary embodiment, the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may be polygonal lines, at least a portion of the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may extend along the second direction X, the sub-signal line INIT_1 of the initial signal line is electrically connected to the eighth connecting electrode through the 27th via, the sub-signal line INIT_2 of the initial signal line is electrically connected to the first pole of the first transistor through the 17th via, the sub-signal line INIT_1 of the initial signal line is electrically connected to the first connecting electrode through the eighth connecting electrode, and the sub-signal line INIT_2 of the initial signal line is electrically connected to the first connecting electrode through the first pole of the first transistor.

[0167] 15J and 15K, in an exemplary embodiment, the two sub-signal lines RST_1 and RST_2 of the reset signal line may be bent lines, at least a portion of the two sub-signal lines RST_1 and RST_2 of the reset signal line may extend along the second direction X, and the sub-signal lines RST_1 and RST_2 of the reset signal line are electrically connected to the second connecting electrode through via 21, and the sub-signal line RST_2 of the reset signal line is electrically connected to the third connecting electrode through via 22. The sub-signal line RST_1 of the reset signal line is electrically connected to the control electrode of the first transistor through the second connecting electrode, and the sub-signal line RST_2 of the reset signal line is electrically connected to the control electrode of the first transistor through the third connecting electrode.

[0168] 15J and 15K, in an exemplary embodiment, the two sub-signal lines Gate_1 and Gate_2 of the scanning signal line may be polygonal lines, at least a portion of the two sub-signal lines Gate_1 and Gate_2 of the scanning signal line may extend along the second direction X, and the sub-signal lines Gate_1 and Gate_2 of the scanning signal line are electrically connected to the fourth connecting electrode through the 23rd via and the sub-signal lines Gate_1 and Gate_2 of the scanning signal line are electrically connected to the fifth connecting electrode through the 24th via. The sub-signal line Gate_1 of the scanning signal line is electrically connected to the control electrode of the fourth transistor through the fourth connecting electrode, and the sub-signal line Gate_2 of the scanning signal line is electrically connected to the control electrode of the fourth transistor through the fifth connecting electrode.

[0169] 15J and 15K, in an exemplary embodiment, the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line may be polygonal lines, at least a portion of the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line may extend along the second direction X, the sub-signal line EM_1 of the light-emitting signal line is electrically connected to the sixth connecting electrode through the 25th via, and the sub-signal line EM_1 of the light-emitting signal line is electrically connected to the seventh connecting electrode through the 26th via, the sub-signal line EM_1 of the light-emitting signal line is electrically connected to the control electrode of the fifth transistor through the sixth connecting electrode, and the sub-signal line EM_2 of the light-emitting signal line is electrically connected to the control electrode of the fifth transistor through the seventh connecting electrode.

[0170] (8) Forming a first flat layer pattern. In an exemplary embodiment, as shown in FIG. 15L, forming the first flat layer pattern may include depositing a first flat thin film on the patterned base to form a first flat layer pattern on the transparent conductive layer, where the first flat layer pattern includes a plurality of vias. FIG. 15L is a schematic diagram of the transparent display area according to FIG. 12 after the first flat layer is formed.

[0171] 15L , the first flat layer pattern may include a 32nd via V32 and a 38th via V38. The 32nd via V32 exposes the first anode connecting line, the 33rd via V33 exposes the second anode connecting line, the 34th via V34 exposes the third anode connecting line, the 35th via V35 exposes the fourth anode connecting line, the 36th via V36 exposes the 13th connecting electrode, the 37th via V37 exposes the first power supply line VDD, and the 38th via V38 exposes the 12th connecting electrode.

[0172] In an exemplary embodiment, as shown in FIG. 15L, the number of 32 vias V32 may be two, and they may be located at both ends of the first anode connecting line. The number of 33 vias V33 may be two, and they may be located at both ends of the second anode connecting line. The number of 34 vias V34 may be two, and they may be located at both ends of the third anode connecting line. The number of 35 vias V35 may be two, and they may be located at both ends of the fourth anode connecting line.

[0173] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 15M and 15N, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the patterned base and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer disposed on the first planar layer. FIG. 15M is a schematic diagram of the fourth conductive layer pattern in the light-transmitting display area according to FIG. 12, and FIG. 15N is a schematic diagram of the light-transmitting display area according to FIG. 12 after the fourth conductive layer pattern has been formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0174] In an exemplary embodiment, as shown in FIGS. 15M and 15N, the fourth conductive layer pattern may include a fourteenth connection electrode VL14 to a twenty-first connection electrode VL21, a first signal connection line VDL1, and a second signal connection line VDL2.

[0175] 15M and 15N, the fourteenth connection electrode VL14 to the twenty-first connection electrode VL21 have a block structure. The first signal connection line VDL1 and the second signal connection line VDL2 may have a polygonal line shape, and at least a portion of the first signal connection line VDL1 and the second signal connection line VDL2 extends along the first direction Y.

[0176] 15M and 15N, in the exemplary embodiment, the fourteenth connecting electrode VL14 and the fifteenth connecting electrode VL15 are electrically connected to the first anode connecting line through the via 32, the sixteenth connecting electrode VL1 is electrically connected to the second anode connecting line through the via 33, the seventeenth connecting electrode VL17 is electrically connected to the thirteenth connecting electrode through the via 36, ​​the eighteenth connecting electrode VL18 and the nineteenth connecting electrode VL19 are electrically connected to the third anode connecting line through the via 34, and the twentieth via V20 and the twenty-first via V21 are electrically connected to the fourth anode connecting line through the via 35. The first signal connecting line VDL1 is electrically connected to the first power supply line VDD to which the first type pixel circuit is electrically connected through the via 37, and the second signal connecting line VDL2 is electrically connected to the twelfth connecting electrode through the via 38 and to the first power supply line through the via 37.

[0177] In an exemplary embodiment, the first power supply lines electrically connected to the first-type pixel circuits located in the same column are connected via the first power supply connecting line, the tenth connecting electrode, and the second power supply connecting line, and the data signal lines electrically connected to the first-type pixel circuits located in the same column are connected via the ninth connecting electrode.

[0178] In an exemplary embodiment, as shown in FIG. 15N, the 14th connecting electrode VL14 is electrically connected to the 15th connecting electrode VL15 via the first anode connecting wire, the 16th connecting electrode VL16 is electrically connected to the 17th connecting electrode VL17 via the second anode connecting wire, the 11th connecting electrode and the 13th connecting electrode, the 18th connecting electrode VL18 is electrically connected to the 19th connecting electrode VL19 via the third anode connecting wire, and the 20th connecting electrode VL20 is electrically connected to the 21st connecting electrode VL21 via the fourth anode connecting wire.

[0179] In an exemplary embodiment, the plurality of connection electrodes serve a receiving role, which can avoid unreliable connections caused by opening deep vias, and can improve the reliability of the display panel.

[0180] (10) Forming a second flat layer pattern. In an exemplary embodiment, as shown in FIG. 15O, forming the second flat layer pattern may include applying a second flat thin film on the patterned base and patterning the second flat thin film through a patterning process to form a second flat layer covering the fourth conductive layer, and forming a plurality of vias in the second flat layer. FIG. 15O is a schematic diagram of the transparent display area according to FIG. 12 after the second flat layer pattern is formed.

[0181] 15O, the plurality of vias in the second flat layer pattern may all include the 39th via V39 to the 46th via V46. The 39th via V39 exposes the 14th connecting electrode, the 40th via V40 exposes the 15th connecting electrode, the 41st via V41 exposes the 16th connecting electrode, the 42nd via V42 exposes the 17th connecting electrode, the 43rd via V43 exposes the 18th connecting electrode, the 44th via V44 exposes the 19th connecting electrode, the 45th via V45 exposes the 20th connecting electrode, and the 46th via V46 exposes the 21st connecting electrode.

[0182] Up to this point, a driving circuit layer is fabricated on the base and completed. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of first-type pixel circuits, scan signal lines, reset signal lines, light-emitting signal lines, data signal lines, initial signal lines, and first to fourth anode connecting lines. In a plane perpendicular to the display panel, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer, which are sequentially stacked on the base.

[0183] In an exemplary embodiment, the base may be a flexible base or a rigid base. The rigid base may be made of one or more of, but not limited to, glass and quartz. The flexible base may be made of, but not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and woven fabric. In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymeric flexible film. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water-oxygen resistance of the substrate. The semiconductor layer may be made of amorphous silicon (a-Si).

[0184] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of one or more metal materials selected from silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of these metals such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo.

[0185] In an exemplary embodiment, the transparent conductive layer may employ, for example, indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0186] In an exemplary embodiment, the first, second, third, and fourth insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite. The first insulating layer may be called a buffer layer, the second insulating layer a gate insulating (GI) layer, the third insulating layer an interlayer dielectric (ILD) layer, and the fourth insulating layer a passivation (PVX) layer. The first and second planar layers may be made of organic materials such as resin. The semiconductor layer may be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc nitride oxide (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, or polythiophene. That is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology, or organic technology.

[0187] In an exemplary embodiment, after the fabrication of the driving circuit layer is completed, a light emitting structure layer is fabricated on the driving circuit layer, and the fabrication process of the light emitting structure layer may include the following operations.

[0188] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, as shown in Figures 15P and 15Q, forming an anode conductive layer pattern may include depositing an anode conductive thin film on the patterned base and patterning the anode conductive thin film through a patterning process to form an anode conductive layer pattern disposed on the second flat layer. Figure 15P is a schematic diagram of the anode conductive layer pattern in the translucent display area according to Figure 12, and Figure 15Q is a schematic diagram of the translucent display area according to Figure 12 after the anode conductive layer pattern has been formed.

[0189] In an exemplary embodiment, the anode conductive layer may have a single layer structure such as indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0190] In an exemplary embodiment, the anode conductive layer pattern may include an anode 110 of the first light-emitting elements 11a and 11b, an anode 120 of the second light-emitting element, and an anode 130 of the third light-emitting elements 13a-13d.

[0191] In an exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the 14th connection electrode via the 39th via, the anode of the first light-emitting element 11b is electrically connected to the 15th connection electrode via the 40th via, the anode of the second light-emitting element 12b is electrically connected to the 16th connection electrode via the 41st via, the anode of the second light-emitting element 12a is electrically connected to the 17th connection electrode via the 42nd via, the anode of the third light-emitting element 13a is electrically connected to the 18th connection electrode via the 43rd via, the anode of the third light-emitting element 13b is electrically connected to the 19th connection electrode via the 44th via, the anode of the third light-emitting element 13c is electrically connected to the 20th connection electrode via the 45th via, and the anode of the third light-emitting element 13d is electrically connected to the 21st connection electrode via the 46th via.

[0192] In the exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b via the 14th connecting electrode, the first anode connecting line, and the 15th connecting electrode. The anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b via the 16th connecting electrode, the 11th connecting electrode, the 13th connecting electrode, and the 17th connecting electrode. The anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b via the 18th connecting electrode, the third anode connecting line, and the 19th connecting electrode. The anode of the third light-emitting element 13c is electrically connected to the anode of the third light-emitting element 13d via the 20th connecting electrode, the fourth anode connecting line, and the 21st connecting electrode.

[0193] In an exemplary embodiment, at least one of the anodes 110 of the first light-emitting elements 11a and 11b, the anode 120 of the second light-emitting element, and the anodes 130 of the third light-emitting elements 13a to 13d may include a main body portion and a connecting portion connected to each other, the main body portion may be rectangular in shape and the corners of the rectangle may be provided with arc-shaped chamfers, and the connecting portion may be strip-shaped extending in a direction away from the main body portion.

[0194] In an exemplary embodiment, the subsequent manufacturing process may include first forming a pixel definition layer pattern, then forming an organic light-emitting layer using a vapor deposition or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a package structure layer. The package structure layer may include a first package layer, a second package layer, and a third package layer stacked together, where the first package layer and the third package layer may be made of inorganic materials and the second package layer may be made of organic materials, and the second package layer may be disposed between the first package layer and the third package layer, thereby ensuring that external water vapor does not penetrate into the light-emitting structure layer.

[0195] In an exemplary embodiment, the manufacturing process of the translucent display area according to FIG. 13 may include the following operations.

[0196] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in FIG. 16A, forming a semiconductor layer pattern may include sequentially depositing a semiconductor thin film on a base and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. FIG. 16A is a schematic diagram of the transparent display area after forming a semiconductor pattern according to FIG. 13.

[0197] In an exemplary embodiment, the semiconductor layer pattern according to FIG. 16A is the same as the semiconductor layer pattern according to FIG. 15A, and will not be described here.

[0198] (2) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 16B and 16C, forming the first conductive layer pattern may include sequentially depositing a first insulating thin film and a first conductive thin film on the patterned base, and patterning the first conductive thin film by a patterning process to form a first insulating layer covering the semiconductor layer pattern and a first conductive layer pattern located on the first insulating layer. FIG. 16B is a schematic diagram of the first conductive layer pattern in the translucent display area according to FIG. 13, and FIG. 16C is a schematic diagram after the first conductive layer pattern is formed in the translucent display area according to FIG. 13. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0199] In an exemplary embodiment, the first conductive layer pattern according to FIGS. 16B and 16C is the same as the first conductive layer pattern according to FIGS. 15B and 15C, and will not be described here.

[0200] (3) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 16D and 16E, forming the second conductive layer pattern may include depositing a second insulating layer thin film and a second conductive thin film on the patterned base, and patterning the second conductive thin film by a patterning process to form a second conductive layer pattern in the second insulating layer. FIG. 16D is a schematic diagram of the second conductive layer pattern in the translucent display area according to FIG. 13, and FIG. 16E is a schematic diagram after the second conductive layer pattern is formed in the translucent display area according to FIG. 13. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0201] In an exemplary embodiment, the second conductive layer pattern according to FIGS. 16D and 16E is the same as the second conductive layer pattern according to FIGS. 15D and 15E, and will not be described here.

[0202] (4) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in FIG. 16F, forming the third insulating layer pattern may include depositing a third insulating thin film on the patterned base, and patterning the third insulating thin film through a patterning process to form a third insulating layer covering the second conductive layer, and forming a plurality of vias in the third insulating layer. FIG. 16F is a schematic diagram of the transparent display area according to FIG. 13 after the third insulating layer pattern is formed.

[0203] In an exemplary embodiment, the third insulating layer pattern according to FIG. 16F is the same as the third insulating layer pattern according to FIG. 15F, and will not be described here.

[0204] (5) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 16G and 16H, forming the third conductive layer may include depositing a third conductive thin film on the patterned base and patterning the third conductive thin film through a patterning process to form a third conductive layer disposed on the third insulating layer. FIG. 16G is a schematic diagram of the third conductive layer pattern in the light-transmitting display area according to FIG. 13, and FIG. 16H is a schematic diagram of the light-transmitting display area after the third conductive layer pattern has been formed according to FIG. 13. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0205] In an exemplary embodiment, as shown in Figures 16G and 16H, the third conductive layer pattern may include a first pole T13 and a second pole T14 of the first transistor, a first pole T23 of the second transistor, a first pole T43 of the fourth transistor, a first pole T53 of the fifth transistor, a second pole T64 of the sixth transistor, a first pole T73 and a second pole T74 of the seventh transistor, the second connection electrode VL2 to the tenth connection electrode VL10, and a shield electrode SL and a power connection line VCL.

[0206] In the exemplary embodiment, the first pole T13 and the second pole T14 of the first transistor, the first pole T23 of the second transistor, the first pole T43 of the fourth transistor, the first pole T53 of the fifth transistor, the second pole T64 of the sixth transistor, the first pole T73 and the second pole T74 of the seventh transistor, the second connecting electrode VL2 to the eighth connecting electrode VL8, and the shield electrode according to Figures 16G and 16H have the same pattern as the first pole T13 and the second pole T14 of the first transistor, the first pole T23 of the second transistor, the first pole T43 of the fourth transistor, the first pole T53 of the fifth transistor, the second pole T64 of the sixth transistor, the first pole T73 and the second pole T74 of the seventh transistor, the second connecting electrode VL2 to the eighth connecting electrode VL8, and the shield electrode SL according to Figures 15G and 15H, and will not be described here.

[0207] 16G and 16H, at least a portion of the ninth connection electrode VL9 and the tenth connection electrode VL10 extends along the second direction X. The power supply connection line VCL extends along the second direction X.

[0208] (6) Forming a fourth insulating layer. In an exemplary embodiment, as shown in FIG. 16I, forming a fourth insulating layer pattern includes depositing a fourth insulating thin film on the patterned base, and patterning the fourth insulating thin film through a patterning process to form a fourth insulating layer covering the third conductive layer, and a plurality of vias are provided in the fourth insulating layer. FIG. 16I is a schematic diagram of the transparent display area according to FIG. 13 after the fourth insulating layer pattern is formed.

[0209] In an exemplary embodiment, as shown in Fig. 16I, the multiple vias in the fourth insulating layer pattern may all include the 17th via V17 to the 31st via V31. The 17th via V17 to the 28th via V28 in Fig. 16I are the same as the 17th via V17 to the 28th via V28 in Fig. 15I, except that the 29th via V29 exposes the 9th connecting electrode, the 30th via V30 exposes the 10th connecting electrode, and the 31st via V31 exposes the power supply connecting line VCL.

[0210] In an exemplary embodiment, the number of the 29th vias V29 may be two, and the two 29th vias may be arranged along the second direction X and located at both ends of the 9th connection electrode, respectively.

[0211] In an exemplary embodiment, the number of the thirtieth vias V30 may be two, and the two thirtieth vias V30 may be arranged along the second direction X and located at both ends of the tenth connecting electrode, respectively.

[0212] In an exemplary embodiment, the number of the 31st vias V31 may be two, and the two 31st vias V31 may be arranged along the second direction X and located at both ends of the electrode connecting line, respectively.

[0213] (7) Forming a transparent conductive layer pattern. In an exemplary embodiment, as shown in Figures 16J and 16K, forming a transparent conductive layer pattern may include depositing a transparent conductive thin film on the patterned base and patterning the transparent conductive thin film through a patterning process to form a transparent conductive layer disposed on the fourth insulating layer. Figure 16J is a schematic diagram of the transparent conductive layer pattern in the light-transmitting display area according to Figure 13, and Figure 16K is a schematic diagram of the light-transmitting display area after the transparent conductive layer pattern has been formed according to Figure 13.

[0214] In an exemplary embodiment, as shown in Figures 16J and 16K, each transparent conductive layer pattern may include a data signal line Data, a first power supply line VDD, a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, a fourth anode connecting line AL4, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scanning signal line, two sub-signal lines EM_1 and EM_2 of the emission signal line, an eleventh connecting electrode VL11 and a twelfth connecting electrode VL12.

[0215] In an exemplary embodiment, as shown in Figures 16J and 16K, the data signal line Data and the first power supply line VDD are located between two sub-signal lines of a plurality of first signal lines to which the first type pixel circuits to which the data signal line Data and the first power supply line VDD are electrically connected are electrically connected, and there may be an overlapping portion between the orthogonal projection at the base and the orthogonal projection at the base of the first type pixel circuit.

[0216] 16J and 16K, the data signal line Data is a polygonal line, at least a portion of which extends along the first direction Y, and the data signal line Data electrically connected to adjacent first-type pixel circuits located in the same column may be the same signal line. The data signal line is electrically connected to the first electrodes of the fourth transistors of the first-type pixel circuits electrically connected to it through the 18th via.

[0217] 16J and 16K, the first power supply line VDD is a polygonal line, at least a portion of the first power supply line VDD extends along the first direction Y, and the first power supply lines VDD electrically connected to adjacent first-type pixel circuits located in the same column may be installed at intervals. The first power supply line is electrically connected to the first electrode of the fifth transistor of the first-type pixel circuit electrically connected thereto through the 19th via, and is electrically connected to the shield electrode through the 28th via.

[0218] In an exemplary embodiment, as shown in FIGS. 16J and 16K, the first power line VDD includes a power supply main body portion VDDM extending along a first direction Y and a power supply connection portion VDDS at least a portion of which extends along a second direction X.

[0219] 16J and 16K, at least a portion of the power supply connecting line VCL extends along the second direction X and is electrically connected to a first power supply line VDD to which adjacent first-type pixel circuits located in the same row are electrically connected. A power supply connection portion of the first power supply line to which one of the first-type pixel circuits located in the same row is electrically connected is electrically connected to the power supply connecting line VCL through via 31, and a power supply body of the first power supply line to which the other of the first-type pixel circuits located in the same row is electrically connected is electrically connected to the power supply connecting line VCL through via 31. The placement of the power supply connecting line VCL in cooperation with the first power supply line forms a mesh structure, which can achieve uniformity in the display of the display substrate.

[0220] In an exemplary embodiment, as shown in FIGS. 16J and 16K, the first to fourth anode connecting lines AL1 to AL4 may be polygonal lines.

[0221] In an exemplary embodiment, as shown in FIGS. 16J and 16K , the first anode connecting line AL1 is located between the first power supply line VDD to which the first-type pixel circuit electrically connects and the data signal line Data of the first-type pixel circuit in the adjacent column, at least a portion of the first anode connecting line AL1 extends along the second direction X, and the first anode connecting line AL1 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit electrically connected to it through the 20th via and electrically connected to the 9th connecting electrode through the 29th via.

[0222] In an exemplary embodiment, as shown in FIGS. 16J and 16K , the second anode connecting line AL2 is located between the first power supply line VDD to which the first-type pixel circuit to which it is electrically connected and the data signal line Data of the first-type pixel circuit in the adjacent column, at least a portion of the second anode connecting line AL2 extends along the second direction X, and the second anode connecting line AL2 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit to which it is electrically connected through the 20th via, and is electrically connected to the 10th connecting electrode through the 30th via.

[0223] 16J and 16K, the third anode connecting line AL3 is located between the first power supply line VDD to which the first-type pixel circuit electrically connected and the data signal line Data to which the adjacent first-type pixel circuit located in the same row electrically connected. At least a portion of the third anode connecting line AL3 extends along the first direction Y, and the third anode connecting line AL3 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit electrically connected thereto through the 20th via.

[0224] 16J and 16K, the fourth anode connecting line AL4 is located between the first power supply line VDD to which the first-type pixel circuit electrically connected and the data signal line Data to which the adjacent first-type pixel circuit located in the same row electrically connected. At least a portion of the fourth anode connecting line AL4 may extend along the first direction Y, and the fourth anode connecting line AL4 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit electrically connected through the 20th via.

[0225] In an exemplary embodiment, as shown in FIGS. 16J and 16K, the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may be polygonal lines, at least a portion of which extends along the first direction Y. The sub-signal line INIT_1 of the initial signal line is electrically connected to the eighth connecting electrode through the 27th via, and the sub-signal line INIT_2 of the initial signal line is electrically connected to the first pole of the first transistor through the 17th via. The sub-signal line INIT_1 of the initial signal line is electrically connected to the first connecting electrode through the 8th connecting electrode. The sub-signal line INIT_2 of the initial signal line is electrically connected to the first connecting electrode through the first pole of the first transistor.

[0226] 16J and 16K, in an exemplary embodiment, the two sub-signal lines RST_1 and RST_2 of the reset signal line may be bent-line shaped, at least a portion of the two sub-signal lines RST_1 and RST_2 of the reset signal line may extend along the second direction Y, and the sub-signal line RST_1 of the reset signal line is electrically connected to the second connecting electrode through the via 21, and the sub-signal line RST_2 of the reset signal line is electrically connected to the third connecting electrode through the via 22. The sub-signal line RST_1 of the reset signal line is electrically connected to the control electrode of the first transistor through the second connecting electrode, and the sub-signal line RST_2 of the reset signal line is electrically connected to the control electrode of the first transistor through the third connecting electrode.

[0227] 16J and 16K, in an exemplary embodiment, the two sub-signal lines Gate_1 and Gate_2 of the scanning signal line may be bent lines, at least a portion of the two sub-signal lines Gate_1 and Gate_2 of the scanning signal line may extend along the second direction Y, the sub-signal line Gate_1 of the scanning signal line is electrically connected to the fourth connecting electrode through the 23rd via, and the sub-signal line Gate_2 of the scanning signal line is electrically connected to the fifth connecting electrode through the 24th via. The sub-signal line Gate_1 of the scanning signal line is electrically connected to the control electrode of the fourth transistor through the fourth connecting electrode, and the sub-signal line Gate_2 of the scanning signal line is electrically connected to the control electrode of the fourth transistor through the fifth connecting electrode.

[0228] 16J and 16K, in an exemplary embodiment, the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line may be bent-line shaped, at least a portion of the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line may extend along the second direction Y, and the sub-signal line EM_1 of the light-emitting signal line is electrically connected to the sixth connecting electrode through the 25th via, and the sub-signal line EM_1 of the light-emitting signal line is electrically connected to the seventh connecting electrode through the 26th via. The sub-signal line EM_1 of the light-emitting signal line is electrically connected to the control electrode of the fifth transistor through the sixth connecting electrode, and the sub-signal line EM_2 of the light-emitting signal line is electrically connected to the control electrode of the fifth transistor through the seventh connecting electrode.

[0229] (8) Forming a first flat layer pattern. In an exemplary embodiment, as shown in FIG. 16L, forming the first flat layer pattern may include depositing a first flat thin film on the patterned base to form a first flat layer pattern disposed on the transparent conductive layer, and the first flat layer pattern may include a plurality of vias. FIG. 16L is a schematic diagram of the transparent display area according to FIG. 13 after the first flat layer is formed.

[0230] 16L , the first flat layer pattern may include a 32nd via V32 and a 38th via V38. The 32nd via exposes the first power supply line, the 33rd via V33 exposes the first anode connecting line, the 34th via V34 exposes the second anode connecting line, the 35th via V35 exposes the third anode connecting line, the 36th via V36 exposes the fourth anode connecting line, the 37th via V37 exposes the 11th connecting electrode, and the 38th via V38 exposes the 12th connecting electrode.

[0231] In an exemplary embodiment, as shown in FIG. 16L, the number of 33 vias V33 may be two, and they may be located at both ends of the first anode connecting line. The number of 34 vias V34 may be two, and they may be located at both ends of the second anode connecting line. The number of 35 vias V35 may be two, and they may be located at both ends of the third anode connecting line. The number of 36 vias V36 may be two, and they may be located at both ends of the fourth anode connecting line.

[0232] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 16M and 16N, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the patterned base and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer disposed on the first planar layer. FIG. 16M is a schematic diagram of the fourth conductive layer pattern in the light-transmitting display area according to FIG. 13, and FIG. 16N is a schematic diagram of the light-transmitting display area according to FIG. 13 after the fourth conductive layer pattern has been formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0233] In an exemplary embodiment, as shown in FIGS. 16M and 16N, the fourth conductive layer pattern may have a thirteenth connection electrode VL13 to a twentieth connection electrode VL20 and a signal connection line VDL.

[0234] 16M and 16N, the thirteenth connection electrode VL13 to the twentieth connection electrode VL20 have a block structure. The signal connection line VDL may have a polygonal line shape, and at least a part of the signal connection line VDL may extend along the first direction Y.

[0235] 16M and 16N, the thirteenth-connecting electrode VL13 is electrically connected to the first anode connecting line through the via-hole 33, the fourteenth-connecting electrode VL14 is electrically connected to the second anode connecting line through the via-hole 34, the fifteenth-connecting electrode VL15 and the sixteenth-connecting electrode VL16 are electrically connected to the third anode connecting line through the via-hole 35, the seventeenth-connecting electrode VL17 and the eighteenth-connecting electrode VL18 are electrically connected to the fourth anode connecting line through the via-hole 36, the nineteenth-connecting electrode VL19 is electrically connected to the eleventh-connecting electrode through the via-hole 37, and the twentieth-connecting electrode VL20 is electrically connected to the twelfth-connecting electrode through the via-hole 38. The signal connecting line VDL is electrically connected to a first power supply line to which the first-type pixel circuits are electrically connected through the via-hole 32.

[0236] In an exemplary embodiment, the first power supply lines electrically connected to the first type pixel circuits located in the same column are electrically connected via a signal connection line.

[0237] In an exemplary embodiment, as shown in FIG. 16N, the 13th connecting electrode VL13 is electrically connected to the 19th connecting electrode VL19 via the first anode connecting wire, the 9th connecting electrode, and the 11th connecting electrode, the 14th connecting electrode VL14 is electrically connected to the 20th connecting electrode VL20 via the second anode connecting wire, the 10th connecting electrode, and the 12th connecting electrode, the 15th connecting electrode VL15 is electrically connected to the 16th connecting electrode VL16 via the third anode connecting wire, and the 17th connecting electrode VL17 is electrically connected to the 18th connecting electrode VL18 via the fourth anode connecting wire.

[0238] In an exemplary embodiment, the plurality of connection electrodes serve a receiving role, which can avoid unreliable connections caused by opening deep vias, and can improve the reliability of the display panel.

[0239] (10) Forming a second flat layer pattern. In an exemplary embodiment, as shown in FIG. 16O, forming the second flat layer pattern may include applying a second flat thin film on the patterned base and patterning the second flat thin film through a patterning process to form a second flat layer covering the fourth conductive layer, and forming a plurality of vias in the second flat layer. FIG. 16O is a schematic diagram of the transparent display area according to FIG. 13 after the second flat layer pattern is formed.

[0240] 16O, the plurality of vias in the second flat layer pattern may all include the 39th via V39 to the 46th via V46. The 39th via V39 exposes the 13th connecting electrode, the 40th via V40 exposes the 14th connecting electrode, the 41st via V41 exposes the 15th connecting electrode, the 42nd via V42 exposes the 16th connecting electrode, the 43rd via V43 exposes the 17th connecting electrode, the 44th via V44 exposes the 18th connecting electrode, the 45th via V45 exposes the 19th connecting electrode, and the 46th via V46 exposes the 20th connecting electrode.

[0241] Up to this point, a driving circuit layer is fabricated on the base and completed. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of first-type pixel circuits, scan signal lines, reset signal lines, light-emitting signal lines, data signal lines, initial signal lines, and first to fourth anode connecting lines. In a plane perpendicular to the display panel, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer, which are sequentially stacked on the base.

[0242] In an exemplary embodiment, the base may be a flexible base or a rigid base. The rigid base may be made of one or more of, but not limited to, glass and quartz. The flexible base may be made of, but not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and woven fabric. In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymeric flexible film. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water-oxygen resistance of the substrate. The semiconductor layer may be made of amorphous silicon (a-Si).

[0243] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of one or more metal materials selected from silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of these metals such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo.

[0244] In an exemplary embodiment, the transparent conductive layer may employ, for example, indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0245] In an exemplary embodiment, the first, second, third, and fourth insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite. The first insulating layer may be called a buffer layer, the second insulating layer a gate insulating (GI) layer, the third insulating layer an interlayer dielectric (ILD) layer, and the fourth insulating layer a passivation (PVX) layer. The first and second planar layers may be made of organic materials such as resin. The semiconductor layer may be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc nitride oxide (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, or polythiophene. That is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology, or organic technology.

[0246] In an exemplary embodiment, after the fabrication of the driving circuit layer is completed, a light emitting structure layer is fabricated on the driving circuit layer, and the fabrication process of the light emitting structure layer may include the following operations.

[0247] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, as shown in Figures 16P and 16Q, forming an anode conductive layer pattern may include depositing an anode conductive thin film on the patterned base, and patterning the anode conductive thin film by a patterning process to form an anode conductive layer pattern disposed on the second flat layer. Figure 16P is a schematic diagram of the anode conductive layer pattern in the translucent display area according to Figure 13, and Figure 16Q is a schematic diagram of the translucent display area according to Figure 13 after the anode conductive layer pattern has been formed.

[0248] In an exemplary embodiment, the anode conductive layer may have a single layer structure such as indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0249] In an exemplary embodiment, the anode conductive layer pattern according to FIG. 16P is the same as the anode conductive layer pattern according to FIG. 15P, and will not be described here.

[0250] In an exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the 13th connection electrode via the 39th via, the anode of the first light-emitting element 11b is electrically connected to the 19th connection electrode via the 45th via, the anode of the second light-emitting element 12a is electrically connected to the 14th connection electrode via the 40th via, the anode of the second light-emitting element 12b is electrically connected to the 20th connection electrode via the 46th via, the anode of the third light-emitting element 13a is electrically connected to the 15th connection electrode via the 41st via, the anode of the third light-emitting element 13b is electrically connected to the 16th connection electrode via the 42nd via, the anode of the third light-emitting element 13c is electrically connected to the 17th connection electrode via the 43rd via, and the anode of the third light-emitting element 13d is electrically connected to the 18th connection electrode via the 44th via.

[0251] In the exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b via the 13th connecting electrode, the first anode connecting line, the 9th connecting electrode, the 11th connecting electrode, and the 19th connecting electrode. The anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b via the 14th connecting electrode, the second anode connecting line, the 10th connecting electrode, the 12th connecting electrode, and the 20th connecting electrode. The anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b via the 15th connecting electrode, the third anode connecting line, and the 16th connecting electrode. The anode of the third light-emitting element 13c is electrically connected to the anode of the third light-emitting element 13d via the 17th connecting electrode, the fourth anode connecting line, and the 18th connecting electrode.

[0252] In an exemplary embodiment, the subsequent manufacturing process may include first forming a pixel definition layer pattern, then forming an organic light-emitting layer using a vapor deposition or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a package structure layer. The package structure layer may include a first package layer, a second package layer, and a third package layer stacked together, where the first package layer and the third package layer may be made of inorganic materials and the second package layer may be made of organic materials, and the second package layer may be disposed between the first package layer and the third package layer, thereby ensuring that external water vapor does not penetrate into the light-emitting structure layer.

[0253] In an exemplary embodiment, the manufacturing process of the translucent display area according to FIG. 14 may include the following operations.

[0254] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in FIG. 17A, forming a semiconductor layer pattern may include sequentially depositing a semiconductor thin film on a base and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. FIG. 17A is a schematic diagram of the transparent display area after forming a semiconductor pattern according to FIG. 14.

[0255] In an exemplary embodiment, the semiconductor layer pattern according to FIG. 17A is the same as the semiconductor layer pattern according to FIG. 15A, and will not be described here.

[0256] (2) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 17B and 17C, forming the first conductive layer pattern may include sequentially depositing a first insulating thin film and a first conductive thin film on the patterned base, and patterning the first conductive thin film by a patterning process to form a first insulating layer covering the semiconductor layer pattern and a first conductive layer pattern located on the first insulating layer. FIG. 17B is a schematic diagram of the first conductive layer pattern in the translucent display area according to FIG. 14, and FIG. 17C is a schematic diagram after the first conductive layer pattern is formed in the translucent display area according to FIG. 14. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0257] In an exemplary embodiment, the first conductive layer pattern according to FIGS. 17B and 17C is the same as the first conductive layer pattern according to FIGS. 15B and 15C, and will not be described here.

[0258] (3) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 17D and 17E, forming the second conductive layer pattern may include depositing a second insulating layer thin film and a second conductive thin film on the patterned base, and patterning the second conductive thin film by a patterning process to form a second conductive layer pattern in the second insulating layer. FIG. 17D is a schematic diagram of the second conductive layer pattern in the translucent display area according to FIG. 14, and FIG. 17E is a schematic diagram after the second conductive layer pattern is formed in the translucent display area according to FIG. 14. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0259] In an exemplary embodiment, the second conductive layer pattern according to FIGS. 17D and 17E is the same as the second conductive layer pattern according to FIGS. 15D and 15E, and will not be described here.

[0260] (4) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in FIG. 17F, forming the third insulating layer pattern may include depositing a third insulating thin film on the patterned base, and patterning the third insulating thin film through a patterning process to form a third insulating layer covering the second conductive layer, and forming a plurality of vias in the third insulating layer. FIG. 17F is a schematic diagram of the transparent display area according to FIG. 14 after the third insulating layer pattern is formed.

[0261] In an exemplary embodiment, the third insulating layer pattern according to FIG. 17F is the same as the third insulating layer pattern according to FIG. 15F, and will not be described here.

[0262] (5) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 17G and 17H, forming the third conductive layer may include depositing a third conductive thin film on the patterned base and patterning the third conductive thin film through a patterning process to form a third conductive layer disposed on the third insulating layer. FIG. 17G is a schematic diagram of the third conductive layer pattern in the light-transmitting display area according to FIG. 14, and FIG. 17H is a schematic diagram of the light-transmitting display area after the third conductive layer pattern has been formed according to FIG. 14. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0263] In an exemplary embodiment, as shown in Figures 17G and 17H, the third conductive layer pattern may include a first pole T13 and a second pole T14 of the first transistor, a first pole T23 of the second transistor, a first pole T43 of the fourth transistor, a first pole T53 of the fifth transistor, a second pole T64 of the sixth transistor, a first pole T73 and a second pole T74 of the seventh transistor, a second connecting electrode VL2 to a twelfth connecting electrode VL12, and a shield electrode SL.

[0264] In the exemplary embodiment, the first pole T13 and the second pole T14 of the first transistor, the first pole T23 of the second transistor, the first pole T43 of the fourth transistor, the first pole T53 of the fifth transistor, the second pole T64 of the sixth transistor, the first pole T73 and the second pole T74 of the seventh transistor, the second connecting electrode VL2 to the eighth connecting electrode VL8, and the shield electrode according to Figures 17G and 17H have the same pattern as the first pole T13 and the second pole T14 of the first transistor, the first pole T23 of the second transistor, the first pole T43 of the fourth transistor, the first pole T53 of the fifth transistor, the second pole T64 of the sixth transistor, the first pole T73 and the second pole T74 of the seventh transistor, the second connecting electrode VL2 to the eighth connecting electrode VL8, and the shield electrode SL according to Figures 15G and 15H, and will not be described here.

[0265] In an exemplary embodiment, as shown in FIGS. 17G and 17H, the ninth connecting electrode VL9 and the twelfth connecting electrode VL12 extend along the second direction X, and at least a portion of the tenth connecting electrode VL10 and the eleventh connecting electrode VL11 extend along the second direction X.

[0266] (6) Forming a fourth insulating layer. In an exemplary embodiment, as shown in FIG. 17I, forming a fourth insulating layer pattern includes depositing a fourth insulating thin film on the patterned base, and patterning the fourth insulating thin film through a patterning process to form a fourth insulating layer covering the third conductive layer, and a plurality of vias are provided in the fourth insulating layer. FIG. 17I is a schematic diagram of the transparent display area according to FIG. 14 after the fourth insulating layer pattern is formed.

[0267] In an exemplary embodiment, as shown in Fig. 17I, the multiple vias in the fourth insulating layer pattern may all include the 17th via V17 to the 32nd via V32. The 17th via V17 to the 28th via V28 in Fig. 17 are the same as the 17th via V17 to the 28th via V28 in Fig. 15I, except that the 29th via V29 exposes the 9th connecting electrode, the 30th via V30 exposes the 10th connecting electrode, the 31st via V31 exposes the 11th connecting electrode, and the 32nd via V32 exposes the 12th connecting electrode.

[0268] In an exemplary embodiment, the number of the 29th vias V29 may be two, and the two 29th vias may be arranged along the second direction X and located at both ends of the 9th connection electrode, respectively.

[0269] In an exemplary embodiment, the number of the thirtieth vias V30 may be two, and the two thirtieth vias V30 may be arranged along the second direction X and located at both ends of the tenth connecting electrode, respectively.

[0270] In the embodiment example, the number of the 31st vias V31 may be two, and the two 31st vias V31 may be arranged along the second direction X and located at both ends of the 11th connecting electrode, respectively.

[0271] In an exemplary embodiment, the number of the 32nd vias V32 may be two, and the two 32nd vias V32 may be arranged along the second direction X and located at both ends of the 12th connection electrode, respectively.

[0272] (7) Forming a transparent conductive layer pattern. In an exemplary embodiment, as shown in Figures 17J and 17K, forming a transparent conductive layer pattern may include depositing a transparent conductive thin film on the patterned base and patterning the transparent conductive thin film through a patterning process to form a transparent conductive layer disposed on the fourth insulating layer. Figure 17J is a schematic diagram of the transparent conductive layer pattern in the light-transmitting display area according to Figure 14, and Figure 17K is a schematic diagram of the light-transmitting display area after the transparent conductive layer pattern has been formed according to Figure 14.

[0273] In an exemplary embodiment, as shown in Figures 17J and 17K, each of the transparent conductive layer patterns may include a data signal line Data, a first power supply line VDD, a first anode connecting line AL1, a second anode connecting line AL2, a third anode connecting line AL3, two sub-signal lines INIT_1 and INIT_2 of the initial signal line, two sub-signal lines RST_1 and RST_2 of the reset signal line, two sub-signal lines Gate_1 and Gate_2 of the scanning signal line, two sub-signal lines EM_1 and EM_2 of the light-emitting signal line, and a thirteenth connecting electrode VL13 to a seventeenth connecting electrode VL17.

[0274] In an exemplary embodiment, as shown in Figures 17J and 17K, the data signal line Data and the first power supply line VDD are located between two sub-signal lines of a plurality of first signal lines to which the first type pixel circuits to which the data signal line Data and the first power supply line VDD are electrically connected are electrically connected, and there may be an overlapping portion between the orthogonal projection at the base and the orthogonal projection at the base of the first type pixel circuit.

[0275] 17J and 17K, the data signal line Data may be linear, at least a portion of the data signal line Data may extend along the first direction Y, and the data signal line Data electrically connected to adjacent first-type pixel circuits located in the same column may be the same signal line. The data signal line is electrically connected to the first pole of the fourth transistor of the first-type pixel circuit electrically connected thereto through the 18th via.

[0276] 17J and 17K, the first power supply line VDD may be linear, at least a portion of the first power supply line VDD may extend along the first direction Y, and the first power supply lines VDD electrically connected to adjacent first-type pixel circuits located in the same column may be spaced apart. The first power supply line is electrically connected to the first electrode of the fifth transistor of the first-type pixel circuit electrically connected thereto through the 19th via, and is electrically connected to the shield electrode through the 28th via.

[0277] In the exemplary embodiment, as shown in FIGS. 17J and 17K, the first to fourth anode connecting lines AL1 to AL4 are polygonal lines.

[0278] In an exemplary embodiment, as shown in FIGS. 17J and 17K , the first anode connecting line AL1 is located between the first power supply line VDD and the data signal line Data of the first-type pixel circuit in the adjacent column, at least a portion of the first anode connecting line AL1 may extend along the second direction X, and the first anode connecting line AL1 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit in the adjacent column through the 20th via and electrically connected to the tenth connecting electrode through the 30th via.

[0279] In an exemplary embodiment, as shown in FIGS. 17J and 17K , the second anode connecting line AL2 is located between the first power supply line VDD and the data signal line Data of the first-type pixel circuit in the adjacent column, at least a portion of the second anode connecting line AL2 may extend along the second direction X, and the second anode connecting line AL2 is electrically connected to the second electrode of the sixth transistor of the first-type pixel circuit in the adjacent column through the 20th via and electrically connected to the 9th connecting electrode through the 29th via.

[0280] In an exemplary embodiment, as shown in Figures 17J and 17K, the third anode connecting line AL3 is located between the first power supply line VDD to which the first-type pixel circuits electrically connect and the data signal line Data to which adjacent first-type pixel circuits located in the same row are electrically connected, at least a portion of the third anode connecting line AL3 may extend along the first direction Y, and the third anode connecting line AL3 is electrically connected to the 12th connecting electrode through the 32nd via.

[0281] In an exemplary embodiment, as shown in FIGS. 17J and 17K, the two sub-signal lines INIT_1 and INIT_2 of the initial signal line may be polygonal lines, at least a portion of which extends along the first direction Y. The sub-signal line INIT_1 of the initial signal line is electrically connected to the eighth connecting electrode through the 27th via, and the sub-signal line INIT_2 of the initial signal line is electrically connected to the first pole of the first transistor through the 17th via. The sub-signal line INIT_1 of the initial signal line is electrically connected to the first connecting electrode through the 8th connecting electrode. The sub-signal line INIT_2 of the initial signal line is electrically connected to the first connecting electrode through the first pole of the first transistor.

[0282] 17J and 17K, in an exemplary embodiment, the two sub-signal lines RST_1 and RST_2 of the reset signal line may be bent-line shaped, at least a portion of the two sub-signal lines RST_1 and RST_2 of the reset signal line may extend along the second direction Y, and the sub-signal line RST_1 of the reset signal line is electrically connected to the second connecting electrode through the via 21, and the sub-signal line RST_2 of the reset signal line is electrically connected to the third connecting electrode through the via 22. The sub-signal line RST_1 of the reset signal line is electrically connected to the control electrode of the first transistor through the second connecting electrode, and the sub-signal line RST_2 of the reset signal line is electrically connected to the control electrode of the first transistor through the third connecting electrode.

[0283] 17J and 17K, in an exemplary embodiment, the two sub-signal lines Gate_1 and Gate_2 of the scanning signal line may be bent-line shaped, at least a portion of the two sub-signal lines Gate_1 and Gate_2 of the scanning signal line may extend along the second direction Y, the sub-signal line Gate_1 of the scanning signal line is electrically connected to the fourth connecting electrode through the 23rd via, and the sub-signal line Gate_2 of the scanning signal line is electrically connected to the fifth connecting electrode through the 24th via. The sub-signal line Gate_1 of the scanning signal line is electrically connected to the control electrode of the fourth transistor through the fourth connecting electrode, and the sub-signal line Gate_2 of the scanning signal line is electrically connected to the control electrode of the fourth transistor through the fifth connecting electrode.

[0284] 17J and 17K, in an exemplary embodiment, the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line may be bent-line shaped, at least a portion of the two sub-signal lines EM_1 and EM_2 of the light-emitting signal line may extend along the second direction Y, and the sub-signal line EM_1 of the light-emitting signal line is electrically connected to the sixth connecting electrode through the 25th via, and the sub-signal line EM_1 of the light-emitting signal line is electrically connected to the seventh connecting electrode through the 26th via. The sub-signal line EM_1 of the light-emitting signal line is electrically connected to the control electrode of the fifth transistor through the sixth connecting electrode, and the sub-signal line EM_2 of the light-emitting signal line is electrically connected to the control electrode of the fifth transistor through the seventh connecting electrode.

[0285] In an exemplary embodiment, as shown in Figures 17J and 17K, the 13th connection electrode VL13 is electrically connected to the 10th connection electrode through the 30th via and electrically connected to the 11th connection electrode through the 31st via.

[0286] 17J and 17K, the fourteenth connecting electrode VL14 is electrically connected to the eleventh connecting electrode through via No. 31. The thirteenth connecting electrode is electrically connected to the fourteenth connecting electrode through the first anode connecting line, the tenth connecting electrode, the thirteenth connecting electrode, and the eleventh connecting electrode.

[0287] In an exemplary embodiment, as shown in Figures 17J and 17K, the 15th connection electrode VL15 is electrically connected to the second electrode of the sixth transistor of the first type pixel circuit, which is electrically connected through the 20th via.

[0288] 17J and 17K, the sixteenth connecting electrode VL16 is electrically connected to the ninth connecting electrode through the 29th via, and the sixteenth connecting electrode is electrically connected to the second anode connecting line AL2 through the ninth connecting electrode.

[0289] 17J and 17K, the seventeenth connecting electrode VL17 is electrically connected to the twelfth connecting electrode through via No. 32. The seventeenth connecting electrode VL17 is electrically connected to the third anode connecting line AL3 through the twelfth connecting electrode.

[0290] (8) Forming a first flat layer pattern. In an exemplary embodiment, as shown in FIG. 17L, forming the first flat layer pattern may include depositing a first flat thin film on the patterned base to form a first flat layer pattern disposed on the transparent conductive layer, and the first flat layer pattern may include a plurality of vias. FIG. 17L is a schematic diagram of the transparent display area according to FIG. 14 after the first flat layer is formed.

[0291] 17L , the first flat layer pattern may include a 33rd via V33 and a 40th via V40. The 33rd via V33 exposes the first power line, the 34th via V34 exposes the first anode connecting line, the 35th via V35 exposes the 14th connecting electrode, the 36th via V36 exposes the 16th connecting electrode, the 37th via V37 exposes the second anode connecting line, the 38th via V38 exposes the 15th connecting electrode, the 39th via V39 exposes the third anode connecting line, and the 40th via V40 exposes the 17th connecting electrode.

[0292] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 17M and 17N, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the patterned base and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer disposed on the first planar layer. FIG. 17M is a schematic diagram of the fourth conductive layer pattern in the light-transmitting display area according to FIG. 14, and FIG. 17N is a schematic diagram of the light-transmitting display area according to FIG. 14 after the fourth conductive layer pattern has been formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0293] In an exemplary embodiment, as shown in FIGS. 17M and 17N, the fourth conductive layer pattern may include an eighteenth connection electrode VL18 to a twenty-third connection electrode VL23 and a signal connection line VDL.

[0294] 17M and 17N, in the exemplary embodiment, the eighteenth connection electrode VL18 to the twenty-first connection electrode VL21 and the twenty-third connection electrode VL23 have a block structure. The twenty-second connection electrode VL22 has a horizontally inverted "7" shape, and the signal connection line VDL may have a bent line shape, and at least a part of the signal connection line VDL may extend along the first direction Y.

[0295] In the exemplary embodiment, as shown in FIGS. 17M and 17N, the signal connection line VDL is electrically connected to the first power supply line through the 33rd via.

[0296] In an exemplary embodiment, as shown in Figures 17M and 17N, the 18th connecting electrode VL18 is electrically connected to the 14th connecting electrode through the 35th via, the 19th connecting electrode VL19 is electrically connected to the first anode connecting line through the 34th via, the 20th connecting electrode VL20 is electrically connected to the 16th connecting electrode through the 36th via, the 21st connecting electrode VL21 is electrically connected to the second anode connecting line through the 37th via, the 22nd connecting electrode VL22 is electrically connected to the 15th connecting electrode through the 38th via and electrically connected to the third anode connecting line through the 39th via, and the 23rd connecting electrode VL23 is electrically connected to the 17th connecting electrode through the 40th via.

[0297] In the exemplary embodiment, the first power supply lines electrically connected to the first type pixel circuits located in the same column are electrically connected via the signal connection line VDL.

[0298] In an exemplary embodiment, as shown in FIG. 17N, the 18th connecting electrode VL18 is electrically connected to the 19th connecting electrode VL19 via the 14th connecting electrode, the 11th connecting electrode, the 13th connecting electrode, the 10th connecting electrode and the first anode connecting line, the 20th connecting electrode VL20 is electrically connected to the 21st connecting electrode VL21 via the 16th connecting electrode, the 9th connecting electrode and the first anode connecting line, and the 22nd connecting electrode VL22 is electrically connected to the 23rd connecting electrode VL23 via the third anode connecting line, the 12th connecting electrode and the 17th connecting electrode.

[0299] In an exemplary embodiment, the plurality of connection electrodes serve a receiving role, which can avoid unreliable connections caused by opening deep vias, and can improve the reliability of the display panel.

[0300] (10) Forming a second flat layer pattern. In an exemplary embodiment, as shown in FIG. 17O, forming the second flat layer pattern may include applying a second flat thin film on the patterned base and patterning the second flat thin film through a patterning process to form a second flat layer covering the fourth conductive layer, and forming a plurality of vias in the second flat layer. FIG. 17O is a schematic diagram of the transparent display area according to FIG. 14 after the second flat layer pattern is formed.

[0301] 17O, the plurality of vias in the second flat layer pattern may all include the 41st via V41 to the 46th via V46. The 41st via V41 exposes the 18th connecting electrode, the 42nd via V42 exposes the 19th connecting electrode, the 43rd via V43 exposes the 20th connecting electrode, the 44th via V44 exposes the 21st connecting electrode, the 45th via V45 exposes the 22nd connecting electrode, and the 46th via V46 exposes the 23rd connecting electrode.

[0302] Up to this point, a driving circuit layer is fabricated on the base and completed. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of first-type pixel circuits, scan signal lines, reset signal lines, light-emitting signal lines, data signal lines, initial signal lines, and first to fourth anode connecting lines. In a plane perpendicular to the display panel, the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer, which are sequentially stacked on the base.

[0303] In an exemplary embodiment, the base may be a flexible base or a rigid base. The rigid base may be made of one or more of, but not limited to, glass and quartz. The flexible base may be made of, but not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and woven fabric. In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymeric flexible film. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water-oxygen resistance of the substrate. The semiconductor layer may be made of amorphous silicon (a-Si).

[0304] In one exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of one or more metal materials selected from silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of these metals such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo.

[0305] In an exemplary embodiment, the transparent conductive layer may employ, for example, indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0306] In an exemplary embodiment, the first, second, third, and fourth insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite. The first insulating layer may be called a buffer layer, the second insulating layer a gate insulating (GI) layer, the third insulating layer an interlayer dielectric (ILD) layer, and the fourth insulating layer a passivation (PVX) layer. The first and second planar layers may be made of organic materials such as resin. The semiconductor layer may be made of materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc nitride oxide (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, or polythiophene. That is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology, or organic technology.

[0307] In an exemplary embodiment, after the fabrication of the driving circuit layer is completed, a light emitting structure layer is fabricated on the driving circuit layer, and the fabrication process of the light emitting structure layer may include the following operations.

[0308] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 17P and 16Q, forming an anode conductive layer pattern may include depositing an anode conductive thin film on the patterned base, and patterning the anode conductive thin film by a patterning process to form an anode conductive layer pattern disposed on the second flat layer. FIG. 17P is a schematic diagram of the anode conductive layer pattern in the translucent display area according to FIG. 14, and FIG. 17Q is a schematic diagram of the translucent display area according to FIG. 14 after the anode conductive layer pattern has been formed.

[0309] In an exemplary embodiment, the anode conductive layer may have a single layer structure such as indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0310] In an exemplary embodiment, the anode of the first light-emitting element 11b is electrically connected to the 18th connection electrode via the 41st via, the anode of the first light-emitting element 11a is electrically connected to the 19th connection electrode via the 42nd via, the anode of the second light-emitting element 12b is electrically connected to the 20th connection electrode via the 43rd via, the anode of the second light-emitting element 12a is electrically connected to the 21st connection electrode via the 44th via, the anode of the third light-emitting element 13a is electrically connected to the 22nd connection electrode via the 45th via, and the anode of the third light-emitting element 13b is electrically connected to the 23rd connection electrode via the 46th via.

[0311] In the exemplary embodiment, the anode of the first light-emitting element 11a is electrically connected to the anode of the first light-emitting element 11b via the 18th, 14th, 11th, 13th, 10th connecting electrodes, the first anode connecting line, and the 19th connecting electrode. The anode of the second light-emitting element 12a is electrically connected to the anode of the second light-emitting element 12b via the 20th, 16th, 9th connecting electrodes, the first anode connecting line, and the 21st connecting electrode. The anode of the third light-emitting element 13a is electrically connected to the anode of the third light-emitting element 13b via the 22nd connecting electrode VL22, the third anode connecting line, the 12th connecting electrode, the 17th connecting electrode, and the 23rd connecting electrode VL23.

[0312] In an exemplary embodiment, the subsequent manufacturing process may include first forming a pixel definition layer pattern, then forming an organic light-emitting layer using a vapor deposition or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a package structure layer. The package structure layer may include a first package layer, a second package layer, and a third package layer stacked together, where the first package layer and the third package layer may be made of inorganic materials and the second package layer may be made of organic materials, and the second package layer may be disposed between the first package layer and the third package layer, thereby ensuring that external water vapor does not penetrate into the light-emitting structure layer.

[0313] The above-mentioned structure and its manufacturing process of the present disclosure are only exemplary descriptions, and in the exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or omitted according to actual needs, and the present disclosure is not limited thereto.

[0314] In an exemplary embodiment, the display panel of the present disclosure may be applied to a display device having a pixel circuit such as an OLED, a quantum dot display (QLED), a light-emitting diode display (Micro LED or Mini LED), or a quantum dot light-emitting diode display (QDLED), and the present disclosure is not limited thereto.

[0315] Fig. 18 is a structural schematic diagram of a display device according to an embodiment of the present disclosure, and Fig. 19 is a cross-sectional view taken along the line AA in Fig. 18. As shown in Fig. 18 and Fig. 19, an embodiment of the present disclosure also provides a display device, which includes a display substrate 1 and a photosensitive sensor 2 provided by any of the above embodiments, and the photosensitive sensor 2 is located within the light-transmitting display area A1 of the display substrate 1 and on the side away from the light-emitting side of the display substrate 1.

[0316] In some exemplary embodiments, the display substrate may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component having a display function, such as an OLED display, a mobile phone, a tablet, a television, a display, a laptop, a digital photo frame, or a navigation system, and the embodiments of the present disclosure are not limited thereto.

[0317] In an exemplary embodiment, when the light-transmitting display area A1 is rectangular, the orthographic area of ​​the photosensitive sensor 2 at the base is equal to or less than the area of ​​the inscribed circle of the light-transmitting display area A1.

[0318] In an exemplary embodiment, the photosensitive sensor 2 may include at least one of a camera module (e.g., a front-mounted camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), and the like.

[0319] In an exemplary embodiment, the front camera module is generally used when a user takes a selfie or makes a video call, and the display area of ​​the display device displays the image obtained by the selfie for the user to view. The front camera module includes, for example, a lens, an image sensor, an image processing chip, etc. An optical image of a scene is projected onto the surface of the image sensor (image sensors include both CCD and CMOS) by the lens, converted into an electrical signal, and then converted into a digital image signal by the image processing chip, which is then sent to a processor for processing, and the image of the scene is output to the display screen.

[0320] In an exemplary embodiment, a 3D structured light sensor and a Time of Flight sensor may be used for facial recognition to unlock the display device.

[0321] A display device according to an embodiment of the present invention can display an image in a translucent display area and maintain display integrity across the entire display device.

[0322] The drawings in the present disclosure relate only to the structures according to the embodiments of the present disclosure, and other structures may refer to the general design.

[0323] For clarity, in the figures illustrating embodiments of the present disclosure, the thicknesses and sizes of layers or microstructures are exaggerated. As will be understood, when an element such as a layer, film, region, or substrate is referred to as being located "on" or "under" another element, the element can be located "directly" "on" or "under" the other element, or intermediate elements can be present.

[0324] Although the embodiments disclosed in the present disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not used to limit the present disclosure. Those skilled in the art can make any modifications and changes in the embodiments and details without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure must comply with the scope defined by the appended claims. [Explanation of symbols]

[0325] 1 Display board 2 Photosensitive sensors 11 First light-emitting element 12 Second light-emitting element 13 Third light-emitting element 110 Light-emitting area 111 Anode 120 luminous area 121 Anode 130 Light-emitting area 131 Anode A1 Translucent display area A2 Normal display area AA display area BB surrounding area

Claims

1. A display substrate, a display area and a peripheral area at least partially surrounding the display area, the display area including a light-transmitting display area and a normal display area located on at least one side of the light-transmitting display area, and the light transmittance of the light-transmitting display area is greater than the light transmittance of the normal display area; the display substrate includes a base and a plurality of light-emitting elements and a plurality of pixel circuits located on one side of the base, the plurality of light-emitting elements including a plurality of first-type light-emitting elements located in the light-transmitting display area, the plurality of pixel circuits including a plurality of first-type pixel circuits located in the light-transmitting display area, at least one first-type pixel circuit among the plurality of first-type pixel circuits electrically connected to at least two first-type light-emitting elements emitting light of the same color, and the first-type pixel circuit configured to drive the emission of the at least two first-type light-emitting elements; A display substrate in which there is an overlap between an orthogonal projection of the at least one first-type pixel circuit on the base and an orthogonal projection of the at least one first-type light-emitting element on the base.

2. 2. The display substrate according to claim 1, wherein there is an overlap between the orthogonal projection of the at least one first-type pixel circuit on the base and the orthogonal projection of at least some of the first-type light-emitting elements among the at least two first-type light-emitting elements electrically connected to the at least one first-type pixel circuit on the base.

3. a plurality of first signal lines, wherein the at least one first-type pixel circuit is electrically connected to at least one first signal line; 3. The display substrate according to claim 1, wherein the plurality of first signal lines include at least one of a scanning signal line, a reset signal line, an initial signal line, and a light-emitting signal line.

4. 4. The display substrate according to claim 3, wherein the first signal line includes a plurality of sub-signal lines, and adjacent sub-signal lines of the first signal line are electrically connected via the first type pixel circuit that electrically connects them.

5. a plurality of second signal lines, wherein the at least one first-type pixel circuit is electrically connected to at least one second signal line; 5. The display substrate of claim 3, wherein the plurality of second signal lines include at least one of data signal lines and first power supply lines, the plurality of data signal lines and the plurality of first power supply lines extend along a first direction, the data signal lines and the first power supply lines electrically connected to the first-type pixel circuits are located between adjacent sub-signal lines of the first signal lines, and orthogonal projections of the data signal lines and the first power supply lines electrically connected to the first-type pixel circuits on the base overlap with orthogonal projections of the first-type pixel circuits on the base.

6. 6. The display substrate of claim 5, wherein the orthogonal projection of at least one of the scanning signal line, the reset signal line, the initial signal line, the light-emitting signal line, the data signal line, and the first power supply line on the base partially overlaps the orthogonal projection of the first type light-emitting element on the base.

7. the plurality of first-type light-emitting elements include at least a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light; an anode area of ​​at least one first light-emitting element among the plurality of first light-emitting elements is larger than an anode area of ​​at least one third light-emitting element among the plurality of third light-emitting elements, an anode area of ​​at least one second light-emitting element among the plurality of second light-emitting elements is larger than an anode area of ​​the at least one third light-emitting element, and an anode area of ​​at least one second light-emitting element among the plurality of second light-emitting elements is larger than an anode area of ​​at least one first light-emitting element among the plurality of first light-emitting elements; 7. The display substrate according to claim 5, wherein the first color light is red light, the second color light is blue light, and the third color light is green light.

8. the first-type pixel circuit includes a plurality of transistors and at least one capacitor; and in a direction perpendicular to the display substrate, the light-transmitting display region includes at least a semiconductor layer disposed on the base, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a transparent conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer; the semiconductor layer includes at least active layers of a plurality of transistors of the first type pixel circuit; the first conductive layer includes at least control poles of a plurality of transistors of the first type pixel circuits and first plates of capacitors; the second conductive layer includes at least a second plate of a capacitor of the first type pixel circuit; the third conductive layer includes at least first and second electrodes of a plurality of transistors of the first type pixel circuit and a plurality of connecting electrodes; the transparent conductive layer includes at least a plurality of first signal lines, a plurality of second signal lines, and a plurality of anode connecting lines, and at least one anode connecting line among the plurality of anode connecting lines is electrically connected to at least one first-type pixel circuit and an anode of at least two first-type light-emitting elements that emit light of the same color; The display substrate according to claim 7 , wherein the fourth conductive layer includes at least a plurality of signal connection lines.

9. The plurality of first-type light-emitting elements are arranged in the following manner:

9. The display substrate of claim 8, wherein the plurality of third light-emitting elements are arranged in an i-th row at regular intervals, the second light-emitting elements and the first light-emitting elements are alternately arranged in adjacent rows of the i-th row, the first light-emitting elements and the second light-emitting elements are alternately arranged in a j-th column, the plurality of third light-emitting elements are arranged in adjacent columns of the j-th column at regular intervals, the first light-emitting elements and the third light-emitting elements are alternately arranged along a third direction, and the second light-emitting elements and the third light-emitting elements are alternately arranged along a fourth direction, the third direction and the fourth direction intersect with the first direction and the second direction, respectively, the first direction is a column direction, and the second direction is a row direction.

10. 10. The display substrate of claim 9, wherein the plurality of first-type pixel circuits include at least one first pixel circuit, at least one second pixel circuit, at least one third pixel circuit, and at least one fourth pixel circuit, wherein the first pixel circuit is electrically connected to two of the first light-emitting elements, the second pixel circuit is electrically connected to two of the second light-emitting elements, the third pixel circuit is electrically connected to two of the third light-emitting elements, and the fourth pixel circuit is electrically connected to two of the third light-emitting elements, and the third pixel circuit and the fourth pixel circuit are electrically connected to different third light-emitting elements.

11. 11. The display substrate of claim 10, wherein two of the first light-emitting elements electrically connected to the first pixel circuits are located in the same row, two of the second light-emitting elements electrically connected to the second pixel circuits are located in the same row, two of the third light-emitting elements electrically connected to the third pixel circuits are located in the same row, and two of the third light-emitting elements electrically connected to the fourth pixel circuits are located in the same row.

12. an orthogonal projection of the first pixel circuit on the base partially overlaps with an orthogonal projection of one of the first light-emitting elements electrically connected thereto on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps an orthogonal projection of the first light-emitting element located between two second light-emitting elements electrically connected thereto, an orthogonal projection of the third pixel circuit on the base partially overlaps with an orthogonal projection of the second light-emitting element on the base, and the second light-emitting element overlapping with the third pixel circuit is located in a row adjacent to a row in which two of the third light-emitting elements electrically connected to the third pixel circuit are located, and is located in a middle column in which two of the third light-emitting elements electrically connected to the third pixel circuit are located; 12. The display substrate of claim 11, wherein the orthogonal projection of the fourth pixel circuit on the base partially overlaps the orthogonal projection of the second light-emitting element on the base, the second light-emitting element overlapping the fourth pixel circuit is located in a row adjacent to a row in which two of the third light-emitting elements electrically connected to the fourth pixel circuit are located and is located in an intermediate column in which two of the third light-emitting elements electrically connected to the fourth pixel circuit are located, and the second light-emitting element overlapping the third pixel circuit is a light-emitting element different from the second light-emitting element overlapping the fourth pixel circuit.

13. the anode connecting lines include a first anode connecting line, a second anode connecting line, a third anode connecting line, and a fourth anode connecting line; the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the second direction; the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the second direction; the third anode connecting line is located between a first power line and a data signal line electrically connected to the third pixel circuit; the fourth anode connecting line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connecting line extends along the second direction; and the fourth anode connecting line is located between a first power line and a data signal line electrically connected to the fourth pixel circuit.

14. first power supply lines electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced-apart first power supply lines located in the same column are electrically connected via at least one signal connection line located in the fourth conductive layer; 14. The display substrate of claim 13, wherein data signal lines electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced apart data signal lines located in the same column are electrically connected via at least one signal connecting line located in the fourth conductive layer.

15. 11. The display substrate of claim 10, wherein the two first light-emitting elements electrically connected to the first pixel circuits are arranged along a third direction, the two second light-emitting elements electrically connected to the second pixel circuits are arranged along a fourth direction, the two third light-emitting elements electrically connected to the third pixel circuits are located in the same column, and the two third light-emitting elements electrically connected to the fourth pixel circuits are located in the same column.

16. an orthogonal projection of the first pixel circuit on the base partially overlaps with an orthogonal projection of one of the first light-emitting elements electrically connected thereto on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; an orthogonal projection of the third pixel circuit on the base partially overlaps with an orthogonal projection of one of the third light-emitting elements electrically connected thereto on the base; 16. The display substrate of claim 15, wherein the orthogonal projection of the fourth pixel circuit on the base partially overlaps with the orthogonal projection of one of the third light-emitting elements electrically connected thereto, and the third light-emitting element overlapping the third pixel circuit is a light-emitting element different from the third light-emitting element overlapping the fourth pixel circuit.

17. the anode connecting lines include a first anode connecting line, a second anode connecting line, a third anode connecting line, and a fourth anode connecting line; 17. The display substrate of claim 15, wherein the first anode connecting line is electrically connected to the first pixel circuit and the first light-emitting element, respectively, and at least a portion of the first anode connecting line extends along the first direction; the second anode connecting line is electrically connected to the second pixel circuit and the second light-emitting element, respectively, and at least a portion of the second anode connecting line extends along the first direction; the third anode connecting line is electrically connected to the third pixel circuit and the third light-emitting element, respectively, and at least a portion of the third anode connecting line extends along the first direction; the third anode connecting line is located on a side of a first power supply line electrically connected to the third pixel circuit, away from a data signal line; and the fourth anode connecting line is electrically connected to the fourth pixel circuit and the third light-emitting element, respectively, and at least a portion of the fourth anode connecting line extends along the first direction; and the fourth anode connecting line is located on a side of a first power supply line electrically connected to the fourth pixel circuit.

18. 18. The display substrate of claim 17, wherein the data signal line electrically connecting the first-type pixel circuits located in the same column is the same signal line, the first power supply lines electrically connecting at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced-apart first power supply lines located in the same column are electrically connected via at least one signal connecting line located in the fourth conductive layer.

19. the transparent conductive layer further includes a power connection line, at least a portion of the power connection line extending along a second direction; 19. The display substrate of claim 18, wherein the power supply connecting lines are each electrically connected to a first power supply line that electrically connects two adjacent first-type pixel circuits located in the same row, and the first power supply line and the power supply connecting line are electrically connected via a connection electrode located in the third conductive layer.

20. For the same first type pixel circuit, the first power supply line includes a power supply main body portion extending along the first direction and a power supply connection portion extending along the second direction, the power supply connection portion being located on a side of the power supply main body away from the data signal line, 20. The display substrate of claim 19, wherein the power supply connection line is electrically connected to the power supply connection portion of one of the first type pixel circuits and the power supply main portion of the other of the first type pixel circuits located in the same row.

21. The plurality of first-type light-emitting elements are arranged in the following manner:

9. The display substrate of claim 8, wherein the plurality of second light-emitting elements are arranged in a jth column, the first light-emitting elements and the third light-emitting elements are arranged alternately in adjacent jth columns, the plurality of second light-emitting elements are arranged in an ith row, and the first light-emitting elements and the third light-emitting elements are installed between adjacent second light-emitting elements located in the same row.

22. 22. The display substrate of claim 21, wherein the plurality of first-type pixel circuits include at least one first pixel circuit, at least one second pixel circuit, and at least one third pixel circuit, wherein the first pixel circuit is electrically connected to two of the first light-emitting elements, the second pixel circuit is electrically connected to two of the second light-emitting elements, and the third pixel circuit is electrically connected to two of the third light-emitting elements.

23. 23. The display substrate of claim 22, wherein two first light-emitting elements electrically connected to the first pixel circuits are located in the same row, two second light-emitting elements electrically connected to the second pixel circuits are located in the same row, and two third light-emitting elements electrically connected to the third pixel circuits are located in the same row.

24. an orthogonal projection of the first pixel circuit on the base partially overlaps with an orthogonal projection of one of the first light-emitting elements electrically connected thereto on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; The display substrate of claim 23 , wherein the orthogonal projection of the third pixel circuit on the base partially overlaps with the orthogonal projection of one of the third light-emitting elements electrically connected thereto on the base.

25. The display substrate of claim 24 , wherein at least two of the first light-emitting element overlapping the first pixel circuit, the second light-emitting element overlapping the second pixel circuit, and the third light-emitting element overlapping the third pixel circuit are adjacent to each other.

26. an orthogonal projection of the first pixel circuit on the base partially overlaps with an orthogonal projection of one of the first light-emitting elements electrically connected thereto on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; 24. The display substrate of claim 23, wherein a plane projection of the third pixel circuit at the base partially overlaps a plane projection of the second light-emitting element located between two of the third light-emitting elements electrically connected to the third pixel circuit at the base.

27. an orthogonal projection of the first pixel circuit on the base partially overlaps with an orthogonal projection of a second light-emitting element located between two of the first light-emitting elements electrically connected to the first pixel circuit, on the base; an orthogonal projection of the second pixel circuit on the base partially overlaps with an orthogonal projection of one of the second light-emitting elements electrically connected thereto on the base; The display substrate of claim 23 , wherein the orthogonal projection of the third pixel circuit on the base partially overlaps with the orthogonal projection of one of the third light-emitting elements electrically connected thereto on the base.

28. the anode connecting lines include a first anode connecting line, a second anode connecting line, and a third anode connecting line; 28. The display substrate of claim 23, wherein the first anode connecting lines are electrically connected to the first pixel circuits and the first light-emitting elements, respectively, and at least a portion of the first anode connecting lines extends along the second direction; the second anode connecting lines are electrically connected to the second pixel circuits and the second light-emitting elements, respectively, and at least a portion of the second anode connecting lines extends along the second direction; and the third anode connecting lines are electrically connected to the third pixel circuits and the third light-emitting elements, respectively, and at least a portion of the third anode connecting lines extends along the second direction.

29. 29. The display substrate of claim 28, wherein the data signal lines electrically connected to the first-type pixel circuits located in the same column are the same signal line, the first power supply lines electrically connected to at least two adjacent first-type pixel circuits located in the same column are spaced apart, and the spaced-apart first power supply lines located in the same column are electrically connected via at least one signal connecting line located in the fourth conductive layer.

30. the plurality of light-emitting elements further include a plurality of second-type light-emitting elements located in the normal display area, and the plurality of pixel circuits further include a plurality of second-type pixel circuits located in the normal display area; 2. The display substrate of claim 1, wherein at least one second-type light-emitting element among the plurality of second-type light-emitting elements is electrically connected to at least one second-type pixel circuit among the plurality of second-type pixel circuits, and there is an overlapping portion between the orthogonal projection of the second-type light-emitting element on the base and the orthogonal projection of the second-type pixel circuit electrically connected to the second-type light-emitting element on the base.

31. A display device comprising the display substrate according to any one of claims 1 to 30.

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