optoelectronic devices

Abstract

The present disclosure relates to a pixel comprising a light emitting element (32) and a first transistor (36) coupled in series between a reference node (40) and a supply node (52), and a first circuit (106) having a first terminal coupled to a control terminal of the first transistor (36) and a second terminal coupled to the reference node (40). The first circuit (106) is configured to generate a control voltage (VGS) at the first terminal and includes variable voltage dividers (108, 110, 112, 120) configured to provide the control voltage (VGS) to the first terminal. The pixel further comprises a first switch (114) coupled between the first terminal of the first circuit and a conduction terminal of the first transistor (36).

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to optoelectronic devices, and more particularly to devices comprising pixels and their drivers. [Background technology]

[0002] An image pixel corresponds to a unit element of an image displayed by a display screen. To display a color image, a display screen generally includes at least three elements, also referred to as display subpixels, for displaying each pixel of the image, each of which emits light of a substantially single color (e.g., red, green, and blue) referred to as an image pixel color component. The image pixel color components emitted by the three display subpixels are superimposed to give a viewer a sense of color corresponding to the pixel of the displayed image. In this case, the ensemble formed by the three display subpixels used to display a pixel of the image is referred to as a display pixel of the display screen. Each display subpixel may have a light source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in an array, with each display pixel located at the intersection of a row (also called a line) and a column of the array. Each display pixel comprises, for example, a light-emitting element and associated electronic components, such as a driver. Electrodes are provided along the rows and columns for connecting each display pixel to control circuitry. Typically, each row of display pixels is selected in succession by a signal ROW sent along the row electrode, and the display pixels of the selected row are programmed to display a desired image pixel by a signal COL sent along the column electrode. Summary of the Invention [Problem to be solved by the invention]

[0004] Each generation of screen has more display pixels to provide more detailed images, but the increasing number of display pixels, and therefore the associated electronic components, creates a significant quiescent current and increases energy consumption.

[0005] One embodiment overcomes all or some of the drawbacks of known optoelectronic devices.

[0006] There is a need for optoelectronic devices that generate less quiescent current.

[0007] A more compact pixel driver is needed.

[0008] The control voltage of the transistor in the pixel needs to be optimized. [Means for solving the problem]

[0009] The embodiment is a light emitting element and a first transistor connected in series between a reference node and a supply node; a first circuit having a first terminal coupled to the control terminal of the first transistor and a second terminal coupled to the reference node; a first switch coupled between a first terminal of the first circuit and a conduction terminal of the first transistor; The pixel includes a first circuit configured to generate a control voltage at the first terminal, the first circuit having a variable voltage divider configured to provide the control voltage to the first terminal, the variable voltage divider having two capacitive branches, and a ratio between the capacitive branches being variable. Such a structure can reduce quiescent current and reduce pixel size.

[0010] According to an embodiment, the variable voltage divider comprises a first capacitor coupled between a first terminal and a second terminal of the first circuit.

[0011] According to an embodiment, the first circuit has a third terminal coupled to a node to which a data signal is applied.

[0012] According to an embodiment, the variable voltage divider comprises a second capacitor coupled between a first terminal of the first circuit and a third terminal of the first circuit.

[0013] According to an embodiment, the pixel includes a second switch coupled between a second terminal of the first circuit and a third switch coupled between the second capacitor and the third terminal of the first circuit.

[0014] According to an embodiment, the variable voltage divider includes at least one third capacitor, which is configured to be coupled between the first terminal and either the second terminal or the third terminal depending on a control voltage.

[0015] According to an embodiment, at least one third capacitor is respectively connected in series with a fourth switch, one terminal of the second capacitor is connected to a first terminal of the first circuit, a second terminal of the second capacitor is connected to a first terminal of the fourth switch, and the fourth switch has a second terminal connected to the second terminal of the first circuit and a third terminal connected to the third terminal of the first circuit.

[0016] According to an embodiment, the first circuit comprises at least two sets of second capacitors coupled in series with fourth switches controlled by different control voltages.

[0017] According to an embodiment, the first transistor and the light emitting element are connected in series with a fifth switch.

[0018] According to an embodiment, the first circuit includes a sixth switch coupled between the control terminal of the first transistor and a node to which a reset voltage is applied.

[0019] Another embodiment provides a display screen comprising a plurality of pixels as described above.

[0020] According to an embodiment, the pixels are arranged in an array, and the third terminal of each first circuit is configured to receive a voltage common to all pixels in the same row.

[0021] According to an embodiment, the light emitting element is connected to a common cathode, and the light emitting element of each pixel is connected between the first transistor of the pixel and the reference node.

[0022] Another embodiment is a method of controlling a pixel as described above, comprising the steps of: a first stage of closing the first switch and charging a capacitor of the variable voltage divider coupled between a first terminal and a second terminal of the first circuit; a second stage in which the first switch is open; The present invention provides a method comprising:

[0023] According to an embodiment, the method alternates between the first and second stages. [Brief explanation of the drawings]

[0024] The foregoing and other features and advantages are explained in more detail in the following specific embodiments, given as non-limiting examples with reference to the accompanying drawings, in which:

[0025] [Figure 1] 1A and 1B illustrate examples of optoelectronic devices. [Figure 2] FIG. 1 is a diagram illustrating an example of a pixel. [Figure 3] 3 shows a portion of the pixel of FIG. 2 in more detail according to an embodiment. [Figure 4] 4 shows a portion of the pixel of FIG. 2 in more detail according to the embodiment of FIG. 3. [Figure 5] FIG. 4 illustrates the operation of the embodiment of FIG. [Figure 6] 4 illustrates another operation of the embodiment of FIG. 3. [Figure 7] 4 illustrates another operation of the embodiment of FIG. 3. [Figure 8] 4A-4C illustrate various operations of the embodiment of FIG. 3 in more detail. [Figure 9] 3 shows a portion of the device of FIG. 2 in more detail, according to another embodiment. [Figure 10] 9A and 9B show a portion of the pixel of FIG. 2 in more detail. [Figure 11] FIG. 10 illustrates the operation of the embodiment of FIG. [Figure 12] 10 illustrates another operation of the embodiment of FIG. 9. [Figure 13] 10 illustrates another operation of the embodiment of FIG. 9. [Figure 14] FIG. 10 illustrates the operation of the embodiment of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0026] In the various drawings, like features are designated by like reference numerals, and in particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structural, dimensional, and material characteristics.

[0027] For clarity, only those operations and elements useful for understanding the embodiments described herein are shown and described in detail.

[0028] Unless otherwise indicated, when referring to two elements connected together, this refers to a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, this refers to the two elements being connected or being coupled via one or more other elements.

[0029] In the following disclosure, unless otherwise indicated, when reference is made to terms that qualify absolute positions such as "front," "back," "up," "down," "left," or "right," or relative positions such as "up," "down," "high," or "low," or terms that qualify orientations such as "horizontal" or "vertical," this refers to the orientation shown in the drawings.

[0030] Unless otherwise specified, the terms "about," "approximately," "substantially," and "to the extent" refer to within 10%, preferably within 5%, of the relevant value.

[0031] FIG. 1 illustrates an example of an optoelectronic device 10 .

[0032] The device 10 includes a screen 12. The screen 12 is configured to project, for example, light, an image, or a video. The screen includes an array of pixels 14. The screen 12 may have, for example, at least 1 million pixels, for example, at least 2 million pixels, for example, at least 8 million pixels. The screen includes 16 rows of pixels 14 and 18 columns of pixels 14.

[0033] The device 10 further comprises a row control circuit or driver 20 and a column control circuit or driver 22. The row control circuit 20 is configured to provide a row voltage ROW, i.e., a common control voltage for all pixels in a row. Similarly, the column control circuit 22 is configured to provide a column voltage COL, i.e., a common control voltage for all pixels in a column. For example, the voltage ROW corresponds to a line select and a clock signal for an illumination mode, e.g., a pulse width modulation (PWM) mode. For example, the voltage COL corresponds to illumination data, e.g., video data.

[0034] Device 10 includes a controller 24 configured to provide data to row control circuitry 20 and column control circuitry 22 to generate, for example, voltages ROW and COL. Controller 24 may further provide clock signals to row control circuitry 20 and column control circuitry 22 and ultimately to pixels 14. Controller 24 may be, for example, a timing controller.

[0035] 2 shows a schematic representation of an embodiment of pixel 14. Pixel 14 has region 26 and region 30.

[0036] Region 26 includes at least one light-emitting element. For example, the light-emitting element is referred to as a light-emitting diode in the remainder of the specification. However, the light-emitting element can be any type of light-emitting component. Region 26 includes, for example, three light-emitting diodes: one configured to provide blue light, one configured to provide green light, and one configured to provide red light.

[0037] Region 30 is, for example, a pixel driver. Region 30 includes analog and digital circuits. Region 30 includes peripheral circuits. Region 30 includes, for example, power supply circuits configured to provide supply voltages for the pixels. Region 30 includes, for example, control logic.

[0038] For example, each pixel has only four input pads, not shown, in other words, each pixel receives only four external voltages: a supply voltage, a reference voltage, e.g., ground GND, a signal ROW transmitted along a row electrode, and a signal COL transmitted along a column electrode.

[0039] Figure 3 shows in more detail a portion of pixel 14 of Figure 2 according to an embodiment. In the example of Figure 3, the pixel is configured to be connected to other pixels with a common anode.

[0040] The pixel 14 includes a light-emitting diode 32. The light-emitting diode 32 is connected in series with a transistor 36 and a switch 38 between a node 52, to which the pixel's supply voltage VCC is applied, and a node 40, to which a reference voltage, e.g., ground GND, is applied. The transistor 36 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), e.g., a p-channel transistor. The transistor 36 has a control terminal, e.g., a gate, and two conductive terminals, e.g., a drain and a source. The switch 38 has two terminals 48 and 50.

[0041] Light-emitting diode 32, switch 38, and transistor 36 are connected in series between node 52 and node 40. Light-emitting diode 32, transistor 36, and switch 38 are connected so that light-emitting diodes of different pixels can be connected to a common anode. Light-emitting diode 32 is connected between node 52 and switch 38. In other words, the anode of light-emitting diode 32 is connected, preferably connected, to node 52, and the cathode of light-emitting diode 32 is connected, preferably connected, to terminal 48 of switch 38. Terminal 50 of switch 38 is connected to node 40 by transistor 36. In other words, terminal 50 of switch 38 is connected, preferably connected, to node 105, which is connected, preferably connected, to a conductive terminal, e.g., the drain of transistor 36, and the other conductive terminal, e.g., the source, of transistor 36 is connected, preferably connected, to node 40.

[0042] The control terminal of transistor 36 is coupled, preferably connected, to a circuit 106 configured to generate a voltage VGS.

[0043] The circuit 106 comprises a variable capacitive voltage divider, in other words a voltage divider in which the ratio between the two capacitive branches is variable.

[0044] The voltage divider, and therefore circuit 106, includes a capacitor 108. The capacitance of capacitor 108 is preferably constant. Capacitor 108 is coupled between the control terminal of transistor 36 and node 40. A first terminal of capacitor 108 is coupled, preferably connected, to node 109, which is coupled, preferably connected, to the control terminal of transistor 36. A second terminal of capacitor 108 is coupled, preferably connected, to node 40.

[0045] The control terminal of transistor 36 is further coupled to node 118, to which is applied voltage ROW1, which is generated from voltage ROW. The control terminal of transistor 36 is coupled to node 118 by capacitor 120, which preferably has a constant capacitance. More precisely, the control terminal of transistor 36 is coupled, preferably connected, to a terminal of capacitor 120. In other words, said terminal of capacitor 120 is coupled, preferably connected, to node 109. Another terminal of capacitor 120 is coupled, preferably connected, to node 118.

[0046] The voltage divider further includes at least one capacitor 110 coupled in parallel with either capacitor 108 or capacitor 120 in response to a control signal. The capacitance of capacitor 110 is, for example, constant. The capacitances of capacitors 110 are, for example, substantially equal.

[0047] In the example of Figure 3, the voltage divider has three capacitors 110 (110a, 110b, 110c). In general, the number of capacitors 110 is application dependent.

[0048] Each capacitor 110 is coupled in series with a switch 112. In other words, capacitor 110a is coupled in series with switch 112a, capacitor 110b is coupled in series with switch 112b, and capacitor 110c is coupled in series with switch 112c.

[0049] One terminal of each capacitor 110 is coupled, preferably connected, to node 109. Another terminal of each capacitor 110 is coupled, preferably connected, to an input terminal of a corresponding switch 112. Each switch 112 has a first output terminal coupled, preferably connected, to node 40 and a second output terminal coupled, preferably connected, to node 118. Each switch 112 is configured to connect the corresponding capacitor 110 to either node 40 or node 118 in response to a control voltage. Each switch 112 is preferably controlled by its own control voltage, e.g., independently of the control voltages of the other switches 112.

[0050] The value of voltage VGS is therefore determined by the control voltage of switch 112, which determines the ratio of the capacitances of the two branches of the voltage divider.

[0051] Circuit 106 further includes a switch 114 coupled between node 109 and node 105. Circuit 106 further includes a switch 115 coupled between node 109 and a node 111 to which a reset voltage VRS is applied.

[0052] Switch 115 has a control terminal that is, for example, coupled, preferably connected, to a node to which control voltage SW1 is applied. Switch 115 is configured to be used to reset the voltage divider. Switch 114 has a control terminal that is, for example, coupled, preferably connected, to a node to which control voltage SW2 is applied.

[0053] The control terminal of switch 38 is, for example, coupled, preferably connected, to a node to which a control voltage SW3 is applied.

[0054] The circuit of FIG. 3 may, for example, undergo a calibration step, in which a known value of capacitance is applied to the branch of the voltage divider. The capacitor connected between node 109 and node 40 is charged, and voltage CTL (not shown in FIG. 3) has a first value. Voltage CTL then assumes a second value, and voltage VGS determined by the capacitive voltage divider is applied to transistor 36. The LED then illuminates according to known data. The brightness of the LED is measured and compared with the desired brightness. The value of the control voltage of switch 112 is changed depending on the difference between the desired brightness and the measured brightness. The brightness of the LED is measured again. To further correct the value of the brightness of the LED, a calibration step may, for example, be applied again.

[0055] Figure 4 shows in more detail an implementation of a part of the pixel of Figure 2 according to the embodiment of Figure 3. More precisely, Figure 4 shows a circuit 200 for generating the control voltages SW1, SW2 and SW3.

[0056] The control voltages SW1, SW2 and SW3 are derived from the signal ROW, the voltage CTL and the voltage PWM-D.

[0057] The voltage CTL indicates that the driver is in PWM mode. In other words, the voltage CTL is, for example, a binary value, taking one value when the driver is in PWM mode and another value when the driver is in video data writing mode. The voltage PWM-D corresponds, for example, to a binary signal. The voltage PWM-D corresponds to data in PWM mode.

[0058] Circuit 200 has input node 202 configured to receive signal ROW, input node 204 configured to receive voltage CTL, and input node 206 configured to receive signal PWM-D. Circuit 200 has output node 208 having voltage SW1 applied thereto, output node 210 having voltage SW2 applied thereto, and output node 212 having voltage SW3 applied thereto.

[0059] Circuit 200 includes a logic gate NAND 214. A first input of logic gate 214 is coupled, preferably connected, to node 204. A second input of logic gate 214 is coupled, preferably connected, to node 202 through an inverter 216. In other words, the input of inverter 216 is coupled, preferably connected, to node 202, and the output of inverter 216 is coupled, preferably connected, to the second input of logic gate 214.

[0060] Circuit 200 includes logic gate AND 218. The output of logic gate 218 is coupled, preferably connected, to node 212. A first input of logic gate 218 is coupled, preferably connected, to node 206. A second input of logic gate 218 is coupled, preferably connected, to the output of logic gate 214.

[0061] Circuit 200 includes logic gate NOR 220. The output of logic gate 220 is coupled, preferably connected, to node 210. A first input of logic gate 220 is coupled, preferably connected, to the output of logic gate 214. A second input of logic gate 220 is coupled to node 222. Node 222 is coupled to the output of logic gate 214 by delay circuit 224. In other words, one terminal of delay circuit 224 is coupled, preferably connected, to the output of logic gate 214, and the other terminal of delay circuit 224 is coupled, preferably connected, to node 222.

[0062] Circuit 200 includes logic gate NOR 226. The output of logic gate 226 is coupled, preferably connected, to node 208. A first input of logic gate 226 is coupled, preferably connected, to the output of logic gate 214. A second input of logic gate 226 is coupled, preferably connected, to node 222 through inverter 228. In other words, the input of inverter 228 is coupled, preferably connected, to node 222, and the output of inverter 228 is coupled, preferably connected, to the second input of logic gate 226.

[0063] Figures 5, 6 and 7 show the successive steps of the pixel operation. Figures 5 and 6 show the driver refresh. Figure 7 shows the PWM mode. Refresh is preferably applied periodically during PWM driving of the pixel, e.g. before all data is sent.

[0064] Figure 5 illustrates the operation of the embodiment of Figure 3. More precisely, Figure 5 illustrates the reset step.

[0065] During this step, control voltages SW1, SW2 and SW3 are such that switch 115 is closed, switch 114 is open and switch 38 is open. Thus, the voltage at the gate of transistor 36 is substantially equal to the reset value VRS.

[0066] Figure 6 illustrates another operation of the embodiment of Figure 3. Figure 6 illustrates the programming steps.

[0067] During this step, control voltages SW1, SW2 and SW3 are such that switch 115 is open, switch 114 is closed and switch 38 is open. Thus, the voltage at the gate of transistor 36 is substantially equal to the threshold voltage Vth of transistor 36.

[0068] Figure 7 shows another operation of the embodiment of Figure 3. This operation corresponds to the PWM mode.

[0069] During this step, control voltages SW1, SW2, and SW3 are such that switch 115 is open and switch 114 is open. Switch 38 opens and closes in response to PWM data. The voltage at the gate of transistor 36 is determined by signal ROW1.

[0070] Figure 8 shows in more detail various operations of the embodiment of Figure 3. More precisely, Figure 8 shows signal ROW1, voltage CTL, control voltage SW1, control voltage SW2 and control voltage SW3 during the PWM mode (A) and the video data writing mode (B).

[0071] During the video data write mode (B), the voltage CTL is at a low value, which indicates that the pixel is not in PWM mode in this example. Furthermore, the voltages SW1, SW2, and SW3 have high, high, and low values, respectively. The switches 115, 114, and 38 are open. The signal ROW1 corresponds to a clock signal for writing data received on the signal COL.

[0072] PWM mode (A) has alternating periods (C) and (D).

[0073] During each period (D), the light-emitting element 32 illuminates in response to at least one data, for example, one data. Each period (D) corresponds to a step in FIG. 7. Therefore, voltages SW1 and SW2 both have high values, corresponding to an open state. Voltage SW3 is a voltage that causes the switch 38 to open or close in response to the programmed illumination of the pixel. Voltage CTL has a high value indicating PWM mode. Signal ROW1 has a high value.

[0074] Period (C) corresponds to driver refresh, or in other words, the successive steps of Figures 5 and 6. During the beginning of period (C), or in other words, during the steps of Figure 5, signal ROW1 has a low value, voltage CTL has a high value, voltage SW1 has a low value, voltage SW2 has a high value, and voltage SW3 has a low value. During the remainder of period (C), or in other words, during the steps of Figure 6, signal ROW1 has a low value, voltage CTL has a high value, voltage SW1 has a high value, voltage SW2 has a low value, and voltage SW3 has a low value.

[0075] Preferably, the periods (C) have the same duration. The periods (D) have, for example, the same duration. Alternatively, the periods (D) are binary weighted periods. In other words, a certain duration of the periods (D) is equal to 1 / (2 n ) times the maximum duration of the periods (D), where n is a positive integer value. Alternatively, the periods (C) occur, for example, periodically in the PWM mode (A).

[0076] FIG. 9 shows a portion of the device of FIG. 2 in more detail according to another embodiment.

[0077] The embodiment of FIG. 9 differs from the embodiment of FIG. 3 in that a switch 230 and a switch 232 are provided in the embodiment of FIG.

[0078] Switch 230 is coupled in series with capacitor 120 between node 109 and node 118. In other words, one terminal of capacitor 120 is coupled, preferably connected, to node 109, and the other terminal of capacitor 120 is coupled, preferably connected, to node 234. One terminal of switch 230 is coupled, preferably connected, to node 234, and the other terminal of switch 230 is coupled, preferably connected, to node 118.

[0079] Switch 232 is coupled between node 40 and node 234. In other words, one terminal of switch 232 is coupled, preferably connected, to node 234, and another terminal of switch 232 is coupled, preferably connected, to node 40.

[0080] Switch 230 and switch 232 are configured to have opposite states. In other words, when one of switch 230 and switch 232 is open, the other is closed. Switch 230 has a control terminal configured to receive control voltage SW4. Switch 232 has a control terminal configured to receive control voltage SW4'. Control voltage SW4 and control voltage SW4' are, for example, complementary binary voltages. Voltage SW4 is, for example, equal to voltage CTL.

[0081] Figure 10 shows in more detail a part of the pixel of Figure 2 according to the embodiment of Figure 9. More precisely, Figure 10 shows a circuit 200 for generating control voltages SW1, SW2 and SW3.

[0082] The control voltages SW1, SW2 and SW3 are derived from the signal ROW, the voltage CTL and the voltage PWM-D.

[0083] Circuit 200 has an input node 202' configured to receive signal ROW, an input node 204' configured to receive voltage CTL, and an input node 206' configured to receive signal PWM-D. Circuit 200 has output nodes 208' to which voltage SW1 is applied, 210' to which voltage SW2 is applied, and 212' to which voltage SW3 is applied.

[0084] Circuit 200 includes a logic gate NAND 214'. A first input of logic gate 214' is coupled, preferably connected, to node 204'. A second input of logic gate 214' is coupled, preferably connected, to node 202' via inverter 216'. In other words, the input of inverter 216' is coupled, preferably connected, to node 202', and the output of inverter 216' is coupled, preferably connected, to the second input of logic gate 214'.

[0085] Circuit 200 includes a logic gate AND 218'. The output of logic gate 218' is coupled, preferably connected, to node 212'. A first input of logic gate 218' is coupled, preferably connected, to node 206'. A second input of logic gate 218' is coupled, preferably connected, to the output of logic gate 214'.

[0086] Circuit 200 includes a logic gate NOR 220'. The output of logic gate 220' is coupled, preferably connected, to node 210'. A first input of logic gate 220' is coupled, preferably connected, to node 204'. A second input of logic gate 220' is coupled to node 222'. Node 222' is coupled to node 204' by delay circuit 224'. In other words, one terminal of delay circuit 224' is coupled, preferably connected, to node 204', and the other terminal of delay circuit 224' is coupled, preferably connected, to node 222'.

[0087] Circuit 200 includes a logic gate NOR 226'. The output of logic gate 226' is coupled, preferably connected, to node 208'. A first input of logic gate 226' is coupled, preferably connected, to node 204'. A second input of logic gate 226' is coupled, preferably connected, to node 222' via inverter 228'. In other words, the input of inverter 228' is coupled, preferably connected, to node 222', and the output of inverter 228' is coupled, preferably connected, to the second input of logic gate 226'.

[0088] 11, 12 and 13 show successive steps in the operation of a pixel.

[0089] Figure 11 illustrates the operation of the embodiment of Figure 9. More precisely, Figure 11 illustrates the reset step.

[0090] During this step, control voltages SW1, SW2, SW3 and SW4 are such that switches 38, 114 and 230 are open and switches 115 and 232 are closed. Thus, the voltage at the gate of transistor 36 is substantially equal to the reset value VRS.

[0091] Figure 12 illustrates another operation of the embodiment of Figure 9. Figure 12 illustrates the programming steps.

[0092] During this step, control voltages SW1, SW2, SW3 and SW4 are such that switches 38, 115 and 230 are open and switches 114 and 232 are closed. Thus, the voltage at the gate of transistor 36 is substantially equal to the value Vth of transistor 36.

[0093] Figure 13 shows another operation of the embodiment of Figure 9. This operation corresponds to the PWM mode.

[0094] During this step, control voltages SW1, SW2, SW3, and SW4 are such that switches 114, 115, and 232 are open and switch 230 is closed. Switch 38 opens and closes in response to PWM data. The voltage at the gate of transistor 36 is determined by signal ROW1.

[0095] Figure 14 shows the operation of the embodiment of Figure 9. More precisely, Figure 14 shows the signal ROW1, the voltage CTL, in other words, the control voltages SW4, SW1, SW2 and SW3 during the PWM mode (A) and the video data write mode (B).

[0096] During PWM mode, control voltages SW1 and SW2 are maintained at high values. In other words, switches 115 and 114 are both closed. Voltage CTL, or voltage SW4, is maintained at high values. Therefore, switches 230 and 232 remain closed and open, respectively, during PWM mode. Signal ROW remains low during period (C) and high during period (D). Period (C) occurs periodically, for example, during PWM mode (A). During period (C), voltage SW3 is maintained at a low value, corresponding to the open state of switch 38. During period (D), voltage SW3 alternates between high and low values ​​depending on the desired illumination of the pixel.

[0097] The PWM mode (A) has alternating periods (C) and (D). In the operation of the pixel, the PWM mode (A) and the data writing mode (B) alternate.

[0098] The data write mode has a first period (E) followed by a second period (F). The first period (E) corresponds to the start stage of the data write mode.

[0099] During the first period (E), the signal ROW, the voltage CTL, the voltage SW1, and the voltage SW3 are maintained at low values, and the voltage SW2 is maintained at high value.

[0100] During the second period (F), voltage CTL has a low value, which in this example indicates that the pixel is not in PWM mode. Furthermore, voltages SW1, SW2, and SW3 have high, high, and low values, respectively. Switches 115 and 38 are open. Switch 114 is closed. Signal ROW1 corresponds to a clock signal for writing data received on signal COL.

[0101] An advantage of the described embodiment is that the control circuitry for transistor 36 is simplified, less expensive and smaller, especially the analog portion of each pixel is reduced.

[0102] Another advantage of the described embodiment is that the control circuit is a passive device, reducing quiescent current.

[0103] Another advantage of the described embodiment is that the voltage VGS is generated based on the voltages ROW and COL.

[0104] Another advantage of the described embodiment is that the voltage VGS can be easily optimized and thus each pixel can be calibrated independently.

[0105] An advantage of the above-described embodiment is that it is possible to vary the capacitance value of the capacitive voltage divider for each pixel. The capacitive voltage divider can be used to calibrate the pixels, for example, by trimming, thereby compensating for variations in pixel-to-pixel efficiency. By individually correcting the pixels, all pixels can emit the same level of light. Non-variable capacitive voltage dividers, such as those disclosed in U.S. Patent Application Publication No. 2017 / 0084220, do not provide this uniformity because they do not allow for individual calibration of the pixels. In fact, it is not possible to apply different variable voltages to the input of the voltage divider for each pixel. Typically, display pixels are distributed in an array, and multiple pixels, e.g., all pixels in a line of a display pixel array, receive the same signal, so the voltage applied to the voltage divider is the same for multiple pixels, e.g., all pixels in a line of a display pixel array.

[0106] Various embodiments and variations have been described, and those skilled in the art will understand that certain features of these embodiments can be combined and that other variations will readily occur to those skilled in the art.

[0107] Finally, the actual implementation of the embodiments and variations described herein is within the skill of one skilled in the art based on the functional representations given above. In particular, there are multiple ways to implement a capacitive voltage divider with two capacitive branches, where the ratio between the two capacitive branches is variable, and the voltage divider is configured to ensure that the division ratio between the two capacitive branches is changed by changing the capacitance value of at least one of the capacitive branches. An example of such a voltage divider 106 is described herein. However, this description of such a voltage divider is not limiting, and one skilled in the art can conceive of capacitive voltage dividers with the same functional characteristics but different implementations.

[0108] This application claims priority from French Patent Application No. 2209863, the contents of which are incorporated herein by reference to the fullest extent permitted by law.

Claims

1. a light emitting element (32) and a first transistor (36) connected in series between a reference node (40) and a supply node (52); a first circuit (106) having a first terminal coupled to the control terminal of the first transistor (36) and a second terminal coupled to the reference node (40); a first switch (114) coupled between a first terminal of the first circuit and a conductive terminal of the first transistor (36); It is equipped with the first circuit is configured to generate a control voltage (VGS) at the first terminal, and includes a variable voltage divider (108, 110, 112, 120) configured to provide the control voltage (VGS) at the first terminal, the variable voltage divider having two capacitive branches, and a ratio between the capacitive branches is variable.

2. 2. The pixel of claim 1, wherein the variable voltage divider comprises a first capacitor (108) coupled between a first terminal and a second terminal of the first circuit (106).

3. 3. The pixel according to claim 1 or 2, wherein the first circuit has a third terminal (118) coupled to a node to which a data signal (ROW) is applied.

4. 4. The pixel of claim 3, wherein the variable voltage divider comprises a second capacitor (120) coupled between a first terminal of the first circuit (106) and a third terminal (118) of the first circuit.

5. 5. The pixel of claim 4, further comprising a second switch (232) coupled between the second terminal of the first circuit and a third switch (230) coupled between the second capacitor and the third terminal of the first circuit.

6. the variable voltage divider includes at least one third capacitor (110a, 110b, 110c); 6. The pixel of claim 3, wherein the third capacitor is configured to be coupled between the first terminal and either the second terminal or the third terminal in response to a control voltage (CTL).

7. At least one third capacitor is connected in series with each of the fourth switches (112a, 112b, 112c), one terminal of the second capacitor is coupled to a first terminal of the first circuit; a second terminal of the second capacitor coupled to a first terminal of the fourth switch; 7. The pixel of claim 6, wherein the fourth switch has a second terminal coupled to the second terminal of the first circuit and a third terminal coupled to the third terminal of the first circuit.

8. 8. The pixel of claim 7, wherein the first circuit comprises at least two collections of second capacitors coupled in series with fourth switches controlled by different control voltages.

9. The pixel of any one of claims 1 to 8, wherein the first transistor (36) and the light emitting element (32) are coupled in series with a fifth switch (38).

10. 10. The pixel of claim 1, wherein the first circuit comprises a sixth switch (115) coupled between a control terminal of the first transistor (36) and a node to which a reset voltage is applied.

11. A display screen comprising a plurality of pixels according to any one of claims 1 to 10.

12. The pixels are arranged in an array, 12. A display screen according to claim 11, wherein the third terminal (118) of each first circuit is adapted to receive a voltage common to all pixels of the same row.

13. The light emitting element is connected to a common cathode, 13. A display screen according to claim 11 or 12, wherein the light emitting element (32) of each pixel is coupled between the first transistor (36) of the pixel and the reference node (40).

14. A method for controlling a pixel according to any one of claims 1 to 10, comprising: a first step of closing the first switch (114) and charging a capacitor of the variable voltage divider coupled between the first terminal and the second terminal of the first circuit; a second stage in which the first switch (120) is open; A method comprising:

15. 15. The method of claim 14, wherein the first stage and the second stage alternate.

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