Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device, the display substrate including a driving circuit layer, a first scan line and a second scan line, the driving circuit layer including pixel units arranged in an array, each pixel unit including a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit, the pixel driving circuit including a first transistor and a second transistor, the active pattern of the first transistor including a first channel region, the active pattern of the second transistor including a second channel region, the first channel region located on a side of the first scan line away from the second scan line, and the second channel region located on a side of the second scan line away from the first scan line.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. [Background technology]

[0002] With the development of display technology, the range of applications for display products is becoming wider and wider, and display products with high resolution and high refresh rates are becoming increasingly popular. However, medium and large display products cannot achieve the high refresh rate function due to the heavy load. Summary of the Invention

[0003] The following provides a brief summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] In one aspect, the present disclosure provides a display substrate, the display substrate comprising: A substrate; a driving circuit layer including pixel units arranged in an array, at least one of the pixel units including a plurality of sub-pixels, at least one of the sub-pixels including a pixel driving circuit, the pixel driving circuit including a light emitting element, a plurality of transistors and a storage capacitor, the plurality of transistors including a first transistor and a second transistor, the first transistor and the second transistor being coupled; a plurality of scanning lines including first scanning lines and second scanning lines, the first scanning lines and the second scanning lines extending along a first direction and sequentially arranged along a second direction, the first direction being an extension direction of the sub-pixel rows and the second direction being an extension direction of the sub-pixel columns; Here, the plurality of transistors include active patterns, and the active pattern of each of the transistors includes a channel region and a conductive region, the active pattern of the first transistor includes a first channel region, and the active pattern of the second transistor includes a second channel region, the first channel region is located on a side of the first scan line away from the second scan line, and the second channel region is located on a side of the second scan line away from the first scan line.

[0005] Optionally, the display substrate further includes a plurality of signal lines, the plurality of signal lines including a first signal line and a second signal line; the first signal line is coupled to a first pole of the first transistor, the second signal line is coupled to a first pole of the second transistor, and the first transistor T1 is configured to transmit a voltage signal on the first signal line to a second pole of the first transistor under control of a first scan line signal; the second transistor is configured to transmit a voltage signal on a second signal line to a second pole of the second transistor under control of the second scan line signal; The second pole of the first transistor and the second pole of the second transistor are coupled to a first node.

[0006] Optionally, the plurality of scanning lines further includes a third scanning line, and the plurality of signal lines further includes a power supply line; the third scan line includes a first branch scan line extending in the first direction and a second branch scan line extending in the second direction, the first branch scan line and the second branch scan line being coupled together; the plurality of transistors further includes a third transistor and a drive transistor; the storage capacitor includes a first electrode plate and a second electrode plate; a second electrode of the third transistor, a gate of the driving transistor, and a first electrode of the storage capacitor are coupled to a second node, a gate of the third transistor is coupled to the third scan line, a first electrode of the third transistor is coupled to the first node, and the third transistor is configured to transmit a voltage signal of the first node to the second node under control of the third scan line signal; In the sub-pixels in the same row, the first branch scanning line is located on the side of the first scanning line that is farther away from the second scanning line.

[0007] Optionally, the plurality of transistors further include a fourth transistor and a fifth transistor, the plurality of scan lines further include a light emitting scan line and a fourth scan line, and the plurality of signal lines further include a third signal line; the light-emitting scanning lines extend along the first direction, a gate of the fourth transistor is coupled to the emission scan line, a first pole of the fourth transistor is coupled to the power supply line, a second pole of the fourth transistor is coupled to the first pole of the driving transistor, and the fourth transistor is configured to transmit a voltage signal from the power supply line to the second pole of the driving transistor under control of an emission scan line signal; A gate of the fifth transistor is coupled to the fourth scan line, a first pole of the fifth transistor is coupled to the third signal line, and a second pole of the fifth transistor is coupled to the light-emitting element, and the fifth transistor is configured to transmit a voltage signal of the third signal line to the light-emitting element under the control of the fourth scan line signal.

[0008] Optionally, the power supply lines include a first power supply line extending along the first direction and a second power supply line extending along the second direction, the first power supply line and the second power supply line are coupled together, and in the sub-pixels of the same row, the first power supply line is located on a side of the light emitting scan line that is farther away from the first scan line; the third signal line includes a first sub-line extending along the first direction and a second sub-line extending along the second direction, the first sub-line and the second sub-line being coupled to each other; the fourth scanning line extends along the first direction, and in the sub-pixels of the same row, the fourth scanning line is located on a side of the first power supply line that is farther away from the light emitting scanning line; The first sub-line is located on the side of the fourth scan line that is away from the first scan line.

[0009] Optionally, the pixel driving circuits of the plurality of sub-pixels form M sub-pixel rows and N sub-pixel columns, where M and N are positive integers greater than or equal to 1, and at least two sub-pixels located in the same column are coupled to the same first signal line.

[0010] Optionally, the display substrate further comprises a plurality of control regions, each of the control regions comprising at least one repeat unit; The third scan lines are respectively coupled to the gates of the third transistors included in each of the repeat units, and are used to control the on or off of the third transistors included in each repeat unit in the corresponding control region.

[0011] Along the first direction, within the same control region, the first branch scanning lines coupled to the sub-pixels in the repeat unit are coupled, and the first branch scanning lines are disconnected between the control regions.

[0012] Optionally, the orthogonal projection of the second power supply line onto the substrate and the orthogonal projection of the first branch scanning line onto the substrate do not overlap.

[0013] Optionally, there is an overlap region between the orthogonal projection of the first power supply line onto the substrate and the orthogonal projection of the second branch scan line onto the substrate.

[0014] Optionally, in a direction perpendicular to the substrate, the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are sequentially disposed on the substrate; the active layer includes active patterns of the plurality of transistors, the active patterns including channel regions and conductive regions; the first conductive layer includes gates of the plurality of transistors, a second branch scan line, and a second sub-line; the second conductive layer includes a second plate of the storage capacitor; the third conductive layer includes the first scan line, the second scan line, the first branch scan line, the light emitting scan line, the fourth scan line, the second signal line, the first power supply line, and the first sub-line; The fourth conductive layer includes the first signal line and the second power line.

[0015] Optionally, the spacing between the second signal line and the second scan line is equal to or greater than the spacing between the first scan line and the second scan line.

[0016] Optionally, an interlayer insulating layer is disposed between the second conductive layer and the third conductive layer, the interlayer insulating layer includes a first via structure, and the first via structure includes a first via and a second via; an orthogonal projection of the gate of the first transistor onto the substrate and an orthogonal projection of the first scan line onto the substrate at least partially overlap each other to form a first overlap region, and an orthogonal projection of the first via onto the substrate is located in the first overlap region; an orthogonal projection of the gate of the second transistor onto the substrate and an orthogonal projection of the second scan line onto the substrate at least partially overlap each other to form a second overlap region, and an orthogonal projection of the second via onto the substrate is located in the second overlap region; The distance between the first via and the second via is greater than the distance between the first scan line and the second scan line.

[0017] Optionally, the first branch scanning line includes a first connection portion, and in the sub-pixels of the same row, the first connection portion is located on a side of the first branch scanning line that is farther away from the light-emitting scanning line; The first via structure includes a ninth via, the second branch scan line is coupled to the first branch scan line through the ninth via, and the orthogonal projection of the ninth via onto the substrate is located within the orthogonal projection of the first connection portion onto the substrate.

[0018] Optionally, the first plate of the storage capacitor includes a first sub-plate and a second sub-plate, the first sub-plate being located on the first conductive layer, the second sub-plate being located on the third conductive layer, and the third conductive layer including a second connection portion; the first via structure includes a 15th via and a 16th via, the second sub-plate is coupled to the first sub-plate through the 15th via, and the second sub-plate is coupled to the second node through the 16th via; The orthogonal projections of the 15th via and the 16th via onto the substrate are located within the orthogonal projection of the second connection portion onto the substrate.

[0019] optionally, a first organic layer on a side of the third conductive layer away from the substrate, the first organic layer including a second via structure, the first via structure including a twelfth via, and the second via structure including an eighteenth via; the first signal line is coupled to a first electrode of the first transistor through the twelfth via and the eighteenth via, and there is an overlap region between orthogonal projections of the eighteenth via and the twelfth via onto the substrate; The third conductive layer further includes a third connection portion, and the orthogonal projection of the third connection portion onto the substrate covers the orthogonal projections of the 18th via and the 12th via onto the substrate.

[0020] Optionally, the second via structure includes a twentieth via, and the second power line is coupled to the first power line through the twentieth via; the first power supply line includes a fourth connection portion, and in the sub-pixels in the same row, the fourth connection portion is located on a side of the first power supply line closer to the fourth scan line; The orthogonal projection of the twentieth via onto the substrate partially overlaps with the orthogonal projection of the fourth connection portion onto the substrate.

[0021] Optionally, the width of the 20th via along the first direction is smaller than the width along the second direction.

[0022] Optionally, the light-emitting element layer is located on a side of the fourth conductive layer away from the substrate, the light-emitting element layer including a first electrode layer, a pixel defining layer, a light-emitting functional layer and a second electrode layer, and the first electrode layer includes a plurality of first electrodes corresponding one-to-one to the plurality of sub-pixels.

[0023] Optionally, a second organic layer is included on the side of the fourth conductive layer away from the substrate, the second organic layer includes a fourth via structure, the fourth via structure includes a 21st via, and the plurality of first electrodes are coupled to the seventh connection portion through the 21st via, and further realize coupling with a second plate of the storage capacitor and a second electrode of the driving transistor.

[0024] Optionally, the fourth conductive layer further includes an auxiliary electrode, the auxiliary electrode includes an eighth connection portion, and the eighth connection portion is located to the left of the auxiliary electrode in a plan view.

[0025] Optionally, the pixel definition layer includes a first pixel definition layer and a second pixel definition layer, the first pixel definition layer is arranged along the first direction and extends along the second direction, the first pixel definition layer and the second pixel definition layer define an aperture region of each sub-pixel, an emission region of each sub-pixel is located within the aperture region, and a height of the second pixel definition layer is greater than a height of the first pixel definition layer in a direction perpendicular to the substrate.

[0026] Optionally, the plurality of sub-pixels are divided into a plurality of repeat units arranged in an array, each repeat unit including two sub-units arranged along a first direction, each sub-unit including a plurality of sub-pixels arranged along the first direction, and within a repeat unit, a pixel-defining structure between adjacent sub-pixels in two adjacent sub-units is an integral structure.

[0027] Optionally, within the plurality of repeating units, the first pixel definition layer includes a first pattern and the second pixel definition layer includes a second pattern, and an orthogonal projection of the second pattern onto the substrate covers an orthogonal projection of the first pattern onto the substrate.

[0028] Optionally, the fourth via structure includes a 22nd via, the second pattern includes a 23rd via, and the second electrode layer is coupled to an auxiliary electrode through the 23rd via and the 22nd via; The orthogonal projection of the 23rd via onto the substrate covers the orthogonal projection of the 22nd via onto the substrate.

[0029] Optionally, the first electrode layer includes a ninth connection portion, the orthogonal projection of the eighth connection portion onto the substrate is located within the orthogonal projection of the ninth connection portion onto the substrate, and the orthogonal projection of the eighth connection portion onto the substrate covers the 22nd via.

[0030] Optionally, the 23rd via is located at the center of the second pattern.

[0031] Based on the technical solution of the above display substrate, a second aspect of the present disclosure provides a display device including the above display substrate.

[0032] The drawings described below are intended to provide a further understanding of the present invention, which forms a part of the present invention, and the exemplary embodiments of the present invention and their descriptions are intended to illustrate the present invention and are not to be construed as an undue limitation on the present invention. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a schematic local view of the planar structure of a display device; [Figure 2] FIG. 2 is a schematic local view of the structure of a display substrate. [Figure 3] FIG. 2 is a local schematic diagram of an equivalent circuit of a pixel driving circuit. [Figure 4] FIG. 2 is a local schematic diagram of an equivalent circuit of a pixel driving circuit. [Figure 5] FIG. 2 is a local schematic diagram of a circuit structure of a repeat unit according to an embodiment of the present disclosure. [Figure 6] FIG. 10 is an equivalent local schematic diagram of the resistance capacitance of a partition scan line according to an embodiment of the present disclosure. [Figure 7] FIG. 10 is a drive time series diagram according to an embodiment of the present disclosure. [Figure 8] FIG. 1 is a schematic local view of an active layer pattern according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a schematic topographical view of a first conductive layer pattern according to an embodiment of the present disclosure. [Figure 10] FIG. 2 is a topographical schematic view of a second conductive layer pattern according to an embodiment of the present disclosure. [Figure 11] FIG. 2 is a schematic local view of a stacked structure of an active layer pattern, a first conductive layer pattern, and a second conductive layer pattern according to an embodiment of the present disclosure. [Figure 12] 1 is a top view of a via structure through an interlayer dielectric layer according to an embodiment of the present disclosure; [Figure 13] FIG. 10 is a schematic topographical view of a third conductive layer pattern according to an embodiment of the present disclosure. [Figure 14] 1 is a schematic local view of a stacked structure of an active layer pattern, a first conductive layer pattern, a second conductive layer, and a third conductive layer pattern according to an embodiment of the present disclosure. [Figure 15] FIG. 2 is a top-down schematic view of a via structure through a first organic layer according to an embodiment of the present disclosure. [Figure 16] FIG. 2 is a top-down schematic view of a via structure through a first passivation layer according to an embodiment of the present disclosure. [Figure 17] FIG. 10 is a schematic local view of a fourth conductive layer pattern according to an embodiment of the present disclosure. [Figure 18] 1 is a schematic local view of a stacked structure of an active layer pattern, a first conductive layer pattern, a second conductive layer, a third conductive layer pattern, and a fourth conductive layer pattern according to an embodiment of the present disclosure. FIG. [Figure 19] FIG. 10 is a top-down schematic view of a via structure through a second passivation layer according to an embodiment of the present disclosure. [Figure 20] FIG. 10 is a top-down schematic view of a via structure through a second organic layer according to an embodiment of the present disclosure. [Figure 21] FIG. 2 is a schematic local view of a first electrode layer pattern according to an embodiment of the present disclosure. [Figure 22] 1 is a schematic local view of a stacked structure of an active layer pattern, a first conductive layer pattern, a second conductive layer, a third conductive layer pattern, a fourth conductive layer, and a first electrode layer pattern according to an embodiment of the present disclosure. FIG. [Figure 23] FIG. 2 is a topographical schematic diagram of a first pixel defining layer pattern according to an embodiment of the present disclosure. [Figure 24] FIG. 10 is a topographical schematic diagram of a second pixel defining layer pattern according to an embodiment of the present disclosure. [Figure 25]FIG. 10 is a schematic local view of a stacked structure of an active layer pattern, a first conductive layer pattern, a second conductive layer, a third conductive layer pattern, a fourth conductive layer, a first electrode layer, a first pixel defining layer, and a second pixel defining layer pattern according to an embodiment of the present disclosure. [Figure 26] FIG. 26 is a schematic cross-sectional view of the structure taken along line AA' in FIG. 25 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0034] To further describe the display substrate and display device provided according to the embodiments of the present invention, detailed descriptions will be given below in conjunction with the accompanying drawings.

[0035] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. The embodiments described below are not all embodiments, but only some embodiments of the present disclosure. Based on the embodiments described in the present disclosure, all other embodiments obtained by those skilled in the art without requiring creative work belong to the scope of protection of the present disclosure.

[0036] Unless otherwise defined, technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. Ordinal numbers such as "first," "second," "third," and "fourth" are used herein to avoid confusion of components and are not intended to limit the number of elements.

[0037] In this disclosure, for convenience, the positional relationship of components is described with reference to the drawings using terms indicating orientation or positional relationship, such as "center," "top," "bottom," "left," and "inner." However, this is merely to facilitate explanation and simplified description of the present specification, and is not intended to indicate or imply that the referred device or element must be constructed and operated in a specific orientation or in a specific direction, and should not be understood as a limitation on the present disclosure. The positional relationship of components may be changed as appropriate depending on the direction in which each component is described. Therefore, the terms described in the specification are not limited and may be exchanged as appropriate in some cases.

[0038] In the present disclosure, unless otherwise clearly specified and limited, the terms "connect," "connect," and "couple" should be understood in a broad sense. For example, when describing some embodiments, the terms "connect" or "couple" may be used, and may refer to a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection via an intermediate member, or internal communication between two elements. Similar words such as "comprise" or "comprise" mean that the element or object appearing before the word covers the elements or objects listed thereafter and their equivalents, but do not exclude other elements or objects. Those skilled in the art can specifically understand the specific meanings of the above terms in the present disclosure.

[0039] In this disclosure, a transistor refers to an element that includes at least three terminals: a gate, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and can pass current through the drain electrode, channel region, and source electrode. In this specification, the channel region refers to a region through which current mainly flows.

[0040] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. The functions of a "source electrode" and a "drain electrode" may be interchangeable, such as when a transistor with reversed polarity is used or when the current direction in circuit operation is changed. Therefore, in this specification, the terms "source electrode" and "drain electrode" are interchangeable.

[0041] In this disclosure, "electrical connection" includes cases where components are connected via an element having some kind of electrical function. The "element having some kind of electrical function" is not particularly limited as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "elements having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions. The proportions in the drawings in this disclosure may be used as a reference for actual processes, but are not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in a display substrate and the number of subpixels per pixel are also not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely structural schematics.

[0042] In the present disclosure, the terms "film" and "layer" can be substituted for each other. For example, a "conductive layer" can be substituted for a "conductive film" in some cases. Similarly, an "insulating film" can be substituted for an "insulating layer" in some cases. In the present disclosure, the term "about" means a numerical value that does not strictly limit boundaries but is allowed within the range of process and measurement error.

[0043] Some embodiments of the present disclosure provide a display device, which may include any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, or a tablet, and further includes a flexible circuit board, a printed circuit board, and a backplate.

[0044] 1 is a schematic diagram of a planar structure of a display device according to an embodiment of the present disclosure. As shown in FIG. 1, the display device 01 includes a display substrate 10, which includes a display area AA and a non-display area SA. The non-display area SA may be located on at least one side of the display area AA. For example, the non-display area SA may be arranged to surround the display area AA.

[0045] The display device may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (including miniLED or microLED) display panel, or the like.

[0046] In an exemplary embodiment, the display substrate 10 may be rectangular, curved, or have other irregular patterns. For example, as shown in Figure 1, the display substrate is a curved rectangle. For convenience of explanation, the display area AA is set to be roughly rectangular, and the extension directions of two mutually perpendicular sides are defined as a first direction (X-axis direction) and a second direction (Y-axis direction), respectively.

[0047] The display device 01 may further include other components, such as a display driver integrated circuit (DDIC) 20. The DDIC 20 is coupled to the display substrate 10; for example, the DDIC 20 may be bound onto the display substrate 10 and configured to provide data signals to the display substrate 10.

[0048] In an exemplary embodiment, the display substrate 10 includes a plurality of pixel units P arranged in an array, and at least one pixel unit P includes a plurality of subpixels. The plurality of subpixels may include a first subpixel SP1 for emitting a first color light, a second subpixel SP2 for emitting a second color light, a third subpixel SP3 for emitting a third color light, and a fourth subpixel SP4 for emitting a fourth color light. For example, the first subpixel SP1 may be a red subpixel (R) that emits red light, the second subpixel SP2 may be a blue subpixel (B) that emits blue light, the third subpixel SP3 may be a green subpixel (G) that emits green light, and the fourth subpixel SP4 may be a white subpixel (W) that emits white light. In an exemplary embodiment, each pixel unit P may include, but is not limited to, three subpixels (e.g., RGB) or four subpixels (e.g., RGBW). This disclosure will be described taking an example in which each pixel unit includes three sub-pixels (RGB).

[0049] 2 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 2, the display substrate 10 includes a plurality of pixel driving circuits Q arranged in an array and light emitting elements coupled to the pixel driving circuits Q. The light emitting elements may be OLEDs or QLEDs. The light emitting elements are configured to emit light of a corresponding brightness in response to a signal output by the pixel driving circuit of the subpixel in which they are located.

[0050] In an exemplary embodiment, pixel driving circuits of a plurality of subpixels may form M subpixel rows and N subpixel columns, where M and N are both positive integers greater than or equal to 1. For example, pixel driving circuits arranged in a row along a first direction are referred to as pixel driving circuits of the same row, and pixel driving circuits arranged in a column along a second direction are referred to as pixel driving circuits of the same column. In the present disclosure, the first direction is the extension direction of the subpixel rows, and the second direction is the extension direction of the subpixel columns. Exemplarily, the present disclosure provides an outline of an array arrangement of adjacent subpixel rows and adjacent subpixel columns, i.e., the (m-1)th row and the mth row, and the (n-1)th column and the nth column, where m is a positive integer greater than 1 and less than or equal to M, and n is a positive integer greater than 1 and less than or equal to N.

[0051] The pixel driving circuit Q includes a plurality of transistors and a storage capacitor. Here, the transistors may be thin film transistors (TFTs), metal oxide semiconductor field effect transistors (MOSs), or other switching devices with the same characteristics, and the present disclosure will be described using thin film transistors as an example. In an exemplary embodiment, the pixel driving circuit may include a 2T1C, 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, etc. structure, where T represents a thin film transistor and C represents a storage capacitor.

[0052] In the pixel driving circuit according to the embodiment of the present disclosure, all the transistors may be N-type transistors. The embodiments of the present disclosure include, but are not limited to, this. For example, one or more transistors in the pixel driving circuit according to the embodiment of the present disclosure may be P-type transistors, and the electrodes of the P-type transistors may be connected to the electrodes of the corresponding N-type transistors in the embodiment of the present disclosure, and a corresponding high or low level may be applied to the corresponding gates.

[0053] In an exemplary embodiment, the display substrate includes a plurality of signal lines and a plurality of scan lines coupled to a plurality of pixel driving circuits. Illustratively, the signal lines include a first signal line D and a power supply line VDD. For example, the pixel driving circuit of a sub-pixel in an n-th column (representing any column) is coupled to the first signal line D(n) and the power supply line VDD, the first signal line D(n) being configured to provide a data signal to the pixel driving circuit of the sub-pixel in the n-th column, and the power supply line VDD being configured to provide a power supply voltage signal to the pixel driving circuit.

[0054] In an exemplary embodiment, the plurality of scan lines includes a first scan line G1 and a second scan line G2. For example, the pixel driving circuit of the (m-1)th row drives the first scan line G1. <m-1>and the first scanning line G1 <m-1>is configured to provide a first scan signal to the pixel driving circuit of the (m-1)th row and control the writing of the data signal in the pixel driving circuit. The pixel driving circuit is configured to receive the data signal transmitted from the first signal line D under the control of the first scan line G1 and output a corresponding current to the light emitting element. The numbers in parentheses in FIG. 2 indicate the row number corresponding to each scan line, for example, G1 <m-1>represents the first scan line of the m-1th row, and G2 <m-1>represents the second scanning line of the (m-1)th row.

[0055] 3 is an equivalent circuit schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in FIG. 3, in an exemplary embodiment, the pixel driving circuit includes a storage capacitor and a plurality of transistors, including a first transistor T1 and a second transistor T2.

[0056] In the exemplary embodiment, the display substrate 10 further includes a plurality of signal lines and a plurality of scanning lines coupled to the pixel driving circuit, the plurality of signal lines including a first signal line D and a second signal line Vref, and the plurality of scanning lines including a first scanning line G1 and a second scanning line G2, the first scanning line G1 and the second scanning line G2 both extending along a first direction and sequentially arranged along a second direction, the first direction being the extension direction of the subpixel rows, the second direction being the extension direction of the subpixel columns, and the first direction intersecting with the second direction.

[0057] Here, the gate of the first transistor T1 is coupled to the first scan line G1, the first pole of the first transistor T1 is coupled to the first signal line D, and the second pole of the first transistor T1 is coupled to the first node N1. When an on-level scan signal is applied to the first scan line G1, the first transistor T1 is configured to input the data voltage signal from the first signal line D to the first node N1 under the control of the signal from the first scan line G1.

[0058] The gate of the second transistor T2 is coupled to the second scan line G2, the first pole of the second transistor T2 is coupled to the second signal line Vref, and the second pole of the second transistor T2 is coupled to the first node N1. When an on-level scan signal is applied to the second scan line G2, the second transistor T2 is configured to input the reference voltage signal from the second signal line Vref to the first node N1 under the control of the second scan line G2.

[0059] In the pixel driving circuit according to the embodiment of the present disclosure, the plurality of transistors further includes a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a driving transistor DT, the plurality of scan lines further includes a third scan line G3, an emission scan line EM and a fourth scan line G4, and the plurality of signal lines further includes a power supply line VDD and a third signal line Vinit.

[0060] Here, the gate of the third transistor T3 is coupled to the third scan line G3, the first electrode of the third transistor T3 is coupled to the first node N1, and the second electrode of the third transistor T3 is coupled to the second node N2. When an on-level scan signal is applied to the third scan line G3, the third transistor T3 is configured to input the voltage of the first node N1 to the second node N2 under the control of the third scan line G3.

[0061] The gate of the fourth transistor T4 is coupled to the emission scanning line EM, the first electrode of the fourth transistor T4 is coupled to the power supply line VDD, and the second electrode of the fourth transistor T4 is coupled to the first electrode of the driving transistor DT, so that when an on-level signal is applied to the emission scanning line EM, the fourth transistor T4 is configured to input a voltage signal from the power supply line to the first electrode of the driving transistor DT under the control of the emission scanning line EM.

[0062] The gate of the driving transistor DT is coupled to the second node N2, i.e., the second electrode of the third transistor T3, the first electrode of the driving transistor DT is coupled to the second electrode of the fourth transistor T4, and the second electrode of the driving transistor DT is coupled to the first electrode of the light-emitting element. The driving transistor DT determines a driving current value based on the potential difference between its gate and first electrode, and applies the generated driving current to the light-emitting element to drive it to emit light.

[0063] The gate of the fifth transistor T5 is coupled to the fourth scan line G4, the first pole of the fifth transistor T5 is coupled to the first electrode of the light-emitting element, and the second pole of the fifth transistor T5 is coupled to the third signal line Vinit. When an on-level signal is applied to the fourth scan line G4, the fifth transistor T5 is configured to transmit a voltage signal from the third signal line Vinit to the first electrode of the light-emitting element, thereby resetting the first electrode of the light-emitting element.

[0064] The storage capacitor C includes a first electrode C1 and a second electrode C2, and the first electrode C1 is coupled to the second node N2, i.e., the first electrode C1 of the storage capacitor C is connected to the gate of the driving transistor T3, and the second electrode C2 is coupled to the first electrode of the light-emitting element.

[0065] In an exemplary embodiment, the transistors included in the pixel driving circuit may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, while the oxide thin-film transistor has advantages such as low leakage current. The low-temperature polysilicon thin-film transistor and the oxide thin-film transistor are integrated on a single display substrate to form a display substrate including both the low-temperature polysilicon thin-film transistor and the oxide transistor (Low Temperature Polysilicon + Oxide, LTPO), which utilizes the advantages of both to achieve low-frequency operation, reduce power consumption, and improve display quality.

[0066] In an exemplary embodiment, the gate of at least one thin film transistor has a dual-gate structure, which can better prevent leakage current from the transistor. FIG. 4 shows an equivalent circuit diagram for a case in which the gates of the first transistor T1, the second transistor T2, and the fifth transistor T5 have a dual-gate structure. While FIG. 4 shows some thin film transistors with a dual gate electrode structure, the present disclosure is not limited thereto. The thin film transistors of the present disclosure may also have a single-gate structure, which can be selected by those skilled in the art according to actual needs.

[0067] 5 is a schematic diagram of the circuit structure of a repeat unit according to an embodiment of the present disclosure. In the display substrate structure of the present disclosure, to improve resolution and simplify processes, scan lines or signal lines in the pixel driving circuit can be shared between different rows or different columns, and illustratively, the sub-pixels in at least two rows or two columns share at least one of the scan lines. Illustratively, at least two sub-pixels located in the same row share at least one of the first scan line G1, the second scan line G2, the third scan line G3, and the emission scan line EM.

[0068] As shown in FIG. 5, the present disclosure illustrates a situation in which subpixels in the same row share the first scan line G1, the second scan line G2, and the emission scan line EM. In addition to sharing scan lines between pixel driving circuits, signal lines may also be shared. For example, at least two subpixels in the same column may be commonly connected to the same first signal line. Sharing lines in a display panel can improve the resolution of the display panel and reduce process complexity. While FIG. 5 illustrates a sharing of signal lines and scan lines in a driving circuit, the present disclosure is not limited to this, and those skilled in the art can select the appropriate line according to their actual needs.

[0069] In an exemplary embodiment, the power supply line VDD and the third signal line Vinit may be designed in a mesh-like pattern. Here, the power supply line VDD includes a first power supply line VDD-1 extending along a first direction and a second power supply line VDD-2 extending along a second direction. The first power supply line VDD-1 and the second power supply line VDD-2 are coupled together, and the first power supply line VDD-1 is located on the side of the emission scan line EM away from the first scan line G1. The fourth scan line G4 extends along the first direction and is located on the side of the first power supply line VDD-1 away from the emission scan line EM. The third signal line Vinit includes a first sub-line Vinit-1 extending along the first direction and a second sub-line Vinit-2 extending along the second direction, where the first sub-line Vinit-1 is located on the side of the fourth scan line G4 away from the first scan line G1. The mesh-like distribution structure of the present disclosure significantly reduces voltage drop during signal transmission and improves screen uniformity.

[0070] In the exemplary embodiment, in the second direction, the first branch scanning line G3-1 is located on the side of the first scanning line G1 that is away from the second scanning line G2, and the emission scanning line EM is located on the side of the first branch scanning line G3-1 that is away from the first scanning line G1.

[0071] 5 and 6, to more clearly illustrate the operation process of the pixel driving circuit, in an exemplary embodiment, the display substrate is divided into a plurality of control regions (e.g., control region 1 to control region X) and a plurality of third scan lines G3, and the plurality of control regions correspond one-to-one to the plurality of third scan lines G3. Each control region includes at least one repeat unit, each repeat unit includes two sub-units arranged along a first direction, and each sub-unit includes a plurality of sub-pixels arranged along the first direction. The third scan lines G3 are respectively coupled to the gates of the third transistors T3 included in each repeat unit in the corresponding control region and are used to control the on / off of the third transistors T3 included in each repeat unit in the corresponding control region.

[0072] According to the specific configuration of the above display substrate, the display substrate of the embodiment of the present disclosure includes multiple control regions, and each third scanning line G3 can control whether all third transistors T3 in the corresponding control region are turned on, thereby achieving the effect of controlling whether the region achieves a high refresh frequency.

[0073] In the exemplary embodiment, within the same control region, the third scan lines G3 are each integrally formed with a control bus G30.

[0074] In an exemplary embodiment, the display substrate further includes a driver chip, the control bus G30 and the driver chip are located on the same side of the display substrate, the control bus is coupled to the driver chip to receive control signals from the driver chip, and transmits the received control signals to the third scan line G3 coupled thereto, and further controls whether to turn on the third transistor T3 in the corresponding control area.

[0075] In the exemplary embodiment, the first branch scanning line G3-1 is arranged along the second direction and extends along the first direction, the second branch scanning line G3-2 is arranged along the first direction and extends along the second direction, the second branch scanning line G3-2 is respectively coupled to the plurality of first branch scanning lines G3-1, the second branch scanning line G3-2 is coupled to the control bus G30, and the first branch scanning line G3-1 is respectively coupled to the gate of each write control transistor T3 included in the corresponding repeat unit.

[0076] In an exemplary embodiment, as shown in FIG. 6 and FIG. 7, a display substrate including X control regions will be taken as an example for detailed description.

[0077] Display time period of Nth frame: 1st third scanning line G3 <1> and the H-th third scanning line G3 <h>The control signals transmitted by the first third scan line G3 are all at the valid level VGH. <1> All the third transistors T3 included in the first control region corresponding to the H-th third scan line G3 are turned on. <h>All the third transistors T3 included in the H-th control region corresponding to the I-th third scan line G3 are turned on, thus ensuring that the I-th control region and the H-th control region are regions that can achieve normal refresh, and achieving high refresh operation of the I-th control region and the H-th control region when scanning the display substrate row by row. The control signal transmitted by the I-th third scanning line G3 is at an inactive level VGL. All third transistors T3 included in the Ith control region corresponding to H are turned off, and the Ith control region cannot achieve high refresh operation when scanning the display substrate row by row, so that the Ith control region is not refreshed in the Nth frame and its display screen is not updated in the Nth frame, thus saving data amount and achieving the effect of high refresh of partition, where H and I are positive integers greater than 1 and less than or equal to X.

[0078] Partition selection is performed for frame N+1 by controlling the control signal transmitted on the third scan line G3 during the blanking period, where the blanking period is located at the beginning or end of the display period of each frame.

[0079] Display time period of N+1th frame: 1st third scan line G3 <1> and the I-th third scanning line G3 The control signals transmitted by the first third scan line G3 are all at the valid level VGH. <1> All the write control transistors T3 included in the first control region corresponding to the I-th third scan line G3 are turned on. All the write control transistors T3 included in the I-th control region corresponding to the H-th third scan line G3 are turned on, thus ensuring that the I-th control region and the I-th control region are regions that can achieve normal refresh, and achieving high refresh operation of the I-th control region and the I-th control region when scanning the display substrate row by row. <h>The control signal transmitted through the H-th third scan line G3 is at an inactive level VGL. <h>All the write control transistors T3 included in the Hth control region corresponding to the Hth control region are turned off, and when scanning the display substrate row by row, the Hth control region cannot achieve high refresh operation, so the Hth control region is not refreshed in the Hth frame and its display screen is not updated in the Hth frame. In this way, the amount of data saved is provided to the high refresh region, and the effect of high refresh of the partition can be achieved.

[0080] In an exemplary embodiment, considering the heavy load on the third scanning line G3, the control signal transmitted on the third scanning line G3 can be adjusted immediately when the Nth frame ends and the blanking period begins.

[0081] In the display substrate according to the embodiment of the present disclosure, the control region and the third scan line G3 are provided, so that the display substrate can effectively achieve the high refresh rate function of the display substrate.

[0082] In the display substrate of the above embodiment, the first branch scanning line G3-1 and the second branch scanning line G3-2 are provided, which not only can better realize the transmission of control signals, but also can reduce the difficulty of layout of the third scanning line and ensure the reliability of the coupling between the third scanning line and the gate of the third transistor T3.

[0083] In an exemplary embodiment, the first branch scan lines located in the same row along the first direction in the same control region are sequentially arranged end-to-end. Illustratively, the first branch scan lines located in the same row along the first direction in the same control region are formed as an integral structure.

[0084] In an exemplary embodiment, in adjacent control regions, there is a gap between adjacent first branch scan lines along the first direction.

[0085] In the display substrate according to the above embodiment, the first branch scanning lines adjacent to each other along the first direction within the same control region are coupled together, so that the third scanning lines form a lattice structure within the same control region, which is advantageous in reducing the overall load on the third scanning line G3 and reducing the voltage drop of the third scanning line G3.

[0086] In an exemplary embodiment, the first branch scan lines adjacent to each other along the first direction within the same control region may be provided independently of each other.

[0087] In an exemplary embodiment, the power supply line VDD includes a first power supply line VDD-1 extending along a first direction and a second power supply line VDD-2 extending along a second direction, and the first power supply line VDD-1 and the second power supply line VDD-2 are coupled together. Along the first direction, the second power supply line VDD-2 is arranged alternately with the repeat unit, and the orthogonal projection of the first branch scanning line G3-1 onto the substrate and the orthogonal projection of the second power supply line VDD-2 onto the substrate do not overlap.

[0088] In an exemplary embodiment, as shown in Figures 8 to 26, in a direction perpendicular to the display substrate, the display substrate includes a substrate 101, and an active layer 103, a first conductive layer 105, a second conductive layer 107, a third conductive layer 109 and a fourth conductive layer 112 arranged sequentially apart from the substrate, and the substrate 101 may be a flexible substrate or a rigid substrate.

[0089] 8 to 25 exemplarily show schematic plan views of each layer in the display substrate of the present disclosure. As shown in Fig. 8, the active layer 103 includes an active pattern p of each transistor in the pixel driving circuit, and the active pattern of each transistor includes a channel region and a conductive region. The conductive regions of each transistor are located on both sides of the channel region and serve as the first and second poles of the transistor, respectively. Specifically, the active pattern p1 of the first transistor T1 includes a first channel region T1p, a first pole T11, and a second pole T12; the active pattern p2 of the second transistor T2 includes a second channel region T2p, a first pole T21, and a second pole T22; the active pattern p3 of the third transistor T3 includes a third channel region T3p, a first pole T31, and a second pole T32; the active pattern p4 of the fourth transistor T4 includes a fourth channel region T4p, a first pole T41, and a second pole T42; the active pattern p5 of the fifth transistor T5 includes a fifth channel region T5p, a first pole T51, and a second pole T52; and the active pattern pd of the drive transistor DT includes a channel region DTp, a first pole DT1, and a second pole DT2. Here, the second pole T12 of the first transistor T1, the second pole T22 of the second transistor T2, and the first pole T31 of the third transistor T3 are common, and the position where these three are commonly connected is referred to as the first node N1, and the position where the second pole T32 of the third transistor T3 and the drive transistor are connected is referred to as the second node N2. The first pole DT1 of the drive transistor DT simultaneously functions as the second pole T42 of the fourth transistor. The second pole DT2 of the drive transistor DT simultaneously functions as the first pole T51 of the fifth transistor. In addition, for example, the first pole T11 of the first transistor, the first pole T21 of the second transistor, the first pole T41 of the fourth transistor, and the first pole T22 of the fifth transistor are each provided separately.

[0090] Continuing to refer to FIG. 8 , the active pattern p1 of the first transistor T1, the active pattern p2 of the second transistor T2, and the active pattern p3 of the third transistor T3 in the mth pixel row have an integrated structure and are located on the side of the drive transistor active pattern pd in the mth pixel drive circuit that is closer to the (m−1)th pixel drive circuit, and the active pattern p4 of the fourth transistor T4 and the active pattern p5 of the fifth transistor T5 are located on the side of the drive transistor active pattern pd in the mth pixel drive circuit that is closer to the (m+1)th pixel drive circuit.

[0091] In exemplary embodiments, the active layer may be formed from one or more of amorphous silicon, polycrystalline silicon, and oxide semiconductor materials.

[0092] As shown in FIG. 9, the first conductive layer 105 is also referred to as a first gate metal layer, and includes the gates of each transistor, the second branch scan line G3-2, and the second sub-line vinit-2.

[0093] In an exemplary embodiment, the first plate of the storage capacitor includes a first sub-plate C1 and a second sub-plate C12, the first sub-plate being located on the first conductive layer.

[0094] As shown in FIG. 10, the second conductive layer 107 is also referred to as the second gate metal layer, and in the exemplary embodiment, the second plate C2 of the storage capacitor is located in the second conductive layer.

[0095] 11 shows a schematic diagram of the stacked structure of the active layer 103, the first conductive layer 105, and the second conductive layer 107. The overlapping regions of the projections of the first conductive layer 105 and the active layer 103 onto the substrate 101 can be the gates of the transistors, specifically including the gate T1g of the first transistor, the gate T2g of the second transistor, the gate T3g of the third transistor, the gate T4g of the fourth transistor, the gate T5g of the fifth transistor, and the gate DTg of the drive transistor DT.

[0096] In an exemplary embodiment, as shown in FIGS. 11 and 26, the manufacturing process of the display substrate of the present disclosure may include the following steps:

[0097] forming a buffer layer 102 on a substrate 101, depositing an active layer 103 made of a semiconductor material on the side of the buffer layer 102 away from the substrate 101, and patterning the active layer 103 to form an active pattern p of each transistor; depositing a gate insulating layer 104 on the active layer 103, then depositing a first conductive layer 105 on the gate insulating layer 104, and patterning the first conductive layer 105 to form a second branch scanning line G3-2, a second sub-line vinit-2, a first sub-electrode C11 of the storage capacitor C, and gates of each transistor; Conductive treatment is performed on a partial structure of the active layer 103, and the area shielded by the first conductive layer 105 forms a channel area of ​​each transistor of the pixel driving circuit, and the unshielded active layer 103 is made conductive, i.e., forms a conductive area of ​​each transistor active pattern; This may then include depositing a first insulating layer 106 on the first conductive layer 105, then depositing a second conductive layer 107 on the first insulating layer 106, and patterning the second conductive layer 107 to form a second plate C2 of the storage capacitor.

[0098] 12, an interlayer insulating layer 108 is provided on the side of the second conductive layer 107 (Gate2) away from the substrate, i.e., between the second conductive layer and the third conductive layer, and a first via structure V100 penetrating the interlayer insulating layer 108 is formed on the interlayer insulating layer 108, and the first via structure V100 is used for connecting between structures above and below the interlayer insulating layer 108. The first via structure V100 includes a plurality of vias.

[0099] 13, the third conductive layer 109 (SD1) includes a first scanning line G1, a second scanning line G2, a first branch scanning line G3-1, an emission scanning line EM, a fourth scanning line G4, a second signal line Vref, a first power supply line VDD-1, a first sub-line Vinit-1, and a second sub-electrode plate C12 of the storage capacitor. Here, the first scanning line G1, the second scanning line G2, the first branch scanning line G3-1, the emission scanning line EM, the fourth scanning line G4, the second signal line Vref, the first power supply line VDD-1, and the first sub-line Vinit-1 all extend along the first direction and are arranged along the second direction. For example, in the subpixel in the (m-1)th row, the first scan line G1 and the second scan line G2 are adjacent to each other, the first scan line G1 being located on the side of the second scan line G2 closer to the subpixel in the (m-1)th row, and the first branch scan line G3-1 being located on the side of the first scan line G1 farther from the second scan line G2, where the first branch scan line G3-1 includes a first connection portion K1, and in the subpixel in the (m-1)th row (any row), the first connection portion K1 is located on the side of the first branch scan line G3-1 closer to the first scan line G1. The second signal line Vref and the second scan line G2 are adjacent to each other and are located on the side of the second scan line G2 farther from the first scan line G1. The first power supply line VDD-1 and the emission scan line EM are adjacent to each other, where the first power supply line VDD-1 is located on the side of the emission scan line EM farther from the first scan line G1. The fourth scan line G4 is located on the side of the first power supply line VDD-1 farther from the emission scan line EM. The first sub-line vinit-1 is located on the side of the fourth scanning line G4 that is farther from the first scanning line G1. The distance between the second signal line Vref and the second scanning line G2 is equal to or greater than the distance between the first scanning line G1 and the second scanning line G2.

[0100] In the exemplary embodiment, the third conductive layer includes a second connection portion K2, and the second connection portion K2 and the second sub-electrode plate are integral with each other. The third conductive layer further includes a third connection portion K3, and the third connection portion K3 is located to the left of the second connection portion K2 in the sub-pixels of the same row in plan view.

[0101] In the exemplary embodiment, the first power supply line VDD-1 includes a fourth connection portion K4, and in the sub-pixels of the same row, the fourth connection portion is located on the side of the first power supply line VDD-1 closer to the fourth scan line G4.

[0102] In the exemplary embodiment, the third conductive layer includes a fifth connection portion K5 and a sixth connection portion K6, and within the subpixels of the same row, the second connection portion K2, the third connection portion K3, the fifth connection portion K5 and the sixth connection portion K6 are all located between the first branch scanning line G3-1 and the emission scanning line EM.

[0103] In an exemplary embodiment of the present disclosure, each connection portion includes a first connection portion K1, a second connection portion K2, a third connection portion K3, a fourth connection portion K4, a fifth connection portion K5, and a sixth connection portion K6, and is used for electrical connection of each conductive layer structure.

[0104] FIG. 14 is a schematic diagram showing a stacked structure of the active layer 103, the first conductive layer 105, the second conductive layer 107, and the third conductive layer 109. Specifically, as shown in FIGS. 8 to 14 and 26, the first scan line G1 is coupled to the gate T1g of the first transistor T1 via a first via structure, e.g., the first via V1. The second scan line G2 is coupled to the gate T2g of the second transistor T2 via a first via structure, e.g., the second via V2. The first branch scan line G3-1 is coupled to the gate T3g of the third transistor T3 via a first via structure, e.g., the third via V3. The emission scan line EM is coupled to the gate T4g of the fourth transistor T4 via a first via structure, e.g., the fourth via V4. The fourth scan line G4 is coupled to the gate T5g of the fifth transistor T5 via a first via structure, e.g., the fifth via V5. The second signal line Vref is coupled to the first pole T21 of the second transistor through a first via structure, e.g., the sixth via V6. The first power supply line VDD-1 is coupled to the first pole T41 of the fourth transistor through a first via structure, e.g., the seventh via V7. The first sub-line Vinit-1 is coupled to the first pole T51 of the fifth transistor through a first via structure, e.g., the eighth via V8.

[0105] As shown in Figures 8 and 14, in subpixels in the same row, the first channel region T1p is located on the side of the first scanning line G1 away from the second scanning line G2, and the second channel region T2p is located on the side of the second scanning line G2 away from the first scanning line G1.

[0106] In an exemplary embodiment, the orthographic projection of the gate T1g of the first transistor T1 onto the substrate and the orthographic projection of the first scanning line G1 onto the substrate at least partially overlap to form a first overlap region A1. The orthographic projection of the first via V1 onto the substrate is located in the first overlap region A1. The orthographic projection of the gate T2g of the second transistor onto the substrate and the orthographic projection of the second scanning line G2 onto the substrate at least partially overlap to form a second overlap region A2. The orthographic projection of the second via V2 onto the substrate is located in the second overlap region A2. The distance between the first via V1 and the second via V2 is greater than the distance between the first scanning line G1 and the second scanning line G2. In the sub-pixels of the same row, the fifth channel region T5p is located on the side closer to the second scanning line G2 of the fourth scanning line G4. The channel region of the driving transistor may be in the shape of the Chinese character "几" (similar to the English letter n), and includes an opening structure T. In the sub-pixels of the nth column, the opening structure faces the sub-pixels of the (n - 1)th column.

[0107] Continuing to refer to FIGS. 8 to 14, the second branch scanning line G3-2 is coupled to the first branch scanning line G3-1 via a first via structure, illustratively the ninth via V9. Here, the orthographic projection of the ninth via V9 onto the substrate is located within the orthographic projection of the first connection portion K1 onto the substrate.

[0108] In an exemplary embodiment, the third connection portion K3 is coupled to the first pole T11 of the first transistor T1 via a first via structure, illustratively the twelfth via V12. The fifth connection portion K5 is coupled to the second electrode plate C2 of the storage capacitor via a first via structure, illustratively the tenth via V10, and is simultaneously coupled to the second pole of the driving transistor via the eleventh via V11. Illustratively, the tenth via V10 and the eleventh via V1 are arranged along the first direction and do not overlap in the direction perpendicular to the substrate. [[ID=~10]]

[0109] The sixth connection portion K6 is coupled to the second electrode C2 of the storage capacitor through a first via structure, e.g., a thirteenth via V13, and simultaneously coupled to the first electrode of the fifth transistor through a fourteenth via V14. The second sub-plate C12 is coupled to the first sub-plate C11 of the storage capacitor and the second node N2 through a first via structure, e.g., a fifteenth via V15 and a sixteenth via V16, respectively. Within the subpixels of the same column, the fifteenth vias V1 and V16 are arranged along the second direction, and the thirteenth vias V13 and V14 are also arranged along the second direction. Exemplarily, the orthogonal projection of the sixth connection portion K6 onto the substrate covers the orthogonal projection of the thirteenth vias V13 and V14 onto the substrate.

[0110] The first sub-line Vinit-1 is coupled to the second sub-line Vinit-2 through a first via structure, illustratively a seventeenth via V17.

[0111] In the display substrate according to the embodiment of the present disclosure, the multiple via connections can improve the electrical connection performance and reduce the connection resistance, and those skilled in the art can select the number of vias used to connect different conductive layers according to actual needs.

[0112] 15, a first organic layer 110 is provided on the side of the third conductive layer 109 that is away from the substrate 101, and a second via structure V200 is formed that penetrates the first organic layer 110. The upper and lower structures of the first organic layer 110 are connected by the second via structure V200 that includes a plurality of vias.

[0113] 16 and 26, a first passivation layer 111 may be further disposed on the side of the first organic layer 110 that faces away from the substrate 101. The first passivation layer 111 includes a third via structure V300 that penetrates the first passivation layer PVX1, and the third via structure V300 is disposed to correspond to the second via structure V200 and is used for electrical connection between the upper and lower structures of the first organic layer 110 and the first passivation layer 111.

[0114] As shown in FIG. 17, the fourth conductive layer 112 includes a plurality of first signal lines D, a second power supply line VDD-2, and a seventh connection portion K7 that extend in the second direction.

[0115] In the exemplary embodiment, the fourth conductive layer 11 further includes an auxiliary electrode Aux, which includes an eighth connecting portion K8, and the eighth connecting portion K8 is located to the left of the auxiliary electrode line Aux in a plan view. In the first direction, the auxiliary electrode Aux and the second branch scanning line G3-2 are adjacent to each other in a plan view.

[0116] 18 shows a schematic diagram of a stacked structure of the active layer 103, the first conductive layer 105, the second conductive layer 107, the third conductive layer 109, and the fourth conductive layer 112. Here, the subpixels in the same column share one first signal line D, which is coupled to the third connection portion K3 through a second via structure, e.g., the 18th via V18, and further realizes coupling with the corresponding first pole of the first transistor T1. Here, the orthogonal projection of the third connection portion onto the substrate covers the orthogonal projection of the 12th and 18th vias onto the substrate.

[0117] In the exemplary embodiment, there is an overlap region between the orthogonal projection of the auxiliary electrode Aux onto the substrate and the orthogonal projection of the first branch scan line G3-1 onto the substrate. The seventh connection portion K7 is coupled to the seventh connection portion K5 via a second via structure, illustratively the 19th via V19, and further realizes a coupling between the second electrode C2 of the storage capacitor and the second electrode of the driving transistor. The orthogonal projection of the seventh connection portion K7 onto the substrate covers the orthogonal projection of the 19th via V19 onto the substrate. Exemplarily, in a plan view, the 19th via V19 is located closer to the first scan line G1 than the 10th via V10 in the subpixels of the same row.

[0118] In the exemplary embodiment, the orthogonal projection of the fifth connection portion K5 onto the substrate covers the orthogonal projection of the seventh connection portion K7 onto the substrate. The fifth connection portion K5 covers the orthogonal projection of the tenth, eleventh, and nineteenth vias onto the substrate.

[0119] In the exemplary embodiment, the second power line VDD-2 is connected to the first power line VDD-1 through a second via structure, illustratively the twentieth via V20. The orthogonal projection of the twentieth via V20 onto the substrate partially overlaps with the orthogonal projection of the fourth connection portion K4 onto the substrate. Illustratively, the width of the twentieth via V20 along the first direction is smaller than its width along the second direction.

[0120] In an exemplary embodiment, a second organic layer 114 is disposed on the side of the fourth conductive layer 112 away from the substrate, and a fourth via structure V400 is formed through the second organic layer 114, the fourth via structure V400 is used to connect between the upper and lower structures of the second organic layer 114, and the fourth via structure V400 includes a plurality of vias.

[0121] In an exemplary embodiment, a second passivation layer 113 may be further disposed between the second organic layer 114 and the fourth conductive layer 112. The second passivation layer 113 includes a fifth via structure V500, which includes a plurality of vias. Schematic diagrams of via structures corresponding to the second passivation layer 113 and the second organic layer 114 are shown in Figures 19 and 20, respectively. The fifth via structure V500 is disposed to correspond to the fourth via structure V400.

[0122] The display substrate according to the embodiment of the present disclosure includes a first passivation layer and a second passivation layer. In other embodiments, the display substrate may include no passivation layer or only one of the passivation layers. For example, when the display substrate includes the first passivation layer 111, the first organic layer and the first passivation layer are located between the third conductive layer 109 and the fourth conductive layer 112. The distance between the third conductive layer 109 and the fourth conductive layer 112 is large, effectively reducing the parasitic capacitance between the conductive line formed by the fourth conductive layer 112 and the conductive line formed by the third conductive layer 109. This meets the load needs of medium- and large-sized display products and supports high refresh rates. The second passivation layer 113 and the second organic layer 114 may be disposed in a similar manner.

[0123] 21 to 26, the display substrate according to the embodiment of the present disclosure includes a light-emitting element layer 30, which is located on the side of the second organic layer 114 away from the substrate 101 and includes a first electrode layer 115, a pixel defining layer 120, a light-emitting functional layer 116, and a second electrode layer 117, which are stacked together. The first electrodes include a plurality of first electrodes corresponding to the plurality of subpixels in a one-to-one relationship. The plurality of first electrodes are coupled to the lower conductive layers through via structures penetrating the second organic layer 114 and the second passivation layer 113, e.g., via V21 to a seventh connection portion 7 located on the fourth conductive layer 112, and further coupled between the second electrode C2 of the storage capacitor and the second electrode of the driving transistor. The first electrode layer 115 further includes a ninth connection portion K9, which is coupled to the auxiliary electrode Aux through a fourth via structure, e.g., via V22 to a fourth via structure. The orthogonal projection of the ninth connecting portion K9 onto the substrate covers the orthogonal projection of the eighth connecting portion K8 onto the substrate. For example, the orthogonal projection of the eighth connecting portion K8 onto the substrate may be located at an intermediate position between the orthogonal projections of the ninth connecting portion K9 onto the substrate. The light-emitting functional layer 116 is connected to the first electrode 115, and the second electrode 117 is connected to the light-emitting functional layer 115. The light-emitting functional layer 116 emits light of a corresponding color when driven by the first electrode 115 and the second electrode 117.

[0124] In the exemplary embodiment, the 19th via V19 and the 21st via V21 in the subpixels of the same row are arranged along the first direction.

[0125] In an exemplary embodiment, the light-emitting functional layer 116 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Exemplarily, the hole injection layers and electron injection layers of all subpixels may be a common layer connected to each other, the hole transport layers and electron transport layers of all subpixels may be a common layer connected to each other, or the hole blocking layers of all subpixels may be a common layer connected to each other, and the emitting layers and electron blocking layers of adjacent subpixels may have a small overlap or may be separated.

[0126] 23 to 26, pixel definition layer 120 includes first pixel definition layer 118 and second pixel definition layer 119, where first pixel definition layer 118 extends along a first direction and is arranged along a second direction, and second pixel definition layer 119 is arranged along the first direction and extends along the first direction. First pixel definition layer 118 and second pixel definition layer 119 define an aperture region of each subpixel, and an emission region of each subpixel is located within the aperture region. First pixel definition layer 118 is located between a substrate and second pixel definition layer 119. Illustratively, the height of second pixel definition layer 119 is greater than the height of first pixel definition layer 118 in a direction perpendicular to the substrate.

[0127] During the fabrication process, inkjet printing is used to drop light-emitting ink into the aperture regions, thereby forming an organic film layer in the light-emitting functional layer within the aperture regions. Because the height of the second pixel definition layer 119 is greater than that of the first pixel definition layer 118, the ink can flow within a row of aperture regions arranged along the second direction during the inkjet printing process, enhancing the ink fluidity. Thus, the ink content within each aperture region is equalized, thereby improving ink deposition uniformity. Furthermore, because the aperture regions in the same row arranged along the second direction are connected to each other, the inkjet printing process can be used to form sub-pixel units of the same color in the same row.

[0128] In an exemplary embodiment, the plurality of sub-pixels are divided into a plurality of repeating units arranged in an array, each repeating unit including two sub-units arranged along a first direction, and each sub-unit including a plurality of sub-pixels arranged along the first direction, for example, a repeating unit including six sub-pixels arranged along the first direction, and the six sub-pixels including BRGBRG arranged along the first direction, where one set of BRG represents one sub-unit.

[0129] In an exemplary embodiment, within the plurality of repeating units, the first pixel definition layer includes a first pattern H1, the second pixel definition layer includes a second pattern H2, and the orthogonal projection of the second pattern H2 onto the substrate covers the orthogonal projection of the first pattern H1 onto the substrate.

[0130] 23 , in an exemplary embodiment, along the first direction, the first pixel definition layer 118 corresponding to each subunit BRG includes a first definition structure 1181, a second definition structure 1182, and a third definition structure 1183 corresponding to each subpixel in the subunit, and within a repeat unit, the pixel definition structures between adjacent subpixels in two adjacent subunits are an integral structure. Illustratively, the repeat unit includes six subpixels BRGBRG, where BRG represents one subunit, and within the subunit, B corresponds to the first definition structure, R corresponds to the second definition structure, and G corresponds to the third definition structure, and the third definition structure and the first definition structure corresponding to adjacent subpixel GB in adjacent subunits may be connected to each other as an integral structure. In at least one repeating unit, the third defining structure corresponding to the adjacent subunit includes a first recess L1, and the first defining structure includes a second recess L2, and in a plan view, the first recess L1 and the second recess L2 are oriented in opposite directions but have similar contours, forming a first pattern H1. The orthogonal projection of the first pattern H1 onto the substrate covers the orthogonal projection of the ninth connecting portion K9 onto the substrate.

[0131] 24, in an exemplary embodiment, in at least one repeat unit, the corresponding second pixel definition layer 119 between adjacent subunits includes a second pattern H2, which includes a first protrusion T1 toward the first subunit and a second protrusion T2 toward the second subunit, where the first protrusion T1 and the first recess L1 have similar contours, and the second protrusion T2 and the second recess L2 have similar contours. Here, the orthogonal projection of the second pattern H2 onto the substrate covers the orthogonal projection of the first pattern H1 onto the substrate, and illustratively, the overlapping region may be located in the central region of the second pattern H2. The second pattern further includes a 23rd via V23, and illustratively, the 23rd via V23 can be located at the center position of the second pattern H2, i.e., within the same repeating unit, the distance from the 23rd via V23 to the first protrusion T1 and the distance from the 23rd via V23 to the second protrusion T2 along the first direction are equal, and such a design makes the ink flow on both sides of the second pattern more uniform during ink printing.

[0132] In an exemplary embodiment, the second electrode layer is connected to the ninth connecting portion K9 through the 23rd via V23, and can further be connected to the auxiliary electrode Aux. In a plan view, the orthogonal projection of the 23rd via V23 onto the substrate covers the orthogonal projection of the 22nd via V22 onto the substrate. Considering process error sources, the term "equal" referred to in this disclosure allows for a certain error range.

[0133] An embodiment of the present disclosure further provides a display device including the display substrate according to the above embodiment, which may be any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet, etc., and further includes a flexible circuit board, a printed circuit board, and a back plate.

[0134] In the embodiments of the present disclosure, the term "same layer" may refer to a film layer on the same structure layer. Alternatively, for example, the film layers on the same layer may be layer structures formed by using the same deposition process to form a specific pattern, and then using the same mask to pattern the film layer in a single-step construction process. Depending on the specific pattern, the single-step construction process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0135] In this specification, the embodiments may refer to each other for the same similar parts, and each embodiment will be described focusing on the differences from other embodiments. In particular, the method embodiments are substantially similar to the product embodiments, so they can be simply described, and the relevant points can be referred to the partial description of the product embodiments.

[0136] Although the embodiments disclosed in the present disclosure are as described above, the above contents are merely embodiments adopted to facilitate understanding of the present disclosure and are not used to limit the present invention. Any person skilled in the art may make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed by the present disclosure, but the patent protection scope of the present invention must comply with the scope defined by the appended claims. [Explanation of symbols]

[0137] 01, display device 10, display substrate 20, display drive circuit 101, substrate 102, buffer layer 103, active layer 104, gate insulating layer; 105, first conductive layer; 106, first insulating layer 107, second conductive layer 108, interlayer insulating layer 109, third conductive layer 110, first organic layer; 111, first passivation layer 112, fourth conductive layer; 113, second passivation layer 114, second organic layer 115, first electrode layer 116, light-emitting functional layer 117, second electrode layer 118, first pixel definition layer 119, second pixel definition layer 120, pixel definition layer< / h> < / h> < / h> < / h>

Claims

1. A display substrate, A substrate; a driving circuit layer including pixel units arranged in an array, at least one of the pixel units including a plurality of sub-pixels, at least one of the sub-pixels including a pixel driving circuit, the pixel driving circuit including a light emitting element, a plurality of transistors and a storage capacitor, the plurality of transistors including a first transistor and a second transistor, the first transistor and the second transistor being coupled to each other; a plurality of scanning lines including first scanning lines and second scanning lines, the first scanning lines and the second scanning lines extending along a first direction and sequentially arranged along a second direction, the first direction being an extension direction of the sub-pixel rows and the second direction being an extension direction of the sub-pixel columns; wherein the plurality of transistors include active patterns, the active pattern of each of the transistors includes a channel region and a conductive region, the active pattern of the first transistor includes a first channel region, the active pattern of the second transistor includes a second channel region, the first channel region is located on a side of the first scan line away from the second scan line, and the second channel region is located on a side of the second scan line away from the first scan line.

2. the display substrate further includes a plurality of signal lines, the plurality of signal lines including a first signal line and a second signal line; the first signal line is coupled to a first pole of the first transistor, the second signal line is coupled to a first pole of the second transistor, and the first transistor is configured to transmit a voltage signal on the first signal line to a second pole of the first transistor under control of a first scan line signal; the second transistor is configured to transmit a voltage signal on a second signal line to a second pole of the second transistor under control of the second scan line signal; 2. The display substrate of claim 1, wherein the second pole of the first transistor and the second pole of the second transistor are coupled to a first node.

3. the plurality of scanning lines further includes a third scanning line, and the plurality of signal lines further includes a power supply line; the third scan line includes a first branch scan line extending along the first direction and a second branch scan line extending along the second direction, the first branch scan line and the second branch scan line being coupled together; the plurality of transistors further includes a third transistor and a drive transistor; the storage capacitor includes a first plate and a second plate; a second pole of the third transistor, a gate of the driving transistor, and a first plate of the storage capacitor are coupled to a second node, a gate of the third transistor is coupled to the third scan line, a first pole of the third transistor is coupled to the first node, and the third transistor is configured to transmit a voltage signal of the first node to the second node under control of the third scan line signal; The display substrate of claim 2 , wherein the first branch scan line is located on a side of the first scan line that is farther away from the second scan line in the sub-pixels of the same row.

4. the plurality of transistors further include a fourth transistor and a fifth transistor, the plurality of scan lines further include a light emitting scan line and a fourth scan line, and the plurality of signal lines further include a third signal line; the light-emitting scanning lines extend along the first direction, a gate of the fourth transistor is coupled to the emission scan line, a first pole of the fourth transistor is coupled to the power supply line, a second pole of the fourth transistor is coupled to a first pole of the drive transistor, and the fourth transistor is configured to transmit a voltage signal from the power supply line to the second pole of the drive transistor under control of an emission scan line signal; 4. The display substrate of claim 3, wherein a gate of the fifth transistor is coupled to the fourth scan line, a first pole of the fifth transistor is coupled to the third signal line, and a second pole of the fifth transistor is coupled to the light-emitting element, and the fifth transistor is configured to transmit a voltage signal of the third signal line to the light-emitting element under control of the fourth scan line signal.

5. the power supply lines include a first power supply line extending along the first direction and a second power supply line extending along the second direction, the first power supply line and the second power supply line are coupled together, and in the sub-pixels of the same row, the first power supply line is located on a side of the light emitting scan line that is farther from the first scan line; the third signal line includes a first sub-line extending along the first direction and a second sub-line extending along the second direction, the first sub-line and the second sub-line being coupled to each other; the fourth scanning line extends along the first direction, and in the sub-pixels of the same row, the fourth scanning line is located on a side of the first power supply line that is farther away from the light emitting scanning line; The display substrate of claim 4 , wherein the first sub-line is located on a side of the fourth scan line that is farther away from the first scan line.

6. 2. The display substrate of claim 1, wherein the pixel driving circuits of the plurality of sub-pixels form M sub-pixel rows and N sub-pixel columns, where M and N are positive integers greater than or equal to 1, and at least two sub-pixels located in the same column are coupled to the same first signal line.

7. the display substrate further includes a plurality of control regions, each of the control regions including at least one repeat unit; the third scanning lines are respectively coupled to gates of the third transistors included in each of the repeat units, and are used to control the on / off of the third transistors included in each of the repeat units in the corresponding control region; 7. The display substrate of claim 6, wherein the first branch scan lines coupled to the sub-pixels in the repeat unit within the same control region along the first direction are coupled to each other, and the first branch scan lines are disconnected between the control regions.

8. The display substrate of claim 7 , wherein the orthogonal projection of the second power supply line onto the substrate and the orthogonal projection of the first branch scanning line onto the substrate do not overlap.

9. The display substrate of claim 7 , wherein there is an overlapping area between the orthogonal projection of the first power supply line onto the substrate and the orthogonal projection of the second branch scanning line onto the substrate.

10. In a direction perpendicular to the substrate, the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are sequentially disposed on the substrate; the active layer includes active patterns of the plurality of transistors, the active patterns including channel regions and conductive regions; the first conductive layer includes gates of the plurality of transistors, a second branch scan line, and a second sub-line; the second conductive layer includes a second plate of the storage capacitor; the third conductive layer includes the first scan line, the second scan line, the first branch scan line, the light emitting scan line, the fourth scan line, the second signal line, the first power supply line, and the first sub-line; the fourth conductive layer includes the first signal line and the second power supply line; The display substrate of claim 7 , wherein the distance between the second signal line and the second scan line is equal to or greater than the distance between the first scan line and the second scan line.

11. an interlayer insulating layer is disposed between the second conductive layer and the third conductive layer, the interlayer insulating layer includes a first via structure, the first via structure includes a first via and a second via; an orthogonal projection of the gate of the first transistor onto the substrate and an orthogonal projection of the first scan line onto the substrate at least partially overlap each other to form a first overlap region, and an orthogonal projection of the first via onto the substrate is located in the first overlap region; an orthogonal projection of the gate of the second transistor onto the substrate and an orthogonal projection of the second scan line onto the substrate at least partially overlap each other to form a second overlap region, and an orthogonal projection of the second via onto the substrate is located in the second overlap region; The display substrate of claim 10 , wherein a distance between the first via and the second via is greater than a distance between the first scan line and the second scan line.

12. the first branch scanning line includes a first connection portion, and in the sub-pixels of the same row, the first connection portion is located on a side of the first branch scanning line that is farther away from the light emitting scanning line; 12. The display substrate of claim 11, wherein the first via structure includes a ninth via, the second branch scanning line is coupled to the first branch scanning line through the ninth via, and the orthogonal projection of the ninth via onto the substrate is located within the orthogonal projection of the first connection portion onto the substrate.

13. the first plate of the storage capacitor includes a first sub-plate and a second sub-plate, the first sub-plate is located on the first conductive layer, the second sub-plate is located on the third conductive layer, and the third conductive layer includes a second connection portion; the first via structure includes a fifteenth via and a sixteenth via, the second sub-plate is coupled to the first sub-plate through the fifteenth via, and the second sub-plate is coupled to the second node through the sixteenth via; The display substrate of claim 12 , wherein orthogonal projections of the fifteenth via and the sixteenth via onto the substrate are located within an orthogonal projection of the second connection portion onto the substrate.

14. a first organic layer on a side of the third conductive layer away from the substrate, the first organic layer including a second via structure, the first via structure including a twelfth via, and the second via structure including an eighteenth via; the first signal line is coupled to a first pole of the first transistor through the twelfth via and the eighteenth via, and there is an overlap region between orthogonal projections of the eighteenth via and the twelfth via onto the substrate; The display substrate of claim 13 , wherein the third conductive layer further includes a third connection portion, and an orthogonal projection of the third connection portion onto the substrate covers an orthogonal projection of the 18th via and the 12th via onto the substrate.

15. the second via structure includes a twentieth via, and the second power line is coupled to the first power line through the twentieth via; the first power supply line includes a fourth connection portion, and in the sub-pixels in the same row, the fourth connection portion is located on a side of the first power supply line closer to the fourth scan line; an orthogonal projection of the 20th via onto the substrate partially overlaps with an orthogonal projection of the fourth connection portion onto the substrate; The display substrate of claim 14 , wherein the width of the 20th via in the first direction is smaller than the width of the 20th via in the second direction.

16. 11. The display substrate of claim 10, further comprising: a light-emitting element layer located on a side of the fourth conductive layer away from the substrate; the light-emitting element layer including a first electrode layer, a pixel defining layer, a light-emitting functional layer, and a second electrode layer; and the first electrode layer including a plurality of first electrodes corresponding one-to-one to the plurality of sub-pixels.

17. 17. The display substrate of claim 16, further comprising a second organic layer on a side of the fourth conductive layer away from the substrate, the second organic layer comprising a fourth via structure, the fourth via structure comprising a 21st via, the plurality of first electrodes being coupled to the seventh connection portion through the 21st via, and further realizing coupling with a second plate of the storage capacitor and a second electrode of the driving transistor.

18. 18. The display substrate of claim 17, wherein the fourth conductive layer further comprises an auxiliary electrode, the auxiliary electrode comprises an eighth connection portion, and the eighth connection portion is located to the left of the auxiliary electrode in a plan view.

19. 19. The display substrate of claim 18, wherein the pixel definition layer includes a first pixel definition layer and a second pixel definition layer, the first pixel definition layer is arranged along the first direction and extends along the second direction, the first pixel definition layer and the second pixel definition layer define an aperture region of each subpixel, an emission region of each subpixel is located within the aperture region, and a height of the second pixel definition layer is greater than a height of the first pixel definition layer in a direction perpendicular to the substrate.

20. 20. The display substrate of claim 19, wherein the plurality of sub-pixels are divided into a plurality of repeat units arranged in an array, each repeat unit including two sub-units arranged along a first direction, each sub-unit including a plurality of sub-pixels arranged along the first direction, and within a repeat unit, a pixel defining structure between adjacent sub-pixels in two adjacent sub-units is an integral structure; and within the plurality of repeat units, the first pixel defining layer includes a first pattern, and the second pixel defining layer includes a second pattern, and an orthogonal projection of the second pattern onto the substrate covers an orthogonal projection of the first pattern onto the substrate.

21. the fourth via structure includes a 22nd via, the second pattern includes a 23rd via, and the second electrode layer is coupled to an auxiliary electrode through the 23rd via and the 22nd via; The display substrate of claim 20 , wherein an orthogonal projection of the 23rd via onto the substrate covers an orthogonal projection of the 22nd via onto the substrate.

22. the first electrode layer includes a ninth connection portion, an orthogonal projection of the eighth connection portion onto the substrate is located within an orthogonal projection of the ninth connection portion onto the substrate, and the orthogonal projection of the eighth connection portion onto the substrate covers the 22nd via; The display substrate of claim 21 , wherein the 23rd via is located at the center of the second pattern.

23. A display device comprising the display substrate according to any one of claims 1 to 22.

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