Display substrate and manufacturing method thereof, display device

Abstract

The present specification relates to a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 60 extending in a second direction, a plurality of first connecting lines 70 extending in the first direction, and a plurality of second connecting lines 80 extending in the second direction. The circuit units include pixel driving circuits, and at least one data signal line 60 is connected to the plurality of pixel driving circuits of one unit column, first ends of the plurality of first connecting lines 70 corresponding to the plurality of data signal lines 60 and second ends of the plurality of first connecting lines 70 corresponding to the plurality of second connecting lines 80, the pixel driving circuits of adjacent unit columns are mirror-symmetrical with respect to a center line, and the second connecting lines 80 are disposed in gaps between the pixel driving circuits of adjacent unit columns.

Description

[Technical Field]

[0001] The present specification relates to the field of display technology, but is not limited thereto, and specifically to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as autonomous light emission, wide viewing angle, high contrast, low power consumption, extremely fast response speed, light weight, thin profile, bendability, and low cost. With the development of display technology, flexible displays that use OLEDs or QLEDs as light-emitting devices and thin film transistors (TFTs) for signal control have become mainstream products in the current display field. Summary of the Invention [Means for solving the problem]

[0003] The following is a summary of the subject matter described herein, which does not limit the scope of protection of the claims.

[0004] In one aspect, the present disclosure provides a display substrate, the display substrate including a display area, the display area including a driving structure layer disposed on a base, the driving structure layer including at least a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, the first direction intersecting the second direction, the circuit units including pixel driving circuits, at least one data signal line connected to a plurality of pixel driving circuits of one unit column, first ends of the plurality of first connecting lines connected to a plurality of data signal lines, and second ends of the plurality of first connecting lines connected to a plurality of second connecting lines, the pixel driving circuits of adjacent unit columns are mirror-symmetrical with respect to a center line, the center line being a straight line located between the adjacent unit columns and extending along the second direction, the second connecting line being disposed in a gap between the pixel driving circuits of the adjacent unit columns.

[0005] In an exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and the minimum distance in the first direction between the second connecting line and the adjacent data signal line is greater than the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0006] In an exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and the minimum distance in the first direction between the second connecting line and the adjacent data signal line is 1 / 2 of the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0007] In an exemplary embodiment, the driving structure layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are provided in gaps between the pixel driving circuits of adjacent unit columns.

[0008] In an exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power supply wiring, and the minimum distance in the first direction between the power supply wiring and the adjacent data signal line is greater than the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0009] In an exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power supply wiring, and the minimum distance in the first direction between the power supply wiring and the adjacent data signal line is 1 / 2 of the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0010] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving structure layer includes a plurality of conductive layers sequentially arranged on a base, the first connecting line and the second connecting line being arranged on different conductive layers, and the data signal line and the second connecting line being arranged on the same conductive layer.

[0011] In an exemplary embodiment, the plurality of conductive layers include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially disposed along a direction away from the base, the first connection line is disposed in the second source-drain metal layer, the data signal line and the second connection line are disposed in the third source-drain metal layer, the data signal line is connected to a first end of the first connection line through a via, and the second connection line is connected to a second end of the first connection line through a via.

[0012] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a second transistor, and a storage capacitor, the first transistor including at least a first active layer, the second transistor including at least a second active layer, the second region of the first active layer and the first region of the second active layer being connected to each other as an integral structure and connected to a first plate of the storage capacitor via a first connecting electrode, the second source-drain metal layer further including a shield electrode, an orthogonal projection of the shield electrode at the base at least partially overlapping with an orthogonal projection of the second region of the first active layer and the first region of the second active layer at the base, and an orthogonal projection of the shield electrode at the base at least partially overlapping with an orthogonal projection of the first connecting electrode at the base.

[0013] In an exemplary embodiment, the third source-drain metal layer further includes a first power line, and the first power line is connected to the shield electrode through a via.

[0014] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate further includes a light-emitting structure layer disposed on a side of the driving structure layer away from the base, the light-emitting structure layer including a plurality of light-emitting units, the light-emitting units including at least an anode, and in at least one light-emitting unit, a positive projection of the anode on the base at least partially overlaps with a positive projection of the first power line on the base, and a negative projection of the anode on the base at least partially overlaps with a positive projection of the shield electrode on the base.

[0015] In an exemplary embodiment, in at least one light-emitting unit, the orthogonal projection of the anode at the base has a first overlapping area with the orthogonal projection of the first power line at the base, and the orthogonal projection of the anode at the base has a second overlapping area with the orthogonal projection of the shield electrode at the base, and the area of ​​the first overlapping area is smaller than the area of ​​the second overlapping area.

[0016] In an exemplary embodiment, the pixel driving circuit includes at least a fourth transistor, a first pole of the fourth transistor is connected to the data signal line via a data connection electrode, and in at least one circuit unit, the first connection line is connected to the data connection electrode.

[0017] In an exemplary embodiment, at least one circuit unit further includes a data connection block, a first end of the data connection block connected to the first connection line, and a second end of the data connection block connected to the data connection electrode.

[0018] In an exemplary embodiment, in at least one circuit unit, the first connection line, the data connection electrode, and the data connection block are provided in the same layer and are connected to each other to form an integrated structure.

[0019] In an exemplary embodiment, at least one circuit unit further includes a second initial signal line extending along the first direction and a second initial connecting line extending along the second direction, and the second initial connecting lines are installed between two adjacent second initial signal lines in the second direction and are respectively connected to the two second initial signal lines, thereby forming second initial connecting lines having a network connection structure in the display area.

[0020] In an exemplary embodiment, the second initial connection lines are installed in odd-numbered unit columns, or the second initial connection lines are installed in even-numbered unit columns.

[0021] In an exemplary embodiment, of two adjacent unit rows, the unit column in which the second initial connection line is located in one unit row is different from the unit column in which the second initial connection line is located in the other unit row.

[0022] In an exemplary embodiment, the second initial signal line and the second initial connection line are provided in the same layer and are connected to each other in an integrated structure.

[0023] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor and a plurality of transistors, and the plurality of conductive layers include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are sequentially arranged along a direction away from the base, the shielding layer including at least a shielding electrode, the first semiconductor layer including at least active layers of a plurality of low-temperature polysilicon transistors, and the first gate metal layer including at least a first scanning signal line, an emission signal line, a second gate metal layer, a third gate metal layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are sequentially arranged along a direction away from the base, the shielding layer including at least a shielding electrode, the first semiconductor layer including at least active layers of a plurality of low-temperature polysilicon transistors, and the first gate metal layer including at least a first scanning signal line, an emission signal line, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, the second gate metal layer includes at least the second plate of the storage capacitor; the second semiconductor layer includes at least the active layers of a plurality of oxide transistors; the third gate metal layer includes at least a second scanning signal line and a third scanning signal line; the first source-drain metal layer includes at least a second initial signal line having a network connection structure; the second source-drain metal layer includes at least a shield electrode and the first connecting line; and the third source-drain metal layer includes at least a first power line, the data signal line, and the second connecting line.

[0024] In an exemplary embodiment, the plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the first transistor and the second transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low temperature polysilicon transistors.

[0025] In another aspect, the present disclosure provides a display device comprising the display substrate described above.

[0026] In yet another aspect, the present disclosure provides a method for manufacturing a display substrate, the display substrate including a display region, the method comprising: forming a driving structure layer on a base of the display area, the driving structure layer including at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, the first direction intersecting the second direction; the circuit units including pixel driving circuits, at least one data signal line connected to the plurality of pixel driving circuits of one unit column, first ends of the plurality of first connecting lines connected to corresponding ones of the plurality of data signal lines, second ends of the plurality of first connecting lines connected to corresponding ones of the plurality of second connecting lines; the pixel driving circuits of adjacent unit columns are mirror symmetrical with respect to a center line, the center line being a straight line located between adjacent unit columns and extending along the second direction; and the second connecting line being disposed in a gap between the pixel driving circuits of adjacent unit columns.

[0027] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a structural schematic diagram of a display device. [Figure 2] FIG. 2 is a structural schematic diagram of a display substrate. [Figure 3] FIG. 2 is a schematic plan view of the display area of ​​the display substrate. [Figure 4] FIG. 2 is a schematic cross-sectional view of a display area of ​​a display substrate. [Figure 5] FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit. [Figure 6] 1 is a schematic planar structural view of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 7] FIG. 2 is a schematic diagram illustrating the layout of data connection lines according to an exemplary embodiment of the present disclosure. [Figure 8] 1 is a schematic planar structural view of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 9] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after forming a shielding layer pattern. [Figure 10]FIG. 2 is a schematic diagram of the state after a first semiconductor layer pattern is formed in the embodiment of the present disclosure. [Figure 11] FIG. 2 is a schematic diagram of the state after a first semiconductor layer pattern is formed in the embodiment of the present disclosure. [Figure 12] FIG. 2 is a schematic diagram of the first conductive layer pattern formed in the embodiment of the present disclosure. [Figure 13] FIG. 2 is a schematic diagram of the first conductive layer pattern formed in the embodiment of the present disclosure. [Figure 14] FIG. 2 is a schematic diagram of the second conductive layer pattern formed in the embodiment of the present disclosure. [Figure 15] FIG. 2 is a schematic diagram of the second conductive layer pattern formed in the embodiment of the present disclosure. [Figure 16] FIG. 10 is a schematic diagram of the state after a second semiconductor layer pattern is formed in the embodiment of the present disclosure. [Figure 17] FIG. 10 is a schematic diagram of the state after a second semiconductor layer pattern is formed in the embodiment of the present disclosure. [Figure 18] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after a third conductive layer pattern is formed. [Figure 19] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after a third conductive layer pattern is formed. [Figure 20] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after a sixth insulating layer pattern is formed. [Figure 21] FIG. 10 is a schematic diagram of the fourth conductive layer pattern formed in the embodiment of the present disclosure. [Figure 22] FIG. 10 is a schematic diagram of the fourth conductive layer pattern formed in the embodiment of the present disclosure. [Figure 23] FIG. 2 is a schematic diagram of the first flat layer pattern formed in the embodiment of the present disclosure. [Figure 24] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after forming a fifth conductive layer pattern. [Figure 25] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after forming a fifth conductive layer pattern. [Figure 26] FIG. 2 is a schematic diagram of the second flat layer pattern formed in the embodiment of the present disclosure. [Figure 27] FIG. 10 is a schematic diagram of the sixth conductive layer pattern after it has been formed in the embodiment of the present disclosure. [Figure 28] FIG. 10 is a schematic diagram of the sixth conductive layer pattern after it has been formed in the embodiment of the present disclosure. [Figure 29] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after a third flat layer pattern is formed. [Figure 30] FIG. 2 is a schematic diagram of an anode conductive layer pattern formed in an embodiment of the present disclosure. [Figure 31] FIG. 10 is a schematic diagram of the embodiment of the present disclosure after forming a pixel definition layer pattern. [Figure 32] FIG. 10 is a schematic planar structure diagram of another display substrate in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] The drawings are intended to facilitate understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present application, but are not intended to limit the technical solutions of the present disclosure.

[0030] To clarify the objectives, technical solutions, and advantages of the present disclosure, the following detailed description of the embodiments of the present disclosure will be given with reference to the accompanying drawings. It should be noted that the embodiments can be implemented in many different forms. As those skilled in the art can easily understand, the manner and content of the present disclosure can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the following embodiments. Where there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0031] The proportions in the drawings in this disclosure may be used as a reference for actual processes, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0032] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to limit the number of components.

[0033] For convenience, the positions of components in this specification are described with reference to the drawings using terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer." However, this is intended to simplify and explain the specification, and is not intended to indicate or suggest that the described devices or elements have a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationships of components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms described in the specification may not be limited and may be appropriately changed as the case may be.

[0034] In this specification, unless otherwise clearly specified and limited, the terms "attach," "couple," and "connect" should be understood in a broad sense. For example, they may be fixedly connected, detachably connected, or integrally connected. They may be mechanically connected or electrically connected. They may be directly connected, indirectly connected via a linker, or internally connected between two elements. Those skilled in the art can understand the specific meanings of the above terms in the present disclosure according to the specific circumstances.

[0035] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, channel region, and source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0036] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. When using a transistor with opposite polarity, or when the current direction during operation in a circuit changes, the functions of "source electrode" and "drain electrode" may be interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" may be interchangeable, and "source terminal" and "drain terminal" may be interchangeable.

[0037] In this specification, "electrically connected" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of "elements having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0038] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and includes a state in which the angle is between -5° and 5°. "Perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and includes a state in which the angle is between 85° and 95°.

[0039] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive thin film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0040] The triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not intended to be exact, and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and may have small variations due to tolerances, chamfers, arc edges, and variations.

[0041] In this disclosure, "about" refers to a case where the boundary is not precisely defined, but rather allows for a numerical value within the error range of process and measurement.

[0042] FIG. 1 is a structural diagram of a display device. As shown in FIG. 1, the display device includes a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data drivers are connected to a plurality of data signal lines (D1-Dn), the scan drivers are connected to a plurality of scan signal lines (S1-Sm), and the light-emitting drivers are connected to a plurality of light-emitting signal lines (E1-Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively. In an exemplary embodiment, the timing controller provides gray values ​​and control signals conforming to the specifications of the data driver to the data driver, provides clock signals, scan start signals, etc. conforming to the specifications of the scan driver to the scan driver, and provides clock signals, emission stop signals, etc. conforming to the specifications of the light-emitting driver to the light-emitting driver. The data driver generates data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn using gray values ​​and control signals received from the timing controller. For example, the data driver may sample gray values ​​using a clock signal and apply data voltages corresponding to the gray values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver receives a clock signal, a scan start signal, etc. from the timing controller and generates scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver may sequentially provide scan signals having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and generate scan signals by sequentially transferring the scan start signal, provided in the form of an on-level pulse, to the next stage circuit under the control of a clock signal, where m may be a natural number.The light emitting driver receives a clock signal, a firing stop signal, etc. from the timing controller to generate firing signals to be provided to the light emitting signal lines E1, E2, E3, ..., Eo. For example, the light emitting driver may sequentially provide firing signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate firing signals by sequentially transferring the firing stop signal, provided in the form of an off-level pulse, to the next stage circuit under the control of the clock signal, where o may be a natural number.

[0043] FIG. 2 is a structural schematic diagram of a display substrate. As shown in FIG. 2, the display substrate may include a display area 100, a bind area 200 located on one side of the display area 100, and a bezel area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area and may include a plurality of sub-pixels Pxij constituting a pixel array, where the sub-pixels Pxij are configured to display moving or still images, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and may be deformable, for example, by being curled, bent, folded, or rolled up.

[0044] In an exemplary embodiment, the bind area 200 may include a fan-out area, a bend area, a driver chip area, and a bind pin area, arranged in this order along a direction away from the display area. The fan-out area may be connected to the display area and include a plurality of data fan-out lines, and the data fan-out lines are configured to be connected to data signal lines in the display area using a fan-out wiring scheme. The bend area may be connected to the fan-out area and include a composite insulating layer having a groove formed therein, and be configured to bend the driver chip area and the bind pin area to the back surface of the display area. The driver chip area may be connected to the bend area and may include an integrated circuit (IC) configured to be connected to the plurality of data fan-out lines. The bind pin area may be connected to the driver chip area and may include a bond pad configured to be bound to an external flexible printed circuit (FPC).

[0045] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crevice dam region, and a cutting region, which are sequentially arranged along a direction away from the display region. The circuit region may be connected to the display region and may include at least a gate driving circuit, which is connected to the scanning signal lines and the light-emitting signal lines in the display region. The power line region may be connected to the circuit region and may include at least a power lead line, which extends along a direction parallel to the edge of the display region and is connected to the cathode of the display region. The crevice dam region may be connected to the power line region and may include at least a plurality of crevice lines in the composite insulating layer. The cutting region may be connected to the crevice dam region and may include a cutting groove in the composite insulating layer, and the cutting groove may be configured to cut along the cutting groove after all the film layers of the display substrate are manufactured and completed.

[0046] In an exemplary embodiment, at least one isolation dam may be provided in the fan-out region of the binding region 200 and the power line region of the bezel region 300, and the at least one isolation dam may extend along a direction parallel to the edge of the display region to form a ring-shaped structure surrounding the display region, where the edge of the display region is one edge of the display region binding region or the bezel region.

[0047] FIG. 3 is a schematic planar diagram of a display region of a display substrate. As shown in FIG. 3, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to scan signal lines, data signal lines, and emission signal lines, respectively. The pixel driving circuit is configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and emission signal lines and output currents corresponding to the light-emitting units. The light-emitting units in each sub-pixel are connected to the pixel driving circuit of the corresponding sub-pixel, and are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the corresponding sub-pixel.

[0048] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third and fourth sub-pixels P3 and P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombic, pentagonal, or hexagonal, and the four sub-pixels may be arranged in a diamond-like manner to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontally parallel, vertically parallel, square, or other manner, and the present disclosure is not limited thereto.

[0049] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a manner such as horizontal parallel, vertical parallel, or square, and the present disclosure is not limited thereto.

[0050] 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of four subpixels in the display region. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the base 101, and a packaging structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the base 101. In some possible embodiments, the display substrate may include other film layers, such as a touch structure layer, and the present disclosure is not limited thereto.

[0051] In an exemplary embodiment, the base 101 may be a flexible base or a rigid base. The driving structure layer 102 may include multiple circuit units, each of which may include a pixel driving circuit consisting of at least multiple transistors and a storage capacitor. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least an anode, a pixel-defining layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode and cathode. The package structure layer 104 may include a first package layer, a second package layer, and a third package layer stacked together. The first and third package layers may be made of inorganic materials, and the second package layer may be made of organic materials. The second package layer is disposed between the first and third package layers, forming an inorganic / organic / inorganic stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0052] 5 is an equivalent circuit schematic diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C, and the pixel driving circuits may be connected to eight signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, light-emitting signal line E, data signal line D, first initial signal line INIT1, second initial signal line INIT1, and first power supply line VDD).

[0053] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to a first pole of the third transistor T3, a second pole of the fourth transistor T4, and a second pole of the fifth transistor T5, respectively. The second node N2 is connected to a second pole of the first transistor T1, a first pole of the second transistor T2, a gate electrode of the third transistor T3, and a first end of the storage capacitor C, respectively. The third node N3 is connected to a second pole of the second transistor T2, a second pole of the third transistor T3, and a first pole of the sixth transistor T6, respectively. The fourth node N4 is connected to a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7, respectively. The fourth node N4 is further connected to an anode of the light-emitting device EL.

[0054] In an exemplary embodiment, the first end of the storage capacitor C is connected to the second node N2, and the second end of the storage capacitor C is connected to the first power supply line VDD, i.e., the first end of the storage capacitor C is connected to the gate electrode of the third transistor T3.

[0055] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scanning signal line S2, the first pole of the first transistor T1 is connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is connected to the second node N2. When an ON scanning signal is applied to the second scanning signal line S2, the first transistor T1 transfers a first initialization voltage to the first end of the storage capacitor C to initialize the storage capacitor C.

[0056] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to a third scan signal line S3, the first pole of the second transistor T2 is connected to a second node N2, and the second pole of the second transistor T2 is connected to a third node N3. When an on scan signal is applied to the third scan signal line S3, the second transistor T2 connects the gate electrode of the third transistor T3 (the second node N2) to the second pole of the third transistor T3 (the third node N3).

[0057] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the second node N2, i.e., the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, the first pole of the third transistor T3 is connected to the first node N1, and the second pole of the third transistor T3 is connected to the third node N3. The third transistor T3 may also be called a drive transistor, and the third transistor T3 determines the magnitude of the drive current flowing between the first power supply line VDD and the light emitting device EL according to the potential difference between its gate electrode and first pole.

[0058] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When an on scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the first node N1.

[0059] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, the second electrode of the fifth transistor T5 is connected to the first node N1, and the signal of the first power supply line VDD is a continuously supplied high-level signal. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. When an ON light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 are turned on, forming a driving current path between the first power supply line VDD and the light-emitting device EL, causing the light-emitting device EL to emit light.

[0060] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. When an ON scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the fourth node N4 to initialize or discharge the charge stored in the anode of the light emitting device EL.

[0061] In exemplary embodiments, the light-emitting device EL may be an OLED including a stacked anode (first electrode), an organic light-emitting layer, and a cathode (second electrode), or may be a QLED including a stacked anode (first electrode), a quantum dot light-emitting layer, and a cathode (second electrode).

[0062] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to a fourth node N4, a second electrode of the light-emitting device EL is connected to a second power supply line VSS, and the signal of the second power supply line VSS is a continuously supplied low-level signal.

[0063] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve product yield. In some possible embodiments, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0064] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon transistors, oxide transistors, or both. The active layer of the low-temperature polysilicon transistors is made of low-temperature polysilicon (abbreviated as "LTPS"), and the active layer of the metal oxide transistors is made of metal oxide semiconductor (oxide). The low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while the oxide transistors have advantages such as low leakage current. By integrating the low-temperature polysilicon transistors and the metal oxide transistors on a single display substrate to form a low-temperature polycrystalline oxide (abbreviated as "LTPO") display substrate, the advantages of both can be utilized, thereby enabling low-frequency driving, reducing power consumption, and improving display properties.

[0065] In an exemplary embodiment, the first transistor T1 and the second transistor T2 may employ metal oxide transistors, and the third transistor T3 to the seventh transistor T7 may employ low temperature polysilicon transistors.

[0066] In an exemplary embodiment, in the pixel driving circuit shown in FIG. 5 , the first transistor T1 and the second transistor T2 are N-type oxide transistors, and the third transistor T3 to the seventh transistor T7 are P-type low-temperature polysilicon transistors, for example. The operation procedure of the pixel driving circuit may include:

[0067] In the first stage (which can be called the reset stage), the signal on the second scanning signal line S2 is an on signal (high level), and the signals on the first scanning signal line S1, the third scanning signal line S3, and the light-emitting signal line E are off signals. The on signal on the second scanning signal line S2 turns on the first transistor T1, and the signal on the first initialization signal line INIT1 is supplied to the second node N2 via the first transistor T1 to initialize (reset) the storage capacitor C, clearing any existing charge in the storage capacitor. Since the first end of the storage capacitor C is low level, the third transistor T3 is turned on. In this stage, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are off, and the OLED does not emit light.

[0068] In the second phase (which may be referred to as a data writing phase or threshold compensation phase), the signals on the first scanning signal line S1 and the third scanning signal line S3 are on signals, the signals on the second scanning signal line S2 and the light-emitting signal line E are off signals, and a data voltage is output from the data signal line D. The on signals on the first scanning signal line S1 and the third scanning signal line S3 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. By turning on the second transistor T2 and the fourth transistor T4, the data voltage output from the data signal line D is supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage at the first end (second node N2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output from the data signal line D and Vth is the threshold voltage of the third transistor T3. By turning on the seventh transistor T7, the signal of the second initial signal line INIT2 is supplied to the first pole of the OLED, which initializes (resets) the first pole of the OLED and clears the voltage pre-stored therein to complete the initialization, ensuring that the OLED does not emit light. At this stage, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0069] In the third stage (which can be called the light-emitting stage), the signal on the light-emitting signal line E is an ON signal, and the signals on the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 are OFF signals. The ON signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output from the first power supply line VDD supplies a driving voltage to the first electrode of the OLED via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the OLED to emit light.

[0070] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-|Vth|, the driving current of the third transistor T3 is given by the following equation:

[0071] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[Vdd-Vd] 2

[0072] Here, I is the driving current flowing through the third transistor T3, i.e., the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output from the data signal line D, and Vdd is the power supply voltage output from the first power supply line VDD.

[0073] As OLED display technology advances, consumer demands for display performance are increasing. Ultra-narrow bezels have become a new trend in display product development. Therefore, narrower bezels, and even bezel-less designs, are becoming increasingly important in OLED display product design. On a display substrate, the bind area typically includes a fan-out area, bend area, driver chip area, and bind pin area, which are arranged sequentially away from the display area. Because the width of the bind area is smaller than the display area, the signal lines of the driver chip and bind pads in the bind area must be routed to the larger display area via the fan-out area using a fan-out wiring method. The greater the difference in width between the display area and the bind area, and the more diagonal fan-out lines there are in the fan-out area, the greater the distance between the driver chip area and the display area. This increases the space occupied by the fan area, making it difficult to design a narrow lower bezel. The lower bezel is typically maintained at around 2.0 mm. In another display substrate, a normal power lead is provided in the bezel area, and the power lead continuously supplies and transmits a low-voltage power signal. In order to reduce the voltage drop of the low-voltage power signal, the width of the bezel power lead becomes large, and the width of the left and right bezels of the display device also becomes large.

[0074] FIG. 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a base, a light-emitting structure layer disposed on a side of the driving structure layer away from the base, and a packaging structure layer disposed on a side of the light-emitting structure layer away from the base. As shown in FIG. 6 , in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a binding area 200 located on a second direction Y side of the display area 100, and a bezel area 300 located on the other side of the display area 100. In an exemplary embodiment, the driving structure layer of the display area 100 may include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one of which may include a pixel driving circuit configured to output a current corresponding to a connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting units, and at least one of the light-emitting units may include a light-emitting device, which is connected to a pixel driving circuit of a corresponding circuit unit, and which is configured to emit light of a corresponding brightness in response to a current output by the pixel driving circuit connected to it.

[0075] In an exemplary embodiment, the circuit unit in this disclosure refers to an area divided for each pixel driving circuit, and the light-emitting unit in this disclosure refers to an area divided for each light-emitting device. In an exemplary embodiment, the position and shape of the orthogonal projection on the base of the light-emitting unit may correspond to the position and shape of the orthogonal projection on the base of the circuit unit, or the position and shape of the orthogonal projection on the base of the light-emitting unit may not correspond to the position and shape of the orthogonal projection on the base of the circuit unit.

[0076] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as unit rows, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as unit columns, where the plurality of unit rows and the plurality of unit columns form an array of circuit units, and the first direction X and the second direction Y intersect.

[0077] In an exemplary embodiment, the driving structure layer of the display area 100 may further include a plurality of data signal lines 60, a plurality of first connecting lines 70, and a plurality of second connecting lines 80. The data signal lines 60 are respectively connected to a plurality of pixel driving circuits in one unit column and configured to supply data signals to the connected pixel driving circuits. First ends of the plurality of first connecting lines 70 are connected to corresponding data signal lines 60, and second ends of the plurality of first connecting lines 70 are connected to corresponding second connecting lines 80. The first connecting lines 70 and the second connecting lines 80 constitute data connecting lines, forming a structure in which the data connecting lines are located in the display area (Fanout in AA, abbreviated as FIAA). Some of the data connecting lines 60 are connected to the leading lines 210 of the bind area 200 via data connecting lines, and other parts of the data signal lines 60 are directly connected to the leading lines 210 of the bind area 200.

[0078] In an exemplary embodiment, the bind area 200 may include a lead area 201 connected to the display area 100, a bend area, and a driver chip area, which are sequentially arranged along a direction away from the display area, the lead area 201 being connected to the display area 100, and the bend area being connected to the lead area 201. The lead area 201 may be provided with a plurality of lead-out lines 210, which may extend along a direction away from the display area, with first ends of some of the lead-out lines 210 connected to corresponding data connection lines 60 of the display area 100 and first ends of other lead-out lines connected to corresponding second connection lines 80 of the display area 100, and second ends of the plurality of lead-out lines 210 extending along the second direction Y and crossing the bend area before being connected to a driver chip in the driver chip area, so that the driver chip applies a data signal supplied from the driver chip to the data signal line 60 via the lead-out line 210. Since the first connecting line 70 and the second connecting line 80 are arranged in the display area, the length of the lead wire area in the second direction Y can be effectively shortened, the width of the lower bezel can be significantly shortened, the screen occupancy rate can be improved, and it is advantageous for realizing full-screen display.

[0079] In an exemplary embodiment, the lead-out line 210 may be directly connected to the data signal line 60 and the second connection line 80 or may be connected through a via, and the present disclosure is not limited thereto.

[0080] In an exemplary embodiment, the first connection line 70 may have a linear shape extending along the first direction X, the second connection line 80 may have a linear shape extending along the second direction Y, and the data signal line 60 may have a linear shape extending along the second direction Y. In an exemplary embodiment, the first connection line 70 may be disposed perpendicular to the data signal line 60, and the second connection line 80 may be disposed parallel to the data signal line 60.

[0081] In the present disclosure, "A extends along direction B" means that A may include a main portion and a sub-portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being longer than the length of the sub-portion extending along direction B. In the following description, "A extends along direction B" always means "the main body of A extends along direction B." In an exemplary embodiment, the second direction Y may be a direction from the display area toward the binding area, and the opposite direction of the second direction Y may be a direction from the binding area toward the display area.

[0082] 6, the driving structure layer of the display area 100 may further include a plurality of power supply lines 90. In an exemplary embodiment, the power supply lines 90 may have a linear shape extending along the second direction Y, and the plurality of power supply lines 90 may be sequentially arranged along the first direction X.

[0083] In an exemplary embodiment, the power supply wiring 90 may be disposed between two data signal lines 60 adjacent to each other in the first direction X.

[0084] In an exemplary embodiment, the power supply wiring 90 and the second connecting line 80 may be provided on the same layer and may be synchronously formed by the same patterning process. At least one circuit row may be provided with only the power supply wiring 90, and the second connecting line 80 may not be provided in that circuit row. At least one circuit row may be provided with the power supply wiring 90 and the second connecting line 80, and a break DF configured to achieve insulation between the power supply wiring 90 and the second connecting line 80 may be provided between the power supply wiring 90 and the second connecting line 80.

[0085] In an exemplary embodiment, the plurality of power supply lines 90 may be lines that continuously supply low-voltage signals. For example, the power supply lines may be second power supply lines VSS. The plurality of power supply lines 90 may be connected to power supply lead lines provided in the bind region or bezel region. The present disclosure realizes a structure in which low-voltage power supply lines are provided in subpixels (VSS in pixels) by providing power supply lines in the display region, which effectively reduces the resistance of power supply signal lines and the voltage drop of low-voltage power supply signals, thereby achieving low power consumption. This effectively improves the uniformity of power supply signals on the display substrate, effectively improving display uniformity and display attributes and quality. Furthermore, the structure in which low-voltage power supply lines are provided in subpixels can significantly reduce the width of power supply lead lines in the bezel region and bind region, which is advantageous for achieving a narrow bezel.

[0086] In an exemplary embodiment, the display substrate has a center line O, and the plurality of data signal lines 60, the plurality of first connecting lines 70, the plurality of second connecting lines 80, the plurality of power supply wirings 90 and the plurality of lead-out lines 210 on the display substrate may be arranged symmetrically with respect to the center line O, and the center line O may be a straight line that equally divides the plurality of unit columns of the display area 100 and extends along the second direction Y.

[0087] In an exemplary embodiment, the driving structure layer may include multiple conductive layers, the first connecting line 70 and the second connecting line 80 may be provided in different conductive layers, the data signal line 60 and the second connecting line 80 may be provided in the same conductive layer, the first connecting line 70 may be connected to the data signal line 60 through a first connecting hole, and the second connecting line 80 may be connected to the first connecting line 70 through a second connecting hole.

[0088] 7 is a schematic diagram of the arrangement of data connecting lines according to an exemplary embodiment of the present disclosure, illustrating a structure of six data signal lines, two data connecting lines, and six lead-out lines in the left region of the display substrate. As shown in FIG. 7, in the exemplary embodiment, the plurality of data signal lines in the left region may include data signal line 60-1 to data signal line 60-6, the plurality of first connecting lines may include first connecting line 70-1 and first connecting line 70-2, the plurality of second connecting lines 80 may include second connecting line 80-1 and second connecting line 80-2, and the plurality of lead-out lines may include lead-out line 210-1 to lead-out line 210-6.

[0089] In an exemplary embodiment, the data signal lines 60-1 to 60-6 may be linear and extend along the second direction Y, and may be arranged in ascending order of numbers along the first direction X. The first connection lines 70-1 and 70-2 may be linear and extend along the first direction X, and may be arranged in ascending order of numbers along the second direction Y. The second connection lines 80-1 and 80-2 may be linear and extend along the second direction Y, and may be arranged in ascending order of numbers along the first direction X.

[0090] In the exemplary embodiment, the first end of the first connection line 70-1 is connected to the data signal line 60-1 through the first connection hole K1, the second end of the first connection line 70-1 extends along the first direction X and then connects to the first end of the second connection line 80-1 through the second connection hole K2, the second end of the second connection line 80-1 extends along the second direction Y to the bind region and then connects to the first end of the lead-out line 210-1, and the second end of the lead-out line 210-1 extends along the second direction Y, beyond the bend region, and then connects to the driver chip in the driver chip region, thereby realizing that the lead-out line 210-1 is connected to the data signal line 60-1 through the second connection line 80-1 and the first connection line 70-1.

[0091] In the exemplary embodiment, the first end of the first connection line 70-2 is connected to the data signal line 60-2 through the first connection hole K1, the second end of the first connection line 70-2 extends along the first direction X and then connects to the first end of the second connection line 80-2 through the second connection hole K2, the second end of the second connection line 80-2 extends along the second direction Y to the bind region and then connects to the first end of the lead-out line 210-2, and the second end of the lead-out line 210-2 extends along the second direction Y, beyond the bend region, and then connects to the driver chip in the driver chip region, thereby realizing that the lead-out line 210-2 is connected to the data signal line 60-2 through the second connection line 80-2 and the first connection line 70-2.

[0092] In the exemplary embodiment, the data signal lines 60-3 to 60-6 extend along the second direction Y to the bind region and are then connected to corresponding first ends of the lead-out lines 210-3 to 210-6, and the second ends of the lead-out lines 210-3 to 210-6 extend along the second direction Y, pass through the bend region, and are then connected to the driver chip in the driver chip region.

[0093] In an exemplary embodiment, the order of pins connected to the lead-out lines in the driver chip is an insertion order, where the second pin (the pin connected to lead-out line 210-2) is inserted between the third pin (the pin connected to lead-out line 210-3) and the fourth pin (the pin connected to lead-out line 210-4), and the first pin (the pin connected to lead-out line 210-1) is inserted between the fourth pin and the fifth pin (the pin connected to lead-out line 210-5). The driver chip utilizes an insertion order design to achieve data signal output without sudden load changes and improve display attributes. In an exemplary embodiment, the insertion order design is only one implementation method, and a forward order design may also be adopted in actual designs. For example, an over-line design may be used to match the order of pin output signals from the driver chip with the arrangement order of data signal lines in the display area.

[0094] In an exemplary embodiment, the spacing between adjacent first connecting lines 70 in the second direction Y may be the same or different, and the spacing between adjacent second connecting lines 80 in the first direction X may be the same or different, and the present disclosure is not limited thereto.

[0095] In an exemplary embodiment, at least one second connection line 80 may be provided between two data signal lines 60 adjacent to each other in the first direction X.

[0096] The present disclosure provides a data connection line including a first connection line and a second connection line within the display area, and connects the pull-out line of the binding area to the data signal line via the data connection line, thereby eliminating the need to provide a fan-shaped diagonal line in the pull-out line area, effectively shortening the length of the pull-out line area, significantly shortening the width of the lower bezel, improving the screen occupancy rate, and advantageously realizing full-screen display.

[0097] An exemplary embodiment of the present disclosure provides a display substrate, the display substrate including a display area, the display area including a driving structure layer disposed on a base, the driving structure layer including at least a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, the first direction intersecting the second direction, the circuit units including pixel driving circuits, at least one data signal line connected to the plurality of pixel driving circuits of one unit column, first ends of the plurality of first connecting lines connected to corresponding ones of the plurality of data signal lines, second ends of the plurality of first connecting lines connected to corresponding ones of the plurality of second connecting lines, the pixel driving circuits of adjacent unit columns being mirror-symmetrical with respect to a center line, the center line being a straight line located between the adjacent unit columns and extending along the second direction, the second connecting line being disposed in a gap between the pixel driving circuits of the adjacent unit columns.

[0098] In one exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and the minimum distance in the first direction between the second connecting line and the adjacent data signal line is greater than the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0099] In another exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and the minimum distance in the first direction between the second connecting line and the adjacent data signal line is 1 / 2 of the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0100] In an exemplary embodiment, the driving structure layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are provided in gaps between the pixel driving circuits of adjacent unit columns.

[0101] In one exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power supply wiring, and the minimum distance in the first direction between the power supply wiring and the adjacent data signal line is greater than the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0102] In another exemplary embodiment, two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power supply wiring, and the minimum distance in the first direction between the power supply wiring and the adjacent data signal line is 1 / 2 of the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

[0103] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving structure layer includes a plurality of conductive layers sequentially arranged on a base, the first connecting line and the second connecting line being arranged on different conductive layers, and the data signal line and the second connecting line being arranged on the same conductive layer.

[0104] In an exemplary embodiment, the plurality of conductive layers include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially disposed along a direction away from the base, the first connection line is disposed in the second source-drain metal layer, the data signal line and the second connection line are disposed in the third source-drain metal layer, the data signal line is connected to a first end of the first connection line through a via, and the second connection line is connected to a second end of the first connection line through a via.

[0105] In an exemplary embodiment, the third source-drain metal layer further includes a plurality of power supply wirings extending along the second direction, the power supply wirings being provided in gaps between the pixel driving circuits of adjacent unit columns.

[0106] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor and a plurality of transistors, and the plurality of conductive layers include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are sequentially arranged along a direction away from the base, the shielding layer including at least a shielding electrode, the first semiconductor layer including at least active layers of a plurality of low-temperature polysilicon transistors, and the first gate metal layer including at least a first scanning signal line, an emission signal line, a second gate metal layer, a third gate metal layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are sequentially arranged along a direction away from the base, the shielding layer including at least a shielding electrode, the first semiconductor layer including at least active layers of a plurality of low-temperature polysilicon transistors, and the first gate metal layer including at least a first scanning signal line, an emission signal line, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, the second gate metal layer includes at least the second plate of the storage capacitor; the second semiconductor layer includes at least the active layers of a plurality of oxide transistors; the third gate metal layer includes at least a second scanning signal line and a third scanning signal line; the first source-drain metal layer includes at least a second initial signal line having a network connection structure; the second source-drain metal layer includes at least a shield electrode and the first connecting line; and the third source-drain metal layer includes at least a first power line, the data signal line, and the second connecting line.

[0107] In an exemplary embodiment, the plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the first transistor and the second transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low temperature polysilicon transistors.

[0108] 8 is a schematic planar structure diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a pixel driving circuit structure of eight circuit units (two unit rows, four unit columns) in a display area. In an exemplary embodiment, the display substrate may include a display area, which may include at least a driving structure layer disposed on a base and a light-emitting structure layer disposed on a side of the driving structure layer away from the base. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting at least a plurality of unit rows and a plurality of unit columns, where the plurality of circuit units in each unit row are sequentially arranged along a first direction X, the plurality of unit rows are sequentially arranged along a second direction Y, the plurality of circuit units in each unit column are sequentially arranged along the second direction Y, and the plurality of unit columns are sequentially arranged along the first direction X, where the first direction X intersects with the second direction Y. In an exemplary embodiment, the driving structure layer may further include a plurality of data signal lines 60 extending along the second direction Y, a plurality of first connecting lines 70 extending along the first direction X, and a plurality of second connecting lines 80 extending along the second direction Y, and the circuit unit may include a pixel driving circuit, where at least one data signal line 60 is electrically connected to a plurality of pixel driving circuits in one unit column, and the data signal line 60 is configured to supply a data signal to the connected pixel driving circuit. In an exemplary embodiment, first ends of the plurality of first connecting lines 70 are connected to corresponding ones of the plurality of data signal lines 60, and second ends of the plurality of first connecting lines 70 are connected to corresponding ones of the plurality of second connecting lines 80, and the first connecting lines 70 and the second connecting lines 80 are configured to supply a data signal to the connected data signal line 60.

[0109] In this disclosure, "A extends along direction B" means that A may include a main portion and a sub-portion connected to the main portion, the main portion being a line, line segment or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being longer than the length of the sub-portion extending along direction B. In the following description, "A extends along direction B" always means "the main body of A extends along direction B."

[0110] In an exemplary embodiment, the pixel driving circuits of adjacent unit columns may be mirror-symmetric with respect to a center line, and the center line may be a straight line located between two adjacent unit columns and extending along the second direction Y. The symmetrical structure forms gaps between the pixel driving circuits of adjacent unit columns, and multiple second connecting lines 80 may be respectively provided in the gaps between the pixel driving circuits of the adjacent unit columns.

[0111] In an exemplary embodiment, at least one second connecting line 80 may be provided between two data signal lines 60 of adjacent unit columns, and the two data signal lines 60 may be mirror-symmetric with respect to the second connecting line 80.

[0112] In an exemplary embodiment, the minimum distance L1 in the first direction X between at least one second connection line 80 and an adjacent data signal line 60 may be greater than the minimum distance L3 in the first direction X between two data signal lines 60 in adjacent unit columns.

[0113] In an exemplary embodiment, the driving structure layer may include a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially disposed on a base in a plane perpendicular to the display substrate, the second source-drain metal layer may include at least a first connecting line 70, and the third source-drain metal layer may include at least a data signal line 60 and a second connecting line 80, i.e., the first connecting line 70 and the second connecting line 80 are disposed in different conductive layers, and the data signal line 60 and the second connecting line 80 are disposed in the same conductive layer.

[0114] In an exemplary embodiment, the data signal line 60 may be connected to a first end of the first connection line 70 via the first wrap pier K1, and the second connection line 80 may be connected to a second end of the first connection line 70 via the second wrap pier K2. That is, the second connection line 80 extending along the second direction Y and located in the third source-drain metal layer is connected to the first connection line 70 extending along the first direction X and located in the second source-drain metal layer via the first wrap pier K1, and the first connection line 70 extending along the first direction X and located in the second source-drain metal layer is connected to the data signal line 60 extending along the second direction Y and located in the third source-drain metal layer via the second wrap pier K2.

[0115] In an exemplary embodiment, the driving structure layer may further include a plurality of power supply wirings 90 extending along the second direction Y, and the plurality of power supply wirings 90 may be respectively provided in the gaps between the pixel driving circuits of adjacent unit columns.

[0116] In an exemplary embodiment, at least one power supply wiring 90 may be provided between two data signal lines 60 of adjacent unit columns, and the two data signal lines 60 may be mirror-symmetric with respect to the power supply wiring 90.

[0117] In an exemplary embodiment, the minimum distance L2 in the first direction X between at least one power supply wiring 90 and an adjacent data signal line 60 may be greater than the minimum distance L3 in the first direction X between two data signal lines 60 in adjacent unit columns.

[0118] In an exemplary embodiment, the power supply wiring 90 may be provided in the third source-drain metal layer.

[0119] In an exemplary embodiment, the pixel driving circuit may include at least a first transistor, a second transistor, and a storage capacitor, where the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, and the second region of the first active layer and the first region of the second active layer are connected to each other as an integral structure and to a first plate of the storage capacitor via a first connecting electrode. At least one circuit unit may further include a shield electrode 63, where an orthogonal projection at a base of the shield electrode 63 at least partially overlaps with an orthogonal projection at a base of the second region of the first active layer and the first region of the second active layer, and where an orthogonal projection at the base of the shield electrode 63 at least partially overlaps with an orthogonal projection at a base of the first connecting electrode.

[0120] In an exemplary embodiment, the at least one circuit unit may further include a first power supply line 64 , which may be connected to the shield electrode 63 .

[0121] In an exemplary embodiment, a shield electrode 63 may be provided in the second source-drain metal layer, a first power supply line 64 may be provided in the third source-drain metal layer, and the first power supply line 64 may be connected to the shield electrode 63 through a via.

[0122] In an exemplary embodiment, the pixel driving circuit may include at least a fourth transistor, and the data signal line 60 may be connected to a first electrode of the fourth transistor in the pixel driving circuit via a data connecting electrode 61. In at least one circuit unit, the first connecting line 70 is connected to the data connecting electrode 61.

[0123] In an exemplary embodiment, at least one circuit unit may further include a data connection block 72, a first end of which is connected to the first connection line 70, and a second end of which is connected to the data connection electrode 61.

[0124] In the exemplary embodiment, the first connection line 70, the data connection block 72 and the data connection electrode 61 are provided in the same layer and are connected to each other in an integrated structure.

[0125] In an exemplary embodiment, the plurality of transistors may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the first transistor and the second transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low-temperature polysilicon transistors.

[0126] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor and a plurality of transistors, and the plurality of conductive layers may include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are sequentially arranged along a direction away from the base. The shielding layer may include at least a shielding electrode, the first semiconductor layer may include at least active layers of a plurality of low-temperature polysilicon transistors, the first gate metal layer may include at least a first scanning signal line, a light-emitting signal line and a first plate of a storage capacitor, the second gate metal layer may include at least a second plate of the storage capacitor, the second semiconductor layer may include at least active layers of a plurality of oxide transistors, the third gate metal layer may include at least a second scanning signal line and a third scanning signal line, the first source-drain metal layer may include at least a second initial signal line having a network connection structure, the second source-drain metal layer may include at least a shielding electrode and a first connecting line, and the third source-drain metal layer may include at least a first power line, a data signal line and a second connecting line.

[0127] The manufacturing process of a display substrate is described below by way of example. The "patterning process" described in this disclosure includes processes such as photoresist application, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, and transparent conductive materials, and organic material application, mask exposure, and development for organic materials. Deposition may include one or more of sputtering, evaporation, and chemical vapor deposition. Coating may include one or more of spraying, spin coating, and inkjet printing. Etching may include one or more of dry etching and wet etching, but the present disclosure is not limited to these processes. A "thin film" refers to a thin film layer fabricated on a base material by deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern." In the present disclosure, "A and B are disposed on the same layer" means that A and B are formed simultaneously by the same patterning process. The "thickness" of a film layer is the size of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of the present disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" or "the orthogonal projection of A includes the orthogonal projection of B" means that the boundary of the orthogonal projection of B is within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0128] In an exemplary embodiment, taking eight circuit units (two unit rows, four unit columns) as an example, the manufacturing process of the driving structure layer may include the following operations:

[0129] (1) Forming a shielding layer pattern: In an exemplary embodiment, as shown in Figure 9, forming a shielding layer pattern may include depositing a shielding thin film on a base, patterning the shielding thin film by a patterning process, and forming a shielding layer pattern on the base.

[0130] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a first shielding connecting line 91 , a second shielding connecting line 92 , a third shielding connecting line 93 and a shielding electrode 94 .

[0131] In the exemplary embodiment, the shielding electrode 94 may be rectangular, and the corners of the rectangle may be chamfered. The first shielding connecting line 91 may be linear and extend along the first direction X, and may be located on the first direction X side of the shielding electrode 94 and connected to the shielding electrode 94. The second shielding connecting line 92 may be polygonal and extend along the second direction Y, and may be located on the second direction Y side of the shielding electrode 94 and connected to the shielding electrode 94. The third shielding connecting line 93 may be polygonal and extend along the second direction Y, and may be located on the opposite side of the shielding electrode 94 in the second direction Y and connected to the shielding electrode 94.

[0132] In the exemplary embodiment, the first shielding connecting line 91 of each circuit unit is connected to the shielding electrode 94 of the adjacent circuit unit in the first direction X, so that the shielding layers of one unit row are integrally connected to form an integral structure connected to each other.

[0133] In an exemplary embodiment, the second shielding connecting line 92 of each circuit unit is connected to the third shielding connecting line 93 of the adjacent circuit unit in the second direction Y, so that the shielding layers of one unit row are integrally connected to form an integral structure that is connected to each other.

[0134] In an exemplary embodiment, the shielding layers of the unit rows and unit columns are connected together to ensure that the shielding layers on the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0135] In an exemplary embodiment, the shielding layers of adjacent unit rows may be mirror-symmetric with respect to the center line, which may be a straight line located between the adjacent unit rows and extending along the second direction Y. For example, the shielding layer of the Nth row and the shielding layer of the N+1th row may be mirror-symmetric with respect to the center line, the shielding layer of the N+1th row and the shielding layer of the N+2th row may be mirror-symmetric with respect to the center line, and the shielding layer of the N+2th row and the shielding layer of the N+3th row may be mirror-symmetric with respect to the center line.

[0136] In an exemplary embodiment, the shapes of the shielding layers of the multiple unit rows may be essentially the same.

[0137] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 10 and 11, forming the first semiconductor layer pattern may include sequentially depositing a first insulating thin film and a first semiconductor thin film on a base, patterning the first semiconductor thin film by a patterning process, and forming a first insulating layer covering the shielding layer and a first semiconductor layer pattern provided on the first insulating layer. Figure 11 is a schematic plan view of the first semiconductor layer in Figure 10.

[0138] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7, and the third active layer 13 to the seventh active layer 17 are an integral structure connected to each other.

[0139] In the exemplary embodiment, an orthogonal projection of the third active layer 13 at the base at least partially overlaps with an orthogonal projection of the shielding electrode 94 at the base. In the first direction X, the sixth active layer 16 may be located on one side of the third active layer 13 in the first direction X of the circuit unit, and the fourth active layer 14 and the fifth active layer 15 may be located on the opposite side of the third active layer 13 in the first direction X of the circuit unit. In the second direction Y, the fourth active layer 14 in the Mth circuit unit may be located on a side of the third active layer 13 closer to the (M+1)th circuit unit in the circuit unit, and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 in the Mth circuit unit may be located on a side of the third active layer 13 away from the (M+1)th circuit unit in the circuit unit, where M may be a positive integer greater than or equal to 1.

[0140] In an exemplary embodiment, the third active layer 13 may have an inverted Ω shape, the fourth active layer 14 and the fifth active layer 15 may have an I shape, and the sixth active layer 16 and the seventh active layer 17 may have an L shape.

[0141] In an exemplary embodiment, each of the third active layer 13 to the seventh active layer 17 may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer may simultaneously be the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, the second region 13-2 of the third active layer may simultaneously be the first region 16-1 of the sixth active layer, and the second region 16-2 of the sixth active layer may simultaneously be the second region 17-2 of the seventh active layer. Alternatively, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be provided separately.

[0142] In an exemplary embodiment, the first region 17-1 of the seventh active layer in the circuit unit in the (M+1)th row may be provided in the circuit unit in the Mth row.

[0143] In an exemplary embodiment, in one unit row, the first regions 15-1 of the fifth active layers of two adjacent circuit units may be connected to each other. For example, the first region 15-1 of the fifth active layer in the (N+1)th column and the first region 15-1 of the fifth active layer in the (N+2)th column are connected to each other. Since the first region of the fifth active layer in each circuit unit is configured to be connected to a first power line to be formed later, forming the first regions of the fifth active layers of adjacent circuit units into an integrated structure that connects them to each other can ensure that the first electrodes of the fifth transistors T5 of adjacent circuit units have the same potential, which is beneficial to improving panel uniformity, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0144] In an exemplary embodiment, the first semiconductor layers of adjacent unit columns may be mirror-symmetric with respect to the center line. For example, the first semiconductor layer of the Nth column and the first semiconductor layer of the N+1th column may be mirror-symmetric with respect to the center line, the first semiconductor layer of the N+1th column and the first semiconductor layer of the N+2th column may be mirror-symmetric with respect to the center line, and the first semiconductor layer of the N+2th column and the first semiconductor layer of the N+3th column may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the first semiconductor layers in multiple unit columns may be essentially the same.

[0145] In an exemplary embodiment, the first semiconductor layer may be made of polysilicon (p-Si), i.e., the third to seventh transistors may be LTPS transistors. In an exemplary embodiment, patterning the first semiconductor thin film by a patterning process may include first forming an amorphous silicon (a-Si) thin film on the first insulating thin film, subjecting the amorphous silicon thin film to a dehydrogenation treatment, and subjecting the dehydrogenated amorphous silicon thin film to a crystallization treatment to form a polycrystalline silicon thin film. The polycrystalline silicon thin film is then patterned to form the first semiconductor layer pattern.

[0146] (3) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 12 and 13, forming the first conductive layer pattern may include sequentially depositing a second insulating thin film and a first conductive thin film on the base on which the above-mentioned pattern is formed, patterning the first conductive thin film by a patterning process, and forming a second insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern provided on the second insulating layer. FIG. 13 is a schematic plan view of the first conductive layer in FIG. 12. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0147] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scanning signal line 21, a light emitting signal line 22, and a first plate 23 of a storage capacitor.

[0148] In an exemplary embodiment, the first plate 23 may be rectangular in shape, with chamfered corners, and the orthogonal projection of the base of the first plate 23 at least partially overlaps the orthogonal projection of the base of the third active layer of the third transistor T3. In an exemplary embodiment, the first plate 23 may simultaneously be one plate of a storage capacitor and the gate electrode of the third transistor T3.

[0149] In an exemplary embodiment, the shape of the first scanning signal line 21 may be a line whose main body extends along the first direction X, the first scanning signal line 21 in the circuit unit in the Mth row may be located on a side of the first electrode plate 23 of this circuit unit that is closer to the circuit unit in the (M+1)th row, the region in the circuit unit in the Mth row where the first scanning signal line 21 overlaps with the fourth active layer of this circuit unit may be the gate electrode of the fourth transistor T4, and the region in the circuit unit in the Mth row where the first scanning signal line 21 overlaps with the seventh active layer of the circuit unit in the (M+1)th row may be the gate electrode of the seventh transistor T7.

[0150] In an exemplary embodiment, the shape of the light-emitting signal line 22 may be a line whose main body extends along the first direction X, and the light-emitting signal line 22 in the circuit unit in the Mth row may be located on the side of the first electrode plate 23 of this circuit unit away from the circuit unit in the (M+1)th row, and the area where the light-emitting signal line 22 overlaps with the fifth active layer of this circuit unit is the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 22 overlaps with the sixth active layer of this circuit unit is the gate electrode of the sixth transistor T6.

[0151] In an exemplary embodiment, the first scanning signal line 21 and the light-emitting signal line 22 may be set to have unequal widths, and the widths of the first scanning signal line 21 and the light-emitting signal line 22 are the dimensions in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines, and the present disclosure is not limited thereto.

[0152] In an exemplary embodiment, the first scanning signal line 21 may include a region that overlaps with the first semiconductor layer and a region that does not overlap with the first semiconductor layer, and the width of the first scanning signal line 21 in the region that overlaps with the first semiconductor layer may be smaller than the width of the first scanning signal line 21 in the region that does not overlap with the first semiconductor layer.

[0153] In an exemplary embodiment, the light-emitting signal line 22 may include an area that overlaps with the first semiconductor layer and an area that does not overlap with the first semiconductor layer, and the width of the first scanning signal line 21 in the area that overlaps with the first semiconductor layer may be greater than the width of the first scanning signal line 21 in the area that does not overlap with the first semiconductor layer.

[0154] In an exemplary embodiment, the first conductive layers of adjacent unit columns may be mirror-symmetric with respect to the center line. For example, the first conductive layer of the Nth column and the first conductive layer of the N+1th column may be mirror-symmetric with respect to the center line, the first conductive layer of the N+1th column and the first conductive layer of the N+2th column may be mirror-symmetric with respect to the center line, and the first conductive layer of the N+2th column and the first conductive layer of the N+3th column may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the first conductive layers in multiple unit columns may be essentially the same.

[0155] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer may be treated to be conductive, using the first conductive layer as a shielding portion, so that the first semiconductor layer in the area shielded by the first conductive layer forms the channel regions of the third transistor T3 to the seventh transistor T7, and the first semiconductor layer in the area not shielded by the first conductive layer is made conductive, i.e., the first and second regions of the active layers of the third transistor T3 to the seventh transistor T7 are both made conductive.

[0156] (4) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 14 and 15, forming the second conductive layer pattern may include sequentially depositing a third insulating thin film and a second conductive thin film on the base on which the above-mentioned pattern is formed, patterning the second conductive thin film by a patterning process, and forming a third insulating layer covering the first conductive layer and a second conductive layer pattern provided on the third insulating layer. FIG. 15 is a schematic plan view of the second conductive layer in FIG. 14. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0157] In the exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a first initial signal line 31, a second shielding line 32, a third shielding line 33, and a second plate 34 of the storage capacitor.

[0158] In an exemplary embodiment, the outline of the second plate 34 may be rectangular, the corners of the rectangle may be chamfered, the orthogonal projection of the second plate 34 at the base may at least partially overlap the orthogonal projection of the first plate 23 at the base, and the second plate 34 may be the other plate of a memory capacitor, with the first plate 23 and the second plate 34 forming the memory capacitor of the pixel driving circuit.

[0159] In an exemplary embodiment, an opening 35 is provided in the second plate 34, and the opening 35 may be rectangular in shape and may be located in the center of the second plate 34 so that the second plate 34 forms a ring-shaped structure. The opening 35 exposes the third insulating layer covering the first plate 23, and the orthogonal projection of the first plate 23 at its base includes the orthogonal projection of the opening 35 at its base. In an exemplary embodiment, the opening 35 is configured to accommodate a first via to be formed later, and the first via is located inside the opening 35 to expose the first plate 23 and connect the second pole of the first transistor T1 to the first plate 23, which will be formed later.

[0160] In an exemplary embodiment, portions of the second plates 34 of two adjacent circuit units in one unit row may be connected to each other. For example, the second plate 34 of the (N+1)th column and the second plate 34 of the (N+2)th column are connected to each other as an integral structure. In an exemplary embodiment, the second plate 34 of each circuit unit is connected to a first power line to be formed subsequently. Therefore, by forming the second plates 34 of adjacent circuit units to be connected to each other as an integral structure, the integral second plates can be multiplexed as power signal lines, ensuring that the multiple second plates in one unit row have the same potential, which is beneficial to improving panel uniformity, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0161] In an exemplary embodiment, the shape of the first initial signal line 31 may be a line whose main body extends along the first direction X, and the first initial signal line 31 in the circuit unit in the Mth row may be located on the side of the second electrode plate 34 of the circuit unit that is closer to the circuit unit in the (M+1)th row.

[0162] In an exemplary embodiment, the second shielding wire 32 and the third shielding wire 33 may have a linear shape with their main body extending along the first direction X, and the second shielding wire 32 and the third shielding wire 33 in the Mth row of circuit units may be located between the first initial signal line 31 and the second electrode plate 34 of the circuit unit, and the second shielding wire 32 may be located on the side of the third shielding wire 33 away from the second electrode plate 34, that is, the third shielding wire 33 may be located between the second shielding wire 32 and the second electrode plate 34.

[0163] In an exemplary embodiment, the second shielding line 32 is configured to shield a first active layer of a first transistor, and the third shielding line 33 is configured to shield a second active layer of a second transistor. The second shielding line 32 and the third shielding line 33 may have unequal widths, and the widths of the second shielding line 32 and the third shielding line 33 are the same as the width in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between signal lines, and the present disclosure is not limited thereto.

[0164] In an exemplary embodiment, the second conductive layers of adjacent unit columns may be mirror-symmetric with respect to the center line. For example, the second conductive layer of the Nth column and the second conductive layer of the N+1th column may be mirror-symmetric with respect to the center line, the second conductive layer of the N+1th column and the second conductive layer of the N+2th column may be mirror-symmetric with respect to the center line, and the second conductive layer of the N+2th column and the second conductive layer of the N+3th column may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the second conductive layers in multiple unit columns may be essentially the same.

[0165] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 16 and 17, forming the second semiconductor layer pattern may include sequentially depositing a fourth insulating thin film and a second semiconductor thin film on the base on which the pattern is formed, patterning the second semiconductor thin film using a patterning process, and forming a fourth insulating layer covering the base and a second semiconductor layer pattern disposed on the fourth insulating layer. Figure 17 is a schematic plan view of the second semiconductor layer of Figure 16.

[0166] In the exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2.

[0167] In an exemplary embodiment, the first active layer 11 and the second active layer 12 may have an "I" shape, and the first active layer 11 in the Mth row of circuit units may be located on the side of the second active layer 12 of that circuit unit closer to the M+1th row of circuit units.

[0168] In an exemplary embodiment, the orthogonal projection at the base of the first active layer 11 at least partially overlaps with the orthogonal projection at the base of the second shielding line 32, and the orthogonal projection at the base of the second active layer 12 at least partially overlaps with the orthogonal projection at the base of the third shielding line 33.

[0169] In an exemplary embodiment, the first active layer 11 and the second active layer 12 may both include a first region, a second region, and a channel region located between the first region and the second region. The first region 11-1 of the first active layer may be located on a side of the second shielding line 32 away from the second active layer 12, and the second region 11-2 of the first active layer may be located on a side of the second shielding line 32 closer to the second active layer 12. The first region 12-1 of the second active layer may be located on a side of the third shielding line 33 away from the first active layer 11, and the second region 12-2 of the second active layer may be located on a side of the third shielding line 33 closer to the first active layer 11.

[0170] In an exemplary embodiment, the second region 11-2 of the first active layer may be the first region 12-1 of the second active layer, i.e., the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be an integral structure connected to each other and located between the second shielding line 32 and the third shielding line 33.

[0171] In an exemplary embodiment, the orthogonal projections at the base of the second region 11-2 of the first active layer and the first region 12-1 of the second active layer of the integral structure at least partially overlap with the orthogonal projections at the base of the first scanning signal line 21 in the circuit unit.

[0172] In an exemplary embodiment, the second semiconductor layers of adjacent unit columns may be mirror-symmetric with respect to the center line. For example, the second semiconductor layer of the Nth column and the second semiconductor layer of the N+1th column may be mirror-symmetric with respect to the center line, the second semiconductor layer of the N+1th column and the second semiconductor layer of the N+2th column may be mirror-symmetric with respect to the center line, and the second semiconductor layer of the N+2th column and the second semiconductor layer of the N+3th column may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the second semiconductor layers in multiple unit columns may be essentially the same.

[0173] In an exemplary embodiment, the second semiconductor layer may be an oxide, i.e., the first transistor T1 and the second transistor T2 may be oxide transistors. In an exemplary embodiment, the second semiconductor thin film may employ indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0174] (6) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 18 and 19, forming the third conductive layer pattern may include sequentially depositing a fifth insulating thin film and a third conductive thin film on the base on which the above-mentioned pattern is formed, patterning the third conductive thin film by a patterning process, and forming a fifth insulating layer covering the second semiconductor layer and a third conductive layer pattern provided on the fifth insulating layer. FIG. 19 is a schematic plan view of the third conductive layer in FIG. 18. In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0175] In the exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a second scanning signal line 41 and a third scanning signal line 42 .

[0176] In an exemplary embodiment, the second scanning signal line 41 and the third scanning signal line 42 may have a linear shape with their main bodies extending along the first direction X. The second scanning signal line 41 and the third scanning signal line 42 in the circuit unit of the Mth row may be located between the first initial signal line 31 and the second electrode plate 34 of the circuit unit, and the second scanning signal line 41 may be located on the side of the third scanning signal line 42 away from the second electrode plate 34, i.e., the third scanning signal line 42 may be located between the second scanning signal line 41 and the second electrode plate 34.

[0177] In an exemplary embodiment, the area where the second scanning signal line 41 overlaps with the first active layer is the gate electrode of the first transistor T1, and the area where the third scanning signal line 42 overlaps with the second active layer is the gate electrode of the second transistor T2.

[0178] In an exemplary embodiment, the orthogonal projection at the base of the second scanning signal line 41 at least partially overlaps with the orthogonal projection at the base of the second shielding line 32, and the second shielding line 32 and the second scanning signal line 41 may be connected to the same signal source, so that the second shielding line 32 may be the bottom gate electrode of the first transistor T1 and the second scanning signal line 41 may be the top gate electrode of the first transistor T1, forming the first transistor T1 with a dual-gate structure.

[0179] In an exemplary embodiment, the orthogonal projection at the base of the third scanning signal line 42 at least partially overlaps with the orthogonal projection at the base of the third shielding line 33, and the third shielding line 33 and the third scanning signal line 42 may be connected to the same signal source, so that the third shielding line 33 may be the bottom gate electrode of the second transistor T2, and the third scanning signal line 42 may be the top gate electrode of the second transistor T2, forming the second transistor T2 with a dual-gate structure.

[0180] In an exemplary embodiment, the third conductive layers of adjacent unit columns may be mirror-symmetric with respect to the center line. For example, the third conductive layer of the Nth column and the third conductive layer of the N+1th column may be mirror-symmetric with respect to the center line, the third conductive layer of the N+1th column and the third conductive layer of the N+2th column may be mirror-symmetric with respect to the center line, and the third conductive layer of the N+2th column and the third conductive layer of the N+3th column may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the third conductive layers in multiple unit columns may be essentially the same.

[0181] (7) Forming a sixth insulating layer pattern. In an exemplary embodiment, as shown in Figure 20, forming the sixth insulating layer pattern may include depositing a sixth insulating thin film on the base on which the above-mentioned pattern is formed, patterning the fifth insulating thin film by a patterning process, forming a sixth insulating layer covering the third conductive layer, and providing a plurality of vias in the sixth insulating layer.

[0182] In an exemplary embodiment, the multiple vias of each circuit unit may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0183] In an exemplary embodiment, the orthogonal projection at the base of the first via V1 is located within the range of the orthogonal projection at the base of the opening 35, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the first via V1 are removed by etching to expose the surface of the first electrode plate 23, and the first via V1 is configured to connect a first connection electrode to be formed later to the first electrode plate 23 through the via.

[0184] In an exemplary embodiment, the second via V2 is located within a range of an orthogonal projection at the base of the second electrode plate 34, the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the second via V2 are etched away to expose the surface of the second electrode plate 34, and the second via V2 is configured to connect a fourth connection electrode to be formed later to the second electrode plate 34 through the via.

[0185] In an exemplary embodiment, the orthogonal projection at the base of the third via V3 is located within the range of the orthogonal projection at the base of the first region of the fifth active layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via V3 are removed by etching to expose the surface of the first region of the fifth active layer, and the third via V3 is configured to connect a fourth connection electrode to be formed later to the first region of the fifth active layer through the via.

[0186] In an exemplary embodiment, the orthogonal projection at the base of the fourth via V4 is located within the range of the orthogonal projection at the base of the second region of the sixth active layer (which is also the second region of the seventh active layer), the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are removed by etching to expose the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer), and the fourth via V4 is configured to connect a sixth connection electrode to be formed later to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0187] In an exemplary embodiment, the orthogonal projection at the base of the fifth via V5 is located within the range of the orthogonal projection at the base of the first region of the fourth active layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 are removed by etching to expose the surface of the first region of the fourth active layer, and the fifth via V5 is configured to connect a third connection electrode to be formed later to the first region of the fourth active layer through the via.

[0188] In an exemplary embodiment, the orthogonal projection at the base of the sixth via V6 is located within the range of the orthogonal projection at the base of the second region of the third active layer (which is also the first region of the sixth active layer), the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via V6 are removed by etching to expose the surface of the second region of the third active layer (which is also the first region of the sixth active layer), and the sixth via V6 is configured to connect a fifth connection electrode to be formed later to the second region of the third active layer (which is also the first region of the sixth active layer) through the via.

[0189] In an exemplary embodiment, the orthogonal projection at the base of the seventh via V7 is located within the range of the orthogonal projection at the base of the first region of the seventh active layer, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the seventh via V7 are removed by etching to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to connect a second initial signal line to be formed later to the first region of the seventh active layer through the via.

[0190] In an exemplary embodiment, the orthogonal projection at the base of the eighth via V8 is located within the range of the orthogonal projection at the base of the first region of the first active layer, the sixth insulating layer and the fifth insulating layer within the eighth via V8 are removed by etching to expose the surface of the first region of the first active layer, and the eighth via V8 is configured to connect a second connection electrode to be formed later to the first region of the first active layer through the via.

[0191] In an exemplary embodiment, the orthogonal projection at the base of the ninth via V9 is located within the range of the orthogonal projection at the base of the second region of the second active layer, the sixth insulating layer and the fifth insulating layer within the ninth via V9 are removed by etching to expose the surface of the second region of the second active layer, and the ninth via V9 is configured to connect a fifth connecting electrode to be formed later to the second region of the second active layer through the via.

[0192] In an exemplary embodiment, the orthogonal projection at the base of the tenth via V10 is located within the range of the orthogonal projection at the base of the second region of the first active layer (which is also the first region of the second active layer), the sixth insulating layer and the fifth insulating layer in the tenth via V10 are removed by etching to expose the surface of the second region of the first active layer (which is also the first region of the second active layer), and the tenth via V10 is configured to connect a first connection electrode to be formed later to the second region of the first active layer (which is also the first region of the second active layer) through the via.

[0193] In an exemplary embodiment, the orthogonal projection at the base of the 11th via V11 is located within the range of the orthogonal projection at the base of the first initial signal line 31, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the 11th via V11 are removed by etching to expose the surface of the first initial signal line 31, and the 11th via V11 is configured to connect a second connection electrode to be formed later to the first initial signal line 31 through the via.

[0194] In an exemplary embodiment, the vias in adjacent unit rows may be mirror-symmetric with respect to the centerline. For example, the vias in the Nth row and the vias in the N+1th row may be mirror-symmetric with respect to the centerline, the vias in the N+1th row and the vias in the N+2th row may be mirror-symmetric with respect to the centerline, and the vias in the N+2th row and the vias in the N+3th row may be mirror-symmetric with respect to the centerline. In an exemplary embodiment, the shapes of the vias in the multiple unit rows may be essentially the same.

[0195] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 21 and 22, forming the fourth conductive layer may include depositing a fourth conductive thin film on the base on which the pattern is formed, patterning the fourth conductive thin film by a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer. FIGS. 22 and 21 are schematic plan views of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0196] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a second initial signal line 57, and a second initial connection line 58.

[0197] In an exemplary embodiment, the first connection electrode 51 may have a polygonal line shape with its main body extending along the second direction Y, with a first end of the first connection electrode 51 connected to the first plate 23 through the first via V1 and a second end of the first connection electrode 51 extending along the second direction Y and then connected to the second region of the first active layer (which is also the first region of the second active layer) through the tenth via V10, so that the first plate 23, the second pole of the first transistor T1, and the first pole of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 51 may simultaneously serve as the second pole of the first transistor T1 and the first pole of the second transistor T2 (the second node N2 of the pixel driving circuit).

[0198] In an exemplary embodiment, the second connection electrode 52 may have a stripe shape extending along the first direction X, with a first end of the second connection electrode 52 connected to the first region of the first active layer through the eighth via V8 and a second end of the second connection electrode 52 connected to the first initial signal line 31 through the eleventh via V11, thereby writing the first initial voltage transmitted by the first initial signal line 31 to the first pole of the first transistor T1. In an exemplary embodiment, the second connection electrode 52 may be the first pole of the first transistor T1.

[0199] In an exemplary embodiment, in each unit row, the second connection electrode 52 in the Nth column and the second connection electrode 52 in the N+1th column may be an integral structure connected to each other, and the second connection electrode 52 in the N+2th column and the second connection electrode 52 in the N+3th column may be an integral structure connected to each other.

[0200] In an exemplary embodiment, the third connection electrode 53 may have a rectangular shape and be connected to the first region of the fourth active layer through a fifth via V5. In an exemplary embodiment, the third connection electrode 53 may be a first pole of the fourth transistor T4, and the third connection electrode 53 is configured to be connected to an eleventh connection electrode to be formed later.

[0201] In an exemplary embodiment, the fourth connection electrode 54 may have a Y-shape, with a first end of the fourth connection electrode 54 connected to the second plate 34 through the second via V2 and a second end of the fourth connection electrode 54 connected to the first region of the fifth active layer through the third via V3, thereby realizing that the first pole of the fifth transistor T5 in the circuit unit and the second plate 34 of the storage capacitor have the same potential. In an exemplary embodiment, the fourth connection electrode 54 may be the first pole of the fifth transistor T5, and is configured to be connected to a shield electrode to be formed later.

[0202] In an exemplary embodiment, in at least one unit row, the fourth connecting electrode 54 in the (N+1)th column and the fourth connecting electrode 54 in the (N+2)th column may be connected to each other as an integral structure. In an exemplary embodiment, because the fourth connecting electrode 54 of each circuit unit is connected to a first power line to be formed later, forming the fourth connecting electrodes 54 of adjacent circuit units as an integral structure connected to each other can ensure that the fourth connecting electrodes 54 of adjacent circuit units have the same potential, such that the first electrodes of the fifth transistors T5 of adjacent circuit units have the same potential and the second plates 34 of the storage capacitors of adjacent circuit units have the same potential, which is beneficial to improving panel uniformity, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0203] In the exemplary embodiment, the orthogonal projection at the base of the fourth connecting electrode 54 at least partially overlaps with the orthogonal projection at the base of the second region of the seventh active layer, and the fourth connecting electrode 54 having a constant potential performs a shielding function and ensures the potential stability of key nodes in the pixel driving circuit.

[0204] In an exemplary embodiment, the fifth connecting electrode 55 may be rectangular in shape, with a first end of the fifth connecting electrode 55 connected to the second region of the third active layer (which is also the first region of the sixth active layer) through a sixth via V6, and a second end of the fifth connecting electrode 55 connected to the second region of the second active layer through a ninth via V9. In an exemplary embodiment, the fifth connecting electrode 55 may simultaneously serve as the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6 (the third node N3 of the pixel driving circuit).

[0205] In an exemplary embodiment, the sixth connecting electrode 56 may have a polygonal shape, and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fourth via V4. In an exemplary embodiment, the sixth connecting electrode 56 may simultaneously serve as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, and is configured to be connected to a twelfth connecting electrode that will be formed later.

[0206] In an exemplary embodiment, the second initial signal line 57 may have a polygonal shape with its main body extending along the first direction X. The second initial signal line 57 of the Mth circuit unit may be disposed on a side of the storage capacitor close to the M+1th circuit unit. The second initial signal line 57 of the Mth circuit unit is connected to a first region of the seventh active layer of the M+1th circuit unit through a seventh via V7, thereby writing the second initial voltage transmitted by the second initial signal line 57 to the first pole of the seventh transistor T7. Since the second initial signal line 57 is connected to the first regions of all seventh active layers in one unit row, it can be ensured that the first poles of all seventh transistors T7 in one unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0207] In an exemplary embodiment, the second initial connecting line 58 may have a polygonal line shape with its main body extending along the second direction Y, and the second initial connecting line 58 may be disposed between two adjacent second initial signal lines 57 in the second direction Y and connected to the two second initial signal lines 57, respectively. In this way, the second initial signal line 57 extending along the first direction X and the second initial connecting line 58 extending along the second direction Y form an initial signal line with a network connection structure in the display area, which not only minimizes the resistance of the initial signal line, reduces the voltage drop of the initial voltage, effectively improves the uniformity of the initial voltage on the display substrate, effectively improves the uniformity in the signal plane, and effectively improves display uniformity, but also makes the potential of the fourth node (anode) of the pixel driving circuit more uniform in the reset stage, which facilitates consistent lighting speeds of the light-emitting devices, and improves display attributes and display quality.

[0208] In an exemplary embodiment, the second initial connection lines 58 may be installed in odd-numbered unit columns or even-numbered unit columns, i.e., one second initial connection line 58 is installed for every two unit columns.

[0209] In an exemplary embodiment, of two adjacent unit rows, the unit column in which the second initial connection line 58 in one unit row is located is different from the unit column in which the second initial connection line 58 in the other unit row is located. For example, the second initial connection lines 58 connected to the second initial signal lines 57 in the (M-1)th row and the second initial signal lines 57 in the (M+1)th row, respectively, may be located in the circuit unit in the (N+2)th column, while the second initial connection lines 58 connected to the second initial signal lines 57 in the (M-1)th row and the second initial signal lines 57 in the (M+1)th row, respectively, may be located in the circuit unit in the (N+2)th column.

[0210] In the exemplary embodiment, the second initial signal line 57 and the second initial connection line 58 are formed synchronously by the same patterning process and are an integral structure connected to each other.

[0211] In an exemplary embodiment, the first connection electrodes 51 to sixth connection electrodes 56 and second initial signal lines 57 of adjacent unit columns may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the first connection electrodes 51 to sixth connection electrodes 56 and second initial signal lines 57 in multiple unit columns may be basically the same.

[0212] (9) Forming a first flat layer pattern. In an exemplary embodiment, as shown in Figure 23, forming the first flat layer pattern may include applying a first flat thin film to the base on which the above-mentioned pattern is formed, patterning the first flat thin film by a patterning process, forming a first flat layer covering the fourth conductive layer pattern, and providing a plurality of vias in the first flat layer.

[0213] In the exemplary embodiment, the plurality of vias in each circuit unit includes at least a 21st via V21, a 22nd via V22, and a 23rd via V23.

[0214] In an exemplary embodiment, the orthogonal projection at the base of the 21st via V21 is located within the range of the orthogonal projection at the base of the third connection electrode 53, the first flat layer within the 21st via V21 is removed by etching to expose the surface of the third connection electrode 53, and the 21st via V21 is configured to connect the 11th connection electrode to be formed later to the third connection electrode 53 through the via.

[0215] In an exemplary embodiment, the orthogonal projection at the base of the 22nd via V22 is located within the range of the orthogonal projection at the base of the 6th connecting electrode 56, the first flat layer within the 22nd via V22 is removed by etching to expose the surface of the 6th connecting electrode 56, and the 22nd via V22 is configured to connect the 12th connecting electrode to be formed later to the 6th connecting electrode 56 through the via.

[0216] In an exemplary embodiment, the orthogonal projection at the base of the 23rd via V23 is located within the range of the orthogonal projection at the base of the fourth connecting electrode 54, the first flat layer within the 23rd via V23 is removed by etching to expose the surface of the fourth connecting electrode 54, and the 23rd via V232 is configured to connect a later-formed shield electrode to the fourth connecting electrode 54 through the via.

[0217] In an exemplary embodiment, the vias in the first planar layer of adjacent unit columns may be mirror-symmetric about the centerline. In an exemplary embodiment, the vias in the first planar layer of multiple unit rows may have essentially the same shape.

[0218] (10) Forming a fifth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 24 and 25, forming the fifth conductive layer may include depositing a fifth conductive thin film on the base on which the pattern is formed, patterning the fifth conductive thin film by a patterning process, and forming a fifth conductive layer provided on the first flat layer. FIG. 25 is a schematic plan view of the fifth conductive layer in FIG. 24. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0219] In the exemplary embodiment, the fifth conductive layer of each circuit unit includes at least an eleventh connecting electrode 61 , a twelfth connecting electrode 62 , and a shielding electrode 63 .

[0220] In an exemplary embodiment, the shape of the 11th connection electrode 61 may be a stripe shape with its main body extending along the second direction Y, the 11th connection electrode 61 is connected to the third connection electrode 53 through the 21st via V21, and the 11th connection electrode 61 is configured to be connected to a data signal line to be formed later, and the 11th connection electrode 61 may also be called a data connection electrode.

[0221] In an exemplary embodiment, the shape of the twelfth connecting electrode 62 may be polygonal, and the twelfth connecting electrode 62 is connected to the sixth connecting electrode 56 through the 22nd via V22, and the twelfth connecting electrode 62 is configured to be connected to an anode connecting electrode that will be formed later.

[0222] In an exemplary embodiment, the shape of the shield electrode 63 may be a block shape with its main body extending along the second direction Y, and the shield electrode 63 is connected to the fourth connection electrode 54 through the 23rd via V23, and the shield electrode 63 is configured to be connected to the first power line that will be formed later.

[0223] In the exemplary embodiment, the shield electrode 63 may include a shield body portion 63-1 and a shield connection portion 63-2. The shield body portion 63-1 may have a rectangular shape, and the corners of the rectangle may be chamfered. An orthogonal projection of the shield body portion 63-1 at a base at least partially overlaps an orthogonal projection of the first connection electrode 51 at a base. An orthogonal projection of the shield body portion 63-1 at a base at least partially overlaps an orthogonal projection of the second region of the first active layer and an orthogonal projection of the first region of the second active layer at a base. The shield connection portion 63-2 may have a strip shape extending along the second direction Y. A first end of the shield connection portion 63-2 is connected to the shield body portion 63-1. A second end of the shield connection portion 63-2 extends in a direction away from the shield body portion 63-1 and is then connected to the fourth connection electrode 54 via the via hole V23. An orthogonal projection of the shield connection portion 63-2 at a base at least partially overlaps an orthogonal projection of the first connection electrode 51 at a base.

[0224] In the exemplary embodiment, the shield electrode 63 completely shields the second region of the first active layer and the first region of the second active layer, thereby blocking light emitted by the light emitting device and light reflected by the film layer from reaching the oxide transistor, preventing characteristic drift of the oxide transistor due to light irradiation and improving the electrical characteristics of the oxide transistor. Since the shield electrode 63 is connected to the first power line to be formed later, the shield electrode 63, which has a constant potential, effectively shields the second node N2 in the pixel driving circuit from being affected by data voltage jumps and other signals, thereby preventing the potential of the second node N2 from being affected by data voltage jumps and other signals. This not only effectively prevents crosstalk degradation, but also avoids display differences caused by some circuit units having second connecting lines but not others, thereby improving the display effect.

[0225] In an exemplary embodiment, the fourth conductive layer may further include a first connection line 70 , a first wrap block 71 , and a data connection block 72 .

[0226] In an exemplary embodiment, the shape of the first connection line 70 may be a broken line whose main body extends along the first direction X, and the first connection line 70 of the circuit unit in the Mth row may be installed on the side of the shield electrode 63 closer to the circuit unit in the (M+1)th row, and the first connection line 70 is configured as a horizontal wiring in the data connection line.

[0227] In an exemplary embodiment, in at least one unit row, in order to ensure etching uniformity of the display substrate, a break may be provided in the first connecting line 70, and the first connecting line 70 on one side of the break is a horizontal wiring in the data connecting line, and the first connecting line 70 on the other side of the break is a dummy wiring.

[0228] In an exemplary embodiment, the first wrap block 71 may be polygonal in shape, located between adjacent unit columns, and connected to the first connecting line 70. For example, the first wrap block 71 may be provided between the Nth and N+1th columns, or the first wrap block 71 may be provided between the N+2th and N+3th columns. In an exemplary embodiment, to ensure etching uniformity of the display substrate, a portion of the first wrap block 71 is configured to be connected to a second connecting line to be formed later, and another portion of the first wrap block 71 has a dummy wrap structure.

[0229] In an exemplary embodiment, the shape of the data connection block 72 may be a strip extending along the second direction Y, and a first end of the data connection block 72 is connected to the first connection line 70, and a second end of the data connection block 72 is connected to the third connection electrode 53.

[0230] In an exemplary embodiment, in at least one circuit unit, the first connection line 70, the first wrap block 71, and the data connection block 72 may be an integral structure that is formed synchronously by the same patterning process and connected to each other.

[0231] In an exemplary embodiment, the eleventh connection electrode 61, the twelfth connection electrode 62, and the shield electrode 63 of adjacent unit columns may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the eleventh connection electrode 61, the twelfth connection electrode 62, and the shield electrode 63 in multiple unit columns may be basically the same.

[0232] (11) Forming a second flat layer pattern. In an exemplary embodiment, as shown in Figure 26, forming the second flat layer pattern may include applying a second flat thin film to the base on which the above-mentioned pattern is formed, patterning the second flat thin film by a patterning process, forming a second flat layer covering the fifth conductive layer pattern, and providing a plurality of vias in the second flat layer.

[0233] In the exemplary embodiment, the plurality of vias in each circuit unit includes at least a 31st via V31, a 32nd via V32, and a 33rd via V33.

[0234] In the exemplary embodiment, the orthogonal projection at the base of the 31st via V31 is located within the range of the orthogonal projection at the base of the 11th connecting electrode 61, the second flat layer in the 31st via V31 is removed by etching to expose the surface of the 11th connecting electrode 61, and the 31st via V31 is configured to connect a data signal line to be formed later to the 11th connecting electrode 61 through the via. In the exemplary embodiment, the 31st via V31 on the 11th connecting electrode 61 (data connecting electrode) connected to the first connecting line 70 may be referred to as a first wrap via.

[0235] In an exemplary embodiment, the orthogonal projection at the base of the 32nd via V32 is located within the range of the orthogonal projection at the base of the 12th connecting electrode 62, the second flat layer in the 32nd via V32 is removed by etching to expose the surface of the 12th connecting electrode 62, and the 32nd via V32 is configured to connect a later-formed anode connecting electrode to the 12th connecting electrode 62 through the via.

[0236] In an exemplary embodiment, the orthogonal projection at the base of the 33rd via V33 is located within the range of the orthogonal projection at the base of the shield connection portion 63-2 in the shield electrode 63, the second flat layer in the 33rd via V33 is removed by etching to expose the surface of the shield connection portion 63-2, and the 33rd via V33 is configured to connect the first power line to be formed later to the shield electrode 63 through the via.

[0237] In an exemplary embodiment, the plurality of vias on the second flat layer may further include a 34 via V34. The orthogonal projection of the 34 via V34 at the base is located within the range of the orthogonal projection of the base of the first wrap block 71, the second flat layer within the 34 via V34 is removed by etching to expose the surface of the first wrap block 71, and the 34 via V34 is configured to connect a second connecting line, which will be formed later, to the first connecting line 70 through the via. In an exemplary embodiment, the 34 via V34 is provided in a portion of the first wrap block 71, and the 34 via V34 may be referred to as a second wrap via.

[0238] In an exemplary embodiment, the 31st via V31, the 32nd via V32, and the 33rd via V33 in adjacent unit columns may be mirror-symmetrical with respect to the center line. In an exemplary embodiment, the 31st via V31, the 32nd via V32, and the 33rd via V33 in multiple unit rows may have essentially the same shape.

[0239] (12) Forming a sixth conductive layer pattern. In an exemplary embodiment, as shown in Figures 27 and 28, forming the sixth conductive layer may include depositing a sixth conductive thin film on the base on which the pattern is formed, patterning the sixth conductive thin film by a patterning process, and forming a sixth conductive layer disposed on the second flat layer, and Figure 28 is a schematic plan view of the sixth conductive layer in Figure 27. In an exemplary embodiment, the sixth conductive layer may be referred to as a third source-drain metal (SD3) layer.

[0240] In the exemplary embodiment, the sixth conductive layer of each circuit unit includes at least a data signal line 60 , a first power supply line 64 , and an anode connecting electrode 65 .

[0241] In an exemplary embodiment, the data signal line 60 may have a linear shape with its main body extending along the second direction Y, and the data signal line 60 is connected to the eleventh connecting electrode 61 through the thirty-first via V31. The eleventh connecting electrode 61 is connected to the third connecting electrode 53 through a via, and the third connecting electrode 53 is connected to the first region of the fourth active layer through a via, so that the data signal line 60 is connected to the first pole of the fourth transistor T4, and the data signal line 60 can write a data signal to the first pole of the fourth transistor T4.

[0242] In an exemplary embodiment, the data signal lines are disposed on the third source-drain metal (SD3) layer and are spaced apart from their corresponding signal lines by thick first and second planar layers, thereby increasing the distance between the data signal lines and their corresponding signal lines and reducing the parasitic capacitance between the data signal lines and their corresponding signal lines, thereby effectively reducing the capacitive load of the data signal lines.

[0243] In an exemplary embodiment, the first power line 64 may have a polygonal body extending along the second direction Y, and the first power line 64 is connected to the shield connection portion 63-2 of the shield electrode 63 through the via hole V33. The shield electrode 63 is connected to the fourth connection electrode 54 through a via hole, and the fourth connection electrode 54 is connected to the first region of the fifth active layer and the second plate 34 through a via hole. This allows the first power line 64 to be connected to the first electrode and the second plate 34 of the fifth transistor T5, and the first power line 64 can write a power signal to the first electrode of the fifth transistor T5, and the first electrode of the fifth transistor T5 and the second plate 34 of the storage capacitor have the same potential.

[0244] In an exemplary embodiment, the first power supply line 64 may be a broken line with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power supply line and the data signal line.

[0245] In an exemplary embodiment, the anode connecting electrode 65 may have a polygonal shape, and is connected to the twelfth connecting electrode 62 through the 32nd via V32, and is configured to be connected to an anode to be formed later. The twelfth connecting electrode 62 is connected to the sixth connecting electrode 56 through a via, and the sixth connecting electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through vias, so that the anode to be formed later can be connected to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, and the pixel driving circuit can drive the light emitting device to emit light.

[0246] In an exemplary embodiment, the sixth conductive layer may further include a second connection line 80, a second wrap block 81, and a power supply line 90.

[0247] In an exemplary embodiment, the second connection line 80 may have a linear body extending along the second direction Y, may be located in a gap between the pixel driving circuits of adjacent unit columns, and is connected to the first wrap block 71 through the via hole V34. The first wrap block 71 is connected to the first connection line 70, thereby realizing a connection between the second connection line 80 and the first connection line 70. The first connection line 70 is connected to the eleventh connection electrode 61 through the data connection block 72, and the eleventh connection electrode 61 is connected to the data signal line 60 through the via hole, thereby realizing a sequential connection between the data signal line 60, the first connection line 70, and the second connection line 80.

[0248] In an exemplary embodiment, the second wrap block 81 may be polygonal in shape, located between adjacent unit columns, and connected to the second connection line 80. For example, the second wrap block 81 may be located between the Nth and N+1th columns, or the second wrap block 81 may be located between the N+2th and N+3th columns. In an exemplary embodiment, the orthogonal projection at the base of the second wrap block 81 at least partially overlaps with the orthogonal projection at the base of the first wrap block 71. To ensure etching uniformity of the display substrate, a portion of the second wrap block 81 is connected to the first wrap block 71 through the 34th via V34, and another portion of the second wrap block 81 has a dummy wrap structure.

[0249] In an exemplary embodiment, the pixel driving circuits in the display area have a mirror-symmetric structure, and the pixel driving circuits of adjacent unit columns are mirror-symmetric. Therefore, without changing the size of the circuit units, a gap can be formed between the pixel driving circuits of adjacent unit columns by central compression, and the second connecting line extending along the vertical direction of the display area can be installed in the gap between the adjacent pixel driving circuits, thereby maximizing the distance between the second connecting line and the data signal line and maximizing the reduction in the interference caused by capacitive coupling between the second connecting line and the data signal line.

[0250] In an exemplary embodiment, at least one second connecting line 80 may be provided between two data signal lines 60 of adjacent unit columns, and the two data signal lines 60 may be mirror-symmetric with respect to the center line, and the two data signal lines 60 may be mirror-symmetric with respect to the second connecting line 80.

[0251] In an exemplary embodiment, the minimum distance L1 in the first direction X between at least one second connection line 80 and an adjacent data signal line 60 may be greater than the minimum distance L3 in the first direction X between two data signal lines 60 in adjacent unit columns.

[0252] In an exemplary embodiment, the second connecting line is disposed on the third source-drain metal (SD3) layer and is spaced apart from the corresponding signal line by the thick first and second planar layers, thereby increasing the distance between the second connecting line and the corresponding signal line and reducing the parasitic capacitance between the second connecting line and the corresponding signal line, thereby effectively reducing the capacitive load of the second connecting line.

[0253] In an exemplary embodiment, the first connection line is provided in the second source-drain metal (SD2) layer, and the second connection line is provided in the third source-drain metal (SD3) layer, so that the first connection line and the second connection line can be connected using only one planar layer via, which is advantageous for minimizing the occupied space and realizing a high-resolution display.

[0254] In an exemplary embodiment, the power supply wiring 90 may have a linear shape with its main body extending along the second direction Y, and the power supply wiring 90 is located between some adjacent unit columns. Between at least one unit column, only the power supply wiring 90 may be provided, and the second connection line 80 may not be provided. Between at least one unit column, the second connection line 80 and the power supply wiring 90 may be provided, and the power supply wiring 90 and the second connection line 80 may be located on the same straight line extending along the second direction Y. A break may be provided between the power supply wiring 90 and the second connection line 80, and the break is configured to achieve insulation between the power supply wiring 90 and the second connection line 80.

[0255] In an exemplary embodiment, at least one power supply wiring 90 may be placed between two data signal lines 60 of adjacent unit columns, and the two data signal lines 60 may be mirror-symmetric with respect to the power supply wiring 90.

[0256] In an exemplary embodiment, the minimum distance L2 in the first direction X between at least one power supply wiring 90 and an adjacent data signal line 60 may be greater than the minimum distance L3 in the first direction X between two data signal lines 60 in adjacent unit columns.

[0257] In an exemplary embodiment, the plurality of power supply lines 90 may be lines that continuously supply low-voltage signals. For example, the power supply lines may be second power supply lines VSS. The plurality of power supply lines 90 may be connected to power supply lead lines provided in the bind region or bezel region. The present disclosure realizes a structure in which low-voltage power supply lines are provided in subpixels (VSS in pixels) by providing power supply lines in the display region, which effectively reduces the resistance of power supply signal lines and the voltage drop of low-voltage power supply signals, thereby achieving low power consumption. This effectively improves the uniformity of power supply signals on the display substrate, effectively improving display uniformity and display attributes and quality. Furthermore, the structure in which low-voltage power supply lines are provided in subpixels can significantly reduce the width of power supply lead lines in the bezel region and bind region, which is advantageous for achieving a narrow bezel.

[0258] In an exemplary embodiment, the data signal lines 60, the first power supply lines 64, and the anode connecting electrodes 65 of adjacent unit columns may be mirror-symmetric with respect to the center line. In an exemplary embodiment, the shapes of the data signal lines 60, the first power supply lines 64, and the anode connecting electrodes 65 in multiple unit columns may be essentially the same.

[0259] (13) Forming a third flat layer pattern. In an exemplary embodiment, as shown in Figure 29, forming the third flat layer pattern may include applying a third flat thin film to the base on which the above-mentioned pattern is formed, patterning the third flat thin film by a patterning process, forming a third flat layer covering the sixth conductive layer pattern, and providing a plurality of vias in the third flat layer.

[0260] In the exemplary embodiment, the vias of each circuit unit include at least an anode via V40. The orthogonal projection at the base of the anode via V40 is located within the range of the orthogonal projection at the base of the anode connecting electrode 65, the third flat layer within the anode via V40 is removed by etching to expose the surface of the anode connecting electrode 65, and the anode via V40 is configured to connect a later-formed anode to the anode connecting electrode 65 through the via.

[0261] Up to this point, a driving structure layer is fabricated on the base and completed. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, each of which may include a pixel driving circuit and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer, and a third flat layer, which are sequentially disposed on the base. the shielding layer may include at least a shielding electrode; the first semiconductor layer may include at least active layers of the third to seventh transistors; the first conductive layer may include at least a first scanning signal line, a light-emitting signal line, and a first plate of the storage capacitor; the second conductive layer may include at least a first initial signal line and a second plate of the storage capacitor; the second semiconductor layer may include at least active layers of the first to second transistors; the third conductive layer may include at least a second scanning signal line and a third scanning signal line; the fourth conductive layer may include at least a second initial signal line, a second initial connecting line, and a plurality of connecting electrodes; the fifth conductive layer may include at least a shielding electrode and a first power supply line; and the sixth conductive layer may include at least a data signal line, a first power supply line, a second power supply line, and a second connecting line.

[0262] In exemplary embodiments, the base may be a flexible base or a rigid base. The rigid base may be one or more of, but is not limited to, glass and quartz, and the flexible base may be one or more of, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and woven fibers. In exemplary embodiments, the flexible base may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The first flexible material layer and the second flexible material layer may be made of materials such as polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film, the first inorganic material layer and the second inorganic material layer may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water and oxygen resistance of the substrate, the first inorganic material layer and the second inorganic material layer are also called barrier layers, and the semiconductor layer may be made of amorphous silicon (a-Si).

[0263] In an exemplary embodiment, the first, second, third, fourth, fifth, and sixth conductive layers may be made of one or more metal materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or alloy materials of these metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may have a single-layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first, second, third, fourth, fifth, and sixth insulating layers may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multilayer, or composite. The first insulating layer may be referred to as a buffer layer, the second, third, fourth, and fifth insulating layers may be referred to as gate insulating (GI) layers, and the sixth insulating layer may be referred to as an interlayer dielectric (ILD) layer. The first flat layer, the second flat layer, and the third flat layer may be made of an organic material such as a resin.

[0264] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in one unit row may be essentially mirror-symmetric with respect to a center line, which is a straight line located between the two adjacent circuit units and extending along the second direction Y. For example, the pixel driving circuit in the Nth column and the pixel driving circuit in the N+1th column may be mirror-symmetric with respect to the center line. Also, for example, the pixel driving circuit in the N+1th column and the pixel driving circuit in the N+2th column may be mirror-symmetric with respect to the center line.

[0265] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units may be essentially mirror-symmetric with respect to the center line, which may include any one or more of the following: the first semiconductor layers in two adjacent circuit units in one unit row may be mirror-symmetric with respect to the center line, the first conductive layers in two adjacent circuit units in one unit row may be mirror-symmetric with respect to the center line, the second conductive layers in two adjacent circuit units in one unit row may be mirror-symmetric with respect to the center line, the second semiconductor layers in two adjacent circuit units in one unit row may be mirror-symmetric with respect to the center line, and the third conductive layers in two adjacent circuit units in one unit row may be mirror-symmetric with respect to the center line.

[0266] In an exemplary embodiment, after the driving structure layer is manufactured and completed, a light emitting structure layer is manufactured on the driving structure layer, and the process of manufacturing the light emitting structure layer may include the following operations.

[0267] (14) Forming an anode conductive layer pattern. In an exemplary embodiment, as shown in Figure 30, forming an anode conductive layer pattern may include depositing an anode conductive thin film on the base on which the pattern has been formed, and patterning the anode conductive thin film by a patterning process to form an anode conductive layer provided on the third flat layer, where the anode conductive layer includes at least a plurality of anode patterns.

[0268] In an exemplary embodiment, the anode conductive layer may employ a single layer structure such as indium tin oxide ITO or indium zinc oxide IZO, or a multi-layer composite structure such as ITO / Ag / ITO.

[0269] In an exemplary embodiment, the multiple anode patterns may include a first anode 90A located at a red light-emitting unit that emits red light, a second anode 90B located at a blue light-emitting unit that emits blue light, a third anode 90C located at a first green light-emitting unit that emits green light, and a fourth anode 90D located at a second green light-emitting unit that emits green light.

[0270] In an exemplary embodiment, the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may each be connected to the anode connection electrode 65 of the circuit unit in which they are located through an anode via V40.

[0271] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may include an anode body portion and an anode connection portion that are connected to each other, the anode body portion may be rectangular in shape and the corners of the rectangle may be provided with arc-shaped chamfers, the anode connection portion may be strip-shaped, and a first end of the anode connection portion is connected to the anode body portion and a second end of the anode connection portion extends in a direction away from the anode body portion and is then connected to the anode connection electrode 65 through the anode via V40.

[0272] In an exemplary embodiment, the orthogonal projections of the first anode, the second anode, the third anode, and the fourth anode at their bases at least partially overlap with the orthogonal projections of the first power wire at their bases, and the orthogonal projections of the first anode and the second anode at their bases at least partially overlap with the orthogonal projections of the shield electrode at their bases.

[0273] In an exemplary embodiment, in at least one light-emitting unit, an orthogonal projection of the first anode at the base and an orthogonal projection of the first power line at the base have a first overlapping area, and an orthogonal projection of the first anode at the base and an orthogonal projection of the first anode at the base have a second overlapping area with an orthogonal projection of the first anode at the base and an orthogonal projection of the second anode at the base and an orthogonal projection of the second anode at the base have a first overlapping area, and an orthogonal projection of the second anode at the base and an orthogonal projection of the shield electrode at the base and an orthogonal projection of the first overlapping area are smaller than the area of ​​the second overlapping area. In the present disclosure, by providing the shield electrode on the second source-drain metal layer SD2 and the first power line on the third source-drain metal layer SD3, the overlapping areas of the first anode and the second anode and the first power line are effectively reduced, which effectively reduces the parasitic capacitance of the fourth node N4 of the pixel driving circuit and improves the lighting speed of the light-emitting device.

[0274] (15) Forming a pixel definition layer pattern. In an exemplary embodiment, as shown in Fig. 31 , forming the pixel definition layer pattern may include applying a pixel definition thin film to the base on which the above-mentioned pattern is formed, patterning the pixel definition thin film by a patterning process, forming a pixel definition layer covering the anode conductive layer pattern, providing a plurality of pixel openings 90E in the pixel definition layer, and removing the pixel definition thin film in the pixel openings 90E to expose surfaces of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D.

[0275] In an exemplary embodiment, the subsequent manufacturing flow may include first forming an organic light-emitting layer by vapor deposition or inkjet printing, forming a cathode on the organic light-emitting layer, and then forming a package structure layer. The package structure layer may include a first package layer, a second package layer, and a third package layer stacked together, where the first package layer and the third package layer may be made of inorganic materials, and the second package layer may be made of organic materials. The second package layer is disposed between the first package layer and the third package layer, and can ensure that external water vapor does not penetrate into the light-emitting structure layer.

[0276] As can be seen from the above-described structure and manufacturing process of the display substrate, the display substrate according to the exemplary embodiment of the present disclosure has data connection lines within the display area, and the outgoing lines in the binding area are connected to the data signal lines via the data connection lines. This eliminates the need for fan-shaped diagonal lines in the outgoing line area, effectively shortening the length of the outgoing line area, significantly reducing the width of the lower bezel, improving the screen occupancy rate, and advantageous for realizing a full-screen display. In the present disclosure, the first connection line is disposed on the second source-drain metal layer, and the second connection line is disposed on the third source-drain metal layer. This allows the first and second connection lines to be connected with only one planar layer via, minimizing the occupied space and advantageous for realizing a high-resolution display. The resolution (PPI) of the LTPO display substrate can be increased to 480 while realizing a narrow bezel. In the present disclosure, the data signal lines and the second connecting lines are disposed on the third source-drain metal layer, thereby increasing the distance between the data signal lines and the second connecting lines and the corresponding signal lines, and reducing the parasitic capacitance between the data signal lines and the second connecting lines and the corresponding signal lines, thereby effectively reducing the capacitive load of the data signal lines and the second connecting lines.In the present disclosure, the pixel driving circuit adopts mirror symmetry and central compression, and the second connecting lines are disposed in the gaps between adjacent unit rows, thereby maximizing the distance between the second connecting lines and the data signal lines and maximizing the reduction of interference caused by capacitive coupling between the second connecting lines and the data signal lines. In the present disclosure, by providing a shield electrode on the second source-drain metal layer, the shield electrode can block the irradiation of the oxide transistor with light emitted by the light emitting device and light reflected by the film layer, preventing characteristic drift of the oxide transistor due to light irradiation and improving the electrical characteristics of the oxide transistor. Meanwhile, the shield electrode effectively shields the influence of data voltage jumps and other signals to the second node N2 in the pixel driving circuit, avoiding the influence of data voltage jumps and other signals on the potential of the second node N2, effectively avoiding degradation of crosstalk. In addition, it can avoid display differences caused by some circuit units being provided with second connecting lines and some circuit units not being provided with second connecting lines, improving the display effect.In this disclosure, by forming a second initial signal line with a network connection structure in the display area, the resistance of the initial signal line is minimized, reducing the voltage drop of the initial voltage and effectively improving the uniformity of the initial voltage on the display substrate, effectively improving the uniformity within the signal plane, and effectively improving display uniformity. It also makes the potential of the fourth node (anode) of the pixel driving circuit more uniform during the reset phase, making it easier to match the lighting speed of the light-emitting devices and improving display attributes and quality. In this disclosure, by forming the shield electrode on the second source-drain metal layer and the first power line on the third source-drain metal layer, the overlapping area between the anode and the first power line is effectively reduced, effectively reducing the parasitic capacitance of the fourth node N4 of the pixel driving circuit and improving the lighting speed of the light-emitting devices. In this disclosure, by locating the power wiring within the display area, a VSS-in-pixel structure is realized, significantly reducing the width of the bezel power lead, significantly reducing the width of the left and right bezels, improving the screen occupancy rate, and favoring full-screen display. The manufacturing process of the present disclosure has good compatibility with existing manufacturing processes, is simple to realize, easy to implement, has high production efficiency, low manufacturing cost, and high yield rate.

[0277] 32 is a schematic planar structure diagram of another display substrate according to an embodiment of the present disclosure. As shown in FIG. 12, the main body structure of the display substrate of this exemplary embodiment is basically similar to the main body structure of the display substrate of the above-described embodiment, except that the minimum distance L1 in the first direction X between at least one second connecting line 80 and an adjacent data signal line 60 may be approximately half the minimum distance L3 in the first direction X between two data signal lines 60 in adjacent unit columns, and the minimum distance L2 in the first direction X between at least one power supply line 90 and an adjacent data signal line 60 may be approximately half the minimum distance L3 in the first direction X between two data signal lines 60 in adjacent unit columns.

[0278] In an exemplary embodiment, in the display substrate shown in FIG. 8, the second connecting line 80 is disposed between two data signal lines 60 with a large gap between them in adjacent unit columns, and in the display substrate shown in FIG. 32, the second connecting line 80 is disposed between two data signal lines 60 with a small gap between them in adjacent unit columns.

[0279] The above-described structure and its manufacturing process of the present disclosure are merely exemplary descriptions, and in the exemplary embodiments, the corresponding structure can be changed or the composition process can be added or removed according to actual needs, and the present disclosure is not limited thereto.

[0280] In an exemplary embodiment, the display substrate of the present disclosure can be applied to other display devices having pixel driving circuits, such as quantum dot displays, although the present disclosure is not limited thereto.

[0281] The present disclosure further provides a method for manufacturing a display substrate according to the above embodiment. In an exemplary embodiment, the display substrate includes a display area, and the manufacturing method includes: forming a driving structure layer on a base of the display area, the driving structure layer including at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, the first direction intersecting the second direction; the circuit units including pixel driving circuits, at least one data signal line connected to the plurality of pixel driving circuits of one unit column, first ends of the plurality of first connecting lines connected to corresponding ones of the plurality of data signal lines, second ends of the plurality of first connecting lines connected to corresponding ones of the plurality of second connecting lines; the pixel driving circuits of adjacent unit columns are mirror symmetrical with respect to a center line, the center line being a straight line located between adjacent unit columns and extending along the second direction; and the second connecting line being disposed in a gap between the pixel driving circuits of adjacent unit columns.

[0282] Although the embodiments disclosed in the present disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not used to limit the present disclosure. Those skilled in the art can make any modifications and changes in the embodiments and details without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure must comply with the scope defined by the appended claims. [Explanation of symbols]

[0283] 11-first active layer, 12-second active layer, 13-third active layer, 14-4th active layer, 15-5th active layer, 16-6th active layer, 17 - seventh active layer, 21 - first scanning signal line, 22 - light-emitting signal line 23-1st polar plate, 31-1st initial signal line 32-2nd shielding line, 33-Third shielding line, 34-Second plate, 35-Aperture, 41—second scanning signal line; 42—third scanning signal line; 51—first connection electrode; 52—second connection electrode; 53—third connection electrode; 54—fourth connection electrode; 55 - fifth connecting electrode, 56 - sixth connecting electrode, 57 - second initial signal line 58 - second initial connection line; 60 - data signal line; 61 - eleventh connection electrode; 62 - twelfth connection electrode; 63 - shield electrode; 64 - first power line; 65—anode connecting electrode; 70—first connecting wire; 71—first lap block; 72 - data connection block; 80 - second connection line; 81 - second wrap block; 90—power supply wiring; 91—first shield connecting wire; 92—second shield connecting wire; 93—third shield connecting line; 94—shielding electrode; 100—display area 101 - base; 102 - driving structure layer; 103 - light-emitting structure layer; 104 - package structure layer, 200 - bind area, 300 - bezel area.

Claims

1. A display substrate, a display substrate including a display area, the display area including a driving structure layer provided on a base, the driving structure layer including at least a plurality of circuit units configuring a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, the first direction intersecting the second direction, the circuit units including pixel driving circuits, at least one data signal line connected to a plurality of pixel driving circuits of one unit column, first ends of the plurality of first connecting lines connected to a corresponding plurality of data signal lines, second ends of the plurality of first connecting lines connected to a corresponding plurality of second connecting lines, the pixel driving circuits of adjacent unit columns being mirror-symmetrical with respect to a center line, the center line being a straight line located between the adjacent unit columns and extending along the second direction, the second connecting line being provided in a gap between the pixel driving circuits of the adjacent unit columns.

2. 2. The display substrate of claim 1, wherein two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance in the first direction between the second connecting line and the adjacent data signal line is greater than a minimum distance in the first direction between the two data signal lines in the adjacent unit column.

3. 2. The display substrate of claim 1, wherein two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance in the first direction between the second connecting line and the adjacent data signal line is half of a minimum distance in the first direction between the two data signal lines in the adjacent unit column.

4. The display substrate according to claim 1 , wherein the driving structure layer further includes a plurality of power supply wirings extending along the second direction, the power supply wirings being provided in gaps between the pixel driving circuits of adjacent unit columns.

5. 5. The display substrate of claim 4, wherein two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power supply wiring, and a minimum distance in the first direction between the power supply wiring and the adjacent data signal line is greater than a minimum distance in the first direction between the two data signal lines in the adjacent unit column.

6. 5. The display substrate of claim 4, wherein two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power supply wiring, and the minimum distance in the first direction between the power supply wiring and the adjacent data signal line is 1 / 2 of the minimum distance in the first direction between the two data signal lines in the adjacent unit column.

7. 7. The display substrate of claim 1, wherein in a plane perpendicular to the display substrate, the driving structure layer includes a plurality of conductive layers sequentially disposed on a base, the first connecting lines and the second connecting lines being disposed on different conductive layers, and the data signal lines and the second connecting lines being disposed on the same conductive layer.

8. 8. The display substrate of claim 7, wherein the plurality of conductive layers include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially arranged along a direction away from the base, the first connection line is arranged in the second source-drain metal layer, the data signal line and the second connection line are arranged in the third source-drain metal layer, the data signal line is connected to a first end of the first connection line through a via, and the second connection line is connected to a second end of the first connection line through a via.

9. 9. The display substrate of claim 8, wherein the pixel driving circuit includes at least a first transistor, a second transistor, and a storage capacitor, the first transistor including at least a first active layer, the second transistor including at least a second active layer, the second region of the first active layer and the first region of the second active layer being connected to each other as an integral structure and connected to a first plate of the storage capacitor via a first connecting electrode, the second source-drain metal layer further including a shield electrode, wherein an orthogonal projection of the shield electrode at the base at least partially overlaps with an orthogonal projection of the second region of the first active layer and the first region of the second active layer at the base, and an orthogonal projection of the shield electrode at the base at least partially overlaps with an orthogonal projection of the first connecting electrode at the base.

10. The display substrate of claim 9 , wherein the third source / drain metal layer further includes a first power line, and the first power line is connected to the shield electrode through a via.

11. 11. The display substrate of claim 10, wherein in a plane perpendicular to the display substrate, the display substrate further includes a light-emitting structure layer disposed on a side of the driving structure layer away from the base, the light-emitting structure layer including a plurality of light-emitting units, the light-emitting units including at least an anode, and in at least one light-emitting unit, a orthogonal projection of the anode on the base at least partially overlaps a orthogonal projection of the first power line on the base, and a orthogonal projection of the anode on the base at least partially overlaps a orthogonal projection of the shield electrode on the base.

12. 12. The display substrate of claim 11, wherein in at least one light-emitting unit, an orthogonal projection of the anode on the base has a first overlapping area with an orthogonal projection of the first power line on the base, and an orthogonal projection of the anode on the base has a second overlapping area with an orthogonal projection of the shield electrode on the base, and an area of ​​the first overlapping area is smaller than an area of ​​the second overlapping area.

13. 7. The display substrate of claim 1, wherein the pixel driving circuit includes at least a fourth transistor, a first electrode of the fourth transistor is connected to the data signal line via a data connecting electrode, and in at least one circuit unit, the first connecting line is connected to the data connecting electrode.

14. 14. The display substrate of claim 13, wherein at least one circuit unit further includes a data connection block, a first end of the data connection block connected to the first connection line, and a second end of the data connection block connected to the data connection electrode.

15. The display substrate according to claim 14 , wherein in at least one circuit unit, the first connecting line, the data connecting electrode and the data connecting block are provided in the same layer and are connected to each other to form an integrated structure.

16. The display substrate of any one of claims 1 to 6, wherein at least one circuit unit may further include a second initial signal line extending along the first direction and a second initial connection line extending along the second direction, the second initial connection line being disposed between two adjacent second initial signal lines in the second direction and connected to the two second initial signal lines respectively, thereby constituting a second initial connection line having a network connection structure in the display area.

17. The display substrate of claim 16 , wherein the second initial connection lines are arranged in odd-numbered unit columns, or the second initial connection lines are arranged in even-numbered unit columns.

18. 17. The display substrate of claim 16, wherein the unit column in which the second initial connection line is located in one of two adjacent unit rows is different from the unit column in which the second initial connection line is located in the other unit row.

19. The display substrate of claim 16 , wherein the second initial signal line and the second initial connection line are provided in the same layer and are connected to each other in an integrated structure.

20. The pixel driving circuit includes at least a storage capacitor and a plurality of transistors, and the plurality of conductive layers include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are arranged in sequence along a direction away from the base, the shielding layer includes at least a shielding electrode, the first semiconductor layer includes at least active layers of a plurality of low-temperature polysilicon transistors, and the first gate metal layer includes at least a first scanning signal line, an emission signal line, and a first electrode plate of the storage capacitor. the second gate metal layer includes at least a second electrode plate of a storage capacitor, the second semiconductor layer includes at least active layers of a plurality of oxide transistors, the third gate metal layer includes at least a second scanning signal line and a third scanning signal line, the first source-drain metal layer includes at least a second initial signal line having a network connection structure, the second source-drain metal layer includes at least a shield electrode and the first connecting line, and the third source-drain metal layer includes at least a first power line, the data signal line, and the second connecting line.

21. 21. The display substrate of claim 20, wherein the plurality of transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, the first transistor and the second transistor being oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor being low-temperature polysilicon transistors.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

23. 1. A method for manufacturing a display substrate, the display substrate including a display region, the method comprising: a driving structure layer formed on a base of the display area, the driving structure layer including at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, the first direction intersecting the second direction, the circuit units including pixel driving circuits, at least one data signal line connected to the plurality of pixel driving circuits of one unit column, first ends of the plurality of first connecting lines connected to corresponding ones of the plurality of data signal lines, second ends of the plurality of first connecting lines connected to corresponding ones of the plurality of second connecting lines, the pixel driving circuits of adjacent unit columns being mirror-symmetrical with respect to a center line, the center line being a straight line located between the adjacent unit columns and extending along the second direction, and the second connecting line being provided in a gap between the pixel driving circuits of adjacent unit columns.

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