Register placement system, method and electronic device

Abstract

This application provides a register allocation system, method, and electronic device, and relates to the technical field of computers. The register allocation system includes a display processing device, a memory, and a hardware automatic control unit. The display processing device includes a plurality of registers. The memory pre-stores at least one allocation instruction for specifying a target register to be allocated in the display processing device. The hardware automatic control unit is connected to a register allocation interface in the display processing device, receives a startup instruction including a storage address of the allocation instruction, retrieves and analyzes the allocation instruction from the memory based on the startup instruction, and allocates the target register in the display processing device based on the analyzed allocation instruction. By using the hardware automatic control unit to allocate registers instead of the conventional method of allocating registers by a CPU, the burden on CPU bandwidth can be minimized.

Description

[Technical Field]

[0001] This application relates to the field of computers, and more particularly to register configuration systems, methods and electronic devices. [Background technology]

[0002] As demand for various high-definition displays increases, the entire algorithm unit and its processing processes in display processing units (DPUs) are becoming increasingly complex. Accordingly, various control processes are also becoming more complex. Furthermore, the number of registers allocated by software is increasing dramatically, and the interaction between software and hardware is becoming more frequent. Due to these new challenges, it is difficult and unrealistic to realize various control and allocation processes using only the traditional central processing unit (CPU) control method. In other words, such an operation method cannot meet actual performance requirements. Summary of the Invention

[0003] The present application provides a register allocation system, method and electronic device to solve the problem that the realization of various control and allocation processes by the conventional CPU control method in the prior art cannot meet the actual performance requirements.

[0004] In a first aspect, the present application provides a register allocation system including a display processing device, a memory, and a hardware automatic control unit, wherein the display processing device includes a plurality of registers, the memory pre-stores at least one allocation instruction for specifying a target register to be allocated in the display processing device, and the hardware automatic control unit is connected to a register allocation interface in the display processing device, receives a startup instruction including a storage address of the allocation instruction, retrieves and analyzes the allocation instruction from the memory based on the startup instruction, and allocates the target register in the display processing device based on the analyzed allocation instruction.

[0005] In the embodiments of the present application, instead of the conventional method of allocating registers by a CPU, registers are allocated by a hardware automatic control unit, thereby minimizing the bandwidth burden imposed on the CPU when allocating a GPU. Even if the number of registers to be allocated increases, this method makes it possible to realize allocation for the registers, thereby optimizing the display processing process.

[0006] In relation to the technical solution according to the first aspect above, in some possible embodiments, the hardware automatic control unit is connected to an interactive interface of each data path of the display processing device, and different data paths include different registers, and the hardware automatic control unit sends a placement start command to the data path indicating the start of placement of the target register, and further receives a placement status signal returned from the data path indicating whether all registers included in the data path have been placed.

[0007] In an embodiment of the present application, the hardware automatic control unit can clarify the register placement status in each data path of the display processing device through data interaction with each data path of the display processing device, making it easier for the hardware automatic control unit to determine whether there is a data path required for register placement.

[0008] In relation to the technical solution according to the first aspect above, in some possible embodiments, the display processing device includes a plurality of data paths, and the hardware automatic control unit records the placement status of the registers included in each of the data paths, indicating whether the registers have been placed or not, in response to the placement status signal returned from each of the data paths.

[0009] In the embodiment of the present application, the hardware automatic control unit records the allocation status of the registers included in each data path, which makes it easier to subsequently determine which data path's registers to allocate.

[0010] In relation to the technical solution according to the first aspect above, in some possible embodiments, the register placement system further includes a central processing unit connected to the hardware automatic control unit and transmitting the startup command to the hardware automatic control unit.

[0011] In relation to the technical solution according to the first aspect above, in some possible embodiments, the hardware automatic control unit transmits its internal status to the central processing unit, and the central processing unit determines whether the hardware automatic control unit is abnormal according to the received status of the hardware automatic control unit, and if the hardware automatic control unit is abnormal, transmits an interrupt command to the hardware automatic control unit to instruct it to stop operating.

[0012] In an embodiment of the present application, the central processing unit monitors the internal state of the hardware automatic control unit, and if the hardware automatic control unit detects an abnormality, it can send an interrupt command to the hardware automatic control unit to stop the operation of the hardware automatic control unit, thereby preventing situations such as register allocation errors caused by an abnormality in the hardware automatic control unit and improving the reliability of the register allocation system.

[0013] In relation to the technical solution according to the first aspect above, in some possible embodiments, the placement instruction includes an instruction type, the number of target registers with consecutive addresses, an offset address of the first target register, an instruction body, and an instruction end flag.

[0014] In relation to the technical solution according to the first aspect, in some possible embodiments, the instruction body describes a calculation method for an actual allocation address of each target register, and the hardware automatic control unit analyzes the allocation instruction according to the instruction type, obtains the number of target registers, the offset address of the first target register, the instruction body, and the instruction end flag, determines the actual allocation address of each target register based on the number of target registers with consecutive addresses, the offset address of the first target register, and the calculation method in the instruction body, and allocates each target register based on the actual allocation address of each target register.

[0015] In the embodiment of the present application, the instruction body describes how to calculate the actual allocation address of each target register, so that the address of the target register to be allocated can be calculated based on the number of target registers with consecutive addresses and the offset address of the first target register. This allows multiple registers to be allocated with one instruction, reduces the number of allocation instructions to be sent, and improves allocation efficiency.

[0016] In relation to the technical solution according to the first aspect, in some possible embodiments, the instruction body further describes a method for calculating the total number of target registers with consecutive addresses, wherein the hardware automatic control unit determines the total number of target registers with consecutive addresses according to the number of target registers with consecutive addresses and the calculation method for the total number of target registers, and determines the actual allocation address of each target register based on the total number of target registers with consecutive addresses, the offset address of the first target register, and the instruction body.

[0017] In the embodiment of the present application, since the length of the field for recording the number of target registers with consecutive addresses is limited in the placement instruction, if there are a large number of target registers with consecutive addresses, the total number of target registers with consecutive addresses can be calculated by describing a calculation method for the total number of target registers with consecutive addresses in the instruction body.Since there is no need to divide the placement instruction into multiple placement instructions, the number of placement instructions sent can be reduced, improving placement efficiency.

[0018] In a second aspect, the present application provides a register allocation method, which is applied to a hardware automatic control unit in a register allocation system described in the first aspect and / or an implementable form related to the first aspect, and includes the steps of receiving a startup command, retrieving the allocation command from the memory based on the startup command and analyzing it, and allocating a target register in the display processing device based on the analyzed allocation command.

[0019] In a third aspect, the present application provides an electronic device, the electronic device including the register arrangement system described in the first aspect and / or any of the possible embodiments related to the first aspect.

[0020] The beneficial effect of this invention is that instead of the conventional CPU-based register allocation method, the hardware automatic control unit allocates registers in the display processing device, thereby minimizing the burden on the CPU's bandwidth. Even if the number of registers to be allocated increases, this method can realize the allocation for the registers, thereby optimizing the display processing process.

[0021] In order to more clearly explain the technical solutions of the embodiments of the present application, the following will briefly explain the drawings necessary for explaining the embodiments. The following drawings only illustrate some embodiments of the present application and do not limit the scope. Those skilled in the art can obtain other related drawings based on these drawings without using inventive abilities. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 is a structural block diagram of a first register placement system according to an embodiment of the present application; [Figure 2] FIG. 1 is a structural schematic diagram of the connection between a hardware automatic control unit and a display processing device according to an embodiment of the present application. [Figure 3] FIG. 10 is a schematic diagram of an instruction end flag according to an embodiment of the present application; [Figure 4] FIG. 2 is a structural schematic diagram of a first placement instruction according to an embodiment of the present application; [Figure 5] FIG. 10 is a structural schematic diagram of a second placement command according to an embodiment of the present application; [Figure 6] FIG. 10 is a structural schematic diagram of a third placement command according to an embodiment of the present application; [Figure 7] FIG. 10 is a structural schematic diagram of a fourth placement command according to an embodiment of the present application; [Figure 8] FIG. 2 is a structural block diagram of a second register placement system according to an embodiment of the present application; [Figure 9] 1 is a flowchart of a register allocation method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, the technical solutions according to the embodiments of the present application will be described with reference to the accompanying drawings.

[0024] Note that like reference numerals refer to like elements in the drawings, and therefore, when defined in one drawing, further definition and interpretation in other drawings is unnecessary. Furthermore, in this application, relational terms such as "first" and "second," etc., may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. Furthermore, terms such as "have," "include," and any variations thereof are intended to cover non-exclusive inclusions. Thus, a process, method, article, or apparatus that includes a set of elements is not necessarily limited to those elements and may include other elements not expressly specified or inherent to those processes, methods, articles, or apparatus.

[0025] Hereinafter, the technical solution of the present application will be described in detail with reference to the drawings.

[0026] 1 is a structural schematic diagram of a register allocation system 100 according to an embodiment of the present application. The register allocation system 100 includes a display processing device 110, a memory 130, and a hardware automatic control unit 120.

[0027] The display processing device 110 includes a number of registers.

[0028] Optionally, display processor 110 includes at least one data path, and if display processor 110 includes multiple data paths, different data paths include different registers.

[0029] The display processing device 110 may be any type of conventional display processing device 110, and the specific type of the display processing device 110 is not limited here.

[0030] The memory 130 pre-stores at least one allocation instruction for specifying a target register to be allocated in the display processing device 110 .

[0031] The memory 130 may be any conventional type of memory 130, such as a USB disk, a portable hard disk, a read-only memory 130 (ROM), a random access memory 130 (RAM), a magnetic disk, an optical disk, or any other medium capable of storing program code, but the specific type of memory 130 is not limited here.

[0032] The hardware automatic control unit 120 is connected to a register allocation interface in the display processing device 110. The hardware automatic control unit 120 receives a start-up command including a storage address of a allocation command, obtains and analyzes the allocation command from the memory 130 based on the start-up command, and allocates a target register in the display processing device 110 based on the analyzed allocation command.

[0033] The hardware automatic control unit 120 may be, but is not limited to, a PDMA (Programming Direct Memory Access).

[0034] FIG. 2 shows a specific method of connecting the automatic hardware control unit 120 and the display processing device according to an embodiment.

[0035] Here, the automatic hardware control unit 120 is connected to the pre-processor shown in Fig. 2, the crossbar shown in Fig. 2, the post-processor shown in Fig. 2, and the output interface shown in Fig. 2 of the display processing device 110, and realizes the allocation of registers in the display processing device 110 by sending instructions to at least one of the pre-processor, the crossbar, the post-processor, and the output interface. The automatic hardware control unit 120 obtains activation instructions and allocation instructions via the bus interface shown in Fig. 2.

[0036] In the past, a CPU sent instructions to a display processing device, which then sent the instructions from the CPU to a preprocessor, crossbar, postprocessor, and output interface to allocate registers in the display processing device. In contrast, in the present application, data transmission by the display processing device is not required, which improves the efficiency of register allocation.

[0037] Optionally, the hardware automatic control unit 120 may be provided independently or within the display processing device 110 .

[0038] In one embodiment, the placement instruction includes a register address, which subsequently facilitates the hardware automatic control unit 120 to determine and place the target register according to the register address.

[0039] Optionally, the placement instruction may further include an instruction type for analysis by the hardware automatic control unit 120 into the placement instruction.

[0040] Here, the instruction type may represent the type of placement instruction, such as a 16-bit instruction, a 32-bit instruction, etc. The examples here are merely for ease of understanding and are not intended to limit the present application.

[0041] In one embodiment, multiple placement instructions may be stored as an instruction list in memory 130. In this case, the placement instructions also include an instruction end flag to distinguish between different placement instructions.

[0042] The end-of-command flag is usually located at the end of a placement command. By reading the end-of-command flag, you can confirm that all the contents of the current placement command have been read.

[0043] The command end flag may be a character string made up of characters or a binary code, and the specific implementation method of the command end flag is not limited here.

[0044] Optionally, in some specific cases, multiple different display regions need to be activated multiple times within one frame. Due to high requirements for timeliness, this multiple activation operation needs to be fully automated by automatic triggering by the hardware automatic control unit 120 and handshaking interaction with different hardware blocks of the display processing device 110. Therefore, a flag indicating that the end of the configuration data for an image region has been reached may be provided in the command end flag.

[0045] When the hardware automatic control unit 120 reads the flag indicating that the end of the configuration data of this image area has been reached, it automatically jumps to the shift position of the next image area (shift storage position, i.e., the position of the memory area determined by the shift address of the image area and the size of the image area) in response to this flag, and controls the operation process such as analysis, placement and execution of the next placement command.

[0046] Figure 3 shows one way to implement the command end flag. Next section size indicates the size of the next image area, and Next section address offset indicates the offset address of the next image area. By reading Next section size and Next section address offset, you can identify the shift position of the next image area and jump to it.

[0047] Here, LSB (Least Significant Bit) refers to the bit position that represents the smallest value in a binary number, and MSB (Most Significant Bit) refers to the bit position that represents the largest value in a binary number. Generally, MSB is located at the leftmost end of a binary number, and LSB is located at the rightmost end of a binary number.

[0048] The examples here are for ease of understanding only and are not intended to limit the present application.

[0049] Optionally, any other data beyond the end of instruction flag may be considered invalid data.

[0050] In one embodiment, in order to reduce the number of placement instructions, the register address in the placement instruction can be expressed as the number of target registers with consecutive addresses, the offset address of the first target register, and the instruction body.

[0051] Optionally, the instruction body may store other content besides the register address, such as a register allocation instruction, the number of registers, etc. The content included in the instruction body is not limited here.

[0052] Optionally, the instruction body may also describe how to calculate the actual allocation address for each target register.

[0053] In one embodiment, the placement instruction includes an instruction type, the number of target registers with consecutive addresses, the offset address of the first target register, an instruction body, and an instruction end flag.

[0054] Here, the specific roles and principles of the instruction type, the number of target registers with consecutive addresses, the offset address of the first target register, the instruction body, and the instruction end flag are the same as those described above, so the explanation will be omitted.

[0055] Figure 4 shows the structure of a placement instruction. Instruction is the instruction type, Length is the number of consecutive target register addresses, Address is the offset address of the first target register, Configure data is the instruction itself, End of frame flag is the instruction end flag, and Invalid data is invalid data.

[0056] Optionally, if the instruction body describes a calculation method for the actual allocation address of each target register, the hardware automatic control unit 120 analyzes the allocation instruction according to the instruction type, obtains the number of target registers, the offset address of the first target register, the instruction body, and the instruction end flag, and determines the actual allocation address of each target register based on the number of target registers with consecutive addresses, the offset address of the first target register, and the calculation method in the instruction body, and allocates each target register based on the actual allocation address of each target register.

[0057] The specific process by which the hardware automatic control unit 120 determines the target register address in response to the placement command will be described using the placement command shown in FIG. 5 as an example.

[0058] As shown in Figure 5, Length=3 means that there are three target registers with consecutive addresses. Address is the offset address of the first target register. The instruction body states "Register offset base on Address," which indicates the offset amount of these three consecutive registers based on the offset address of the first target register. Therefore, the actual offset amount of the first target register is Address + Register offset base on Address. Then, the actual location address of the first target register is obtained based on the sum of the preset base address and the actual offset amount of the first target register.

[0059] Because the three target registers are consecutive, adding 1 to the actual location address of the first target register gives the actual location address of the second target register, and adding 2 to the actual location address of the first target register gives the actual location address of the third target register.

[0060] The examples here are for ease of understanding only and are not intended to limit the present application.

[0061] In a placement instruction, the length of the field for recording the number of target registers with consecutive addresses is limited, so if the number of consecutive target registers is too large, all of the fields for recording the number of target registers with consecutive addresses in the placement instruction may not be displayed.

[0062] In this case, the instruction body may further describe a method for calculating the total number of target registers with consecutive addresses. In this case, the hardware automatic control unit 120 determines the total number of target registers with consecutive addresses according to the number of target registers with consecutive addresses and the method for calculating the total number of target registers, and determines the actual allocation address of each target register based on the total number of target registers with consecutive addresses, the offset address of the first target register, and the instruction body.

[0063] Here, according to the number of target registers with consecutive addresses and the calculation method for the total number of target registers, the instruction body describes a second number (number) of target registers with consecutive addresses, and the total number of target registers with consecutive addresses is obtained by adding this second number of target registers with consecutive addresses to the number of target registers with consecutive addresses described in the allocation instruction.

[0064] The description will be given taking the arrangement command shown in FIG. 6 as an example.

[0065] Here, "Length=M" means that there are M target registers with consecutive addresses, where M is a positive integer. "Register number=M+N" means that the total number of target registers with consecutive addresses is M+N, where N is a positive integer. The other contents shown in Figure 6 are the same as those in Figure 5 above, so their explanation will be omitted.

[0066] The examples here are for ease of understanding only and are not intended to limit the present application.

[0067] Furthermore, the specific method for realizing the placement command shown in this application is not limited to the above example.

[0068] Optionally, if there are multiple non-contiguous target registers, the instruction body may include an offset for each target register.

[0069] At this time, for each target register, the actual allocation address of each target register is obtained based on the offset amount of that target register, the offset address of the first target register, and the preset base address.

[0070] Optionally, the instruction body may state the number of non-contiguous target registers.

[0071] The description will be given taking the arrangement command shown in FIG. 7 as an example.

[0072] As shown in Figure 7, Length=1 means that there is one target register with consecutive addresses. Address is the offset address of the first target register. "Register number=3" written in the instruction body means that there are three non-consecutive target registers. "Offset of the 1st register," "Offset of the 2nd register," and "Offset of the 3rd register" indicate the offset amounts based on the offset address of the first target register for each of these three non-consecutive registers.

[0073] Therefore, the actual offset of the first target register is Address + Offset of the 1st register. Then, the actual allocation address of the first target register is obtained based on the sum of the preset base address and the actual offset of the first target register.

[0074] Similarly, the actual offset of the second target register is Address + Offset of the 2nd register, and the actual offset of the third target register is Address + Offset of the 3rd register.

[0075] "Configure data" written in the command body in FIG. 7 represents configuration data.

[0076] The examples here are for ease of understanding only and are not intended to limit the present application.

[0077] In one embodiment, the hardware automation control unit 120 is connected to the interactive interface of each data path of the display processing device 110, where different data paths include different registers.

[0078] The hardware automatic control unit 120 transmits a placement start command to the data path indicating the start of placement of the target register, and further receives a placement status signal returned from the data path indicating whether all the registers included in the data path have been placed.

[0079] Here, the placement status signal may be either a reply completion signal or a placement incomplete signal.

[0080] The placement incomplete signal may include the number of the unplaced register, its storage address, and other information.

[0081] Optionally, if the display processing device 110 includes multiple data paths, the automatic hardware control unit 120 records the allocation status of the registers included in each data path, indicating whether the registers have been allocated, in accordance with the allocation status signal returned from each data path. By recording the allocation status of the registers included in each data path, the automatic hardware control unit 120 can easily determine which data path's registers to allocate in the future.

[0082] In one embodiment, if the display processing device 110 includes multiple data paths, the hardware automatic control unit 120 records the information of the destination registers in the display processing device 110 that are located.

[0083] For example, information such as the offset address of the allocated target register or the actual allocation address may be recorded. The example here is merely for ease of understanding and does not limit the present application, as long as the recorded information uniquely represents the target register.

[0084] The recorded information can be used to identify target registers in each data path that have not yet been placed, making it easier to subsequently determine which data path's registers should be placed.

[0085] In one embodiment, as shown in FIG. 8, the register allocation system 100 further includes a central processing unit 140 .

[0086] Here, the central processing unit 140 is connected to the hardware automatic control unit 120 and sends a start command to the hardware automatic control unit 120 .

[0087] The wake-up command wakes up the hardware automatic control unit 120 and instructs it to begin arranging registers.

[0088] Optionally, the hardware automatic control unit 120 transmits its internal state to the central processing unit 140 .

[0089] In response to this, the central processing unit 140 determines whether the hardware automatic control unit 120 is abnormal based on the received status of the hardware automatic control unit 120, and if the hardware automatic control unit 120 is abnormal, it sends an interrupt command to the hardware automatic control unit 120 to instruct it to stop operating.

[0090] The central processing unit 140 monitors the internal state of the hardware automatic control unit 120, and if the hardware automatic control unit 120 malfunctions, it can send an interrupt command to stop the operation of the hardware automatic control unit 120. This prevents situations such as register allocation errors caused by malfunctions in the hardware automatic control unit 120, improving the reliability of the register allocation system 100.

[0091] The central processing unit 1410 may be any type of central processing unit (CPU), and the specific type of the central processing unit 140 is not limited.

[0092] Based on the same technical idea, the present application further provides a register allocation method, which is applied to the hardware automatic control unit 120 in the above register allocation system 100. As shown in Fig. 9, the steps involved therein will be described below with reference to Fig. 9.

[0093] S100: A start command is received.

[0094] Here, the start command includes the storage address of the placement command.

[0095] Optionally, the activation command may be sent from the central processing unit to the hardware automatic control unit.

[0096] S200: Based on the start command, a placement command is obtained from the memory and analyzed.

[0097] When a start instruction is received, a placement instruction can be obtained based on the storage address included in the start instruction, and the placement instruction can be analyzed to obtain the actual placement address of the target register, and the target register can be placed based on this actual placement address.

[0098] Here, the allocation instruction and the specific implementation method for analyzing the allocation instruction to obtain the actual allocation address of the target register have been clearly explained above, so the explanation will be omitted.

[0099] S300: The target register in the display processing device is allocated based on the parsed allocation command.

[0100] The placement instruction is analyzed to obtain the actual placement address of the target register, and the target register is then placed based on this actual placement address.

[0101] Here, the specific method and logic for allocating the target register are well known to those skilled in the art, and therefore will not be described here.

[0102] The register allocation method according to the embodiments of the present application has the same implementation principles and technical effects as the above-mentioned register allocation system embodiments, and for the sake of simplicity, for anything not mentioned in the method embodiments, reference can be made to the corresponding descriptions in the above-mentioned register allocation system embodiments.

[0103] Based on a similar technical idea, the present application further provides an electronic device, which includes the above register arrangement system.

[0104] Here, the specific implementation method and principle of the register allocation system have been clearly explained above, so further explanation will be omitted.

[0105] The electronic device may be an electronic device that requires the placement of a register in a display processing device such as a computer or a server, and the specific type of electronic device is not limited.

[0106] The above description is only a preferred embodiment of the present application and does not limit the present application. Those skilled in the art may have various modifications and variations to the present application. As long as they do not deviate from the spirit and principle of the present application, any modifications, equivalent replacements, improvements, etc., are included in the protection scope of the present application.

Claims

1. a display processing device including a plurality of registers; a memory that pre-stores at least one allocation instruction for specifying a target register to be allocated in the display processing device; a hardware automatic control unit connected to a register allocation interface in the display processing device, receiving a startup command including a storage address of the allocation command, acquiring and analyzing the allocation command from the memory based on the startup command, and allocating a target register in the display processing device based on the analyzed allocation command. A register allocation system comprising:

2. the hardware automatic control unit is connected to an interactive interface of each data path of the display processing device, and different data paths include different registers; The hardware automatic control unit transmits a placement start command to the data path, which indicates the start of placement of the target register, and further receives a placement status signal, which is returned from the data path and indicates whether all registers included in the data path have been placed.

2. The register allocation system according to claim 1.

3. the display processing device includes a plurality of data paths; The hardware automatic control unit records the allocation status of the register included in each of the data paths, indicating whether the register has been allocated or not, in response to the allocation status signal returned from each of the data paths.

3. The register allocation system according to claim 2.

4. a central processing unit connected to the hardware automatic control unit and transmitting the start command to the hardware automatic control unit; 2. The register allocation system according to claim 1.

5. The hardware automatic control unit transmits its internal state to the central processing unit; The central processing unit determines whether the automatic hardware control unit is abnormal based on the received status of the automatic hardware control unit, and if the automatic hardware control unit is abnormal, sends an interrupt command to the automatic hardware control unit to instruct it to stop operating.

5. The register allocation system according to claim 4.

6. The placement instruction includes an instruction type, the number of target registers with consecutive addresses, the offset address of the first target register, an instruction body, and an instruction end flag.

6. The register allocation system according to claim 1, wherein the register allocation system is a register allocation system for allocating a plurality of registers to the register.

7. The instruction body describes a method for calculating the actual allocation address of each target register, The hardware automatic control unit analyzes the placement instruction according to the instruction type, obtains the number of target registers, the offset address of the first target register, the instruction body, and the instruction end flag, determines an actual placement address of each of the target registers based on the number of target registers with consecutive addresses, the offset address of the first target register, and the calculation method in the instruction body, and places each of the target registers based on the actual placement address of each of the target registers.

7. The register allocation system according to claim 6.

8. The instruction body further describes a method for calculating the total number of target registers whose addresses are consecutive, The hardware automatic control unit determines the total number of target registers with consecutive addresses according to the number of target registers with consecutive addresses and a calculation method for the total number of target registers, and determines an actual allocation address of each target register based on the total number of target registers with consecutive addresses, the offset address of the first target register, and the instruction body.

8. The register allocation system according to claim 7.

9. The register allocation system according to any one of claims 1 to 8 is applied to a hardware automatic control unit, receiving a wake-up command; retrieving and analyzing the placement instruction from the memory based on the activation instruction; and allocating a target register in the display processing device based on the parsed allocation instruction. A register allocation method comprising:

10. An electronic device comprising the register arrangement system according to any one of claims 1 to 8.

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