Electronic device, memory system, and power control method

Abstract

The present application discloses a host, a system, and a control method belonging to the field of storage technology. The system includes a host and a memory system, and the host configures a first interface to send an identifier to a memory controller of the memory system, the identifier indicating a peak power capability supported by the host. After receiving the identifier through a second interface, the memory controller determines a peak power management policy according to the identifier and processes I / O requests according to the determined peak power management policy. Using the present application, the memory controller of the memory system can detect the peak power capability supported by the host, and then determine a peak power management policy according to the detected peak power capability, thereby achieving the full storage performance of the memory system.

Description

[Technical Field]

[0001] The present application relates to the field of storage technology, and in particular to hosts, systems, and control methods. [Background technology]

[0002] A hardware system corresponding to some devices (e.g., a mobile phone, a tablet) may include a host and a memory system, in which the host may supply power to the memory system, and the maximum power supplied may be referred to as peak power.

[0003] To ensure normal operation of the power management unit and memory system, it is generally required that the operating power of the memory system does not exceed the peak power supported by the host.

[0004] However, the peak power supported by hosts in the market is inconsistent, and therefore memory manufacturers generally limit the operating power of their memory systems so that the memory systems they offer can fit into a larger number of hosts in the market. Summary of the Invention [Problem to be solved by the invention]

[0005] An example of the present application provides a host, a system, and a control method, in which a memory system included in the system can detect the peak power capability supported by the host, and determine an appropriate peak power management policy according to the detected peak power capability, thereby achieving the full storage performance of the memory system. The technical scheme is as follows: [Means for solving the problem]

[0006] In a first aspect, a system is provided that includes a host and a memory system, the host having a first interface, the memory system having a memory controller, the memory controller having a second interface, the host and the memory system coupled via the first interface and the second interface to perform information interaction, wherein: The host is configured to transmit an identifier indicating a peak power capability supported by the host via the first interface, and the memory controller is configured to receive the identifier via the second interface and determine a peak power management policy according to the received identifier.

[0007] In one example, the host includes a power management unit, the power management unit adapted to provide power to the memory system, and the identifier is adapted to indicate a peak power capability supported by the power management unit.

[0008] In one example, said identifier is adapted to indicate the amount of current that the power management unit can provide to the memory system according to the peak power capability supported.

[0009] In one example, the current that the power management unit can provide to the memory system according to the supported peak power capability includes at least one of Icc or Iccq.

[0010] In one example, a default peak power management policy is set in the memory controller, and the memory controller is configured to, after determining a peak power management policy, replace the default peak power management policy with the determined peak power management policy.

[0011] In one example, the peak power management policy includes parameters that control the execution of the memory system.

[0012] In one example, the parameters in the peak power management policy include at least one of a clock frequency, a degree of parallelism of the flash memory NAND, and an operation latency of an I / O request.

[0013] In one example, the memory system includes a flash universal storage UFS memory system, and the first interface and the second interface include a UFS interface.

[0014] In one example, the identifier is carried in an extension field of the UFS data packet.

[0015] In one example, the power management unit includes a power management chip PMIC.

[0016] In one example, the memory controller is further configured to send a response message via the second interface after receiving the identifier, the response message indicating that the identifier was received by the memory controller. The host is further configured to receive the response message via the first interface.

[0017] In one example, the host is further configured to send I / O requests via the first interface, and the memory controller is further configured to receive the I / O requests via the second interface and control the memory to process the I / O requests according to the determined peak power management policy.

[0018] In a second aspect, a host is provided, the host having a first interface, the host being coupled to a second interface of a memory controller in a memory system via the first interface to perform information interaction.

[0019] The host is configured to send an identifier via the first interface to a second interface of the memory controller, the identifier indicating a peak power capability supported by the host, and the host is configured to receive a response message sent by the memory controller via the first interface, the response message indicating that the identifier was received by the memory controller.

[0020] In one example, the host includes a power management unit, the power management unit adapted to provide power to the memory system, and the identifier is adapted to indicate a peak power capability supported by the power management unit.

[0021] In one example, said identifier is adapted to indicate the amount of current that the power management unit can provide to the memory system according to the peak power capability supported.

[0022] In one example, the current that the power management unit can provide to the memory system according to the supported peak power capability includes at least one of Icc or Iccq.

[0023] In one example, the host is further configured to send an I / O request via the first interface to a second interface of the memory controller.

[0024] In one example, the memory system includes a flash universal storage UFS memory system, the first interface includes a UFS interface, and the identifier is carried in an extension field of a UFS data packet.

[0025] In one example, the power management unit includes a power management chip PMIC.

[0026] In a third aspect, a memory system is provided, the memory system including a memory controller and a memory, the memory controller having a second interface, the memory controller being coupled to a first interface of a host via the second interface to perform information interaction.

[0027] The memory controller is configured to receive, via the second interface, an identifier transmitted by the host via the first interface and indicating a peak power capability supported by the host, and to determine a peak power management policy according to the identifier.

[0028] The memory controller is configured to control the memory to process I / O requests according to the determined peak power management policy.

[0029] In one example, a default peak power management policy is set in the memory controller, and the memory controller is configured to, after determining a peak power management policy, replace the default peak power management policy with the determined peak power management policy.

[0030] In one example, the peak power management policy includes parameters that control the execution of the memory system.

[0031] In one example, the parameters include at least one of a clock frequency, a degree of parallelism of the flash memory NAND, and an operation latency of an I / O request.

[0032] In one example, the memory system includes a flash universal storage UFS memory system, the second interface includes a UFS interface, and the identifier is carried in an extension field of a UFS data packet.

[0033] In one example, the memory controller is further configured to send a response message via the second interface after receiving the identifier, the response message indicating that the identifier was received by the memory controller.

[0034] In a fourth aspect, a control method for a system is provided, the system including a host and a memory system, the host including a first interface, the memory system including a memory controller, the memory controller including a second interface, the host and the memory system coupled via the first interface and performing information interaction, the control method including transmitting, by the host, an identifier via the first interface, the identifier indicating a peak power capability supported by the host, receiving, by the memory controller, the identifier via the second interface, and determining a peak power management policy consistent with the peak power capability according to the identifier.

[0035] In one example, the host includes a power management unit, the power management unit adapted to provide power to the memory system, and the identifier adapted to indicate a peak power capability supported by the power management unit.

[0036] In one example, the identifier is adapted to indicate the amount of current that the power management unit can provide to the memory system according to the supported peak power capability.

[0037] In one example, the current that the power management unit can provide to the memory system according to the supported peak power capability includes at least one of Icc or Iccq.

[0038] In one example, a default peak power management policy is set in the memory controller. After determining the peak power management policy, the control method further includes replacing the default peak power management policy with the determined peak power management policy by the memory controller.

[0039] In one example, the peak power management policy includes parameters that control the execution of the memory system.

[0040] In one example, the parameters include at least one of a clock frequency, a degree of parallelism of the flash memory NAND, and an operation latency of an I / O request.

[0041] In one example, the memory system includes a flash universal storage UFS memory system, and the first interface and the second interface include a UFS interface.

[0042] In one example, the identifier is carried in an extension field of the UFS data packet.

[0043] In one example, the power management unit includes a power management chip PMIC.

[0044] In one example, the control method further includes transmitting, by the memory controller, a response message via the second interface after receiving the identifier, the response message indicating that the identifier was received by the memory controller. The host receives the response message via the first interface.

[0045] In one example, the control method further includes transmitting, by the host, an I / O request via the first interface, and a memory controller receiving the I / O request via the second interface and controlling the memory to process the I / O request according to the determined peak power management policy.

[0046] The beneficial effects brought about by the technical solutions provided by the embodiments of the present application include: In one example of the present application, after information interaction is established between the host and the memory controller of the memory system via the interface, the host may send an identifier corresponding to the supported peak power capability to the memory controller. The memory controller may determine a peak power management policy that matches the peak power capability of the host according to the received identifier, and then process I / O requests according to the determined peak power management policy. Therefore, the memory controller can adjust the peak power management policy according to the peak power capability of the host without pre-limiting the storage performance of the memory system, thereby utilizing the full performance of the memory system.

[0047] In order to more clearly show the technical solutions in the embodiments of the present application, the accompanying drawings that need to be used in the description of the embodiments are briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these accompanying drawings without any creative efforts. [Brief explanation of the drawings]

[0048] [Figure 1] 1 is a schematic diagram of an exemplary system provided by an example of the present application; [Figure 2] 1 is a diagram of an exemplary memory card provided by an example of the present application. [Figure 3] 1 is a schematic diagram of an exemplary solid-state drive provided by an example of the present application. [Figure 4] 1 is a schematic diagram of an exemplary system provided by an example of the present application; [Figure 5] 1 is a flowchart of a control method for an exemplary system provided by one embodiment of the present application. [Figure 6] 1 is a flowchart of a control method for an exemplary system provided by one embodiment of the present application. [Figure 7] 1 is a schematic structural diagram of an exemplary memory provided by an example of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0049] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application are described in more detail below in conjunction with the accompanying drawings.

[0050] FIG. 1 shows a block diagram of an example system 100 with a memory system according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. As shown in FIG. 1 , the system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to transmit or receive data from the memory 104.

[0051] The memory 104 may be any memory device disclosed in this disclosure. In one example, the memory 104 is a NAND flash memory device, such as a three-dimensional (3D) NAND flash memory device.

[0052] In some implementations, memory controller 106 is coupled to memory 104 and host 108 and configured to control memory 104. Memory controller 106 may manage data stored in memory 104 and communicate with host 108. In some implementations, memory controller 106 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, memory controller 106 is designed to operate in a high-duty-cycle environment, such as a SSD or an embedded multimedia card (eMMC), which are used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays. Memory controller 106 may be configured to control operations of memory 104, such as reading, erasing, and programming. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, memory controller 106 is also configured to process error correction codes (ECC) associated with data read from and written to memory 104. Memory controller 106 may also perform any other suitable functions, such as formatting memory 104. Memory controller 106 may communicate with external devices (e.g., host 108) according to a particular communication protocol.For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0053] The memory controller 106 and one or more memories 104 may be incorporated into various types of storage devices, such as in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged in different types of end electronic products. In one example shown in FIG. 2 , the memory controller 106 and the single memory device 104 may be incorporated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, etc. The memory card 202 may further include a memory card connector 24 that couples the memory card 202 to a host (e.g., the host 108 of FIG. 1 ). In another example shown in FIG. 3 , the memory controller 106 and multiple memory devices may be incorporated into an SSD 306. SSD 306 may further include an SSD connector 308 that couples SSD 306 to a host (e.g., host 108 in FIG. 1 ). In some implementations, at least one of the storage capacity and operating speed of SSD 306 is greater than at least one of the storage capacity and operating speed of memory card 202.

[0054] A host 108 in the system 100 may supply power to the memory system 102. In the example shown in FIG. 4, the host 108 may include a power management unit (PMU) 402. The PMU 402 may supply power to the memory 104 and the memory controller 106. The voltage and current provided by the PMU 402 to the memory 104 are Vcc and Icc, respectively, and the voltage and current provided by the PMU 402 to the memory controller 106 are Vccq and Iccq, respectively. The maximum power provided by the PMU 402 to the memory 104 may be referred to as peak power. During operation, the memory system 102 needs to ensure that the power it requires does not exceed the peak power supported by the host (or PMU).

[0055] In some implementations, the peak power supported by hosts 108 provided by different host manufacturers is inconsistent, and therefore, to improve the adaptability of memory system 102, memory manufacturers generally limit the operating power of memory system 102 to less than the peak power supported by most hosts 108 in the market. In one example, peak power may be represented by a corresponding peak current, and peak powers supported by hosts 108 in the market may include 800 mA, 1 A, and 1.2 A, and memory manufacturers may limit the operating power of memory system 102 to less than 800 mA.

[0056] The operating power of the memory system 102 is directly related to the storage performance of the memory system 102, and limiting the operating power can also be achieved by limiting the storage performance of the memory system 102, for example, by limiting the read and write speeds of the memory system 102, thereby enforcing the limiting of the operating power of the memory system 102. Thus, although the adaptability of the memory system 102 is improved, if the host 108 in the system 100 can support a higher peak power, the memory system 102 cannot reach its full storage performance.

[0057] An example of the present application provides a control method for a system, which may be a system 100 shown in Fig. 1, including a host and a memory system. In this system, the memory system can detect the peak power of the host, and then adjust the peak power management policy according to the detected peak power, so that the full storage performance of the memory system can be achieved.

[0058] 5 and 6 are flowcharts of a control method of a system provided by an example of the present application. As shown in FIG. 5 or 6, in the system provided by an example of the present application, the host has a first interface, the memory controller of the memory system has a second interface, and the host and the memory system are coupled via the first interface and the second interface to perform information interaction.

[0059] Referring to FIG. 5, the control method of the system provided by an example of the present application is as follows: Step 501. Transmitting, by a host, an identifier that indicates a peak power capability supported by the host via a first interface. Includes:

[0060] In one embodiment, an identifier adapted to indicate a supported peak power capability may be stored in a host, and the host may transmit the identifier via a configured first interface to a second interface of the memory controller.

[0061] Step 502. Receive, by the memory controller, an identifier via a second interface.

[0062] Step 503. Determine, by the memory controller, a peak power management policy that matches the peak power capability according to the identifier.

[0063] Here, the peak power management policy can be used to control the operating power of the memory system. In one example, the peak power management policy is to limit the write rate of the memory to achieve the effect of controlling the operating power of the memory system.

[0064] In one embodiment, after receiving the identifier sent by the host, the memory controller, via a second interface configured in the memory controller, can determine a peak power management policy corresponding to the received identifier from the correspondence between the stored identifiers and peak power management policies, and then use the determined peak power management policy as the peak power management policy to be adopted during operation of the memory system.

[0065] In the above correspondence relationship, the peak power management policy corresponding to the identifier matches the peak power capability indicated by the identifier. For example, the identifier "1 hour" indicates that the peak power supported by the host is 650 mA, and in the process of the memory system applying the peak power management policy corresponding to "1 hour," the peak current generated may be less than 650 mA and close to (or equal to) 650 mA. The identifier "2 hours" indicates that the peak power supported by the host is 800 mA, and in the process of the memory system applying the peak power management policy corresponding to "2 hours," the peak current generated may be less than 800 mA and close to (or equal to) 800 mA.

[0066] In a system control method provided in an example of the present application, a host can transmit a peak power capability supported by the host to a memory system, and a memory controller in the memory system can dynamically match and apply an appropriate peak power management policy according to the peak power capability supported by the host. The example of the present application avoids setting a peak power management policy that causes the memory system to have low storage performance in order to match with most hosts, and allows the memory system to reach full storage performance when operating with various hosts.

[0067] As shown in FIG. 6, a host in a system may send an initialization command to a second interface of a memory controller via a first interface after power-on. After receiving the initialization command, the memory controller may perform an initialization operation and send an RSP (response message) to the host via the second interface. After receiving the RSP of the memory system via the first interface for the first time, the host may send an identifier via the first interface that indicates to the memory controller a peak power capability supported by the host. After receiving the identifier that indicates a peak power capability supported by the host via the second interface, the memory controller may determine and apply a peak power management policy corresponding to the received identifier according to the stored correspondence. After receiving the identifier, the memory controller may again send an RSP to the host via the second interface, the second RSP indicating that the identifier sent by the host has been received by the memory controller.

[0068] Continuing to refer to FIG. 6 , after the host receives the RSP sent by the memory controller via the first interface for the second time, when there is a pending I / O (Input / Output) request in the host, the host can send the I / O request to the memory controller via the first interface. After receiving the I / O request via the second interface, the memory controller can control the memory to process the I / O request according to the determined peak power management policy. Therefore, the memory system can process the I / O request according to the peak power management policy that matches the peak power capability of the host, thereby allowing the memory system to reach full storage performance without exceeding the peak power of the host. Furthermore, because the memory system can flexibly adjust the matching peak power management policy according to the peak power of the host, the memory system provided by one embodiment of the present application has higher adaptability than some embodiments.

[0069] In the system shown in FIG. 4 , the host may supply power to the memory system through a PMU, which may be a control chip integrated into the host controller of the host or a control chip independent of the host controller. In one example, the PMU may include a power management IC (PMIC) independent of the host controller. Therefore, the identifier used to indicate the peak power capability supported by the host in the above example may be used to indicate the peak power capability supported by the PMU. Because the operating voltage provided by the PMU to the memory controller and memory is relatively stable during operation of the memory system, the magnitude of the current provided by the PMU to the memory controller and memory can reflect the peak power capability of the PMU. Therefore, the identifier described above indicating the peak power capability of the PMU may also be used to indicate the magnitude of the current the PMU can provide to the memory system according to the supported peak power capability.

[0070] In one example, the aforementioned peak power management policy includes at least one parameter that controls the operation of the memory system. The at least one parameter can be used to control the write rate of the memory in the memory system and to control the operating power of the memory system, so that the operating power of the memory system is less than or equal to the peak power supported by the host. Table 1 shows the relationship between the peak power capability supported by the host and the write rate of the memory, where the memory cells in the memory may be triple-level (TLC).

[0071] [Table 1]

[0072] As shown in Table 1, if the peak power capability supported by the host is 800mA, the memory write speed can be controlled at 650MB / s through the parameters of the peak power management policy so that the operating power of the memory system does not exceed the peak power supported by the host.

[0073] In one example, at least one parameter included in the peak power management policy may include a clock frequency of the memory system, a degree of parallelism of the flash memory NAND, and an operational latency of an I / O request. Here, the clock frequency refers to the clock frequency used by the memory system during execution. In one example, the higher the clock frequency, the higher the write rate and the corresponding operating power consumed by the memory system. The parallelism of the NAND refers to the number of NAND cells performing write operations simultaneously. In one example, the higher the parallelism, the higher the write rate and the corresponding operating power consumed by the memory system. The operational latency of the I / O request refers to the time interval between adjacent I / O requests processed by the memory controller. In one example, the shorter the operational latency, the higher the write rate and the corresponding operating power consumed by the memory system.

[0074] In the correspondence between the identifiers and the peak power management policies described above, the values ​​of the parameters included in the peak power management policies corresponding to each identifier may be set by an engineer. For example, a write rate that meets the limit required by the peak power capability may be used as an input to a configuration algorithm, and the configuration algorithm outputs the values ​​of each of the aforementioned parameters. Various processes for the configuration algorithm may be used, and will not be described in detail in the examples of this application.

[0075] In one embodiment, after receiving an identifier transmitted by a host and indicating a peak power capability, the memory controller can determine a peak power management policy corresponding to the received identifier in a pre-stored correspondence, and then set the value of a parameter for operating the memory system to the value of a parameter included in the peak power management policy. Thus, the write rate of the memory can be adjusted according to the peak power capability supported by the host, so that the full storage performance of the memory can be reached, and the operating power of the memory system does not exceed the peak power supported by the host.

[0076] Since the corresponding power consumption is relatively large when the memory performs a write operation, the control of the operating power of the memory system can be implemented by controlling the write rate. However, the examples of the present application are not limited to achieving the control of the operating power of the memory system only by controlling the write rate. Similarly, the examples of the present application can also adjust the above parameters to control the erase rate and read rate of the memory, thereby implementing further control of the operating power of the memory system.

[0077] In one example, the memory system provided by the present application may include a UFS memory system. Communication between the host and the memory system may follow the UFS protocol. Thus, the first interface of the host and the second interface of the memory controller may both include a UFS interface.

[0078] In one example of the present application, the memory in the UFS memory system may be referred to as a UFS memory, and the memory controller in the UFS memory system may be referred to as a UFS memory controller. The PMU may supply power to the UFS memory and the UFS memory controller, respectively. The voltage and current provided by the PMU to the UFS memory are Vcc and Icc, respectively, and the voltage and current provided by the PMU to the UFS memory controller are Vccq and Iccq, respectively. The Vcc and Vccq provided by the PMU to the UFS memory system are relatively stable. Therefore, the identifier used for the host's peak power capability may represent the magnitude of Icc and Iccq, respectively, provided by the host to the UFS memory system having the peak power capability.

[0079] Here, when the host transmits an identifier indicating the magnitude of Icc and Iccq to the UFS memory controller via the UFS interface, the identifier may be carried within the UFS data packet. The identifier may further be added to the extension field of the UFS data packet. Table 2 shows additional information about Icc and Iccq in the extension field of the UFS data packet.

[0080] [Table 2]

[0081] Here, "size" represents the number of bits of the identifier that indicate the magnitude of Iccq or Icc that are occupied in the extension field. "name" represents the name of the bits of the identifier that are occupied in the extension field. "value" represents the numeric type of the identifier, and the above identifiers may be hexadecimal values ​​as shown in Table 2. "user cont" represents that the extension field is pre-configured by technical staff. "description" represents the peak power capability of the host that is indicated by the identifier that corresponds to Iccq or Icc when it takes on different values.

[0082] In one example, when sending a UFS data packet to a UFS memory controller, the host can carry only an identifier corresponding to Icc. Accordingly, a correspondence relationship between different Icc identifiers and peak power management policies may be stored in the correspondence relationship of the UFS memory controller. In another example, when sending a UFS data packet to a UFS memory controller, the host can carry only identifiers corresponding to Icc and Iccq. Accordingly, a correspondence relationship between two different Icc and Iccq identifiers and peak power management policies may be stored in the correspondence relationship of the UFS memory controller.

[0083] In one example, a default peak power management policy is set in the memory controller. The default peak power management policy can control the operating power of the memory system to meet the peak power capabilities supported by most hosts on the market. For example, the default peak power management policy can control the operating power of the memory system to meet the peak power capabilities supported by more than a preset number of types of hosts.

[0084] Thus, in one aspect, even if the host does not have the capability to send an identifier to the memory controller that is intended to indicate its peak power capability, the memory controller can still control the operation of the memory system using a default peak power management policy. In another aspect, even if the memory controller does not have the capability to find a matching peak power management policy according to the identifier sent by the host, the act of sending the identifier to the memory controller by the host does not affect the normal operation of the memory controller.

[0085] An example of the present application also provides a host, which may include each of the hosts shown in Figures 1, 4 to 6 above. The host has a first interface, and the host is coupled to a second interface of a memory controller in a memory system via the first interface to perform information interaction.

[0086] The host is configured to send an identifier via the first interface to a second interface of the memory controller, the identifier indicating a peak power capability supported by the host, and the host is configured to receive a response message sent by the memory controller via the first interface, the response message indicating that the identifier was received by the memory controller.

[0087] In one example, the host includes a power management unit, the power management unit adapted to provide power to the memory system, and the identifier adapted to indicate a peak power capability supported by the power management unit.

[0088] In one example, the identifier is adapted to indicate the amount of current that the power management unit can provide to the memory system according to the supported peak power capability.

[0089] In one example, the current that the power management unit can provide to the memory system according to the supported peak power capability includes at least one of Icc or Iccq.

[0090] In one example, the host is further configured to send an I / O request via the first interface to a second interface of the memory controller.

[0091] In one example, the memory system includes a UFS memory system, the first interface includes a UFS interface, and the identifier is carried in an extension field of a UFS data packet.

[0092] In one example, the power management unit includes a power management chip PMIC.

[0093] The host provided by the example of the present application can perform the operations performed by the host in the control method provided by the example of the present application, the details of which can be referred to the contents of the above example and will not be repeated here. The host provided by the example of the present application can actively transmit the peak power capability supported by the host to the memory system, so that the memory system can adjust the peak power management policy of the memory system according to the peak power capability supported by the host to reach the full storage performance of the memory system.

[0094] An example of the present application also provides a memory system, which can include each of the memory systems shown in Figures 1 to 4. The memory system includes a memory controller and a memory, the memory controller having a second interface, and the memory controller is coupled to the first interface of a host via the second interface to perform information interaction.

[0095] The memory controller is configured to receive, via the second interface, an identifier transmitted by the host via the first interface and indicating a peak power capability supported by the host, and to determine a peak power management policy according to the identifier.

[0096] The memory controller is configured to control the memory to process I / O requests according to the determined peak power management policy.

[0097] In one example, a default peak power management policy is set in the memory controller.

[0098] The memory controller is configured, after determining the peak power management policy, to replace the default peak power management policy with the determined peak power management policy.

[0099] In one example, the peak power management policy includes parameters that control the execution of the memory system.

[0100] In one example, the parameters include at least one of a clock frequency, a degree of parallelism of the flash memory NAND, and an operation latency of an I / O request.

[0101] In one example, the memory system includes a flash universal storage UFS memory system, the second interface includes a UFS interface, and the identifier is carried in an extension field of a UFS data packet.

[0102] In one example, the memory controller is further configured to send a response message via the second interface after receiving the identifier, the response message indicating that the identifier was received by the memory controller.

[0103] The memory system provided by the example of the present application can execute the method operations performed by the memory system in the control method provided by the example of the present application, the details of which can be referred to the contents of the above example and will not be repeated here. The memory system provided by the example of the present application can receive an identifier indicating the peak power capability of the host, and then determine and apply a peak power management policy of the memory system based on the identifier, thereby achieving the full storage performance of the memory system.

[0104] An example of the present application also provides a system, which may be the system 100 shown in FIG. 1 above, wherein the system includes a host and a memory system, wherein the host has a first interface, the memory system has a memory controller, and the memory controller has a second interface, and the host and the memory system are coupled via the first interface and the second interface to perform information interaction, where: The host is configured to transmit an identifier over the first interface that is adapted to indicate a peak power capability supported by the host.

[0105] The memory controller is configured to receive the identifier via the second interface and determine a peak power management policy according to the identifier.

[0106] In one example, the host includes a power management unit, the power management unit adapted to provide power to the memory system, and the identifier adapted to indicate a peak power capability supported by the power management unit.

[0107] In one example, the identifier is adapted to indicate the amount of current that the power management unit can provide to the memory system according to the supported peak power capability.

[0108] In one example, the current that the power management unit can provide to the memory system according to the supported peak power capability includes at least one of Icc or Iccq.

[0109] In one example, a default peak power management policy is set in the memory controller, and the memory controller is configured to, after determining a peak power management policy, replace the default peak power management policy with the determined peak power management policy.

[0110] In one example, the peak power management policy includes parameters that control the execution of the memory system.

[0111] In one example, the parameters include at least one of a clock frequency, a degree of parallelism of the flash memory NAND, and an operation latency of an I / O request.

[0112] In one example, the memory system includes a flash universal storage UFS memory system, and the first interface and the second interface include a UFS interface.

[0113] In one example, the identifier is carried in an extension field of the UFS data packet.

[0114] In one example, the power management unit includes a power management chip PMIC.

[0115] In one example, the memory controller is further configured to send a response message via the second interface after receiving the identifier, the response message indicating that the identifier was received by the memory controller. The host is further configured to receive the response message via the first interface.

[0116] In one example, the host is further configured to send I / O requests via the first interface, and the memory controller is further configured to receive the I / O requests via the second interface and control the memory to process the I / O requests according to the determined peak power management policy.

[0117] A system provided by an example of the present application, including a host and a memory system, can implement the system control method in the above example, the details of which can be referred to in the above example and will not be repeated here. In the system provided by an example of the present application, the host can send an identifier corresponding to the supported peak power capability to the memory controller. The memory controller can determine a peak power management policy that matches the peak power capability of the host according to the received identifier, and then process I / O requests according to the determined peak power management policy. Therefore, the memory controller can adjust the peak power management policy according to the peak power capability of the host without pre-limiting the storage performance of the memory system, thereby utilizing the full performance of the memory system.

[0118] 7 shows a schematic circuit diagram of an example memory device 700 including peripheral circuits according to some aspects of the present disclosure. Memory 700 may be a memory included in the example memory systems described above, such as the memory shown in FIGS. 1-5.

[0119] The memory 700 may include a memory cell array device 701 and peripheral circuits 702 coupled to the memory cell array device 701. The memory cell array device 701 may be a NAND flash memory cell array in which memory cells 706 are arranged in an array of NAND memory strings 708, with each NAND memory string 708 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 708 includes multiple memory cells 706 coupled in series and stacked vertically. Each memory cell 706 can hold a continuous analog value, e.g., voltage or charge, depending on the number of electrons trapped within the region of the memory cell 706. Each memory cell 706 may be a "floating gate" type memory cell including a floating gate transistor or a "charge trap" type memory cell including a charge trap transistor.

[0120] In some embodiments, each memory cell 706 is a single-level cell (SLC), which has two possible memory states and can therefore store one bit of data. For example, a first memory state of "0" may correspond to a first voltage range, and a second memory state of "1" may correspond to a second voltage range. In some embodiments, each memory cell 706 is a multi-level cell (MLC), which can store more than a single bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed from an erased state to assume one of three possible memory states by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value being available for the erased state.

[0121] 7, each NAND memory string 708 may include a source select gate (SSG) 710 at its source terminal and a drain select gate (DSG) 712 at its drain terminal. The SSG 710 and DSG 712 may be configured to activate a selected NAND memory string 708 (column of the array) during read and program operations. In some embodiments, the sources of NAND memory strings 708 in the same block 704 are coupled via the same source line (SL) 714 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 708 in the same block 704 have an array common source (ACS). According to some embodiments, the DSG 712 of each NAND memory string 708 is coupled to a corresponding bit line 716 from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 708 is configured to be selected or deselected by at least one of applying a select voltage (e.g., above the threshold voltage of the transistor comprising the DSG 712) or a deselect voltage (e.g., 0V) to the corresponding DSG 712 via one or more DSG lines 713, or applying a select voltage (e.g., above the threshold voltage of the transistor comprising the SSG 710) or a deselect voltage (e.g., 0V) to the corresponding SSG 710 via one or more SSG lines 715.

[0122] 7 , the memory cell array device 701 may include multiple blocks 704, each including multiple NAND memory strings 708, and each of the multiple blocks 704 may have a common source line 714 (e.g., coupled to ground). In some implementations, each block 704 is a basic data unit for an erase operation, i.e., all memory cells 706 in the same block 704 are erased simultaneously. To erase memory cells 706 in a selected block 704 a, the source lines 714 coupled to the selected block 704 a and unselected blocks 704 b in the same plane as the selected block 704 a may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20 V or greater)). It should be understood that in some examples, the erase operation may be performed at a half-block level, a quarter-block level, or a level having any suitable number of blocks or any suitable percentage of blocks. The memory cells 706 of adjacent NAND memory strings 708 can be coupled via word lines 718 that select which row of memory cells 706 is affected by read and program operations. In some implementations, each word line 718 is coupled to multiple memory cells 706. Each word line 718 can include multiple control gates (gate electrodes) to each memory cell 706 in a corresponding page 720, and gate lines that couple the control gates.

[0123] In one example of the present application, a peak power management policy may be set according to the specific type of memory cells contained in the memory to match the peak power capabilities supported by different hosts so that the power of the memory during operation does not exceed the peak power of the power supply host.

[0124] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. Unless expressly limited otherwise, the term "at least one" refers to one or more, and the term "plurality" refers to two or more.

[0125] The above description is only an illustrative example of the present application, and is not intended to limit the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A host having a first interface, configured to transmit, via the first interface, an identifier adapted to indicate a peak power capability supported by the host; With the host, A memory system including a memory controller having a second interface, wherein the host and the memory system are coupled via the first interface and the second interface to perform information interaction, and the memory controller: receiving the identifier via the second interface; determining a peak power management policy according to the identifier a memory system configured as follows: Including, the system.

2. 2. The system of claim 1, wherein the host includes a power management unit adapted to provide power to the memory system, and the identifier is adapted to indicate the peak power capability supported by the power management unit.

3. 3. The system of claim 2, wherein the identifier indicates a magnitude of current that the power management unit is capable of providing to the memory system according to the supported peak power capability.

4. 4. The system of claim 3, wherein the current that the power management unit can provide to the memory system according to the supported peak power capability comprises at least one of Icc or Iccq.

5. A default peak power management policy is set for the memory controller; The system of claim 1 , wherein the memory controller is configured, after determining the peak power management policy, to replace the default peak power management policy with the determined peak power management policy.

6. The system of claim 1 , wherein the peak power management policy includes one or more parameters that control the performance of the memory system.

7. 7. The system of claim 6, wherein the one or more parameters include at least one of a clock frequency, a degree of parallelism of a flash memory NAND, and an operation latency of an I / O request.

8. The system of claim 1 , wherein the memory system comprises a Flash Universal Storage (UFS) memory system, and wherein the first interface and the second interface each comprise a UFS interface.

9. 9. The system of claim 8, wherein the identifier is carried in an extension field of a UFS data packet.

10. The system according to claim 2 , wherein the power management unit comprises a power management chip PMIC.

11. the memory controller is further configured to send a response message via the second interface after receiving the identifier, the response message indicating that the identifier was received by the memory controller; The system of claim 1 , wherein the host is further configured to receive the response message via the first interface.

12. the host is further configured to send an I / O request via the first interface; The memory controller: receiving the I / O request via the second interface; Controlling the memory to process the I / O requests in accordance with the determined peak power management policy. The system of claim 1 , further configured to:

13. a host having a first interface, coupled to a second interface of a memory controller in a memory system via the first interface to perform information interaction; configured to transmit an identifier via the first interface to the second interface of the memory controller, the identifier indicating a peak power capability supported by the host; configured to receive a response message transmitted by the memory controller via the first interface, the response message indicating that the identifier was received by the memory controller. host.

14. 14. The host of claim 13, comprising a power management unit adapted to provide power to the memory system, the identifier adapted to indicate the peak power capability supported by the power management unit.

15. 15. The host of claim 14, wherein the identifier indicates a magnitude of current the power management unit is capable of providing to the memory system according to the supported peak power capability.

16. 16. The host of claim 15, wherein the current that the power management unit can provide to the memory system in accordance with the supported peak power capability includes at least one of Icc or Iccq.

17. 17. The host of claim 13, wherein the host is further configured to send I / O requests to the second interface of the memory controller via the first interface.

18. 17. The host of claim 13, wherein the memory system comprises a Flash Universal Storage (UFS) memory system, the first interface comprises a UFS interface, and the identifier is carried in an extension field of a UFS data packet.

19. The host according to claim 14 , wherein the power management unit includes a power management chip PMIC.

20. Memory and a memory controller having a second interface, coupled to the first interface of the host via the second interface, and performing information interaction; Including, The memory controller: receiving, via the second interface, an identifier transmitted by the host via the first interface and adapted to indicate a peak power capability supported by the host; determining a peak power management policy according to the identifier; Controlling the memory to process I / O requests in accordance with the determined peak power management policy. The memory system is configured as follows.

21. A default peak power management policy is set for the memory controller; 21. The memory system of claim 20, wherein the memory controller is configured, after determining the peak power management policy, to replace the default peak power management policy with the determined peak power management policy.

22. 22. The memory system of claim 20 or 21, wherein the peak power management policy comprises one or more parameters that control the performance of the memory system.

23. 23. The memory system of claim 22, wherein the one or more parameters include at least one of a clock frequency, a degree of parallelism of a flash memory NAND, and an operational latency of an I / O request.

24. 22. The memory system of claim 20 or 21, wherein the memory system comprises a Flash Universal Storage UFS memory system, the second interface comprises a UFS interface, and the identifier is carried in an extension field of a UFS data packet.

25. 22. The memory system of claim 20 or 21, wherein the memory controller is further configured to send a response message via the second interface after receiving the identifier, the response message indicating that the identifier was received by the memory controller.

26. 1. A control method for a system, the system including a host having a first interface and a memory system including a memory controller having a second interface, the host and the memory system being coupled via the first interface and the second interface to perform information interaction, the method comprising: transmitting, by the host, over the first interface, an identifier adapted to indicate a peak power capability supported by the host; receiving, by the memory controller, the identifier via the second interface; determining, by the memory controller, a peak power management policy consistent with the peak power capability according to the identifier; A method comprising:

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